* [RFC PATCH 0/2] ARM: update cpuinfo to print CPU model name
From: Rob Herring @ 2013-01-29 16:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359474865-15408-1-git-send-email-ruslan.bilovol@ti.com>
On 01/29/2013 09:54 AM, Ruslan Bilovol wrote:
> Hi,
>
> The following patches update cpuinfo to print CPU
> model name for ARM. First patch exactly makes needed
> changes for ARM architecture.
> Second patch adds this ability to OMAP4 SoCs.
>
> This adds a common approach to show SoC name.
>
> Looks like there were few attempts to do similar
> changes to cpuinfo without any luck.
Care to point out how your solution is different from those or addresses
the issues with them.
Assuming we want to do this, I think this information should come from
DeviceTree. OMAP may have this in a register, but others don't.
Rob
>
> So - comments are welcome
>
> Ruslan Bilovol (2):
> ARM: kernel: update cpuinfo to print CPU model name
> ARM: OMAP4: setup CPU model name during ID initialisation
>
> arch/arm/include/asm/setup.h | 1 +
> arch/arm/kernel/setup.c | 10 ++++++++++
> arch/arm/mach-omap2/id.c | 18 ++++++++++++++++--
> 3 files changed, 27 insertions(+), 2 deletions(-)
>
^ permalink raw reply
* [BUG] i.MX25: soft lockups/freezes while getnstimeofday
From: Steffen Trumtrar @ 2013-01-29 16:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi!
I have a problem with an imx25 on 3.7.2 kernel.
* Scenario
The scenario is as follows:
Under normal circumstances (i.e. system is running some daemons, but apart from
that idles most of the time), soft lockups happen after several hours. When the
watchdog_timer_fn has printed its stack dump, the system hangs for about 6min
and then continues to run as nothing ever happend.
I am able to force the lockup when I run the following little code snippet:
while(1)
syscall(SYS_clock_gettime, CLOCK_REALTIME, &tp);
With this running on the system, the lockup happens after 10-30mins:
[ 1175.247095] BUG: soft lockup - CPU#0 stuck for 22s! [time-test:268]
[ 1175.253421] Modules linked in:
[ 1175.256537] irq event stamp: 555315876
[ 1175.260318] hardirqs last enabled at (555315875): [<c000df28>] __irq_svc+0x48/0x54
[ 1175.268073] hardirqs last disabled at (555315876): [<c000df14>] __irq_svc+0x34/0x54
[ 1175.275802] softirqs last enabled at (555315874): [<c00243dc>] __do_softirq+0x210/0x2a0
[ 1175.283977] softirqs last disabled at (555315867): [<c0024854>] irq_exit+0x64/0xc8
[ 1175.291610]
[ 1175.293134] Pid: 268, comm: time-test
[ 1175.297788] CPU: 0 Not tainted (3.7.2-Katara-00060-g49acf87-dirty #25)
[ 1175.304707] PC is at getnstimeofday+0xc4/0xf0
[ 1175.309104] LR is at getnstimeofday+0x98/0xf0
[ 1175.313503] pc : [<c0052b4c>] lr : [<c0052b20>] psr: 80000013
[ 1175.313503] sp : d104bf38 ip : 00000005 fp : d104bf74
[ 1175.325022] r10: 43ecbb48 r9 : d104bf88 r8 : d1811020
[ 1175.330280] r7 : ffffffff r6 : c4653600 r5 : f02f5ec5 r4 : ce61ad4b
[ 1175.336840] r3 : fffffffb r2 : 00001243 r1 : 00000000 r0 : 3b9ac9ff
[ 1175.343402] Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
[ 1175.350572] Control: 0005317f Table: 912ec000 DAC: 00000015
[ 1175.356408] [<c00130dc>] (unwind_backtrace+0x0/0xec) from [<c0391514>] (dump_stack+0x20/0x24)
[ 1175.365020] [<c0391514>] (dump_stack+0x20/0x24) from [<c000f2f0>] (show_regs+0x4c/0x58)
[ 1175.373115] [<c000f2f0>] (show_regs+0x4c/0x58) from [<c0071c18>] (watchdog_timer_fn+0x108/0x15c)
[ 1175.381991] [<c0071c18>] (watchdog_timer_fn+0x108/0x15c) from [<c0043470>] (__run_hrtimer+0x11c/0x250)
[ 1175.391378] [<c0043470>] (__run_hrtimer+0x11c/0x250) from [<c0043d40>] (hrtimer_interrupt+0x104/0x268)
[ 1175.400775] [<c0043d40>] (hrtimer_interrupt+0x104/0x268) from [<c00196a0>] (mxc_timer_interrupt+0x34/0x44)
[ 1175.410515] [<c00196a0>] (mxc_timer_interrupt+0x34/0x44) from [<c00726a0>] (handle_irq_event_percpu+0x88/0x274)
[ 1175.420677] [<c00726a0>] (handle_irq_event_percpu+0x88/0x274) from [<c00728d8>] (handle_irq_event+0x4c/0x6c)
[ 1175.430583] [<c00728d8>] (handle_irq_event+0x4c/0x6c) from [<c0074fc8>] (handle_level_irq+0xe0/0xf8)
[ 1175.439793] [<c0074fc8>] (handle_level_irq+0xe0/0xf8) from [<c0071ec4>] (generic_handle_irq+0x30/0x40)
[ 1175.449179] [<c0071ec4>] (generic_handle_irq+0x30/0x40) from [<c000ecec>] (handle_IRQ+0x70/0x94)
[ 1175.458036] [<c000ecec>] (handle_IRQ+0x70/0x94) from [<c0008740>] (avic_handle_irq+0x44/0x50)
[ 1175.466630] [<c0008740>] (avic_handle_irq+0x44/0x50) from [<c000df24>] (__irq_svc+0x44/0x54)
[ 1175.475104] Exception stack(0xd104bef0 to 0xd104bf38)
[ 1175.480202] bee0: 3b9ac9ff 00000000 00001243 fffffffb
[ 1175.488436] bf00: ce61ad4b f02f5ec5 c4653600 ffffffff d1811020 d104bf88 43ecbb48 d104bf74
[ 1175.496660] bf20: 00000005 d104bf38 c0052b20 c0052b4c 80000013 ffffffff
[ 1175.503346] [<c000df24>] (__irq_svc+0x44/0x54) from [<c0052b4c>] (getnstimeofday+0xc4/0xf0)
[ 1175.511785] [<c0052b4c>] (getnstimeofday+0xc4/0xf0) from [<c003d1b0>] (posix_clock_realtime_get+0x1c/0x24)
[ 1175.521524] [<c003d1b0>] (posix_clock_realtime_get+0x1c/0x24) from [<c003e5a8>] (sys_clock_gettime+0x3c/0x9c)
[ 1175.531520] [<c003e5a8>] (sys_clock_gettime+0x3c/0x9c) from [<c000e300>] (ret_fast_syscall+0x0/0x38)
The board itself supposedly worked up until v3.4.
The mxc-timer is set up to use ipg_clk_highfreq with a per5_div set to 2,
therefore it is clocked with 120MHz. I tried to set the per5_div to 4 to have
a 60MHz clock, but this didn't change anything.
On the other hand, I tried parenting the ipg_clk to the per5_clk to get a
66MHz clock. This seems to be working fine, but I only have it running for 4h now.
* Suspects
The current suspect is arch/arm/plat-mxc/time.c or the GPT respectively.
Is it okay to clock the gpt via the ipg_clk_highfreq? It is a valid clksrc according
to the datasheet, but that doesn't mean that the timer is stable then ;-)
It seems, that it is not correct to use the highfreq-clock, but I can't be absolutely
sure from the datasheet, maybe someone with access to the verilog/vhdl code can shed
some insight?!
Or is it valid, but leads to some very obscure and rare condition in the timer?
What I don't understand than, is why it worked with older kernels, when the
clocks are not okay. And what is happening in those 6mins when the system is
hanging?
It does not appear to be:
- some timer wrap around (should happen more often)
- some race condition with the set_next_event
- something with getnstimeofday itself
I hope I didn't forget anything of importance and Shawn (someone) has an idea.
Or can tell me, that ipg_clk_highfreq is definitely wrong, because of $reason.
Thanks,
Steffen
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 03/10] gpio: pxa: avoid to use global irq base
From: Haojian Zhuang @ 2013-01-29 16:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <51065BFC.6000205@compulab.co.il>
On 28 January 2013 19:07, Igor Grinberg <grinberg@compulab.co.il> wrote:
> On 01/23/13 10:25, Haojian Zhuang wrote:
>> Avoid to use global irq_base in gpio-pxa driver. Define irq_base in each
>> pxa_gpio_chip instead. Then we can avoid to use macro PXA_GPIO_TO_IRQ() &
>> MMP_GPIO_TO_IRQ().
>>
>> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
>> ---
>> arch/arm/mach-pxa/pxa25x.c | 2 +-
>> arch/arm/mach-pxa/pxa27x.c | 2 +-
>> drivers/gpio/gpio-pxa.c | 142 ++++++++++++++++++++++----------------------
>> include/linux/gpio-pxa.h | 4 +-
>> 4 files changed, 77 insertions(+), 73 deletions(-)
>
> [...]
>
>> diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
>> index 8e66c6b..da6e7fd 100644
>> --- a/drivers/gpio/gpio-pxa.c
>> +++ b/drivers/gpio/gpio-pxa.c
>
> [...]
>
>> @@ -485,7 +452,7 @@ static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
>> return 0;
>> }
>>
>> -const struct irq_domain_ops pxa_irq_domain_ops = {
>> +static const struct irq_domain_ops pxa_irq_domain_ops = {
>> .map = pxa_irq_domain_map,
>> .xlate = irq_domain_xlate_twocell,
>> };
>
> You should also move this out of CONFIG_OF as I don't think it is a dependency,
> and also otherwise you get the below...
>
>> @@ -529,14 +496,6 @@ static int pxa_gpio_probe_dt(struct platform_device *pdev)
>> nr_gpios = nr_banks << 5;
>> pxa_last_gpio = nr_gpios - 1;
>>
>> - irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
>> - if (irq_base < 0) {
>> - dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
>> - goto err;
>> - }
>> - domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
>> - &pxa_irq_domain_ops, NULL);
>> - pxa_gpio_of_node = np;
>> return 0;
>> err:
>> iounmap(gpio_reg_base);
>> @@ -546,6 +505,56 @@ err:
>> #define pxa_gpio_probe_dt(pdev) (-1)
>> #endif
>>
>> +static int pxa_init_gpio_chip(struct platform_device *pdev, int gpio_end,
>> + int (*set_wake)(unsigned int, unsigned int))
>> +{
>> + int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
>> + struct pxa_gpio_chip *chips;
>> +
>> + chips = devm_kzalloc(&pdev->dev, nbanks * sizeof(*chips), GFP_KERNEL);
>> + if (chips == NULL) {
>> + pr_err("%s: failed to allocate GPIO chips\n", __func__);
>> + return -ENOMEM;
>> + }
>> +
>> + for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
>> + struct gpio_chip *c = &chips[i].chip;
>> +
>> + sprintf(chips[i].label, "gpio-%d", i);
>> + chips[i].regbase = gpio_reg_base + BANK_OFF(i);
>> + chips[i].set_wake = set_wake;
>> +
>> + c->base = gpio;
>> + c->label = chips[i].label;
>> +
>> + c->direction_input = pxa_gpio_direction_input;
>> + c->direction_output = pxa_gpio_direction_output;
>> + c->get = pxa_gpio_get;
>> + c->set = pxa_gpio_set;
>> + c->to_irq = pxa_gpio_to_irq;
>> +#ifdef CONFIG_OF_GPIO
>> + c->of_node = pxa_gpio_of_node;
>> + c->of_xlate = pxa_gpio_of_xlate;
>> + c->of_gpio_n_cells = 2;
>> +#endif
>> +
>> + /* number of GPIOs on last bank may be less than 32 */
>> + c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
>> +
>> + chips[i].irq_base = irq_alloc_descs(-1, 0, c->ngpio, 0);
>> + if (chips[i].irq_base < 0)
>> + return -EINVAL;
>> + if (!irq_domain_add_legacy(pdev->dev.of_node, c->ngpio,
>> + chips[i].irq_base, 0,
>> + &pxa_irq_domain_ops, &chips[i]))
>
> if !CONFIG_OF, you get:
> drivers/gpio/gpio-pxa.c:479: error: 'pxa_irq_domain_ops' undeclared (first use in this function)
>
> Also, for !CONFIG_IRQ_DOMAIN, you get:
> drivers/gpio/gpio-pxa.c: In function 'pxa_init_gpio_chip':
> drivers/gpio/gpio-pxa.c:477: error: implicit declaration of function 'irq_domain_add_legacy'
>
> Should we select IRQ_DOMAIN for PXA?
> Will it work for other drivers?
>
We could use IRQ_DOMAIN. After all these patches are applied, there's
no CONFIG_IRQ_DOMAIN in pxa-gpio.c.
I tested the gpio driver on pxa910 (arch/mmp) w/wo CONFIG_OF. It works.
Thanks for your test. I'm sorry that I didn't do enough build test on
pxa. I'll fix all these issues.
>> + return -ENODEV;
>> +
>> + gpiochip_add(c);
>> + }
>> + pxa_gpio_chips = chips;
>> + return 0;
>> +}
>> +
>> static int pxa_gpio_probe(struct platform_device *pdev)
>> {
>> struct pxa_gpio_chip *c;
>
> [...]
>
>
> --
> Regards,
> Igor.
^ permalink raw reply
* [PATCH v2 0/4] Preparatory GIC patches for arm64 support
From: Catalin Marinas @ 2013-01-29 16:18 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
That's the second version of the GIC clean-up patches to support arm64.
The only change from v1 is that the second patch (chained_irq.h) also
covers drivers/gpio and drivers/pinctrl (#include change).
Catalin
Catalin Marinas (4):
arm: Move the set_handle_irq and handle_arch_irq declarations to
asm/irq.h
arm: Move chained_irq_(enter|exit) to a generic file
irqchip: gic: Call handle_bad_irq() directly
irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
arch/arm/include/asm/irq.h | 5 +++
arch/arm/include/asm/mach/irq.h | 36 --------------------
arch/arm/mach-at91/gpio.c | 3 +-
arch/arm/mach-exynos/common.c | 1 +
arch/arm/mach-exynos/platsmp.c | 8 -----
arch/arm/mach-highbank/platsmp.c | 7 ----
arch/arm/mach-imx/platsmp.c | 12 -------
arch/arm/mach-msm/platsmp.c | 8 -----
arch/arm/mach-omap2/omap-smp.c | 7 ----
arch/arm/mach-shmobile/smp-emev2.c | 7 ----
arch/arm/mach-shmobile/smp-r8a7779.c | 7 ----
arch/arm/mach-shmobile/smp-sh73a0.c | 7 ----
arch/arm/mach-socfpga/platsmp.c | 12 -------
arch/arm/mach-spear13xx/platsmp.c | 8 -----
arch/arm/mach-tegra/platsmp.c | 8 -----
arch/arm/mach-ux500/platsmp.c | 8 -----
arch/arm/plat-samsung/irq-vic-timer.c | 3 +-
arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +-
arch/arm/plat-versatile/platsmp.c | 8 -----
drivers/gpio/gpio-msm-v2.c | 3 +-
drivers/gpio/gpio-mxc.c | 2 +-
drivers/gpio/gpio-omap.c | 3 +-
drivers/gpio/gpio-pl061.c | 2 +-
drivers/gpio/gpio-pxa.c | 3 +-
drivers/gpio/gpio-tegra.c | 3 +-
drivers/irqchip/irq-gic.c | 32 +++++++++++++-----
drivers/irqchip/irq-vic.c | 2 +-
drivers/pinctrl/pinctrl-at91.c | 3 +-
drivers/pinctrl/pinctrl-exynos.c | 3 +-
drivers/pinctrl/pinctrl-nomadik.c | 2 +-
drivers/pinctrl/pinctrl-sirf.c | 2 +-
drivers/pinctrl/spear/pinctrl-plgpio.c | 2 +-
drivers/staging/imx-drm/ipu-v3/ipu-common.c | 2 +-
include/linux/irqchip/arm-gic.h | 1 -
include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++
35 files changed, 97 insertions(+), 178 deletions(-)
create mode 100644 include/linux/irqchip/chained_irq.h
^ permalink raw reply
* [PATCH v2 1/4] arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h
From: Catalin Marinas @ 2013-01-29 16:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359476319-23720-1-git-send-email-catalin.marinas@arm.com>
This patch prepares the removal of <asm/mach/irq.h> include in the
GIC and VIC irqchip drivers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
---
arch/arm/include/asm/irq.h | 5 +++++
arch/arm/include/asm/mach/irq.h | 5 -----
drivers/irqchip/irq-vic.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 35c21c3..53c15de 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *);
void handle_IRQ(unsigned int, struct pt_regs *);
void init_IRQ(void);
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+extern void (*handle_arch_irq)(struct pt_regs *);
+extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
+#endif
+
#endif
#endif
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 18c8830..749d505 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -20,11 +20,6 @@ struct seq_file;
extern void init_FIQ(int);
extern int show_fiq_list(struct seq_file *, int);
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-extern void (*handle_arch_irq)(struct pt_regs *);
-extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
-#endif
-
/*
* This is for easy migration, but should be changed in the source
*/
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index 3cf97aa..e38cb00 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -33,7 +33,7 @@
#include <linux/irqchip/arm-vic.h>
#include <asm/exception.h>
-#include <asm/mach/irq.h>
+#include <asm/irq.h>
#include "irqchip.h"
^ permalink raw reply related
* [PATCH v2 2/4] arm: Move chained_irq_(enter|exit) to a generic file
From: Catalin Marinas @ 2013-01-29 16:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359476319-23720-1-git-send-email-catalin.marinas@arm.com>
These functions have been introduced by commit 10a8c383 (irq: introduce
entry and exit functions for chained handlers) in asm/mach/irq.h. This
patch moves them to linux/irqchip/chained_irq.h so that generic irqchip
drivers do not rely on architecture specific header files.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
---
arch/arm/include/asm/mach/irq.h | 31 -----------------
arch/arm/mach-at91/gpio.c | 3 +-
arch/arm/mach-exynos/common.c | 1 +
arch/arm/plat-samsung/irq-vic-timer.c | 3 +-
arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +-
drivers/gpio/gpio-msm-v2.c | 3 +-
drivers/gpio/gpio-mxc.c | 2 +-
drivers/gpio/gpio-omap.c | 3 +-
drivers/gpio/gpio-pl061.c | 2 +-
drivers/gpio/gpio-pxa.c | 3 +-
drivers/gpio/gpio-tegra.c | 3 +-
drivers/irqchip/irq-gic.c | 1 +
drivers/pinctrl/pinctrl-at91.c | 3 +-
drivers/pinctrl/pinctrl-exynos.c | 3 +-
drivers/pinctrl/pinctrl-nomadik.c | 2 +-
drivers/pinctrl/pinctrl-sirf.c | 2 +-
drivers/pinctrl/spear/pinctrl-plgpio.c | 2 +-
drivers/staging/imx-drm/ipu-v3/ipu-common.c | 2 +-
include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++
19 files changed, 69 insertions(+), 55 deletions(-)
create mode 100644 include/linux/irqchip/chained_irq.h
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 749d505..2092ee1 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -30,35 +30,4 @@ do { \
raw_spin_unlock(&desc->lock); \
} while(0)
-#ifndef __ASSEMBLY__
-/*
- * Entry/exit functions for chained handlers where the primary IRQ chip
- * may implement either fasteoi or level-trigger flow control.
- */
-static inline void chained_irq_enter(struct irq_chip *chip,
- struct irq_desc *desc)
-{
- /* FastEOI controllers require no action on entry. */
- if (chip->irq_eoi)
- return;
-
- if (chip->irq_mask_ack) {
- chip->irq_mask_ack(&desc->irq_data);
- } else {
- chip->irq_mask(&desc->irq_data);
- if (chip->irq_ack)
- chip->irq_ack(&desc->irq_data);
- }
-}
-
-static inline void chained_irq_exit(struct irq_chip *chip,
- struct irq_desc *desc)
-{
- if (chip->irq_eoi)
- chip->irq_eoi(&desc->irq_data);
- else
- chip->irq_unmask(&desc->irq_data);
-}
-#endif
-
#endif
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index c5d7e1e..a5afcf7 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -22,10 +22,9 @@
#include <linux/module.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/of_address.h>
-#include <asm/mach/irq.h>
-
#include <mach/hardware.h>
#include <mach/at91_pio.h>
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 7f01a92..60dad95 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -25,6 +25,7 @@
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/irqchip/arm-gic.h>
+#include <linux/irqchip/chained_irq.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index f980cf3..5d205e7 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -16,6 +16,7 @@
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/io.h>
#include <mach/map.h>
@@ -23,8 +24,6 @@
#include <plat/irq-vic-timer.h>
#include <plat/regs-timer.h>
-#include <asm/mach/irq.h>
-
static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
index bae5613..fafdb05 100644
--- a/arch/arm/plat-samsung/s5p-irq-gpioint.c
+++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c
@@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>
@@ -22,8 +23,6 @@
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
-#include <asm/mach/irq.h>
-
#define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
#define CON_OFFSET 0x700
diff --git a/drivers/gpio/gpio-msm-v2.c b/drivers/gpio/gpio-msm-v2.c
index 55a7e77..dd2edde 100644
--- a/drivers/gpio/gpio-msm-v2.c
+++ b/drivers/gpio/gpio-msm-v2.c
@@ -23,13 +23,12 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
-#include <asm/mach/irq.h>
-
#include <mach/msm_gpiomux.h>
#include <mach/msm_iomap.h>
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 7877335..7176743 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -24,6 +24,7 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@@ -32,7 +33,6 @@
#include <linux/of_device.h>
#include <linux/module.h>
#include <asm-generic/bug.h>
-#include <asm/mach/irq.h>
enum mxc_gpio_hwtype {
IMX1_GPIO, /* runs on i.mx1 */
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f1fbedb2..6996da9 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -25,11 +25,10 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/gpio.h>
#include <linux/platform_data/gpio-omap.h>
-#include <asm/mach/irq.h>
-
#define OFF_MODE 1
static LIST_HEAD(omap_gpio_list);
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index b820869..2976336 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -15,6 +15,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/bitops.h>
#include <linux/workqueue.h>
#include <linux/gpio.h>
@@ -23,7 +24,6 @@
#include <linux/amba/pl061.h>
#include <linux/slab.h>
#include <linux/pm.h>
-#include <asm/mach/irq.h>
#define GPIODIR 0x400
#define GPIOIS 0x404
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 8325f58..2d3af98 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -19,6 +19,7 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
@@ -26,8 +27,6 @@
#include <linux/syscore_ops.h>
#include <linux/slab.h>
-#include <asm/mach/irq.h>
-
#include <mach/irqs.h>
/*
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 414ad91..8e21555 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -27,11 +27,10 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>
-#include <asm/mach/irq.h>
-
#define GPIO_BANK(x) ((x) >> 5)
#define GPIO_PORT(x) (((x) >> 3) & 0x3)
#define GPIO_BIT(x) ((x) & 0x7)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 69d9a39..688b977 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -38,6 +38,7 @@
#include <linux/interrupt.h>
#include <linux/percpu.h>
#include <linux/slab.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/irqchip/arm-gic.h>
#include <asm/irq.h>
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 75933a6..5cbadc9 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -18,6 +18,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/pinctrl/machine.h>
@@ -27,8 +28,6 @@
/* Since we request GPIOs from ourself */
#include <linux/pinctrl/consumer.h>
-#include <asm/mach/irq.h>
-
#include <mach/hardware.h>
#include <mach/at91_pio.h>
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 8738933..911c5e7 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -23,13 +23,12 @@
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>
-#include <asm/mach/irq.h>
-
#include "pinctrl-samsung.h"
#include "pinctrl-exynos.h"
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 39c1651..d30d3c1 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -23,6 +23,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
@@ -33,7 +34,6 @@
/* Since we request GPIOs from ourself */
#include <linux/pinctrl/consumer.h>
#include <linux/platform_data/pinctrl-nomadik.h>
-#include <asm/mach/irq.h>
#include "pinctrl-nomadik.h"
#include "core.h"
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 498b2ba..35e8cea 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -14,6 +14,7 @@
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/consumer.h>
@@ -25,7 +26,6 @@
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
-#include <asm/mach/irq.h>
#define DRIVER_NAME "pinmux-sirf"
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
index 295b349..a4908ec 100644
--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
+++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
@@ -15,12 +15,12 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/spinlock.h>
-#include <asm/mach/irq.h>
#define MAX_GPIO_PER_REG 32
#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-common.c b/drivers/staging/imx-drm/ipu-v3/ipu-common.c
index 366f259..6efe4e1 100644
--- a/drivers/staging/imx-drm/ipu-v3/ipu-common.c
+++ b/drivers/staging/imx-drm/ipu-v3/ipu-common.c
@@ -25,8 +25,8 @@
#include <linux/clk.h>
#include <linux/list.h>
#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/of_device.h>
-#include <asm/mach/irq.h>
#include "imx-ipu-v3.h"
#include "ipu-prv.h"
diff --git a/include/linux/irqchip/chained_irq.h b/include/linux/irqchip/chained_irq.h
new file mode 100644
index 0000000..adf4c30
--- /dev/null
+++ b/include/linux/irqchip/chained_irq.h
@@ -0,0 +1,52 @@
+/*
+ * Chained IRQ handlers support.
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __IRQCHIP_CHAINED_IRQ_H
+#define __IRQCHIP_CHAINED_IRQ_H
+
+#include <linux/irq.h>
+
+/*
+ * Entry/exit functions for chained handlers where the primary IRQ chip
+ * may implement either fasteoi or level-trigger flow control.
+ */
+static inline void chained_irq_enter(struct irq_chip *chip,
+ struct irq_desc *desc)
+{
+ /* FastEOI controllers require no action on entry. */
+ if (chip->irq_eoi)
+ return;
+
+ if (chip->irq_mask_ack) {
+ chip->irq_mask_ack(&desc->irq_data);
+ } else {
+ chip->irq_mask(&desc->irq_data);
+ if (chip->irq_ack)
+ chip->irq_ack(&desc->irq_data);
+ }
+}
+
+static inline void chained_irq_exit(struct irq_chip *chip,
+ struct irq_desc *desc)
+{
+ if (chip->irq_eoi)
+ chip->irq_eoi(&desc->irq_data);
+ else
+ chip->irq_unmask(&desc->irq_data);
+}
+
+#endif /* __IRQCHIP_CHAINED_IRQ_H */
^ permalink raw reply related
* [PATCH v2 3/4] irqchip: gic: Call handle_bad_irq() directly
From: Catalin Marinas @ 2013-01-29 16:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359476319-23720-1-git-send-email-catalin.marinas@arm.com>
Previously, the gic_handle_cascade_irq() function was calling the
ARM-specific do_bad_IRQ() function which calls handle_bad_irq() after
acquiring the desk->lock. Locking the cascaded IRQ desc is not needed
for error reporting, so just call handle_bad_irq() directly.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
---
drivers/irqchip/irq-gic.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 688b977..ef1429a 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -44,7 +44,6 @@
#include <asm/irq.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>
-#include <asm/mach/irq.h>
#include "irqchip.h"
@@ -324,7 +323,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
if (unlikely(gic_irq < 32 || gic_irq > 1020))
- do_bad_IRQ(cascade_irq, desc);
+ handle_bad_irq(cascade_irq, desc);
else
generic_handle_irq(cascade_irq);
^ permalink raw reply related
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
From: Catalin Marinas @ 2013-01-29 16:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359476319-23720-1-git-send-email-catalin.marinas@arm.com>
All the calls to gic_secondary_init() pass 0 as the first argument.
Since this function is called on each CPU when starting, it can be done
in a platform-independent way via a CPU notifier registered by the GIC
code.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-exynos/platsmp.c | 8 --------
arch/arm/mach-highbank/platsmp.c | 7 -------
arch/arm/mach-imx/platsmp.c | 12 ------------
arch/arm/mach-msm/platsmp.c | 8 --------
arch/arm/mach-omap2/omap-smp.c | 7 -------
arch/arm/mach-shmobile/smp-emev2.c | 7 -------
arch/arm/mach-shmobile/smp-r8a7779.c | 7 -------
arch/arm/mach-shmobile/smp-sh73a0.c | 7 -------
arch/arm/mach-socfpga/platsmp.c | 12 ------------
arch/arm/mach-spear13xx/platsmp.c | 8 --------
arch/arm/mach-tegra/platsmp.c | 8 --------
arch/arm/mach-ux500/platsmp.c | 8 --------
arch/arm/plat-versatile/platsmp.c | 8 --------
drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++-------
include/linux/irqchip/arm-gic.h | 1 -
15 files changed, 21 insertions(+), 115 deletions(-)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a083e05..a0e8ff7 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -20,7 +20,6 @@
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
@@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit exynos_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
index 8797a70..a984573 100644
--- a/arch/arm/mach-highbank/platsmp.c
+++ b/arch/arm/mach-highbank/platsmp.c
@@ -17,7 +17,6 @@
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/smp_scu.h>
@@ -25,11 +24,6 @@
extern void secondary_startup(void);
-static void __cpuinit highbank_secondary_init(unsigned int cpu)
-{
- gic_secondary_init(0);
-}
-
static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
highbank_set_cpu_jump(cpu, secondary_startup);
@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
struct smp_operations highbank_smp_ops __initdata = {
.smp_init_cpus = highbank_smp_init_cpus,
.smp_prepare_cpus = highbank_smp_prepare_cpus,
- .smp_secondary_init = highbank_secondary_init,
.smp_boot_secondary = highbank_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = highbank_cpu_die,
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index b2872ec..7f63dda 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -12,7 +12,6 @@
#include <linux/init.h>
#include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/page.h>
#include <asm/smp_scu.h>
#include <asm/mach/map.h>
@@ -42,16 +41,6 @@ void __init imx_scu_map_io(void)
scu_base = IMX_IO_ADDRESS(base);
}
-static void __cpuinit imx_secondary_init(unsigned int cpu)
-{
- /*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-}
-
static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
imx_set_cpu_jump(cpu, v7_secondary_startup);
@@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
struct smp_operations imx_smp_ops __initdata = {
.smp_init_cpus = imx_smp_init_cpus,
.smp_prepare_cpus = imx_smp_prepare_cpus,
- .smp_secondary_init = imx_secondary_init,
.smp_boot_secondary = imx_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = imx_cpu_die,
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 42932865..00cdb0a 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -15,7 +15,6 @@
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
@@ -42,13 +41,6 @@ static inline int get_core_count(void)
static void __cpuinit msm_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 3616779..c6ce880 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
4, 0, 0, 0, 0, 0);
/*
- * If any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 953eb1f..384e27d 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -23,7 +23,6 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
#include <mach/common.h>
#include <mach/emev2.h>
#include <asm/smp_plat.h>
@@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
}
-static void __cpuinit emev2_secondary_init(unsigned int cpu)
-{
- gic_secondary_init(0);
-}
-
static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
cpu = cpu_logical_map(cpu);
@@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)
struct smp_operations emev2_smp_ops __initdata = {
.smp_init_cpus = emev2_smp_init_cpus,
.smp_prepare_cpus = emev2_smp_prepare_cpus,
- .smp_secondary_init = emev2_secondary_init,
.smp_boot_secondary = emev2_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = emev2_cpu_kill,
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 3a4acf2..9949065 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -23,7 +23,6 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
#include <mach/common.h>
#include <mach/r8a7779.h>
#include <asm/smp_plat.h>
@@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
}
-static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
-{
- gic_secondary_init(0);
-}
-
static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
struct r8a7779_pm_ch *ch = NULL;
@@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)
struct smp_operations r8a7779_smp_ops __initdata = {
.smp_init_cpus = r8a7779_smp_init_cpus,
.smp_prepare_cpus = r8a7779_smp_prepare_cpus,
- .smp_secondary_init = r8a7779_secondary_init,
.smp_boot_secondary = r8a7779_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = r8a7779_cpu_kill,
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 9812ea3..f3b4912 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -23,7 +23,6 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
#include <mach/common.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
@@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)
return scu_get_core_count(scu_base);
}
-static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
-{
- gic_secondary_init(0);
-}
-
static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
cpu = cpu_logical_map(cpu);
@@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)
struct smp_operations sh73a0_smp_ops __initdata = {
.smp_init_cpus = sh73a0_smp_init_cpus,
.smp_prepare_cpus = sh73a0_smp_prepare_cpus,
- .smp_secondary_init = sh73a0_secondary_init,
.smp_boot_secondary = sh73a0_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = sh73a0_cpu_kill,
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 4e9e69d..4b468ef 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -22,7 +22,6 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_scu.h>
@@ -33,16 +32,6 @@
extern void __iomem *sys_manager_base_addr;
extern void __iomem *rst_manager_base_addr;
-static void __cpuinit socfpga_secondary_init(unsigned int cpu)
-{
- /*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-}
-
static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
@@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu)
struct smp_operations socfpga_smp_ops __initdata = {
.smp_init_cpus = socfpga_smp_init_cpus,
.smp_prepare_cpus = socfpga_smp_prepare_cpus,
- .smp_secondary_init = socfpga_secondary_init,
.smp_boot_secondary = socfpga_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = socfpga_cpu_die,
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
index af4ade6..551c69c 100644
--- a/arch/arm/mach-spear13xx/platsmp.c
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -15,7 +15,6 @@
#include <linux/jiffies.h>
#include <linux/io.h>
#include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_scu.h>
#include <mach/spear.h>
@@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index c72e249..dea94d2 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -18,7 +18,6 @@
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
#include <linux/clk/tegra.h>
#include <asm/cacheflush.h>
@@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
static void __cpuinit tegra_secondary_init(unsigned int cpu)
{
- /*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
}
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index b8adac9..b4d0735 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -16,7 +16,6 @@
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
@@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit ux500_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index f2ac155..1e1b2d7 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -14,7 +14,6 @@
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
@@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);
void __cpuinit versatile_secondary_init(unsigned int cpu)
{
/*
- * if any interrupts are already enabled for the primary
- * core (e.g. timer irq), then they will not have been enabled
- * for us: do so
- */
- gic_secondary_init(0);
-
- /*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index ef1429a..f103cb8 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -28,6 +28,7 @@
#include <linux/module.h>
#include <linux/list.h>
#include <linux/smp.h>
+#include <linux/cpu.h>
#include <linux/cpu_pm.h>
#include <linux/cpumask.h>
#include <linux/io.h>
@@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
return 0;
}
+#ifdef CONFIG_SMP
+static int __cpuinit gic_secondary_init(struct notifier_block *nfb,
+ unsigned long action, void *hcpu)
+{
+ if (action == CPU_STARTING)
+ gic_cpu_init(&gic_data[0]);
+ return NOTIFY_OK;
+}
+
+/*
+ * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
+ * priority because the GIC needs to be up before the ARM generic timers.
+ */
+static struct notifier_block __cpuinitdata gic_cpu_notifier = {
+ .notifier_call = gic_secondary_init,
+ .priority = 100,
+};
+#endif
+
const struct irq_domain_ops gic_irq_domain_ops = {
.map = gic_irq_domain_map,
.xlate = gic_irq_domain_xlate,
@@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
#ifdef CONFIG_SMP
set_smp_cross_call(gic_raise_softirq);
+ register_cpu_notifier(&gic_cpu_notifier);
#endif
set_handle_irq(gic_handle_irq);
@@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
gic_pm_init(gic);
}
-void __cpuinit gic_secondary_init(unsigned int gic_nr)
-{
- BUG_ON(gic_nr >= MAX_GIC_NR);
-
- gic_cpu_init(&gic_data[gic_nr]);
-}
-
#ifdef CONFIG_OF
static int gic_cnt __initdata = 0;
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index a67ca55..59e59b3 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn;
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset, struct device_node *);
-void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
static inline void gic_init(unsigned int nr, int start,
^ permalink raw reply related
* [PATCH v2 05/27] arm: pci: add a align_resource hook
From: Thomas Petazzoni @ 2013-01-29 16:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130129155820.GB23505@n2100.arm.linux.org.uk>
Russell,
On Tue, 29 Jan 2013 15:58:20 +0000, Russell King - ARM Linux wrote:
> On Tue, Jan 29, 2013 at 04:12:11PM +0100, Thomas Petazzoni wrote:
> > On Mon, 28 Jan 2013 19:56:14 +0100, Thomas Petazzoni wrote:
> > > The PCI specifications says that an I/O region must be aligned on a 4
> > > KB boundary, and a memory region aligned on a 1 MB boundary.
>
> BTW, this, as a general statement, is wrong - though it really depends
> what you mean by "region".
Yes, sorry, my statement does not correctly reflect the reality. My
knowledge of the PCI terminology is still quite fuzzy (as you found
out). What I am referring to is that the PCI standard requires the I/O
base register of a PCI-to-PCI bridge to contain a 4 KB aligned address.
>From the PCI-to-PCI Bridge Architecture Specification, Revision 1.1,
section 3.2.5.6. I/O Base Register and I/O Limit Register:
"""
If a bridge implements an I/O address range, the upper 4 bits of
both the I/O Base and I/O Limit registers are writable and
correspond to address bits AD[15::12]. For the purpose of address
decoding, the bridge assumes that the lower 12 address bits,
AD[11::00], of the I/O base address (not implemented in the I/O Base
register) are zero. Similarly, the bridge assumes that the lower 12
address bits, AD[11::00], of the I/O limit address (not implemented
in the I/O Limit register) are FFFh. Thus, the bottom of the defined
I/O address range will be aligned to a 4 KB boundary and the top of
the defined I/O address range will be one less than a 4 KB boundary.
"""
And the Linux PCI resource allocation code complies with this, so that
if I have two PCI-to-PCI bridges (each having downstream a device with
an I/O BAR), then the first PCI-to-PCI bridge gets its I/O base address
register set to ADDR + 0x0, and the second bridge gets its I/O base
address set to ADDR + 0x1000. And this doesn't play well with the
requirements of Marvell address decoding windows for PCIe I/O regions,
which must be 64 KB aligned.
So I guess I should simply rewrite the commit log to make it clear that
I'm referring to the I/O base address register of PCI-to-PCI bridges.
Would this be more correct? In that case, maybe in fact I really need a
hook so that this alignment requirement on only applied on the
resources allocated to bridges, and not on their downstream devices?
Thanks,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 1/5] dmaengine: dw_dmac: move to generic DMA binding
From: Arnd Bergmann @ 2013-01-29 16:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKohpoms+WC_XJnH2b6uoycRKkF-yxZUg2J+8NrYJP8fnDNLtg@mail.gmail.com>
On Tuesday 29 January 2013, Viresh Kumar wrote:
> On 29 January 2013 19:01, Arnd Bergmann <arnd@arndb.de> wrote:
> > Ah, good. So I guess the "dma-requests" property should actually
> > be "16" then.
>
> yes, even i was checking on that separately :)
Actually, I just discovered something odd in the
arch/arm/mach-spear/spear13xx-dma.h file that gets removed
in the last patch: there, we define request numbers up to
32, e.g.
- SPEAR1310_DMA_REQ_UART2_RX = 14,
- SPEAR1310_DMA_REQ_UART2_TX = 15,
- SPEAR1310_DMA_REQ_UART5_RX = 16,
- SPEAR1310_DMA_REQ_UART5_TX = 17,
What is the meaning of this, if the maximum request number is 15?
> > Could we have device-to-device DMAs with this controller, and if
> > we can, should we have both 'src' and 'dst' fields? Are the
> > two number ranges sharing the same address space, i.e. is
> > request '7' as the destination guaranteed to be the same device
> > as request '7' in the source?
>
> Request lines are per master... So, for a master single request line
> is independent of direction. Many DMA controllers have capability of
> doing dev-to-dev transfers but DMAENGINE doesn't have any support
> for it, even we don't have a usecase too :)
>
> > If we need two lines, we could interleave them with the bus
> > master numbers:
>
> not required.
Ok. Would it be enough to have only one master and one request
field in the DT dma descriptor then, and have the code figure
whether to use it as source or destination, based on the
configuration? Which one should come first? Since you have
multiple masters per controller, and multiple requests per
master, it sounds like the cleanest descriptor form would
be
<controller master request>;
Or possibly
<controller master request direction>;
if the direction needs to be known at the time the channel
is requested.
Arnd
^ permalink raw reply
* [PATCH 5/5] mv643xx_eth: convert to use the Marvell Orion MDIO driver
From: Florian Fainelli @ 2013-01-29 16:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130129170131.7964a110@skate>
On 01/29/2013 05:01 PM, Thomas Petazzoni wrote:
> Dear Florian Fainelli,
>
> On Tue, 29 Jan 2013 16:24:08 +0100, Florian Fainelli wrote:
>> This patch converts the Marvell MV643XX ethernet driver to use the
>> Marvell Orion MDIO driver. As a result, PowerPC and ARM platforms
>> registering the Marvell MV643XX ethernet driver are also updated to
>> register a Marvell Orion MDIO driver. This driver voluntarily overlaps
>> with the Marvell Ethernet shared registers because it will use a subset
>> of this shared register (shared_base + 0x4 - shared_base + 0x84). The
>> Ethernet driver is also updated to look up for a PHY device using the
>> Orion MDIO bus driver.
>>
>> Signed-off-by: Florian Fainelli <florian@openwrt.org>
>> ---
>> arch/arm/plat-orion/common.c | 84 +++++++++++--
> In this file, there was one "MV643XX_ETH_SHARED_NAME" platform_device
> registered for each network interface. Why? If the driver is shared,
> isn't the whole idea to register it only once?
It looks like I introduced two redundant mvmdio instances as ge01 refers
to the ge00 smi bus (the same applies to ge11 and ge10). Thanks for
spotting this.
>
> In any case, one of the idea of separating the mvmdio driver from the
> mvneta driver in the first place is that there should be only one
> instance of the mvmdio device, even if there are multiple network
> interfaces. The reason is that from a HW point of the view, the MDIO
> unit is shared between the network interfaces. If you look at
> armada-370-xp.dtsi, there is only one mvmdio device registered, and two
> network interfaces (using the mvneta driver) that are registered (and
> actually up to four network interfaces can exist, they are added by
> some other .dtsi files depending on the specific SoC).
>
> So I don't think there should be one instance of the mvmdio per network
> interface.
>
> Also, I am wondering what's left in this MV643XX_ETH_SHARED_NAME driver
> once the MDIO stuff has been pulled out in a separate driver? I think
> the whole point of this work should be to get rid of this
> MV643XX_ETH_SHARED_NAME driver, no?
If you take a closer look at mv643xx_eth you will see that the "shared"
driver still handles the mconf bus window configuration, which is not
abstracted yet. Besides that, I would rather do it step by step.
--
Florian
^ permalink raw reply
* i.Mx6Quad - eth0: tx queue full!
From: Vikram Narayanan @ 2013-01-29 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5106D5D4.2090200@boundarydevices.com>
On 1/29/2013 1:17 AM, Troy Kisky wrote:
> On 1/28/2013 10:39 AM, Vikram Narayanan wrote:
>> Running the latest head <linux-2.6.git> on an i.Mx6Quad based platform
>> gives me the below error when flooded with ping requests.
>>
>> == Start log ==
>> [ 2555.004031] ------------[ cut here ]------------
>> [ 2555.009740] WARNING: at net/sched/sch_generic.c:254
>> dev_watchdog+0x298/0x2b8()
>> [ 2555.018721] NETDEV WATCHDOG: eth0 (fec): transmit queue 0 timed out
>
> I think the tx interrupt status bit was lost. The packets were
> transmitted, but the interrupt never
> happened. The controller should have been reset here, but perhaps a bug
> with the reset code.
> Are you using the mainline kernel, or a version Freescale's kernel.
I tried with both the kernels. Freescale's and mainline results in the
same error.
> mainline fec_restart does not reset tx_full
>
> You can try adding
> fep->tx_full = 0;
With this there was no improvement.
> to fec_restart, though it would be better to call fec_enet_tx in
> fec_timeout
> and skip the call to fec_restart if it returns some packets.
fec_enet_tx returns void, how do I check for the return packets.
I'm sorry, I couldn't get your point here.
>
>> [ 2555.026733] Modules linked in:
>> [ 2555.030598] Backtrace:
>> [ 2555.034252] [<800119c8>] (dump_backtrace+0x0/0x10c) from
>> [<803b8494>] (dump_stack+0x18/0x1c)
>> [ 2555.044438] r6:000000fe r5:80302f64 r4:80503dd0 r3:80510e80
>> [ 2555.052019] [<803b847c>] (dump_stack+0x0/0x1c) from [<8001df08>]
>> (warn_slowpath_common+0x54/0x6c)
>> [ 2555.062679] [<8001deb4>] (warn_slowpath_common+0x0/0x6c) from
>> [<8001dfc4>] (warn_slowpath_fmt+0x38/0x40)
>> [ 2555.073936] r8:8052ebf1 r7:805040c0 r6:00000000 r5:8f9771d4
>> r4:8f977000
>> r3:00000009
>> [ 2555.084816] [<8001df8c>] (warn_slowpath_fmt+0x0/0x40) from
>> [<80302f64>] (dev_watchdog+0x298/0x2b8)
>> [ 2555.095535] r3:8f977000 r2:8049f6d4
>> [ 2555.099868] [<80302ccc>] (dev_watchdog+0x0/0x2b8) from [<8002acf8>]
>> (call_timer_fn.isra.33+0x2c/0x8c)
>> [ 2555.110794] [<8002accc>] (call_timer_fn.isra.33+0x0/0x8c) from
>> [<8002af48>] (run_timer_softirq+0x1f0/0x204)
>> [ 2555.122240] r7:80571114 r6:805040c0 r5:00000000 r4:80570900
>> [ 2555.129894] [<8002ad58>] (run_timer_softirq+0x0/0x204) from
>> [<80025750>] (__do_softirq+0xc8/0x180)
>> [ 2555.140599] [<80025688>] (__do_softirq+0x0/0x180) from [<80025b40>]
>> (irq_exit+0x88/0x90)
>> [ 2555.150492] [<80025ab8>] (irq_exit+0x0/0x90) from [<8000ec58>]
>> (handle_IRQ+0x44/0x98)
>> [ 2555.160112] r4:804ffde0 r3:00000220
>> [ 2555.164848] [<8000ec14>] (handle_IRQ+0x0/0x98) from [<80008540>]
>> (gic_handle_irq+0x30/0x64)
>> [ 2555.174956] r6:80503f28 r5:8050a518 r4:f400010c r3:00000000
>> [ 2555.182694] [<80008510>] (gic_handle_irq+0x0/0x64) from
>> [<8000df80>] (__irq_svc+0x40/0x50)
>> [ 2555.192737] Exception stack(0x80503f28 to 0x80503f70)
>> [ 2555.198639] 3f20: 8052f150 a0000093 00000000
>> 00000000 80502000 8052ed08
>> [ 2555.208600] 3f40: 8050a4f4 803bfaec 8050df00 412fc09a 80502000
>> 80503f7c 80503f80 80503f70
>> [ 2555.218584] 3f60: 8000eee4 8000eee8 60000013 ffffffff
>> [ 2555.224730] r7:80503f5c r6:ffffffff r5:60000013 r4:8000eee8
>> [ 2555.232292] [<8000eeb8>] (default_idle+0x0/0x38) from [<8000f0d8>]
>> (cpu_idle+0xcc/0x114)
>> [ 2555.242204] [<8000f00c>] (cpu_idle+0x0/0x114) from [<803b3718>]
>> (rest_init+0x64/0x7c)
>> [ 2555.251858] [<803b36b4>] (rest_init+0x0/0x7c) from [<804cc7dc>]
>> (start_kernel+0x258/0x298)
>> [ 2555.261963] [<804cc584>] (start_kernel+0x0/0x298) from [<10008078>]
>> (0x10008078)
>> [ 2555.271167] ---[ end trace 3d2ffb53e6fe41f3 ]---
>> [ 2555.277270] eth0: tx queue full!.
>> [ 2555.288776] eth0: tx queue full!.
>> [ 2555.293594] eth0: tx queue full!.
>> [ 2555.297944] eth0: tx queue full!.
>> [ 2555.302229] eth0: tx queue full!.
> All the packet have been transmitted but the transmit queue is full, so
> no more
> tx interrupts can happen to replace the previously lost tx interrupt.
>
> I've seen MII interrupts clear the TX interrupt status bit.
>
Do you suspect the MAC <-> PHY interconnect? I'm having an MII interface.
Regards,
Vikram
^ permalink raw reply
* i.Mx6Quad - eth0: tx queue full!
From: Vikram Narayanan @ 2013-01-29 16:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5106D5D4.2090200@boundarydevices.com>
On 1/29/2013 1:17 AM, Troy Kisky wrote:
> On 1/28/2013 10:39 AM, Vikram Narayanan wrote:
>> Running the latest head <linux-2.6.git> on an i.Mx6Quad based platform
>> gives me the below error when flooded with ping requests.
>>
>> == Start log ==
>> [ 2555.004031] ------------[ cut here ]------------
>> [ 2555.009740] WARNING: at net/sched/sch_generic.c:254
>> dev_watchdog+0x298/0x2b8()
>> [ 2555.018721] NETDEV WATCHDOG: eth0 (fec): transmit queue 0 timed out
>
> I think the tx interrupt status bit was lost. The packets were
> transmitted, but the interrupt never
> happened. The controller should have been reset here, but perhaps a bug
> with the reset code.
> Are you using the mainline kernel, or a version Freescale's kernel.
I tried with both the kernels. Freescale's and mainline results in the
same error.
> mainline fec_restart does not reset tx_full
>
> You can try adding
> fep->tx_full = 0;
With this there was no improvement.
> to fec_restart, though it would be better to call fec_enet_tx in
> fec_timeout
> and skip the call to fec_restart if it returns some packets.
fec_enet_tx returns void, how do I check for the return packets.
I'm sorry, I couldn't get your point here.
>
>> [ 2555.026733] Modules linked in:
>> [ 2555.030598] Backtrace:
>> [ 2555.034252] [<800119c8>] (dump_backtrace+0x0/0x10c) from
>> [<803b8494>] (dump_stack+0x18/0x1c)
>> [ 2555.044438] r6:000000fe r5:80302f64 r4:80503dd0 r3:80510e80
>> [ 2555.052019] [<803b847c>] (dump_stack+0x0/0x1c) from [<8001df08>]
>> (warn_slowpath_common+0x54/0x6c)
>> [ 2555.062679] [<8001deb4>] (warn_slowpath_common+0x0/0x6c) from
>> [<8001dfc4>] (warn_slowpath_fmt+0x38/0x40)
>> [ 2555.073936] r8:8052ebf1 r7:805040c0 r6:00000000 r5:8f9771d4
>> r4:8f977000
>> r3:00000009
>> [ 2555.084816] [<8001df8c>] (warn_slowpath_fmt+0x0/0x40) from
>> [<80302f64>] (dev_watchdog+0x298/0x2b8)
>> [ 2555.095535] r3:8f977000 r2:8049f6d4
>> [ 2555.099868] [<80302ccc>] (dev_watchdog+0x0/0x2b8) from [<8002acf8>]
>> (call_timer_fn.isra.33+0x2c/0x8c)
>> [ 2555.110794] [<8002accc>] (call_timer_fn.isra.33+0x0/0x8c) from
>> [<8002af48>] (run_timer_softirq+0x1f0/0x204)
>> [ 2555.122240] r7:80571114 r6:805040c0 r5:00000000 r4:80570900
>> [ 2555.129894] [<8002ad58>] (run_timer_softirq+0x0/0x204) from
>> [<80025750>] (__do_softirq+0xc8/0x180)
>> [ 2555.140599] [<80025688>] (__do_softirq+0x0/0x180) from [<80025b40>]
>> (irq_exit+0x88/0x90)
>> [ 2555.150492] [<80025ab8>] (irq_exit+0x0/0x90) from [<8000ec58>]
>> (handle_IRQ+0x44/0x98)
>> [ 2555.160112] r4:804ffde0 r3:00000220
>> [ 2555.164848] [<8000ec14>] (handle_IRQ+0x0/0x98) from [<80008540>]
>> (gic_handle_irq+0x30/0x64)
>> [ 2555.174956] r6:80503f28 r5:8050a518 r4:f400010c r3:00000000
>> [ 2555.182694] [<80008510>] (gic_handle_irq+0x0/0x64) from
>> [<8000df80>] (__irq_svc+0x40/0x50)
>> [ 2555.192737] Exception stack(0x80503f28 to 0x80503f70)
>> [ 2555.198639] 3f20: 8052f150 a0000093 00000000
>> 00000000 80502000 8052ed08
>> [ 2555.208600] 3f40: 8050a4f4 803bfaec 8050df00 412fc09a 80502000
>> 80503f7c 80503f80 80503f70
>> [ 2555.218584] 3f60: 8000eee4 8000eee8 60000013 ffffffff
>> [ 2555.224730] r7:80503f5c r6:ffffffff r5:60000013 r4:8000eee8
>> [ 2555.232292] [<8000eeb8>] (default_idle+0x0/0x38) from [<8000f0d8>]
>> (cpu_idle+0xcc/0x114)
>> [ 2555.242204] [<8000f00c>] (cpu_idle+0x0/0x114) from [<803b3718>]
>> (rest_init+0x64/0x7c)
>> [ 2555.251858] [<803b36b4>] (rest_init+0x0/0x7c) from [<804cc7dc>]
>> (start_kernel+0x258/0x298)
>> [ 2555.261963] [<804cc584>] (start_kernel+0x0/0x298) from [<10008078>]
>> (0x10008078)
>> [ 2555.271167] ---[ end trace 3d2ffb53e6fe41f3 ]---
>> [ 2555.277270] eth0: tx queue full!.
>> [ 2555.288776] eth0: tx queue full!.
>> [ 2555.293594] eth0: tx queue full!.
>> [ 2555.297944] eth0: tx queue full!.
>> [ 2555.302229] eth0: tx queue full!.
> All the packet have been transmitted but the transmit queue is full, so
> no more
> tx interrupts can happen to replace the previously lost tx interrupt.
>
> I've seen MII interrupts clear the TX interrupt status bit.
>
Do you suspect the MAC <-> PHY interconnect? I'm having an MII interface.
Regards,
Vikram
^ permalink raw reply
* [PATCH 1/5] dmaengine: dw_dmac: move to generic DMA binding
From: Arnd Bergmann @ 2013-01-29 16:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130129154409.GA23505@n2100.arm.linux.org.uk>
On Tuesday 29 January 2013, Russell King - ARM Linux wrote:
> That's a good way to represent it but it fails in a very big way:
> You're stuffing N peripherals down to 3 request lines to the DMA
> engine, and you may want more than 3 of those peripherals to be
> making use of the DMA engine at any one time.
>
> Before anyone says "you shouldn't be doing this" consider this:
> your typical DMA slave engine already has this structure:
>
> N DMA channels <---> M DMA requests <---> M peripherals
>
> where N < M. In other words, there is already a MUX between the
> peripherals and the DMA engine channels themselves (what do you think
> the "request index" which you have to program into DMA channel control
> registers is doing...
Ok.
> We support this external mux today in the PL080 driver - and we do that
> by having the PL080 driver do the scheduling of virtual DMA channels on
> the actual hardware itself. The PL080 driver has knowledge that there
> may be some sort of additional muxing layer between it and the
> peripheral.
>
> As the APIs stand today, you just can't do this without having the
> DMA engine driver itself intimately involved because a layer above
> doesn't really have much clue as to what's going on, and the DMA
> engine stuff itself doesn't layer particularly well.
If the pl080 driver already has code for the mux in it, then it should
handle both of_dma_controller instances in my example. It would
not change anything regarding the binding, which just describes the
way that the hardware is connected. I have not looked at the implementation
of the pl080 driver, but I'd assume we could get away with just having
two separate xlate() functions. It's slightly ugly to have one driver
take responsibility for two device_node:s, but it's not unheard of.
In the probe function for the pl080 node, the driver can walk the
entire device tree to find any mux devices connected to it and
register an of_dma_controller() with its xlate function for those.
Unless you see another issue with this, I'd assume it's all covered
by the new interface, but it also doesn't get better than what we
have today.
Arnd
^ permalink raw reply
* [PATCH] mailbox: prevent pl320-ipc code from breaking none-AMBA systems
From: Mark Langsdorf @ 2013-01-29 16:36 UTC (permalink / raw)
To: linux-arm-kernel
The pl320-ipc code depends on ARM AMBA, and should have the dependency
in its Kconfig.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
---
drivers/mailbox/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 9489554..9545c9f 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -8,6 +8,7 @@ menuconfig MAILBOX
if MAILBOX
config PL320_MBOX
bool "ARM PL320 Mailbox"
+ depends on ARM_AMBA
help
An implementation of the ARM PL320 Interprocessor Communication
Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
--
1.7.11.7
^ permalink raw reply related
* [PATCH 2/2] clk: tegra: adapt tegra periph clk to mux table/mask
From: Stephen Warren @ 2013-01-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130129095158.GS4118@tbergstrom-lnx.Nvidia.com>
On 01/29/2013 02:51 AM, Peter De Schrijver wrote:
> On Mon, Jan 28, 2013 at 05:49:53PM +0100, Stephen Warren wrote:
>> On 01/28/2013 08:54 AM, Peter De Schrijver wrote:
>>> The tegra peripheral clock type uses struct clk_mux directly, so it needs to
>>> be updated to handle the new mask and table fields. Also the macros need
>>> to be updated
>>
>> Just a quick note on patch dependencies here:
>>
>> Patch 1/2 can presumably be taken through the clk tree whenever Mike is
>> OK with it.
>>
>> Patch 2/2 depends on patches in the Tegra tree for 3.9. Since patch 2/2
>> is useful mostly for the Tegra114 clock driver, and I don't imagine that
>> will get posted/merged in time for 3.9, it's probably easiest to just
>> take patch 2/2 for 3.10 along with the Tegra114 clock driver. Also, I
>> imagine there won't be any more clk/Tegra tree dependencies in 3.10, so
>> patch 2/2 and the Tegra114 clk driver patches can likely go through the
>> clk tree itself for 3.10.
>
> No. Because 1/2 changes struct clk_mux and the tegra peripheral clock type
> uses struct clk_mux directly, 2/2 needs to be applied together with 1/2, even
> if the new functionality is not yet used.
Oh, then they can't be two separate patches then, or "git bisect" won't
work. I guess it's best to wait for 3.10 for this:-(
^ permalink raw reply
* [BUG] i.MX25: soft lockups/freezes while getnstimeofday
From: Fabio Estevam @ 2013-01-29 16:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130129161230.GA3128@pengutronix.de>
Hi Steffen,
On Tue, Jan 29, 2013 at 2:12 PM, Steffen Trumtrar
<s.trumtrar@pengutronix.de> wrote:
> The board itself supposedly worked up until v3.4.
>
> The mxc-timer is set up to use ipg_clk_highfreq with a per5_div set to 2,
> therefore it is clocked with 120MHz. I tried to set the per5_div to 4 to have
> a 60MHz clock, but this didn't change anything.
> On the other hand, I tried parenting the ipg_clk to the per5_clk to get a
> 66MHz clock. This seems to be working fine, but I only have it running for 4h now.
Can you dump the clock tree in 3.4 and 3.7.2, so that we can compare them?
Just looked at the FSL BSP and they have the following:
/* GPT clock must be derived from AHB clock */
clk_set_rate(&per_clk[5], ahb_clk.rate / 10);
Regards,
Fabio Estevam
^ permalink raw reply
* i.Mx6Quad - eth0: tx queue full!
From: Fabio Estevam @ 2013-01-29 16:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5107F9DB.2000402@gmail.com>
On Tue, Jan 29, 2013 at 2:33 PM, Vikram Narayanan <vikram186@gmail.com> wrote:
> I tried with both the kernels. Freescale's and mainline results in the same
> error.
Do you also see this issue with a 3.6 or 3.7 stable kernels?
^ permalink raw reply
* [PATCH v2 05/27] arm: pci: add a align_resource hook
From: Arnd Bergmann @ 2013-01-29 16:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130129172055.0ca5f341@skate>
On Tuesday 29 January 2013, Thomas Petazzoni wrote:
> And the Linux PCI resource allocation code complies with this, so that
> if I have two PCI-to-PCI bridges (each having downstream a device with
> an I/O BAR), then the first PCI-to-PCI bridge gets its I/O base address
> register set to ADDR + 0x0, and the second bridge gets its I/O base
> address set to ADDR + 0x1000. And this doesn't play well with the
> requirements of Marvell address decoding windows for PCIe I/O regions,
> which must be 64 KB aligned.
But we normally only assign a 64 KB I/O window to each PCI host bridge.
Requiring PCI bridges to be space 64 KB apart would mean that we cannot
actually support bridges at all.
Is this just about your "virtual" bridges? If each one has its
own 64 KB I/O range and its own configuration space, that sounds
a lot like you should make them appear as individual domains instead.
Arnd
^ permalink raw reply
* [PATCH 5/5] mv643xx_eth: convert to use the Marvell Orion MDIO driver
From: Thomas Petazzoni @ 2013-01-29 16:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5107F88C.8030002@openwrt.org>
Dear Florian Fainelli,
On Tue, 29 Jan 2013 17:27:56 +0100, Florian Fainelli wrote:
> It looks like I introduced two redundant mvmdio instances as ge01
> refers to the ge00 smi bus (the same applies to ge11 and ge10).
> Thanks for spotting this.
Ok, good.
> If you take a closer look at mv643xx_eth you will see that the
> "shared" driver still handles the mconf bus window configuration,
> which is not abstracted yet.
Indeed, I've seen that. But I don't understand why it's done in the
mv643xx_eth_shared_probe(). The mbus window configuration registers are
per-network interface, so this call to mv643xx_eth_conf_mbus_windows()
could presumably be done in mv643xx_eth_probe().
At least in mvneta, we have the same registers, and we do their
initialization in the driver normal (and only) ->probe() routine.
> Besides that, I would rather do it step by step.
Yes, agreed. But I think it would be good to have followed patches that
progressively get rid of the shared driver thing, as it will help in
bringing a proper DT binding in the mv643xx_eth driver. But it
certainly doesn't need to be part of this specific patch.
Thanks,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [RFC] arm: use built-in byte swap function
From: Woodhouse, David @ 2013-01-29 16:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130129083522.GA14302@pd.tnic>
On Tue, 2013-01-29 at 09:35 +0100, Borislav Petkov wrote:
>
> >
> > #ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
> > -#if GCC_VERSION >= 40400
> > +#if (!defined(__arm__) && GCC_VERSION >= 40400) || \
> > + (defined(__arm__) && GCC_VERSION >= 40600)
>
> There should be no arch-specific stuff in a generic header. I guess
> you probably need to select ARCH_USE_BUILTIN_BSWAP in an arm-specific
> compiler.h header after checking compiler version...
If we're really going to have many different architectures depending on
different versions of GCC for this (if it wasn't sane to use it from
4.4/4.8 when it got introduced, and depends on some later arch-specific
optimisation), then perhaps we'll have the arch provide the
corresponding required GCC_VERSION for using each of 64/32/16 bit
builtins, instead of just a yes/no flag? Or just define
__HAVE_BUILTIN_BSWAPxx__ for itself, perhaps?
In fact we could start by having just the problematic architectures set
__HAVE_BUILTIN_BSWAPxx__ for themselves according to whatever criteria
they want, and then if there's scope for consolidating that in the
generic code then we can do so later.
--
Sent with MeeGo's ActiveSync support.
David Woodhouse Open Source Technology Centre
David.Woodhouse at intel.com Intel Corporation
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^ permalink raw reply
* [GIT PULL] CSR SiRFmarco SoC infrastructures for 3.9
From: Olof Johansson @ 2013-01-29 16:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGsJ_4yV5KJ2yWQtbOLO5Dj_MrQS3v0sPN4hinJAzTsfH6quvg@mail.gmail.com>
On Mon, Jan 28, 2013 at 06:08:27PM +0800, Barry Song wrote:
> 2013/1/28 Olof Johansson <olof@lixom.net>:
> > On Thu, Jan 24, 2013 at 11:21:02AM +0800, Barry Song wrote:
> >> Hi Olof, Arnd,
> >>
> >> pls pull the following changes for CSR SiRFmarco SoC. it has been
> >> rebased againest arm-soc timer/cleanup tree.
> >>
> >> since commit 90cf214d6a549bf482e3c5751ee256cc885b96ea:
> >>
> >> ARM: at91: fix board-rm9200-dt after sys_timer conversion
> >> (2013-01-14 10:14:04 -0800)
> >>
> >> are available in the git repository at:
> >> git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel.git
> >> marco-timer-cleanup-rebase
> >
> > Pulled in as prima2/marco, included in next/soc. Thanks!
>
> Olof, thanks.
>
> >
> > I noticed that there is no defconfig for any mach-prima2 platforms. Feel
> > free to submit one so we get build coverage of the platform.
>
> there have been. arch/arm/configs/prima2_defconfig
Ah, it enables ARCH_SIRF, I was searching for ARCH_PRIMA2 or ARCH_MARCO. Good.
-Olof
^ permalink raw reply
* [GIT PULL] Renesas pinmux for v3.9
From: Olof Johansson @ 2013-01-29 16:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359080696-31489-1-git-send-email-horms+renesas@verge.net.au>
On Fri, Jan 25, 2013 at 11:23:36AM +0900, Simon Horman wrote:
> Hi Olof, Hi Arnd,
>
> please consider the following pinmux enhancements for 3.9.
>
> As discussed previously this series includes changes for shmobile (ARM
> based SoC), the SH architecture and pinmux. It has been agreed by the
> maintainers, Paul Mundt, Linus Walleij and myself in conjunction with the
> patch-series author Laurent Pinchart and arm-soc co-maintainer Olof
> Johansson to take this seies through my renesas tree and thus the arm-soc
> tree as a single branch to avoid a complex set of branch dependencies.
>
> These changes have been sitting in next for several weeks now.
>
> I expect there to be a follow-up series of similar complexity
> in the 3.10 time-frame. A focus of that series being to add DT bindings.
>
> ----------------------------------------------------------------
> The following changes since commit 9931faca02c604c22335f5a935a501bb2ace6e20:
>
> Linux 3.8-rc3 (2013-01-09 18:59:55 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git pfc
This will go in through a next/sh-pinmux branch on its own given the
size of the branch. It's been pulled and merged in with for-next.
Thanks!
-Olof
^ permalink raw reply
* [GIT PULL] Renesas ARM-based SoC defconfig for v3.9 #2
From: Olof Johansson @ 2013-01-29 17:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359079374-25032-1-git-send-email-horms+renesas@verge.net.au>
On Fri, Jan 25, 2013 at 11:02:52AM +0900, Simon Horman wrote:
> Hi Olof, Hi Arnd,
>
> please consider the following defconfig enhancements for 3.9.
>
> This series is based on the renesas/defconfig branch in the arm-soc tree.
>
> ----------------------------------------------------------------
> The following changes since commit 8098df15c26b2bf16924df5a134d1a649692ab62:
>
> ARM: mach-shmobile: kzm9d: update defconfig (2013-01-15 08:57:09 +0900)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git defconfig2
Thanks, pulled on top of previous defconfig branch.
-Olof
^ permalink raw reply
* [GIT PULL] Renesas ARM-based SoC boards for v3.9
From: Olof Johansson @ 2013-01-29 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359080253-30995-1-git-send-email-horms+renesas@verge.net.au>
On Fri, Jan 25, 2013 at 11:17:26AM +0900, Simon Horman wrote:
> Hi Olof, Hi Arnd,
>
> please consider the following board enhancements for 3.9.
>
> ----------------------------------------------------------------
> The following changes since commit 9931faca02c604c22335f5a935a501bb2ace6e20:
>
> Linux 3.8-rc3 (2013-01-09 18:59:55 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git boards
Pulled, thanks.
-Olof
^ permalink raw reply
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