* [PATCH 2/4] pinctrl/abx500: replace incorrect return value
From: Linus Walleij @ 2013-01-30 19:40 UTC (permalink / raw)
To: linux-arm-kernel
From: Lee Jones <lee.jones@linaro.org>
Currently in the empty abx500_pin_config_get() function, we're
returning -EINVAL, with a comment stating that the reason for the
failure is that the function isn't implemented yet. Well there's
a proper return code for that. If we use it, we can do away with
the comment too, as it would be implied.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/pinctrl-abx500.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
index 539c9bb..305a9cb 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -971,8 +971,7 @@ int abx500_pin_config_get(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *config)
{
- /* Not implemented */
- return -EINVAL;
+ return -ENOSYS;
}
int abx500_pin_config_set(struct pinctrl_dev *pctldev,
--
1.7.11.3
^ permalink raw reply related
* [PATCH 3/4] pinctrl/abx500: beautify the ABX500 pin control driver
From: Linus Walleij @ 2013-01-30 19:40 UTC (permalink / raw)
To: linux-arm-kernel
From: Lee Jones <lee.jones@linaro.org>
This patch provides some superficial changes to the driver to
aid with readability and maintainability. We're mostly fixing
things like white-space errors, spreading out code which as
been clumped together impeding readability and comment layout,
such as using the new "/**" comment start for function headers
etc. No code semantics were harmed in the making of this patch.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/pinctrl-abx500.c | 94 +++++++++++++++++++++++++---------------
1 file changed, 59 insertions(+), 35 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
index 305a9cb..426b47c 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -127,7 +127,7 @@ static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip)
}
static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
- unsigned offset, bool *bit)
+ unsigned offset, bool *bit)
{
struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
u8 pos = offset % 8;
@@ -149,7 +149,7 @@ static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
}
static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
- unsigned offset, int val)
+ unsigned offset, int val)
{
struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
u8 pos = offset % 8;
@@ -160,12 +160,14 @@ static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
AB8500_MISC, reg, BIT(pos), val << pos);
if (ret < 0)
dev_err(pct->dev, "%s write failed\n", __func__);
+
return ret;
}
+
/**
* abx500_gpio_get() - Get the particular GPIO value
- * @chip: Gpio device
- * @offset: GPIO number to read
+ * @chip: Gpio device
+ * @offset: GPIO number to read
*/
static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
{
@@ -179,6 +181,7 @@ static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
dev_err(pct->dev, "%s failed\n", __func__);
return ret;
}
+
return bit;
}
@@ -193,7 +196,7 @@ static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
}
static int abx500_config_pull_updown(struct abx500_pinctrl *pct,
- int offset, enum abx500_gpio_pull_updown val)
+ int offset, enum abx500_gpio_pull_updown val)
{
u8 pos;
int ret;
@@ -223,6 +226,7 @@ static int abx500_config_pull_updown(struct abx500_pinctrl *pct,
out:
if (ret < 0)
dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
+
return ret;
}
@@ -234,6 +238,7 @@ static int abx500_gpio_direction_output(struct gpio_chip *chip,
struct pullud *pullud = pct->soc->pullud;
unsigned gpio;
int ret;
+
/* set direction as output */
ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
if (ret < 0)
@@ -253,6 +258,7 @@ static int abx500_gpio_direction_output(struct gpio_chip *chip,
if (ret < 0)
return ret;
}
+
/* set the output as 1 or 0 */
return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
}
@@ -284,13 +290,14 @@ static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
}
static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
- unsigned gpio, int alt_setting)
+ unsigned gpio, int alt_setting)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
struct alternate_functions af = pct->soc->alternate_functions[gpio];
int ret;
int val;
unsigned offset;
+
const char *modes[] = {
[ABX500_DEFAULT] = "default",
[ABX500_ALT_A] = "altA",
@@ -309,6 +316,7 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
/* on ABx5xx, there is no GPIO0, so adjust the offset */
offset = gpio - 1;
+
switch (alt_setting) {
case ABX500_DEFAULT:
/*
@@ -324,6 +332,7 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
offset, val);
break;
+
case ABX500_ALT_A:
/*
* for ABx5xx family, alt_a mode is always selected by
@@ -348,6 +357,7 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
offset, 1);
break;
+
case ABX500_ALT_B:
ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
offset, 0);
@@ -359,6 +369,7 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
af.alt_bit2,
!!(af.altb_val && BIT(1)));
break;
+
case ABX500_ALT_C:
ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
offset, 0);
@@ -370,13 +381,15 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
default:
dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting);
+
return -EINVAL;
}
+
return ret;
}
static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
- unsigned gpio)
+ unsigned gpio)
{
u8 mode;
bool bit_mode;
@@ -404,6 +417,7 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
"alt_bitX value not in correct range (-1 to 7)\n");
return -EINVAL;
}
+
/* if alt_bit2 is used, alt_bit1 must be used too */
if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
dev_err(pct->dev,
@@ -420,6 +434,7 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
*/
if (mode)
return ABX500_DEFAULT;
+
/*
* pin use the AlternatFunction register
* read alt_bit1 value
@@ -448,8 +463,9 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
#include <linux/seq_file.h>
static void abx500_gpio_dbg_show_one(struct seq_file *s,
- struct pinctrl_dev *pctldev, struct gpio_chip *chip,
- unsigned offset, unsigned gpio)
+ struct pinctrl_dev *pctldev,
+ struct gpio_chip *chip,
+ unsigned offset, unsigned gpio)
{
struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
const char *label = gpiochip_is_requested(chip, offset - 1);
@@ -457,6 +473,7 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s,
int mode = -1;
bool is_out;
bool pull;
+
const char *modes[] = {
[ABX500_DEFAULT] = "default",
[ABX500_ALT_A] = "altA",
@@ -516,9 +533,9 @@ static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
#else
static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
- struct pinctrl_dev *pctldev,
- struct gpio_chip *chip,
- unsigned offset, unsigned gpio)
+ struct pinctrl_dev *pctldev,
+ struct gpio_chip *chip,
+ unsigned offset, unsigned gpio)
{
}
#define abx500_gpio_dbg_show NULL
@@ -780,9 +797,9 @@ static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
}
static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
- unsigned function,
- const char * const **groups,
- unsigned * const num_groups)
+ unsigned function,
+ const char * const **groups,
+ unsigned * const num_groups)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
@@ -830,7 +847,7 @@ static void abx500_disable_lazy_irq(struct gpio_chip *chip, unsigned gpio)
}
static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
- unsigned group)
+ unsigned group)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
struct gpio_chip *chip = &pct->chip;
@@ -851,11 +868,12 @@ static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
abx500_disable_lazy_irq(chip, g->pins[i]);
ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
}
+
return ret;
}
static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
- unsigned function, unsigned group)
+ unsigned function, unsigned group)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
const struct abx500_pingroup *g;
@@ -869,8 +887,8 @@ static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
}
int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned offset)
+ struct pinctrl_gpio_range *range,
+ unsigned offset)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
const struct abx500_pinrange *p;
@@ -908,8 +926,8 @@ int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
}
static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned offset)
+ struct pinctrl_gpio_range *range,
+ unsigned offset)
{
}
@@ -931,7 +949,7 @@ static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
}
static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
- unsigned selector)
+ unsigned selector)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
@@ -939,19 +957,20 @@ static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
}
static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
- unsigned selector,
- const unsigned **pins,
- unsigned *num_pins)
+ unsigned selector,
+ const unsigned **pins,
+ unsigned *num_pins)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
*pins = pct->soc->groups[selector].pins;
*num_pins = pct->soc->groups[selector].npins;
+
return 0;
}
static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned offset)
+ struct seq_file *s, unsigned offset)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
struct gpio_chip *chip = &pct->chip;
@@ -968,15 +987,15 @@ static struct pinctrl_ops abx500_pinctrl_ops = {
};
int abx500_pin_config_get(struct pinctrl_dev *pctldev,
- unsigned pin,
- unsigned long *config)
+ unsigned pin,
+ unsigned long *config)
{
return -ENOSYS;
}
int abx500_pin_config_set(struct pinctrl_dev *pctldev,
- unsigned pin,
- unsigned long config)
+ unsigned pin,
+ unsigned long config)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
struct pullud *pullud = pct->soc->pullud;
@@ -990,6 +1009,7 @@ int abx500_pin_config_set(struct pinctrl_dev *pctldev,
pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
(param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") :
(argument ? "pull up" : "pull down"));
+
/* on ABx500, there is no GPIO0, so adjust the offset */
offset = pin - 1;
@@ -1018,13 +1038,18 @@ int abx500_pin_config_set(struct pinctrl_dev *pctldev,
ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
offset, argument ? 0 : 1);
break;
+
case PIN_CONFIG_OUTPUT:
ret = abx500_gpio_direction_output(chip, offset, argument);
+
break;
+
default:
dev_err(chip->dev, "illegal configuration requested\n");
+
return -EINVAL;
}
+
return ret;
}
@@ -1090,7 +1115,7 @@ static int abx500_gpio_probe(struct platform_device *pdev)
int i;
pdata = abx500_pdata->gpio;
- if (!pdata) {
+ if (!pdata) {
dev_err(&pdev->dev, "gpio platform data missing\n");
return -ENODEV;
}
@@ -1150,8 +1175,7 @@ static int abx500_gpio_probe(struct platform_device *pdev)
goto out_free;
ret = gpiochip_add(&pct->chip);
if (ret) {
- dev_err(&pdev->dev, "unable to add gpiochip: %d\n",
- ret);
+ dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
goto out_rem_irq;
}
dev_info(&pdev->dev, "added gpiochip\n");
@@ -1193,9 +1217,9 @@ out_free:
return ret;
}
-/*
+/**
* abx500_gpio_remove() - remove Ab8500-gpio driver
- * @pdev : Platform device registered
+ * @pdev: Platform device registered
*/
static int abx500_gpio_remove(struct platform_device *pdev)
{
--
1.7.11.3
^ permalink raw reply related
* [PATCH 4/4] pinctrl/abx500: destroy mutex if returning early due to error
From: Linus Walleij @ 2013-01-30 19:40 UTC (permalink / raw)
To: linux-arm-kernel
From: Lee Jones <lee.jones@linaro.org>
Current failure path neglects to mutex_destroy() before returning
an error due to an invalid parameter or an error received from
gpiochip_add(). This patch aims to remedy that behaviour.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/pinctrl-abx500.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
index 426b47c..81ef515 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -1155,11 +1155,13 @@ static int abx500_gpio_probe(struct platform_device *pdev)
default:
dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n",
(int) platid->driver_data);
+ mutex_destroy(&pct->lock);
return -EINVAL;
}
if (!pct->soc) {
dev_err(&pdev->dev, "Invalid SOC data\n");
+ mutex_destroy(&pct->lock);
return -EINVAL;
}
@@ -1176,6 +1178,7 @@ static int abx500_gpio_probe(struct platform_device *pdev)
ret = gpiochip_add(&pct->chip);
if (ret) {
dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
+ mutex_destroy(&pct->lock);
goto out_rem_irq;
}
dev_info(&pdev->dev, "added gpiochip\n");
--
1.7.11.3
^ permalink raw reply related
* [PATCH v2 0/5] arm: mvebu: add support for local timer for Armada 370/XP
From: Jason Cooper @ 2013-01-30 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359135165-32108-1-git-send-email-gregory.clement@free-electrons.com>
Thomas Gleixner, John Stultz,
I'm getting close to pulling this series in through arm-soc. Would you
prefer to take the clocksource patches through your tree, or provide an
Acked-by and I can take them through mvebu/arm-soc?
I'm comfortable with either, if you decide to take them, please let me
know which tree and branch you put them in so I can properly depend on
them.
thx,
Jason.
On Fri, Jan 25, 2013 at 06:32:40PM +0100, Gregory CLEMENT wrote:
> Hello,
>
> The Armada XP SoCs comes with private timers. This allows us to use
> local timers through CONFIG_LOCAL_TIMERS and as stated in the kconfig
> help, it prevents a "thundering herd" at every timer tick.
>
> Armada 370 also have these private timers, and even if it comes only
> with a single CPU, the feature is also enabled for this SoC to keep
> the code generic.
>
> In order to be able to use the local timer, I also had to add the
> support for the per-CPU interrupts.
>
> There are not many changes since the first version (see the changelog
> below), I hope it means that everybody is happy with this patch
> set. If it is, so please could you give your acked-by. I especially
> expect the acked-by from John Stultz then I will feel more comfortable
> to ask Jason to pull it.
>
> This patch set is based on 3.8-rc4 and is obviously 3.9 material. The
> git branch called local_timer is available at:
> https://github.com/MISL-EBU-System-SW/mainline-public.git.
>
> Thanks,
>
> Changelog:
> V1->V2:
> - Fixed unneeded empty line and wrong indentation.
> - Made percpu_armada_370_xp_evt a static variable
> - Removed the patch "arm: kconfig: don't select TWD with local timer
> for Armada 370/XP" from the series. There is still some improvement
> possible in this area, but this patch set not depends on it.
>
> Gregory CLEMENT (5):
> arm: mvebu: Add support for local interrupt
> clocksource: time-armada-370-xp: add local timer support
> arm: mvebu: update defconfig with local timer support
> arm: mvebu: update DT to support local timers
> clocksource: update and move armada-370-xp-timer documentation to
> timer directory
>
> .../bindings/arm/armada-370-xp-timer.txt | 12 --
> .../bindings/timer/marvell,armada-370-xp-timer.txt | 15 ++
> arch/arm/boot/dts/armada-370-xp.dtsi | 5 +-
> arch/arm/configs/mvebu_defconfig | 1 -
> arch/arm/mach-mvebu/irq-armada-370-xp.c | 15 +-
> drivers/clocksource/time-armada-370-xp.c | 150 +++++++++++++++-----
> 6 files changed, 141 insertions(+), 57 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt
> create mode 100644 Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
>
> --
> 1.7.9.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 1/1] drivers: net: davinci_cpdma: acknowledge interrupt properly
From: Mugunthan V N @ 2013-01-30 19:56 UTC (permalink / raw)
To: linux-arm-kernel
CPDMA interrupts are not properly acknowledged which leads to interrupt
storm, only cpdma interrupt 0 is acknowledged in Davinci CPDMA driver.
Changed cpdma_ctlr_eoi api to acknowledge 1 and 2 interrupts which are
used for rx and tx respectively.
Reported-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
drivers/net/ethernet/ti/davinci_cpdma.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c b/drivers/net/ethernet/ti/davinci_cpdma.c
index f862918..afe14a6 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.c
+++ b/drivers/net/ethernet/ti/davinci_cpdma.c
@@ -487,6 +487,8 @@ int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr)
{
dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 0);
+ dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 1);
+ dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 2);
}
struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/1] drivers: net: davinci_cpdma: acknowledge interrupt properly
From: Koen Kooi @ 2013-01-30 20:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359575813-15703-1-git-send-email-mugunthanvnm@ti.com>
Op 30 jan. 2013, om 20:56 heeft Mugunthan V N <mugunthanvnm@ti.com> het volgende geschreven:
> CPDMA interrupts are not properly acknowledged which leads to interrupt
> storm, only cpdma interrupt 0 is acknowledged in Davinci CPDMA driver.
> Changed cpdma_ctlr_eoi api to acknowledge 1 and 2 interrupts which are
> used for rx and tx respectively.
A brief inspection shows that this still isn't following the TRM, but Pantelis' patch does. Can you please fix this driver to follow the TRM and make it work on both PG1.0 and PG2.0 instead of papering over bugs instead of fixing them properly?
^ permalink raw reply
* [PATCH 4/4] pinctrl/abx500: destroy mutex if returning early due to error
From: Stephen Warren @ 2013-01-30 20:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359574822-15729-1-git-send-email-linus.walleij@stericsson.com>
On 01/30/2013 12:40 PM, Linus Walleij wrote:
> From: Lee Jones <lee.jones@linaro.org>
>
> Current failure path neglects to mutex_destroy() before returning
> an error due to an invalid parameter or an error received from
> gpiochip_add(). This patch aims to remedy that behaviour.
> diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
> @@ -1155,11 +1155,13 @@ static int abx500_gpio_probe(struct platform_device *pdev)
> default:
> dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n",
> (int) platid->driver_data);
> + mutex_destroy(&pct->lock);
> return -EINVAL;
Especially given there's already a label out_free which performs this
mutex_destroy(), those last two lines would be better as:
ret = -EINVAL;
goto out_free;
> }
>
> if (!pct->soc) {
> dev_err(&pdev->dev, "Invalid SOC data\n");
> + mutex_destroy(&pct->lock);
> return -EINVAL;
Same there.
> }
>
> @@ -1176,6 +1178,7 @@ static int abx500_gpio_probe(struct platform_device *pdev)
> ret = gpiochip_add(&pct->chip);
> if (ret) {
> dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
> + mutex_destroy(&pct->lock);
> goto out_rem_irq;
And here, just change the goto target to out_free rather than adding the
mutex_destroy() call.
^ permalink raw reply
* [PATCH v2 2/2] ARM: kirkwood: fix to retain gbe MAC addresses for DT kernels
From: Sebastian Hesselbarth @ 2013-01-30 20:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130130183049.GR7717@titan.lakedaemon.net>
The ethernet controller used on kirkwood looses its MAC address
register contents when the corresponding clock is gated. As soon as
mv643xx_eth is built as module, the clock gets gated and when loading
the module, the MAC address is gone.
Proper DT support for the mv643xx_eth driver is expected soon, so we add
a workaround to always enable ge0/ge1 clocks on kirkwood. This workaround
is also already used on non-DT kirkwood kernels.
Reported-by: Simon Baatz <gmbnomis@gmail.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
[v2]
- add note in patch description that MAC address is lost only when using
modular driver
- add note in patch description that the workaround will be removed soon
Cc: Simon Baatz <gmbnomis@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
arch/arm/mach-kirkwood/board-dt.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index de4fd2b..e714ead 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -41,16 +41,12 @@ static void __init kirkwood_legacy_clk_init(void)
struct device_node *np = of_find_compatible_node(
NULL, NULL, "marvell,kirkwood-gating-clock");
-
struct of_phandle_args clkspec;
+ struct clk *clk;
clkspec.np = np;
clkspec.args_count = 1;
- clkspec.args[0] = CGC_BIT_GE0;
- orion_clkdev_add(NULL, "mv643xx_eth_port.0",
- of_clk_get_from_provider(&clkspec));
-
clkspec.args[0] = CGC_BIT_PEX0;
orion_clkdev_add("0", "pcie",
of_clk_get_from_provider(&clkspec));
@@ -63,14 +59,24 @@ static void __init kirkwood_legacy_clk_init(void)
orion_clkdev_add("1", "pcie",
of_clk_get_from_provider(&clkspec));
- clkspec.args[0] = CGC_BIT_GE1;
- orion_clkdev_add(NULL, "mv643xx_eth_port.1",
- of_clk_get_from_provider(&clkspec));
-
clkspec.args[0] = CGC_BIT_SDIO;
orion_clkdev_add(NULL, "mvsdio",
of_clk_get_from_provider(&clkspec));
+ /*
+ * The ethernet interfaces forget the MAC address assigned by
+ * u-boot if the clocks are turned off. Until proper DT support
+ * is available we always enable them for now.
+ */
+ clkspec.args[0] = CGC_BIT_GE0;
+ clk = of_clk_get_from_provider(&clkspec);
+ orion_clkdev_add(NULL, "mv643xx_eth_port.0", clk);
+ clk_prepare_enable(clk);
+
+ clkspec.args[0] = CGC_BIT_GE1;
+ clk = of_clk_get_from_provider(&clkspec);
+ orion_clkdev_add(NULL, "mv643xx_eth_port.1", clk);
+ clk_prepare_enable(clk);
}
static void __init kirkwood_of_clk_init(void)
--
1.7.10.4
^ permalink raw reply related
* Commit 384a290283fde63ba8dc671fca5420111cdac19a seems to break 11MPCore boot
From: Russell King - ARM Linux @ 2013-01-30 20:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1301301223290.6300@xanadu.home>
On Wed, Jan 30, 2013 at 12:30:06PM -0500, Nicolas Pitre wrote:
> On Wed, 30 Jan 2013, Russell King - ARM Linux wrote:
>
> > On Wed, Jan 30, 2013 at 04:45:35PM +0000, Russell King - ARM Linux wrote:
> > > What we could do is scan interrupts 0-31 for a non-zero value. If they're
> > > all zero, we should complain. Otherwise, we use the first non-zero value
> > > we find and validate it for a single bit set.
> >
> > And here's a patch to do this - I've not run this but it's just built
> > successfully here. Anyone want to give it a go?
> >
> > I've decided that if we do hit the mask==0 case, we should just wail
> > loudly - panic'ing will bring the kernel to a halt right there and then,
> > which may be before any console drivers have been initialized (and the
> > kernel message buffer is no longer easy to read). Moreover, panic()ing,
> > along with the possibility of rebooting won't really fix this kind of
> > error - it's rather fatal as far as that goes. So, I think just wailing
> > at CRIT level is fine for this condition that should not occur.
> >
> > arch/arm/common/gic.c | 23 +++++++++++++++++++++--
> > 1 files changed, 21 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
> > index 36ae03a..3bcef49 100644
> > --- a/arch/arm/common/gic.c
> > +++ b/arch/arm/common/gic.c
> > @@ -351,6 +351,23 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
> > irq_set_chained_handler(irq, gic_handle_cascade_irq);
> > }
> >
> > +static u8 gic_get_cpumask(struct gic_chip_data *gic)
> > +{
> > + void __iomem *base = gic_data_dist_base(gic);
> > + u8 mask, i;
> > +
> > + for (i = mask = 0; i < 32; i++) {
> > + mask = readl_relaxed(base + GIC_DIST_TARGET + i);
> > + if (mask)
> > + break;
> > + }
>
> That should probably be:
>
> u32 mask;
>
> for (i = 0; i < 32; i += 4) {
> mask = readl_relaxed(base + GIC_DIST_TARGET + i);
> mask |= (mask >> 16);
> mask |= (mask >> 8);
> if (mask)
> return mask;
> }
>
> I know that the spec says that the GIC should accept byte sized
> accesses, but that too is known not to work on all implementations.
Right... this is what my current set of patches to make things work
again looks like... and still there's more problems to go...
arch/arm/common/gic.c | 25 +++++++++++++++++++++++--
arch/arm/mach-realview/include/mach/irqs-eb.h | 2 +-
arch/arm/mm/dma-mapping.c | 2 +-
drivers/dma/amba-pl08x.c | 2 ++
4 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 36ae03a..87dfa90 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -351,6 +351,25 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
irq_set_chained_handler(irq, gic_handle_cascade_irq);
}
+static u8 gic_get_cpumask(struct gic_chip_data *gic)
+{
+ void __iomem *base = gic_data_dist_base(gic);
+ u32 mask, i;
+
+ for (i = mask = 0; i < 32; i += 4) {
+ mask = readl_relaxed(base + GIC_DIST_TARGET + i);
+ mask |= mask >> 16;
+ mask |= mask >> 8;
+ if (mask)
+ break;
+ }
+
+ if (!mask)
+ pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
+
+ return mask;
+}
+
static void __init gic_dist_init(struct gic_chip_data *gic)
{
unsigned int i;
@@ -369,7 +388,9 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
/*
* Set all global interrupts to this CPU only.
*/
- cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0);
+ cpumask = gic_get_cpumask(gic);
+ cpumask |= cpumask << 8;
+ cpumask |= cpumask << 16;
for (i = 32; i < gic_irqs; i += 4)
writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
@@ -400,7 +421,7 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
* Get what the GIC says our CPU mask is.
*/
BUG_ON(cpu >= NR_GIC_CPU_IF);
- cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);
+ cpu_mask = gic_get_cpumask(gic);
gic_cpu_map[cpu] = cpu_mask;
/*
diff --git a/arch/arm/mach-realview/include/mach/irqs-eb.h b/arch/arm/mach-realview/include/mach/irqs-eb.h
index d6b5073..4475423 100644
--- a/arch/arm/mach-realview/include/mach/irqs-eb.h
+++ b/arch/arm/mach-realview/include/mach/irqs-eb.h
@@ -115,7 +115,7 @@
/*
* Only define NR_IRQS if less than NR_IRQS_EB
*/
-#define NR_IRQS_EB (IRQ_EB_GIC_START + 96)
+#define NR_IRQS_EB (IRQ_EB_GIC_START + 128)
#if defined(CONFIG_MACH_REALVIEW_EB) \
&& (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 076c26d..dda3904 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -640,7 +640,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
if (is_coherent || nommu())
addr = __alloc_simple_buffer(dev, size, gfp, &page);
- else if (gfp & GFP_ATOMIC)
+ else if (!(gfp & __GFP_WAIT))
addr = __alloc_from_pool(size, &page);
else if (!IS_ENABLED(CONFIG_CMA))
addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 7d1f24f..7b1f3b2 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -1690,7 +1690,9 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
static void pl08x_timer(unsigned long data)
{
struct pl08x_driver_data *pl08x = (struct pl08x_driver_data *)data;
+ local_irq_disable();
pl08x_irq(pl08x->adev->irq[0], pl08x);
+ local_irq_enable();
mod_timer(&pl08x->timer, jiffies + 2);
}
^ permalink raw reply related
* [RFC PATCH v3 1/2] ARM: kernel: update cpuinfo to print SoC model name
From: Matt Sealey @ 2013-01-30 20:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1301301402330.6300@xanadu.home>
On Wed, Jan 30, 2013 at 1:07 PM, Nicolas Pitre <nico@fluxnic.net> wrote:
> On Wed, 30 Jan 2013, Ruslan Bilovol wrote:
>
>> Currently, reading /proc/cpuinfo provides userspace with CPU ID of
>> the CPU carrying out the read from the file.
>> Userspace using this information may decide what module
>> to load or how to configure some specific (and processor-depended)
>> settings or so.
>> However, since really different SoCs can share same ARM core,
>> this information currently is not so useful.
>> For example, TI OMAP4460 and OMAP4470 SoCs show the same
>> information in the /proc/cpuinfo whereas they are different.
>> Since in most cases ARM CPU is a part of some system on a chip (SoC),
>> the "cpuinfo" file looks like exactly that place, where this
>> information have to be displayed.
>>
>> So added new line "SoC name" in the "cpuinfo" output for system
>> on a chip name. It is placed between CPU information and machine
>> information, so the file structure looks gracefully (CPU-SoC-Hardware)
>>
>> Example:
>>
>> / # cat proc/cpuinfo
>> [...]
>> CPU variant : 0x2
>> CPU part : 0xc09
>> CPU revision : 10
>>
>> SoC name : OMAP4470
>>
>> Hardware : OMAP4 Blaze Tablet
>
> Please remove that extra blank line between "SoC name" and "Hardware".
> The blank line after "CPU revision" is fine.
>
> Also, please rename this to "System name". Not all systems are "on
> chip". By using "System name" this is more universally useful.
I can't agree with "System name", it is confusing in common
terminology since it's about the same definition as the current
"Hardware" line.
If we're just printing out the name of the device surrounding the CPU
- be it a Northbridge/Southbridge combination or SoC packaging -
"Chipset" might be a better name for it.
--
Matt Sealey <matt@genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.
^ permalink raw reply
* [PATCH 1/2] ARM: memory: use SZ_ constants for defining the virtual memory layout
From: Matt Sealey @ 2013-01-30 20:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359554912-26872-1-git-send-email-will.deacon@arm.com>
On Wed, Jan 30, 2013 at 8:08 AM, Will Deacon <will.deacon@arm.com> wrote:
> Parts of the virtual memory layout (mainly the modules area) are
> described using open-coded immediate values.
>
> Use the SZ_ definitions from linux/sizes.h instead to make the code
> clearer.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
> arch/arm/include/asm/memory.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 73cf03a..a0fd518 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -36,23 +36,23 @@
> * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
> */
> #define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
> -#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(0x01000000))
> +#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
> #define TASK_UNMAPPED_BASE (UL(CONFIG_PAGE_OFFSET) / 3)
>
> /*
> * The maximum size of a 26-bit user space task.
> */
> -#define TASK_SIZE_26 UL(0x04000000)
> +#define TASK_SIZE_26 UL(SZ_64M)
Wouldn't this make far more sense as UL(1<<26) ?
--
Matt Sealey <matt@genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.
^ permalink raw reply
* [PATCH V2] arm: mvebu: Improve the SMP support of the interrupt controller
From: Jason Cooper @ 2013-01-30 20:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1354740203-26665-1-git-send-email-gregory.clement@free-electrons.com>
On Wed, Dec 05, 2012 at 09:43:23PM +0100, Gregory CLEMENT wrote:
> This patch makes the interrupt controller driver more SMP aware for
> the Armada XP SoCs. It adds the support for the per-CPU irq. It also
> adds the implementation for the set_affinity hook.
>
> Patch initialy wrote by Yehuda Yitschak and reworked by Gregory
> CLEMENT.
>
> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
> arch/arm/boot/dts/armada-xp.dtsi | 2 +-
> arch/arm/mach-mvebu/irq-armada-370-xp.c | 52 +++++++++++++++++++++++++++++++
> 2 files changed, 53 insertions(+), 1 deletion(-)
reapplied to mvebu/boards ;-)
squashed in Yehuda's fix.
thx,
Jason.
^ permalink raw reply
* [PATCH v2 05/27] arm: pci: add a align_resource hook
From: Bjorn Helgaas @ 2013-01-30 20:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130130124721.0ad0294e@skate>
On Wed, Jan 30, 2013 at 4:47 AM, Thomas Petazzoni
<thomas.petazzoni@free-electrons.com> wrote:
> So what I'm going to do now is rework my patch series by removing the
> emulated host bridge (which is normally mandatory by PCIe standard, but
> Linux doesn't need it, so we don't care), ...
This is a tangent since you're removing the emulated host bridge
anyway, but it's been mentioned a couple of times, and I'd like to
understand this. Jason mentioned earlier in the [07/27] emulated host
bridge thread that the PCIe spec requires a host bridge at 00:00.0.
I've never seen that mentioned in the spec; can somebody point me to
the actual requirement that host bridges appear in config space?
My understanding has been that host bridges, whether PCI or PCIe, are
required to *exist*, but that the way you enumerate them and configure
them is outside the scope of the PCI/PCIe specs. I know that many
chips, especially for x86, *do* make the host bridge appear in config
space, but I've never seen a requirement for that.
Bjorn
^ permalink raw reply
* ixp4xx eth broken in 3.7.0/3.8-rc5?
From: Mikael Pettersson @ 2013-01-30 20:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20744.61933.566806.942439@pilspetsen.it.uu.se>
Mikael Pettersson writes:
> Ben Hutchings writes:
> > On Tue, 2013-01-29 at 19:32 -0500, Xi Wang wrote:
> > > On 1/29/13 7:11 PM, Mikael Pettersson wrote:
> > > > A git bisect identified the following as the culprit:
> > > >
> > > > > From 1a4901177574083c35fafc24c4d151c2a7c7647c Mon Sep 17 00:00:00 2001
> > > > > From: Xi Wang <xi.wang@gmail.com>
> > > > > Date: Sat, 17 Nov 2012 20:25:09 +0000
> > > > > Subject: [PATCH] ixp4xx_eth: avoid calling dma_pool_create() with NULL dev
> > > > >
> > > > > Use &port->netdev->dev instead of NULL since dma_pool_create() doesn't
> > > > > allow NULL dev.
> > > > >
> > > > > Signed-off-by: Xi Wang <xi.wang@gmail.com>
> > > > > Cc: Andrew Morton <akpm@linux-foundation.org>
> > > > > Signed-off-by: David S. Miller <davem@davemloft.net>
> > > > > ---
> > > > > drivers/net/ethernet/xscale/ixp4xx_eth.c | 8 +++++---
> > > > > 1 files changed, 5 insertions(+), 3 deletions(-)
> > > >
> > > > Reverting this unbreaks ixp4xx_eth on my ixp4xx machine with kernels
> > > > 3.7.0 and 3.8-rc5.
> > >
> > > Thanks. The problem was that in init_queues(), the dma_pool_create()
> > > call requires a non-null dev.
> > >
> > > dma_pool = dma_pool_create(DRV_NAME, ??, ...);
>
> I had a look around in the 3.8-rc5 kernel source.
>
> mm/dmapool.c:dma_pool_create() needs a non-NULL dev in the CONFIG_NUMA case,
> because it calls dev_to_node(dev) which dereferences dev if CONFIG_NUMA.
> But in the non-CONFIG_NUMA case there is no dereference of dev, and in fact
> there is an explicit check for dev being NULL or not towards the end of
> dma_pool_create(). So that explains why ixp4xx works without the change:
> it's not NUMA.
>
> A quick grep found three calls to dma_pool_create() with a NULL dev parameter,
> two in drivers/usb/gadget/amd5536udc.c and one in arch/arm/mach-s3c64xx/dma.c.
> These would all be broken with CONFIG_NUMA but Ok otherwise.
>
> > >
> > > What do you think would work here?
> >
> > For DMA purposes I would expect the right device to be the parent bus
> > device, i.e. port->netdev->dev.parent. The driver might also need to
> > set its DMA masks.
>
> At least on ixp4xx the DMA masks are normally set by the platform PCI init
> code (it has a 64MB PCI DMA window limitation).
>
> I can give the port->netdev->dev.parent variant a try later this evening.
No joy, s/&port->netdev->dev/port->netdev->dev.parent/ in init_queues' call
to dma_pool_create made no difference, it still fails.
/Mikael
^ permalink raw reply
* [PATCH] ARM: kirkwood: of_serial: fix clock gating by removing clock-frequency
From: Simon Baatz @ 2013-01-30 20:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359493774-27627-1-git-send-email-jason@lakedaemon.net>
Hi Jason,
On Tue, Jan 29, 2013 at 09:09:34PM +0000, Jason Cooper wrote:
> When DT support for kirkwood was first introduced, there was no clock
> infrastructure. As a result, we had to manually pass the
> clock-frequency to the driver from the device node.
>
> Unfortunately, on kirkwood, with minimal config or all module configs,
> clock-frequency breaks booting because of_serial doesn't consume the
> gate_clk when clock-frequency is defined.
>
> The end result on kirkwood is that runit gets gated, and then the boot
> fails when the kernel tries to write to the serial port.
>
> Fix the issue by removing the clock-frequency parameter from all
> kirkwood dts files.
>
> Booted on dreamplug without earlyprintk and successfully logged in via
> ttyS0.
>
> Reported-by: Simon Baatz <gmbnomis@gmail.com>
> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
> ---
If you like, you can add my
Tested-by: Simon Baatz <gmbnomis@gmail.com>
(On IB-NAS6210 serial console, earlyprintk and successful login via
ttyS0)
- Simon
^ permalink raw reply
* Commit 384a290283fde63ba8dc671fca5420111cdac19a seems to break 11MPCore boot
From: Nicolas Pitre @ 2013-01-30 21:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130130203014.GU23505@n2100.arm.linux.org.uk>
On Wed, 30 Jan 2013, Russell King - ARM Linux wrote:
> Right... this is what my current set of patches to make things work
> again looks like... and still there's more problems to go...
>
[...]
> diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
> index 36ae03a..87dfa90 100644
> --- a/arch/arm/common/gic.c
> +++ b/arch/arm/common/gic.c
> @@ -351,6 +351,25 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
> irq_set_chained_handler(irq, gic_handle_cascade_irq);
> }
>
> +static u8 gic_get_cpumask(struct gic_chip_data *gic)
> +{
> + void __iomem *base = gic_data_dist_base(gic);
> + u32 mask, i;
> +
> + for (i = mask = 0; i < 32; i += 4) {
> + mask = readl_relaxed(base + GIC_DIST_TARGET + i);
> + mask |= mask >> 16;
> + mask |= mask >> 8;
> + if (mask)
> + break;
> + }
> +
> + if (!mask)
> + pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
> +
> + return mask;
> +}
> +
> static void __init gic_dist_init(struct gic_chip_data *gic)
> {
> unsigned int i;
> @@ -369,7 +388,9 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
> /*
> * Set all global interrupts to this CPU only.
> */
> - cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0);
> + cpumask = gic_get_cpumask(gic);
> + cpumask |= cpumask << 8;
> + cpumask |= cpumask << 16;
> for (i = 32; i < gic_irqs; i += 4)
> writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
>
> @@ -400,7 +421,7 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
> * Get what the GIC says our CPU mask is.
> */
> BUG_ON(cpu >= NR_GIC_CPU_IF);
> - cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);
> + cpu_mask = gic_get_cpumask(gic);
> gic_cpu_map[cpu] = cpu_mask;
>
> /*
For the above...
Reviewed-by: Nicolas Pitre <nico@linaro.org>
I'm not familiar with Realview and the other issues being fixed.
Nicolas
^ permalink raw reply
* [RFC PATCH v3 1/2] ARM: kernel: update cpuinfo to print SoC model name
From: Nicolas Pitre @ 2013-01-30 21:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKGA1bncYCAwvU1-ZYkAYd_RGUvqq4NCWDeV5EXt4Z6qrgr3Sw@mail.gmail.com>
On Wed, 30 Jan 2013, Matt Sealey wrote:
> On Wed, Jan 30, 2013 at 1:07 PM, Nicolas Pitre <nico@fluxnic.net> wrote:
> > On Wed, 30 Jan 2013, Ruslan Bilovol wrote:
> >
> >> Currently, reading /proc/cpuinfo provides userspace with CPU ID of
> >> the CPU carrying out the read from the file.
> >> Userspace using this information may decide what module
> >> to load or how to configure some specific (and processor-depended)
> >> settings or so.
> >> However, since really different SoCs can share same ARM core,
> >> this information currently is not so useful.
> >> For example, TI OMAP4460 and OMAP4470 SoCs show the same
> >> information in the /proc/cpuinfo whereas they are different.
> >> Since in most cases ARM CPU is a part of some system on a chip (SoC),
> >> the "cpuinfo" file looks like exactly that place, where this
> >> information have to be displayed.
> >>
> >> So added new line "SoC name" in the "cpuinfo" output for system
> >> on a chip name. It is placed between CPU information and machine
> >> information, so the file structure looks gracefully (CPU-SoC-Hardware)
> >>
> >> Example:
> >>
> >> / # cat proc/cpuinfo
> >> [...]
> >> CPU variant : 0x2
> >> CPU part : 0xc09
> >> CPU revision : 10
> >>
> >> SoC name : OMAP4470
> >>
> >> Hardware : OMAP4 Blaze Tablet
> >
> > Please remove that extra blank line between "SoC name" and "Hardware".
> > The blank line after "CPU revision" is fine.
> >
> > Also, please rename this to "System name". Not all systems are "on
> > chip". By using "System name" this is more universally useful.
>
> I can't agree with "System name", it is confusing in common
> terminology since it's about the same definition as the current
> "Hardware" line.
>
> If we're just printing out the name of the device surrounding the CPU
> - be it a Northbridge/Southbridge combination or SoC packaging -
> "Chipset" might be a better name for it.
That suits me as well.
Nicolas
^ permalink raw reply
* i.Mx6Quad - eth0: tx queue full!
From: Troy Kisky @ 2013-01-30 21:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <51093882.2060700@gmail.com>
On 1/30/2013 8:13 AM, Vikram Narayanan wrote:
> On 1/30/2013 12:16 AM, Troy Kisky wrote:
>> I have fixed this bug (and more) on Freescale's kernel
>> (imx-3.0.35_1.1.0). I created a branch you can try.
>> Feel free to port to mainline.
> Thanks a lot for the branch. I saw a lot of differences between
> your driver and the mainline. I should spend some time If I had
> to port this to mainline.
>
>> This is the patch that should fix your problem
>> fec: clear TX_FULL in fec_restart
>>
>>
>> Please let me know results.
> When NAPI is disabled I saw a severe packet loss
> (around 40% in a flood ping) which spitted out this,
>
> [ 470.390928] net eth0: missed rxf 2000000 1c000000 0
> [ 470.419098] net eth0: missed rxf 2000000 1c000000 0
> [ 470.443800] net eth0: missed rxf 2000000 1c000000 0
> [ 470.450315] net eth0: missed rxf 2000000 1c000000 0
>
> When NAPI is enabled, it was working good. Though it
> resulted in the same error, it recovered by itself,
> which is perfectly fine for me. :)
>
You'll also have better performance if you pass "enable_wait_mode=off"
in bootargs.
^ permalink raw reply
* [PATCH v2 05/27] arm: pci: add a align_resource hook
From: Jason Gunthorpe @ 2013-01-30 21:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAErSpo4GKimzwTBB8aN4aj7ms=8pfkoV1=j8mstPDCxc-+gPxQ@mail.gmail.com>
On Wed, Jan 30, 2013 at 01:48:33PM -0700, Bjorn Helgaas wrote:
> This is a tangent since you're removing the emulated host bridge
> anyway, but it's been mentioned a couple of times, and I'd like to
> understand this. Jason mentioned earlier in the [07/27] emulated host
> bridge thread that the PCIe spec requires a host bridge at 00:00.0.
> I've never seen that mentioned in the spec; can somebody point me to
> the actual requirement that host bridges appear in config space?
Hum, a more careful search/reading brings up this:
7.2.2.1. Host Bridge Requirements
[...] The use of Host Bridge PCI class code is reserved for backwards
compatibility; host Bridge configuration space is opaque to standard
PCI Express software and may be implemented in an implementation
specific manner that is compatible with PCI Host Bridge Type 0
configuration space. A PCI Express Host Bridge is not required to
signal errors through a Root Complex Event Collector. This support is
optional for PCI Express Host Bridges.
So, if it is present it is required to be compatible with the 'PCI
Host Bridge' stuff, but it is not mandatory.
My bad, I believe I got also confused with the spec language regarding
a 'host bridge' vs a 'host bridge configuration space'
Regards,
Jason
^ permalink raw reply
* [PATCH 2/2] regulators: anatop: add set_voltage_time_sel interface
From: Troy Kisky @ 2013-01-30 21:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359585461-11377-1-git-send-email-b20788@freescale.com>
On 1/30/2013 3:37 PM, Anson Huang wrote:
> some of anatop's regulators(vppcpu, vddpu and vddsoc) have
> register settings about LDO's step time, which will impact
> the LDO ramp up speed, need to use set_voltage_time_sel
> interface to add necessary delay everytime LDOs' voltage
> is increased.
>
> offset 0x170:
> bit [24-25]: vddcpu
> bit [26-27]: vddpu
> bit [28-29]: vddsoc
>
> field definition:
> 0'b00: 64 cycles of 24M clock;
> 0'b01: 128 cycles of 24M clock;
> 0'b02: 256 cycles of 24M clock;
> 0'b03: 512 cycles of 24M clock;
>
> Signed-off-by: Anson Huang <b20788@freescale.com>
> ---
> drivers/regulator/anatop-regulator.c | 42 ++++++++++++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
> index 8f39cac..a857b9c 100644
> --- a/drivers/regulator/anatop-regulator.c
> +++ b/drivers/regulator/anatop-regulator.c
> @@ -31,12 +31,18 @@
> #include <linux/regulator/driver.h>
> #include <linux/regulator/of_regulator.h>
>
> +#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
> +#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
> +
> struct anatop_regulator {
> const char *name;
> u32 control_reg;
> struct regmap *anatop;
> int vol_bit_shift;
> int vol_bit_width;
> + u32 delay_reg;
> + int delay_bit_shift;
> + int delay_bit_width;
> int min_bit_val;
> int min_voltage;
> int max_voltage;
> @@ -55,6 +61,33 @@ static int anatop_regmap_set_voltage_sel(struct regulator_dev *reg,
> return regulator_set_voltage_sel_regmap(reg, selector);
> }
>
> +static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
> + unsigned int old_sel,
> + unsigned int new_sel)
> +{
> + struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
> + u32 val;
> + int ret = 0;
> +
> + /* check whether need to care about LDO ramp up speed */
> + if (anatop_reg->delay_reg) {
> + /*
> + * the delay for LDO ramp up time is
> + * based on the register setting, we need
> + * to calculate how many steps LDO need to
> + * ramp up, and how much delay needed. (us)
> + */
> + regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
> + val = (val >> anatop_reg->delay_bit_shift) &
> + ((1 << anatop_reg->delay_bit_width) - 1);
> + ret = new_sel > old_sel ? (new_sel - old_sel) *
The (new_sel > old_sel) could be part of the above if.
if (anatop_reg->delay_reg && new_sel > old_sel)
> + ((LDO_RAMP_UP_UNIT_IN_CYCLES << val) /
> + LDO_RAMP_UP_FREQ_IN_MHZ + 1) : 0;
> + }
> +
> + return ret;
> +}
> +
> static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
> {
> struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
> @@ -67,6 +100,7 @@ static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
>
> static struct regulator_ops anatop_rops = {
> .set_voltage_sel = anatop_regmap_set_voltage_sel,
> + .set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
> .get_voltage_sel = anatop_regmap_get_voltage_sel,
> .list_voltage = regulator_list_voltage_linear,
> .map_voltage = regulator_map_voltage_linear,
> @@ -143,6 +177,14 @@ static int anatop_regulator_probe(struct platform_device *pdev)
> goto anatop_probe_end;
> }
>
> + /* read LDO ramp up setting, only for core reg */
> + of_property_read_u32(np, "anatop-delay-reg-offset",
> + &sreg->delay_reg);
> + of_property_read_u32(np, "anatop-delay-bit-width",
> + &sreg->delay_bit_width);
> + of_property_read_u32(np, "anatop-delay-bit-shift",
> + &sreg->delay_bit_shift);
> +
> rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
> + sreg->min_bit_val;
> rdesc->min_uV = sreg->min_voltage;
^ permalink raw reply
* [PATCH] ARM:mach-msm: seting tail NUL after strncpy
From: David Brown @ 2013-01-30 21:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5108A913.6080304@asianux.com>
Chen Gang <gang.chen@asianux.com> writes:
> temp need NUL terminated, or next ptr may cause issue.
>
> Signed-off-by: Chen Gang <gang.chen@asianux.com>
> ---
> arch/arm/mach-msm/clock-debug.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-msm/clock-debug.c
> b/arch/arm/mach-msm/clock-debug.c
> index 4886404..bdca900 100644
> --- a/arch/arm/mach-msm/clock-debug.c
> +++ b/arch/arm/mach-msm/clock-debug.c
> @@ -105,6 +105,8 @@ int __init clock_debug_add(struct clk *clock)
> return -ENOMEM;
>
> strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1);
> + temp[ARRAY_SIZE(temp)-1] = '\0';
> +
> for (ptr = temp; *ptr; ptr++)
I believe that Stephen Boyd is putting some significant work into this
code. Stephen, can you see if this bug is still in your current
version of the code, and make sure that it is fixed there?
Thanks,
David
--
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* [GIT PULL 1/8] ARM: tegra: cleanup
From: Stephen Warren @ 2013-01-30 21:42 UTC (permalink / raw)
To: linux-arm-kernel
This pull request contains various cleanup and minor changes to core
Tegra code:
* Tegra clocksource driver is moved to drivers/clocksource.
* Various typos, warning cleanup, statics cleanup, section mismatch
fixes, etc.
* Various small fixes/cleanups for CPU/hotplug/SMP code.
This pull request is based on a merge of v3.8-rc3 and at least part of
arm-soc's timer/cleanup branch.
----------------------------------------------------------------
The following changes since commit f3dab3989b4282e448cba0f0708934276dcb413a:
Merge remote-tracking branch 'korg_arm-soc/timer/cleanup' into for-3.9/cleanup
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git tegra-for-3.9-cleanup
for you to fetch changes up to 24e30c9417230b359bf6dfeb923e90138df7c112:
ARM: tegra: fix compile error when disable CPU_IDLE
----------------------------------------------------------------
Hiroshi Doyu (2):
clocksource: tegra: cosmetic: Fix error message
ARM: tegra: Make variables static
Joseph Lo (7):
ARM: tegra30: fix power up sequence for boot_secondary
ARM: tegra: update the cache maintenance order for CPU shutdown
ARM: tegra: moving the clock gating procedure to tegra_cpu_kill
ARM: tegra: clean up the CPUINIT section
ARM: tegra: make device can run on UP
ARM: tegra30: make the wait time of CPU power up to proportional to HZ
ARM: tegra: fix compile error when disable CPU_IDLE
Richard Zhao (1):
ARM: tegra: cpufreq: move clk_get/put out of function tegra_cpu_init/exit
Stephen Warren (2):
ARM: tegra: move timer.c to drivers/clocksource/
ARM: tegra: fix Kconfig warnings when !SMP
arch/arm/Kconfig | 1 +
arch/arm/mach-tegra/Kconfig | 4 +-
arch/arm/mach-tegra/Makefile | 6 +-
arch/arm/mach-tegra/apbio.c | 2 +-
arch/arm/mach-tegra/board-dt-tegra20.c | 13 +-
arch/arm/mach-tegra/board-dt-tegra30.c | 5 +-
arch/arm/mach-tegra/board.h | 1 -
arch/arm/mach-tegra/common.c | 3 +
arch/arm/mach-tegra/common.h | 1 +
arch/arm/mach-tegra/cpu-tegra.c | 40 +--
arch/arm/mach-tegra/cpuidle-tegra30.c | 6 +-
arch/arm/mach-tegra/flowctrl.c | 4 +-
arch/arm/mach-tegra/headsmp.S | 221 ----------------
arch/arm/mach-tegra/hotplug.c | 21 +-
arch/arm/mach-tegra/platsmp.c | 43 +++-
arch/arm/mach-tegra/pm.c | 4 +-
arch/arm/mach-tegra/reset-handler.S | 239 ++++++++++++++++++
arch/arm/mach-tegra/reset.c | 2 +-
arch/arm/mach-tegra/sleep-tegra20.S | 3 -
arch/arm/mach-tegra/sleep-tegra30.S | 3 -
arch/arm/mach-tegra/sleep.S | 4 +-
arch/arm/mach-tegra/sleep.h | 1 +
arch/arm/mach-tegra/tegra30_clocks_data.c | 6 +-
drivers/clocksource/Makefile | 1 +
.../clocksource/tegra20_timer.c | 9 +-
25 files changed, 352 insertions(+), 291 deletions(-)
create mode 100644 arch/arm/mach-tegra/reset-handler.S
rename arch/arm/mach-tegra/timer.c => drivers/clocksource/tegra20_timer.c (97%)
^ permalink raw reply
* [GIT PULL 2/8] ARM: tegra: Common Clock Framework rework
From: Stephen Warren @ 2013-01-30 21:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359582159-28816-1-git-send-email-swarren@wwwdotorg.org>
Tegra already supports the common clock framework, but had issues:
1) The clock driver was located in arch/arm/mach-tegra/ rather than
drivers/clk/.
2) A single "Tegra clock" type was implemented, rather than separate
clock types for PLL, mux, divider, ... type in HW.
3) Clock lookups by device drivers were still driven by device name
and connection ID, rather than through device tree.
This pull request solves all three issues. This required some DT changes
to add clocks properties, and driver changes to request clocks more
"correctly". Finally, this rework allows all AUXDATA to be removed from
Tegra board files, and various duplicate clock lookup entries to be
removed from the driver.
This pull request is based on the previous pull request, with tag
tegra-for-3.9-cleanup.
----------------------------------------------------------------
The following changes since commit 24e30c9417230b359bf6dfeb923e90138df7c112:
ARM: tegra: fix compile error when disable CPU_IDLE
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git tegra-for-3.9-soc-ccf
for you to fetch changes up to ef3ffe5a0458606c488def757bb7f6dd013c2db5:
clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()s
----------------------------------------------------------------
Prashant Gaikwad (18):
ARM: tegra: add function to read chipid
ARM: tegra: move tegra_cpu_car.h to linux/clk/tegra.h
ARM: tegra: define Tegra30 CAR binding
clk: tegra: add Tegra specific clocks
clk: tegra: add clock support for Tegra20
clk: tegra: add clock support for Tegra30
ARM: tegra: migrate to new clock code
ARM: tegra: remove legacy clock code
spi: tegra: do not use clock name to get clock
ARM: tegra: add clock properties to Tegra20 DT
ARM: tegra: add clock properties to Tegra30 DT
ARM: tegra: paz00: add clock information to DT
staging: nvec: remove use of clk_get_sys
ASoC: tegra: remove auxdata
ARM: tegra20: remove auxdata
ARM: tegra30: remove auxdata
clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s
clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()s
Stephen Warren (1):
ARM: tegra: define Tegra20 CAR binding
.../bindings/clock/nvidia,tegra20-car.txt | 205 ++
.../bindings/clock/nvidia,tegra30-car.txt | 262 ++
arch/arm/boot/dts/tegra20-paz00.dts | 2 +
arch/arm/boot/dts/tegra20.dtsi | 50 +
arch/arm/boot/dts/tegra30.dtsi | 62 +-
arch/arm/mach-tegra/Makefile | 5 -
arch/arm/mach-tegra/board-dt-tegra20.c | 54 -
arch/arm/mach-tegra/board-dt-tegra30.c | 62 +-
arch/arm/mach-tegra/clock.c | 166 --
arch/arm/mach-tegra/clock.h | 153 --
arch/arm/mach-tegra/common.c | 44 +-
arch/arm/mach-tegra/cpu-tegra.c | 2 +-
arch/arm/mach-tegra/cpuidle-tegra30.c | 2 +-
arch/arm/mach-tegra/fuse.c | 8 +-
arch/arm/mach-tegra/hotplug.c | 2 +-
arch/arm/mach-tegra/include/mach/clk.h | 44 -
arch/arm/mach-tegra/pcie.c | 2 +-
arch/arm/mach-tegra/platsmp.c | 2 +-
arch/arm/mach-tegra/pm.c | 2 +-
arch/arm/mach-tegra/powergate.c | 2 +-
arch/arm/mach-tegra/tegra20_clocks.c | 1623 ------------
arch/arm/mach-tegra/tegra20_clocks.h | 42 -
arch/arm/mach-tegra/tegra20_clocks_data.c | 1143 --------
arch/arm/mach-tegra/tegra30_clocks.c | 2506 ------------------
arch/arm/mach-tegra/tegra30_clocks.h | 54 -
arch/arm/mach-tegra/tegra30_clocks_data.c | 1425 ----------
drivers/clk/Makefile | 1 +
drivers/clk/tegra/Makefile | 11 +
drivers/clk/tegra/clk-audio-sync.c | 87 +
drivers/clk/tegra/clk-divider.c | 187 ++
drivers/clk/tegra/clk-periph-gate.c | 179 ++
drivers/clk/tegra/clk-periph.c | 218 ++
drivers/clk/tegra/clk-pll-out.c | 123 +
drivers/clk/tegra/clk-pll.c | 648 +++++
drivers/clk/tegra/clk-super.c | 154 ++
drivers/clk/tegra/clk-tegra20.c | 1256 +++++++++
drivers/clk/tegra/clk-tegra30.c | 1987 ++++++++++++++
drivers/clk/tegra/clk.c | 85 +
drivers/clk/tegra/clk.h | 502 ++++
drivers/dma/tegra20-apb-dma.c | 2 +-
drivers/gpu/drm/tegra/dc.c | 3 +-
drivers/gpu/drm/tegra/drm.c | 1 -
drivers/gpu/drm/tegra/hdmi.c | 3 +-
drivers/i2c/busses/i2c-tegra.c | 3 +-
drivers/input/keyboard/tegra-kbc.c | 2 +-
drivers/spi/spi-tegra20-sflash.c | 4 +-
drivers/spi/spi-tegra20-slink.c | 4 +-
drivers/staging/nvec/TODO | 4 -
drivers/staging/nvec/nvec.c | 5 +-
.../linux/clk/tegra.h | 13 +-
include/linux/tegra-soc.h | 22 +
sound/soc/tegra/tegra30_ahub.c | 16 +-
52 files changed, 6079 insertions(+), 7365 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
delete mode 100644 arch/arm/mach-tegra/clock.c
delete mode 100644 arch/arm/mach-tegra/clock.h
delete mode 100644 arch/arm/mach-tegra/include/mach/clk.h
delete mode 100644 arch/arm/mach-tegra/tegra20_clocks.c
delete mode 100644 arch/arm/mach-tegra/tegra20_clocks.h
delete mode 100644 arch/arm/mach-tegra/tegra20_clocks_data.c
delete mode 100644 arch/arm/mach-tegra/tegra30_clocks.c
delete mode 100644 arch/arm/mach-tegra/tegra30_clocks.h
delete mode 100644 arch/arm/mach-tegra/tegra30_clocks_data.c
create mode 100644 drivers/clk/tegra/Makefile
create mode 100644 drivers/clk/tegra/clk-audio-sync.c
create mode 100644 drivers/clk/tegra/clk-divider.c
create mode 100644 drivers/clk/tegra/clk-periph-gate.c
create mode 100644 drivers/clk/tegra/clk-periph.c
create mode 100644 drivers/clk/tegra/clk-pll-out.c
create mode 100644 drivers/clk/tegra/clk-pll.c
create mode 100644 drivers/clk/tegra/clk-super.c
create mode 100644 drivers/clk/tegra/clk-tegra20.c
create mode 100644 drivers/clk/tegra/clk-tegra30.c
create mode 100644 drivers/clk/tegra/clk.c
create mode 100644 drivers/clk/tegra/clk.h
rename arch/arm/mach-tegra/tegra_cpu_car.h => include/linux/clk/tegra.h (91%)
create mode 100644 include/linux/tegra-soc.h
^ permalink raw reply
* [GIT PULL 3/8] ARM: tegra: USB driver cleanup
From: Stephen Warren @ 2013-01-30 21:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359582159-28816-1-git-send-email-swarren@wwwdotorg.org>
The Tegra USB driver has a number of issues:
1) The PHY driver isn't a true platform device, and doesn't implement
the standard USB PHY API.
2) struct device instance numbers were used to make decisions in the
driver, rather than being parameterized by DT or platform data.
This pull request solves issue (2), and lays the groundwork for solving
issue (1). The work on issue (1) involved introducing new DT nodes for
the USB PHYs, which in turn interacted with the Tegra common clock
framework changes, due to the move of clock lookups into device tree.
Hence, these USB driver changes are taken through the Tegra tree with
acks from USB maintainers.
This pull request is based on the previous pull request, with tag
tegra-for-3.9-soc-ccf.
----------------------------------------------------------------
The following changes since commit ef3ffe5a0458606c488def757bb7f6dd013c2db5:
clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()s
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git tegra-for-3.9-soc-usb
for you to fetch changes up to ab137d04db5a4b32250ce5ef1b288ce6cf06adf6:
usb: host: tegra: make use of PHY pointer of HCD
----------------------------------------------------------------
Stephen Warren (2):
ARM: tegra: add clocks properties to USB PHY nodes
usb: host: tegra: don't touch EMC clock
Venu Byravarasu (11):
ARM: tegra: remove USB address related macros from iomap.h
usb: phy: use kzalloc to allocate struct tegra_usb_phy
ARM: tegra: Add new DT property to USB node.
usb: host: tegra: Resetting PORT0 based on information received via DT.
usb: phy: remove unused APIs from Tegra PHY.
ARM: tegra: add DT nodes for Tegra USB PHY
USB: PHY: tegra: get rid of instance number to differentiate legacy controller
USB: PHY: tegra: Get rid of instance number to differentiate PHY type
usb: add APIs to access host registers from Tegra PHY
ARM: tegra: Add reset GPIO information to PHY DT node
usb: host: tegra: make use of PHY pointer of HCD
.../bindings/usb/nvidia,tegra20-ehci.txt | 3 +
.../bindings/usb/nvidia,tegra20-usb-phy.txt | 17 +++
arch/arm/boot/dts/tegra20-harmony.dts | 4 +
arch/arm/boot/dts/tegra20-paz00.dts | 4 +
arch/arm/boot/dts/tegra20-seaboard.dts | 4 +
arch/arm/boot/dts/tegra20-trimslice.dts | 4 +
arch/arm/boot/dts/tegra20-ventana.dts | 4 +
arch/arm/boot/dts/tegra20.dtsi | 29 ++++
arch/arm/mach-tegra/board-dt-tegra20.c | 6 +-
arch/arm/mach-tegra/iomap.h | 9 --
drivers/usb/host/ehci-tegra.c | 97 ++++++++-----
drivers/usb/phy/tegra_usb_phy.c | 132 ++++++------------
include/linux/usb/tegra_usb_phy.h | 16 ++-
13 files changed, 191 insertions(+), 138 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
^ permalink raw reply
* [GIT PULL 4/8] ARM: tegra: cpuidle enhancements
From: Stephen Warren @ 2013-01-30 21:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359582159-28816-1-git-send-email-swarren@wwwdotorg.org>
This pull request implements a new "LP2" cpuidle state for Tegra20,
which makes use of the couple cpuidle feature.
It is based on (most of) the previous pull request, with tag
tegra-for-3.9-soc-usb.
----------------------------------------------------------------
The following changes since commit 9304512151b0933c454f0842cdb19bec23422bc5:
usb: host: tegra: don't touch EMC clock
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git tegra-for-3.9-soc-cpuidle
for you to fetch changes up to 1d328606c66b9bb1c0552f585943d596f37ae3b9:
ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
----------------------------------------------------------------
Joseph Lo (5):
ARM: tegra: add pending SGI checking API
ARM: tegra20: cpuidle: add powered-down state for secondary CPU
clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_ops
ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit
ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
arch/arm/mach-tegra/Kconfig | 1 +
arch/arm/mach-tegra/cpuidle-tegra20.c | 197 ++++++++++++++++++++++++++-
arch/arm/mach-tegra/flowctrl.c | 38 +++++-
arch/arm/mach-tegra/flowctrl.h | 4 +
arch/arm/mach-tegra/irq.c | 15 +++
arch/arm/mach-tegra/irq.h | 22 +++
arch/arm/mach-tegra/pm.c | 3 +
arch/arm/mach-tegra/sleep-tegra20.S | 200 ++++++++++++++++++++++++++++
arch/arm/mach-tegra/sleep.S | 19 +++
arch/arm/mach-tegra/sleep.h | 26 ++++
drivers/clk/tegra/clk-tegra20.c | 93 +++++++++++++
11 files changed, 609 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/mach-tegra/irq.h
^ permalink raw reply
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