* [PATCHv5 09/16] arm: arch_timer: add arch_counter_set_user_access
From: Mark Rutland @ 2013-01-31 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359634539-9580-1-git-send-email-mark.rutland@arm.com>
Several bits in CNTKCTL reset to 0, including PL0VTEN. For architectures
using the generic timer which wish to have a fast gettimeofday vDSO
implementation, these bits must be set to 1 by the kernel. For
architectures without a vDSO, it's best to leave the bits set to 0 for
now to ensure that if and when support is added, it's implemented sanely
architecture wide.
As the bootloader might set PL0VTEN to a value that doesn't correspond
to that which the kernel prefers, we must explicitly set it to the
architecture port's preferred value.
This patch adds arch_counter_set_user_access, which sets the PL0 access
permissions to that required by the architecture. For arch/arm, this
currently means disabling all userspace access.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
arch/arm/include/asm/arch_timer.h | 12 ++++++++++++
arch/arm/kernel/arch_timer.c | 2 ++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 75975d9..729f6d9 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -106,6 +106,18 @@ static inline u64 arch_counter_get_cntvct(void)
asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
return cval;
}
+
+static inline void __cpuinit arch_counter_set_user_access(void)
+{
+ u32 cntkctl;
+
+ asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
+
+ /* disable user access to everything */
+ cntkctl &= ~((3 << 8) | (7 << 0));
+
+ asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
+}
#else
static inline int arch_timer_of_register(void)
{
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index c8dfec0..94f5033 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -155,6 +155,8 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
}
+ arch_counter_set_user_access();
+
return 0;
}
--
1.8.1.1
^ permalink raw reply related
* [PATCHv5 08/16] arm: arch_timer: divorce from local_timer api
From: Mark Rutland @ 2013-01-31 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359634539-9580-1-git-send-email-mark.rutland@arm.com>
Currently, the arch_timer driver is tied to the arm port, as it relies
on code in arch/arm/smp.c to setup and teardown timers as cores are
hotplugged on and off. The timer is registered through an arm-specific
registration mechanism, preventing sharing the driver with the arm64
port.
This patch moves the driver to using a cpu notifier instead, making it
easier to port.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/kernel/arch_timer.c | 52 ++++++++++++++++++++++++--------------------
1 file changed, 29 insertions(+), 23 deletions(-)
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index e973cc0..c8dfec0 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -21,7 +21,6 @@
#include <linux/io.h>
#include <asm/delay.h>
-#include <asm/localtimer.h>
#include <asm/arch_timer.h>
#include <asm/sched_clock.h>
@@ -37,7 +36,7 @@ enum ppi_nr {
static int arch_timer_ppi[MAX_TIMER_PPI];
-static struct clock_event_device __percpu **arch_timer_evt;
+static struct clock_event_device __percpu *arch_timer_evt;
static struct delay_timer arch_delay_timer;
static bool arch_timer_use_virtual = true;
@@ -63,14 +62,14 @@ static irqreturn_t inline timer_handler(const int access,
static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
{
- struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+ struct clock_event_device *evt = dev_id;
return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
}
static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
{
- struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+ struct clock_event_device *evt = dev_id;
return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
}
@@ -141,13 +140,13 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
clk->set_next_event = arch_timer_set_next_event_phys;
}
+ clk->cpumask = cpumask_of(smp_processor_id());
+
clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
clockevents_config_and_register(clk, arch_timer_rate,
0xf, 0x7fffffff);
- *__this_cpu_ptr(arch_timer_evt) = clk;
-
if (arch_timer_use_virtual)
enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
else {
@@ -251,12 +250,26 @@ static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
}
-static struct local_timer_ops arch_timer_ops __cpuinitdata = {
- .setup = arch_timer_setup,
- .stop = arch_timer_stop,
-};
+static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self,
+ unsigned long action, void *hcpu)
+{
+ struct clock_event_device *evt = this_cpu_ptr(arch_timer_evt);
+
+ switch (action & ~CPU_TASKS_FROZEN) {
+ case CPU_STARTING:
+ arch_timer_setup(evt);
+ break;
+ case CPU_DYING:
+ arch_timer_stop(evt);
+ break;
+ }
+
+ return NOTIFY_OK;
+}
-static struct clock_event_device arch_timer_global_evt;
+static struct notifier_block arch_timer_cpu_nb __cpuinitdata = {
+ .notifier_call = arch_timer_cpu_notify,
+};
static int __init arch_timer_register(void)
{
@@ -267,7 +280,7 @@ static int __init arch_timer_register(void)
if (err)
goto out;
- arch_timer_evt = alloc_percpu(struct clock_event_device *);
+ arch_timer_evt = alloc_percpu(struct clock_event_device);
if (!arch_timer_evt) {
err = -ENOMEM;
goto out;
@@ -303,20 +316,13 @@ static int __init arch_timer_register(void)
goto out_free;
}
- err = local_timer_register(&arch_timer_ops);
- if (err) {
- /*
- * We couldn't register as a local timer (could be
- * because we're on a UP platform, or because some
- * other local timer is already present...). Try as a
- * global timer instead.
- */
- arch_timer_global_evt.cpumask = cpumask_of(0);
- err = arch_timer_setup(&arch_timer_global_evt);
- }
+ err = register_cpu_notifier(&arch_timer_cpu_nb);
if (err)
goto out_free_irq;
+ /* Immediately configure the timer on the boot CPU */
+ arch_timer_setup(this_cpu_ptr(arch_timer_evt));
+
/* Use the architected timer for the delay loop. */
arch_delay_timer.read_current_timer = &arch_timer_read_current_timer;
arch_delay_timer.freq = arch_timer_rate;
--
1.8.1.1
^ permalink raw reply related
* [PATCHv5 07/16] arm: arch_timer: add isbs to register accessors
From: Mark Rutland @ 2013-01-31 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359634539-9580-1-git-send-email-mark.rutland@arm.com>
Without the isbs in arch_timer_get_cnt{p,v}ct the cpu may speculate
reads and return stale values. This could be bad for code sensitive to
changes in expected deltas between calls (e.g. the delay loop).
Without isbs in arch_timer_reg_write the processor may reorder
instructions around enabling/disabling of the timer or writing the
compare value, which we probably don't want.
This patch adds isbs to prevent those issues.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
arch/arm/include/asm/arch_timer.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index db0fdc4..75975d9 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -49,6 +49,8 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val
break;
}
}
+
+ isb();
}
static inline u32 arch_timer_reg_read(const int access, const int reg)
@@ -91,6 +93,7 @@ static inline u64 arch_counter_get_cntpct(void)
{
u64 cval;
+ isb();
asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
return cval;
}
@@ -99,6 +102,7 @@ static inline u64 arch_counter_get_cntvct(void)
{
u64 cval;
+ isb();
asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
return cval;
}
--
1.8.1.1
^ permalink raw reply related
* [PATCHv5 06/16] arm: arch_timer: factor out register accessors
From: Mark Rutland @ 2013-01-31 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359634539-9580-1-git-send-email-mark.rutland@arm.com>
Currently the arch_timer register accessors are thrown together with
the main driver, preventing us from porting the driver to other
architectures.
This patch moves the register accessors into a header file, as with
the arm64 version. Constants required by the accessors are also moved.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/include/asm/arch_timer.h | 94 +++++++++++++++++++++++++++++++++++++++
arch/arm/kernel/arch_timer.c | 92 --------------------------------------
2 files changed, 94 insertions(+), 92 deletions(-)
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index d40229d..db0fdc4 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -1,13 +1,107 @@
#ifndef __ASMARM_ARCH_TIMER_H
#define __ASMARM_ARCH_TIMER_H
+#include <asm/barrier.h>
#include <asm/errno.h>
#include <linux/clocksource.h>
+#include <linux/types.h>
#ifdef CONFIG_ARM_ARCH_TIMER
int arch_timer_of_register(void);
int arch_timer_sched_clock_init(void);
struct timecounter *arch_timer_get_timecounter(void);
+
+#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
+#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
+#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
+
+#define ARCH_TIMER_REG_CTRL 0
+#define ARCH_TIMER_REG_TVAL 1
+
+#define ARCH_TIMER_PHYS_ACCESS 0
+#define ARCH_TIMER_VIRT_ACCESS 1
+
+/*
+ * These register accessors are marked inline so the compiler can
+ * nicely work out which register we want, and chuck away the rest of
+ * the code. At least it does so with a recent GCC (4.6.3).
+ */
+static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
+{
+ if (access == ARCH_TIMER_PHYS_ACCESS) {
+ switch (reg) {
+ case ARCH_TIMER_REG_CTRL:
+ asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+ break;
+ case ARCH_TIMER_REG_TVAL:
+ asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+ break;
+ }
+ }
+
+ if (access == ARCH_TIMER_VIRT_ACCESS) {
+ switch (reg) {
+ case ARCH_TIMER_REG_CTRL:
+ asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
+ break;
+ case ARCH_TIMER_REG_TVAL:
+ asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
+ break;
+ }
+ }
+}
+
+static inline u32 arch_timer_reg_read(const int access, const int reg)
+{
+ u32 val = 0;
+
+ if (access == ARCH_TIMER_PHYS_ACCESS) {
+ switch (reg) {
+ case ARCH_TIMER_REG_CTRL:
+ asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+ break;
+ case ARCH_TIMER_REG_TVAL:
+ asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+ break;
+ }
+ }
+
+ if (access == ARCH_TIMER_VIRT_ACCESS) {
+ switch (reg) {
+ case ARCH_TIMER_REG_CTRL:
+ asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
+ break;
+ case ARCH_TIMER_REG_TVAL:
+ asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
+ break;
+ }
+ }
+
+ return val;
+}
+
+static inline u32 arch_timer_get_cntfrq(void)
+{
+ u32 val;
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+ return val;
+}
+
+static inline u64 arch_counter_get_cntpct(void)
+{
+ u64 cval;
+
+ asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
+ return cval;
+}
+
+static inline u64 arch_counter_get_cntvct(void)
+{
+ u64 cval;
+
+ asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
+ return cval;
+}
#else
static inline int arch_timer_of_register(void)
{
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index f31c9ee..e973cc0 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -46,98 +46,6 @@ static bool arch_timer_use_virtual = true;
* Architected system timer support.
*/
-#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
-#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
-#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
-
-#define ARCH_TIMER_REG_CTRL 0
-#define ARCH_TIMER_REG_TVAL 1
-
-#define ARCH_TIMER_PHYS_ACCESS 0
-#define ARCH_TIMER_VIRT_ACCESS 1
-
-/*
- * These register accessors are marked inline so the compiler can
- * nicely work out which register we want, and chuck away the rest of
- * the code. At least it does so with a recent GCC (4.6.3).
- */
-static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
-{
- if (access == ARCH_TIMER_PHYS_ACCESS) {
- switch (reg) {
- case ARCH_TIMER_REG_CTRL:
- asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
- break;
- case ARCH_TIMER_REG_TVAL:
- asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
- break;
- }
- }
-
- if (access == ARCH_TIMER_VIRT_ACCESS) {
- switch (reg) {
- case ARCH_TIMER_REG_CTRL:
- asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
- break;
- case ARCH_TIMER_REG_TVAL:
- asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
- break;
- }
- }
-
- isb();
-}
-
-static inline u32 arch_timer_reg_read(const int access, const int reg)
-{
- u32 val = 0;
-
- if (access == ARCH_TIMER_PHYS_ACCESS) {
- switch (reg) {
- case ARCH_TIMER_REG_CTRL:
- asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
- break;
- case ARCH_TIMER_REG_TVAL:
- asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
- break;
- }
- }
-
- if (access == ARCH_TIMER_VIRT_ACCESS) {
- switch (reg) {
- case ARCH_TIMER_REG_CTRL:
- asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
- break;
- case ARCH_TIMER_REG_TVAL:
- asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
- break;
- }
- }
-
- return val;
-}
-
-static inline u32 arch_timer_get_cntfrq(void)
-{
- u32 val;
- asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
- return val;
-}
-
-static inline u64 arch_counter_get_cntpct(void)
-{
- u64 cval;
- asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
- return cval;
-}
-
-static inline u64 arch_counter_get_cntvct(void)
-{
- u64 cval;
- asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
- return cval;
-}
-
static irqreturn_t inline timer_handler(const int access,
struct clock_event_device *evt)
{
--
1.8.1.1
^ permalink raw reply related
* [PATCHv5 05/16] arm: arch_timer: split cntfrq accessor
From: Mark Rutland @ 2013-01-31 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359634539-9580-1-git-send-email-mark.rutland@arm.com>
The CNTFRQ register is not duplicated for physical and virtual timers,
and accessing it as if it were is confusing.
Instead, use a separate accessor which doesn't take the access type
as a parameter.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/kernel/arch_timer.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index eb78f43..f31c9ee 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -51,8 +51,7 @@ static bool arch_timer_use_virtual = true;
#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
#define ARCH_TIMER_REG_CTRL 0
-#define ARCH_TIMER_REG_FREQ 1
-#define ARCH_TIMER_REG_TVAL 2
+#define ARCH_TIMER_REG_TVAL 1
#define ARCH_TIMER_PHYS_ACCESS 0
#define ARCH_TIMER_VIRT_ACCESS 1
@@ -101,9 +100,6 @@ static inline u32 arch_timer_reg_read(const int access, const int reg)
case ARCH_TIMER_REG_TVAL:
asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
break;
- case ARCH_TIMER_REG_FREQ:
- asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
- break;
}
}
@@ -121,6 +117,13 @@ static inline u32 arch_timer_reg_read(const int access, const int reg)
return val;
}
+static inline u32 arch_timer_get_cntfrq(void)
+{
+ u32 val;
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+ return val;
+}
+
static inline u64 arch_counter_get_cntpct(void)
{
u64 cval;
@@ -253,8 +256,7 @@ static int arch_timer_available(void)
u32 freq;
if (arch_timer_rate == 0) {
- freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS,
- ARCH_TIMER_REG_FREQ);
+ freq = arch_timer_get_cntfrq();
/* Check the timer frequency. */
if (freq == 0) {
--
1.8.1.1
^ permalink raw reply related
* [PATCHv5 04/16] arm: arch_timer: standardise counter reading
From: Mark Rutland @ 2013-01-31 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359634539-9580-1-git-send-email-mark.rutland@arm.com>
We're currently inconsistent with respect to our accesses to the
physical and virtual counters, mixing and matching the two.
This patch introduces and uses a function pointer for accessing the
correct counter based on whether we're using physical or virtual
interrupts. All current accesses to the counter accessors are redirected
through it.
When the driver is moved out to drivers/clocksource, there's the
possibility that code called before the timer code is initialised will
attempt to call arch_timer_read_counter (e.g. sched_clock for AArch64).
To avoid having to have to check whether the timer has been initialised
either in arch_timer_read_counter or one of it's callers, a default
implementation is assigned that simply returns 0.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/kernel/arch_timer.c | 58 +++++++++++++++++---------------------------
1 file changed, 22 insertions(+), 36 deletions(-)
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index 498c29f..eb78f43 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -272,51 +272,37 @@ static int arch_timer_available(void)
return 0;
}
-static u32 notrace arch_counter_get_cntpct32(void)
+/*
+ * Some external users of arch_timer_read_counter (e.g. sched_clock) may try to
+ * call it before it has been initialised. Rather than incur a performance
+ * penalty checking for initialisation, provide a default implementation that
+ * won't lead to time appearing to jump backwards.
+ */
+static u64 arch_timer_read_zero(void)
{
- cycle_t cnt = arch_counter_get_cntpct();
-
- /*
- * The sched_clock infrastructure only knows about counters
- * with at most 32bits. Forget about the upper 24 bits for the
- * time being...
- */
- return (u32)cnt;
+ return 0;
}
-static u32 notrace arch_counter_get_cntvct32(void)
-{
- cycle_t cnt = arch_counter_get_cntvct();
+u64 (*arch_timer_read_counter)(void) = arch_timer_read_zero;
- /*
- * The sched_clock infrastructure only knows about counters
- * with at most 32bits. Forget about the upper 24 bits for the
- * time being...
- */
- return (u32)cnt;
+static u32 arch_timer_read_counter32(void)
+{
+ return arch_timer_read_counter();
}
static cycle_t arch_counter_read(struct clocksource *cs)
{
- /*
- * Always use the physical counter for the clocksource.
- * CNTHCTL.PL1PCTEN must be set to 1.
- */
- return arch_counter_get_cntpct();
+ return arch_timer_read_counter();
}
static unsigned long arch_timer_read_current_timer(void)
{
- return arch_counter_get_cntpct();
+ return arch_timer_read_counter();
}
static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
{
- /*
- * Always use the physical counter for the clocksource.
- * CNTHCTL.PL1PCTEN must be set to 1.
- */
- return arch_counter_get_cntpct();
+ return arch_timer_read_counter();
}
static struct clocksource clocksource_counter = {
@@ -484,23 +470,23 @@ int __init arch_timer_of_register(void)
}
}
+ if (arch_timer_use_virtual)
+ arch_timer_read_counter = arch_counter_get_cntvct;
+ else
+ arch_timer_read_counter = arch_counter_get_cntpct;
+
return arch_timer_register();
}
int __init arch_timer_sched_clock_init(void)
{
- u32 (*cnt32)(void);
int err;
err = arch_timer_available();
if (err)
return err;
- if (arch_timer_use_virtual)
- cnt32 = arch_counter_get_cntvct32;
- else
- cnt32 = arch_counter_get_cntpct32;
-
- setup_sched_clock(cnt32, 32, arch_timer_rate);
+ setup_sched_clock(arch_timer_read_counter32,
+ 32, arch_timer_rate);
return 0;
}
--
1.8.1.1
^ permalink raw reply related
* [PATCHv5 03/16] arm: arch_timer: use u64/u32 for register data
From: Mark Rutland @ 2013-01-31 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359634539-9580-1-git-send-email-mark.rutland@arm.com>
To ensure the correct size of types, use u64 for the return value of
arch_timer_get_cnt{p,v}ct, and u32 for arch_timer_rate, matching the
size of the registers these values are taken from. While we're changing
them anyway, simplify the implementation of arch_timer_get_cnt{p,v}ct.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/kernel/arch_timer.c | 30 +++++++++++-------------------
1 file changed, 11 insertions(+), 19 deletions(-)
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index 1bb3b582..498c29f 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -25,7 +25,7 @@
#include <asm/arch_timer.h>
#include <asm/sched_clock.h>
-static unsigned long arch_timer_rate;
+static u32 arch_timer_rate;
enum ppi_nr {
PHYS_SECURE_PPI,
@@ -121,27 +121,18 @@ static inline u32 arch_timer_reg_read(const int access, const int reg)
return val;
}
-static inline cycle_t arch_timer_counter_read(const int access)
+static inline u64 arch_counter_get_cntpct(void)
{
- cycle_t cval = 0;
-
- if (access == ARCH_TIMER_PHYS_ACCESS)
- asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
-
- if (access == ARCH_TIMER_VIRT_ACCESS)
- asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
-
+ u64 cval;
+ asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
return cval;
}
-static inline cycle_t arch_counter_get_cntpct(void)
-{
- return arch_timer_counter_read(ARCH_TIMER_PHYS_ACCESS);
-}
-
-static inline cycle_t arch_counter_get_cntvct(void)
+static inline u64 arch_counter_get_cntvct(void)
{
- return arch_timer_counter_read(ARCH_TIMER_VIRT_ACCESS);
+ u64 cval;
+ asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
+ return cval;
}
static irqreturn_t inline timer_handler(const int access,
@@ -259,7 +250,7 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
static int arch_timer_available(void)
{
- unsigned long freq;
+ u32 freq;
if (arch_timer_rate == 0) {
freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS,
@@ -275,7 +266,8 @@ static int arch_timer_available(void)
}
pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
- arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100,
+ (unsigned long)arch_timer_rate / 1000000,
+ (unsigned long)(arch_timer_rate / 10000) % 100,
arch_timer_use_virtual ? "virt" : "phys");
return 0;
}
--
1.8.1.1
^ permalink raw reply related
* [PATCHv5 02/16] arm: arch_timer: remove redundant available check
From: Mark Rutland @ 2013-01-31 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359634539-9580-1-git-send-email-mark.rutland@arm.com>
This check is a holdover from the pre-devicetree days. As the timer
is not probed except by platforms which register it via devicetree,
it's not strictly necessary.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm/kernel/arch_timer.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index 6dd73c6..1bb3b582 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -20,11 +20,9 @@
#include <linux/of_irq.h>
#include <linux/io.h>
-#include <asm/cputype.h>
#include <asm/delay.h>
#include <asm/localtimer.h>
#include <asm/arch_timer.h>
-#include <asm/system_info.h>
#include <asm/sched_clock.h>
static unsigned long arch_timer_rate;
@@ -259,20 +257,10 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
return 0;
}
-/* Is the optional system timer available? */
-static int local_timer_is_architected(void)
-{
- return (cpu_architecture() >= CPU_ARCH_ARMv7) &&
- ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
-}
-
static int arch_timer_available(void)
{
unsigned long freq;
- if (!local_timer_is_architected())
- return -ENXIO;
-
if (arch_timer_rate == 0) {
freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS,
ARCH_TIMER_REG_FREQ);
--
1.8.1.1
^ permalink raw reply related
* [PATCHv5 01/16] arm: arch_timer: balance device_node refcounting
From: Mark Rutland @ 2013-01-31 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359634539-9580-1-git-send-email-mark.rutland@arm.com>
When we get the device_node for the arch timer, it's refcount is
automatically incremented in of_find_matching_node, but it is
never decremented.
This patch decrements the refcount on the node after we're finished
using it.
Reported-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/kernel/arch_timer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index c8ef207..6dd73c6 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -488,6 +488,8 @@ int __init arch_timer_of_register(void)
for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
+ of_node_put(np);
+
/*
* If no interrupt provided for virtual timer, we'll have to
* stick to the physical timer. It'd better be accessible...
--
1.8.1.1
^ permalink raw reply related
* [PATCHv5 00/16] Unify arm_generic and arch_timer drivers
From: Mark Rutland @ 2013-01-31 12:15 UTC (permalink / raw)
To: linux-arm-kernel
This is an updated version of v4 of the series I posted 2 weeks ago [1].
The only change is the last two patches, moving over to always using the
virtual counters. I've left these as separate patches rather than
folding them in to allow them to be reviewed more easily.
I've tested the series on a TC2 and an AArch64 model, and I'm happy that
it all works.
Stephen, Thomas:
I've not folded the CLOCKSOURCE_OF_DECLARE patch as it's unclear what
path everything is going to take, and I don't a have a tree with
Stephen's patch that I can base on.
There's already a dependency on the timer broadcast rework, and adding
more branches to the mix is going to get messy. I can take the version
with ifdefs under the assumption we remove them in a later patch once
Stephen's patch is in. Does that sound ok?
Thanks,
Mark.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/142070.html
Marc Zyngier (2):
ARM: arch_timers: switch to physical timers if HYP mode is available
ARM: hyp: initialize CNTVOFF to zero
Mark Rutland (14):
arm: arch_timer: balance device_node refcounting
arm: arch_timer: remove redundant available check
arm: arch_timer: use u64/u32 for register data
arm: arch_timer: standardise counter reading
arm: arch_timer: split cntfrq accessor
arm: arch_timer: factor out register accessors
arm: arch_timer: add isbs to register accessors
arm: arch_timer: divorce from local_timer api
arm: arch_timer: add arch_counter_set_user_access
arm: arch_timer: move core to drivers/clocksource
arm64: arm_generic: prevent reading stale time
arm64: move from arm_generic to arm_arch_timer
Documentation: Add ARMv8 to arch_timer devicetree
clocksource: arch_timer: use virtual counters
.../devicetree/bindings/arm/arch_timer.txt | 7 +-
arch/arm/Kconfig | 3 +-
arch/arm/include/asm/arch_timer.h | 109 ++++-
arch/arm/kernel/arch_timer.c | 504 +--------------------
arch/arm/kernel/hyp-stub.S | 3 +
arch/arm/mach-omap2/Kconfig | 2 +-
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/arch_timer.h | 133 ++++++
arch/arm64/include/asm/arm_generic.h | 100 ----
arch/arm64/kernel/time.c | 29 +-
drivers/clocksource/Kconfig | 6 +-
drivers/clocksource/Makefile | 2 +-
drivers/clocksource/arm_arch_timer.c | 378 ++++++++++++++++
drivers/clocksource/arm_generic.c | 232 ----------
include/clocksource/arm_arch_timer.h | 63 +++
include/clocksource/arm_generic.h | 21 -
16 files changed, 738 insertions(+), 855 deletions(-)
create mode 100644 arch/arm64/include/asm/arch_timer.h
delete mode 100644 arch/arm64/include/asm/arm_generic.h
create mode 100644 drivers/clocksource/arm_arch_timer.c
delete mode 100644 drivers/clocksource/arm_generic.c
create mode 100644 include/clocksource/arm_arch_timer.h
delete mode 100644 include/clocksource/arm_generic.h
--
1.8.1.1
^ permalink raw reply
* [GIT PULL] power: ab8500-bm: Latest Mainline<->STE delta reduction patch-set
From: Lee Jones @ 2013-01-31 12:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130123144441.GN15873@gmail.com>
Hi Anton,
> Okay, after Linus Walleij's diligent observaions, I have removed all
> new functionallity related to Deep Debug and will continue to
> investigate what I need to do in that regard.
>
> In the mean-time, here's the fresh deep-debug:less pull-request:
>
> ----------------------------------------------------------------
>
> The following changes since commit 8fd526fd18233887ba652079a369f4eee0de9d9d:
>
> qnap-poweroff: Fix license string (2013-01-19 18:04:04 -0800)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/ljones/linux-3.0-ux500.git tb-power-2
>
> for you to fetch changes up to 34c11a709e928090cf34ecd706f7d3170f4e5026:
>
> u8500-charger: Delay for USB enumeration (2013-01-23 14:39:22 +0000)
Did you pull this in the end?
> ----------------------------------------------------------------
> Hakan Berg (1):
> ab8500-fg: Adjust for RF bursts voltage drops
>
> Henrik S?lver (1):
> ab8500-charger: AB workaround for invalid charger
>
> Jonas Aaberg (2):
> ab8500-bm: Flush all work queues before suspending
> ab8500-charger: Do not touch VBUSOVV bits
>
> Lee Jones (7):
> ab8500-charger: Kick watchdog
> ab8500-chargalg: Update battery health on safety timer exp
> pm2301: Move all configuration and emum structs out to a header
> file
> ab8500-chargalg: Only root should have write permission on sysfs
> file
> abx500-chargalg: Add new sysfs interface to get current charge
> status
> pm2301: LPN mode control support
> ab8500-bm: Remove individual [charger|btemp|fg|chargalg] pdata
> structures
>
> Loic Pallardy (2):
> pm2301: Remove volt_now & curr_now properties
> pm2301: Update watchdog for pm2xxx support
>
> Martin Bergstr?m (1):
> ab8500-fg: Go to INIT_RECOVERY when charger removed
>
> Michel JAOUEN (2):
> pm2301: Provide u9540 support for the pm2301 charger
> ab8500-btemp: Adaptation to AB8505 and AB9540 platforms
>
> Nicolas Guion (1):
> ab8500-charger: Add support for autopower on AB8505 and AB9540
>
> Olivier Clergeaud (1):
> pm2301: Clean-up PM2301 interrupt management
>
> Paer-Olof Haakansson (1):
> u8500-charger: Delay for USB enumeration
>
> Rajkumar Kasirajan (2):
> pm2301: Enable vbat low monitoring
> ab8500-fg: Use correct battery charge full design
>
> drivers/mfd/ab8500-core.c | 6 +
> drivers/power/Kconfig | 7 +
> drivers/power/Makefile | 1 +
> drivers/power/ab8500_btemp.c | 67 +-
> drivers/power/ab8500_charger.c | 617 ++++++++++++----
> drivers/power/ab8500_fg.c | 51 +-
> drivers/power/abx500_chargalg.c | 43 +-
> drivers/power/pm2301_charger.c | 1088 +++++++++++++++++++++++++++++
> drivers/power/pm2301_charger.h | 513 ++++++++++++++
> include/linux/mfd/abx500.h | 3 +
> include/linux/mfd/abx500/ab8500-bm.h | 22 +-
> include/linux/mfd/abx500/ab8500.h | 19 +
> include/linux/mfd/abx500/ux500_chargalg.h | 5 +
> include/linux/pm2301_charger.h | 61 ++
> 14 files changed, 2306 insertions(+), 197 deletions(-)
> create mode 100644 drivers/power/pm2301_charger.c
> create mode 100644 drivers/power/pm2301_charger.h
> create mode 100644 include/linux/pm2301_charger.h
>
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH] arm: mvebu: support for the new Armada XP evaluation board(DB-MV784MP-GP)
From: Gregory CLEMENT @ 2013-01-31 12:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130130181035.GP7717@titan.lakedaemon.net>
On 01/30/2013 07:10 PM, Jason Cooper wrote:
>
> Gregory,
>
> Adding devicetree-discuss.
I should have added it in in CC in my first version
>
> Guys, how do you prefer to handle plug-in RAM modules? describe the
> soldered-in amount, or?
>
> On Wed, Jan 30, 2013 at 06:35:17PM +0100, Gregory CLEMENT wrote:
>> On 01/30/2013 06:33 PM, Jason Cooper wrote:
>>> On Wed, Jan 30, 2013 at 06:26:14PM +0100, Gregory CLEMENT wrote:
>>>> This is the new Armada XP evaluation board from Marvell. It comes with
>>>> a RS232 port over USB, a SATA link, an internal SSD, 4 Ethernet
>>>> Gigabit links.
>>>>
>>>> Support for USB (Host and device), SDIO, PCIe will be added as drivers
>>>> when they become available for Armada XP in mainline.
>>>>
>>>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>>>> ---
>>>> arch/arm/boot/dts/Makefile | 1 +
>>>> arch/arm/boot/dts/armada-xp-gp.dts | 94 ++++++++++++++++++++++++++++++++++++
>>>> 2 files changed, 95 insertions(+)
>>>> create mode 100644 arch/arm/boot/dts/armada-xp-gp.dts
>>>>
> ...
>>>> + memory {
>>>> + device_type = "memory";
>>>> + reg = <0x00000000 0xC0000000>; /* 3 GB */
>>>
>>> Is this the soldered on the board amount, or the amount with an
>>> expandable slot filled?
>>
>> It is not soldered, so you can change the amount of memory
>
> Well, there's something we don't encounter too much in the embedded
> world. ;-) I'm inclined to think the entry here should be the soldered
> on amount, and the bootloader would (hypothetically) change the DT to
> the probed amount. But I haven't seen a precedent set yet...
Well on this board there is no soldered memory at all.
>
> thx,
>
> Jason.
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] arm: mvebu: support for the new Armada XP evaluation board(DB-MV784MP-GP)
From: Gregory CLEMENT @ 2013-01-31 12:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130131110716.50b7340b@skate>
On 01/31/2013 11:07 AM, Thomas Petazzoni wrote:
> Dear Andrew Lunn,
>
> On Thu, 31 Jan 2013 10:50:25 +0100, Andrew Lunn wrote:
>
>> We have the same issue with OpenBox AX3. All the devices we have in
>> our hands have 1GB soldered down, plus 2GB on expansion. The DT
>> currently has the full 3GB.
>>
>> However, there has been discussion of reducing this down to 1GB since
>> both Thomas and Gregory have unstable systems with the full 3GB, but
>> mine box is stable with the full 3GB. So i don't know how strong a
>> precedent that sets....
>
> It seems that if we have CONFIG_ARM_ATAG_DTB_COMPAT, then the code in
> arch/arm/boot/compressed/atags_to_fdt.c will update the DT memory node
> according to the ATAG_MEM passed by the bootloader.
>
>From my point of view these dts file are just given as reference, and the
bootloader should be able to modify them on the fly according the hardware
configuration of the board.
And for old bootloader then we can use the CONFIG_ARM_ATAG_DTB_COMPAT as
pointed by Thomas.
So I am not sure that the amount of memory is very important.
However I think that having a value by default is useful, so unless
there is a strong argument against it, I would like to keep it, maybe with
a comment in the dts to emphasize that it is just a default value and the
amount of memory can be changed.
> Best regards,
>
> Thomas
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [RFC PATCH v3 1/2] ARM: kernel: update cpuinfo to print SoC model name
From: Ruslan Bilovol @ 2013-01-31 11:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130130232408.GL2637@n2100.arm.linux.org.uk>
On Thu, Jan 31, 2013 at 1:24 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Wed, Jan 30, 2013 at 02:07:53PM -0500, Nicolas Pitre wrote:
>> On Wed, 30 Jan 2013, Ruslan Bilovol wrote:
>>
>> > Currently, reading /proc/cpuinfo provides userspace with CPU ID of
>> > the CPU carrying out the read from the file.
>> > Userspace using this information may decide what module
>> > to load or how to configure some specific (and processor-depended)
>> > settings or so.
>> > However, since really different SoCs can share same ARM core,
>> > this information currently is not so useful.
>> > For example, TI OMAP4460 and OMAP4470 SoCs show the same
>> > information in the /proc/cpuinfo whereas they are different.
>> > Since in most cases ARM CPU is a part of some system on a chip (SoC),
>> > the "cpuinfo" file looks like exactly that place, where this
>> > information have to be displayed.
>> >
>> > So added new line "SoC name" in the "cpuinfo" output for system
>> > on a chip name. It is placed between CPU information and machine
>> > information, so the file structure looks gracefully (CPU-SoC-Hardware)
>> >
>> > Example:
>> >
>> > / # cat proc/cpuinfo
>> > [...]
>> > CPU variant : 0x2
>> > CPU part : 0xc09
>> > CPU revision : 10
>> >
>> > SoC name : OMAP4470
>> >
>> > Hardware : OMAP4 Blaze Tablet
>>
>> Please remove that extra blank line between "SoC name" and "Hardware".
>> The blank line after "CPU revision" is fine.
>>
>> Also, please rename this to "System name". Not all systems are "on
>> chip". By using "System name" this is more universally useful.
>
> You may notice I've already suggested that this should be using the SoC
> infrastructure to export this information, which was explicitly designed
> to do this.
>
> If we're going to have one SoC doing one thing and another SoC exporting
> this information a completely different way, we're doomed. We need to
> make a decision and do it one way and one way only - and that decision
> was made when drivers/base/soc.c was merged.
>
> Unfortunately, I'd forgotten about that when I made my initial comments
> about the difference between "CPU" and "SoC".
Yes agree - let's stop this discussion at this point. I'm going to
learn that soc framework and provide better solution.
Unfortunately, I didn't find it when looked into the kernel sources
for similar approaches.
Regards,
Ruslan
^ permalink raw reply
* [PATCH 07/10] ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
From: Rajendra Nayak @ 2013-01-31 11:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <51095A65.9070102@ti.com>
On Wednesday 30 January 2013 11:07 PM, Jon Hunter wrote:
>
> On 01/18/2013 09:27 AM, Santosh Shilimkar wrote:
>> From: Rajendra Nayak <rnayak@ti.com>
>>
>> Add the clock tree related data for OMAP54xx platforms.
>
> [snip]
>
>> + CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_54XX),
>> + CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_54XX),
>> + CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_54XX),
>> + CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_54XX),
>> + CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_54XX),
>> + CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_54XX),
>> + CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_54XX),
>> + CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_54XX),
>> + CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_54XX),
>> + CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_54XX),
>> + CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_54XX),
>
> I have been trying to get away from having so many aliases for the same
> clock for timers. Here we should replace all of the above and just have ...
>
> + CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_54XX),
>
> For more details see [1].
>
>> + CLK("omap_timer.1", "sys_ck", &sys_clkin, CK_54XX),
>> + CLK("omap_timer.2", "sys_ck", &sys_clkin, CK_54XX),
>> + CLK("omap_timer.3", "sys_ck", &sys_clkin, CK_54XX),
>> + CLK("omap_timer.4", "sys_ck", &sys_clkin, CK_54XX),
>> + CLK("omap_timer.9", "sys_ck", &sys_clkin, CK_54XX),
>> + CLK("omap_timer.10", "sys_ck", &sys_clkin, CK_54XX),
>> + CLK("omap_timer.11", "sys_ck", &sys_clkin, CK_54XX),
>> + CLK("omap_timer.5", "sys_ck", &dss_syc_gfclk_div, CK_54XX),
>> + CLK("omap_timer.6", "sys_ck", &dss_syc_gfclk_div, CK_54XX),
>> + CLK("omap_timer.7", "sys_ck", &dss_syc_gfclk_div, CK_54XX),
>> + CLK("omap_timer.8", "sys_ck", &dss_syc_gfclk_div, CK_54XX),
>> +};
>
> These aliases will not work with device-tree because the device-name is
> formatted <addr>.<device>. Hence, when configuring a the timer parent
> clock via the dmtimer driver it will fail. So it should be more like ...
>
> + CLK("4ae18000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
> + CLK("48032000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
> + CLK("48034000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
> + CLK("48036000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
> + CLK("40138000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
> + CLK("4013a000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
> + CLK("4013c000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
> + CLK("4013e000.timer", "timer_sys_ck", &dss_syc_gfclk_div,
> CK_54XX),
> + CLK("4803e000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX),
> + CLK("48086000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX),
> + CLK("48088000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX),
>
> For more details see [2].
Thanks Jon. I will update the autogen scripts to generate these
accordingly.
>
> If you would like to test the dmtimer driver on omap5, then you can grab
> my omap-test module [3], build it (see README), load it and then ...
>
> # echo 1 > /sys/kernel/debug/omap-test/timer/all
>
> This will perform some basic tests on all the dmtimers. I would do it
> myself, but there appears to be several issues getting this to boot on
> an ES1.0 (which is probably expected).
Right. This is ES2.0 data, so won't boot on an ES1.0 device.
regards,
Rajendra
>
> Cheers
> Jon
>
> [1] http://www.spinics.net/lists/linux-omap/msg71272.html
> [2] https://patchwork.kernel.org/patch/1204351/
> [3] https://github.com/jonhunter/omap-test
>
^ permalink raw reply
* [PATCH v2 4/4] irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
From: Catalin Marinas @ 2013-01-31 11:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130131112538.GW23505@n2100.arm.linux.org.uk>
On Thu, Jan 31, 2013 at 11:25:38AM +0000, Russell King - ARM Linux wrote:
> On Tue, Jan 29, 2013 at 07:11:56PM -0500, Nicolas Pitre wrote:
> > On Tue, 29 Jan 2013, Catalin Marinas wrote:
> > > I would like to get them in as soon as possible (ideally 3.9) as AArch64
> > > needs GIC support. I can base them on Rob's branch (already in -next)
> > > and send them the same route (the arm-soc tree if Olof/Arnd are ok to
> > > take them).
> >
> > Well... I'd prefer if my series was merged by RMK since this is mostly
> > core ARM code. That is posing dependency issues.
> >
> > I think I'll just ignore your change for now and we'll fix things up
> > during the v3.9-rc period.
>
> Given that the ARM kernel seems to be rather broken at the moment, that's
> not going to happen until the 32-bit kernel gets some loving attention to
> make it work again.
>
> Our primary responsibility is not to stuff the kernel with new features
> as quickly as we possibly can. It's to make sure that the kernel works,
> and at the moment, it doesn't. I'm not talking about ancient architectures.
> I'm talking about platforms using ARMv6 and above - platforms with the GIC
> which I'd be able to test this change on.
FWIW, I tested this on vexpress with CA9x4 tile with both 3.8-rc3 (Rob's
branch) and latest linux-next.
If you want to test this change for longer, I'm ok to leave it for 3.10
and stick it in -next at some point (after 3.9-rc1 since there are many
conflicts). I'd like however to push the other trivial code-moving
patches in this series.
--
Catalin
^ permalink raw reply
* [PATCH v3 1/4] ASoC: tlv320aic3x: Convert mic bias to a supply widget
From: Hebbar, Gururaja @ 2013-01-31 11:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130131113035.GF11078@opensource.wolfsonmicro.com>
On Thu, Jan 31, 2013 at 17:00:38, Mark Brown wrote:
> On Thu, Jan 31, 2013 at 11:27:07AM +0000, Hebbar, Gururaja wrote:
> > On Thu, Jan 31, 2013 at 16:54:16, Mark Brown wrote:
>
> > > As mentioned when you posted this before this patch needs to update the
> > > machine drivers using the device too.
>
> > The patch-set 2/4 does the same thing. Since I have da850-evm at my end, I
> > have modified that machine driver and sent-it as 2/4.
>
> Two problems here. One is that the update should be done in the same
> patch and the other is that you need to update *all* the machine drivers
> using the device, not just one of them.
Ok, I will send the updated version now.
>
Regards,
Gururaja
^ permalink raw reply
* [PATCH v2 0/4] Preparatory GIC patches for arm64 support
From: Russell King - ARM Linux @ 2013-01-31 11:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130131103044.GB12877@arm.com>
On Thu, Jan 31, 2013 at 10:30:44AM +0000, Catalin Marinas wrote:
> Olof, Arnd,
>
> On Tue, Jan 29, 2013 at 04:18:35PM +0000, Catalin Marinas wrote:
> > That's the second version of the GIC clean-up patches to support arm64.
> > The only change from v1 is that the second patch (chained_irq.h) also
> > covers drivers/gpio and drivers/pinctrl (#include change).
>
> Are you ok to merge this series via the arm-soc tree for 3.9-rc1? There
> are no complaints so far (only acks ;). This would allow me to push GIC
> support for arm64.
So I don't exist anymore to you?
Catalin, it's already been suggested to you that this series is more
core ARM stuff than SoC stuff, and it's also been suggested that you
merge this through my tree.
No, I guess this figures after all your excessively negative replies
on all of my comments during the review of ARM64.
^ permalink raw reply
* [PATCH] ARM: omap4: clock data: Add missing clkdm association for dpll_usb
From: Rajendra Nayak @ 2013-01-31 11:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1301250810090.471@utopia.booyaka.com>
Hi Paul,
>> dpll_usb needs the clkdm association so the clkdm can be
>> turned on before a relock. All other dplls for omap4 belong
>> to the ALWON (always on) domain.
>>
>> The association was present as part of the older data file
>> (clock44xx_data.c) but looks like was accidently dropped with
>> the common clk convertion.
>
> Thanks, queued for v3.8-rc fixes.
I just realized that apart from adding the missing .clkdm_name, I
also need to populate a .init as part of clk_ops for dpll_usb
so the clockdomain lookup can then happen based on the .clkdm_name.
I have updated the $Subject patch and posted a v2 (http://marc.info
/?l=linux-omap&m=135963212530790&w=2). Would it be possible for you to
pick the v2 instead and drop this one from your fixes branch.
regards,
Rajendra
>
> - Paul
>
^ permalink raw reply
* [REGRESSION+BISECT] imx6: 3.8+: sata failure with 24d340ac "ARM i.MX6: Fix ethernet PLL clocks"
From: Paolo Pisati @ 2013-01-31 11:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
sata doesn't work anymore in 3.8rcX (while it was ok in 3.7 + 1 patch[1]) and i've bisected
it down to:
>From 24d340ac43882583024ffcce1cd38b9b2391eb51 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Wed, 21 Nov 2012 14:42:31 +0100
Subject: [PATCH 132/144] ARM i.MX6: Fix ethernet PLL clocks
In current code the ethernet PLL is not handled correctly. The PLL runs at
500MHz
and has different outputs. Only the enet reference clock is implemented. This
patch changes the PLL so that it outputs 500MHz and adds the additional outputs
as dividers. This now matches the datasheet which says:
...
ahci 2200000.ahci: forcing PORTS_IMPL to 0x1
ahci 2200000.ahci: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
ahci 2200000.ahci: flags: ncq sntf pm led clo only pmp pio slum part ccc apst
scsi0 : ahci_platform
ata1: SATA max UDMA/133 mmio [mem 0x02200000-0x02203fff] port 0x100 irq 71
...
ata1: link is slow to respond, please be patient (ready=0)
ata1: softreset failed (device not ready)
ata1: SATA link down (SStatus 0 SControl 300)
...
without that patch, it works like a charm.
Here is my kernel config:
http://people.canonical.com/~ppisati/imx6_sata/config
Anyone else seeing this?
1: http://people.canonical.com/~ppisati/imx6_sata/0001-Add-IMX6Q-AHCI-support.patch
--
bye,
p.
^ permalink raw reply
* [PATCH v2] ARM: omap4: clock data: Add missing clkdm association for dpll_usb
From: Rajendra Nayak @ 2013-01-31 11:35 UTC (permalink / raw)
To: linux-arm-kernel
dpll_usb needs the clkdm association so the clkdm can be
turned on before a relock. All other dplls for omap4 belong
to the ALWON (always on) domain.
The association was present as part of the older data file
(clock44xx_data.c) but looks like got accidently dropped with
the common clk convertion.
More details of the patch which fixed this up in the older
data file can be dound here..
http://www.spinics.net/lists/linux-omap/msg63076.html
Adding the .clkdm_name as part of the clk_hw_omap struct also
means a new .init needs to be part of the clk_ops for dpll_usb
to initialise the clkdm.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/cclock44xx_data.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index a2cc046..e71a19c 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -595,15 +595,26 @@ static const char *dpll_usb_ck_parents[] = {
static struct clk dpll_usb_ck;
+static const struct clk_ops dpll_usb_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+ .init = &omap2_init_clk_clkdm,
+};
+
static struct clk_hw_omap dpll_usb_ck_hw = {
.hw = {
.clk = &dpll_usb_ck,
},
.dpll_data = &dpll_usb_dd,
+ .clkdm_name = "l3_init_clkdm",
.ops = &clkhwops_omap3_dpll,
};
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_ck_ops);
+DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
static const char *dpll_usb_clkdcoldo_ck_parents[] = {
"dpll_usb_ck",
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/2] USB chipidea i.MX: use devm_usb_get_phy_by_phandle to get phy
From: Sascha Hauer @ 2013-01-31 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359631937-26646-1-git-send-email-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/usb/chipidea/ci13xxx_imx.c | 31 ++++++++++---------------------
1 file changed, 10 insertions(+), 21 deletions(-)
diff --git a/drivers/usb/chipidea/ci13xxx_imx.c b/drivers/usb/chipidea/ci13xxx_imx.c
index b598bb8f..1df4b41 100644
--- a/drivers/usb/chipidea/ci13xxx_imx.c
+++ b/drivers/usb/chipidea/ci13xxx_imx.c
@@ -30,7 +30,6 @@
((struct usb_phy *)platform_get_drvdata(pdev))
struct ci13xxx_imx_data {
- struct device_node *phy_np;
struct usb_phy *phy;
struct platform_device *ci_pdev;
struct clk *clk;
@@ -90,12 +89,12 @@ static int ci13xxx_imx_probe(struct platform_device *pdev)
{
struct ci13xxx_imx_data *data;
struct ci13xxx_platform_data *pdata;
- struct platform_device *plat_ci, *phy_pdev;
- struct device_node *phy_np;
+ struct platform_device *plat_ci;
struct resource *res;
struct regulator *reg_vbus;
struct pinctrl *pinctrl;
int ret;
+ struct usb_phy *phy;
if (of_find_property(pdev->dev.of_node, "fsl,usbmisc", NULL)
&& !usbmisc_ops)
@@ -147,18 +146,12 @@ static int ci13xxx_imx_probe(struct platform_device *pdev)
return ret;
}
- phy_np = of_parse_phandle(pdev->dev.of_node, "fsl,usbphy", 0);
- if (phy_np) {
- data->phy_np = phy_np;
- phy_pdev = of_find_device_by_node(phy_np);
- if (phy_pdev) {
- struct usb_phy *phy;
- phy = pdev_to_phy(phy_pdev);
- if (phy &&
- try_module_get(phy_pdev->dev.driver->owner)) {
- usb_phy_init(phy);
- data->phy = phy;
- }
+ phy = devm_usb_get_phy_by_phandle(&pdev->dev, "fsl,usbphy", 0);
+ if (!IS_ERR(phy)) {
+ ret = usb_phy_init(phy);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to init phy: %d\n", ret);
+ goto err_clk;
}
}
@@ -170,7 +163,7 @@ static int ci13xxx_imx_probe(struct platform_device *pdev)
dev_err(&pdev->dev,
"Failed to enable vbus regulator, err=%d\n",
ret);
- goto put_np;
+ goto err_clk;
}
data->reg_vbus = reg_vbus;
} else {
@@ -222,9 +215,7 @@ static int ci13xxx_imx_probe(struct platform_device *pdev)
err:
if (reg_vbus)
regulator_disable(reg_vbus);
-put_np:
- if (phy_np)
- of_node_put(phy_np);
+err_clk:
clk_disable_unprepare(data->clk);
return ret;
}
@@ -244,8 +235,6 @@ static int ci13xxx_imx_remove(struct platform_device *pdev)
module_put(data->phy->dev->driver->owner);
}
- of_node_put(data->phy_np);
-
clk_disable_unprepare(data->clk);
platform_set_drvdata(pdev, NULL);
--
1.7.10.4
^ permalink raw reply related
* [PATCH 1/2] USB mxs-phy: Register phy with framework
From: Sascha Hauer @ 2013-01-31 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359631937-26646-1-git-send-email-s.hauer@pengutronix.de>
We now have usb_add_phy_dev(), so use it to register with the framework
to be able to find the phy from the USB driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/usb/otg/mxs-phy.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/usb/otg/mxs-phy.c b/drivers/usb/otg/mxs-phy.c
index 5158332..5b39885 100644
--- a/drivers/usb/otg/mxs-phy.c
+++ b/drivers/usb/otg/mxs-phy.c
@@ -127,6 +127,7 @@ static int mxs_phy_probe(struct platform_device *pdev)
void __iomem *base;
struct clk *clk;
struct mxs_phy *mxs_phy;
+ int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -166,11 +167,19 @@ static int mxs_phy_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, &mxs_phy->phy);
+ ret = usb_add_phy_dev(&mxs_phy->phy);
+ if (ret)
+ return ret;
+
return 0;
}
static int mxs_phy_remove(struct platform_device *pdev)
{
+ struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);
+
+ usb_remove_phy(&mxs_phy->phy);
+
platform_set_drvdata(pdev, NULL);
return 0;
--
1.7.10.4
^ permalink raw reply related
* [PATCH] USB chipidea i.MX: use framework phy handling
From: Sascha Hauer @ 2013-01-31 11:32 UTC (permalink / raw)
To: linux-arm-kernel
This series switches the mxs phy and the i.MX chipidea support
from homegrew phy support to use usb_add_phy_dev/devm_usb_get_phy_by_phandle.
Based on
[PATCH v2] Add USB of helpers and use them in the chipidea driver
But I think this could also be applied separately if necessary.
Sascha
----------------------------------------------------------------
Sascha Hauer (2):
USB mxs-phy: Register phy with framework
USB chipidea i.MX: use devm_usb_get_phy_by_phandle to get phy
drivers/usb/chipidea/ci13xxx_imx.c | 31 ++++++++++---------------------
drivers/usb/otg/mxs-phy.c | 9 +++++++++
2 files changed, 19 insertions(+), 21 deletions(-)
^ permalink raw reply
* [PATCH v3 1/4] ASoC: tlv320aic3x: Convert mic bias to a supply widget
From: Mark Brown @ 2013-01-31 11:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1BAFE6F6C881BF42822005164F1491C33EB5A48E@DBDE01.ent.ti.com>
On Thu, Jan 31, 2013 at 11:27:07AM +0000, Hebbar, Gururaja wrote:
> On Thu, Jan 31, 2013 at 16:54:16, Mark Brown wrote:
> > As mentioned when you posted this before this patch needs to update the
> > machine drivers using the device too.
> The patch-set 2/4 does the same thing. Since I have da850-evm at my end, I
> have modified that machine driver and sent-it as 2/4.
Two problems here. One is that the update should be done in the same
patch and the other is that you need to update *all* the machine drivers
using the device, not just one of them.
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