* [PATCH v3 12/15] drivers/bus: add ARM CCI support
From: Santosh Shilimkar @ 2013-02-01 6:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359445870-18925-13-git-send-email-nicolas.pitre@linaro.org>
On Tuesday 29 January 2013 01:21 PM, Nicolas Pitre wrote:
> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>
> On ARM multi-cluster systems coherency between cores running on
> different clusters is managed by the cache-coherent interconnect (CCI).
> It allows broadcasting of TLB invalidates and memory barriers and it
> guarantees cache coherency at system level.
>
> This patch enables the basic infrastructure required in Linux to
> handle and programme the CCI component. The first implementation is
> based on a platform device, its relative DT compatible property and
> a simple programming interface.
>
> Signed-off-by: Nicolas Pitre <nico@linaro.org>
> ---
> drivers/bus/Kconfig | 4 ++
> drivers/bus/Makefile | 2 +
> drivers/bus/arm-cci.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++
> include/linux/arm-cci.h | 30 ++++++++++++++
> 4 files changed, 143 insertions(+)
> create mode 100644 drivers/bus/arm-cci.c
> create mode 100644 include/linux/arm-cci.h
>
> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
> index 0f51ed687d..d032f74ff2 100644
> --- a/drivers/bus/Kconfig
> +++ b/drivers/bus/Kconfig
> @@ -19,4 +19,8 @@ config OMAP_INTERCONNECT
>
> help
> Driver to enable OMAP interconnect error handling driver.
> +
> +config ARM_CCI
> + bool "ARM CCI driver support"
> +
> endmenu
> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
> index 45d997c854..55aac809e5 100644
> --- a/drivers/bus/Makefile
> +++ b/drivers/bus/Makefile
> @@ -6,3 +6,5 @@ obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
>
> # Interconnect bus driver for OMAP SoCs.
> obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
> +
> +obj-$(CONFIG_ARM_CCI) += arm-cci.o
> diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
> new file mode 100644
> index 0000000000..25ae156924
> --- /dev/null
> +++ b/drivers/bus/arm-cci.c
> @@ -0,0 +1,107 @@
> +/*
> + * ARM Cache Coherency Interconnect (CCI400) support
> + *
> + * Copyright (C) 2012-2013 ARM Ltd.
> + * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/arm-cci.h>
> +
> +#define CCI400_EAG_OFFSET 0x4000
> +#define CCI400_KF_OFFSET 0x5000
> +
> +#define DRIVER_NAME "CCI"
> +struct cci_drvdata {
> + void __iomem *baseaddr;
> + spinlock_t lock;
> +};
> +
> +static struct cci_drvdata *info;
> +
> +void disable_cci(int cluster)
> +{
> + u32 cci_reg = cluster ? CCI400_KF_OFFSET : CCI400_EAG_OFFSET;
> + writel_relaxed(0x0, info->baseaddr + cci_reg);
> +
> + while (readl_relaxed(info->baseaddr + 0xc) & 0x1)
0xc ? Is that a status register ? A define for the same would be
good. Rest of the patch looks fine.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply
* [PATCH v6 03/10] ARM: edma: add AM33XX support to the private EDMA API
From: Luciano Coelho @ 2013-02-01 6:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130131214241.GJ2244@beef>
On Thu, 2013-01-31 at 16:42 -0500, Matt Porter wrote:
> On Thu, Jan 31, 2013 at 08:58:39PM +0000, Arnd Bergmann wrote:
> > On Thursday 31 January 2013, Matt Porter wrote:
> > > On Wed, Jan 30, 2013 at 09:32:58AM +0000, Arnd Bergmann wrote:
> > > > On Wednesday 30 January 2013, Matt Porter wrote:
> > > > > + dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
> > > > > + of_dma_controller_register(dev->of_node,
> > > > > + of_dma_simple_xlate,
> > > > > + &edma_filter_info);
> > > > > + }
> > > >
> > > > How do you actually deal with the problem mentioned by Padma, that
> > > > the filter function does not know which edma instance it is looking
> > > > at? If you assume that there can only be a single edma instance in
> > > > the system, that is probably a limitation that should be documented
> > > > somewhere, and ideally the probe() function should check for that.
> > >
> > > I make an assumption of one edma instance in the system in the case of
> > > DT being populated. This is always true right now as the only SoC with
> > > two EDMA controllers in existence is Davinci DA850. Until recently,
> > > Davinci had no DT support. Given the steady work being done today on DT
> > > support for DA850, it'll probably be something needed in 3.10.
> > >
> > > I will add a comment and check in probe() to capture this assumption
> > > and then plan to update separately to support DA850 booting from DT.
> >
> > Ok, sounds good. Hopefully by then we will already have a nicer
> > way to write an xlate function that does not rely on a filter
> > function.
>
> Yes, it would be nice to avoid what Padma had to do. I should have
> mentioned also that the second EDMA on DA850 has no DMA events of
> immediate use on it anyway. All the in-kernel users use events on the
> first controller, except for the second MMC instance. That's only used
> for a wl12xx module on the EVM and that driver has no DT support so it
> doesn't matter yet in the DT case. Because of this, DA850 can actually
> add EDMA DT support immediately (on top of this series) and add DMA
> support to the DT support already posted for the Davinci SPI and MMC
> client drivers.
I haven't followed this whole discussion in details, but please notice
that I'm aiming to get DT support for the WiLink modules (wlcore,
wl12xx...) for 3.10. ;)
--
Cheers,
Luca.
^ permalink raw reply
* [PATCH v3 11/15] ARM: vexpress/dcscb: do not hardcode number of CPUs per cluster
From: Santosh Shilimkar @ 2013-02-01 5:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359445870-18925-12-git-send-email-nicolas.pitre@linaro.org>
On Tuesday 29 January 2013 01:21 PM, Nicolas Pitre wrote:
> If 4 CPUs are assumed, the A15x1-A7x1 model configuration would never
> shut down the initial cluster as the 0xf reset bit mask will never be
> observed. Let's construct this mask based on the provided information
> in the DCSCB config register for the number of CPUs per cluster.
>
> Signed-off-by: Nicolas Pitre <nico@linaro.org>
> ---
> arch/arm/mach-vexpress/dcscb.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
> index f993608944..8d363357ef 100644
> --- a/arch/arm/mach-vexpress/dcscb.c
> +++ b/arch/arm/mach-vexpress/dcscb.c
> @@ -46,10 +46,12 @@ static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
>
> static void __iomem *dcscb_base;
> static int dcscb_use_count[4][2];
> +static int dcscb_mcpm_cpu_mask[2];
s/2/MAX_CLUSTERS ?
Apart from above minor question,
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply
* [PATCH v3 10/15] ARM: vexpress/dcscb: add CPU use counts to the power up/down API implementation
From: Santosh Shilimkar @ 2013-02-01 5:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359445870-18925-11-git-send-email-nicolas.pitre@linaro.org>
On Tuesday 29 January 2013 01:21 PM, Nicolas Pitre wrote:
> It is possible for a CPU to be told to power up before it managed
> to power itself down. Solve this race with a usage count as mandated
> by the API definition.
>
> Signed-off-by: nicolas Pitre <nico@linaro.org>
> ---
> arch/arm/mach-vexpress/dcscb.c | 77 +++++++++++++++++++++++++++++++++---------
> 1 file changed, 61 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
> index 677ced9efc..f993608944 100644
> --- a/arch/arm/mach-vexpress/dcscb.c
> +++ b/arch/arm/mach-vexpress/dcscb.c
> @@ -45,6 +45,7 @@
> static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
>
> static void __iomem *dcscb_base;
> +static int dcscb_use_count[4][2];
>
> static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
> {
> @@ -61,14 +62,27 @@ static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
> local_irq_disable();
> arch_spin_lock(&dcscb_lock);
>
> - rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
> - if (rst_hold & (1 << 8)) {
> - /* remove cluster reset and add individual CPU's reset */
> - rst_hold &= ~(1 << 8);
> - rst_hold |= 0xf;
> + dcscb_use_count[cpu][cluster]++;
> + if (dcscb_use_count[cpu][cluster] == 1) {
> + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
> + if (rst_hold & (1 << 8)) {
> + /* remove cluster reset and add individual CPU's reset */
> + rst_hold &= ~(1 << 8);
> + rst_hold |= 0xf;
> + }
> + rst_hold &= ~(cpumask | (cpumask << 4));
> + writel(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
> + } else if (dcscb_use_count[cpu][cluster] != 2) {
> + /*
> + * The only possible values are:
> + * 0 = CPU down
> + * 1 = CPU (still) up
> + * 2 = CPU requested to be up before it had a chance
> + * to actually make itself down.
> + * Any other value is a bug.
> + */
> + BUG();
No strong opinion but would switch case be better here ?
> }
> - rst_hold &= ~(cpumask | (cpumask << 4));
> - writel(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
>
> arch_spin_unlock(&dcscb_lock);
> local_irq_enable();
> @@ -78,7 +92,8 @@ static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
>
> static void dcscb_power_down(void)
> {
> - unsigned int mpidr, cpu, cluster, rst_hold, cpumask, last_man;
> + unsigned int mpidr, cpu, cluster, rst_hold, cpumask;
> + bool last_man = false, skip_wfi = false;
>
> mpidr = read_cpuid_mpidr();
> cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> @@ -89,13 +104,26 @@ static void dcscb_power_down(void)
> BUG_ON(cpu >= 4 || cluster >= 2);
>
> arch_spin_lock(&dcscb_lock);
> - rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
> - rst_hold |= cpumask;
> - if (((rst_hold | (rst_hold >> 4)) & 0xf) == 0xf)
> - rst_hold |= (1 << 8);
> - writel(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
> + dcscb_use_count[cpu][cluster]--;
> + if (dcscb_use_count[cpu][cluster] == 0) {
> + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
> + rst_hold |= cpumask;
> + if (((rst_hold | (rst_hold >> 4)) & 0xf) == 0xf) {
> + rst_hold |= (1 << 8);
> + last_man = true;
> + }
> + writel(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
> + } else if (dcscb_use_count[cpu][cluster] == 1) {
> + /*
> + * A power_up request went ahead of us.
> + * Even if we do not want to shut this CPU down,
> + * the caller expects a certain state as if the WFI
> + * was aborted. So let's continue with cache cleaning.
> + */
> + skip_wfi = true;
> + } else
> + BUG();
Same comment as above.
Rest looks fine.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply
* [PATCH v3 09/15] ARM: vexpress: introduce DCSCB support
From: Santosh Shilimkar @ 2013-02-01 5:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359445870-18925-10-git-send-email-nicolas.pitre@linaro.org>
On Tuesday 29 January 2013 01:21 PM, Nicolas Pitre wrote:
> This adds basic CPU and cluster reset controls on RTSM for the
> A15x4-A7x4 model configuration using the Dual Cluster System
> Configuration Block (DCSCB).
>
> The cache coherency interconnect (CCI) is not handled yet.
>
> Signed-off-by: Nicolas Pitre <nico@linaro.org>
> ---
> arch/arm/mach-vexpress/Kconfig | 8 ++
> arch/arm/mach-vexpress/Makefile | 1 +
> arch/arm/mach-vexpress/dcscb.c | 159 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 168 insertions(+)
> create mode 100644 arch/arm/mach-vexpress/dcscb.c
>
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index 52d315b792..f3f92b120a 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -52,4 +52,12 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
> config ARCH_VEXPRESS_CA9X4
> bool "Versatile Express Cortex-A9x4 tile"
>
> +config ARCH_VEXPRESS_DCSCB
> + bool "Dual Cluster System Control Block (DCSCB) support"
> + depends on CLUSTER_PM
> + help
> + Support for the Dual Cluster System Configuration Block (DCSCB).
> + This is needed to provide CPU and cluster power management
> + on RTSM.
> +
> endmenu
> diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
> index 80b64971fb..2253644054 100644
> --- a/arch/arm/mach-vexpress/Makefile
> +++ b/arch/arm/mach-vexpress/Makefile
> @@ -6,5 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
>
> obj-y := v2m.o reset.o
> obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
> +obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o
> obj-$(CONFIG_SMP) += platsmp.o
> obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
> diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
> new file mode 100644
> index 0000000000..677ced9efc
> --- /dev/null
> +++ b/arch/arm/mach-vexpress/dcscb.c
> @@ -0,0 +1,159 @@
> +/*
> + * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Control Block
> + *
> + * Created by: Nicolas Pitre, May 2012
> + * Copyright: (C) 2012-2013 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/io.h>
> +#include <linux/spinlock.h>
> +#include <linux/errno.h>
> +#include <linux/vexpress.h>
> +
> +#include <asm/mcpm_entry.h>
> +#include <asm/proc-fns.h>
> +#include <asm/cacheflush.h>
> +#include <asm/cputype.h>
> +#include <asm/cp15.h>
> +
> +
> +#define DCSCB_PHYS_BASE 0x60000000
> +
> +#define RST_HOLD0 0x0
> +#define RST_HOLD1 0x4
> +#define SYS_SWRESET 0x8
> +#define RST_STAT0 0xc
> +#define RST_STAT1 0x10
> +#define EAG_CFG_R 0x20
> +#define EAG_CFG_W 0x24
> +#define KFC_CFG_R 0x28
> +#define KFC_CFG_W 0x2c
> +#define DCS_CFG_R 0x30
> +
> +/*
> + * We can't use regular spinlocks. In the switcher case, it is possible
> + * for an outbound CPU to call power_down() after its inbound counterpart
> + * is already live using the same logical CPU number which trips lockdep
> + * debugging.
> + */
> +static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
> +
> +static void __iomem *dcscb_base;
> +
> +static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
> +{
> + unsigned int rst_hold, cpumask = (1 << cpu);
> +
> + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> + if (cpu >= 4 || cluster >= 2)
Is this a CCI limitation ?
> + return -EINVAL;
> +
> + /*
> + * Since this is called with IRQs enabled, and no arch_spin_lock_irq
> + * variant exists, we need to disable IRQs manually here.
> + */
> + local_irq_disable();
> + arch_spin_lock(&dcscb_lock);
> +
> + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
> + if (rst_hold & (1 << 8)) {
> + /* remove cluster reset and add individual CPU's reset */
> + rst_hold &= ~(1 << 8);
> + rst_hold |= 0xf;
> + }
> + rst_hold &= ~(cpumask | (cpumask << 4));
> + writel(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
> +
> + arch_spin_unlock(&dcscb_lock);
> + local_irq_enable();
> +
> + return 0;
> +}
> +
> +static void dcscb_power_down(void)
> +{
> + unsigned int mpidr, cpu, cluster, rst_hold, cpumask, last_man;
> +
> + mpidr = read_cpuid_mpidr();
> + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> + cpumask = (1 << cpu);
> +
> + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> + BUG_ON(cpu >= 4 || cluster >= 2);
> +
> + arch_spin_lock(&dcscb_lock);
> + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
> + rst_hold |= cpumask;
> + if (((rst_hold | (rst_hold >> 4)) & 0xf) == 0xf)
> + rst_hold |= (1 << 8);
> + writel(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
> + arch_spin_unlock(&dcscb_lock);
> + last_man = (rst_hold & (1 << 8));
> +
> + /*
> + * Now let's clean our L1 cache and shut ourself down.
> + * If we're the last CPU in this cluster then clean L2 too.
> + */
> +
How about merging these two comments ?
> + /*
> + * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
> + * a preliminary flush here for those CPUs. At least, that's
> + * the theory -- without the extra flush, Linux explodes on
> + * RTSM (maybe not needed anymore, to be investigated)..
> + */
> + flush_cache_louis();
> + cpu_proc_fin();
Lorenzo already noticed the I cache getting disable here.
That should be fixed. Rest of the patch looks fine.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply
* [PATCH v3 08/15] ARM: introduce common set_auxcr/get_auxcr functions
From: Santosh Shilimkar @ 2013-02-01 5:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359445870-18925-9-git-send-email-nicolas.pitre@linaro.org>
On Tuesday 29 January 2013 01:21 PM, Nicolas Pitre wrote:
> From: Rob Herring <rob.herring@calxeda.com>
>
> Move the private set_auxcr/get_auxcr functions from
> drivers/cpuidle/cpuidle-calxeda.c so they can be used across platforms.
>
> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Acked-by: Tony Lindgren <tony@atomide.com>
> Signed-off-by: Nicolas Pitre <nico@linaro.org>
> ---
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply
* [PATCH v3 07/15] ARM: vexpress: Select the correct SMP operations at run-time
From: Santosh Shilimkar @ 2013-02-01 5:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359445870-18925-8-git-send-email-nicolas.pitre@linaro.org>
On Tuesday 29 January 2013 01:21 PM, Nicolas Pitre wrote:
> From: Jon Medhurst <tixy@linaro.org>
>
The patch deserves couple of lines of description here.
> Signed-off-by: Jon Medhurst <tixy@linaro.org>
> ---
> arch/arm/include/asm/mach/arch.h | 3 +++
> arch/arm/kernel/setup.c | 5 ++++-
> arch/arm/mach-vexpress/core.h | 2 ++
> arch/arm/mach-vexpress/platsmp.c | 12 ++++++++++++
> arch/arm/mach-vexpress/v2m.c | 2 +-
> 5 files changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
> index 917d4fcfd9..3d01c6d6c3 100644
> --- a/arch/arm/include/asm/mach/arch.h
> +++ b/arch/arm/include/asm/mach/arch.h
> @@ -17,8 +17,10 @@ struct pt_regs;
> struct smp_operations;
> #ifdef CONFIG_SMP
> #define smp_ops(ops) (&(ops))
> +#define smp_init_ops(ops) (&(ops))
> #else
> #define smp_ops(ops) (struct smp_operations *)NULL
> +#define smp_init_ops(ops) (void (*)(void))NULL
> #endif
>
> struct machine_desc {
> @@ -42,6 +44,7 @@ struct machine_desc {
> unsigned char reserve_lp2 :1; /* never has lp2 */
> char restart_mode; /* default restart mode */
> struct smp_operations *smp; /* SMP operations */
> + void (*smp_init)(void);
> void (*fixup)(struct tag *, char **,
> struct meminfo *);
> void (*reserve)(void);/* reserve mem blocks */
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index 3f6cbb2e3e..41edca8582 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -768,7 +768,10 @@ void __init setup_arch(char **cmdline_p)
> arm_dt_init_cpu_maps();
> #ifdef CONFIG_SMP
> if (is_smp()) {
> - smp_set_ops(mdesc->smp);
> + if(mdesc->smp_init)
> + (*mdesc->smp_init)();
> + else
> + smp_set_ops(mdesc->smp);
> smp_init_cpus();
> }
> #endif
> diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
> index f134cd4a85..3a761fd76c 100644
> --- a/arch/arm/mach-vexpress/core.h
> +++ b/arch/arm/mach-vexpress/core.h
> @@ -6,6 +6,8 @@
>
> void vexpress_dt_smp_map_io(void);
>
> +void vexpress_smp_init_ops(void);
> +
> extern struct smp_operations vexpress_smp_ops;
>
> extern void vexpress_cpu_die(unsigned int cpu);
> diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
> index c5d70de9bb..667344b479 100644
> --- a/arch/arm/mach-vexpress/platsmp.c
> +++ b/arch/arm/mach-vexpress/platsmp.c
> @@ -12,6 +12,7 @@
> #include <linux/errno.h>
> #include <linux/smp.h>
> #include <linux/io.h>
> +#include <linux/of.h>
> #include <linux/of_fdt.h>
> #include <linux/vexpress.h>
>
> @@ -206,3 +207,14 @@ struct smp_operations __initdata vexpress_smp_ops = {
> .cpu_die = vexpress_cpu_die,
> #endif
> };
> +
> +void __init vexpress_smp_init_ops(void)
> +{
> + struct smp_operations *ops = &vexpress_smp_ops;
> +#ifdef CONFIG_CLUSTER_PM
See if you can avoid this #ifdef in the middle of function.
Reviewed-by: Santosh Shilimkar<santosh.shilimkar@ti.com>
^ permalink raw reply
* [PATCH v4 02/13] ARM: LPAE: use phys_addr_t in alloc_init_pud()
From: Hui Wang @ 2013-02-01 5:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1301312218270.6300@xanadu.home>
Nicolas Pitre wrote:
> On Fri, 1 Feb 2013, Hui Wang wrote:
>
>
>> Cyril Chemparathy wrote:
>>
>>> From: Vitaly Andrianov <vitalya@ti.com>
>>>
>>> This patch fixes the alloc_init_pud() function to use phys_addr_t instead of
>>> unsigned long when passing in the phys argument.
>>>
>>> This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a
>>> (ARM:
>>> pgtable: use phys_addr_t for physical addresses), which applied similar
>>> changes
>>> elsewhere in the ARM memory management code.
>>>
>>> Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
>>> Signed-off-by: Cyril Chemparathy <cyril@ti.com>
>>> Acked-by: Nicolas Pitre <nico@linaro.org>
>>> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
>>> ---
>>> arch/arm/mm/mmu.c | 3 ++-
>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
>>> index 9f06102..ef43689 100644
>>> --- a/arch/arm/mm/mmu.c
>>> +++ b/arch/arm/mm/mmu.c
>>> @@ -612,7 +612,8 @@ static void __init alloc_init_section(pud_t *pud,
>>> unsigned long addr,
>>> }
>>> static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
>>> - unsigned long end, unsigned long phys, const struct mem_type *type)
>>> + unsigned long end, phys_addr_t phys,
>>> + const struct mem_type *type)
>>>
>>>
>> The change is correct but seems useless so far. This function only be called
>> from map_lowmem and devicemaps_init, from i know neither lowmem nor device io
>> registers of existing platforms exceed 32bit address.
>>
>
> It is not because you are not aware of any existing platforms with RAM
> or device IO above the 4GB mark that they don't exist.
>
> For example, some LPAE systems have all their RAM located above the 4G
> physical address mark. A simple (potentially non DMA capable) alias
> exists in the low 32-bit address space to allow the system to boot and
> switch to the real physical RAM addresses once the MMU is turned on.
> Some of that RAM is still qualified as "low mem" i.e. the portion of RAM
> that the kernel keeps permanently mapped in the 32-bit virtual space
> even if all of it is above the 4G mark in physical space.
>
>
>
Got it, thanks for sharing the knowledge.
Regards,
Hui.
> Nicolas
>
>
^ permalink raw reply
* [PATCH v3 06/15] ARM: mcpm: generic SMP secondary bringup and hotplug support
From: Santosh Shilimkar @ 2013-02-01 5:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359445870-18925-7-git-send-email-nicolas.pitre@linaro.org>
On Tuesday 29 January 2013 01:21 PM, Nicolas Pitre wrote:
> Now that the cluster power API is in place, we can use it for SMP secondary
> bringup and CPU hotplug in a generic fashion.
>
> Signed-off-by: Nicolas Pitre <nico@linaro.org>
> ---
> arch/arm/common/Makefile | 2 +-
> arch/arm/common/mcpm_platsmp.c | 85 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 86 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/common/mcpm_platsmp.c
>
> diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
> index c901a38c59..e1c9db45de 100644
> --- a/arch/arm/common/Makefile
> +++ b/arch/arm/common/Makefile
> @@ -13,4 +13,4 @@ obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
> obj-$(CONFIG_SHARP_SCOOP) += scoop.o
> obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
> obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
> -obj-$(CONFIG_CLUSTER_PM) += mcpm_head.o mcpm_entry.o vlock.o
> +obj-$(CONFIG_CLUSTER_PM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
> diff --git a/arch/arm/common/mcpm_platsmp.c b/arch/arm/common/mcpm_platsmp.c
> new file mode 100644
> index 0000000000..401298f5ee
> --- /dev/null
> +++ b/arch/arm/common/mcpm_platsmp.c
> @@ -0,0 +1,85 @@
> +/*
> + * linux/arch/arm/mach-vexpress/mcpm_platsmp.c
> + *
> + * Created by: Nicolas Pitre, November 2012
> + * Copyright: (C) 2012-2013 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Code to handle secondary CPU bringup and hotplug for the cluster power API.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/smp.h>
> +
> +#include <asm/mcpm_entry.h>
> +#include <asm/smp_plat.h>
> +#include <asm/hardware/gic.h>
> +
> +static void __init simple_smp_init_cpus(void)
> +{
> + set_smp_cross_call(gic_raise_softirq);
> +}
> +
> +static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> + unsigned int mpidr, pcpu, pcluster, ret;
> + extern void secondary_startup(void);
> +
> + mpidr = cpu_logical_map(cpu);
> + pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> + pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> + pr_debug("%s: logical CPU %d is physical CPU %d cluster %d\n",
> + __func__, cpu, pcpu, pcluster);
> +
> + mcpm_set_entry_vector(pcpu, pcluster, NULL);
> + ret = mcpm_cpu_power_up(pcpu, pcluster);
> + if (ret)
> + return ret;
> + mcpm_set_entry_vector(pcpu, pcluster, secondary_startup);
> + gic_raise_softirq(cpumask_of(cpu), 0);
> + dsb_sev();
> + return 0;
> +}
> +
> +static void __cpuinit mcpm_secondary_init(unsigned int cpu)
> +{
> + mcpm_cpu_powered_up();
> + gic_secondary_init(0);
This gic init should not be needed with Catalin's notifier
series. Some thing to be removed based on when that series
gets in.
Reviewed-by: Santosh Shilimkar<santosh.shilimkar@ti.com>
^ permalink raw reply
* [PATCH] ARM: dts: AM33XX: Corrects typo in interrupt field in SPI node
From: Philip Avinash @ 2013-02-01 5:37 UTC (permalink / raw)
To: linux-arm-kernel
DT field of "interrupts" was mentioned wrongly as "interrupt" in SPI
node. This went unnoticed as spi-omap2 driver not making use of
interrupt. Fixes the typo.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
---
arch/arm/boot/dts/am33xx.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index fbcb90b..cece3ad 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -309,7 +309,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x48030000 0x400>;
- interrupt = <65>;
+ interrupts = <65>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi0";
status = "disabled";
@@ -320,7 +320,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x481a0000 0x400>;
- interrupt = <125>;
+ interrupts = <125>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi1";
status = "disabled";
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 05/15] ARM: mcpm_head.S: vlock-based first man election
From: Santosh Shilimkar @ 2013-02-01 5:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359445870-18925-6-git-send-email-nicolas.pitre@linaro.org>
On Tuesday 29 January 2013 01:21 PM, Nicolas Pitre wrote:
> From: Dave Martin <dave.martin@linaro.org>
>
> Instead of requiring the first man to be elected in advance (which
> can be suboptimal in some situations), this patch uses a per-
> cluster mutex to co-ordinate selection of the first man.
>
> This should also make it more feasible to reuse this code path for
> asynchronous cluster resume (as in CPUidle scenarios).
>
> We must ensure that the vlock data doesn't share a cacheline with
> anything else, or dirty cache eviction could corrupt it.
>
> Signed-off-by: Dave Martin <dave.martin@linaro.org>
> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
> ---
Reviewed-by: Santosh Shilimkar<santosh.shilimkar@ti.com>
Regards,
Santosh
^ permalink raw reply
* [PATCH v3 04/15] ARM: mcpm: Add baremetal voting mutexes
From: Santosh Shilimkar @ 2013-02-01 5:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359445870-18925-5-git-send-email-nicolas.pitre@linaro.org>
On Tuesday 29 January 2013 01:20 PM, Nicolas Pitre wrote:
> From: Dave Martin <dave.martin@linaro.org>
>
> This patch adds a simple low-level voting mutex implementation
> to be used to arbitrate during first man selection when no load/store
> exclusive instructions are usable.
>
> For want of a better name, these are called "vlocks". (I was
> tempted to call them ballot locks, but "block" is way too confusing
> an abbreviation...)
>
> There is no function to wait for the lock to be released, and no
> vlock_lock() function since we don't need these at the moment.
> These could straightforwardly be added if vlocks get used for other
> purposes.
>
> For architectural correctness even Strongly-Ordered memory accesses
> require barriers in order to guarantee that multiple CPUs have a
> coherent view of the ordering of memory accesses. Whether or not
> this matters depends on hardware implementation details of the
> memory system. Since the purpose of this code is to provide a clean,
> generic locking mechanism with no platform-specific dependencies the
> barriers should be present to avoid unpleasant surprises on future
> platforms.
>
> Note:
>
> * When taking the lock, we don't care about implicit background
> memory operations and other signalling which may be pending,
> because those are not part of the critical section anyway.
>
> A DMB is sufficient to ensure correctly observed ordering if
> the explicit memory accesses in vlock_trylock.
>
> * No barrier is required after checking the election result,
> because the result is determined by the store to
> VLOCK_OWNER_OFFSET and is already globally observed due to the
> barriers in voting_end. This means that global agreement on
> the winner is guaranteed, even before the winner is known
> locally.
>
> Signed-off-by: Dave Martin <dave.martin@linaro.org>
> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
> ---
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply
* [PATCH v3 03/15] ARM: mcpm: introduce helpers for platform coherency exit/setup
From: Santosh Shilimkar @ 2013-02-01 5:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1301311210040.6300@xanadu.home>
On Thursday 31 January 2013 10:46 PM, Nicolas Pitre wrote:
> On Thu, 31 Jan 2013, Santosh Shilimkar wrote:
>
>> On Tuesday 29 January 2013 01:20 PM, Nicolas Pitre wrote:
>>> From: Dave Martin <dave.martin@linaro.org>
>>>
>>> This provides helper methods to coordinate between CPUs coming down
>>> and CPUs going up, as well as documentation on the used algorithms,
>>> so that cluster teardown and setup
>>> operations are not done for a cluster simultaneously.
>>>
>>> For use in the power_down() implementation:
>>> * __mcpm_cpu_going_down(unsigned int cluster, unsigned int cpu)
>>> * __mcpm_outbound_enter_critical(unsigned int cluster)
>>> * __mcpm_outbound_leave_critical(unsigned int cluster)
>>> * __mcpm_cpu_down(unsigned int cluster, unsigned int cpu)
>>>
>>> The power_up_setup() helper should do platform-specific setup in
>>> preparation for turning the CPU on, such as invalidating local caches
>>> or entering coherency. It must be assembler for now, since it must
>>> run before the MMU can be switched on. It is passed the affinity level
>>> which should be initialized.
>>>
>>> Because the mcpm_sync_struct content is looked-up and modified
>>> with the cache enabled or disabled depending on the code path, it is
>>> crucial to always ensure proper cache maintenance to update main memory
>>> right away. Therefore, any cached write must be followed by a cache
>>> clean operation and any cached read must be preceded by a cache
>>> invalidate operation (actually a cache flush i.e. clean+invalidate to
>>> avoid discarding possible concurrent writes) on the accessed memory.
>>>
>>> Also, in order to prevent a cached writer from interfering with an
>>> adjacent non-cached writer, we ensure each state variable is located to
>>> a separate cache line.
>>>
>>> Thanks to Nicolas Pitre and Achin Gupta for the help with this
>>> patch.
>>>
>>> Signed-off-by: Dave Martin <dave.martin@linaro.org>
>>> ---
>> [..]
>>
>>> diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c
>>> index c8c0e2113e..2b83121966 100644
>>> --- a/arch/arm/common/mcpm_entry.c
>>> +++ b/arch/arm/common/mcpm_entry.c
>>> @@ -18,6 +18,7 @@
>>> #include <asm/proc-fns.h>
>>> #include <asm/cacheflush.h>
>>> #include <asm/idmap.h>
>>> +#include <asm/cputype.h>
>>>
>>> extern volatile unsigned long
>>> mcpm_entry_vectors[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER];
>>>
>> [...]
>>
>>> +/*
>>> + * Ensure preceding writes to *p by other CPUs are visible to
>>> + * subsequent reads by this CPU. We must be careful not to
>>> + * discard data simultaneously written by another CPU, hence the
>>> + * usage of flush rather than invalidate operations.
>>> + */
>>> +static void __sync_range_r(volatile void *p, size_t size)
>>> +{
>>> + char *_p = (char *)p;
>>> +
>>> +#ifdef CONFIG_OUTER_CACHE
>>> + if (outer_cache.flush_range) {
>>> +
>> You don't need above #ifdef. In case of non-outer
>> cache the function pointer is null anyways.
>
> We do need the #ifdef, because if CONFIG_OUTER_CACHE is not selected
> then the outer_cache structure simply doesn't exist.
>
You are right. #ifdef in middle of the code looks bit ugly and hence
was thinking to avoid it.
>> /*
>>> + * Ensure dirty data migrated from other CPUs into our cache
>>> + * are cleaned out safely before the outer cache is cleaned:
>>> + */
>>> + __cpuc_clean_dcache_area(_p, size);
>>> +
>>> + /* Clean and invalidate stale data for *p from outer ... */
>>> + outer_flush_range(__pa(_p), __pa(_p + size));
>>> + }
>>> +#endif
>>> +
>>> + /* ... and inner cache: */
>>> + __cpuc_flush_dcache_area(_p, size);
>> This will be un-necessary when inner cache is available, no ?
>> May be you can re-arrange the code like below, unless and until
>> you would like to invalidate any speculative fetches during the
>> outer_flush_range()
>>
>> __cpuc_clean_dcache_area(_p, size);
>> if (outer_cache.flush_range)
>> outer_flush_range(__pa(_p), __pa(_p + size));
>
> As you said, the code is sequenced that way to get rid of potential
> speculative fetch that could happen right before L2 is flushed.
>
Thanks for clarifying it. It makes sense.
Regards,
Santosh
^ permalink raw reply
* [Patch v2 2/2] ARM: OMAP2: am33xx-hwmod: Fix "register offset NULL check" bug
From: Hebbar, Gururaja @ 2013-02-01 5:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1301311528320.23099@utopia.booyaka.com>
On Thu, Jan 31, 2013 at 21:00:32, Paul Walmsley wrote:
> + Koen
>
> Hi
>
> On Thu, 31 Jan 2013, Hebbar Gururaja wrote:
>
> > am33xx_cm_wait_module_ready() checks if register offset is NULL.
> >
> > int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
> > {
> > int i = 0;
> >
> > if (!clkctrl_offs)
> > return 0;
> >
> > In case of AM33xx, CLKCTRL register offset for different clock domains
> > are not uniformly placed. An example of this would be the RTC clock
> > domain with CLKCTRL offset at 0x00.
> > In such cases the module ready check is skipped which leads to a data
> > abort during boot-up when RTC registers is accessed.
> >
> > Remove this check here to avoid checking module readiness for modules
> > with clkctrl register offset at 0x00.
> >
> > Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
>
> Some text has been added to the patch description to describe Koen's test
> results, and the updated patch has been queued for v3.8-rc fixes. Updated
> patch follows.
>
> - Paul
Thanks for the review & update.
Regards,
Gururaja
>
> From: Hebbar Gururaja <gururaja.hebbar@ti.com>
> Date: Thu, 31 Jan 2013 19:55:27 +0530
> Subject: [PATCH] ARM: OMAP2: am33xx-hwmod: Fix "register offset NULL check"
> bug
>
> am33xx_cm_wait_module_ready() checks if register offset is NULL.
>
> int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
> {
> int i = 0;
>
> if (!clkctrl_offs)
> return 0;
>
> In case of AM33xx, CLKCTRL register offset for different clock domains
> are not uniformly placed. An example of this would be the RTC clock
> domain with CLKCTRL offset at 0x00.
> In such cases the module ready check is skipped which leads to a data
> abort during boot-up when RTC registers is accessed.
>
> Remove this check here to avoid checking module readiness for modules
> with clkctrl register offset at 0x00.
>
> Koen Kooi notes that this patch fixes a crash on boot with
> CONFIG_RTC_DRV_OMAP=y with v3.8-rc5.
>
> Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
> Cc: Koen Kooi <koen@dominion.thruhere.net>
> [paul at pwsan.com: noted Koen's test in the patch description]
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
> arch/arm/mach-omap2/cm33xx.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
> index 058ce3c..325a515 100644
> --- a/arch/arm/mach-omap2/cm33xx.c
> +++ b/arch/arm/mach-omap2/cm33xx.c
> @@ -241,9 +241,6 @@ int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
> {
> int i = 0;
>
> - if (!clkctrl_offs)
> - return 0;
> -
> omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
> MAX_MODULE_READY_TIME, i);
>
> --
> 1.7.10.4
>
>
^ permalink raw reply
* [Patch v2 1/2] ARM: OMAP2+: AM33xx: hwmod: add missing HWMOD_NO_IDLEST flags
From: Hebbar, Gururaja @ 2013-02-01 5:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1301311527190.23099@utopia.booyaka.com>
On Thu, Jan 31, 2013 at 20:58:24, Paul Walmsley wrote:
> Hi
>
> On Thu, 31 Jan 2013, Hebbar Gururaja wrote:
>
> > struct omap_hwmod records belonging to wkup m3 domain is missing
> > HWMOD_NO_IDLEST flags; add them.
> >
> > Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
>
> I've modified this patch to add some more description of why it's needed
> as a fix, and queued it for v3.8-rc fixes.
>
> Updated patch follows.
Thanks for the review & update.
Regards,
Gururaja
>
>
> - Paul
>
> From: Hebbar Gururaja <gururaja.hebbar@ti.com>
> Date: Thu, 31 Jan 2013 19:55:26 +0530
> Subject: [PATCH] ARM: OMAP2+: AM33xx: hwmod: add missing HWMOD_NO_IDLEST
> flags
>
> struct omap_hwmod records belonging to wkup m3 domain is missing
> HWMOD_NO_IDLEST flags; add them.
>
> This patch is a prerequisite for a subsequent patch, 'ARM: OMAP2:
> am33xx-hwmod: Fix "register offset NULL check" bug'. That patch would
> otherwise attempt to read from reserved bits.
>
> Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
> [paul at pwsan.com: add some more explanation in the patch description]
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> index 646c14d..1ab693e 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -262,7 +262,8 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
> .name = "wkup_m3",
> .class = &am33xx_wkup_m3_hwmod_class,
> .clkdm_name = "l4_wkup_aon_clkdm",
> - .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
> + /* Keep hardreset asserted */
> + .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
> .mpu_irqs = am33xx_wkup_m3_irqs,
> .main_clk = "dpll_core_m4_div2_ck",
> .prcm = {
> --
> 1.7.10.4
>
>
^ permalink raw reply
* [PATCH 2/7] clk: tegra: Use common of_clk_init() function
From: Prashant Gaikwad @ 2013-02-01 4:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <51020D94.4010509@wwwdotorg.org>
On Friday 25 January 2013 10:14 AM, Stephen Warren wrote:
> On 01/24/2013 04:57 PM, Mike Turquette wrote:
>> Quoting Stephen Warren (2013-01-24 11:32:37)
>>> On 01/24/2013 11:20 AM, Mike Turquette wrote:
>>>> Quoting Prashant Gaikwad (2013-01-04 18:44:48)
>>>>> On Friday 04 January 2013 10:00 PM, Stephen Warren wrote:
>>>>>> On 01/04/2013 12:00 AM, Prashant Gaikwad wrote:
>>>>>>> Use common of_clk_init() function for clocks initialization.
>>>>>>> drivers/clk/tegra/clk-tegra20.c | 3 ++-
>>>>>>> drivers/clk/tegra/clk-tegra30.c | 3 ++-
>>>>>> Oh, so this series is written assuming that the Tegra CCF rework is
>>>>>> already applied then? That makes the dependencies quite painful, since I
>>>>>> think we'll end up with the following order being needed:
>>>>>>
>>>>>> 1) clk: Add composite clock type
>>>>>> -> This would usually go through the clk tree.
>>>>>> 2) The Tegra CCF rework series
>>>>>> -> This must go through the Tegra tree due to lots of dependencies
>>>>>> and merge conflicts with other Tegra patches.
>>>>>> 3) This series
>>>>>> -> This would usually go through the clk tree.
>>>>>>
>>>>>> Is it possible to re-order the dependencies as (1) (3) (2), so that Mike
>>>>>> can apply (1) and (3) to the clock tree, then I can use the clk tree as
>>>>>> the basis for a branch in the Tegra tree to apply (2) and all the other
>>>>>> Tegra patches that will conflict with (2)?
>>>>> If Mike approves the concept and implementation in (1) and (3) then I
>>>>> will repost (2) and (3) with dependencies re-ordered.
>>>> Patch (1) still has some unaddressed comments, and is not a real
>>>> dependency for this series.
>>> I assume "Patch (1)" refers to the list of series a couple emails above,
>>> not the first patch in the series you're replying to; that threw me for
>>> a moment.
>>>
>>>> Since all of the patches have received their
>>>> Tested-by's then I propose to merge all patches from this series into
>>>> clk-next, which exception of patch 2/7 (the Tegra patch).
>>>>
>>>> This reduces your Tegra CCF conversion dependencies and you can role the
>>>> necessary of_clk_init change into your Tegra CCF conversion branch (it
>>>> has my implicit Ack and can be taken through your tree).
>>>>
>>>> Let me know if this is OK for you.
>>> OK, I'm happy to merge your clock tree into the Tegra tree and then
>>> apply 2/7 on top of the Tegra CCF work.
>> Hmm, maybe the clk tree needs to be a dependency branch of arm-soc
>> again, as it has in the past. Would that help with any Tegra merge
>> pain?
> Yes, I think that's what would end up happening if I merge the clk tree
> into the Tegra tree anyway.
Hi Mike,
Have you merged these patches for 3.9?
^ permalink raw reply
* [GIT PULL 5/8] ARM: tegra: SCU base rework
From: Stephen Warren @ 2013-02-01 4:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOesGMjjgz7Am7-D_fQHqgLX=G+Wc_LKL-GYMHd1-NzVC-DUfA@mail.gmail.com>
On 01/31/2013 09:35 PM, Olof Johansson wrote:
> On Thu, Jan 31, 2013 at 8:32 PM, Olof Johansson <olof@lixom.net> wrote:
>> On Wed, Jan 30, 2013 at 02:42:36PM -0700, Stephen Warren wrote:
>>> Tegra currently relies on the SCU to determine the number of CPU
>>> cores, and also hard-codes the SCU physical address.
>>>
>>> This series adds a /cpus node to the Tegra device tree, and updates
>>> the code to rely solely on that to determine the CPU count. A new
>>> API is introduced to query for the existence of SCU registers, and the
>>> SCU register address. Tegra and OMAP2 are converted to use these new
>>> APIs.
>>>
>>> This pull request is based on a merge of v3.8-rc3, and arm-soc's
>>> depends/rmk-perf branch.
>>
>> This one looks like it should also be based on your cleanup, since it has
>> conflicts with it. Please rebase accordingly.
>
> By the way, just in case this looks like a random request...
>
> A few merge conflicts between independent topic branches is not a big
> deal; we can deal with those.
>
> What's somewhat annoying though, is when a previous cleanup branch
> conflicts with later features. So, please base features on top of
> cleanups accordingly.
Hmm. And here I was thinking that I was basing branches on top of
each-other too much given your previous comments about merge conflicts
being OK!
In case it helps, the following commit in linux-next shows the conflict
resolution:
ee05948 Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114
I guess I missed this because I didn't merge for-3.9/scu-base-rework
into my for-next on its own, but only as part of for-3.9/soc-t114,
within which I had resolved the conflict as above.
So, you could just skip this pull request, and it'll be pulled in when
you merge for-3.9/soc-t114.
It that doesn't work for you, I can do the rebase tomorrow morning.
^ permalink raw reply
* [PATCH 2/4] ARM: mach-shmobile: r8a7779: Allow initialisation of GIC by DT
From: Simon Horman @ 2013-02-01 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130201014706.GA14046@verge.net.au>
On Fri, Feb 01, 2013 at 10:47:06AM +0900, Simon Horman wrote:
> On Fri, Feb 01, 2013 at 09:34:10AM +0900, Simon Horman wrote:
> > On Fri, Feb 01, 2013 at 09:11:19AM +0900, Simon Horman wrote:
> > > On Thu, Jan 31, 2013 at 12:32:13PM +0000, Mark Rutland wrote:
> > > > Hi Simon,
> > > >
> > > > On Thu, Jan 31, 2013 at 01:50:49AM +0000, Simon Horman wrote:
> > > > > This allows the GIC interrupt controller of the r8a7779 SoC to be
> > > > > initialised using a flattened device tree blob.
> > > > >
> > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > > > ---
> > > > > arch/arm/boot/dts/r8a7779.dtsi | 40 ++++++++++++++++++++++++++
> > > > > arch/arm/mach-shmobile/include/mach/common.h | 1 +
> > > > > arch/arm/mach-shmobile/intc-r8a7779.c | 27 +++++++++++++----
> > > > > 3 files changed, 62 insertions(+), 6 deletions(-)
> > > > > create mode 100644 arch/arm/boot/dts/r8a7779.dtsi
> > > > >
> > > > > diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> > > > > new file mode 100644
> > > > > index 0000000..eadc12e
> > > > > --- /dev/null
> > > > > +++ b/arch/arm/boot/dts/r8a7779.dtsi
> > > > > @@ -0,0 +1,40 @@
> > > > > +/*
> > > > > + * Device Tree Source for Renesas r8a7740
> > > > > + *
> > > > > + * Copyright (C) 2013 Renesas Solutions Corp.
> > > > > + * Copyright (C) 2013 Simon Horman
> > > > > + *
> > > > > + * This file is licensed under the terms of the GNU General Public License
> > > > > + * version 2. This program is licensed "as is" without any warranty of any
> > > > > + * kind, whether express or implied.
> > > > > + */
> > > > > +
> > > > > +/include/ "skeleton.dtsi"
> > > > > +
> > > > > +/ {
> > > > > + compatible = "renesas,r8a7779";
> > > > > +
> > > > > + cpus {
> > > > > + cpu at 0 {
> > > > > + compatible = "arm,cortex-a9";
> > > > > + };
> > > > > + cpu at 1 {
> > > > > + compatible = "arm,cortex-a9";
> > > > > + };
> > > > > + cpu at 2 {
> > > > > + compatible = "arm,cortex-a9";
> > > > > + };
> > > > > + cpu at 3 {
> > > > > + compatible = "arm,cortex-a9";
> > > > > + };
> > > > > + };
> > > >
> > > > Sorry to sound like a broken record, but it'd be good to see reg and
> > > > device_type set here.
> > >
> > > Sure, will do.
> > >
> > > > > +
> > > > > + gic: interrupt-controller at f0001000 {
> > > > > + compatible = "arm,cortex-a9-gic";
> > > > > + #interrupt-cells = <3>;
> > > > > + #address-cells = <1>;
> > > >
> > > > Why is #address-cells needed here (and without #size-cells)? I see it's in the
> > > > binding document example, but I can't figure out why.
> > >
> > > Its here because I copied the example.
> > > I will see about removing it from here.
> > >
> > > > > + interrupt-controller;
> > > > > + reg = <0xf0001000 0x1000>,
> > > > > + <0xf0000100 0x100>;
> > > > > + };
> > > > > +};
> >
> > A revised patch is below. I should also remove "#address-cells = <1>" from
> > gic in arch/arm/boot/dts/sh73a0.dtsi if it is indeed unnecessary.
One more time:
>From 6031d5177193431a57392dfd2f38be0676bdb535 Mon Sep 17 00:00:00 2001
From: Simon Horman <horms+renesas@verge.net.au>
Date: Tue, 29 Jan 2013 14:21:46 +0900
Subject: [PATCH] ARM: mach-shmobile: r8a7779: Allow initialisation of GIC by
DT
This allows the GIC interrupt controller of the r8a7779 SoC to be
initialised using a flattened device tree blob.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v3
* Fix copy-paste error and use unique reg values for each CPU
v2
As suggested by Mark Rutland
* Add reg and device_type to cpus
* Remove #address-cells from gic
---
arch/arm/boot/dts/r8a7779.dtsi | 50 ++++++++++++++++++++++++++
arch/arm/mach-shmobile/include/mach/common.h | 1 +
arch/arm/mach-shmobile/intc-r8a7779.c | 27 ++++++++++----
3 files changed, 72 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/r8a7779.dtsi
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
new file mode 100644
index 0000000..8c6d52c
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Device Tree Source for Renesas r8a7740
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Simon Horman
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "renesas,r8a7779";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <2>;
+ };
+ cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <3>;
+ };
+ };
+
+ gic: interrupt-controller at f0001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xf0001000 0x1000>,
+ <0xf0000100 0x100>;
+ };
+};
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 16dab18..8ef7ebb 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -63,6 +63,7 @@ extern void r8a7740_pinmux_init(void);
extern void r8a7740_pm_init(void);
extern void r8a7779_init_irq(void);
+extern void r8a7779_init_irq_dt(void);
extern void r8a7779_map_io(void);
extern void r8a7779_earlytimer_init(void);
extern void r8a7779_add_early_devices(void);
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index 8807c27..f9cc4bc 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -24,6 +24,7 @@
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <mach/common.h>
+#include <linux/irqchip.h>
#include <mach/intc.h>
#include <mach/r8a7779.h>
#include <asm/mach-types.h>
@@ -43,13 +44,8 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
return 0; /* always allow wakeup */
}
-void __init r8a7779_init_irq(void)
+static void __init r8a7779_init_irq_common(void)
{
- void __iomem *gic_dist_base = IOMEM(0xf0001000);
- void __iomem *gic_cpu_base = IOMEM(0xf0000100);
-
- /* use GIC to handle interrupts */
- gic_init(0, 29, gic_dist_base, gic_cpu_base);
gic_arch_extn.irq_set_wake = r8a7779_set_wake;
/* route all interrupts to ARM */
@@ -63,3 +59,22 @@ void __init r8a7779_init_irq(void)
__raw_writel(0xbffffffc, INT2SMSKCR3);
__raw_writel(0x003fee3f, INT2SMSKCR4);
}
+
+void __init r8a7779_init_irq(void)
+{
+ void __iomem *gic_dist_base = IOMEM(0xf0001000);
+ void __iomem *gic_cpu_base = IOMEM(0xf0000100);
+
+ /* use GIC to handle interrupts */
+ gic_init(0, 29, gic_dist_base, gic_cpu_base);
+
+ r8a7779_init_irq_common();
+}
+
+#ifdef CONFIG_OF
+void __init r8a7779_init_irq_dt(void)
+{
+ irqchip_init();
+ r8a7779_init_irq_common();
+}
+#endif
--
1.7.10.4
^ permalink raw reply related
* [GIT PULL 5/8] ARM: tegra: SCU base rework
From: Olof Johansson @ 2013-02-01 4:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130201043222.GC5844@quad.lixom.net>
On Thu, Jan 31, 2013 at 8:32 PM, Olof Johansson <olof@lixom.net> wrote:
> On Wed, Jan 30, 2013 at 02:42:36PM -0700, Stephen Warren wrote:
>> Tegra currently relies on the SCU to determine the number of CPU
>> cores, and also hard-codes the SCU physical address.
>>
>> This series adds a /cpus node to the Tegra device tree, and updates
>> the code to rely solely on that to determine the CPU count. A new
>> API is introduced to query for the existence of SCU registers, and the
>> SCU register address. Tegra and OMAP2 are converted to use these new
>> APIs.
>>
>> This pull request is based on a merge of v3.8-rc3, and arm-soc's
>> depends/rmk-perf branch.
>
> This one looks like it should also be based on your cleanup, since it has
> conflicts with it. Please rebase accordingly.
By the way, just in case this looks like a random request...
A few merge conflicts between independent topic branches is not a big
deal; we can deal with those.
What's somewhat annoying though, is when a previous cleanup branch
conflicts with later features. So, please base features on top of
cleanups accordingly.
Thanks,
-Olof
^ permalink raw reply
* [GIT PULL 5/8] ARM: tegra: SCU base rework
From: Olof Johansson @ 2013-02-01 4:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359582159-28816-5-git-send-email-swarren@wwwdotorg.org>
On Wed, Jan 30, 2013 at 02:42:36PM -0700, Stephen Warren wrote:
> Tegra currently relies on the SCU to determine the number of CPU
> cores, and also hard-codes the SCU physical address.
>
> This series adds a /cpus node to the Tegra device tree, and updates
> the code to rely solely on that to determine the CPU count. A new
> API is introduced to query for the existence of SCU registers, and the
> SCU register address. Tegra and OMAP2 are converted to use these new
> APIs.
>
> This pull request is based on a merge of v3.8-rc3, and arm-soc's
> depends/rmk-perf branch.
This one looks like it should also be based on your cleanup, since it has
conflicts with it. Please rebase accordingly.
-Olof
^ permalink raw reply
* Existing queued v3.8-rc fixes postponed to v3.9
From: Paul Walmsley @ 2013-02-01 4:22 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
so, v3.8-rc6 is out, and based on Linus' release message:
http://marc.info/?l=linux-kernel&m=135968304820921&w=2
he only wants to see patches that "fix major security issues, big
user-reported regressions, or nasty oopses".
So as a result the fixes that you've recently sent will be deferred to the
v3.9 merge window.
...
As far as the OMAP4 PM stuff goes, I'm pretty disappointed that v3.8 is
going to be released with non-obvious bootloader dependencies for
full-chip power management. Let's get the warning patch written and
posted right away so it can go in during the v3.9 merge window.
- Paul
^ permalink raw reply
* [PATCH v4 3/3] ARM: mm: use static_vm for managing static mapped areas
From: Nicolas Pitre @ 2013-02-01 4:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359594008-14688-4-git-send-email-iamjoonsoo.kim@lge.com>
On Thu, 31 Jan 2013, Joonsoo Kim wrote:
> A static mapped area is ARM-specific, so it is better not to use
> generic vmalloc data structure, that is, vmlist and vmlist_lock
> for managing static mapped area. And it causes some needless overhead and
> reducing this overhead is better idea.
>
> Now, we have newly introduced static_vm infrastructure.
> With it, we don't need to iterate all mapped areas. Instead, we just
> iterate static mapped areas. It helps to reduce an overhead of finding
> matched area. And architecture dependency on vmalloc layer is removed,
> so it will help to maintainability for vmalloc layer.
>
> Signed-off-by: Joonsoo Kim <iamjoonsoo.kim@lge.com>
Comments below.
>
> diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
> index ceb34ae..7fe5b48 100644
> --- a/arch/arm/mm/ioremap.c
> +++ b/arch/arm/mm/ioremap.c
> @@ -269,13 +269,14 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
> const struct mem_type *type;
> int err;
> unsigned long addr;
> - struct vm_struct * area;
> + struct vm_struct *area;
> + phys_addr_t paddr = __pfn_to_phys(pfn);
>
> #ifndef CONFIG_ARM_LPAE
> /*
> * High mappings must be supersection aligned
> */
> - if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
> + if (pfn >= 0x100000 && (paddr & ~SUPERSECTION_MASK))
> return NULL;
> #endif
>
> @@ -291,24 +292,17 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
> /*
> * Try to reuse one of the static mapping whenever possible.
> */
> - read_lock(&vmlist_lock);
> - for (area = vmlist; area; area = area->next) {
> - if (!size || (sizeof(phys_addr_t) == 4 && pfn >= 0x100000))
> - break;
> - if (!(area->flags & VM_ARM_STATIC_MAPPING))
> - continue;
> - if ((area->flags & VM_ARM_MTYPE_MASK) != VM_ARM_MTYPE(mtype))
> - continue;
> - if (__phys_to_pfn(area->phys_addr) > pfn ||
> - __pfn_to_phys(pfn) + size-1 > area->phys_addr + area->size-1)
> - continue;
> - /* we can drop the lock here as we know *area is static */
> - read_unlock(&vmlist_lock);
> - addr = (unsigned long)area->addr;
> - addr += __pfn_to_phys(pfn) - area->phys_addr;
> - return (void __iomem *) (offset + addr);
> + if (size && !((sizeof(phys_addr_t) == 4 && pfn >= 0x100000))) {
> + struct static_vm *svm;
> +
> + svm = find_static_vm_paddr(paddr, size,
> + STATIC_VM_TYPE(STATIC_VM_MEM, mtype));
> + if (svm) {
> + addr = (unsigned long)svm->vm.addr;
> + addr += paddr - svm->vm.phys_addr;
> + return (void __iomem *) (offset + addr);
> + }
> }
> - read_unlock(&vmlist_lock);
>
> /*
> * Don't allow RAM to be mapped - this causes problems with ARMv6+
> @@ -320,21 +314,21 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
> if (!area)
> return NULL;
> addr = (unsigned long)area->addr;
> - area->phys_addr = __pfn_to_phys(pfn);
> + area->phys_addr = paddr;
>
> #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
> if (DOMAIN_IO == 0 &&
> (((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) ||
> cpu_is_xsc3()) && pfn >= 0x100000 &&
> - !((__pfn_to_phys(pfn) | size | addr) & ~SUPERSECTION_MASK)) {
> + !((paddr | size | addr) & ~SUPERSECTION_MASK)) {
> area->flags |= VM_ARM_SECTION_MAPPING;
> err = remap_area_supersections(addr, pfn, size, type);
> - } else if (!((__pfn_to_phys(pfn) | size | addr) & ~PMD_MASK)) {
> + } else if (!((paddr | size | addr) & ~PMD_MASK)) {
> area->flags |= VM_ARM_SECTION_MAPPING;
> err = remap_area_sections(addr, pfn, size, type);
> } else
> #endif
> - err = ioremap_page_range(addr, addr + size, __pfn_to_phys(pfn),
> + err = ioremap_page_range(addr, addr + size, paddr,
> __pgprot(type->prot_pte));
>
> if (err) {
> @@ -418,34 +412,21 @@ __arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached)
> void __iounmap(volatile void __iomem *io_addr)
> {
> void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
> - struct vm_struct *vm;
> + struct static_vm *svm;
> +
You could salvage the "/* If this is a static mapping we must leave it
alone */" comment here.
> + svm = find_static_vm_vaddr(addr);
> + if (svm)
> + return;
>
> - read_lock(&vmlist_lock);
> - for (vm = vmlist; vm; vm = vm->next) {
> - if (vm->addr > addr)
> - break;
> - if (!(vm->flags & VM_IOREMAP))
> - continue;
> - /* If this is a static mapping we must leave it alone */
> - if ((vm->flags & VM_ARM_STATIC_MAPPING) &&
> - (vm->addr <= addr) && (vm->addr + vm->size > addr)) {
> - read_unlock(&vmlist_lock);
> - return;
> - }
> #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
> - /*
> - * If this is a section based mapping we need to handle it
> - * specially as the VM subsystem does not know how to handle
> - * such a beast.
> - */
Please don't remove the above comment. It is still relevant.
> - if ((vm->addr == addr) &&
> - (vm->flags & VM_ARM_SECTION_MAPPING)) {
> + {
> + struct vm_struct *vm;
> +
> + vm = find_vm_area(addr);
> + if (vm && (vm->flags & VM_ARM_SECTION_MAPPING))
> unmap_area_sections((unsigned long)vm->addr, vm->size);
> - break;
> - }
> -#endif
> }
> - read_unlock(&vmlist_lock);
> +#endif
>
> vunmap(addr);
> }
> diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
> index fb45c79..24c1df4 100644
> --- a/arch/arm/mm/mm.h
> +++ b/arch/arm/mm/mm.h
> @@ -54,16 +54,6 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
> /* (super)section-mapped I/O regions used by ioremap()/iounmap() */
> #define VM_ARM_SECTION_MAPPING 0x80000000
>
> -/* permanent static mappings from iotable_init() */
> -#define VM_ARM_STATIC_MAPPING 0x40000000
> -
> -/* empty mapping */
> -#define VM_ARM_EMPTY_MAPPING 0x20000000
> -
> -/* mapping type (attributes) for permanent static mappings */
> -#define VM_ARM_MTYPE(mt) ((mt) << 20)
> -#define VM_ARM_MTYPE_MASK (0x1f << 20)
> -
This goes with a related question in my previous email: why didn't you
keep those flags as they were?
Nicolas
^ permalink raw reply
* [PATCH v4 00/13] ARM LPAE Fixes - Part 1
From: Nicolas Pitre @ 2013-02-01 4:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359669512-31276-1-git-send-email-cyril@ti.com>
On Thu, 31 Jan 2013, Cyril Chemparathy wrote:
> This series is a repost of the LPAE related changes in preparation for the
> introduction of the Keystone sub-architecture. The original series has now
> been split, and this particular series excludes the earlier changes to the
> runtime code patching implementation. Earlier versions of this series can be
> found at [1], [2], [3] and [4].
>
> These patches are also available in git:
> git://git.kernel.org/pub/scm/linux/kernel/git/cchemparathy/linux-keystone.git upstream/keystone-lpae-v4
This part 1 looks very nice. It received many review cycles already as
well. It would be about time it goes upstream.
I think it is ready to be merged in Russell's tree. Feel free to send
him a pull request whenever you're ready.
Then we'll be free to look at the more controvertial p2v patching stuff.
Nicolas
^ permalink raw reply
* [PATCH] clocksource: always define CLOCKSOURCE_OF_DECLARE
From: Olof Johansson @ 2013-02-01 3:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359568170-26479-1-git-send-email-swarren@wwwdotorg.org>
On Wed, Jan 30, 2013 at 10:49:30AM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> This allows clocksource drivers that support both DT and non-DT to
> always invoke macro CLOCKSOURCE_OF_DECLARE(), rather than wrapping
> it in a #ifdef CONFIG_CLKSRC_OF, which simplifies their code.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> Olof, Arnd, this is based on arm-soc's timer/cleanup branch, which is
> probably the best place for this patch.
Applied (to next/cleanup).
-Olof
^ permalink raw reply
* [PATCH] ARM: imx: fix imx31-dt.c time-related warning
From: Olof Johansson @ 2013-02-01 3:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359518177-21245-1-git-send-email-swarren@wwwdotorg.org>
On Tue, Jan 29, 2013 at 08:56:17PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> Commit 6bb27d7 "ARM: delete struct sys_timer" caused the following:
>
> arch/arm/mach-imx/imx31-dt.c:56:2: warning: initialization from incompatible pointer type [enabled by default]
> arch/arm/mach-imx/imx31-dt.c:56:2: warning: (near initialization for ?__mach_desc_IMX31_DT.init_time?) [enabled by default]
>
> This is because mx31_clocks_init_dt() returns int, whereas the .init_time
> field prototype expects a function returning void. Implement a wrapper so
> that the prototypes match.
>
> Reported-by: Fengguang Wu <fengguang.wu@intel.com>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is based on arm-soc's timer/cleanup branch, which contains
> the commit mentioned above.
Applied.
-Olof
^ permalink raw reply
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