* [PATCH v5 01/10] clk: tegra: Refactor PLL programming code
From: Peter De Schrijver @ 2013-02-01 10:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359713962-16822-1-git-send-email-pdeschrijver@nvidia.com>
Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.
The following changes were done:
* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 178 +++++++++++++++++------------
drivers/clk/tegra/clk-tegra20.c | 144 ++++++++++++------------
drivers/clk/tegra/clk-tegra30.c | 234 +++++++++++++++++++-------------------
3 files changed, 294 insertions(+), 262 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 165f247..912c977 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -113,20 +113,23 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
pll_writel_misc(val, pll);
}
-static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
- void __iomem *lock_addr, u32 lock_bit_idx)
+static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
{
int i;
- u32 val;
+ u32 val, lock_bit;
+ void __iomem *lock_addr;
if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
udelay(pll->params->lock_delay);
return 0;
}
+ lock_addr = pll->clk_base + pll->params->base_reg;
+ lock_bit = BIT(pll->params->lock_bit_idx);
+
for (i = 0; i < pll->params->lock_delay; i++) {
val = readl_relaxed(lock_addr);
- if (val & BIT(lock_bit_idx)) {
+ if (val & lock_bit) {
udelay(PLL_POST_LOCK_DELAY);
return 0;
}
@@ -155,7 +158,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
return val & PLL_BASE_ENABLE ? 1 : 0;
}
-static int _clk_pll_enable(struct clk_hw *hw)
+static void _clk_pll_enable(struct clk_hw *hw)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
u32 val;
@@ -172,11 +175,6 @@ static int _clk_pll_enable(struct clk_hw *hw)
val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
}
-
- clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->base_reg,
- pll->params->lock_bit_idx);
-
- return 0;
}
static void _clk_pll_disable(struct clk_hw *hw)
@@ -204,7 +202,9 @@ static int clk_pll_enable(struct clk_hw *hw)
if (pll->lock)
spin_lock_irqsave(pll->lock, flags);
- ret = _clk_pll_enable(hw);
+ _clk_pll_enable(hw);
+
+ ret = clk_pll_wait_for_lock(pll);
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
@@ -241,8 +241,6 @@ static int _get_table_rate(struct clk_hw *hw,
if (sel->input_rate == 0)
return -EINVAL;
- BUG_ON(sel->p < 1);
-
cfg->input_rate = sel->input_rate;
cfg->output_rate = sel->output_rate;
cfg->m = sel->m;
@@ -290,88 +288,109 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
cfg->output_rate <<= 1)
p_div++;
- cfg->p = 1 << p_div;
+ cfg->p = p_div;
cfg->m = parent_rate / cfreq;
cfg->n = cfg->output_rate / cfreq;
cfg->cpcon = OUT_OF_TABLE_CPCON;
if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
- cfg->p > divp_max(pll) || cfg->output_rate > pll->params->vco_max) {
+ (1 << p_div) > divp_max(pll)
+ || cfg->output_rate > pll->params->vco_max) {
pr_err("%s: Failed to set %s rate %lu\n",
__func__, __clk_get_name(hw->clk), rate);
return -EINVAL;
}
+ if (pll->flags & TEGRA_PLLU)
+ cfg->p ^= 1;
+
return 0;
}
-static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
- unsigned long rate)
+static void _update_pll_mnp(struct tegra_clk_pll *pll,
+ struct tegra_clk_pll_freq_table *cfg)
{
- struct tegra_clk_pll *pll = to_clk_pll(hw);
- unsigned long flags = 0;
- u32 divp, val, old_base;
- int state;
-
- divp = __ffs(cfg->p);
-
- if (pll->flags & TEGRA_PLLU)
- divp ^= 1;
+ u32 val;
- if (pll->lock)
- spin_lock_irqsave(pll->lock, flags);
+ val = pll_readl_base(pll);
- old_base = val = pll_readl_base(pll);
val &= ~((divm_mask(pll) << pll->divm_shift) |
(divn_mask(pll) << pll->divn_shift) |
(divp_mask(pll) << pll->divp_shift));
val |= ((cfg->m << pll->divm_shift) |
(cfg->n << pll->divn_shift) |
- (divp << pll->divp_shift));
- if (val == old_base) {
- if (pll->lock)
- spin_unlock_irqrestore(pll->lock, flags);
- return 0;
+ (cfg->p << pll->divp_shift));
+
+ pll_writel_base(val, pll);
+}
+
+static void _get_pll_mnp(struct tegra_clk_pll *pll,
+ struct tegra_clk_pll_freq_table *cfg)
+{
+ u32 val;
+
+ val = pll_readl_base(pll);
+
+ cfg->m = (val >> pll->divm_shift) & (divm_mask(pll));
+ cfg->n = (val >> pll->divn_shift) & (divn_mask(pll));
+ cfg->p = (val >> pll->divp_shift) & (divp_mask(pll));
+}
+
+static void _update_pll_cpcon(struct tegra_clk_pll *pll,
+ struct tegra_clk_pll_freq_table *cfg,
+ unsigned long rate)
+{
+ u32 val;
+
+ val = pll_readl_misc(pll);
+
+ val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
+ val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
+
+ if (pll->flags & TEGRA_PLL_SET_LFCON) {
+ val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
+ if (cfg->n >= PLLDU_LFCON_SET_DIVN)
+ val |= 1 << PLL_MISC_LFCON_SHIFT;
+ } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
+ val &= ~(1 << PLL_MISC_DCCON_SHIFT);
+ if (rate >= (pll->params->vco_max >> 1))
+ val |= 1 << PLL_MISC_DCCON_SHIFT;
}
+ pll_writel_misc(val, pll);
+}
+
+static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
+ unsigned long rate)
+{
+ struct tegra_clk_pll *pll = to_clk_pll(hw);
+ int state, ret = 0;
+
state = clk_pll_is_enabled(hw);
- if (state) {
+ if (state)
_clk_pll_disable(hw);
- val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
- }
- pll_writel_base(val, pll);
- if (pll->flags & TEGRA_PLL_HAS_CPCON) {
- val = pll_readl_misc(pll);
- val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
- val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
- if (pll->flags & TEGRA_PLL_SET_LFCON) {
- val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
- if (cfg->n >= PLLDU_LFCON_SET_DIVN)
- val |= 0x1 << PLL_MISC_LFCON_SHIFT;
- } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
- val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
- if (rate >= (pll->params->vco_max >> 1))
- val |= 0x1 << PLL_MISC_DCCON_SHIFT;
- }
- pll_writel_misc(val, pll);
- }
+ _update_pll_mnp(pll, cfg);
- if (pll->lock)
- spin_unlock_irqrestore(pll->lock, flags);
+ if (pll->flags & TEGRA_PLL_HAS_CPCON)
+ _update_pll_cpcon(pll, cfg, rate);
- if (state)
- clk_pll_enable(hw);
+ if (state) {
+ _clk_pll_enable(hw);
+ ret = clk_pll_wait_for_lock(pll);
+ }
- return 0;
+ return ret;
}
static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
- struct tegra_clk_pll_freq_table cfg;
+ struct tegra_clk_pll_freq_table cfg, old_cfg;
+ unsigned long flags = 0;
+ int ret = 0;
if (pll->flags & TEGRA_PLL_FIXED) {
if (rate != pll->fixed_rate) {
@@ -387,7 +406,18 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
_calc_rate(hw, &cfg, rate, parent_rate))
return -EINVAL;
- return _program_pll(hw, &cfg, rate);
+ if (pll->lock)
+ spin_lock_irqsave(pll->lock, flags);
+
+ _get_pll_mnp(pll, &old_cfg);
+
+ if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
+ ret = _program_pll(hw, &cfg, rate);
+
+ if (pll->lock)
+ spin_unlock_irqrestore(pll->lock, flags);
+
+ return ret;
}
static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -409,7 +439,7 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
return -EINVAL;
output_rate *= cfg.n;
- do_div(output_rate, cfg.m * cfg.p);
+ do_div(output_rate, cfg.m * (1 << cfg.p));
return output_rate;
}
@@ -418,10 +448,12 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
- u32 val = pll_readl_base(pll);
- u32 divn = 0, divm = 0, divp = 0;
+ struct tegra_clk_pll_freq_table cfg;
+ u32 val;
u64 rate = parent_rate;
+ val = pll_readl_base(pll);
+
if (val & PLL_BASE_BYPASS)
return parent_rate;
@@ -435,16 +467,16 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
return pll->fixed_rate;
}
- divp = (val >> pll->divp_shift) & (divp_mask(pll));
+ _get_pll_mnp(pll, &cfg);
+
if (pll->flags & TEGRA_PLLU)
- divp ^= 1;
+ cfg.p ^= 1;
- divn = (val >> pll->divn_shift) & (divn_mask(pll));
- divm = (val >> pll->divm_shift) & (divm_mask(pll));
- divm *= (1 << divp);
+ cfg.m *= 1 << cfg.p;
+
+ rate *= cfg.n;
+ do_div(rate, cfg.m);
- rate *= divn;
- do_div(rate, divm);
return rate;
}
@@ -538,8 +570,8 @@ static int clk_plle_enable(struct clk_hw *hw)
val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
pll_writel_base(val, pll);
- clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg,
- pll->params->lock_bit_idx);
+ clk_pll_wait_for_lock(pll);
+
return 0;
}
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 5d41569..30bd3fd 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -247,125 +247,125 @@ static struct clk *clks[clk_max];
static struct clk_onecell_data clk_data;
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
- { 12000000, 600000000, 600, 12, 1, 8 },
- { 13000000, 600000000, 600, 13, 1, 8 },
- { 19200000, 600000000, 500, 16, 1, 6 },
- { 26000000, 600000000, 600, 26, 1, 8 },
+ { 12000000, 600000000, 600, 12, 0, 8 },
+ { 13000000, 600000000, 600, 13, 0, 8 },
+ { 19200000, 600000000, 500, 16, 0, 6 },
+ { 26000000, 600000000, 600, 26, 0, 8 },
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
- { 12000000, 666000000, 666, 12, 1, 8},
- { 13000000, 666000000, 666, 13, 1, 8},
- { 19200000, 666000000, 555, 16, 1, 8},
- { 26000000, 666000000, 666, 26, 1, 8},
- { 12000000, 600000000, 600, 12, 1, 8},
- { 13000000, 600000000, 600, 13, 1, 8},
- { 19200000, 600000000, 375, 12, 1, 6},
- { 26000000, 600000000, 600, 26, 1, 8},
+ { 12000000, 666000000, 666, 12, 0, 8},
+ { 13000000, 666000000, 666, 13, 0, 8},
+ { 19200000, 666000000, 555, 16, 0, 8},
+ { 26000000, 666000000, 666, 26, 0, 8},
+ { 12000000, 600000000, 600, 12, 0, 8},
+ { 13000000, 600000000, 600, 13, 0, 8},
+ { 19200000, 600000000, 375, 12, 0, 6},
+ { 26000000, 600000000, 600, 26, 0, 8},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
- { 12000000, 216000000, 432, 12, 2, 8},
- { 13000000, 216000000, 432, 13, 2, 8},
- { 19200000, 216000000, 90, 4, 2, 1},
- { 26000000, 216000000, 432, 26, 2, 8},
- { 12000000, 432000000, 432, 12, 1, 8},
- { 13000000, 432000000, 432, 13, 1, 8},
- { 19200000, 432000000, 90, 4, 1, 1},
- { 26000000, 432000000, 432, 26, 1, 8},
+ { 12000000, 216000000, 432, 12, 1, 8},
+ { 13000000, 216000000, 432, 13, 1, 8},
+ { 19200000, 216000000, 90, 4, 1, 1},
+ { 26000000, 216000000, 432, 26, 1, 8},
+ { 12000000, 432000000, 432, 12, 0, 8},
+ { 13000000, 432000000, 432, 13, 0, 8},
+ { 19200000, 432000000, 90, 4, 0, 1},
+ { 26000000, 432000000, 432, 26, 0, 8},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
- { 28800000, 56448000, 49, 25, 1, 1},
- { 28800000, 73728000, 64, 25, 1, 1},
- { 28800000, 24000000, 5, 6, 1, 1},
+ { 28800000, 56448000, 49, 25, 0, 1},
+ { 28800000, 73728000, 64, 25, 0, 1},
+ { 28800000, 24000000, 5, 6, 0, 1},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
- { 12000000, 216000000, 216, 12, 1, 4},
- { 13000000, 216000000, 216, 13, 1, 4},
- { 19200000, 216000000, 135, 12, 1, 3},
- { 26000000, 216000000, 216, 26, 1, 4},
+ { 12000000, 216000000, 216, 12, 0, 4},
+ { 13000000, 216000000, 216, 13, 0, 4},
+ { 19200000, 216000000, 135, 12, 0, 3},
+ { 26000000, 216000000, 216, 26, 0, 4},
- { 12000000, 594000000, 594, 12, 1, 8},
- { 13000000, 594000000, 594, 13, 1, 8},
- { 19200000, 594000000, 495, 16, 1, 8},
- { 26000000, 594000000, 594, 26, 1, 8},
+ { 12000000, 594000000, 594, 12, 0, 8},
+ { 13000000, 594000000, 594, 13, 0, 8},
+ { 19200000, 594000000, 495, 16, 0, 8},
+ { 26000000, 594000000, 594, 26, 0, 8},
- { 12000000, 1000000000, 1000, 12, 1, 12},
- { 13000000, 1000000000, 1000, 13, 1, 12},
- { 19200000, 1000000000, 625, 12, 1, 8},
- { 26000000, 1000000000, 1000, 26, 1, 12},
+ { 12000000, 1000000000, 1000, 12, 0, 12},
+ { 13000000, 1000000000, 1000, 13, 0, 12},
+ { 19200000, 1000000000, 625, 12, 0, 8},
+ { 26000000, 1000000000, 1000, 26, 0, 12},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
- { 12000000, 480000000, 960, 12, 2, 0},
- { 13000000, 480000000, 960, 13, 2, 0},
- { 19200000, 480000000, 200, 4, 2, 0},
- { 26000000, 480000000, 960, 26, 2, 0},
+ { 12000000, 480000000, 960, 12, 0, 0},
+ { 13000000, 480000000, 960, 13, 0, 0},
+ { 19200000, 480000000, 200, 4, 0, 0},
+ { 26000000, 480000000, 960, 26, 0, 0},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
/* 1 GHz */
- { 12000000, 1000000000, 1000, 12, 1, 12},
- { 13000000, 1000000000, 1000, 13, 1, 12},
- { 19200000, 1000000000, 625, 12, 1, 8},
- { 26000000, 1000000000, 1000, 26, 1, 12},
+ { 12000000, 1000000000, 1000, 12, 0, 12},
+ { 13000000, 1000000000, 1000, 13, 0, 12},
+ { 19200000, 1000000000, 625, 12, 0, 8},
+ { 26000000, 1000000000, 1000, 26, 0, 12},
/* 912 MHz */
- { 12000000, 912000000, 912, 12, 1, 12},
- { 13000000, 912000000, 912, 13, 1, 12},
- { 19200000, 912000000, 760, 16, 1, 8},
- { 26000000, 912000000, 912, 26, 1, 12},
+ { 12000000, 912000000, 912, 12, 0, 12},
+ { 13000000, 912000000, 912, 13, 0, 12},
+ { 19200000, 912000000, 760, 16, 0, 8},
+ { 26000000, 912000000, 912, 26, 0, 12},
/* 816 MHz */
- { 12000000, 816000000, 816, 12, 1, 12},
- { 13000000, 816000000, 816, 13, 1, 12},
- { 19200000, 816000000, 680, 16, 1, 8},
- { 26000000, 816000000, 816, 26, 1, 12},
+ { 12000000, 816000000, 816, 12, 0, 12},
+ { 13000000, 816000000, 816, 13, 0, 12},
+ { 19200000, 816000000, 680, 16, 0, 8},
+ { 26000000, 816000000, 816, 26, 0, 12},
/* 760 MHz */
- { 12000000, 760000000, 760, 12, 1, 12},
- { 13000000, 760000000, 760, 13, 1, 12},
- { 19200000, 760000000, 950, 24, 1, 8},
- { 26000000, 760000000, 760, 26, 1, 12},
+ { 12000000, 760000000, 760, 12, 0, 12},
+ { 13000000, 760000000, 760, 13, 0, 12},
+ { 19200000, 760000000, 950, 24, 0, 8},
+ { 26000000, 760000000, 760, 26, 0, 12},
/* 750 MHz */
- { 12000000, 750000000, 750, 12, 1, 12},
- { 13000000, 750000000, 750, 13, 1, 12},
- { 19200000, 750000000, 625, 16, 1, 8},
- { 26000000, 750000000, 750, 26, 1, 12},
+ { 12000000, 750000000, 750, 12, 0, 12},
+ { 13000000, 750000000, 750, 13, 0, 12},
+ { 19200000, 750000000, 625, 16, 0, 8},
+ { 26000000, 750000000, 750, 26, 0, 12},
/* 608 MHz */
- { 12000000, 608000000, 608, 12, 1, 12},
- { 13000000, 608000000, 608, 13, 1, 12},
- { 19200000, 608000000, 380, 12, 1, 8},
- { 26000000, 608000000, 608, 26, 1, 12},
+ { 12000000, 608000000, 608, 12, 0, 12},
+ { 13000000, 608000000, 608, 13, 0, 12},
+ { 19200000, 608000000, 380, 12, 0, 8},
+ { 26000000, 608000000, 608, 26, 0, 12},
/* 456 MHz */
- { 12000000, 456000000, 456, 12, 1, 12},
- { 13000000, 456000000, 456, 13, 1, 12},
- { 19200000, 456000000, 380, 16, 1, 8},
- { 26000000, 456000000, 456, 26, 1, 12},
+ { 12000000, 456000000, 456, 12, 0, 12},
+ { 13000000, 456000000, 456, 13, 0, 12},
+ { 19200000, 456000000, 380, 16, 0, 8},
+ { 26000000, 456000000, 456, 26, 0, 12},
/* 312 MHz */
- { 12000000, 312000000, 312, 12, 1, 12},
- { 13000000, 312000000, 312, 13, 1, 12},
- { 19200000, 312000000, 260, 16, 1, 8},
- { 26000000, 312000000, 312, 26, 1, 12},
+ { 12000000, 312000000, 312, 12, 0, 12},
+ { 13000000, 312000000, 312, 13, 0, 12},
+ { 19200000, 312000000, 260, 16, 0, 8},
+ { 26000000, 312000000, 312, 26, 0, 12},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
- { 12000000, 100000000, 200, 24, 1, 0 },
+ { 12000000, 100000000, 200, 24, 0, 0 },
{ 0, 0, 0, 0, 0, 0 },
};
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index a163812..28a2997 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -373,164 +373,164 @@ static const struct utmi_clk_param utmi_parameters[] = {
};
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
- { 12000000, 1040000000, 520, 6, 1, 8},
- { 13000000, 1040000000, 480, 6, 1, 8},
- { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
- { 19200000, 1040000000, 325, 6, 1, 6},
- { 26000000, 1040000000, 520, 13, 1, 8},
-
- { 12000000, 832000000, 416, 6, 1, 8},
- { 13000000, 832000000, 832, 13, 1, 8},
- { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
- { 19200000, 832000000, 260, 6, 1, 8},
- { 26000000, 832000000, 416, 13, 1, 8},
-
- { 12000000, 624000000, 624, 12, 1, 8},
- { 13000000, 624000000, 624, 13, 1, 8},
- { 16800000, 600000000, 520, 14, 1, 8},
- { 19200000, 624000000, 520, 16, 1, 8},
- { 26000000, 624000000, 624, 26, 1, 8},
-
- { 12000000, 600000000, 600, 12, 1, 8},
- { 13000000, 600000000, 600, 13, 1, 8},
- { 16800000, 600000000, 500, 14, 1, 8},
- { 19200000, 600000000, 375, 12, 1, 6},
- { 26000000, 600000000, 600, 26, 1, 8},
-
- { 12000000, 520000000, 520, 12, 1, 8},
- { 13000000, 520000000, 520, 13, 1, 8},
- { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
- { 19200000, 520000000, 325, 12, 1, 6},
- { 26000000, 520000000, 520, 26, 1, 8},
-
- { 12000000, 416000000, 416, 12, 1, 8},
- { 13000000, 416000000, 416, 13, 1, 8},
- { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
- { 19200000, 416000000, 260, 12, 1, 6},
- { 26000000, 416000000, 416, 26, 1, 8},
+ { 12000000, 1040000000, 520, 6, 0, 8},
+ { 13000000, 1040000000, 480, 6, 0, 8},
+ { 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */
+ { 19200000, 1040000000, 325, 6, 0, 6},
+ { 26000000, 1040000000, 520, 13, 0, 8},
+
+ { 12000000, 832000000, 416, 6, 0, 8},
+ { 13000000, 832000000, 832, 13, 0, 8},
+ { 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */
+ { 19200000, 832000000, 260, 6, 0, 8},
+ { 26000000, 832000000, 416, 13, 0, 8},
+
+ { 12000000, 624000000, 624, 12, 0, 8},
+ { 13000000, 624000000, 624, 13, 0, 8},
+ { 16800000, 600000000, 520, 14, 0, 8},
+ { 19200000, 624000000, 520, 16, 0, 8},
+ { 26000000, 624000000, 624, 26, 0, 8},
+
+ { 12000000, 600000000, 600, 12, 0, 8},
+ { 13000000, 600000000, 600, 13, 0, 8},
+ { 16800000, 600000000, 500, 14, 0, 8},
+ { 19200000, 600000000, 375, 12, 0, 6},
+ { 26000000, 600000000, 600, 26, 0, 8},
+
+ { 12000000, 520000000, 520, 12, 0, 8},
+ { 13000000, 520000000, 520, 13, 0, 8},
+ { 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */
+ { 19200000, 520000000, 325, 12, 0, 6},
+ { 26000000, 520000000, 520, 26, 0, 8},
+
+ { 12000000, 416000000, 416, 12, 0, 8},
+ { 13000000, 416000000, 416, 13, 0, 8},
+ { 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */
+ { 19200000, 416000000, 260, 12, 0, 6},
+ { 26000000, 416000000, 416, 26, 0, 8},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
- { 12000000, 666000000, 666, 12, 1, 8},
- { 13000000, 666000000, 666, 13, 1, 8},
- { 16800000, 666000000, 555, 14, 1, 8},
- { 19200000, 666000000, 555, 16, 1, 8},
- { 26000000, 666000000, 666, 26, 1, 8},
- { 12000000, 600000000, 600, 12, 1, 8},
- { 13000000, 600000000, 600, 13, 1, 8},
- { 16800000, 600000000, 500, 14, 1, 8},
- { 19200000, 600000000, 375, 12, 1, 6},
- { 26000000, 600000000, 600, 26, 1, 8},
+ { 12000000, 666000000, 666, 12, 0, 8},
+ { 13000000, 666000000, 666, 13, 0, 8},
+ { 16800000, 666000000, 555, 14, 0, 8},
+ { 19200000, 666000000, 555, 16, 0, 8},
+ { 26000000, 666000000, 666, 26, 0, 8},
+ { 12000000, 600000000, 600, 12, 0, 8},
+ { 13000000, 600000000, 600, 13, 0, 8},
+ { 16800000, 600000000, 500, 14, 0, 8},
+ { 19200000, 600000000, 375, 12, 0, 6},
+ { 26000000, 600000000, 600, 26, 0, 8},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
- { 12000000, 216000000, 432, 12, 2, 8},
- { 13000000, 216000000, 432, 13, 2, 8},
- { 16800000, 216000000, 360, 14, 2, 8},
- { 19200000, 216000000, 360, 16, 2, 8},
- { 26000000, 216000000, 432, 26, 2, 8},
+ { 12000000, 216000000, 432, 12, 1, 8},
+ { 13000000, 216000000, 432, 13, 1, 8},
+ { 16800000, 216000000, 360, 14, 1, 8},
+ { 19200000, 216000000, 360, 16, 1, 8},
+ { 26000000, 216000000, 432, 26, 1, 8},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
- { 9600000, 564480000, 294, 5, 1, 4},
- { 9600000, 552960000, 288, 5, 1, 4},
- { 9600000, 24000000, 5, 2, 1, 1},
+ { 9600000, 564480000, 294, 5, 0, 4},
+ { 9600000, 552960000, 288, 5, 0, 4},
+ { 9600000, 24000000, 5, 2, 0, 1},
- { 28800000, 56448000, 49, 25, 1, 1},
- { 28800000, 73728000, 64, 25, 1, 1},
- { 28800000, 24000000, 5, 6, 1, 1},
+ { 28800000, 56448000, 49, 25, 0, 1},
+ { 28800000, 73728000, 64, 25, 0, 1},
+ { 28800000, 24000000, 5, 6, 0, 1},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
- { 12000000, 216000000, 216, 12, 1, 4},
- { 13000000, 216000000, 216, 13, 1, 4},
- { 16800000, 216000000, 180, 14, 1, 4},
- { 19200000, 216000000, 180, 16, 1, 4},
- { 26000000, 216000000, 216, 26, 1, 4},
-
- { 12000000, 594000000, 594, 12, 1, 8},
- { 13000000, 594000000, 594, 13, 1, 8},
- { 16800000, 594000000, 495, 14, 1, 8},
- { 19200000, 594000000, 495, 16, 1, 8},
- { 26000000, 594000000, 594, 26, 1, 8},
-
- { 12000000, 1000000000, 1000, 12, 1, 12},
- { 13000000, 1000000000, 1000, 13, 1, 12},
- { 19200000, 1000000000, 625, 12, 1, 8},
- { 26000000, 1000000000, 1000, 26, 1, 12},
+ { 12000000, 216000000, 216, 12, 0, 4},
+ { 13000000, 216000000, 216, 13, 0, 4},
+ { 16800000, 216000000, 180, 14, 0, 4},
+ { 19200000, 216000000, 180, 16, 0, 4},
+ { 26000000, 216000000, 216, 26, 0, 4},
+
+ { 12000000, 594000000, 594, 12, 0, 8},
+ { 13000000, 594000000, 594, 13, 0, 8},
+ { 16800000, 594000000, 495, 14, 0, 8},
+ { 19200000, 594000000, 495, 16, 0, 8},
+ { 26000000, 594000000, 594, 26, 0, 8},
+
+ { 12000000, 1000000000, 1000, 12, 0, 12},
+ { 13000000, 1000000000, 1000, 13, 0, 12},
+ { 19200000, 1000000000, 625, 12, 0, 8},
+ { 26000000, 1000000000, 1000, 26, 0, 12},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
- { 12000000, 480000000, 960, 12, 2, 12},
- { 13000000, 480000000, 960, 13, 2, 12},
- { 16800000, 480000000, 400, 7, 2, 5},
- { 19200000, 480000000, 200, 4, 2, 3},
- { 26000000, 480000000, 960, 26, 2, 12},
+ { 12000000, 480000000, 960, 12, 0, 12},
+ { 13000000, 480000000, 960, 13, 0, 12},
+ { 16800000, 480000000, 400, 7, 0, 5},
+ { 19200000, 480000000, 200, 4, 0, 3},
+ { 26000000, 480000000, 960, 26, 0, 12},
{ 0, 0, 0, 0, 0, 0 },
};
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
/* 1.7 GHz */
- { 12000000, 1700000000, 850, 6, 1, 8},
- { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
- { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
- { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
- { 26000000, 1700000000, 850, 13, 1, 8},
+ { 12000000, 1700000000, 850, 6, 0, 8},
+ { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
+ { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
+ { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
+ { 26000000, 1700000000, 850, 13, 0, 8},
/* 1.6 GHz */
- { 12000000, 1600000000, 800, 6, 1, 8},
- { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
- { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
- { 19200000, 1600000000, 500, 6, 1, 8},
- { 26000000, 1600000000, 800, 13, 1, 8},
+ { 12000000, 1600000000, 800, 6, 0, 8},
+ { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
+ { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
+ { 19200000, 1600000000, 500, 6, 0, 8},
+ { 26000000, 1600000000, 800, 13, 0, 8},
/* 1.5 GHz */
- { 12000000, 1500000000, 750, 6, 1, 8},
- { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
- { 16800000, 1500000000, 625, 7, 1, 8},
- { 19200000, 1500000000, 625, 8, 1, 8},
- { 26000000, 1500000000, 750, 13, 1, 8},
+ { 12000000, 1500000000, 750, 6, 0, 8},
+ { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
+ { 16800000, 1500000000, 625, 7, 0, 8},
+ { 19200000, 1500000000, 625, 8, 0, 8},
+ { 26000000, 1500000000, 750, 13, 0, 8},
/* 1.4 GHz */
- { 12000000, 1400000000, 700, 6, 1, 8},
- { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
- { 16800000, 1400000000, 1000, 12, 1, 8},
- { 19200000, 1400000000, 875, 12, 1, 8},
- { 26000000, 1400000000, 700, 13, 1, 8},
+ { 12000000, 1400000000, 700, 6, 0, 8},
+ { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
+ { 16800000, 1400000000, 1000, 12, 0, 8},
+ { 19200000, 1400000000, 875, 12, 0, 8},
+ { 26000000, 1400000000, 700, 13, 0, 8},
/* 1.3 GHz */
- { 12000000, 1300000000, 975, 9, 1, 8},
- { 13000000, 1300000000, 1000, 10, 1, 8},
- { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
- { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
- { 26000000, 1300000000, 650, 13, 1, 8},
+ { 12000000, 1300000000, 975, 9, 0, 8},
+ { 13000000, 1300000000, 1000, 10, 0, 8},
+ { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
+ { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
+ { 26000000, 1300000000, 650, 13, 0, 8},
/* 1.2 GHz */
- { 12000000, 1200000000, 1000, 10, 1, 8},
- { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
- { 16800000, 1200000000, 1000, 14, 1, 8},
- { 19200000, 1200000000, 1000, 16, 1, 8},
- { 26000000, 1200000000, 600, 13, 1, 8},
+ { 12000000, 1200000000, 1000, 10, 0, 8},
+ { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
+ { 16800000, 1200000000, 1000, 14, 0, 8},
+ { 19200000, 1200000000, 1000, 16, 0, 8},
+ { 26000000, 1200000000, 600, 13, 0, 8},
/* 1.1 GHz */
- { 12000000, 1100000000, 825, 9, 1, 8},
- { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
- { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
- { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
- { 26000000, 1100000000, 550, 13, 1, 8},
+ { 12000000, 1100000000, 825, 9, 0, 8},
+ { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
+ { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
+ { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
+ { 26000000, 1100000000, 550, 13, 0, 8},
/* 1 GHz */
- { 12000000, 1000000000, 1000, 12, 1, 8},
- { 13000000, 1000000000, 1000, 13, 1, 8},
- { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
- { 19200000, 1000000000, 625, 12, 1, 8},
- { 26000000, 1000000000, 1000, 26, 1, 8},
+ { 12000000, 1000000000, 1000, 12, 0, 8},
+ { 13000000, 1000000000, 1000, 13, 0, 8},
+ { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
+ { 19200000, 1000000000, 625, 12, 0, 8},
+ { 26000000, 1000000000, 1000, 26, 0, 8},
{ 0, 0, 0, 0, 0, 0 },
};
^ permalink raw reply related
* [PATCH v5 00/10] Tegra114 clockframework
From: Peter De Schrijver @ 2013-02-01 10:18 UTC (permalink / raw)
To: linux-arm-kernel
This is the fifth version of the Tegra114 clockframework. It is based on the
for-next branch of
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git and
http://www.spinics.net/lists/arm-kernel/msg220452.html.
It has been boottested on Pluto.
Changes from v4:
* Split the new PLL types patch into smaller patches
* Fix some bugs in the PLL patches
Changes from v3:
* Merge with for-next branch
* Provide empty tegra_cpu_car_ops to make SMP boot not crash
Changes from v2:
* Added missing PLLs
* Added bindings to tegra114.dtsi
* Moved the table patch for clk-mux.c to 'clk: add table lookup to mux'
* Bugfixes
Changes from v1:
* Remove SATA and PCIe clocks. They don't appear in the internal TRM, so I
assume they don't exist.
* Rebase on top of Hiroshi's latest Tegra114 patches
* More generic mux code. This is necessary for the AHUB and DAM clocks.
TODO:
* Remove clk_register_clkdev() where possible
* PLL clock init functions are incomplete and/or need refactoring
* Superclocks are missing
* The audio clocks are almost the same then Tegra30. Refactor the code to
avoid duplication.
* Should blink and blink_override be clocks?
Peter De Schrijver (10):
clk: tegra: Refactor PLL programming code
clk: tegra: Add TEGRA_PLL_BYPASS flag
clk: tegra: Add PLL post divider table
clk: tegra: Add new fields and PLL types for Tegra114
clk: tegra: Add flags to tegra_clk_periph()
clk: tegra: Workaround for Tegra114 MSENC problem
ARM: tegra: Define Tegra114 CAR binding
ARM: dt: Add references to tegra_car clocks
clk: tegra: Implement clocks for Tegra114
clk: tegra: devicetree match for nvidia,tegra114-car
.../bindings/clock/nvidia,tegra114-car.txt | 311 +++
arch/arm/boot/dts/tegra114.dtsi | 7 +-
drivers/clk/tegra/Makefile | 1 +
drivers/clk/tegra/clk-periph-gate.c | 9 +
drivers/clk/tegra/clk-periph.c | 11 +-
drivers/clk/tegra/clk-pll.c | 940 +++++++++-
drivers/clk/tegra/clk-tegra114.c | 2002 ++++++++++++++++++++
drivers/clk/tegra/clk-tegra20.c | 153 +-
drivers/clk/tegra/clk-tegra30.c | 243 ++--
drivers/clk/tegra/clk.c | 1 +
drivers/clk/tegra/clk.h | 85 +-
11 files changed, 3481 insertions(+), 282 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
create mode 100644 drivers/clk/tegra/clk-tegra114.c
^ permalink raw reply
* [PATCH v5 00/10] Tegra114 clockframework
From: Peter De Schrijver @ 2013-02-01 10:16 UTC (permalink / raw)
To: linux-arm-kernel
This is the fifth version of the Tegra114 clockframework. It is based on the
for-next branch of
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git and
http://www.spinics.net/lists/arm-kernel/msg220452.html.
It has been boottested on Pluto.
Changes from v4:
* Split the new PLL types patch into smaller patches
* Fix some bugs in the PLL patches
Changes from v3:
* Merge with for-next branch
* Provide empty tegra_cpu_car_ops to make SMP boot not crash
Changes from v2:
* Added missing PLLs
* Added bindings to tegra114.dtsi
* Moved the table patch for clk-mux.c to 'clk: add table lookup to mux'
* Bugfixes
Changes from v1:
* Remove SATA and PCIe clocks. They don't appear in the internal TRM, so I
assume they don't exist.
* Rebase on top of Hiroshi's latest Tegra114 patches
* More generic mux code. This is necessary for the AHUB and DAM clocks.
TODO:
* Remove clk_register_clkdev() where possible
* PLL clock init functions are incomplete and/or need refactoring
* Superclocks are missing
* The audio clocks are almost the same then Tegra30. Refactor the code to
avoid duplication.
* Should blink and blink_override be clocks?
Peter De Schrijver (10):
clk: tegra: Refactor PLL programming code
clk: tegra: Add TEGRA_PLL_BYPASS flag
clk: tegra: Add PLL post divider table
clk: tegra: Add new fields and PLL types for Tegra114
clk: tegra: Add flags to tegra_clk_periph()
clk: tegra: Workaround for Tegra114 MSENC problem
ARM: tegra: Define Tegra114 CAR binding
ARM: dt: Add references to tegra_car clocks
clk: tegra: Implement clocks for Tegra114
clk: tegra: devicetree match for nvidia,tegra114-car
.../bindings/clock/nvidia,tegra114-car.txt | 311 +++
arch/arm/boot/dts/tegra114.dtsi | 7 +-
drivers/clk/tegra/Makefile | 1 +
drivers/clk/tegra/clk-periph-gate.c | 9 +
drivers/clk/tegra/clk-periph.c | 11 +-
drivers/clk/tegra/clk-pll.c | 940 +++++++++-
drivers/clk/tegra/clk-tegra114.c | 2002 ++++++++++++++++++++
drivers/clk/tegra/clk-tegra20.c | 153 +-
drivers/clk/tegra/clk-tegra30.c | 243 ++--
drivers/clk/tegra/clk.c | 1 +
drivers/clk/tegra/clk.h | 85 +-
11 files changed, 3481 insertions(+), 282 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
create mode 100644 drivers/clk/tegra/clk-tegra114.c
^ permalink raw reply
* [PATCH 1/3] pinctrl: sunxi: Add of_xlate function
From: Linus Walleij @ 2013-02-01 9:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <51085315.2000302@free-electrons.com>
On Tue, Jan 29, 2013 at 11:54 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Le 29/01/2013 23:41, Linus Walleij a ?crit :
>> On Sun, Jan 27, 2013 at 8:02 PM, Maxime Ripard
>> <maxime.ripard@free-electrons.com> wrote:
>>
>>> Since the pin controller of sunxi chips is represented as a single bank
>>> in the driver.
>>> Since this is neither convenient nor represented that way in the
>>> datasheets, define a custom of_xlate function with the layout <bank pin
>>> flag>
>>>
>>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>>
>> This does not apply and I only have 1/3 it seems?
>>
>> Sorry, help me understand which order these patches go in...
>
> My bad, I forgot to mention the order of the patchsets, and to cc you
> for the all series... Sorry about that.
>
> This patch should come after the patch series that adds the support for
> the A10 SoCs in the pinctrl driver.
I now tried to apply this on top of the A10 series and it
*still* does not apply.
> Do you want me to resend this serie and cc you?
Please rebase these three on my allwinner branch:
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
allwinner-sunxi
Seen here:
http://git.kernel.org/?p=linux/kernel/git/linusw/linux-pinctrl.git;a=shortlog;h=refs/heads/allwinner-sunxi
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 5/5] ARM: sunxi: Add the pin groups for UART0 and UART1 on sun4i
From: Linus Walleij @ 2013-02-01 9:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359211016-24097-6-git-send-email-maxime.ripard@free-electrons.com>
On Sat, Jan 26, 2013 at 3:36 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Applied to my allwinner branch.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 4/5] ARM: sunxi: Add the sun4i pinctrl and gpio nodes
From: Linus Walleij @ 2013-02-01 9:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359211016-24097-5-git-send-email-maxime.ripard@free-electrons.com>
On Sat, Jan 26, 2013 at 3:36 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Applied to my allwinner branch.
Thanks,
Linus Walleij
^ permalink raw reply
* [PATCH 3/5] ARM: pinctrl: sunxi: Add the pinctrl pin set for Allwinner A10
From: Linus Walleij @ 2013-02-01 9:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359211016-24097-4-git-send-email-maxime.ripard@free-electrons.com>
On Sat, Jan 26, 2013 at 3:36 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Since the Allwinner SoCs variants don't have the same set of pins to
> handle, we need to declare the pin ranges available.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Applied to my allwinner branch.
Thanks,
Linus Walleij
^ permalink raw reply
* [PATCH 2/5] pinctrl: sunxi: Document sun5i pins functions
From: Linus Walleij @ 2013-02-01 9:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359211016-24097-3-git-send-email-maxime.ripard@free-electrons.com>
On Sat, Jan 26, 2013 at 3:36 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/pinctrl/pinctrl-sunxi.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
Applied to my allwinner branch.
Thanks,
Linus Walleij
^ permalink raw reply
* [PATCH 1/5] ARM: sunxi: Increase the number of GPIOs available
From: Linus Walleij @ 2013-02-01 9:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359211016-24097-2-git-send-email-maxime.ripard@free-electrons.com>
On Sat, Jan 26, 2013 at 3:36 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The Allwinner A10 has 9 banks of 32 GPIOs available, so it doesn't fit
> in the usual 256 limit set by gpio.h. Increase this number to 288.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Patch applied to the pinctrl tree on my allwinner branch,
with Arnd's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 5/5] ARM: OMAP3: Update clocksource timer selection
From: Bedia, Vaibhav @ 2013-02-01 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <510B8A0B.9000600@ti.com>
On Fri, Feb 01, 2013 at 14:55:31, Hunter, Jon wrote:
[...]
> >
> > I don't see this as being DT specific. It is more of a policy change to
> > ensure a wake-up domain timer is used for clocksource when we are using
> > gptimers for both clocksource and clockevents. It was your patch for
> > AM335x that made me see the need for this, if that makes sense. May be I
> > should have referenced that in the changelog.
>
> Sorry to be clear, I don't see the policy change as DT specific.
>
> In answer to your question, yes clkev_nr and clksrc_nr are changed so
> the policy it is consistent regardless of whether you use DT or not. In
> other words, an OMAP3 board using a gptimer for clocksource (such as
> cm-t3517) and does not use DT, would work the same as AM335x with DT.
>
Ok. Thanks for clarifying.
Regards,
Vaibhav
^ permalink raw reply
* [PATCH 1/5] ARM: OMAP2+: Display correct system timer name
From: Bedia, Vaibhav @ 2013-02-01 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <510B8297.8070305@ti.com>
On Fri, Feb 01, 2013 at 14:23:43, Hunter, Jon wrote:
[...]
> >>
> >> +/* Timer name needs to be big enough to store a string of "timerXX" */
> >> +static char timer_name[10];
> >> +
> >
> > Why not move this inside omap_dm_timer_init_one()?
>
> In the non-DT case, the name member of the clocksource/event struct will
> point to this array and so it needs to reside in memory permanently and
> not just temporary. Once we migrate completely to DT then we will be
> able to remove this completely. See following snippet ...
>
> - sprintf(name, "timer%d", gptimer_id);
> - oh_name = name;
> + sprintf(timer_name, "timer%d", gptimer_id);
> + *name = timer_name;
Ok. But in case of non-DT boot if someone selects gptimers for both clkevt and
clksrc, both the name members will end up pointing to the same memory location.
To be specific, in the current code the clkevt timer name will point to the clksrc
name. This won't be noticeable during boot since the clkevt name gets printed
before it is over-written.
Regards,
Vaibhav
^ permalink raw reply
* [PATCH 5/5] ARM: OMAP3: Update clocksource timer selection
From: Jon Hunter @ 2013-02-01 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <510B83D5.1090500@ti.com>
On 02/01/2013 02:59 AM, Jon Hunter wrote:
>
> On 02/01/2013 02:41 AM, Bedia, Vaibhav wrote:
>> Hi Jon,
>>
>> On Wed, Jan 30, 2013 at 22:34:31, Hunter, Jon wrote:
>>> When booting with device-tree for OMAP3 and AM335x devices and a gptimer
>>> is used as the clocksource (which is always the case for AM335x), a
>>> gptimer located in a power domain that is not always-on is selected.
>>> Ideally we should use a gptimer located in a power domain that is always
>>> on (such as the wake-up domain) so that time can be maintained during a
>>> kernel suspend without keeping on additional power domains unnecessarily.
>>>
>>> In order to fix this so that we can select a gptimer located in a power
>>> domain that is always-on, the following changes were made ...
>>> 1. Currently, only when selecting a gptimer to use for a clockevent
>>> timer, do we pass a timer property that can be used to select a
>>> specific gptimer. Change this so that we can pass a property when
>>> selecting a gptimer to use for a clocksource timer too.
>>> 2. Currently, when selecting either a gptimer to use for a clockevent
>>> timer or a clocksource timer and no timer property is passed, then
>>> the first available timer is selected regardless of the properties
>>> it has. Change this so that if no properties are passed, then a timer
>>> that does not have additional features (such as always-on, dsp-irq,
>>> pwm, and secure) is selected.
>>>
>>> Please note that using a gptimer for both clocksource and clockevents
>>> can have a system power impact during idle. The reason being is that
>>> OMAP and AMxxx devices typically only have one gptimer in a power domain
>>> that is always-on. Therefore when the kernel is idle both the clocksource
>>> and clockevent timers will be active and this will keep additional power
>>> domains on. During kernel suspend, only the clocksource timer is active
>>> and therefore, it is better to use a gptimer in a power domain that is
>>> always-on for clocksource.
>>>
>>
>> It's always a pleasure reading the changelog in your patches :)
>
> Thanks.
>
>> [...]
>>>
>>> #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
>>> -OMAP_SYS_GP_TIMER_INIT(3, 1, "timer_sys_ck", "ti,timer-alwon",
>>> - 2, "timer_sys_ck");
>>> +OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
>>> + 1, "timer_sys_ck", "ti,timer-alwon");
>>> #endif
>>>
>>
>> Minor point... was the intention of changing of clkev_nr and clksrc_nr to make
>> it consistent with what happens on AM33xx which is DT-only?
>
> I don't see this as being DT specific. It is more of a policy change to
> ensure a wake-up domain timer is used for clocksource when we are using
> gptimers for both clocksource and clockevents. It was your patch for
> AM335x that made me see the need for this, if that makes sense. May be I
> should have referenced that in the changelog.
Sorry to be clear, I don't see the policy change as DT specific.
In answer to your question, yes clkev_nr and clksrc_nr are changed so
the policy it is consistent regardless of whether you use DT or not. In
other words, an OMAP3 board using a gptimer for clocksource (such as
cm-t3517) and does not use DT, would work the same as AM335x with DT.
Cheers
Jon
^ permalink raw reply
* [PATCH 00/10] ARM: OMAP5: hwmod, clock and prm data files
From: Santosh Shilimkar @ 2013-02-01 9:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358522856-12180-1-git-send-email-santosh.shilimkar@ti.com>
Tony,
On Friday 18 January 2013 08:57 PM, Santosh Shilimkar wrote:
> Series contains the hwmod, clock and prm data files for OMAP54xx SOCs.
> This data was kept out of tree to be validated on es2.0 silicon version
> and also to avoid the es1.0/es2.0 differences which are many.
>
> Benoit Cousson, Rajendra Nayak, Paul Walmesly and Mike have all contributed
> to get the autogen scripts in shape for OMAP5.
>
> From various discussion on the list, the clock data files are suppose
> to be moved to drivers/clk/. Once the direction is clear, patch 8
> can be updated accordingly.
>
> Patches are tested on OMAP5 sEVM and uEVM. For testing few additional patches
> are needed. Same tree can be fetched from here [1]
>
> The following changes since commit 7d1f9aeff1ee4a20b1aeb377dd0f579fe9647619:
>
> Linux 3.8-rc4 (2013-01-17 19:25:45 -0800)
>
> are available in the git repository at:
>
> git://github.com/SantoshShilimkar/linux.git for_3.9/omap5_data_files
>
> for you to fetch changes up to 7f534e1ebeb2bc64250b56fe00eb7d4dfa585e8e:
>
> ARM: OMAP5: Enable build and frameowrk initialisations (2013-01-18 19:45:48 +0530)
>
> ----------------------------------------------------------------
>
> Benoit Cousson (7):
> ARM: OMAP5: PRM: Add OMAP54XX register and bitfield files
> ARM: OMAP5: CM: Add OMAP54XX register and bitfield files
> ARM: OMAP5: PRCM: Add OMAP54XX local MPU PRCM registers
> ARM: OMAP5: SCRM: Add OMAP54XX header file.
> ARM: OMAP2+: clockdomain data: Add OMAP54XX data and update the
> header
> ARM: OMAP5: powerdomain data: Add OMAP54XX data and update the header
> ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
>
> Rajendra Nayak (1):
> ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
>
> Santosh Shilimkar (2):
> ARM: OMAP5: voltagedomain data: Add OMAP5 voltage domain data
> ARM: OMAP5: Enable build and frameowrk initialisations
>
As discussed on the list, I am going to drop the clock-data[7/10]
and build patch[10/10] and prepare a pull request. Let me know
if thats fine with you.
Regards,
Santosh
^ permalink raw reply
* [PATCH v3] arm: mvebu: support for the new Armada XP development board(DB-MV784MP-GP)
From: Ezequiel Garcia @ 2013-02-01 9:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359643812-32654-2-git-send-email-gregory.clement@free-electrons.com>
On Thu, Jan 31, 2013 at 03:50:12PM +0100, Gregory CLEMENT wrote:
> This is the new Armada XP evaluation board from Marvell. It comes with
> a RS232 port over USB, a SATA link, an internal SSD, 4 Ethernet
> Gigabit links.
>
> Support for USB (Host and device), SDIO, PCIe will be added as drivers
> when they become available for Armada XP in mainline.
>
> Tested-by: Simon Guinot <simon.guinot@sequanux.org>
> Tested-by: Florian Fainelli <florian@openwrt.org>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/armada-xp-gp.dts | 101 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 102 insertions(+)
> create mode 100644 arch/arm/boot/dts/armada-xp-gp.dts
>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Regards,
--
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems
From: Thomas Petazzoni @ 2013-02-01 9:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130201035115.GA23649@obsidianresearch.com>
Dear Jason Gunthorpe,
Thanks again for continuing this discussion while I was sleeping :-)
On Thu, 31 Jan 2013 20:51:15 -0700, Jason Gunthorpe wrote:
> > Now, I do have one follow-on question: You said you don't have 30
> > windows, but how many do you have free after allocating windows to
> > any other peripherals that need them, relative to (3 *
> > number-of-root-ports-in-the-SoC)? (3 being IO+Mem+PrefetchableMem.)
>
> Thomas will have to answer this, it varies depending on the SOC, and
> what other on chip peripherals are in use. For instance Kirkwood has
> the same design but there are plenty of windows for the two PCI-E
> links.
Right. I already answered this point directly to Stephen. On Kirkwood,
there are many windows and two PCIe links, so the windows were
statically allocated. On Armada XP, there are 20 windows and 10 PCIe
links. Static allocation is no longer reasonable.
> > The thing here is that when the PCIe core writes to a root port BAR
> > window to configure/enable it the first time, you'll need to capture
> > that transaction and dynamically allocate a window and program it
> > in a way equivalent to what the BAR register write would have
> > achieved on standard HW. Later, the window might need resizing, or
> > even to be completely disabled, if the PCIe core were to change the
> > standard BAR
>
> Right. This is pretty straightforward except for the need to hook the
> alignment fixup..
>
> > register. Dynamically allocating a window when the BAR is written
> > seems a little heavy-weight.
>
> I think what Thomas had here was pretty small, and the windows need to
> be shared with other on chip periphals beyond PCI-E..
Yes, it is not very complicated. We already have some common code that
creates/removes those windows, so it is just a matter of calling the
right thing at the right time. Definitely not hundreds of line of crap.
> Right, this is the main point. If you plug in 3 devices and they all
> only use MMIO regions then you only need to grab 3 windows. The kernel
> disables the unused windows on the bridge so it is easy to tell when
> they are disused.
Ah, I'm interested in further discussing this. I currently have a setup
with one SATA PCIe card and one NIC PCIe card. On the NIC, the I/O
ports are said to be "disabled", but still an I/O region gets allocated
in the PCI-to-PCI bridge that gives access to this particular device.
The device in question is:
05:00.0 Ethernet controller: Intel Corporation 82572EI Gigabit Ethernet Controller (Copper) (rev 06)
Subsystem: Intel Corporation PRO/1000 PT Server Adapter
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 106
Region 0: Memory at c1200000 (32-bit, non-prefetchable) [size=128K]
Region 1: Memory at c1220000 (32-bit, non-prefetchable) [size=128K]
Region 2: I/O ports at c0010000 [disabled] [size=32]
[virtual] Expansion ROM@c1300000 [disabled] [size=128K]
So the Region 2 is disabled. But, in the corresponding bridge:
00:05.0 PCI bridge: Marvell Technology Group Ltd. Device 1092 (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF+ FastB2B+ ParErr+ DEVSEL=?? >TAbort+ <TAbort+ <MAbort+ >SERR+ <PERR+ INTx+
Latency: 0, Cache Line Size: 64 bytes
Bus: primary=00, secondary=05, subordinate=05, sec-latency=0
I/O behind bridge: c0010000-c001ffff
Memory behind bridge: c1200000-c12fffff
Prefetchable memory behind bridge: c1300000-c13fffff
So there is really a range of I/O addresses associated to it, even
though the device will apparently not use it. Would it be possible to
detect that the I/O range is not used by the device, and therefore
avoid the allocation of an address decoding window for this I/O range?
> Agreed.. At the very least generic code would need call back
> functions to the driver... It has a fair bit to do for Marvell:
> - Translate MMIO, prefetch and IO ranges to mbus windows
> - Keep track of the secondary/subordinate bus numbers and fiddle
> with other hardware registers to set those up
> - Copy the link state/control regsiters from the end port config
> space into the bridge express root port capability
> - Probably ditto for AER as well..
>
> Probably simpler just to make one for marvell then mess excessively
> with callbacks..
As replied to Stephen, I've chosen to bring the PCI-to-PCI bridge
emulation code directly into the driver, specifically for this reason.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 4/9] USB: chipidea: add PTW and PTS handling
From: Michael Grzeschik @ 2013-02-01 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359705132-9434-5-git-send-email-s.hauer@pengutronix.de>
On Fri, Feb 01, 2013 at 08:52:07AM +0100, Sascha Hauer wrote:
> From: Michael Grzeschik <m.grzeschik@pengutronix.de>
>
> This patch makes it possible to configure the PTW and PTS bits inside
> the portsc register for host and device mode before the driver starts
> and the phy can be addressed as hardware implementation is designed.
>
> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> .../devicetree/bindings/usb/ci13xxx-imx.txt | 5 +++
> drivers/usb/chipidea/bits.h | 14 ++++++-
> drivers/usb/chipidea/ci13xxx_imx.c | 3 ++
> drivers/usb/chipidea/core.c | 39 ++++++++++++++++++++
> include/linux/usb/chipidea.h | 1 +
> 5 files changed, 61 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> index 5778b9c..dd42ccd 100644
> --- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> +++ b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> @@ -5,6 +5,11 @@ Required properties:
> - reg: Should contain registers location and length
> - interrupts: Should contain controller interrupt
>
> +Recommended properies:
> +- phy_type: the type of the phy connected to the core. Should be one
> + of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
> + property the PORTSC register won't be touched
> +
> Optional properties:
> - fsl,usbphy: phandler of usb phy that connects to the only one port
> - fsl,usbmisc: phandler of non-core register device, with one argument
> diff --git a/drivers/usb/chipidea/bits.h b/drivers/usb/chipidea/bits.h
> index 050de85..d8ffc2f 100644
> --- a/drivers/usb/chipidea/bits.h
> +++ b/drivers/usb/chipidea/bits.h
> @@ -48,10 +48,22 @@
> #define PORTSC_SUSP BIT(7)
> #define PORTSC_HSP BIT(9)
> #define PORTSC_PTC (0x0FUL << 16)
> +/* PTS and PTW for non lpm version only */
> +#define PORTSC_PTS(d) ((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0))
> +#define PORTSC_PTW BIT(28)
>
> /* DEVLC */
> #define DEVLC_PSPD (0x03UL << 25)
> -#define DEVLC_PSPD_HS (0x02UL << 25)
> +#define DEVLC_PSPD_HS (0x02UL << 25)
> +#define DEVLC_PTW BIT(27)
> +#define DEVLC_STS BIT(28)
> +#define DEVLC_PTS(d) (((d) & 0x7) << 29)
> +
> +/* Encoding for DEVLC_PTS and PORTSC_PTS */
> +#define PTS_UTMI 0
> +#define PTS_ULPI 2
> +#define PTS_SERIAL 3
> +#define PTS_HSIC 4
>
> /* OTGSC */
> #define OTGSC_IDPU BIT(5)
> diff --git a/drivers/usb/chipidea/ci13xxx_imx.c b/drivers/usb/chipidea/ci13xxx_imx.c
> index 69024e0..ebc1148 100644
> --- a/drivers/usb/chipidea/ci13xxx_imx.c
> +++ b/drivers/usb/chipidea/ci13xxx_imx.c
> @@ -21,6 +21,7 @@
> #include <linux/clk.h>
> #include <linux/regulator/consumer.h>
> #include <linux/pinctrl/consumer.h>
> +#include <linux/usb/of.h>
>
> #include "ci.h"
> #include "ci13xxx_imx.h"
> @@ -112,6 +113,8 @@ static int ci13xxx_imx_probe(struct platform_device *pdev)
> CI13XXX_PULLUP_ON_VBUS |
> CI13XXX_DISABLE_STREAMING;
>
> + pdata->phy_mode = of_usb_get_phy_mode(pdev->dev.of_node);
> +
> data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> if (!data) {
> dev_err(&pdev->dev, "Failed to allocate CI13xxx-IMX data!\n");
> diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
> index 57cae1f..a3ec29d 100644
> --- a/drivers/usb/chipidea/core.c
> +++ b/drivers/usb/chipidea/core.c
> @@ -67,6 +67,8 @@
> #include <linux/usb/gadget.h>
> #include <linux/usb/otg.h>
> #include <linux/usb/chipidea.h>
> +#include <linux/usb/of.h>
> +#include <linux/phy.h>
>
> #include "ci.h"
> #include "udc.h"
> @@ -211,6 +213,41 @@ static int hw_device_init(struct ci13xxx *ci, void __iomem *base)
> return 0;
> }
>
> +static void hw_phymode_configure(struct ci13xxx *ci)
> +{
> + u32 portsc, lpm;
> +
> + switch (ci->platdata->phy_mode) {
> + case USBPHY_INTERFACE_MODE_UTMI:
> + portsc = PORTSC_PTS(PTS_UTMI);
> + lpm = DEVLC_PTS(PTS_UTMI);
> + break;
> + case USBPHY_INTERFACE_MODE_UTMIW:
> + portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
> + lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
> + break;
> + case USBPHY_INTERFACE_MODE_ULPI:
> + portsc = PORTSC_PTS(PTS_ULPI);
> + lpm = DEVLC_PTS(PTS_ULPI);
> + break;
> + case USBPHY_INTERFACE_MODE_SERIAL:
> + portsc = PORTSC_PTS(PTS_SERIAL);
> + lpm = DEVLC_PTS(PTS_SERIAL);
> + break;
> + case USBPHY_INTERFACE_MODE_HSIC:
> + portsc = PORTSC_PTS(PTS_HSIC);
> + lpm = DEVLC_PTS(PTS_HSIC);
> + break;
> + default:
> + return;
> + }
> +
> + if (ci->hw_bank.lpm)
> + hw_write(ci, OP_PORTSC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
^^^^^^^^^
This is probably supposed to be OP_DEVLC.
> + else
> + hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
> +}
> +
> /**
> * hw_device_reset: resets chip (execute without interruption)
> * @ci: the controller
> @@ -476,6 +513,8 @@ static int ci_hdrc_probe(struct platform_device *pdev)
> : CI_ROLE_GADGET;
> }
>
> + hw_phymode_configure(ci);
> +
> ret = ci_role_start(ci, ci->role);
> if (ret) {
> dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
> diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h
> index 544825d..1a2aa18 100644
> --- a/include/linux/usb/chipidea.h
> +++ b/include/linux/usb/chipidea.h
> @@ -14,6 +14,7 @@ struct ci13xxx_platform_data {
> uintptr_t capoffset;
> unsigned power_budget;
> struct usb_phy *phy;
> + enum usb_phy_interface phy_mode;
> unsigned long flags;
> #define CI13XXX_REGS_SHARED BIT(0)
> #define CI13XXX_REQUIRE_TRANSCEIVER BIT(1)
> --
> 1.7.10.4
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 5/5] ARM: OMAP3: Update clocksource timer selection
From: Jon Hunter @ 2013-02-01 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <B5906170F1614E41A8A28DE3B8D121433ED07250@DBDE01.ent.ti.com>
On 02/01/2013 02:41 AM, Bedia, Vaibhav wrote:
> Hi Jon,
>
> On Wed, Jan 30, 2013 at 22:34:31, Hunter, Jon wrote:
>> When booting with device-tree for OMAP3 and AM335x devices and a gptimer
>> is used as the clocksource (which is always the case for AM335x), a
>> gptimer located in a power domain that is not always-on is selected.
>> Ideally we should use a gptimer located in a power domain that is always
>> on (such as the wake-up domain) so that time can be maintained during a
>> kernel suspend without keeping on additional power domains unnecessarily.
>>
>> In order to fix this so that we can select a gptimer located in a power
>> domain that is always-on, the following changes were made ...
>> 1. Currently, only when selecting a gptimer to use for a clockevent
>> timer, do we pass a timer property that can be used to select a
>> specific gptimer. Change this so that we can pass a property when
>> selecting a gptimer to use for a clocksource timer too.
>> 2. Currently, when selecting either a gptimer to use for a clockevent
>> timer or a clocksource timer and no timer property is passed, then
>> the first available timer is selected regardless of the properties
>> it has. Change this so that if no properties are passed, then a timer
>> that does not have additional features (such as always-on, dsp-irq,
>> pwm, and secure) is selected.
>>
>> Please note that using a gptimer for both clocksource and clockevents
>> can have a system power impact during idle. The reason being is that
>> OMAP and AMxxx devices typically only have one gptimer in a power domain
>> that is always-on. Therefore when the kernel is idle both the clocksource
>> and clockevent timers will be active and this will keep additional power
>> domains on. During kernel suspend, only the clocksource timer is active
>> and therefore, it is better to use a gptimer in a power domain that is
>> always-on for clocksource.
>>
>
> It's always a pleasure reading the changelog in your patches :)
Thanks.
> [...]
>>
>> #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
>> -OMAP_SYS_GP_TIMER_INIT(3, 1, "timer_sys_ck", "ti,timer-alwon",
>> - 2, "timer_sys_ck");
>> +OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
>> + 1, "timer_sys_ck", "ti,timer-alwon");
>> #endif
>>
>
> Minor point... was the intention of changing of clkev_nr and clksrc_nr to make
> it consistent with what happens on AM33xx which is DT-only?
I don't see this as being DT specific. It is more of a policy change to
ensure a wake-up domain timer is used for clocksource when we are using
gptimers for both clocksource and clockevents. It was your patch for
AM335x that made me see the need for this, if that makes sense. May be I
should have referenced that in the changelog.
Cheers
Jon
^ permalink raw reply
* [PATCH 1/1] net: fec: fix miss init spinlock
From: Frank Li @ 2013-02-01 8:56 UTC (permalink / raw)
To: linux-arm-kernel
BUG: spinlock bad magic on CPU#1, swapper/0/1
lock: 0xbfae0f8c, .magic: 00000000, .owner: <none>/-1, .owner_cpu: 0
Backtrace:
[<80011d54>] (dump_backtrace+0x0/0x10c) from [<804e7800>] (dump_stack+0x18/0x1c)
r6:bfae0000 r5:bfae0f8c r4:00000000 r3:806c1310
[<804e77e8>] (dump_stack+0x0/0x1c) from [<804e9f20>] (spin_dump+0x80/0x94)
[<804e9ea0>] (spin_dump+0x0/0x94) from [<804e9f60>] (spin_bug+0x2c/0x30)
r5:805f6f8c r4:bfae0f8c
[<804e9f34>] (spin_bug+0x0/0x30) from [<80257984>] (do_raw_spin_lock+0x170/0x1b0 )
r5:806b4950 r4:bfae0f8c
[<80257814>] (do_raw_spin_lock+0x0/0x1b0) from [<804ed15c>] (_raw_spin_lock_irqs ave+0x18/0x20)
[<804ed144>] (_raw_spin_lock_irqsave+0x0/0x20) from [<8033c694>] (fec_ptp_start_ cyclecounter+0x3c/0x120)
r4:bfae0f8c r3:00000002
[<8033c658>] (fec_ptp_start_cyclecounter+0x0/0x120) from [<80339e08>] (fec_resta rt+0x56c/0x5f8)
r8:00000000 r7:806e6f48 r6:00000112 r5:806b4950 r4:bfae0000
[<8033989c>] (fec_restart+0x0/0x5f8) from [<8033b9e4>] (fec_probe+0x508/0xa48)
Signed-off-by: Frank Li <Frank.Li@freescale.com>
---
drivers/net/ethernet/freescale/fec.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index 69b16b9..f900ae4 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -1607,6 +1607,7 @@ static int fec_enet_init(struct net_device *ndev)
}
spin_lock_init(&fep->hw_lock);
+ spin_lock_init(&fep->tmreg_lock);
fep->netdev = ndev;
--
1.7.1
^ permalink raw reply related
* [PATCH 1/5] ARM: OMAP2+: Display correct system timer name
From: Jon Hunter @ 2013-02-01 8:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <B5906170F1614E41A8A28DE3B8D121433ED07255@DBDE01.ent.ti.com>
Hi Vaibhav,
On 02/01/2013 02:41 AM, Bedia, Vaibhav wrote:
> Hi Jon,
>
> On Wed, Jan 30, 2013 at 22:34:27, Hunter, Jon wrote:
>> Currently on boot, when displaying the name of the gptimer used for
>> clockevents and clocksource timers, the timer ID is shown. However,
>> when booting with device-tree, the timer ID is not used to select a
>> gptimer but a timer property. Hence, it is possible that the timer
>> selected when booting with device-tree does not match the ID shown.
>> Therefore, instead display the HWMOD name of the gptimer and use
>> the HWMOD name as the name of clockevent and clocksource timer (if a
>> gptimer is used).no
>>
>> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
>> ---
>> arch/arm/mach-omap2/timer.c | 44 +++++++++++++++++++++----------------------
>> 1 file changed, 22 insertions(+), 22 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
>> index 72c2ca1..18cb856 100644
>> --- a/arch/arm/mach-omap2/timer.c
>> +++ b/arch/arm/mach-omap2/timer.c
>> @@ -71,6 +71,9 @@
>> #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
>> #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
>>
>> +/* Timer name needs to be big enough to store a string of "timerXX" */
>> +static char timer_name[10];
>> +
>
> Why not move this inside omap_dm_timer_init_one()?
In the non-DT case, the name member of the clocksource/event struct will
point to this array and so it needs to reside in memory permanently and
not just temporary. Once we migrate completely to DT then we will be
able to remove this completely. See following snippet ...
- sprintf(name, "timer%d", gptimer_id);
- oh_name = name;
+ sprintf(timer_name, "timer%d", gptimer_id);
+ *name = timer_name;
Cheers
Jon
^ permalink raw reply
* [PATCH] ARM: nomadik: fix OF compilation regression
From: Linus Walleij @ 2013-02-01 8:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
The Nomadik Device Tree patch series accidentally
selected OF instead of USE_OF which led to problems
during compile:
arch/arm/kernel/devtree.c: In function 'arm_dt_memblock_reserve':
/home/elinwal/linux-arm-soc/arch/arm/kernel/devtree.c:43:7: error: 'initial_boot_params' undeclared (first use in this function)
(etc).
This fixes it up by selecting USE_OF instead.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ARM SoC guys: this applies to your nomadik/dt branch.
Please apply it directly.
---
arch/arm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bef46ed..42ee64e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -904,7 +904,7 @@ config ARCH_NOMADIK
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_CACHE_L2X0
- select OF
+ select USE_OF
select PINCTRL
select PINCTRL_STN8815
select SPARSE_IRQ
--
1.7.11.3
^ permalink raw reply related
* [PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems
From: Thomas Petazzoni @ 2013-02-01 8:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <510B268E.2040104@wwwdotorg.org>
Dear Stephen Warren,
Thanks for this great discussion. I see that Jason has already answered
most of the questions on the why we need this "dynamicity" in the window
configuration. A few comments below.
On Thu, 31 Jan 2013 19:21:02 -0700, Stephen Warren wrote:
> So, the dynamic programming of the windows on Marvell HW is the exact
> logical equivalent of programming a standard PCIe root port's BAR
> registers. It makes perfect sense that should be dynamic. Presumably
> this is something you can make work inside your emulated PCIe/PCIe
> bridge module, simply by capturing writes to the BAR registers, and
> translating them into writes to the Marvell window registers.
That's what I'm doing. In the PATCHv2, my PCIe host driver was reading
back the BARs in the PCI-to-PCI bridges configuration space, and was
setting up the windows according to the addresses that had been
assigned to each bridge.
I am currently working in making this more dynamic: it is directly when
the BAR is being written to in the PCI-to-PCI bridge configuration
space that a window will be setup.
> Now, I do have one follow-on question: You said you don't have 30
> windows, but how many do you have free after allocating windows to any
> other peripherals that need them, relative to (3 *
> number-of-root-ports-in-the-SoC)? (3 being IO+Mem+PrefetchableMem.)
We have 20 windows on Armada XP if I remember correctly, and they are
not only used for PCIe, but also to map the BootROM (needed to boot
secondary CPUs), to map SPI flashes or NOR flashes, for example. So
they are really shared between many uses. In terms of PCIe, there are
only two types of windows: I/O and Memory, there is no notion of
Prefetchable Memory window as far as I could see.
We have up to 10 PCIe interfaces, and only 20 windows. It means that
you basically can't use all PCIe interfaces, there will necessarily be
some limit, due to the limited number of windows.
Also, I'd like to point out that the dynamic configuration is needed
for two reasons:
* The number of windows, as we are discussing now.
* The amount of physical address space available. If you don't
dynamically configure those windows, then you have to account the
"worst case", i.e the PCIe devices that require very large memory
areas. So you end up creating static windows that reserve 32M or 64M
or 128M *per* PCIe link. You can see that it "consumes" pretty
quickly a large part of the 4G physical address space that we have.
Thanks to the dynamic window configuration that we do with the
PCI-to-PCI bridge, we can size the windows exactly the size needed
by the downstream device on each PCIe interface.
> The thing here is that when the PCIe core writes to a root port BAR
> window to configure/enable it the first time, you'll need to capture
> that transaction and dynamically allocate a window and program it in a
> way equivalent to what the BAR register write would have achieved on
> standard HW. Later, the window might need resizing, or even to be
> completely disabled, if the PCIe core were to change the standard BAR
> register. Dynamically allocating a window when the BAR is written
> seems a little heavy-weight.
Why?
> So while it's obvious that window base address and size shouldn't be
> static, I wonder if the assignment of a specific window ID to a
> specific root port ID shouldn be dynamic or static. For example, if
> your HW configuration leaves you with 6 windows available, you could
> support 2 PCIe root ports by statically assigning 3 windows to serve
> each of those 2 root ports. Would that work, or are there systems
> where over-commit is needed, e.g. if there's no IO space behind a
> root port, you could get away with two windows per root port, and
> hence be able to run 3 root ports rather than just 2? Still, if you
> know which PCIe devices are being the root ports, you could still
> represent the over-commit statically in DT
For now, I haven't figured out how not to allocate an I/O window if the
downstream device doesn't use I/O, but I'd like to achieve that, as it
would save one of the two windows needed per PCIe interface... and many
PCIe devices don't need the I/O window.
> Still, I supose doing it dynamically in the driver does end up being a
> lot less to think about for someone creating the DT for a new board.
Indeed.
> Having to translate standard root port BAR register writes to Marvell
> window register allocation/writes would imply that the emulated root
> port code has to be very closely tied into the Marvell PCIe driver,
> and not something that could be at all generic in the most part.
Right. I've already moved the PCI-to-PCI bridge code from the generic
drivers/pci/sw-pci-pci-bridge.c location to be directly into the
driver. It also to integrate more tightly things like window allocation.
> Right. Now that I really understand what the windows are doing, I can
> see that a static window configuration (address/size, perhaps rather
> than windows are used) would not be appropriate.
Glad to see we reached the same conclusion :-)
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [GIT PULL] Nomadik devicetree and cleanups
From: Linus Walleij @ 2013-02-01 8:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130131232015.GA3314@quad.lixom.net>
On Fri, Feb 1, 2013 at 12:20 AM, Olof Johansson <olof@lixom.net> wrote:
> On Wed, Jan 30, 2013 at 11:21:06PM +0100, Linus Walleij wrote:
>> So as I heard this blew up for selecting OF instead of USE_OF here
>> is yet another pull request, with this oneliner change in the relevant
>> patch ("ARM: nomadik: delete old board files"):
>>
>> - select OF
>> + select USE_OF
>>
>> I have tried to provoke builderrors with the defconfig but couldn't.
>>
>> Here is then yet another pull request, and let's hope it works this
>> time around:
>
> Dropping and replacing branches is awkward, and you rewrote history here. It'd
> be better to just take a fixup patch on top that switches the two selects.
Sure, I'll fix...
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 5/5] ARM: OMAP3: Update clocksource timer selection
From: Bedia, Vaibhav @ 2013-02-01 8:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359565471-30721-6-git-send-email-jon-hunter@ti.com>
Hi Jon,
On Wed, Jan 30, 2013 at 22:34:31, Hunter, Jon wrote:
> When booting with device-tree for OMAP3 and AM335x devices and a gptimer
> is used as the clocksource (which is always the case for AM335x), a
> gptimer located in a power domain that is not always-on is selected.
> Ideally we should use a gptimer located in a power domain that is always
> on (such as the wake-up domain) so that time can be maintained during a
> kernel suspend without keeping on additional power domains unnecessarily.
>
> In order to fix this so that we can select a gptimer located in a power
> domain that is always-on, the following changes were made ...
> 1. Currently, only when selecting a gptimer to use for a clockevent
> timer, do we pass a timer property that can be used to select a
> specific gptimer. Change this so that we can pass a property when
> selecting a gptimer to use for a clocksource timer too.
> 2. Currently, when selecting either a gptimer to use for a clockevent
> timer or a clocksource timer and no timer property is passed, then
> the first available timer is selected regardless of the properties
> it has. Change this so that if no properties are passed, then a timer
> that does not have additional features (such as always-on, dsp-irq,
> pwm, and secure) is selected.
>
> Please note that using a gptimer for both clocksource and clockevents
> can have a system power impact during idle. The reason being is that
> OMAP and AMxxx devices typically only have one gptimer in a power domain
> that is always-on. Therefore when the kernel is idle both the clocksource
> and clockevent timers will be active and this will keep additional power
> domains on. During kernel suspend, only the clocksource timer is active
> and therefore, it is better to use a gptimer in a power domain that is
> always-on for clocksource.
>
It's always a pleasure reading the changelog in your patches :)
[...]
>
> #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
> -OMAP_SYS_GP_TIMER_INIT(3, 1, "timer_sys_ck", "ti,timer-alwon",
> - 2, "timer_sys_ck");
> +OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
> + 1, "timer_sys_ck", "ti,timer-alwon");
> #endif
>
Minor point... was the intention of changing of clkev_nr and clksrc_nr to make
it consistent with what happens on AM33xx which is DT-only?
Regards,
Vaibhav
^ permalink raw reply
* [PATCH 0/5] ARM: OMAP2+: System timer updates
From: Bedia, Vaibhav @ 2013-02-01 8:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359565471-30721-1-git-send-email-jon-hunter@ti.com>
Hi Jon,
On Wed, Jan 30, 2013 at 22:34:26, Hunter, Jon wrote:
> This series consists mainly of clean-ups for clockevents and
> clocksource timers on OMAP2+ devices. The most significant change
> in functionality comes from the 5th patch which is changing the
> selection of the clocksource timer for OMAP3 and AM335x devices
> when gptimers are used for clocksource. This change came about from
> Vaibhav Bedia's series for AM335x [1]. See patch for more details on
> the exact nature of the change.
>
> Boot tested with and without device-tree on OMAP2420 H4,
> OMAP3430 SDP, OMAP3430 Beagle Board, OMAP4430 SDP and
> AM335x EVM (AM335x only supports device-tree boot).
>
Thanks for working on this. I have couple of minor comments but with this
series in place I can drop the patch for interchanging the timers for AM33xx
and the suspend-resume handlers for the clockevent also don't need the
sprintf() that I had :)
Reviewed-and-Tested-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
^ permalink raw reply
* [PATCH 1/5] ARM: OMAP2+: Display correct system timer name
From: Bedia, Vaibhav @ 2013-02-01 8:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359565471-30721-2-git-send-email-jon-hunter@ti.com>
Hi Jon,
On Wed, Jan 30, 2013 at 22:34:27, Hunter, Jon wrote:
> Currently on boot, when displaying the name of the gptimer used for
> clockevents and clocksource timers, the timer ID is shown. However,
> when booting with device-tree, the timer ID is not used to select a
> gptimer but a timer property. Hence, it is possible that the timer
> selected when booting with device-tree does not match the ID shown.
> Therefore, instead display the HWMOD name of the gptimer and use
> the HWMOD name as the name of clockevent and clocksource timer (if a
> gptimer is used).
>
> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
> ---
> arch/arm/mach-omap2/timer.c | 44 +++++++++++++++++++++----------------------
> 1 file changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 72c2ca1..18cb856 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -71,6 +71,9 @@
> #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
> #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
>
> +/* Timer name needs to be big enough to store a string of "timerXX" */
> +static char timer_name[10];
> +
Why not move this inside omap_dm_timer_init_one()?
Regards,
Vaibhav
^ permalink raw reply
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