* [PATCH v6 2/8] usb: chipidea: add otg file
From: Peter Chen @ 2013-02-04 3:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359947039-23906-1-git-send-email-peter.chen@freescale.com>
Implement struct usb_otg, In that way, calling otg_set_peripheral
will not be failed at udc.c.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
---
drivers/usb/chipidea/Makefile | 2 +-
drivers/usb/chipidea/ci.h | 2 +
drivers/usb/chipidea/otg.c | 60 +++++++++++++++++++++++++++++++++++++++++
drivers/usb/chipidea/otg.h | 6 ++++
4 files changed, 69 insertions(+), 1 deletions(-)
create mode 100644 drivers/usb/chipidea/otg.c
create mode 100644 drivers/usb/chipidea/otg.h
diff --git a/drivers/usb/chipidea/Makefile b/drivers/usb/chipidea/Makefile
index d92ca32..11f513c 100644
--- a/drivers/usb/chipidea/Makefile
+++ b/drivers/usb/chipidea/Makefile
@@ -2,7 +2,7 @@ ccflags-$(CONFIG_USB_CHIPIDEA_DEBUG) := -DDEBUG
obj-$(CONFIG_USB_CHIPIDEA) += ci_hdrc.o
-ci_hdrc-y := core.o
+ci_hdrc-y := core.o otg.o
ci_hdrc-$(CONFIG_USB_CHIPIDEA_UDC) += udc.o
ci_hdrc-$(CONFIG_USB_CHIPIDEA_HOST) += host.o
ci_hdrc-$(CONFIG_USB_CHIPIDEA_DEBUG) += debug.o
diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h
index d738603..697e369 100644
--- a/drivers/usb/chipidea/ci.h
+++ b/drivers/usb/chipidea/ci.h
@@ -129,6 +129,7 @@ struct hw_bank {
* @vbus_active: is VBUS active
* @transceiver: pointer to USB PHY, if any
* @hcd: pointer to usb_hcd for ehci host driver
+ * @otg: for otg support
*/
struct ci13xxx {
struct device *dev;
@@ -164,6 +165,7 @@ struct ci13xxx {
bool global_phy;
struct usb_phy *transceiver;
struct usb_hcd *hcd;
+ struct usb_otg otg;
};
static inline struct ci_role_driver *ci_role(struct ci13xxx *ci)
diff --git a/drivers/usb/chipidea/otg.c b/drivers/usb/chipidea/otg.c
new file mode 100644
index 0000000..7dea3b3
--- /dev/null
+++ b/drivers/usb/chipidea/otg.c
@@ -0,0 +1,60 @@
+/*
+ * otg.c - ChipIdea USB IP core OTG driver
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Peter Chen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/chipidea.h>
+
+#include "ci.h"
+#include "udc.h"
+#include "bits.h"
+#include "host.h"
+#include "debug.h"
+
+static int ci_otg_set_peripheral(struct usb_otg *otg,
+ struct usb_gadget *periph)
+{
+ otg->gadget = periph;
+
+ return 0;
+}
+
+static int ci_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
+{
+ otg->host = host;
+
+ return 0;
+}
+
+/**
+ * ci_hdrc_otg_init - initialize device related bits
+ * ci: the controller
+ *
+ * This function create otg struct, if the device can switch between
+ * device and host.
+ */
+int ci_hdrc_otg_init(struct ci13xxx *ci)
+{
+ /* Useless at current */
+ ci->otg.set_peripheral = ci_otg_set_peripheral;
+ ci->otg.set_host = ci_otg_set_host;
+ if (!IS_ERR_OR_NULL(ci->transceiver))
+ ci->transceiver->otg = &ci->otg;
+
+ return 0;
+}
diff --git a/drivers/usb/chipidea/otg.h b/drivers/usb/chipidea/otg.h
new file mode 100644
index 0000000..b4c6b3e
--- /dev/null
+++ b/drivers/usb/chipidea/otg.h
@@ -0,0 +1,6 @@
+#ifndef __DRIVERS_USB_CHIPIDEA_OTG_H
+#define __DRIVERS_USB_CHIPIDEA_OTG_H
+
+int ci_hdrc_otg_init(struct ci13xxx *ci);
+
+#endif /* __DRIVERS_USB_CHIPIDEA_OTG_H */
--
1.7.0.4
^ permalink raw reply related
* [PATCH v6 1/8] Revert "USB: chipidea: add vbus detect for udc"
From: Peter Chen @ 2013-02-04 3:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359947039-23906-1-git-send-email-peter.chen@freescale.com>
vbus register is at otgsc, and vbus detect does not belong
to device function. Revert this patch, and will move
vbus detect function to drivers/usb/chipidea/udc.c
This reverts commit 8c4fc031954b4eb72daf13d3c907a985a3eee208.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
---
drivers/usb/chipidea/ci.h | 1 -
drivers/usb/chipidea/udc.c | 39 +--------------------------------------
2 files changed, 1 insertions(+), 39 deletions(-)
diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h
index e25d126..d738603 100644
--- a/drivers/usb/chipidea/ci.h
+++ b/drivers/usb/chipidea/ci.h
@@ -139,7 +139,6 @@ struct ci13xxx {
enum ci_role role;
bool is_otg;
struct work_struct work;
- struct work_struct vbus_work;
struct workqueue_struct *wq;
struct dma_pool *qh_pool;
diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 2f45bba..d214448 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -305,18 +305,6 @@ static u32 hw_test_and_clear_intr_active(struct ci13xxx *ci)
return reg;
}
-static void hw_enable_vbus_intr(struct ci13xxx *ci)
-{
- hw_write(ci, OP_OTGSC, OTGSC_AVVIS, OTGSC_AVVIS);
- hw_write(ci, OP_OTGSC, OTGSC_AVVIE, OTGSC_AVVIE);
- queue_work(ci->wq, &ci->vbus_work);
-}
-
-static void hw_disable_vbus_intr(struct ci13xxx *ci)
-{
- hw_write(ci, OP_OTGSC, OTGSC_AVVIE, 0);
-}
-
/**
* hw_test_and_clear_setup_guard: test & clear setup guard (execute without
* interruption)
@@ -383,16 +371,6 @@ static int hw_usb_reset(struct ci13xxx *ci)
return 0;
}
-static void vbus_work(struct work_struct *work)
-{
- struct ci13xxx *ci = container_of(work, struct ci13xxx, vbus_work);
-
- if (hw_read(ci, OP_OTGSC, OTGSC_AVV))
- usb_gadget_vbus_connect(&ci->gadget);
- else
- usb_gadget_vbus_disconnect(&ci->gadget);
-}
-
/******************************************************************************
* UTIL block
*****************************************************************************/
@@ -1392,7 +1370,6 @@ static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
if (is_active) {
pm_runtime_get_sync(&_gadget->dev);
hw_device_reset(ci, USBMODE_CM_DC);
- hw_enable_vbus_intr(ci);
hw_device_state(ci, ci->ep0out->qh.dma);
} else {
hw_device_state(ci, 0);
@@ -1567,10 +1544,8 @@ static int ci13xxx_start(struct usb_gadget *gadget,
pm_runtime_get_sync(&ci->gadget.dev);
if (ci->platdata->flags & CI13XXX_PULLUP_ON_VBUS) {
if (ci->vbus_active) {
- if (ci->platdata->flags & CI13XXX_REGS_SHARED) {
+ if (ci->platdata->flags & CI13XXX_REGS_SHARED)
hw_device_reset(ci, USBMODE_CM_DC);
- hw_enable_vbus_intr(ci);
- }
} else {
pm_runtime_put_sync(&ci->gadget.dev);
goto done;
@@ -1676,13 +1651,6 @@ static irqreturn_t udc_irq(struct ci13xxx *ci)
} else {
retval = IRQ_NONE;
}
-
- intr = hw_read(ci, OP_OTGSC, ~0);
- hw_write(ci, OP_OTGSC, ~0, intr);
-
- if (intr & (OTGSC_AVVIE & OTGSC_AVVIS))
- queue_work(ci->wq, &ci->vbus_work);
-
spin_unlock(&ci->lock);
return retval;
@@ -1758,7 +1726,6 @@ static int udc_start(struct ci13xxx *ci)
retval = hw_device_reset(ci, USBMODE_CM_DC);
if (retval)
goto put_transceiver;
- hw_enable_vbus_intr(ci);
}
retval = device_register(&ci->gadget.dev);
@@ -1821,9 +1788,6 @@ static void udc_stop(struct ci13xxx *ci)
if (ci == NULL)
return;
- hw_disable_vbus_intr(ci);
- cancel_work_sync(&ci->vbus_work);
-
usb_del_gadget_udc(&ci->gadget);
destroy_eps(ci);
@@ -1864,7 +1828,6 @@ int ci_hdrc_gadget_init(struct ci13xxx *ci)
rdrv->irq = udc_irq;
rdrv->name = "gadget";
ci->roles[CI_ROLE_GADGET] = rdrv;
- INIT_WORK(&ci->vbus_work, vbus_work);
return 0;
}
--
1.7.0.4
^ permalink raw reply related
* [PATCH v6 0/8] Add tested id switch and vbus connect detect support for Chipidea
From: Peter Chen @ 2013-02-04 3:03 UTC (permalink / raw)
To: linux-arm-kernel
Changes for v5:
- Add Alex comments for init/destroy function [3/8] [4/8]
- Remove memset(&ci->gadget, 0, sizeof(ci->gadget)) at destory function [4/8]
- Add Kishon's comment: Change the format of struct usb_otg otg at drivers/usb/chipidea/ci.h
[1/8]
- Add comments for CI_VBUS_STABLE_TIMEOUT [3/8]
- Change the otg_set_peripheral return value check as the fully
chipidea driver users don't need it. [4/8]
- Fix one bug that the oops when re-plug in usb cable after
rmmod gadget [8/8]
Anyone who has tested this patchset, please give a tested-by, thanks.
This patchset adds tested otg id switch function and
vbus connect/disconnect detection for chipidea driver.
The mainly design of id/vbus handling follows msm otg driver.
I hope the msm usb maintainer can have a look of this patchset,
and give some comments, and move the whole msm usb driver to
chipidea framework if possible in the future.
This patch is fully tested at imx6 sabrelite platform.
My chipidea repo: https://github.com/hzpeterchen/linux-usb.git
which is rebased of 3.8-rc5.
Peter Chen (8):
Revert "USB: chipidea: add vbus detect for udc"
usb: chipidea: add otg file
usb: chipidea: add otg id switch and vbus connect/disconnect detect
usb: chipidea: consolidate kinds of APIs for both roles
usb: chipidea: udc: add pullup/pulldown dp at hw_device_state
usb: chipidea: udc: retire the flag CI13_PULLUP_ON_VBUS
usb: chipidea: imx: add internal vbus regulator control
usb: chipidea: udc: fix the oops when plugs in usb cable after rmmod
gadget
drivers/usb/chipidea/Makefile | 2 +-
drivers/usb/chipidea/bits.h | 10 ++
drivers/usb/chipidea/ci.h | 12 ++-
drivers/usb/chipidea/ci13xxx_imx.c | 81 ++++++++++++----
drivers/usb/chipidea/ci13xxx_msm.c | 1 -
drivers/usb/chipidea/core.c | 186 +++++++++++++++++++++++++++++++-----
drivers/usb/chipidea/host.c | 6 +
drivers/usb/chipidea/host.h | 4 +-
drivers/usb/chipidea/otg.c | 68 +++++++++++++
drivers/usb/chipidea/otg.h | 9 ++
drivers/usb/chipidea/udc.c | 123 ++++++++++--------------
drivers/usb/chipidea/udc.h | 4 +-
include/linux/usb/chipidea.h | 1 -
13 files changed, 385 insertions(+), 122 deletions(-)
create mode 100644 drivers/usb/chipidea/otg.c
create mode 100644 drivers/usb/chipidea/otg.h
^ permalink raw reply
* [PATCH v5] cpufreq: add imx6q-cpufreq driver
From: Shawn Guo @ 2013-02-04 2:51 UTC (permalink / raw)
To: linux-arm-kernel
Add an imx6q-cpufreq driver for Freescale i.MX6Q SoC to handle the
hardware specific frequency and voltage scaling requirements.
The driver supports module build and is instantiated by the platform
device/driver mechanism, so that it will not be instantiated on other
platforms, as IMX is built with multiplatform support.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
---
Changes since v4:
* Use regulator API to handle voltage latency
Rafael,
I generated the patch against your bleeding-edge branch, so it should
be applied cleanly.
Shawn
drivers/cpufreq/Kconfig.arm | 9 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/imx6q-cpufreq.c | 331 +++++++++++++++++++++++++++++++++++++++
3 files changed, 341 insertions(+)
create mode 100644 drivers/cpufreq/imx6q-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index ffe55b8..c65226c 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -77,6 +77,15 @@ config ARM_EXYNOS5250_CPUFREQ
This adds the CPUFreq driver for Samsung EXYNOS5250
SoC.
+config ARM_IMX6Q_CPUFREQ
+ tristate "Freescale i.MX6Q cpufreq support"
+ depends on SOC_IMX6Q
+ depends on REGULATOR_ANATOP
+ help
+ This adds cpufreq driver support for Freescale i.MX6Q SOC.
+
+ If in doubt, say N.
+
config ARM_SPEAR_CPUFREQ
bool "SPEAr CPUFreq support"
depends on PLAT_SPEAR
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index e2a5da7..93610b2 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
+obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
##################################################################################
# PowerPC platform drivers
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
new file mode 100644
index 0000000..f73b245
--- /dev/null
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -0,0 +1,331 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/opp.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+
+#define PU_SOC_VOLTAGE_NORMAL 1250000
+#define PU_SOC_VOLTAGE_HIGH 1275000
+#define FREQ_1P2_GHZ 1200000000
+
+static struct regulator *arm_reg;
+static struct regulator *pu_reg;
+static struct regulator *soc_reg;
+
+static struct clk *arm_clk;
+static struct clk *pll1_sys_clk;
+static struct clk *pll1_sw_clk;
+static struct clk *step_clk;
+static struct clk *pll2_pfd2_396m_clk;
+
+static struct device *cpu_dev;
+static struct cpufreq_frequency_table *freq_table;
+static unsigned int transition_latency;
+
+static int imx6q_verify_speed(struct cpufreq_policy *policy)
+{
+ return cpufreq_frequency_table_verify(policy, freq_table);
+}
+
+static unsigned int imx6q_get_speed(unsigned int cpu)
+{
+ return clk_get_rate(arm_clk) / 1000;
+}
+
+static int imx6q_set_target(struct cpufreq_policy *policy,
+ unsigned int target_freq, unsigned int relation)
+{
+ struct cpufreq_freqs freqs;
+ struct opp *opp;
+ unsigned long freq_hz, volt, volt_old;
+ unsigned int index, cpu;
+ int ret;
+
+ ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
+ relation, &index);
+ if (ret) {
+ dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
+ target_freq, ret);
+ return ret;
+ }
+
+ freqs.new = freq_table[index].frequency;
+ freq_hz = freqs.new * 1000;
+ freqs.old = clk_get_rate(arm_clk) / 1000;
+
+ if (freqs.old == freqs.new)
+ return 0;
+
+ for_each_online_cpu(cpu) {
+ freqs.cpu = cpu;
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+ }
+
+ rcu_read_lock();
+ opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
+ if (IS_ERR(opp)) {
+ rcu_read_unlock();
+ dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
+ return PTR_ERR(opp);
+ }
+
+ volt = opp_get_voltage(opp);
+ rcu_read_unlock();
+ volt_old = regulator_get_voltage(arm_reg);
+
+ dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
+ freqs.old / 1000, volt_old / 1000,
+ freqs.new / 1000, volt / 1000);
+
+ /* scaling up? scale voltage before frequency */
+ if (freqs.new > freqs.old) {
+ ret = regulator_set_voltage_tol(arm_reg, volt, 0);
+ if (ret) {
+ dev_err(cpu_dev,
+ "failed to scale vddarm up: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Need to increase vddpu and vddsoc for safety
+ * if we are about to run at 1.2 GHz.
+ */
+ if (freqs.new == FREQ_1P2_GHZ / 1000) {
+ regulator_set_voltage_tol(pu_reg,
+ PU_SOC_VOLTAGE_HIGH, 0);
+ regulator_set_voltage_tol(soc_reg,
+ PU_SOC_VOLTAGE_HIGH, 0);
+ }
+ }
+
+ /*
+ * The setpoints are selected per PLL/PDF frequencies, so we need to
+ * reprogram PLL for frequency scaling. The procedure of reprogramming
+ * PLL1 is as below.
+ *
+ * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
+ * - Disable pll1_sys_clk and reprogram it
+ * - Enable pll1_sys_clk and reparent pll1_sw_clk back to it
+ * - Disable pll2_pfd2_396m_clk
+ */
+ clk_prepare_enable(pll2_pfd2_396m_clk);
+ clk_set_parent(step_clk, pll2_pfd2_396m_clk);
+ clk_set_parent(pll1_sw_clk, step_clk);
+ clk_prepare_enable(pll1_sys_clk);
+ if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
+ clk_disable_unprepare(pll1_sys_clk);
+ clk_set_rate(pll1_sys_clk, freqs.new * 1000);
+ clk_prepare_enable(pll1_sys_clk);
+ clk_set_parent(pll1_sw_clk, pll1_sys_clk);
+ clk_disable_unprepare(pll2_pfd2_396m_clk);
+ } else {
+ /*
+ * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
+ * to provide the frequency.
+ */
+ clk_disable_unprepare(pll1_sys_clk);
+ }
+
+ /* Ensure the arm clock divider is what we expect */
+ ret = clk_set_rate(arm_clk, freqs.new * 1000);
+ if (ret) {
+ dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
+ regulator_set_voltage_tol(arm_reg, volt_old, 0);
+ return ret;
+ }
+
+ /* scaling down? scale voltage after frequency */
+ if (freqs.new < freqs.old) {
+ ret = regulator_set_voltage_tol(arm_reg, volt, 0);
+ if (ret)
+ dev_warn(cpu_dev,
+ "failed to scale vddarm down: %d\n", ret);
+
+ if (freqs.old == FREQ_1P2_GHZ / 1000) {
+ regulator_set_voltage_tol(pu_reg,
+ PU_SOC_VOLTAGE_NORMAL, 0);
+ regulator_set_voltage_tol(soc_reg,
+ PU_SOC_VOLTAGE_NORMAL, 0);
+ }
+ }
+
+ for_each_online_cpu(cpu) {
+ freqs.cpu = cpu;
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+ }
+
+ return 0;
+}
+
+static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
+{
+ int ret;
+
+ ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+ if (ret) {
+ dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
+ return ret;
+ }
+
+ policy->cpuinfo.transition_latency = transition_latency;
+ policy->cur = clk_get_rate(arm_clk) / 1000;
+ cpumask_setall(policy->cpus);
+ cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
+
+ return 0;
+}
+
+static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
+{
+ cpufreq_frequency_table_put_attr(policy->cpu);
+ return 0;
+}
+
+static struct freq_attr *imx6q_cpufreq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
+static struct cpufreq_driver imx6q_cpufreq_driver = {
+ .verify = imx6q_verify_speed,
+ .target = imx6q_set_target,
+ .get = imx6q_get_speed,
+ .init = imx6q_cpufreq_init,
+ .exit = imx6q_cpufreq_exit,
+ .name = "imx6q-cpufreq",
+ .attr = imx6q_cpufreq_attr,
+};
+
+static int imx6q_cpufreq_probe(struct platform_device *pdev)
+{
+ struct device_node *np;
+ struct opp *opp;
+ unsigned long min_volt, max_volt;
+ int num, ret;
+
+ cpu_dev = &pdev->dev;
+
+ np = of_find_node_by_path("/cpus/cpu at 0");
+ if (!np) {
+ dev_err(cpu_dev, "failed to find cpu0 node\n");
+ return -ENOENT;
+ }
+
+ cpu_dev->of_node = np;
+
+ arm_clk = devm_clk_get(cpu_dev, "arm");
+ pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
+ pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
+ step_clk = devm_clk_get(cpu_dev, "step");
+ pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
+ if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
+ IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
+ dev_err(cpu_dev, "failed to get clocks\n");
+ ret = -ENOENT;
+ goto put_node;
+ }
+
+ arm_reg = devm_regulator_get(cpu_dev, "arm");
+ pu_reg = devm_regulator_get(cpu_dev, "pu");
+ soc_reg = devm_regulator_get(cpu_dev, "soc");
+ if (!arm_reg || !pu_reg || !soc_reg) {
+ dev_err(cpu_dev, "failed to get regulators\n");
+ ret = -ENOENT;
+ goto put_node;
+ }
+
+ /* We expect an OPP table supplied by platform */
+ num = opp_get_opp_count(cpu_dev);
+ if (num < 0) {
+ ret = num;
+ dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
+ goto put_node;
+ }
+
+ ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
+ if (ret) {
+ dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
+ goto put_node;
+ }
+
+ if (of_property_read_u32(np, "clock-latency", &transition_latency))
+ transition_latency = CPUFREQ_ETERNAL;
+
+ /*
+ * OPP is maintained in order of increasing frequency, and
+ * freq_table initialised from OPP is therefore sorted in the
+ * same order.
+ */
+ rcu_read_lock();
+ opp = opp_find_freq_exact(cpu_dev,
+ freq_table[0].frequency * 1000, true);
+ min_volt = opp_get_voltage(opp);
+ opp = opp_find_freq_exact(cpu_dev,
+ freq_table[--num].frequency * 1000, true);
+ max_volt = opp_get_voltage(opp);
+ rcu_read_unlock();
+ ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
+ if (ret > 0)
+ transition_latency += ret * 1000;
+
+ /* Count vddpu and vddsoc latency in for 1.2 GHz support */
+ if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) {
+ ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL,
+ PU_SOC_VOLTAGE_HIGH);
+ if (ret > 0)
+ transition_latency += ret * 1000;
+ ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL,
+ PU_SOC_VOLTAGE_HIGH);
+ if (ret > 0)
+ transition_latency += ret * 1000;
+ }
+
+ ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
+ if (ret) {
+ dev_err(cpu_dev, "failed register driver: %d\n", ret);
+ goto free_freq_table;
+ }
+
+ of_node_put(np);
+ return 0;
+
+free_freq_table:
+ opp_free_cpufreq_table(cpu_dev, &freq_table);
+put_node:
+ of_node_put(np);
+ return ret;
+}
+
+static int imx6q_cpufreq_remove(struct platform_device *pdev)
+{
+ cpufreq_unregister_driver(&imx6q_cpufreq_driver);
+ opp_free_cpufreq_table(cpu_dev, &freq_table);
+
+ return 0;
+}
+
+static struct platform_driver imx6q_cpufreq_platdrv = {
+ .driver = {
+ .name = "imx6q-cpufreq",
+ .owner = THIS_MODULE,
+ },
+ .probe = imx6q_cpufreq_probe,
+ .remove = imx6q_cpufreq_remove,
+};
+module_platform_driver(imx6q_cpufreq_platdrv);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
+MODULE_LICENSE("GPL");
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 1/4] thermal: Add support for the thermal sensor on Kirkwood SoCs
From: Zhang Rui @ 2013-02-04 2:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359815749-27705-2-git-send-email-andrew@lunn.ch>
On Sat, 2013-02-02 at 15:35 +0100, Andrew Lunn wrote:
> From: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
>
> This patch adds support for Kirkwood 88F6282 and 88F6283 thermal sensor.
>
> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> .../bindings/thermal/kirkwood-thermal.txt | 15 +++
> drivers/thermal/Kconfig | 7 +
> drivers/thermal/Makefile | 1 +
> drivers/thermal/kirkwood_thermal.c | 136 ++++++++++++++++++++
> 4 files changed, 159 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/thermal/kirkwood-thermal.txt
> create mode 100644 drivers/thermal/kirkwood_thermal.c
>
> diff --git a/Documentation/devicetree/bindings/thermal/kirkwood-thermal.txt b/Documentation/devicetree/bindings/thermal/kirkwood-thermal.txt
> new file mode 100644
> index 0000000..8c0f5eb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/kirkwood-thermal.txt
> @@ -0,0 +1,15 @@
> +* Kirkwood Thermal
> +
> +This version is for Kirkwood 88F8262 & 88F6283 SoCs. Other kirkwoods
> +don't contain a thermal sensor.
> +
> +Required properties:
> +- compatible : "marvell,kirkwood-thermal"
> +- reg : Address range of the thermal registers
> +
> +Example:
> +
> + thermal at 10078 {
> + compatible = "marvell,kirkwood-thermal";
> + reg = <0x10078 0x4>;
> + };
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index c2c77d1..e691500 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -93,6 +93,13 @@ config RCAR_THERMAL
> Enable this to plug the R-Car thermal sensor driver into the Linux
> thermal framework
>
> +config KIRKWOOD_THERMAL
> + tristate "Temperature sensor on Marvell Kirkwood SoCs"
> + depends on ARCH_KIRKWOOD
> + help
> + Support for the Kirkwood thermal sensor driver into the Linux thermal
> + framework. Only kirkwood 88F6282 and 88F6283 have this sensor.
> +
> config EXYNOS_THERMAL
> tristate "Temperature sensor on Samsung EXYNOS"
> depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5)
> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
> index d8da683..99026b2 100644
> --- a/drivers/thermal/Makefile
> +++ b/drivers/thermal/Makefile
> @@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_THERMAL) += cpu_cooling.o
> # platform thermal drivers
> obj-$(CONFIG_SPEAR_THERMAL) += spear_thermal.o
> obj-$(CONFIG_RCAR_THERMAL) += rcar_thermal.o
> +obj-$(CONFIG_KIRKWOOD_THERMAL) += kirkwood_thermal.o
> obj-$(CONFIG_EXYNOS_THERMAL) += exynos_thermal.o
> obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
> obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
> diff --git a/drivers/thermal/kirkwood_thermal.c b/drivers/thermal/kirkwood_thermal.c
> new file mode 100644
> index 0000000..000cfc9
> --- /dev/null
> +++ b/drivers/thermal/kirkwood_thermal.c
> @@ -0,0 +1,136 @@
> +/*
> + * Kirkwood thermal sensor driver
> + *
> + * Copyright (C) 2012 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/thermal.h>
> +
> +#define KIRKWOOD_THERMAL_VALID_OFFSET 9
> +#define KIRKWOOD_THERMAL_VALID_MASK 0x1
> +#define KIRKWOOD_THERMAL_TEMP_OFFSET 10
> +#define KIRKWOOD_THERMAL_TEMP_MASK 0x1FF
> +
> +/* Kirkwood Thermal Sensor Dev Structure */
> +struct kirkwood_thermal_priv {
> + void __iomem *sensor;
> +};
> +
> +static int kirkwood_get_temp(struct thermal_zone_device *thermal,
> + unsigned long *temp)
> +{
> + unsigned long reg;
> + struct kirkwood_thermal_priv *priv = thermal->devdata;
> +
> + reg = readl_relaxed(priv->sensor);
> +
> + /* Valid check */
> + if (!(reg >> KIRKWOOD_THERMAL_VALID_OFFSET) &
> + KIRKWOOD_THERMAL_VALID_MASK) {
> + dev_err(&thermal->device,
> + "Temperature sensor reading not valid\n");
> + return -EIO;
> + }
> +
> + /*
> + * Calculate temperature. See Section 8.10.1 of the 88AP510,
> + * datasheet, which has the same sensor.
> + * Documentation/arm/Marvell/README
> + */
> + reg = (reg >> KIRKWOOD_THERMAL_TEMP_OFFSET) &
> + KIRKWOOD_THERMAL_TEMP_MASK;
> + *temp = ((2281638UL - (7298*reg)) / 10);
> +
> + return 0;
> +}
> +
> +static struct thermal_zone_device_ops ops = {
> + .get_temp = kirkwood_get_temp,
> +};
> +
> +static const struct of_device_id kirkwood_thermal_id_table[] = {
> + { .compatible = "marvell,kirkwood-thermal" },
> + {}
> +};
> +
you do not need #ifdef CONFIG_OF here?
thanks,
rui
> +static int kirkwood_thermal_probe(struct platform_device *pdev)
> +{
> + struct thermal_zone_device *thermal = NULL;
> + struct kirkwood_thermal_priv *priv;
> + struct resource *res;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(&pdev->dev, "Failed to get platform resource\n");
> + return -ENODEV;
> + }
> +
> + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv) {
> + dev_err(&pdev->dev, "kzalloc fail\n");
> + return -ENOMEM;
> + }
> +
> + priv->sensor = devm_request_and_ioremap(&pdev->dev, res);
> + if (!priv->sensor) {
> + dev_err(&pdev->dev, "Failed to request_ioremap memory\n");
> + return -EADDRNOTAVAIL;
> + }
> +
> + thermal = thermal_zone_device_register("kirkwood_thermal", 0, 0,
> + priv, &ops, NULL, 0, 0);
> + if (IS_ERR(thermal)) {
> + dev_err(&pdev->dev,
> + "Failed to register thermal zone device\n");
> + return PTR_ERR(thermal);
> + }
> +
> + platform_set_drvdata(pdev, thermal);
> +
> + return 0;
> +}
> +
> +static int kirkwood_thermal_exit(struct platform_device *pdev)
> +{
> + struct thermal_zone_device *kirkwood_thermal =
> + platform_get_drvdata(pdev);
> +
> + thermal_zone_device_unregister(kirkwood_thermal);
> + platform_set_drvdata(pdev, NULL);
> +
> + return 0;
> +}
> +
> +MODULE_DEVICE_TABLE(of, kirkwood_thermal_id_table);
> +
> +static struct platform_driver kirkwood_thermal_driver = {
> + .probe = kirkwood_thermal_probe,
> + .remove = kirkwood_thermal_exit,
> + .driver = {
> + .name = "kirkwood_thermal",
> + .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(kirkwood_thermal_id_table),
> + },
> +};
> +
> +module_platform_driver(kirkwood_thermal_driver);
> +
> +MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu@nigauri.org>");
> +MODULE_DESCRIPTION("kirkwood thermal driver");
> +MODULE_LICENSE("GPL");
^ permalink raw reply
* [PATCH 1/1] net: fec: fix miss init spinlock
From: Frank Li @ 2013-02-04 2:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130202.230851.809969826800130930.davem@davemloft.net>
2013/2/3 David Miller <davem@davemloft.net>:
> From: Frank Li <Frank.Li@freescale.com>
> Date: Fri, 1 Feb 2013 16:56:26 +0800
>
>> @@ -1607,6 +1607,7 @@ static int fec_enet_init(struct net_device *ndev)
>> }
>>
>> spin_lock_init(&fep->hw_lock);
>> + spin_lock_init(&fep->tmreg_lock);
>
> This breaks the build, tmreg_lock is only present in certain
> configurations.
No, FEC have changed to check dramatically instead of static config.
You can look fec.h. tmreg_lock is always defined.
struct napi_struct napi;
struct ptp_clock *ptp_clock;
struct ptp_clock_info ptp_caps;
unsigned long last_overflow_check;
spinlock_t tmreg_lock;
struct cyclecounter cc;
struct timecounter tc;
int rx_hwtstamp_filter;
u32 base_incval;
u32 cycle_speed;
int hwts_rx_en;
int hwts_tx_en;
struct timer_list time_keep;
best regards
Frank Li
^ permalink raw reply
* [PATCH] regulator: anatop: improve precision of delay time
From: Shawn Guo @ 2013-02-04 2:21 UTC (permalink / raw)
To: linux-arm-kernel
For cpufreq example, it takes 13 steps (25 mV for one step) to increase
vddcore from 0.95 V to 1.275 V, and the time of 64 clock cycles at
24 MHz for one step is ~2.67 uS, so the total delay time would be
~34.71 uS. But the current calculation in the driver gives 39 uS.
Change the formula to have the addition of 1 be the last step, so that
we can get a more precise delay time. For example above, the new
formula will give 35 uS.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/regulator/anatop-regulator.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
index 0df9c6a..0d4a8cc 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -80,8 +80,8 @@ static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
val = (val >> anatop_reg->delay_bit_shift) &
((1 << anatop_reg->delay_bit_width) - 1);
- ret = (new_sel - old_sel) * ((LDO_RAMP_UP_UNIT_IN_CYCLES <<
- val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1);
+ ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
+ val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
}
return ret;
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH 0/4] Add support for LZ4-compressed kernels
From: Markus F.X.J. Oberhumer @ 2013-02-04 2:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130130102353.GA8925@sig21.net>
On 2013-01-30 11:23, Johannes Stezenbach wrote:
> On Mon, Jan 28, 2013 at 11:29:14PM -0500, Nicolas Pitre wrote:
>> On Mon, 28 Jan 2013, Andrew Morton wrote:
>>
>>> On Sat, 26 Jan 2013 14:50:43 +0900
>>> Kyungsik Lee <kyungsik.lee@lge.com> wrote:
>>>
>>>> This patchset is for supporting LZ4 compressed kernel and initial ramdisk on
>>>> the x86 and ARM architectures.
>>>>
>>>> According to http://code.google.com/p/lz4/, LZ4 is a very fast lossless
>>>> compression algorithm and also features an extremely fast decoder.
>>>>
>>>> Kernel Decompression APIs are based on implementation by Yann Collet
>>>> (http://code.google.com/p/lz4/source/checkout).
>>>> De/compression Tools are also provided from the site above.
>>>>
>>>> The initial test result on ARM(v7) based board shows that the size of kernel
>>>> with LZ4 compressed is 8% bigger than LZO compressed but the decompressing
>>>> speed is faster(especially under the enabled unaligned memory access).
>>>>
>>>> Test: 3.4 based kernel built with many modules
>>>> Uncompressed kernel size: 13MB
>>>> lzo: 6.3MB, 301ms
>>>> lz4: 6.8MB, 251ms(167ms, with enabled unaligned memory access)
>>>
>>> What's this "with enabled unaligned memory access" thing? You mean "if
>>> the arch supports CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS"? If so,
>>> that's only x86, which isn't really in the target market for this
>>> patch, yes?
>>
>> I'm guessing this is referring to commit 5010192d5a.
>>
>>> It's a lot of code for a 50ms boot-time improvement. Does anyone have
>>> any opinions on whether or not the benefits are worth the cost?
>>
>> Well, we used to have only one compressed format. Now we have nearly
>> half a dozen, with the same worthiness issue between themselves.
>> Either we keep it very simple, or we make it very flexible. The former
>> would argue in favor of removing some of the existing formats, the later
>> would let this new format in.
>
> This reminded me to check the status of the lzo update and it
> seems it got lost?
> http://lkml.org/lkml/2012/10/3/144
The proposed LZO update currently lives in the linux-next tree.
I had tried several times during the last 12 months to provide an update
of the kernel LZO version, but community interest seemed low and I
basically got no feedback about performance improvements - which made
we wonder if people actually care.
At least akpm did approve the LZO update for inclusion into 3.7, but the code
still has not been merged into the main tree.
> On 2012-10-09 21:26, Andrew Morton wrote:
> [...]
> The changes look OK to me. Please ask Stephen to include the tree in
> linux-next, for a 3.7 merge.
Well, this probably means I have done a rather poor marketing. Anyway, as
people seem to love *synthetic* benchmarks I'm finally posting some timings
(including a brand new ARM unaligned version - this is just a quick hack which
probably still can get optimized further).
Hopefully publishing these numbers will help arousing more interest. :-)
Cheers,
Markus
x86_64 (Sandy Bridge), gcc-4.6 -O3, Silesia test corpus, 256 kB block-size:
compression speed decompression speed
LZO-2005 : 150 MB/sec 468 MB/sec
LZO-2012 : 434 MB/sec 1210 MB/sec
i386 (Sandy Bridge), gcc-4.6 -O3, Silesia test corpus, 256 kB block-size:
compression speed decompression speed
LZO-2005 : 143 MB/sec 409 MB/sec
LZO-2012 : 372 MB/sec 1121 MB/sec
armv7 (Cortex-A9), Linaro gcc-4.6 -O3, Silesia test corpus, 256 kB block-size:
compression speed decompression speed
LZO-2005 : 27 MB/sec 84 MB/sec
LZO-2012 : 44 MB/sec 117 MB/sec
LZO-2013-UA : 47 MB/sec 167 MB/sec
Legend:
LZO-2005 : LZO version in current 3.8 rc6 kernel (which is based on
the LZO 2.02 release from 2005)
LZO-2012 : updated LZO version available in linux-next
LZO-2013-UA : updated LZO version available in linux-next plus
ARM Unaligned Access patch (attached below)
> (Cc: added, I hope Markus still cares and someone could
> eventually take his patch once he resends it.)
>
> Johannes
>
--
Markus Oberhumer, <markus@oberhumer.com>, http://www.oberhumer.com/
-------------- next part --------------
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^ permalink raw reply
* [PATCH v2] rtc: rtc-mv: Add support for clk to avoid lockups
From: Jason Cooper @ 2013-02-04 1:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359891126-21909-1-git-send-email-andrew@lunn.ch>
On Sun, Feb 03, 2013 at 12:32:06PM +0100, Andrew Lunn wrote:
> The Marvell RTC on Kirkwood makes use of the runit clock. Ensure the
> driver clk_prepare_enable() this clock, otherwise there is a danger
> the SoC will lockup when accessing RTC registers with the clock
> disabled.
>
> Reported-by: Simon Baatz gmbnomis at gmail.com
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
>
> Since v1:
> Enable clock before accessing RTC registers.
>
> arch/arm/boot/dts/kirkwood.dtsi | 1 +
> drivers/rtc/rtc-mv.c | 28 ++++++++++++++++++++++++----
> 2 files changed, 25 insertions(+), 4 deletions(-)
Applied to mvebu/fixes with Simon's Tested-by: and added '<' '>' to the
Reported-by:.
thx,
Jason.
^ permalink raw reply
* [PATCH v2] gpio: mvebu: Add clk support to prevent lockup
From: Jason Cooper @ 2013-02-04 1:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359887666-17552-1-git-send-email-andrew@lunn.ch>
On Sun, Feb 03, 2013 at 11:34:26AM +0100, Andrew Lunn wrote:
> The kirkwood SoC GPIO cores use the runit clock. Add code to
> clk_prepare_enable() runit, otherwise there is a danger of locking up
> the SoC by accessing the GPIO registers when runit clock is not
> ticking.
>
> Reported-by: Simon Baatz <gmbnomis@gmail.com>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> Since v1:
> ChangeLog: tclk->runit clock
>
> arch/arm/boot/dts/kirkwood.dtsi | 2 ++
> drivers/gpio/gpio-mvebu.c | 7 +++++++
> 2 files changed, 9 insertions(+)
Linus,
I merge-tested this against your gpio/fixes branch since you had a patch
to the same file:
11c0cee gpio: mvebu: Don't free chip label memory
There were no conflicts. If you don't mind, I'd like to take this
through mvebu/fixes -> arm-soc since this is one of four patches to fix
one reported issue. I'd like to keep them in the same branch.
If this causes a headache for you, please let me know and you can take
it.
Otherwise, applied to mvebu/fixes with Simon's Tested-by:
thx,
Jason.
^ permalink raw reply
* [RFC PATCH 0/4] Add support for LZ4-compressed kernels
From: Markus F.X.J. Oberhumer @ 2013-02-04 1:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <510B6829.7050908@lge.com>
On 2013-02-01 08:00, kyungsik.lee wrote:
> On 2013-01-30 ?? 6:09, Rajesh Pawar wrote:
>>> Andrew Morton <akpm@linux-foundation.org> wrote:
>>>
>>> On Sat, 26 Jan 2013 14:50:43 +0900
>>> Kyungsik Lee <kyungsik.lee@lge.com> wrote:
>>>> [...]
>>>>
>>> What's this "with enabled unaligned memory access" thing? You mean "if
>>> the arch supports CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS"? If so,
>>> that's only x86, which isn't really in the target market for this
>>> patch, yes?
>>> It's a lot of code for a 50ms boot-time improvement. Does anyone have
>>> any opinions on whether or not the benefits are worth the cost?
>> BTW, what happened to the proposed LZO update - woudn't it better to merge
>> this first?
>>
>> Also, under the hood LZ4 seems to be quite similar to LZO, so probably
>> LZO speed would also greatly benefit from unaligned access and some other
>> ARM optimisations
>>
> I didn't test with the proposed LZO update you mentioned. Sorry, which one do
> you mean?
> I did some tests with the latest LZO in the mainline.
In fact you can easily improve LZO decompression speed on armv7 by almost 50%
by adding just a few lines for enabling unaligend access:
armv7 (Cortex-A9), Linaro gcc-4.6 -O3, Silesia test corpus, 256 kB block-size:
compression speed decompression speed
LZO-2005 : 27 MB/sec 84 MB/sec
LZO-2012 : 44 MB/sec 117 MB/sec
LZO-2013-UA : 47 MB/sec 167 MB/sec
Please see my other mail to LKML for details.
Cheers,
Markus
> As a result, LZO is not faster in an unaligned access enabled on ARM. Actually
> Slower.
>
> Decompression time: 336ms(383ms, with unaligned access enabled)
>
> You may refer to https://lkml.org/lkml/2012/10/7/85 to know more about it.
>
> Thanks,
> Kyungsik
>
>
> Thanks,
> Kyungsik
>
--
Markus Oberhumer, <markus@oberhumer.com>, http://www.oberhumer.com/
^ permalink raw reply
* [PATCH v2 2/2] ARM: kirkwood: fix to retain gbe MAC addresses for DT kernels
From: Jason Cooper @ 2013-02-04 1:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359577799-23351-1-git-send-email-sebastian.hesselbarth@gmail.com>
On Wed, Jan 30, 2013 at 09:29:58PM +0100, Sebastian Hesselbarth wrote:
> The ethernet controller used on kirkwood looses its MAC address
> register contents when the corresponding clock is gated. As soon as
> mv643xx_eth is built as module, the clock gets gated and when loading
> the module, the MAC address is gone.
>
> Proper DT support for the mv643xx_eth driver is expected soon, so we add
> a workaround to always enable ge0/ge1 clocks on kirkwood. This workaround
> is also already used on non-DT kirkwood kernels.
>
> Reported-by: Simon Baatz <gmbnomis@gmail.com>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Changelog:
> [v2]
> - add note in patch description that MAC address is lost only when using
> modular driver
> - add note in patch description that the workaround will be removed soon
>
> Cc: Simon Baatz <gmbnomis@gmail.com>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
> arch/arm/mach-kirkwood/board-dt.c | 24 +++++++++++++++---------
> 1 file changed, 15 insertions(+), 9 deletions(-)
Applied to mvebu/fixes with Simon's Tested-by:
thx,
Jason.
^ permalink raw reply
* [PATCH] ARM: kirkwood: of_serial: fix clock gating by removing clock-frequency
From: Jason Cooper @ 2013-02-04 1:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359493774-27627-1-git-send-email-jason@lakedaemon.net>
On Tue, Jan 29, 2013 at 09:09:34PM +0000, Jason Cooper wrote:
> When DT support for kirkwood was first introduced, there was no clock
> infrastructure. As a result, we had to manually pass the
> clock-frequency to the driver from the device node.
>
> Unfortunately, on kirkwood, with minimal config or all module configs,
> clock-frequency breaks booting because of_serial doesn't consume the
> gate_clk when clock-frequency is defined.
>
> The end result on kirkwood is that runit gets gated, and then the boot
> fails when the kernel tries to write to the serial port.
>
> Fix the issue by removing the clock-frequency parameter from all
> kirkwood dts files.
>
> Booted on dreamplug without earlyprintk and successfully logged in via
> ttyS0.
>
> Reported-by: Simon Baatz <gmbnomis@gmail.com>
> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
> ---
> arch/arm/boot/dts/kirkwood-dns320.dts | 2 --
> arch/arm/boot/dts/kirkwood-dns325.dts | 1 -
> arch/arm/boot/dts/kirkwood-dockstar.dts | 1 -
> arch/arm/boot/dts/kirkwood-dreamplug.dts | 1 -
> arch/arm/boot/dts/kirkwood-goflexnet.dts | 1 -
> arch/arm/boot/dts/kirkwood-ib62x0.dts | 1 -
> arch/arm/boot/dts/kirkwood-iconnect.dts | 1 -
> arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 1 -
> arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 1 -
> arch/arm/boot/dts/kirkwood-lschlv2.dts | 1 -
> arch/arm/boot/dts/kirkwood-lsxhl.dts | 1 -
> arch/arm/boot/dts/kirkwood-mplcec4.dts | 1 -
> arch/arm/boot/dts/kirkwood-nsa310.dts | 1 -
> arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 2 --
> arch/arm/boot/dts/kirkwood-topkick.dts | 1 -
> arch/arm/boot/dts/kirkwood.dtsi | 2 --
> 16 files changed, 19 deletions(-)
Applied to mvebu/fixes with Simon's Tested-by:
thx,
Jason.
^ permalink raw reply
* [PATCH V1 RESEND] ARM: gic: add irq_set_affinity to gic_arch_extn
From: Chao Xie @ 2013-02-04 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359447959-20554-1-git-send-email-chao.xie@marvell.com>
hi, Russell
How do you think about this patch?
On Tue, Jan 29, 2013 at 4:25 PM, Chao Xie <chao.xie@marvell.com> wrote:
> gic_arch_extn is used for ARCH specific interrupt controller.
> It has added the callbacks for irq_mask/irq_unamsk and so, but
> irq_set_affinity is not used.
> For SMP architecure, when both cores are powered off, the GIC may
> be powered off too. An external interrupt controller can be used
> as a logic to detect the interrupt and acknowledge power managment
> unitto wake up core.
> Because the irqs may be bound to different cors, when set irq
> affinity, the external interrupt controller should be set too. Then
> it can acknowledge the power managment unit to wake up correct core.
>
> Signed-off-by: Chao Xie <chao.xie@marvell.com>
> ---
> arch/arm/common/gic.c | 27 ++++++++++++++++++---------
> 1 files changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
> index 36ae03a..49920a0 100644
> --- a/arch/arm/common/gic.c
> +++ b/arch/arm/common/gic.c
> @@ -82,12 +82,15 @@ static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
> * Default make them NULL.
> */
> struct irq_chip gic_arch_extn = {
> - .irq_eoi = NULL,
> - .irq_mask = NULL,
> - .irq_unmask = NULL,
> - .irq_retrigger = NULL,
> - .irq_set_type = NULL,
> - .irq_set_wake = NULL,
> + .irq_eoi = NULL,
> + .irq_mask = NULL,
> + .irq_unmask = NULL,
> + .irq_retrigger = NULL,
> + .irq_set_type = NULL,
> +#ifdef CONFIG_SMP
> + .irq_set_affinity = NULL,
> +#endif
> + .irq_set_wake = NULL,
> };
>
> #ifndef MAX_GIC_NR
> @@ -245,6 +248,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
> unsigned int shift = (gic_irq(d) % 4) * 8;
> unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
> u32 val, mask, bit;
> + int ret = IRQ_SET_MASK_OK;
>
> if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
> return -EINVAL;
> @@ -253,11 +257,16 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
> bit = gic_cpu_map[cpu] << shift;
>
> raw_spin_lock(&irq_controller_lock);
> - val = readl_relaxed(reg) & ~mask;
> - writel_relaxed(val | bit, reg);
> + if (gic_arch_extn.irq_set_affinity)
> + ret = gic_arch_extn.irq_set_affinity(d, mask_val, force);
> +
> + if (ret == IRQ_SET_MASK_OK) {
> + val = readl_relaxed(reg) & ~mask;
> + writel_relaxed(val | bit, reg);
> + }
> raw_spin_unlock(&irq_controller_lock);
>
> - return IRQ_SET_MASK_OK;
> + return ret;
> }
> #endif
>
> --
> 1.7.4.1
>
^ permalink raw reply
* [PATCH] ARM:omap2: using strlcpy instead of strncpy
From: Chen Gang @ 2013-02-04 1:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130202180723.GB577@atomide.com>
? 2013?02?03? 02:07, Tony Lindgren ??:
>> is it suitable to sync the MAINTAINER file for it ?
>> > if suitable, can you help to change it ?
> Yes I suggest we add Peter as the maintainer for all twl
> related things.
>
> Regards,
>
> Tony
>
>
ok, thanks.
by the way:
if necessary (not find another suitable members to sync it), I should
sync it (since I found it)
--
Chen Gang
Asianux Corporation
^ permalink raw reply
* [PATCH] mfd: vexpress: Add pseudo-GPIO based LEDs
From: Samuel Ortiz @ 2013-02-03 22:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359541996-18127-1-git-send-email-pawel.moll@arm.com>
Hi Pawel,
On Wed, Jan 30, 2013 at 10:33:16AM +0000, Pawel Moll wrote:
> The LEDs on the Versatile Express motherboard are controlled
> through simple memory-mapped register. This patch extends
> the pseudo-GPIO controller definition for these lines and
> creates generic "leds-gpio" device using them
>
> Signed-off-by: Pawel Moll <pawel.moll@arm.com>
> ---
>
> Hello Samuel,
>
> Would you be so kind to take this patch in for 3.9? Or would
> you prefer to get it in through arm-soc tree?
>
> Thanks!
>
> Pawel
>
> drivers/mfd/vexpress-sysreg.c | 73 +++++++++++++++++++++++++++++++----------
> include/linux/vexpress.h | 8 +++++
> 2 files changed, 63 insertions(+), 18 deletions(-)
Applied to my for-next branch, thanks.
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH] mfd: remove redundant devm_* for 88pm80x PMIC
From: Samuel Ortiz @ 2013-02-03 22:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358822625-5948-1-git-send-email-yizhang@marvell.com>
Hi Yi,
On Tue, Jan 22, 2013 at 10:43:45AM +0800, Yi Zhang wrote:
> devm_* functions are device managed and make error handling
> and code simpler; it also fix error exit paths
>
> Signed-off-by: Yi Zhang <yizhang@marvell.com>
> ---
> drivers/mfd/88pm800.c | 10 +++-------
> drivers/mfd/88pm805.c | 4 ++--
> drivers/mfd/88pm80x.c | 22 ++++------------------
> include/linux/mfd/88pm80x.h | 2 +-
> 4 files changed, 10 insertions(+), 28 deletions(-)
Applied, thanks for the fix.
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH V2 4/6] mfd: tps6507x: add device-tree support.
From: Samuel Ortiz @ 2013-02-03 22:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359445134-13323-5-git-send-email-manishv.b@ti.com>
Hi Manish,
On Tue, Jan 29, 2013 at 01:08:52PM +0530, Vishwanathrao Badarkhe, Manish wrote:
> Add device tree based initialization support for TI's
> tps6507x mfd device.
>
> Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
> ---
> Changes since V1:
> - updated subject line for commit.
>
> :100644 100644 409afa2... 5ad4b77... M drivers/mfd/tps6507x.c
> drivers/mfd/tps6507x.c | 9 +++++++++
> 1 files changed, 9 insertions(+), 0 deletions(-)
Applied, thanks.
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH v2] rtc: rtc-mv: Add support for clk to avoid lockups
From: Jason Cooper @ 2013-02-03 22:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130203194407.GA16366@schnuecks.de>
On Sun, Feb 03, 2013 at 08:44:07PM +0100, Simon Baatz wrote:
> Hi Andrew,
>
> On Sun, Feb 03, 2013 at 12:32:06PM +0100, Andrew Lunn wrote:
> > The Marvell RTC on Kirkwood makes use of the runit clock. Ensure the
> > driver clk_prepare_enable() this clock, otherwise there is a danger
> > the SoC will lockup when accessing RTC registers with the clock
> > disabled.
> >
> > Reported-by: Simon Baatz gmbnomis at gmail.com
> > Signed-off-by: Andrew Lunn <andrew@lunn.ch>
>
> And:
>
> Tested-by: Simon Baatz <gmbnomis@gmail.com>
>
> Btw, <...> is missing from the email address in the Reported-by line.
I'll clean that up. no need for a new version.
> Thanks for providing this so quickly. Now, it looks like this
> (without applying the GPIO fix, yet, because it would already enable
> the runit clock):
>
> # cat /sys/kernel/debug/clk/tclk/runit/clk_enable_count
> 0
> # insmod ./rtc-mv.ko
> # cat /sys/kernel/debug/clk/tclk/runit/clk_enable_count
> 1
> # hwclock
> Sun Feb 3 19:34:53 2013 -1.003522 seconds
> # rmmod rtc-mv
> # cat /sys/kernel/debug/clk/tclk/runit/clk_enable_count
> 0
Great! Thanks for turning around those tests so quickly.
thx,
Jason.
^ permalink raw reply
* [PATCH v2] gpio: mvebu: Add clk support to prevent lockup
From: Simon Baatz @ 2013-02-03 19:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359887666-17552-1-git-send-email-andrew@lunn.ch>
On Sun, Feb 03, 2013 at 11:34:26AM +0100, Andrew Lunn wrote:
> The kirkwood SoC GPIO cores use the runit clock. Add code to
> clk_prepare_enable() runit, otherwise there is a danger of locking up
> the SoC by accessing the GPIO registers when runit clock is not
> ticking.
>
> Reported-by: Simon Baatz <gmbnomis@gmail.com>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Simon Baatz <gmbnomis@gmail.com>
After boot (GPIO is the only driver enabling runit at this point in
time):
# cat /sys/kernel/debug/clk/tclk/runit/clk_enable_count
2
- Simon
^ permalink raw reply
* [PATCH v2] rtc: rtc-mv: Add support for clk to avoid lockups
From: Simon Baatz @ 2013-02-03 19:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359891126-21909-1-git-send-email-andrew@lunn.ch>
Hi Andrew,
On Sun, Feb 03, 2013 at 12:32:06PM +0100, Andrew Lunn wrote:
> The Marvell RTC on Kirkwood makes use of the runit clock. Ensure the
> driver clk_prepare_enable() this clock, otherwise there is a danger
> the SoC will lockup when accessing RTC registers with the clock
> disabled.
>
> Reported-by: Simon Baatz gmbnomis at gmail.com
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
And:
Tested-by: Simon Baatz <gmbnomis@gmail.com>
Btw, <...> is missing from the email address in the Reported-by line.
Thanks for providing this so quickly. Now, it looks like this
(without applying the GPIO fix, yet, because it would already enable
the runit clock):
# cat /sys/kernel/debug/clk/tclk/runit/clk_enable_count
0
# insmod ./rtc-mv.ko
# cat /sys/kernel/debug/clk/tclk/runit/clk_enable_count
1
# hwclock
Sun Feb 3 19:34:53 2013 -1.003522 seconds
# rmmod rtc-mv
# cat /sys/kernel/debug/clk/tclk/runit/clk_enable_count
0
- Simon
^ permalink raw reply
* [PATCHv2 for soc 4/4] arm: socfpga: Add SMP support for actual socfpga harware
From: Pavel Machek @ 2013-02-03 18:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <71B37E0559AC6849A68C5BA94C509FB45A645BA4EA@SJ-ITMSG02.altera.priv.altera.com>
Hi!
> > > Point taken...thanks Russell.
> >
> > Well, I don't think we normally check dtbs for validity with
> > user-helpful error messages, but it is relatively easy in this case.
> >
> > ---cut here---
> >
> > Continue booting with second core disabled if cpu1-start-addr is not
> > present in .dtb.
> >
> > Signed-off-by: Pavel Machek <pavel@denx.de>
> >
> > diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-
> > socfpga/platsmp.c
> > index 81e0da0..90facdd 100644
> > --- a/arch/arm/mach-socfpga/platsmp.c
> > +++ b/arch/arm/mach-socfpga/platsmp.c
> > @@ -82,6 +82,9 @@ static void __init socfpga_smp_init_cpus(void)
> > ncores = 1;
> > }
> > #endif
> > + if (!cpu1start_addr)
> > + ncores = 1;
> > +
>
> This will not work because of commit 5587164eea4aad88fcb79d9b21dc8f14fea598cd
> I sent out a V3 series of this patch, CPU1 will simply fail to come online if
> cpu1-start-addr is not defined.
Are you sure? As far as I can see you still need such a line in v3 of
the patch:
@@ -72,6 +73,11 @@ void __init socfpga_sysmgr_init(void)
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
+
+ if (of_property_read_u32(np, "cpu1-start-addr",
+ (u32 *) &cpu1start_addr))
+ pr_err("SMP: Need cpu1-start-addr in device tree.\n");
+
sys_manager_base_addr = of_iomap(np, 0);
np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
...so cpu1-start-addr is not there, cpu1start_addr is NULL but you
continue booting.
ENTRY(secondary_trampoline)
- movw r0, #:lower16:CPU1_START_ADDR
- movt r0, #:upper16:CPU1_START_ADDR
+ movw r2, #:lower16:cpu1start_addr
+ movt r2, #:upper16:cpu1start_addr
+
+ /* The socfpga VT cannot handle a 0xC0000000 page offset when
loading
+ the cpu1start_addr, we bit clear it. Tested on HW and
VT. */
+ bic r2, r2, #0x40000000
+ ldr r0, [r2]
ldr r1, [r0]
bx r1
...and you'll dereference the NULL pointer here, no?
Sorry for the noise, this really is not all that important...
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply
* [PATCH v3 13/15] ARM: CCI: ensure powerdown-time data is flushed from cache
From: Nicolas Pitre @ 2013-02-03 18:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <510E36CD.9000005@ti.com>
On Sun, 3 Feb 2013, Santosh Shilimkar wrote:
> On Sunday 03 February 2013 03:53 AM, Nicolas Pitre wrote:
> > On Fri, 1 Feb 2013, Santosh Shilimkar wrote:
> >
> > > On Tuesday 29 January 2013 01:21 PM, Nicolas Pitre wrote:
> > > > From: Dave Martin <dave.martin@linaro.org>
> > > >
> > > > Non-local variables used by the CCI management function called after
> > > > disabling the cache must be flushed out to main memory in advance,
> > > > otherwise incoherency of those values may occur if they are sitting
> > > > in the cache of some other CPU when cci_disable() executes.
> > > >
> > > Any CPU calling cci_disable() would have already cleaned its local
> > > cache and the snoop unit should take care of syncing the shared data
> > > before hand from other CPU local caches for shared accesses.
> > > May be I am unable to visualize the issue here or missing some key
> > > point.
> >
> > Let's suppose CPU0 initializes the CCI. Without this patch, the CCI
> > base address might be sitting in CPU0's cache.
> >
> > The last CPU in a cluster to shut itself down is responsible for calling
> > cci_disable(). And being the last, it is also responsible for flushing
> > out its L1 and L2 caches before doing that. If CPU0 went down before
> > that, it did flush its L1 already. So the base address will be flushed
> > to RAM in that case.
> >
> Yes. This is valid case. Thanks for description.
>
> > But if it is a CPU in _another_ cluster which is shutting down and
> > becoming the last man _there_. It will flush its L1 and L2 cache
> > before calling cci_disable(). And
> > because the cache is disabled at that point, that CPU won't
> > send any snoop request across to the other cluster where CPU0 holds the
> > base address in its L1 or even L2 cache.
> >
> > This is why we must push out that value out to RAM before cci_disable()
> > is used.
> >
> > > > This patch adds the appropriate flushing to the CCI driver to ensure
> > > > that the relevant data is available in RAM ahead of time.
> > > >
> > > > Because this creates a dependency on arch-specific cacheflushing
> > > > functions, this patch also makes ARM_CCI depend on ARM.
> > > >
> > > You should do that otherwise to avoid other arch building this
> > > driver for random builds and breaking their builds.
> >
> > Before this patch the driver was buildable on any architecture. That's
> > why this dependency is added only in this patch.
> >
> I was just trying to counter the reasoning in the changelog which says
> dependency is added because of arch specific cache flushing function.
> Meaning even without that ARM dependency should be in place to avoid
> driver getting build for other archs.
Well, some upstream maintainers' opinion is that you should not put
artificial dependencies on a specific architecture if a driver is
buildable on any architecture, even if the built driver is of no use to
those other architectures.
Nicolas
^ permalink raw reply
* [PATCH 0/4] add ux500_wdt support
From: Samuel Ortiz @ 2013-02-03 17:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358509214-22407-1-git-send-email-fabio.baltieri@linaro.org>
Hi Fabio,
On Fri, Jan 18, 2013 at 12:40:10PM +0100, Fabio Baltieri wrote:
> Hi all,
>
> this set adds support for the ux500_wdt timer, implemented in the PRCMU
> unit of ST-Ericsson ux500 architecture.
>
> The first two patches add the necessary definitions and function export
> to the PRCMU driver currently in mainline, while the third an fourth
> patches add the actual watchdog driver and mfd_cell definition to make
> it probe when PRCMU is compiled in.
>
> As the patches touches files in both mfd and watchdog subsystems, what do
> you think is the best way to handle this set?
>
> Thanks,
> Fabio
>
>
> Fabio Baltieri (4):
> mfd: dbx500-prcmu: add watchdog ID definitions
> mfd: dbx500-prcmu: export a9wdog functions
> watchdog: add support for ux500_wdt watchdog
> mfd: db8500-prcmu: add ux500_wdt mfd_cell
All 4 patches (v2 for #3) applied, many thanks.
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
^ permalink raw reply
* [PATCH 06/26] mfd: ab8500-sysctrl: Provide configuration for SysClkReqRfClkBuf registers
From: Samuel Ortiz @ 2013-02-03 17:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130128083816.GZ15873@gmail.com>
Hi Lee,
On Mon, Jan 28, 2013 at 08:38:16AM +0000, Lee Jones wrote:
> On Mon, 28 Jan 2013, Samuel Ortiz wrote:
>
> > Hi Lee, Kennet,
> >
> > On Tue, Jan 15, 2013 at 12:55:46PM +0000, Lee Jones wrote:
> > > From: Kennet Wallden <kennet.wallden@stericsson.com>
> > >
> > > Add the possibility to pass configuration settings for
> > > SysCl1kReqRfClkBuf to SysClk8ReqRfClkBuf via platform data.
> > >
> > > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > > Signed-off-by: Kennet Wallden <kennet.wallden@stericsson.com>
> > > Reviewed-by: Karl-Johan PERNTZ <karl-johan.perntz@stericsson.com>
> > > Reviewed-by: Bengt JONSSON <bengt.g.jonsson@stericsson.com>
> > > ---
> > > drivers/mfd/ab8500-sysctrl.c | 25 +++++++++++++++++++++++++
> > > include/linux/mfd/abx500/ab8500-sysctrl.h | 5 +++++
> > > include/linux/mfd/abx500/ab8500.h | 2 ++
> > > 3 files changed, 32 insertions(+)
> > >
> > > diff --git a/drivers/mfd/ab8500-sysctrl.c b/drivers/mfd/ab8500-sysctrl.c
> > > index cf58f69..19a024e 100644
> > > --- a/drivers/mfd/ab8500-sysctrl.c
> > > +++ b/drivers/mfd/ab8500-sysctrl.c
> > > @@ -113,11 +113,36 @@ int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value)
> > > static int __devinit ab8500_sysctrl_probe(struct platform_device *pdev)
> > > {
> > > struct ab8500_platform_data *plat;
> > > + struct ab8500_sysctrl_platform_data *pdata;
> > >
> > > sysctrl_dev = &pdev->dev;
> > > plat = dev_get_platdata(pdev->dev.parent);
> > > if (plat->pm_power_off)
> > > pm_power_off = ab8500_power_off;
> > > +
> > > + pdata = plat->sysctrl;
> > > +
> > > + if (pdata) {
> > > + int ret;
> > > + int i;
> > > + int j;
> > Cosmetic
> > int i, j, ret;
>
> Hmmm... this is how I'd prefer it too,
Great, I'm glad we agree :)
> but other maintainers prefer
> one-per-line. It would be better if we could standardise it somewhere
> to prevent unnecessary fixups.
I certainly don't like that coding style and I sincerely believe a vast
majority of the kernel code avoids it as well.
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
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