* [PATCH V2] arm: mm: Remove hugetlb warning from Coherent DMA allocator
From: Steve Capper @ 2014-01-16 10:07 UTC (permalink / raw)
To: linux-arm-kernel
The Coherant DMA allocator allocates pages of high order then splits
them up into smaller pages.
This splitting logic would run into problems if the allocator was
given compound pages. Thus the Coherant DMA allocator was originally
incompatible with compound pages existing and, by extension, huge
pages. A compile #error was put in place whenever huge pages were
enabled.
Compatibility with compound pages has since been introduced by the
following commit (which merely excludes GFP_COMP pages from being
requested by the coherant DMA allocator):
ea2e705 ARM: 7172/1: dma: Drop GFP_COMP for DMA memory allocations
When huge page support was introduced to ARM, the compile #error in
dma-mapping.c was replaced by a #warning when it should have been
removed instead.
This patch removes the compile #warning in dma-mapping.c when huge
pages are enabled.
Signed-off-by: Steve Capper <steve.capper@linaro.org>
---
Changed in V2: commit message completely re-written to give a better
justification.
---
arch/arm/mm/dma-mapping.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index f61a570..8edd1b5 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -284,9 +284,6 @@ static void __dma_free_buffer(struct page *page, size_t size)
}
#ifdef CONFIG_MMU
-#ifdef CONFIG_HUGETLB_PAGE
-#warning ARM Coherent DMA allocator does not (yet) support huge TLB
-#endif
static void *__alloc_from_contiguous(struct device *dev, size_t size,
pgprot_t prot, struct page **ret_page,
--
1.8.1.4
^ permalink raw reply related
* [PATCH v4 0/7] mtd: spi-nor: add a new framework for SPI NOR
From: Jagan Teki @ 2014-01-16 9:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D7A237.8@freescale.com>
Hi Huang Shijie,
Thanks for your response, please see below.
On Thu, Jan 16, 2014 at 2:41 PM, Huang Shijie <b32955@freescale.com> wrote:
> ? 2014?01?16? 03:15, Jagan Teki ??:
>
>> Hi,
>>
>> On Wed, Dec 25, 2013 at 11:20 AM, Huang Shijie<b32955@freescale.com>
>> wrote:
>>>
>>> 1.) Why add a new framework for SPI NOR?
>>> The SPI-NOR controller such as Freescale's Quadspi controller is
>>> working
>>> in a different way from the SPI bus. It should knows the NOR commands
>>> to
>>> find the right LUT sequence. Unfortunately, the current code can not
>>> meet
>>> this requirement.
>>>
>>> 2.) How does this patch set do?
>>> This patch set adds a new spi-nor layer.
>>> Before this patch, the layer is like:
>>>
>>> MTD
>>> ------------------------
>>> m25p80
>>> ------------------------
>>> spi bus driver
>>> ------------------------
>>> SPI NOR chip
>>>
>>> After this patch, the layer is like:
>>> MTD
>>> ------------------------
>>> spi-nor
>>> ------------------------
>>> m25p80
>>> ------------------------
>>> spi bus driver
>>> ------------------------
>>> SPI NOR chip
Just for looking on your new framework, is that above link correct.
I guess it should be MTD -- m25p80 -- spi-nor -- spi bus driver -- SPI NOR chip
Because m25p80 will register to mtd core on top and will call spi core
data transfer.
Correct me if am wrong.
>>>
>>> With the spi-nor controller driver(Freescale Quadspi), it looks like:
>>> MTD
>>> ------------------------
>>> spi-nor
>>> ------------------------
>>> fsl-quadspi
>>> ------------------------
>>> SPI NOR chip
>>
>> I'm new to this thread, may be I'll ask basic questions.
>> 1) what does m25p80 contains with your new framework - will excludes
>> quad stuff if they add
>
> sorry, i do not understand your meaning.
>
> do you think the m25p80 can not support the quad read after this patch set?
>
>
>
>> 2) I didn't understand why the controller driver fsl-quadspi will be
>> in mtd becuase as it's (q)spi driver
>> may does flash or non-flash functionalities if ie, the case should be
>> part of drivers/spi/*
>
> Please read this thread, Mark though it should be spi nor driver:
>
> http://marc.info/?l=linux-arm-kernel&m=137782885415953&w=2
>
>> 3) Can you explain your framework precisely take an example of like
>> spi_controller_A with spi_flash_A
>> and qspi_controller_B and qspi_flash_B - how will this new framework
>> operates.
>>
> The framework is just cloned from the m25p80.c, and extract the common code,
> and provides more
> hooks such as
>
> @prepare/unpreare: used to do some work before or after the
> read/write/erase/lock/unlock.
> @read_xfer/write_xfer: We can use these two hooks to code all
> the following hooks if the driver tries to implement them
> by itself.
> @read_reg: used to read the registers, such as read status register,
> read configure register.
> @write_reg: used to write the registers, such as write enable,
> erase sector.
> @read_id: read out the ID info.
> @wait_till_ready: wait till the NOR becomes ready.
> @read: read out the data from the NOR.
> @write: write data to the NOR.
> @erase: erase a sector of the NOR.
>
My basic question is like I have a qspi spi controller in my SOC and I
designed two boards B1 and B2
B1 with quad spi controller connected with non-flash as a slave and B2
with quad spi controller connected
with quad flash as a slave.
Now please tell me how your framework works in this case? how many
drivers do I need to right
and call traces.
--
Thanks,
Jagan.
^ permalink raw reply
* [PATCH V7 3/3] ARM: imx: add suspend in ocram support for i.mx6sl
From: Anson Huang @ 2014-01-16 9:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389864907-4040-1-git-send-email-b20788@freescale.com>
i.MX6SL's suspend in ocram function is derived from i.MX6Q,
it can lower the DDR IO power from ~10mA at 1.2V to ~1mA at 1.2V,
measured on i.MX6SL EVK board, SH5.
Signed-off-by: Anson Huang <b20788@freescale.com>
---
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/pm-imx6q.c | 20 +++++++++++++++++++-
arch/arm/mach-imx/suspend-imx6.S | 28 ++++++++++++++++++++++++++--
3 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 3d96a45..f2df89f 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -105,7 +105,7 @@ ifeq ($(CONFIG_PM),y)
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o suspend-imx6.o
# i.MX6SL reuses i.MX6Q code
-obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
+obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o suspend-imx6.o
endif
# i.MX5 based machines
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index fc57340..0db9456 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -121,6 +121,14 @@ static const u32 imx6dl_mmdc_io_offset[] = {
0x74c, /* GPR_ADDS */
};
+static const u32 imx6sl_mmdc_io_offset[] = {
+ 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
+ 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
+ 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
+ 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
+ 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */
+};
+
static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
.cpu_type = MXC_CPU_IMX6Q,
.mmdc_compat = "fsl,imx6q-mmdc",
@@ -141,6 +149,16 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
.mmdc_io_offset = imx6dl_mmdc_io_offset,
};
+static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
+ .cpu_type = MXC_CPU_IMX6SL,
+ .mmdc_compat = "fsl,imx6sl-mmdc",
+ .src_compat = "fsl,imx6sl-src",
+ .iomuxc_compat = "fsl,imx6sl-iomuxc",
+ .gpc_compat = "fsl,imx6sl-gpc",
+ .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
+ .mmdc_io_offset = imx6sl_mmdc_io_offset,
+};
+
/*
* This structure is for passing necessary data for low level ocram
* suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
@@ -532,5 +550,5 @@ void __init imx6dl_pm_init(void)
void __init imx6sl_pm_init(void)
{
- imx6_pm_common_init(NULL);
+ imx6_pm_common_init(&imx6sl_pm_data);
}
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index d273ee7..f9694d5 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -63,6 +63,7 @@
#define MX6Q_SRC_GPR1 0x20
#define MX6Q_SRC_GPR2 0x24
#define MX6Q_MMDC_MAPSR 0x404
+#define MX6Q_MMDC_MPDGCTRL0 0x83c
#define MX6Q_GPC_IMR1 0x08
#define MX6Q_GPC_IMR2 0x0c
#define MX6Q_GPC_IMR3 0x10
@@ -107,14 +108,36 @@
ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
+ cmp r3, #MXC_CPU_IMX6SL
+ bne 4f
+
+ /* reset read FIFO, RST_RD_FIFO */
+ ldr r7, =MX6Q_MMDC_MPDGCTRL0
+ ldr r6, [r11, r7]
+ orr r6, r6, #(1 << 31)
+ str r6, [r11, r7]
+2:
+ ldr r6, [r11, r7]
+ ands r6, r6, #(1 << 31)
+ bne 2b
+
+ /* reset FIFO a second time */
+ ldr r6, [r11, r7]
+ orr r6, r6, #(1 << 31)
+ str r6, [r11, r7]
+3:
+ ldr r6, [r11, r7]
+ ands r6, r6, #(1 << 31)
+ bne 3b
+4:
/* let DDR out of self-refresh */
ldr r7, [r11, #MX6Q_MMDC_MAPSR]
bic r7, r7, #(1 << 21)
str r7, [r11, #MX6Q_MMDC_MAPSR]
-2:
+5:
ldr r7, [r11, #MX6Q_MMDC_MAPSR]
ands r7, r7, #(1 << 25)
- bne 2b
+ bne 5b
/* enable DDR auto power saving */
ldr r7, [r11, #MX6Q_MMDC_MAPSR]
@@ -282,6 +305,7 @@ resume:
str r7, [r11, #MX6Q_SRC_GPR1]
str r7, [r11, #MX6Q_SRC_GPR2]
+ ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
mov r5, #0x1
resume_mmdc
--
1.7.9.5
^ permalink raw reply related
* [PATCH V7 2/3] ARM: imx: add suspend in ocram support for i.mx6dl
From: Anson Huang @ 2014-01-16 9:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389864907-4040-1-git-send-email-b20788@freescale.com>
i.MX6DL's suspend in ocram function is derived from i.MX6Q,
it can lower the DDR IO power from ~26mA at 1.5V to ~15mA at 1.5V,
measured on i.MX6DL SabreSD board, R25.
Signed-off-by: Anson Huang <b20788@freescale.com>
---
arch/arm/mach-imx/pm-imx6q.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index 5e1d3ab..fc57340 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -109,6 +109,18 @@ static const u32 imx6q_mmdc_io_offset[] = {
0x74c, /* GPR_ADDS */
};
+static const u32 imx6dl_mmdc_io_offset[] = {
+ 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
+ 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
+ 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
+ 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
+ 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
+ 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
+ 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
+ 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
+ 0x74c, /* GPR_ADDS */
+};
+
static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
.cpu_type = MXC_CPU_IMX6Q,
.mmdc_compat = "fsl,imx6q-mmdc",
@@ -119,6 +131,16 @@ static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
.mmdc_io_offset = imx6q_mmdc_io_offset,
};
+static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
+ .cpu_type = MXC_CPU_IMX6DL,
+ .mmdc_compat = "fsl,imx6q-mmdc",
+ .src_compat = "fsl,imx6q-src",
+ .iomuxc_compat = "fsl,imx6dl-iomuxc",
+ .gpc_compat = "fsl,imx6q-gpc",
+ .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
+ .mmdc_io_offset = imx6dl_mmdc_io_offset,
+};
+
/*
* This structure is for passing necessary data for low level ocram
* suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
@@ -505,7 +527,7 @@ void __init imx6q_pm_init(void)
void __init imx6dl_pm_init(void)
{
- imx6_pm_common_init(NULL);
+ imx6_pm_common_init(&imx6dl_pm_data);
}
void __init imx6sl_pm_init(void)
--
1.7.9.5
^ permalink raw reply related
* [PATCH V7 1/3] ARM: imx: add suspend in ocram support for i.mx6q
From: Anson Huang @ 2014-01-16 9:35 UTC (permalink / raw)
To: linux-arm-kernel
When system enter suspend, we can set the DDR IO to
high-Z state to save DDR IOs' power consumption, this
operation can save many power(from ~26mA at 1.5V to ~15mA at 1.5V,
measured on i.MX6Q SabreSD board, R25) of DDR IOs. To
achieve that, we need to copy the suspend code to ocram
and run the low level hardware related code(set DDR IOs
to high-Z state) in ocram.
If there is no ocram space available, then system will
still do suspend in external DDR, hence no DDR IOs will
be set to high-Z.
The OCRAM usage layout is as below,
ocram suspend region(4K currently):
======================== high address ======================
.
.
.
^
^
^
imx6_suspend code
PM_INFO structure(imx6_cpu_pm_info)
======================== low address =======================
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Anson Huang <b20788@freescale.com>
---
Changes since V6:
1. Use u32 pointer instead of array defined in imx6_pm_socdata;
2. Optimize asm code, put all mmdc related resume code together in a macro define.
arch/arm/mach-imx/Makefile | 3 +-
arch/arm/mach-imx/common.h | 8 +-
arch/arm/mach-imx/hardware.h | 4 +-
arch/arm/mach-imx/mach-imx6q.c | 2 +-
arch/arm/mach-imx/mach-imx6sl.c | 3 +-
arch/arm/mach-imx/pm-imx6q.c | 281 +++++++++++++++++++++++++++++++++++-
arch/arm/mach-imx/suspend-imx6.S | 289 ++++++++++++++++++++++++++++++++++++++
7 files changed, 579 insertions(+), 11 deletions(-)
create mode 100644 arch/arm/mach-imx/suspend-imx6.S
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index befcaf5..3d96a45 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -102,7 +102,8 @@ obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
+AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o suspend-imx6.o
# i.MX6SL reuses i.MX6Q code
obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
endif
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 4f4a95c..a363e71 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -145,11 +145,17 @@ void imx_cpu_die(unsigned int cpu);
int imx_cpu_kill(unsigned int cpu);
#ifdef CONFIG_PM
+void imx6_suspend(void __iomem *ocram_vbase);
void imx6q_pm_init(void);
+void imx6dl_pm_init(void);
+void imx6sl_pm_init(void);
void imx6q_pm_set_ccm_base(void __iomem *base);
void imx5_pm_init(void);
#else
+static inline void imx6_suspend(void __iomem *ocram_vbase) {}
static inline void imx6q_pm_init(void) {}
+static inline void imx6dl_pm_init(void) {}
+static inline void imx6sl_pm_init(void) {}
static inline void imx6q_pm_set_ccm_base(void __iomem *base) {}
static inline void imx5_pm_init(void) {}
#endif
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index a3b0b04..abf43bb 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel at pengutronix.de
*
* This program is free software; you can redistribute it and/or
@@ -20,7 +20,9 @@
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#define __ASM_ARCH_MXC_HARDWARE_H__
+#ifndef __ASSEMBLY__
#include <asm/io.h>
+#endif
#include <asm/sizes.h>
#define addr_in_module(addr, mod) \
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index e51e3da..e629593 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -212,7 +212,7 @@ static void __init imx6q_init_machine(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
imx_anatop_init();
- imx6q_pm_init();
+ cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
imx6q_1588_init();
}
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 0f4fd4c..aa873d8 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -55,8 +55,7 @@ static void __init imx6sl_init_machine(void)
imx6sl_fec_init();
imx_anatop_init();
- /* Reuse imx6q pm code */
- imx6q_pm_init();
+ imx6sl_pm_init();
}
static void __init imx6sl_init_irq(void)
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index d45acc0..5e1d3ab 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
@@ -14,16 +14,19 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
+#include <linux/genalloc.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <linux/suspend.h>
#include <asm/cacheflush.h>
+#include <asm/fncpy.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
-#include <asm/hardware/cache-l2x0.h>
+#include <asm/tlb.h>
#include "common.h"
#include "hardware.h"
@@ -58,7 +61,85 @@
#define CGPR 0x64
#define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17)
+#define MX6Q_SUSPEND_OCRAM_SIZE 0x1000
+#define MX6_MAX_MMDC_IO_NUM 33
+
static void __iomem *ccm_base;
+static void __iomem *suspend_ocram_base;
+static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
+
+/*
+ * suspend ocram space layout:
+ * ======================== high address ======================
+ * .
+ * .
+ * .
+ * ^
+ * ^
+ * ^
+ * imx6_suspend code
+ * PM_INFO structure(imx6_cpu_pm_info)
+ * ======================== low address =======================
+ */
+
+struct imx6_pm_base {
+ phys_addr_t pbase;
+ void __iomem *vbase;
+};
+
+struct imx6_pm_socdata {
+ u32 cpu_type;
+ const char *mmdc_compat;
+ const char *src_compat;
+ const char *iomuxc_compat;
+ const char *gpc_compat;
+ const u32 mmdc_io_num;
+ const u32 *mmdc_io_offset;
+};
+
+static const u32 imx6q_mmdc_io_offset[] = {
+ 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
+ 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
+ 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
+ 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
+ 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
+ 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
+ 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
+ 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
+ 0x74c, /* GPR_ADDS */
+};
+
+static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
+ .cpu_type = MXC_CPU_IMX6Q,
+ .mmdc_compat = "fsl,imx6q-mmdc",
+ .src_compat = "fsl,imx6q-src",
+ .iomuxc_compat = "fsl,imx6q-iomuxc",
+ .gpc_compat = "fsl,imx6q-gpc",
+ .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
+ .mmdc_io_offset = imx6q_mmdc_io_offset,
+};
+
+/*
+ * This structure is for passing necessary data for low level ocram
+ * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
+ * definition is changed, the offset definition in
+ * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
+ * otherwise, the suspend to ocram function will be broken!
+ */
+struct imx6_cpu_pm_info {
+ phys_addr_t pbase; /* The physical address of pm_info. */
+ phys_addr_t resume_addr; /* The physical resume address for asm code */
+ u32 cpu_type;
+ u32 pm_info_size; /* Size of pm_info. */
+ struct imx6_pm_base mmdc_base;
+ struct imx6_pm_base src_base;
+ struct imx6_pm_base iomuxc_base;
+ struct imx6_pm_base ccm_base;
+ struct imx6_pm_base gpc_base;
+ struct imx6_pm_base l2_base;
+ u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
+ u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
+} __aligned(8);
void imx6q_set_int_mem_clk_lpm(void)
{
@@ -177,7 +258,17 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
static int imx6q_suspend_finish(unsigned long val)
{
- cpu_do_idle();
+ if (!imx6_suspend_in_ocram_fn) {
+ cpu_do_idle();
+ } else {
+ /*
+ * call low level suspend function in ocram,
+ * as we need to float DDR IO.
+ */
+ local_flush_tlb_all();
+ imx6_suspend_in_ocram_fn(suspend_ocram_base);
+ }
+
return 0;
}
@@ -187,7 +278,12 @@ static int imx6q_pm_enter(suspend_state_t state)
case PM_SUSPEND_MEM:
imx6q_set_lpm(STOP_POWER_OFF);
imx6q_enable_wb(true);
- imx6q_enable_rbc(true);
+ /*
+ * For suspend into ocram, asm code already take care of
+ * RBC setting, so we do NOT need to do that here.
+ */
+ if (!imx6_suspend_in_ocram_fn)
+ imx6q_enable_rbc(true);
imx_gpc_pre_suspend();
imx_anatop_pre_suspend();
imx_set_cpu_jump(0, v7_cpu_resume);
@@ -218,12 +314,172 @@ void __init imx6q_pm_set_ccm_base(void __iomem *base)
ccm_base = base;
}
-void __init imx6q_pm_init(void)
+static int __init imx6_pm_get_base(struct imx6_pm_base *base,
+ const char *compat)
+{
+ struct device_node *node;
+ struct resource res;
+ int ret = 0;
+
+ node = of_find_compatible_node(NULL, NULL, compat);
+ if (!node) {
+ ret = -ENODEV;
+ goto out;
+ }
+
+ ret = of_address_to_resource(node, 0, &res);
+ if (ret)
+ goto put_node;
+
+ base->pbase = res.start;
+ base->vbase = ioremap(res.start, resource_size(&res));
+ if (!base->vbase)
+ ret = -ENOMEM;
+
+put_node:
+ of_node_put(node);
+out:
+ return ret;
+}
+
+static int __init imx6q_ocram_suspend_init(const struct imx6_pm_socdata
+ *socdata)
+{
+ phys_addr_t ocram_pbase;
+ struct device_node *node;
+ struct platform_device *pdev;
+ struct imx6_cpu_pm_info *pm_info;
+ struct gen_pool *ocram_pool;
+ unsigned long ocram_base;
+ int i, ret = 0;
+ const u32 *mmdc_offset_array;
+
+ if (!socdata) {
+ pr_warn("%s: invalid argument!\n", __func__);
+ return -EINVAL;
+ }
+
+ node = of_find_compatible_node(NULL, NULL, "mmio-sram");
+ if (!node) {
+ pr_warn("%s: failed to find ocram node!\n", __func__);
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev) {
+ pr_warn("%s: failed to find ocram device!\n", __func__);
+ ret = -ENODEV;
+ goto put_node;
+ }
+
+ ocram_pool = dev_get_gen_pool(&pdev->dev);
+ if (!ocram_pool) {
+ pr_warn("%s: ocram pool unavailable!\n", __func__);
+ ret = -ENODEV;
+ goto put_node;
+ }
+
+ ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
+ if (!ocram_base) {
+ pr_warn("%s: unable to alloc ocram!\n", __func__);
+ ret = -ENOMEM;
+ goto put_node;
+ }
+
+ ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
+
+ suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
+ MX6Q_SUSPEND_OCRAM_SIZE, false);
+
+ pm_info = suspend_ocram_base;
+ pm_info->pbase = ocram_pbase;
+ pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
+ pm_info->pm_info_size = sizeof(*pm_info);
+
+ /*
+ * ccm physical address is not used by asm code currently,
+ * so get ccm virtual address directly, as we already have
+ * it from ccm driver.
+ */
+ pm_info->ccm_base.vbase = ccm_base;
+
+ ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
+ if (ret) {
+ pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
+ goto put_node;
+ }
+
+ ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
+ if (ret) {
+ pr_warn("%s: failed to get src base %d!\n", __func__, ret);
+ goto src_map_failed;
+ }
+
+ ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
+ if (ret) {
+ pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
+ goto iomuxc_map_failed;
+ }
+
+ ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
+ if (ret) {
+ pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
+ goto gpc_map_failed;
+ }
+
+ ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
+ if (ret) {
+ pr_warn("%s: failed to get pl310-cache base %d!\n",
+ __func__, ret);
+ goto pl310_cache_map_failed;
+ }
+
+ pm_info->cpu_type = socdata->cpu_type;
+ pm_info->mmdc_io_num = socdata->mmdc_io_num;
+ mmdc_offset_array = socdata->mmdc_io_offset;
+
+ for (i = 0; i < pm_info->mmdc_io_num; i++) {
+ pm_info->mmdc_io_val[i][0] =
+ mmdc_offset_array[i];
+ pm_info->mmdc_io_val[i][1] =
+ readl_relaxed(pm_info->iomuxc_base.vbase +
+ mmdc_offset_array[i]);
+ }
+
+ imx6_suspend_in_ocram_fn = fncpy(
+ suspend_ocram_base + sizeof(*pm_info),
+ &imx6_suspend,
+ MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
+
+ goto put_node;
+
+pl310_cache_map_failed:
+ iounmap(&pm_info->gpc_base.vbase);
+gpc_map_failed:
+ iounmap(&pm_info->iomuxc_base.vbase);
+iomuxc_map_failed:
+ iounmap(&pm_info->src_base.vbase);
+src_map_failed:
+ iounmap(&pm_info->mmdc_base.vbase);
+put_node:
+ of_node_put(node);
+
+ return ret;
+}
+
+static void __init imx6_pm_common_init(const struct imx6_pm_socdata
+ *socdata)
{
struct regmap *gpr;
+ int ret;
WARN_ON(!ccm_base);
+ ret = imx6q_ocram_suspend_init(socdata);
+ if (ret)
+ pr_warn("%s: failed to initialize ocram suspend %d!\n",
+ __func__, ret);
+
/*
* This is for SW workaround step #1 of ERR007265, see comments
* in imx6q_set_lpm for details of this errata.
@@ -241,3 +497,18 @@ void __init imx6q_pm_init(void)
suspend_set_ops(&imx6q_pm_ops);
}
+
+void __init imx6q_pm_init(void)
+{
+ imx6_pm_common_init(&imx6q_pm_data);
+}
+
+void __init imx6dl_pm_init(void)
+{
+ imx6_pm_common_init(NULL);
+}
+
+void __init imx6sl_pm_init(void)
+{
+ imx6_pm_common_init(NULL);
+}
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
new file mode 100644
index 0000000..d273ee7
--- /dev/null
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -0,0 +1,289 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/linkage.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "hardware.h"
+
+/*
+ * ==================== low level suspend ====================
+ *
+ * Better to follow below rules to use ARM registers:
+ * r0: pm_info structure address;
+ * r1 ~ r4: for saving pm_info members;
+ * r5 ~ r10: free registers;
+ * r11: io base address.
+ *
+ * suspend ocram space layout:
+ * ======================== high address ======================
+ * .
+ * .
+ * .
+ * ^
+ * ^
+ * ^
+ * imx6_suspend code
+ * PM_INFO structure(imx6_cpu_pm_info)
+ * ======================== low address =======================
+ */
+
+/*
+ * Below offsets are based on struct imx6_cpu_pm_info
+ * which defined in arch/arm/mach-imx/pm-imx6q.c, this
+ * structure contains necessary pm info for low level
+ * suspend related code.
+ */
+#define PM_INFO_PBASE_OFFSET 0x0
+#define PM_INFO_RESUME_ADDR_OFFSET 0x4
+#define PM_INFO_CPU_TYPE_OFFSET 0x8
+#define PM_INFO_PM_INFO_SIZE_OFFSET 0xC
+#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10
+#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14
+#define PM_INFO_MX6Q_SRC_P_OFFSET 0x18
+#define PM_INFO_MX6Q_SRC_V_OFFSET 0x1C
+#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x20
+#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x24
+#define PM_INFO_MX6Q_CCM_P_OFFSET 0x28
+#define PM_INFO_MX6Q_CCM_V_OFFSET 0x2C
+#define PM_INFO_MX6Q_GPC_P_OFFSET 0x30
+#define PM_INFO_MX6Q_GPC_V_OFFSET 0x34
+#define PM_INFO_MX6Q_L2_P_OFFSET 0x38
+#define PM_INFO_MX6Q_L2_V_OFFSET 0x3C
+#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40
+#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44
+
+#define MX6Q_SRC_GPR1 0x20
+#define MX6Q_SRC_GPR2 0x24
+#define MX6Q_MMDC_MAPSR 0x404
+#define MX6Q_GPC_IMR1 0x08
+#define MX6Q_GPC_IMR2 0x0c
+#define MX6Q_GPC_IMR3 0x10
+#define MX6Q_GPC_IMR4 0x14
+#define MX6Q_CCM_CCR 0x0
+
+ .align 3
+
+ .macro sync_l2_cache
+
+ /* sync L2 cache to drain L2's buffers to DRAM. */
+#ifdef CONFIG_CACHE_L2X0
+ ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
+ mov r6, #0x0
+ str r6, [r11, #L2X0_CACHE_SYNC]
+1:
+ ldr r6, [r11, #L2X0_CACHE_SYNC]
+ ands r6, r6, #0x1
+ bne 1b
+#endif
+
+ .endm
+
+ .macro resume_mmdc
+
+ /* restore MMDC IO */
+ cmp r5, #0x0
+ ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
+ ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
+
+ ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
+ ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
+ add r7, r7, r0
+1:
+ ldr r8, [r7], #0x4
+ ldr r9, [r7], #0x4
+ str r9, [r11, r8]
+ subs r6, r6, #0x1
+ bne 1b
+
+ cmp r5, #0x0
+ ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
+ ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
+
+ /* let DDR out of self-refresh */
+ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
+ bic r7, r7, #(1 << 21)
+ str r7, [r11, #MX6Q_MMDC_MAPSR]
+2:
+ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
+ ands r7, r7, #(1 << 25)
+ bne 2b
+
+ /* enable DDR auto power saving */
+ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
+ bic r7, r7, #0x1
+ str r7, [r11, #MX6Q_MMDC_MAPSR]
+
+ .endm
+
+ENTRY(imx6_suspend)
+ ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
+ ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
+ ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+ ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
+
+ /*
+ * counting the resume address in iram
+ * to set it in SRC register.
+ */
+ ldr r6, =imx6_suspend
+ ldr r7, =resume
+ sub r7, r7, r6
+ add r8, r1, r4
+ add r9, r8, r7
+
+ /*
+ * make sure TLB contain the addr we want,
+ * as we will access them after MMDC IO floated.
+ */
+
+ ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
+ ldr r6, [r11, #0x0]
+ ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+ ldr r6, [r11, #0x0]
+
+ /* use r11 to store the IO address */
+ ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
+ /* store physical resume addr and pm_info address. */
+ str r9, [r11, #MX6Q_SRC_GPR1]
+ str r1, [r11, #MX6Q_SRC_GPR2]
+
+ /* need to sync L2 cache before DSM. */
+ sync_l2_cache
+
+ ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
+ /*
+ * put DDR explicitly into self-refresh and
+ * disable automatic power savings.
+ */
+ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
+ orr r7, r7, #0x1
+ str r7, [r11, #MX6Q_MMDC_MAPSR]
+
+ /* make the DDR explicitly enter self-refresh. */
+ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
+ orr r7, r7, #(1 << 21)
+ str r7, [r11, #MX6Q_MMDC_MAPSR]
+
+poll_dvfs_set:
+ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
+ ands r7, r7, #(1 << 25)
+ beq poll_dvfs_set
+
+ ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
+ ldr r6, =0x0
+ ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
+ ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
+ add r8, r8, r0
+set_mmdc_io_lpm:
+ ldr r9, [r8], #0x8
+ str r6, [r11, r9]
+ subs r7, r7, #0x1
+ bne set_mmdc_io_lpm
+
+ /*
+ * mask all GPC interrupts before
+ * enabling the RBC counters to
+ * avoid the counter starting too
+ * early if an interupt is already
+ * pending.
+ */
+ ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+ ldr r6, [r11, #MX6Q_GPC_IMR1]
+ ldr r7, [r11, #MX6Q_GPC_IMR2]
+ ldr r8, [r11, #MX6Q_GPC_IMR3]
+ ldr r9, [r11, #MX6Q_GPC_IMR4]
+
+ ldr r10, =0xffffffff
+ str r10, [r11, #MX6Q_GPC_IMR1]
+ str r10, [r11, #MX6Q_GPC_IMR2]
+ str r10, [r11, #MX6Q_GPC_IMR3]
+ str r10, [r11, #MX6Q_GPC_IMR4]
+
+ /*
+ * enable the RBC bypass counter here
+ * to hold off the interrupts. RBC counter
+ * = 32 (1ms), Minimum RBC delay should be
+ * 400us for the analog LDOs to power down.
+ */
+ ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
+ ldr r10, [r11, #MX6Q_CCM_CCR]
+ bic r10, r10, #(0x3f << 21)
+ orr r10, r10, #(0x20 << 21)
+ str r10, [r11, #MX6Q_CCM_CCR]
+
+ /* enable the counter. */
+ ldr r10, [r11, #MX6Q_CCM_CCR]
+ orr r10, r10, #(0x1 << 27)
+ str r10, [r11, #MX6Q_CCM_CCR]
+
+ /* unmask all the GPC interrupts. */
+ ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+ str r6, [r11, #MX6Q_GPC_IMR1]
+ str r7, [r11, #MX6Q_GPC_IMR2]
+ str r8, [r11, #MX6Q_GPC_IMR3]
+ str r9, [r11, #MX6Q_GPC_IMR4]
+
+ /*
+ * now delay for a short while (3usec)
+ * ARM is at 1GHz@this point
+ * so a short loop should be enough.
+ * this delay is required to ensure that
+ * the RBC counter can start counting in
+ * case an interrupt is already pending
+ * or in case an interrupt arrives just
+ * as ARM is about to assert DSM_request.
+ */
+ ldr r6, =2000
+rbc_loop:
+ subs r6, r6, #0x1
+ bne rbc_loop
+
+ /* Zzz, enter stop mode */
+ wfi
+ nop
+ nop
+ nop
+ nop
+
+ /*
+ * run to here means there is pending
+ * wakeup source, system should auto
+ * resume, we need to restore MMDC IO first
+ */
+ mov r5, #0x0
+ resume_mmdc
+
+ /* return to suspend finish */
+ mov pc, lr
+
+resume:
+ /* invalidate L1 I-cache first */
+ mov r6, #0x0
+ mcr p15, 0, r6, c7, c5, 0
+ mcr p15, 0, r6, c7, c5, 6
+ /* enable the Icache and branch prediction */
+ mov r6, #0x1800
+ mcr p15, 0, r6, c1, c0, 0
+ isb
+
+ /* get physical resume address from pm_info. */
+ ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
+ /* clear core0's entry and parameter */
+ ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
+ mov r7, #0x0
+ str r7, [r11, #MX6Q_SRC_GPR1]
+ str r7, [r11, #MX6Q_SRC_GPR2]
+
+ mov r5, #0x1
+ resume_mmdc
+
+ mov pc, lr
+ENDPROC(imx6_suspend)
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2] pinctrl: sunxi: Honor GPIO output initial vaules
From: Maxime Ripard @ 2014-01-16 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389854063-31016-1-git-send-email-wens@csie.org>
On Thu, Jan 16, 2014 at 02:34:23PM +0800, Chen-Yu Tsai wrote:
> Some GPIO users, such as fixed-regulator, request GPIO output with
> initial value of 1. This was ignored by sunxi driver.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Could you also send it to stable please?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file
From: Pratyush Anand @ 2014-01-16 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2CC2A0A4A178534D93D5159BF3BCB66189FBE8D5D6@EAPEX1MAIL1.st.com>
On Thu, Jan 16, 2014 at 03:25:41PM +0800, Mohit KUMAR DCG wrote:
> Hi Arnd,
>
>
> > -----Original Message-----
> > From: Arnd Bergmann [mailto:arnd at arndb.de]
> > Sent: Sunday, December 15, 2013 12:33 AM
> > To: Mohit KUMAR DCG
> > Cc: linux-arm-kernel at lists.infradead.org; linux-pci at vger.kernel.org;
> > Pratyush ANAND; spear-devel; Viresh Kumar
> > Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to
> > header file
> >
> > On Friday 13 December 2013, Mohit KUMAR DCG wrote:
> > > > The RST bits should probably go into a drivers/reset driver. Not
> > > > sure what the other registers do, but I'm sure we can find a driver
> > > > for these too, possibly they should be part of the PHY driver?
> > >
> > > - Perhaps if we implement phy and reset driver then we may not
> > > require to move these definitions and it will address most of your
> > > comments on SPEar13xx pcie driver. I am understanding and working on
> > > this.l
> > >
>
> Though we are almost ready with v2. But few concerns:
>
> There are Spear soc common register used for misc configurations of clock, reset etc for all ips. Few of
> registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
> For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
>
> We have moved all these sata specific spear1340 configurations in a separate driver. On the basis of spear-ahci dt
> Node this driver's probe is called, which further adds ahci platform driver.
> We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
> The same driver.
>
> Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
> Or we keep this new driver in arch/arm/mach-spear only.
I think this misc configuration register block resource should be
passed to syscon (drivers/mfd/syscon.c) driver.
regmap_update_bits should be used to update these registers and hence
to configure pcie/sata settings.
As far as place is concerned, that can be kept into mfd and can be
named as spear13xx-syscon.c
Whats your opinion arnd?
Regards
Pratyush
>
> Regards
> Mohit
>
> >
> > Ok, very good.
> >
> > Arnd
^ permalink raw reply
* [PATCH v4 13/16] ARM: Add an emulate flag to the kprobes/uprobes instruction decode functions
From: Jon Medhurst (Tixy) @ 2014-01-16 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D6E1FE.8000303@linaro.org>
On Wed, 2014-01-15 at 14:31 -0500, David Long wrote:
> On 12/20/13 09:58, Jon Medhurst (Tixy) wrote:
> > On Sun, 2013-12-15 at 23:08 -0500, David Long wrote:
[...]
> >> {
> >> #ifdef CONFIG_THUMB2_KERNEL
> >> if (thumb) {
> >> @@ -253,7 +253,7 @@ set_emulated_insn(probes_opcode_t insn, struct arch_specific_insn *asi,
> >> * non-zero value, the corresponding nibble in pinsn is validated and modified
> >> * according to the type.
> >> */
> >> -static bool __kprobes decode_regs(probes_opcode_t *pinsn, u32 regs)
> >> +static bool __kprobes decode_regs(probes_opcode_t *pinsn, u32 regs, bool modify)
> >> {
> >> probes_opcode_t insn = *pinsn;
> >> probes_opcode_t mask = 0xf; /* Start at least significant nibble */
> >> @@ -317,9 +317,16 @@ static bool __kprobes decode_regs(probes_opcode_t *pinsn, u32 regs)
> >> /* Replace value of nibble with new register number... */
> >> insn &= ~mask;
> >> insn |= new_bits & mask;
> >> + if (modify) {
> >> + /* Replace value of nibble with new register number */
> >> + insn &= ~mask;
> >> + insn |= new_bits & mask;
> >> + }
> >
> > Huh? As is, the above addition doesn't do anything because insn has
> > already been modified. I guess you played with the idea that you needed
> > to avoid changing insn (you don't) and then didn't undo the experiment
> > quite right. :-)
> >
>
> The conditional modification of the instruction was part of Rabin's
> original work for uprobes, but I messed up the merge from an earlier
> working version of my patches. My intention was/is to delete the old
> unconditional code. Sounds like maybe you disagree though. The intent
> is to only modify the instruction in the kprobes case.
'insn' is the local variable containing the instruction value we're
processing. It doesn't matter if we change that, we just need to avoid
updating the instruction in memory, which the code in the next chunk
already correctly checks for...
> >> }
> >>
> >> - *pinsn = insn;
> >> + if (modify)
> >> + *pinsn = insn;
> >> +
> >> return true;
> >>
So only one of these 'if (modify)' checks is required for code
correctness, and I suggest keeping the second one as it's more explicit
and defensive.
--
Tixy
^ permalink raw reply
* [PATCH v4 0/7] mtd: spi-nor: add a new framework for SPI NOR
From: Huang Shijie @ 2014-01-16 9:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAD6G_RTnNQgeJM8Tc16Sc1_n29d=V9sJN1ePrOAn5YzM+GujMQ@mail.gmail.com>
? 2014?01?16? 03:15, Jagan Teki ??:
> Hi,
>
> On Wed, Dec 25, 2013 at 11:20 AM, Huang Shijie<b32955@freescale.com> wrote:
>> 1.) Why add a new framework for SPI NOR?
>> The SPI-NOR controller such as Freescale's Quadspi controller is working
>> in a different way from the SPI bus. It should knows the NOR commands to
>> find the right LUT sequence. Unfortunately, the current code can not meet
>> this requirement.
>>
>> 2.) How does this patch set do?
>> This patch set adds a new spi-nor layer.
>> Before this patch, the layer is like:
>>
>> MTD
>> ------------------------
>> m25p80
>> ------------------------
>> spi bus driver
>> ------------------------
>> SPI NOR chip
>>
>> After this patch, the layer is like:
>> MTD
>> ------------------------
>> spi-nor
>> ------------------------
>> m25p80
>> ------------------------
>> spi bus driver
>> ------------------------
>> SPI NOR chip
>>
>> With the spi-nor controller driver(Freescale Quadspi), it looks like:
>> MTD
>> ------------------------
>> spi-nor
>> ------------------------
>> fsl-quadspi
>> ------------------------
>> SPI NOR chip
> I'm new to this thread, may be I'll ask basic questions.
> 1) what does m25p80 contains with your new framework - will excludes
> quad stuff if they add
sorry, i do not understand your meaning.
do you think the m25p80 can not support the quad read after this patch set?
> 2) I didn't understand why the controller driver fsl-quadspi will be
> in mtd becuase as it's (q)spi driver
> may does flash or non-flash functionalities if ie, the case should be
> part of drivers/spi/*
Please read this thread, Mark though it should be spi nor driver:
http://marc.info/?l=linux-arm-kernel&m=137782885415953&w=2
> 3) Can you explain your framework precisely take an example of like
> spi_controller_A with spi_flash_A
> and qspi_controller_B and qspi_flash_B - how will this new framework operates.
>
The framework is just cloned from the m25p80.c, and extract the common
code, and provides more
hooks such as
@prepare/unpreare: used to do some work before or after the
read/write/erase/lock/unlock.
@read_xfer/write_xfer: We can use these two hooks to code all
the following hooks if the driver tries to implement them
by itself.
@read_reg: used to read the registers, such as read status register,
read configure register.
@write_reg: used to write the registers, such as write enable,
erase sector.
@read_id: read out the ID info.
@wait_till_ready: wait till the NOR becomes ready.
@read: read out the data from the NOR.
@write: write data to the NOR.
@erase: erase a sector of the NOR.
The drivers can implement these hooks.
thanks
Huang Shijie
^ permalink raw reply
* [PATCH 1/2] usb: chipidea: usbmisc: Add support for i.MX27/i.MX31 CPUs
From: Uwe Kleine-König @ 2014-01-16 9:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D5E9D4.2050405@gtsys.com.hk>
Hello Chris,
On Wed, Jan 15, 2014 at 09:52:20AM +0800, Chris Ruehl wrote:
> I have a customized board running OTG/host and USB2/host (USB1 not connected)
> Both ports are connected to a ISP1504 ULPI
Similar for me here, my board has usb2 only with an ISP1504.
> a) I need a rs-gpio to reset in addition to the cs-gpio the ISP1504 (done)
I see there are several new chipidea patches in next-20140116 compared
to next-20140110 what I am using. Is there explicit support for a
cs-gpios property? If so, it's not obvious.
> b) Implement UPLI viewport (IORESOURCE_MEM) and logic to set the
> external power supply.
> The code (b) was rejected and needs rework.
The patch I'm currently using is appended below. It doesn't work yet,
but I think that's because CS isn't set yet. In my machine's dts I'm
using:
&usbphy2 {
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
};
&usbh2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh2>;
status = "okay";
};
Does this look ok?
I'm out of time currently for this project, but I will search the
mailing list for your patches. If you Cc: on new attempts for b) I will
try to test it.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
arch/arm/boot/dts/imx27-pingrp.h | 14 +++++++++
arch/arm/boot/dts/imx27.dtsi | 67 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 81 insertions(+)
diff --git a/arch/arm/boot/dts/imx27-pingrp.h b/arch/arm/boot/dts/imx27-pingrp.h
index 57ca02f89dff..c4d698fddbc9 100644
--- a/arch/arm/boot/dts/imx27-pingrp.h
+++ b/arch/arm/boot/dts/imx27-pingrp.h
@@ -148,4 +148,18 @@
MX27_PAD_UART3_CTS__UART3_CTS 0x0 \
MX27_PAD_UART3_RTS__UART3_RTS 0x0
+#define MX27_USBH2_PINGRP1 \
+ MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 \
+ MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 \
+ MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 \
+ MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 \
+ MX27_PAD_USBH2_STP__USBH2_STP 0x0 \
+ MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 \
+ MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 \
+ MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 \
+ MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 \
+ MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 \
+ MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 \
+ MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
+
#endif /* __DTS_IMX27_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 7e98966b1834..391769fb291e 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -33,6 +33,9 @@
spi0 = &cspi1;
spi1 = &cspi2;
spi2 = &cspi3;
+ usb0 = &usbotg;
+ usb1 = &usbh1;
+ usb2 = &usbh2;
};
aitc: aitc-interrupt-controller at e0000000 {
@@ -70,6 +73,33 @@
};
};
+ usbphy {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbphy0: usbphy at 0 {
+ compatible = "usb-nop-xceiv";
+ reg = <0>;
+ clocks = <&clks 75>;
+ clock-names = "main_clk";
+ };
+
+ usbphy1: usbphy at 1 {
+ compatible = "usb-nop-xceiv";
+ reg = <1>;
+ clocks = <&clks 75>;
+ clock-names = "main_clk";
+ };
+
+ usbphy2: usbphy at 2 {
+ compatible = "usb-nop-xceiv";
+ reg = <2>;
+ clocks = <&clks 75>;
+ clock-names = "main_clk";
+ };
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -439,6 +469,43 @@
iram = <&iram>;
};
+ usbotg: usb at 10024000 {
+ compatible = "fsl,imx27-usb";
+ reg = <0x10024000 0x200>;
+ interrupts = <56>;
+ clocks = <&clks 15>;
+ fsl,usbmisc = <&usbmisc 0>;
+ fsl,usbphy = <&usbphy0>;
+ status = "disabled";
+ };
+
+ usbh1: usb at 10024200 {
+ compatible = "fsl,imx27-usb";
+ reg = <0x10024200 0x200>;
+ interrupts = <54>;
+ clocks = <&clks 15>;
+ fsl,usbmisc = <&usbmisc 1>;
+ fsl,usbphy = <&usbphy1>;
+ status = "disabled";
+ };
+
+ usbh2: usb at 10024400 {
+ compatible = "fsl,imx27-usb";
+ reg = <0x10024400 0x200>;
+ interrupts = <55>;
+ clocks = <&clks 15>;
+ fsl,usbmisc = <&usbmisc 2>;
+ fsl,usbphy = <&usbphy2>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc at 10024600 {
+ #index-cells = <1>;
+ compatible = "fsl,imx27-usbmisc";
+ reg = <0x10024600 0x200>;
+ clocks = <&clks 62>;
+ };
+
sahara2: sahara at 10025000 {
compatible = "fsl,imx27-sahara";
reg = <0x10025000 0x1000>;
--
1.8.5.2
^ permalink raw reply related
* device-tree: at91: irq and gpios: problem while requesting a gpio used as an interrupt source.
From: boris brezillon @ 2014-01-16 8:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140115180615.GJ9558@ns203013.ovh.net>
On 15/01/2014 19:06, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 11:35 Mon 13 Jan , boris brezillon wrote:
>> On 13/01/2014 11:29, Jean-Jacques Hiblot wrote:
>>> Hello Nicolas, Jean-Christophe,
>>>
>>> As I was trying to enable the touchscreen on the at91sam9261ek with
>>> device-tree support, I ran into an issue. The touchscreen driver needs
>>> to know the state of the pendown gpio and also needs it as an
>>> interrupt source.
>>>
>>> The problem is that when a gpio is used as an interrupt, it's
>>> requested by the pinctrl driver during the xlate stage, marking it
>>> unavaliable for the other driver.
>>> It looks like the at91 pinctrl driver is the only one to use
>>> gpio_request() in the xlate stage. Maybe we should remove this:
>> You should only request it as a GPIO and then use gpio_to_irq to get the
>> related IRQ.
> This here a HUGE issue in the hole kernel
>
> You should NEVER known ti's a gpio in the driver at all gpio_to_irq should never
> exist you need to only see the irq
>
>> Because what is done here, is to solve the case where only the irq
>> is request, and in this specific case we need to request the pin as a
>> GPIO.
> this need to be handled at irq level not drivers
Then propose something (or at least give us a deadline for this new
interrupt
model to come out), because the ADS7843E touchscreen is not working anymore
(at least on at91 platforms).
What this driver needs is a level IRQ (not an edge IRQ). The code in
ads7846_hard_irq<http://lxr.free-electrons.com/ident?i=ads7846_hard_irq>
interrupt handler is here to transform an edge IRQ into a level IRQ.
Is there a way to provide a generic framework to transform edge IRQs
into level IRQs
(because some GPIO controllers do not support level IRQs, and this is
the case for the
at91sam9261 one) ?
Of cource the gpio_to_irq approach is not perfect, but at least it as
the benefit to quickly
fix the bug, and we will still be able to improve this later, when we
have enough tools
(or mechanisms) to do it.
Best Regards,
Boris
> Best Regards,
> J.
^ permalink raw reply
* [PATCH] ARM: exynos_defconfig: Update EHCI config entry
From: Jingoo Han @ 2014-01-16 8:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389861264-7305-1-git-send-email-tushar.behera@linaro.org>
On Thursday, January 16, 2014 5:34 PM, Tushar Behera wrote:
>
> Commit 29824c167bea ("USB: host: Rename ehci-s5p to ehci-exynos")
> renamed the config entry of EHCI host driver. Similar change needs
> to be done in exynos_defconfig as well.
>
> Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
(+cc Vivek Gautam, Yulgon Kim, Julius Werner)
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Yes, right.
I overlooked 'exynos_defconfig', when I changed the name of
Exynos EHCI driver. Thank you for sending the patch. :-)
Best regards,
Jingoo Han
> ---
> arch/arm/configs/exynos_defconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
> index dbe1f1c..4ce7b70 100644
> --- a/arch/arm/configs/exynos_defconfig
> +++ b/arch/arm/configs/exynos_defconfig
> @@ -94,7 +94,7 @@ CONFIG_FONT_7x14=y
> CONFIG_LOGO=y
> CONFIG_USB=y
> CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_EHCI_S5P=y
> +CONFIG_USB_EHCI_EXYNOS=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_DWC3=y
> CONFIG_USB_PHY=y
> --
> 1.7.9.5
^ permalink raw reply
* [PATCH] ARM: exynos_defconfig: Update EHCI config entry
From: Tushar Behera @ 2014-01-16 8:34 UTC (permalink / raw)
To: linux-arm-kernel
Commit 29824c167bea ("USB: host: Rename ehci-s5p to ehci-exynos")
renamed the config entry of EHCI host driver. Similar change needs
to be done in exynos_defconfig as well.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
---
arch/arm/configs/exynos_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index dbe1f1c..4ce7b70 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -94,7 +94,7 @@ CONFIG_FONT_7x14=y
CONFIG_LOGO=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_S5P=y
+CONFIG_USB_EHCI_EXYNOS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC3=y
CONFIG_USB_PHY=y
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 2/2] serial: fsl_lpuart: add DMA support
From: Yao Yuan @ 2014-01-16 8:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201401151025.34628.arnd@arndb.de>
Hi, Arnd
> -----Original Message-----
> > #define DRIVER_NAME "fsl-lpuart"
> > #define DEV_NAME "ttyLP"
> > #define UART_NR 6
> > @@ -121,6 +132,26 @@ struct lpuart_port {
> > struct clk *clk;
> > unsigned int txfifo_size;
> > unsigned int rxfifo_size;
> > +
> > +#ifdef CONFIG_SERIAL_FSL_LPUART_DMA
> > + bool lpuart_dma_use;
> > + struct dma_chan *dma_tx_chan;
> > + struct dma_chan *dma_rx_chan;
> > + struct dma_async_tx_descriptor *dma_tx_desc;
> > + struct dma_async_tx_descriptor *dma_rx_desc;
> > + dma_addr_t dma_tx_buf_bus;
> > + dma_addr_t dma_rx_buf_bus;
> > + dma_cookie_t dma_tx_cookie;
> > + dma_cookie_t dma_rx_cookie;
> > + unsigned char *dma_tx_buf_virt;
> > + unsigned char *dma_rx_buf_virt;
> > + unsigned int dma_tx_bytes;
> > + unsigned int dma_rx_bytes;
> > + int dma_tx_in_progress;
> > + int dma_rx_in_progress;
> > + unsigned int dma_rx_timeout;
> > + struct timer_list lpuart_timer;
> > +#endif
> > };
>
> This part will result in a slight increase in data size even if dma
> support is turned off at compile time.
>
Yes, someone also want me define a independent struct for dma and allocate the memory when dma be use.
But I think this way will add a more memory access time, like a->b->c and a->c. And the variable
about dma is just a few bytes but used frequently. So I think I'd better define the variable about dma in lpuart_port struct.
^ permalink raw reply
* [PATCHv2 2/2] ARM: dts: imx53: add support for Ka-Ro TX53 modules
From: Lothar Waßmann @ 2014-01-16 8:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389860123-14874-1-git-send-email-LW@KARO-electronics.de>
This patch adds support for the Ka-Ro electronics GmbH TX53 modules.
There are two distinct module types. One with an LVDS display
interface and SATA support, the other with a parallel LCD
interface and no SATA interface.
Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx53-tx53-x03x.dts | 286 ++++++++++++++++++++++
arch/arm/boot/dts/imx53-tx53-x13x.dts | 240 +++++++++++++++++++
arch/arm/boot/dts/imx53-tx53.dtsi | 424 +++++++++++++++++++++++++++++----
4 files changed, 911 insertions(+), 41 deletions(-)
create mode 100644 arch/arm/boot/dts/imx53-tx53-x03x.dts
create mode 100644 arch/arm/boot/dts/imx53-tx53-x13x.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 059d280..392b60f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -154,6 +154,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx53-mba53.dtb \
imx53-qsb.dtb \
imx53-smd.dtb \
+ imx53-tx53-x03x.dtb \
+ imx53-tx53-x13x.dtb \
imx53-voipac-bsb.dtb \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts
new file mode 100644
index 0000000..9029ae9
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2013 Lothar Wa?mann <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx53-tx53.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Ka-Ro electronics TX53 module (LCD)";
+ compatible = "karo,tx53", "fsl,imx53";
+
+ aliases {
+ display = &display;
+ };
+
+ soc {
+ display: display at di0 {
+ compatible = "fsl,imx-parallel-display";
+ crtcs = <&ipu 0>;
+ interface-pix-fmt = "rgb24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgb24_vga1>;
+ status = "okay";
+
+ display-timings {
+ VGA {
+ clock-frequency = <25200000>;
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <48>;
+ hsync-len = <96>;
+ hfront-porch = <16>;
+ vback-porch = <31>;
+ vsync-len = <2>;
+ vfront-porch = <12>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+
+ ETV570 {
+ clock-frequency = <25200000>;
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <114>;
+ hsync-len = <30>;
+ hfront-porch = <16>;
+ vback-porch = <32>;
+ vsync-len = <3>;
+ vfront-porch = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+
+ ET0350 {
+ clock-frequency = <6413760>;
+ hactive = <320>;
+ vactive = <240>;
+ hback-porch = <34>;
+ hsync-len = <34>;
+ hfront-porch = <20>;
+ vback-porch = <15>;
+ vsync-len = <3>;
+ vfront-porch = <4>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+
+ ET0430 {
+ clock-frequency = <9009000>;
+ hactive = <480>;
+ vactive = <272>;
+ hback-porch = <2>;
+ hsync-len = <41>;
+ hfront-porch = <2>;
+ vback-porch = <2>;
+ vsync-len = <10>;
+ vfront-porch = <2>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+
+ ET0500 {
+ clock-frequency = <33264000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <88>;
+ hsync-len = <128>;
+ hfront-porch = <40>;
+ vback-porch = <33>;
+ vsync-len = <2>;
+ vfront-porch = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+
+ ET0700 { /* same as ET0500 */
+ clock-frequency = <33264000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <88>;
+ hsync-len = <128>;
+ hfront-porch = <40>;
+ vback-porch = <33>;
+ vsync-len = <2>;
+ vfront-porch = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+
+ ETQ570 {
+ clock-frequency = <6596040>;
+ hactive = <320>;
+ vactive = <240>;
+ hback-porch = <38>;
+ hsync-len = <30>;
+ hfront-porch = <30>;
+ vback-porch = <16>;
+ vsync-len = <3>;
+ vfront-porch = <4>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
+ power-supply = <®_3v3>;
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100
+ >;
+ default-brightness-level = <50>;
+ };
+
+ regulators {
+ reg_lcd_pwr: regulator at 5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "LCD POWER";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ reg_lcd_reset: regulator at 6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ regulator-name = "LCD RESET";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ sgtl5000: codec at 0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <®_2v5>;
+ VDDIO-supply = <®_3v3>;
+ clocks = <&mclk>;
+ };
+
+ polytouch: edt-ft5x06 at 38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_edt_ft5x06_1>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <15 0>;
+ reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ touchscreen: tsc2007 at 48 {
+ compatible = "ti,tsc2007";
+ reg = <0x48>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc2007>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <26 0>;
+ gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+ ti,x-plate-ohms = <660>;
+ linux,wakeup;
+ };
+};
+
+&iomuxc {
+ imx53-tx53-x03x {
+ pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 {
+ fsl,pins = <
+ MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */
+ MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */
+ MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */
+ >;
+ };
+
+ pinctrl_kpp: kppgrp {
+ fsl,pins = <
+ MX53_PAD_GPIO_9__KPP_COL_6 0x1f4
+ MX53_PAD_GPIO_4__KPP_COL_7 0x1f4
+ MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4
+ MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4
+ MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4
+ MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4
+ MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4
+ MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4
+ >;
+ };
+
+ pinctrl_rgb24_vga1: rgb24-vgagrp1 {
+ fsl,pins = <MX53_IPU_DISP0_PINGRP1>;
+ };
+
+ pinctrl_tsc2007: tsc2007grp {
+ fsl,pins = <
+ MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */
+ >;
+ };
+ };
+};
+
+&kpp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_kpp>;
+ /* sample keymap */
+ /* row/col 0,1 are mapped to KPP row/col 6,7 */
+ linux,keymap = <
+ MATRIX_KEY(6, 6, KEY_POWER)
+ MATRIX_KEY(6, 7, KEY_KP0)
+ MATRIX_KEY(6, 2, KEY_KP1)
+ MATRIX_KEY(6, 3, KEY_KP2)
+ MATRIX_KEY(7, 6, KEY_KP3)
+ MATRIX_KEY(7, 7, KEY_KP4)
+ MATRIX_KEY(7, 2, KEY_KP5)
+ MATRIX_KEY(7, 3, KEY_KP6)
+ MATRIX_KEY(2, 6, KEY_KP7)
+ MATRIX_KEY(2, 7, KEY_KP8)
+ MATRIX_KEY(2, 2, KEY_KP9)
+ >;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts
new file mode 100644
index 0000000..eb5d51f
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-tx53-x13x.dts
@@ -0,0 +1,240 @@
+/*
+ * Copyright 2013 Lothar Wa?mann <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx53-tx53.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Ka-Ro electronics TX53 module (LVDS)";
+ compatible = "karo,tx53", "fsl,imx53";
+
+ aliases {
+ display = &lvds0;
+ lvds0 = &lvds0;
+ lvds1 = &lvds1;
+ };
+
+ backlight0: backlight0 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 0 500000 0>;
+ power-supply = <®_3v3>;
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100
+ >;
+ default-brightness-level = <50>;
+ };
+
+ backlight1: backlight1 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 500000 0>;
+ power-supply = <®_3v3>;
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100
+ >;
+ default-brightness-level = <50>;
+ };
+
+ regulators {
+ reg_lcd_pwr0: regulator at 5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "LVDS0 POWER";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ reg_lcd_pwr1: regulator at 6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ regulator-name = "LVDS1 POWER";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ touchscreen2: eeti at 04 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eeti2>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <23 0>;
+ wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+ linux,wakeup;
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ sgtl5000: codec at 0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <®_2v5>;
+ VDDIO-supply = <®_3v3>;
+ clocks = <&mclk>;
+ };
+
+ touchscreen1: eeti at 04 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eeti1>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <22 0>;
+ wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ linux,wakeup;
+ };
+};
+
+&iomuxc {
+ imx53-tx53-x13x {
+ pinctrl_i2c2: i2c2-grp1 {
+ fsl,pins = <MX53_I2C2_PINGRP1>;
+ };
+
+ pinctrl_lvds0: lvds0grp {
+ fsl,pins = <
+ MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
+ MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
+ MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
+ MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
+ MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
+ >;
+ };
+
+ pinctrl_lvds1: lvds1grp {
+ fsl,pins = <
+ MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
+ MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
+ MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
+ MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
+ MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <MX53_PAD_GPIO_9__PWM1_PWMO 0x04>;
+ };
+
+ pinctrl_eeti1: eeti1grp {
+ fsl,pins = <
+ MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */
+ >;
+ };
+
+ pinctrl_eeti2: eeti2grp {
+ fsl,pins = <
+ MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */
+ >;
+ };
+ };
+};
+
+&ldb {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>;
+ status = "okay";
+
+ lvds0: lvds-channel at 0 {
+ fsl,data-mapping = "jeida";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&lvds_timing0>;
+ lvds_timing0: hsd100pxn1 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <220>;
+ hsync-len = <60>;
+ hfront-porch = <40>;
+ vback-porch = <21>;
+ vsync-len = <10>;
+ vfront-porch = <7>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+
+ lvds1: lvds-channel at 1 {
+ fsl,data-mapping = "jeida";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&lvds_timing1>;
+ lvds_timing1: hsd100pxn1 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <220>;
+ hsync-len = <60>;
+ hfront-porch = <40>;
+ vback-porch = <21>;
+ vsync-len = <10>;
+ vfront-porch = <7>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index db4255c..43dc467 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -1,22 +1,69 @@
/*
- * Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ * Copyright 2012 <LW@KARO-electronics.de>
+ * based on imx53-qsb.dts
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
-/include/ "imx53.dtsi"
+#include "imx53.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
- model = "Ka-Ro TX53";
+ model = "Ka-Ro electronics TX53 module";
compatible = "karo,tx53", "fsl,imx53";
- memory {
- reg = <0x70000000 0x40000000>; /* Up to 1GiB */
+ aliases {
+ can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */
+ can1 = &can1;
+ ipu = &ipu;
+ reg_can_xcvr = ®_can_xcvr;
+ usbh1 = &usbh1;
+ usbotg = &usbotg;
+ };
+
+ clocks {
+ ckih1 {
+ clock-frequency = <0>;
+ };
+
+ mclk: clock at 0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_key>;
+
+ power {
+ label = "Power Button";
+ gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ linux,code = <116>; /* KEY_POWER */
+ gpio-key,wakeup;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_stk5led>;
+
+ user {
+ label = "Heartbeat";
+ gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
};
regulators {
@@ -24,102 +71,397 @@
#address-cells = <1>;
#size-cells = <0>;
- reg_3p3v: regulator at 0 {
+ reg_2v5: regulator at 0 {
compatible = "regulator-fixed";
reg = <0>;
- regulator-name = "3P3V";
+ regulator-name = "2V5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
+ reg_3v3: regulator at 1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_can_xcvr: regulator at 2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-always-on;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can_xcvr>;
+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ enable-active-low;
};
+
+ reg_usbh1_vbus: regulator at 3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "usbh1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1_vbus>;
+ gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usbotg_vbus: regulator at 4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "usbotg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg_vbus>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+ sound {
+ compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000";
+ model = "tx53-audio-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ /* '1' based port numbers according to datasheet names */
+ mux-int-port = <1>;
+ mux-ext-port = <5>;
};
};
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssi1>;
+ status = "okay";
+};
+
&can1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can1_2>;
- status = "disabled";
+ pinctrl-0 = <&pinctrl_can1>;
+ xceiver-supply = <®_can_xcvr>;
+ status = "okay";
};
&can2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can2_1>;
- status = "disabled";
+ pinctrl-0 = <&pinctrl_can2>;
+ xceiver-supply = <®_can_xcvr>;
+ status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1_2>;
- status = "disabled";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ fsl,spi-num-chipselects = <2>;
+ status = "okay";
+
+ cs-gpios = <
+ &gpio2 30 GPIO_ACTIVE_HIGH
+ &gpio3 19 GPIO_ACTIVE_HIGH
+ >;
+
+ spidev0: spi at 0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <54000000>;
+ };
+
+ spidev1: spi at 1 {
+ compatible = "spidev";
+ reg = <1>;
+ spi-max-frequency = <54000000>;
+ };
};
&esdhc1 {
+ cd-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ fsl,wp-controller;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_esdhc1_2>;
- status = "disabled";
+ pinctrl-0 = <&pinctrl_esdhc1>;
+ status = "okay";
};
&esdhc2 {
+ cd-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ fsl,wp-controller;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_esdhc2_1>;
- status = "disabled";
+ pinctrl-0 = <&pinctrl_esdhc2>;
+ status = "okay";
};
&fec {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec_1>;
+ pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
- status = "disabled";
+ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
+ phy-handle = <&phy0>;
+ mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */
+ status = "okay";
+
+ phy0: ethernet-phy at 0 {
+ interrupt-parent = <&gpio2>;
+ interrupts = <4>;
+ device_type = "ethernet-phy";
+ };
};
-&i2c3 {
+&i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3_2>;
- status = "disabled";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ rtc1: ds1339 at 68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ds1339>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <20 0>;
+ };
};
-&owire {
+&iomuxc {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_owire_1>;
- status = "disabled";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx53-tx53 {
+ pinctrl_hog: hoggrp {
+ /* pins not in use by any device on the Starterkit board series */
+ fsl,pins = <
+ /* CMOS Sensor Interface */
+ MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4
+ MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4
+ MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4
+ MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4
+ MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4
+ MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4
+ MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4
+ MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4
+ MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4
+ MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4
+ MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4
+ MX53_PAD_GPIO_0__GPIO1_0 0x1f4
+ /* Module Specific Signal */
+ /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */
+ /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */
+ MX53_PAD_EIM_D29__GPIO3_29 0x1f4
+ MX53_PAD_EIM_EB3__GPIO2_31 0x1f4
+ /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */
+ /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */
+ MX53_PAD_EIM_A19__GPIO2_19 0x1f4
+ MX53_PAD_EIM_A20__GPIO2_18 0x1f4
+ MX53_PAD_EIM_A21__GPIO2_17 0x1f4
+ MX53_PAD_EIM_A22__GPIO2_16 0x1f4
+ MX53_PAD_EIM_A23__GPIO6_6 0x1f4
+ MX53_PAD_EIM_A24__GPIO5_4 0x1f4
+ MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4
+ MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4
+ MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4
+ MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4
+ /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */
+ /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */
+ MX53_PAD_GPIO_13__GPIO4_3 0x1f4
+ MX53_PAD_EIM_CS0__GPIO2_23 0x1f4
+ MX53_PAD_EIM_CS1__GPIO2_24 0x1f4
+ MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4
+ MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4
+ MX53_PAD_EIM_EB0__GPIO2_28 0x1f4
+ MX53_PAD_EIM_EB1__GPIO2_29 0x1f4
+ MX53_PAD_EIM_OE__GPIO2_25 0x1f4
+ MX53_PAD_EIM_LBA__GPIO2_27 0x1f4
+ MX53_PAD_EIM_RW__GPIO2_26 0x1f4
+ MX53_PAD_EIM_DA8__GPIO3_8 0x1f4
+ MX53_PAD_EIM_DA9__GPIO3_9 0x1f4
+ MX53_PAD_EIM_DA10__GPIO3_10 0x1f4
+ MX53_PAD_EIM_DA11__GPIO3_11 0x1f4
+ MX53_PAD_EIM_DA12__GPIO3_12 0x1f4
+ MX53_PAD_EIM_DA13__GPIO3_13 0x1f4
+ MX53_PAD_EIM_DA14__GPIO3_14 0x1f4
+ MX53_PAD_EIM_DA15__GPIO3_15 0x1f4
+ >;
+ };
+
+ pinctrl_can1: can1grp {
+ fsl,pins = <MX53_CAN1_PINGRP3>;
+ };
+
+ pinctrl_can2: can2grp {
+ fsl,pins = <MX53_CAN2_PINGRP1>;
+ };
+
+ pinctrl_can_xcvr: can-xcvrgrp {
+ fsl,pins = <MX53_PAD_DISP0_DAT0__GPIO4_21 0xe0>; /* Flexcan XCVR enable */
+ };
+
+ pinctrl_ds1339: ds1339grp {
+ fsl,pins = <MX53_PAD_DI0_PIN4__GPIO4_20 0xe0>;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <MX53_ECSPI1_PINGRP2>;
+ };
+
+ pinctrl_esdhc1: esdhc1grp {
+ fsl,pins = <MX53_ESDHC1_PINGRP1
+ MX53_PAD_EIM_D24__GPIO3_24 0x1f0
+ >;
+ };
+
+ pinctrl_esdhc2: esdhc2grp {
+ fsl,pins = <MX53_ESDHC2_PINGRP1
+ MX53_PAD_EIM_D25__GPIO3_25 0x1f0
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <MX53_FEC_PINGRP1>;
+ };
+
+ pinctrl_gpio_key: gpio-keygrp {
+ fsl,pins = <MX53_PAD_EIM_A25__GPIO5_2 0x1f4>;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <MX53_I2C1_PINGRP2>;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <MX53_I2C3_PINGRP2>;
+ };
+
+ pinctrl_nand: nandgrp {
+ fsl,pins = <MX53_NAND_PINGRP2>;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <MX53_PWM2_PINGRP1>;
+ };
+
+ pinctrl_ssi1: ssi1grp {
+ fsl,pins = <MX53_AUDMUX_PINGRP1>;
+ };
+
+ pinctrl_ssi2: ssi2grp {
+ fsl,pins = <MX53_AUDMUX_PINGRP3
+ MX53_PAD_EIM_D27__GPIO3_27 0x1f0
+ >;
+ };
+
+ pinctrl_stk5led: stk5ledgrp {
+ fsl,pins = <MX53_PAD_EIM_A18__GPIO2_20 0xc0>;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <MX53_UART1_PINGRP2 MX53_UART1_PINGRP3>;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <MX53_UART2_PINGRP2>;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <MX53_UART3_PINGRP1>;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */
+ >;
+ };
+
+ pinctrl_usbh1_vbus: usbh1-vbusgrp {
+ fsl,pins = <
+ MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */
+ >;
+ };
+
+ pinctrl_usbotg_vbus: usbotg-vbusgrp {
+ fsl,pins = <
+ MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */
+ MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */
+ >;
+ };
+ };
+};
+
+&ipu {
+ status = "okay";
+};
+
+&nfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ status = "okay";
};
&pwm2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm2_1>;
- status = "disabled";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ #pwm-cells = <3>;
+};
+
+&sdma {
+ fsl,sdma-ram-script-name = "sdma-imx53.bin";
};
&ssi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux_1>;
- status = "disabled";
+ fsl,mode = "i2s-slave";
+ codec-handle = <&sgtl5000>;
+ status = "okay";
};
&ssi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux_2>;
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1_2>,
- <&pinctrl_uart1_3>;
+ pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
- status = "disabled";
+ status = "okay";
};
&uart2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2_2>;
+ pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
- status = "disabled";
+ status = "okay";
};
&uart3 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3_1>;
+ pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
- status = "disabled";
+ status = "okay";
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ phy_type = "utmi";
+ disable-over-current;
+ vbus-supply = <®_usbh1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ phy_type = "utmi";
+ dr_mode = "peripheral";
+ disable-over-current;
+ vbus-supply = <®_usbotg_vbus>;
+ status = "okay";
};
--
1.7.2.5
^ permalink raw reply related
* [PATCHv2 1/2] ARM: dts: imx53: add another pingroup for NAND pads
From: Lothar Waßmann @ 2014-01-16 8:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389860123-14874-1-git-send-email-LW@KARO-electronics.de>
Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
---
arch/arm/boot/dts/imx53-pingrp.h | 17 +++++++++++++++++
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/imx53-pingrp.h b/arch/arm/boot/dts/imx53-pingrp.h
index ac8e73d..f8d7d9c 100644
--- a/arch/arm/boot/dts/imx53-pingrp.h
+++ b/arch/arm/boot/dts/imx53-pingrp.h
@@ -300,6 +300,23 @@
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 \
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
+#define MX53_NAND_PINGRP2 \
+ MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 \
+ MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 \
+ MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 \
+ MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 \
+ MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 \
+ MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 \
+ MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 \
+ MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 \
+ MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 \
+ MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 \
+ MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 \
+ MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 \
+ MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 \
+ MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 \
+ MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4
+
#define MX53_OWIRE_PINGRP1 \
MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
--
1.7.2.5
^ permalink raw reply related
* [PATCHv2 0/2] ARM: dts: imx53: add support for Ka-Ro TX53 modules
From: Lothar Waßmann @ 2014-01-16 8:15 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for the Ka-Ro electronics GmbH TX53 modules.
There are two distinct module types. One with an LVDS display
interface and SATA support, the other with a parallel LCD
interface and no SATA interface.
Changes wrt. v1:
- set the '#pwm-cells' property locally due to the changed
pwm-polarity patch that made this property optional.
see <1389859585-14006-3-git-send-email-LW@KARO-electronics.de>
^ permalink raw reply
* [PATCH] ARM: orion: provide C-style interrupt handler for MULTI_IRQ_HANDLER
From: Sebastian Hesselbarth @ 2014-01-16 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389775235.10695.51.camel@dagon.hellion.org.uk>
DT-enabled Marvell Kirkwood and Dove SoCs make use of an irqchip
driver. As expected for irqchip drivers, it uses a C-style
interrupt handler and therefore selects MULTI_IRQ_HANDLER.
Now, compiling a kernel with both non-DT and DT support enabled,
selecting MULTI_IRQ_HANDLER will break ASM irq handler used by
non-DT boards.
Therefore, we provide a C-style irq handler even for non-DT boards,
if MULTI_IRQ_HANDLER is set. By installing the C-style irq handler
in orion_irq_init this is transparent to all non-DT board files.
While the regression report was filed on Marvell Kirkwood, also
Marvell Dove non-DT boards are affected and fixed by this patch.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Reported-by: Ian Campbell <ijc@hellion.org.uk>
Fixes: 2326f04321a9 ("ARM: kirkwood: convert to DT irqchip and clocksource")
Fixes: f07d73e33d0e ("ARM: dove: convert to DT irqchip and clocksource")
---
Compared to the two patch version sent on Ian's regression report,
I cooked this down to a single patch only touching plat-orion/irq.c.
I also dropped Orion5x and MV78x00, as they not yet select MULTI_IRQ_HANDLER
at all. Instead I added a comment about taking care of them, as soon as
they move over to an irqchip driver themselves.
I have not yet Cc'ed this patch to -stable to get some discussion and
an Acked-by from Jason or Andrew, too.
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
arch/arm/plat-orion/irq.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index c492e1b3dfdb..807df142444b 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -15,8 +15,51 @@
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <asm/exception.h>
#include <plat/irq.h>
#include <plat/orion-gpio.h>
+#include <mach/bridge-regs.h>
+
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+/*
+ * Compiling with both non-DT and DT support enabled, will
+ * break asm irq handler used by non-DT boards. Therefore,
+ * we provide a C-style irq handler even for non-DT boards,
+ * if MULTI_IRQ_HANDLER is set.
+ *
+ * Notes:
+ * - this is prepared for Kirkwood and Dove only, update
+ * accordingly if you add Orion5x or MV78x00.
+ * - Orion5x uses different macro names and has only one
+ * set of CAUSE/MASK registers.
+ * - MV78x00 uses the same macro names but has a third
+ * set of CAUSE/MASK registers.
+ *
+ */
+
+static void __iomem *orion_irq_base = IRQ_VIRT_BASE;
+
+asmlinkage void
+__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs)
+{
+ u32 stat;
+
+ stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF);
+ stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF);
+ if (stat) {
+ unsigned int hwirq = __fls(stat);
+ handle_IRQ(hwirq, regs);
+ return;
+ }
+ stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF);
+ stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF);
+ if (stat) {
+ unsigned int hwirq = 32 + __fls(stat);
+ handle_IRQ(hwirq, regs);
+ return;
+ }
+}
+#endif
void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
{
@@ -35,6 +78,10 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
ct->chip.irq_unmask = irq_gc_mask_set_bit;
irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
+
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+ set_handle_irq(orion_legacy_handle_irq);
+#endif
}
#ifdef CONFIG_OF
--
1.8.5.2
^ permalink raw reply related
* [PATCHv2 2/2] pwm: imx: support polarity inversion
From: Lothar Waßmann @ 2014-01-16 8:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389859585-14006-1-git-send-email-LW@KARO-electronics.de>
The i.MX PWM controller supports inverting the polarity of the PWM
output. Make this feature available in the pxm-imx driver.
Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
---
Documentation/devicetree/bindings/pwm/imx-pwm.txt | 5 +-
drivers/pwm/pwm-imx.c | 42 +++++++++++++++++++++
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
index b50d7a6d..d0b04b5 100644
--- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
@@ -3,8 +3,9 @@ Freescale i.MX PWM controller
Required properties:
- compatible: should be "fsl,<soc>-pwm"
- reg: physical base address and length of the controller's registers
-- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
- the cells format.
+- #pwm-cells: may be 2 for backwards compatibility or 3 to support
+ switching the output polarity. See pwm.txt in this directory for a
+ description of the cells format.
- interrupts: The interrupt for the pwm controller
Example:
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 3b00a82..05461bb 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -36,6 +36,7 @@
#define MX3_PWMCR_DOZEEN (1 << 24)
#define MX3_PWMCR_WAITEN (1 << 23)
#define MX3_PWMCR_DBGEN (1 << 22)
+#define MX3_PWMCR_POUTC (1 << 18)
#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
#define MX3_PWMCR_EN (1 << 0)
@@ -138,6 +139,9 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
if (test_bit(PWMF_ENABLED, &pwm->flags))
cr |= MX3_PWMCR_EN;
+ if (pwm->polarity == PWM_POLARITY_INVERSED)
+ cr |= MX3_PWMCR_POUTC;
+
writel(cr, imx->mmio_base + MX3_PWMCR);
return 0;
@@ -155,6 +159,11 @@ static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
else
val &= ~MX3_PWMCR_EN;
+ if (chip->pwms[0].polarity == PWM_POLARITY_INVERSED)
+ val |= MX3_PWMCR_POUTC;
+ else
+ val &= ~MX3_PWMCR_POUTC;
+
writel(val, imx->mmio_base + MX3_PWMCR);
}
@@ -198,6 +207,17 @@ static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
clk_disable_unprepare(imx->clk_per);
}
+static int imx_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
+ enum pwm_polarity polarity)
+{
+ struct imx_chip *imx = to_imx_chip(chip);
+
+ dev_dbg(imx->chip.dev, "%s: polarity set to %s\n", __func__,
+ polarity == PWM_POLARITY_INVERSED ? "inverted" : "normal");
+
+ return 0;
+}
+
static struct pwm_ops imx_pwm_ops = {
.enable = imx_pwm_enable,
.disable = imx_pwm_disable,
@@ -209,6 +229,7 @@ struct imx_pwm_data {
int (*config)(struct pwm_chip *chip,
struct pwm_device *pwm, int duty_ns, int period_ns);
void (*set_enable)(struct pwm_chip *chip, bool enable);
+ unsigned output_polarity:1;
};
static struct imx_pwm_data imx_pwm_data_v1 = {
@@ -219,6 +240,7 @@ static struct imx_pwm_data imx_pwm_data_v1 = {
static struct imx_pwm_data imx_pwm_data_v2 = {
.config = imx_pwm_config_v2,
.set_enable = imx_pwm_set_enable_v2,
+ .output_polarity = 1,
};
static const struct of_device_id imx_pwm_dt_ids[] = {
@@ -271,6 +293,26 @@ static int imx_pwm_probe(struct platform_device *pdev)
return PTR_ERR(imx->mmio_base);
data = of_id->data;
+ if (data->output_polarity) {
+ const struct device_node *np = pdev->dev.of_node;
+ u32 num_cells;
+
+ dev_dbg(&pdev->dev, "PWM supports output inversion\n");
+ ret = of_property_read_u32(np, "#pwm-cells", &num_cells);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "missing property '#pwm-cells'\n");
+ return ret;
+ }
+ if (num_cells == 3) {
+ imx_pwm_ops.set_polarity = imx_pwm_set_polarity;
+ imx->chip.of_xlate = of_pwm_xlate_with_flags;
+ } else if (num_cells != 2) {
+ dev_err(&pdev->dev, "'#pwm-cells' must be <2> or <3>\n");
+ return -EINVAL;
+ }
+ imx->chip.of_pwm_n_cells = num_cells;
+ }
+
imx->config = data->config;
imx->set_enable = data->set_enable;
--
1.7.2.5
^ permalink raw reply related
* [PATCHv2 1/2] pwm: imx: indentation cleanup
From: Lothar Waßmann @ 2014-01-16 8:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389859585-14006-1-git-send-email-LW@KARO-electronics.de>
Consistently use TABs for indentation and the same indentation level.
No functional change.
Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
---
drivers/pwm/pwm-imx.c | 26 +++++++++++++-------------
1 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index cc47733..3b00a82 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -21,24 +21,24 @@
/* i.MX1 and i.MX21 share the same PWM function block: */
-#define MX1_PWMC 0x00 /* PWM Control Register */
-#define MX1_PWMS 0x04 /* PWM Sample Register */
-#define MX1_PWMP 0x08 /* PWM Period Register */
+#define MX1_PWMC 0x00 /* PWM Control Register */
+#define MX1_PWMS 0x04 /* PWM Sample Register */
+#define MX1_PWMP 0x08 /* PWM Period Register */
-#define MX1_PWMC_EN (1 << 4)
+#define MX1_PWMC_EN (1 << 4)
/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
-#define MX3_PWMCR 0x00 /* PWM Control Register */
-#define MX3_PWMSAR 0x0C /* PWM Sample Register */
-#define MX3_PWMPR 0x10 /* PWM Period Register */
-#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
-#define MX3_PWMCR_DOZEEN (1 << 24)
-#define MX3_PWMCR_WAITEN (1 << 23)
+#define MX3_PWMCR 0x00 /* PWM Control Register */
+#define MX3_PWMSAR 0x0C /* PWM Sample Register */
+#define MX3_PWMPR 0x10 /* PWM Period Register */
+#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define MX3_PWMCR_DOZEEN (1 << 24)
+#define MX3_PWMCR_WAITEN (1 << 23)
#define MX3_PWMCR_DBGEN (1 << 22)
-#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
-#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
-#define MX3_PWMCR_EN (1 << 0)
+#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
+#define MX3_PWMCR_EN (1 << 0)
struct imx_chip {
struct clk *clk_per;
--
1.7.2.5
^ permalink raw reply related
* [PATCHv2 0/2] pwm: imx: support polarity inversion
From: Lothar Waßmann @ 2014-01-16 8:06 UTC (permalink / raw)
To: linux-arm-kernel
The first patch does a minor source cleanup without any functional
change.
Changes wrt. v1:
- make PWM_POLARITY flag optional, so that the driver will work
with either the existing DT binding or with support for polarity
inversion.
^ permalink raw reply
* [PATCH V6 3/3] ARM: imx: add suspend in ocram support for i.mx6sl
From: Shawn Guo @ 2014-01-16 7:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389840105-17625-3-git-send-email-b20788@freescale.com>
On Thu, Jan 16, 2014 at 10:41:45AM +0800, Anson Huang wrote:
> @@ -119,6 +120,31 @@
>
> .endm
>
> + .macro reset_mmdc_read_fifo
> +
> + /* reset read FIFO, RST_RD_FIFO */
> + ldr r7, =MX6Q_MMDC_MPDGCTRL0
> + ldr r6, [r11, r7]
> + orr r6, r6, #(1 << 31)
> + str r6, [r11, r7]
> +1:
> + ldr r6, [r11, r7]
> + and r6, r6, #(1 << 31)
> + cmp r6, #0
Use 'ands' to save the 'cmp'.
> + bne 1b
> +
> + /* reset FIFO a second time */
> + ldr r6, [r11, r7]
> + orr r6, r6, #(1 << 31)
> + str r6, [r11, r7]
> +2:
> + ldr r6, [r11, r7]
> + and r6, r6, #(1 << 31)
> + cmp r6, #0
Ditto
> + bne 2b
> +
> + .endm
> +
> ENTRY(imx6_suspend)
> ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
> ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
<snip>
> @@ -286,6 +335,14 @@ resume:
> restore_mmdc_io
>
> ldr r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
> +
> + ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
> + cmp r3, #MXC_CPU_IMX6SL
> + bne dsm_restore_mmdc_io_done
> +
> + reset_mmdc_read_fifo
> +dsm_restore_mmdc_io_done:
> +
> enable_mmdc_access
>
> mov pc, lr
Instead of creating 3 macros, restore_mmdc_io, reset_mmdc_read_fifo and
enable_mmdc_access, I was actually suggesting to do all the mmdc resume
work in one macro. We will need to tell the macro whether we're running
at virtual or physical space. For you reference, the following changes
are what I made on top of yours.
Shawn
---8<-------
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index 570fede..1ba8fc8 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -18,8 +18,8 @@
*
* Better to follow below rules to use ARM registers:
* r0: pm_info structure address;
- * r1 ~ r5: for saving pm_info members;
- * r6 ~ r10: free registers;
+ * r1 ~ r4: for saving pm_info members;
+ * r5 ~ r10: free registers;
* r11: io base address.
*
* suspend ocram space layout:
@@ -87,9 +87,13 @@
.endm
- .macro restore_mmdc_io
+ .macro resume_mmdc
+
+ /* restore MMDC IO */
+ cmp r5, #0
+ ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
+ ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
- /* r11 must be the MMDC IO address before calling it */
ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
add r7, r7, r0
@@ -100,48 +104,45 @@
subs r6, r6, #0x1
bne 1b
- .endm
-
- .macro enable_mmdc_access
+ cmp r5, #0
+ ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
+ ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
- /* let DDR out of self-refresh */
- ldr r7, [r11, #MX6Q_MMDC_MAPSR]
- bic r7, r7, #(1 << 21)
- str r7, [r11, #MX6Q_MMDC_MAPSR]
-
-1:
- ldr r7, [r11, #MX6Q_MMDC_MAPSR]
- ands r7, r7, #(1 << 25)
- bne 1b
- /* enable DDR auto power saving */
- ldr r7, [r11, #MX6Q_MMDC_MAPSR]
- bic r7, r7, #0x1
- str r7, [r11, #MX6Q_MMDC_MAPSR]
-
- .endm
-
- .macro reset_mmdc_read_fifo
+ cmp r3, #MXC_CPU_IMX6SL
+ bne 4f
/* reset read FIFO, RST_RD_FIFO */
ldr r7, =MX6Q_MMDC_MPDGCTRL0
ldr r6, [r11, r7]
orr r6, r6, #(1 << 31)
str r6, [r11, r7]
-1:
+2:
ldr r6, [r11, r7]
- and r6, r6, #(1 << 31)
- cmp r6, #0
- bne 1b
+ ands r6, r6, #(1 << 31)
+ bne 2b
/* reset FIFO a second time */
ldr r6, [r11, r7]
orr r6, r6, #(1 << 31)
str r6, [r11, r7]
-2:
+3:
ldr r6, [r11, r7]
- and r6, r6, #(1 << 31)
- cmp r6, #0
- bne 2b
+ ands r6, r6, #(1 << 31)
+ bne 3b
+
+4:
+ /* let DDR out of self-refresh */
+ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
+ bic r7, r7, #(1 << 21)
+ str r7, [r11, #MX6Q_MMDC_MAPSR]
+5:
+ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
+ ands r7, r7, #(1 << 25)
+ bne 5b
+ /* enable DDR auto power saving */
+ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
+ bic r7, r7, #0x1
+ str r7, [r11, #MX6Q_MMDC_MAPSR]
.endm
@@ -281,8 +282,7 @@ set_mmdc_io_lpm_done:
*/
ldr r6, =2000
rbc_loop:
- sub r6, r6, #0x1
- cmp r6, #0x0
+ subs r6, r6, #0x1
bne rbc_loop
/* Zzz, enter stop mode */
@@ -297,18 +297,8 @@ rbc_loop:
* wakeup source, system should auto
* resume, we need to restore MMDC IO first
*/
- ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
- restore_mmdc_io
-
- ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
-
- cmp r3, #MXC_CPU_IMX6SL
- bne restore_mmdc_io_done
-
- reset_mmdc_read_fifo
-restore_mmdc_io_done:
-
- enable_mmdc_access
+ mov r5, #0
+ resume_mmdc
/* return to suspend finish */
mov pc, lr
@@ -331,19 +321,9 @@ resume:
str r7, [r11, #MX6Q_SRC_GPR1]
str r7, [r11, #MX6Q_SRC_GPR2]
- ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
- restore_mmdc_io
-
- ldr r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
-
ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
- cmp r3, #MXC_CPU_IMX6SL
- bne dsm_restore_mmdc_io_done
-
- reset_mmdc_read_fifo
-dsm_restore_mmdc_io_done:
-
- enable_mmdc_access
+ mov r5, #1
+ resume_mmdc
mov pc, lr
ENDPROC(imx6_suspend)
^ permalink raw reply related
* [PATCH V6 1/3] ARM: imx: add suspend in ocram support for i.mx6q
From: Shawn Guo @ 2014-01-16 7:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389840105-17625-1-git-send-email-b20788@freescale.com>
On Thu, Jan 16, 2014 at 10:41:43AM +0800, Anson Huang wrote:
> +/*
> + * ==================== low level suspend ====================
> + *
> + * Better to follow below rules to use ARM registers:
> + * r0: pm_info structure address;
> + * r1 ~ r5: for saving pm_info members;
The register r5 is free to use now.
> + * r6 ~ r10: free registers;
> + * r11: io base address.
> + *
> + * suspend ocram space layout:
> + * ======================== high address ======================
> + * .
> + * .
> + * .
> + * ^
> + * ^
> + * ^
> + * imx6_suspend code
> + * PM_INFO structure(imx6_cpu_pm_info)
> + * ======================== low address =======================
> + */
<snip>
> + /*
> + * now delay for a short while (3usec)
> + * ARM is at 1GHz at this point
> + * so a short loop should be enough.
> + * this delay is required to ensure that
> + * the RBC counter can start counting in
> + * case an interrupt is already pending
> + * or in case an interrupt arrives just
> + * as ARM is about to assert DSM_request.
> + */
> + ldr r6, =2000
> +rbc_loop:
> + sub r6, r6, #0x1
> + cmp r6, #0x0
Use 'subs' instead to save the 'cmp'.
Shawn
> + bne rbc_loop
^ permalink raw reply
* [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file
From: Mohit KUMAR DCG @ 2014-01-16 7:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201312142002.38423.arnd@arndb.de>
Hi Arnd,
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Sunday, December 15, 2013 12:33 AM
> To: Mohit KUMAR DCG
> Cc: linux-arm-kernel at lists.infradead.org; linux-pci at vger.kernel.org;
> Pratyush ANAND; spear-devel; Viresh Kumar
> Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to
> header file
>
> On Friday 13 December 2013, Mohit KUMAR DCG wrote:
> > > The RST bits should probably go into a drivers/reset driver. Not
> > > sure what the other registers do, but I'm sure we can find a driver
> > > for these too, possibly they should be part of the PHY driver?
> >
> > - Perhaps if we implement phy and reset driver then we may not
> > require to move these definitions and it will address most of your
> > comments on SPEar13xx pcie driver. I am understanding and working on
> > this.l
> >
Though we are almost ready with v2. But few concerns:
There are Spear soc common register used for misc configurations of clock, reset etc for all ips. Few of
registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
We have moved all these sata specific spear1340 configurations in a separate driver. On the basis of spear-ahci dt
Node this driver's probe is called, which further adds ahci platform driver.
We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
The same driver.
Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
Or we keep this new driver in arch/arm/mach-spear only.
Regards
Mohit
>
> Ok, very good.
>
> Arnd
^ permalink raw reply
* [PATCH net-next 0/2] net: mvneta: simple cleanups
From: Willy Tarreau @ 2014-01-16 7:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140115.225451.1012267210637180372.davem@davemloft.net>
On Wed, Jan 15, 2014 at 10:54:51PM -0800, David Miller wrote:
> From: Willy Tarreau <w@1wt.eu>
> Date: Thu, 16 Jan 2014 07:16:15 +0100
>
> > Would you prefer that we resend a complete series with all the patches
> > at once ?
>
> That might, in fact, work much better.
OK I'm resending the whole series now. Thanks.
Willy
^ permalink raw reply
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