* [PATCH REPOST] ARM: Fix incorrect FDT initrd parameter override
From: Rob Herring @ 2014-01-16 16:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <deeb5f$5527t1@icp-osb-irony-out2.iinet.net.au>
On Sat, Jan 11, 2014 at 6:20 PM, <klightspeed@killerwolves.net> wrote:
> Commit 65939301acdb (arm: set initrd_start/initrd_end for fdt scan)
> caused the FDT initrd_start and initrd_end to override the
> phys_initrd_start and phys_initrd_size set by the initrd= kernel
> parameter. With this patch initrd_start and initrd_end will be
> overridden if phys_initrd_start and phys_initrd_size are set by the
> kernel initrd= parameter.
>
> Signed-off-by: Ben Peddell <klightspeed@killerwolves.net>
I'd really like to see phys_initrd_* removed, but that would be more
invasive, so:
Acked-by: Rob Herring <robh@kernel.org>
Please submit to Russell's patch system and mark for stable. I don't
think there is time before 3.13 is released.
Rob
> ---
> arch/arm/mm/init.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> index 1f7b19a..819c539 100644
> --- a/arch/arm/mm/init.c
> +++ b/arch/arm/mm/init.c
> @@ -345,10 +345,11 @@ void __init arm_memblock_init(struct meminfo *mi,
> #endif
> #ifdef CONFIG_BLK_DEV_INITRD
> /* FDT scan will populate initrd_start */
> - if (initrd_start) {
> + if (initrd_start && !phys_initrd_size) {
> phys_initrd_start = __virt_to_phys(initrd_start);
> phys_initrd_size = initrd_end - initrd_start;
> }
> + initrd_start = initrd_end = 0;
> if (phys_initrd_size &&
> !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
> pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n",
> --
> 1.8.3.2
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCHv2 2/2] pwm: imx: support polarity inversion
From: Sascha Hauer @ 2014-01-16 16:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389859585-14006-3-git-send-email-LW@KARO-electronics.de>
On Thu, Jan 16, 2014 at 09:06:25AM +0100, Lothar Wa?mann wrote:
> The i.MX PWM controller supports inverting the polarity of the PWM
> output. Make this feature available in the pxm-imx driver.
>
> Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
> ---
> Documentation/devicetree/bindings/pwm/imx-pwm.txt | 5 +-
> drivers/pwm/pwm-imx.c | 42 +++++++++++++++++++++
> 2 files changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> index b50d7a6d..d0b04b5 100644
> --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> @@ -3,8 +3,9 @@ Freescale i.MX PWM controller
> Required properties:
> - compatible: should be "fsl,<soc>-pwm"
> - reg: physical base address and length of the controller's registers
> -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
> - the cells format.
> +- #pwm-cells: may be 2 for backwards compatibility or 3 to support
> + switching the output polarity. See pwm.txt in this directory for a
> + description of the cells format.
> - interrupts: The interrupt for the pwm controller
>
> Example:
> diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> index 3b00a82..05461bb 100644
> --- a/drivers/pwm/pwm-imx.c
> +++ b/drivers/pwm/pwm-imx.c
> @@ -36,6 +36,7 @@
> #define MX3_PWMCR_DOZEEN (1 << 24)
> #define MX3_PWMCR_WAITEN (1 << 23)
> #define MX3_PWMCR_DBGEN (1 << 22)
> +#define MX3_PWMCR_POUTC (1 << 18)
> #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
> #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
> #define MX3_PWMCR_EN (1 << 0)
> @@ -138,6 +139,9 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
> if (test_bit(PWMF_ENABLED, &pwm->flags))
> cr |= MX3_PWMCR_EN;
>
> + if (pwm->polarity == PWM_POLARITY_INVERSED)
> + cr |= MX3_PWMCR_POUTC;
> +
> writel(cr, imx->mmio_base + MX3_PWMCR);
>
> return 0;
> @@ -155,6 +159,11 @@ static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
> else
> val &= ~MX3_PWMCR_EN;
>
> + if (chip->pwms[0].polarity == PWM_POLARITY_INVERSED)
> + val |= MX3_PWMCR_POUTC;
> + else
> + val &= ~MX3_PWMCR_POUTC;
> +
> writel(val, imx->mmio_base + MX3_PWMCR);
> }
>
> @@ -198,6 +207,17 @@ static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
> clk_disable_unprepare(imx->clk_per);
> }
>
> +static int imx_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
> + enum pwm_polarity polarity)
> +{
> + struct imx_chip *imx = to_imx_chip(chip);
> +
> + dev_dbg(imx->chip.dev, "%s: polarity set to %s\n", __func__,
> + polarity == PWM_POLARITY_INVERSED ? "inverted" : "normal");
> +
> + return 0;
> +}
> +
> static struct pwm_ops imx_pwm_ops = {
> .enable = imx_pwm_enable,
> .disable = imx_pwm_disable,
> @@ -209,6 +229,7 @@ struct imx_pwm_data {
> int (*config)(struct pwm_chip *chip,
> struct pwm_device *pwm, int duty_ns, int period_ns);
> void (*set_enable)(struct pwm_chip *chip, bool enable);
> + unsigned output_polarity:1;
> };
>
> static struct imx_pwm_data imx_pwm_data_v1 = {
> @@ -219,6 +240,7 @@ static struct imx_pwm_data imx_pwm_data_v1 = {
> static struct imx_pwm_data imx_pwm_data_v2 = {
> .config = imx_pwm_config_v2,
> .set_enable = imx_pwm_set_enable_v2,
> + .output_polarity = 1,
> };
>
> static const struct of_device_id imx_pwm_dt_ids[] = {
> @@ -271,6 +293,26 @@ static int imx_pwm_probe(struct platform_device *pdev)
> return PTR_ERR(imx->mmio_base);
>
> data = of_id->data;
> + if (data->output_polarity) {
> + const struct device_node *np = pdev->dev.of_node;
> + u32 num_cells;
> +
> + dev_dbg(&pdev->dev, "PWM supports output inversion\n");
> + ret = of_property_read_u32(np, "#pwm-cells", &num_cells);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "missing property '#pwm-cells'\n");
> + return ret;
> + }
> + if (num_cells == 3) {
> + imx_pwm_ops.set_polarity = imx_pwm_set_polarity;
> + imx->chip.of_xlate = of_pwm_xlate_with_flags;
> + } else if (num_cells != 2) {
> + dev_err(&pdev->dev, "'#pwm-cells' must be <2> or <3>\n");
> + return -EINVAL;
> + }
> + imx->chip.of_pwm_n_cells = num_cells;
> + }
Can't this be done in the PWM core? Right now the PWM core checks for
of_pwm_n_cells before calling ->of_xlate. IMO this check should be done
in the of_xlate hook. Then of_pwm_simple_xlate and
of_pwm_xlate_with_flags can be merged into something like:
static struct pwm_device *
of_pwm_simple_xlate(struct pwm_chip *pc, const struct of_phandle_args
*args)
{
struct pwm_device *pwm;
int ret;
if (pc->of_pwm_n_cells < 2)
return ERR_PTR(-EINVAL);
if (args->args[0] >= pc->npwm)
return ERR_PTR(-EINVAL);
pwm = pwm_request_from_chip(pc, args->args[0], NULL);
if (IS_ERR(pwm))
return pwm;
if (pc->of_pwm_n_cells >= 3) {
if (args->args[2] & PWM_POLARITY_INVERTED)
ret = pwm_set_polarity(pwm, PWM_POLARITY_INVERSED);
else
ret = pwm_set_polarity(pwm, PWM_POLARITY_NORMAL);
if (ret)
return ret;
}
pwm_set_period(pwm, args->args[1]);
return pwm;
}
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH v4 9/9] ARM: DTS: imx5* imx6*, use imx51-ssi
From: Markus Pargmann @ 2014-01-16 15:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1387545096-2334-10-git-send-email-mpa@pengutronix.de>
Hi Shawn,
On Fri, Dec 20, 2013 at 02:11:36PM +0100, Markus Pargmann wrote:
> imx51-ssi and imx21-ssi are different IPs. imx51-ssi supports online
> reconfiguration and needs this for correct interaction with SDMA. This
> patch adds imx51-ssi before each imx21-ssi for all imx5/imx6 SoCs.
>
Mark Brown applied all other patches of this series. Could you please
take this one?
Thanks,
Markus
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH] dma: imx-sdma: remove firmare not found warning
From: Sascha Hauer @ 2014-01-16 15:46 UTC (permalink / raw)
To: linux-arm-kernel
When a firmware cannot be found for the SDMA engine then we can
continue with the inernal ROM firmware.
The meaning of this message is frequently asked for and the usual
answer is that this message is of no relevance, so just make it
dev_dbg() and do not alienate the users anymore.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Vinod Koul <vinod.koul@intel.com>
---
drivers/dma/imx-sdma.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index c75679d..fe57a42 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1259,7 +1259,10 @@ static void sdma_load_firmware(const struct firmware *fw, void *context)
unsigned short *ram_code;
if (!fw) {
- dev_err(sdma->dev, "firmware not found\n");
+ dev_dbg(sdma->dev, "firmware not found\n");
+ /*
+ * In this case we just use the ROM firmware.
+ */
return;
}
--
1.8.5.2
^ permalink raw reply related
* [PATCH] ARM i.MX: remove PWM platform support
From: Sascha Hauer @ 2014-01-16 15:39 UTC (permalink / raw)
To: linux-arm-kernel
As the i.MX pwm driver is devicetree only, remove the platform
support for this device.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-imx21.c | 1 -
arch/arm/mach-imx/clk-imx25.c | 8 ----
arch/arm/mach-imx/clk-imx27.c | 1 -
arch/arm/mach-imx/clk-imx51-imx53.c | 2 -
arch/arm/mach-imx/devices-imx25.h | 4 --
arch/arm/mach-imx/devices-imx51.h | 4 --
arch/arm/mach-imx/devices/Kconfig | 3 --
arch/arm/mach-imx/devices/Makefile | 1 -
arch/arm/mach-imx/devices/devices-common.h | 9 ----
arch/arm/mach-imx/devices/platform-mxc_pwm.c | 69 ----------------------------
10 files changed, 102 deletions(-)
delete mode 100644 arch/arm/mach-imx/devices/platform-mxc_pwm.c
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index d7ed660..bdc2e46 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -149,7 +149,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
- clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0");
clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 69858c7..dc36e6c 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -265,14 +265,6 @@ int __init mx25_clocks_init(void)
clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
- clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0");
- clk_register_clkdev(clk[per10], "per", "mxc_pwm.0");
- clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1");
- clk_register_clkdev(clk[per10], "per", "mxc_pwm.1");
- clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2");
- clk_register_clkdev(clk[per10], "per", "mxc_pwm.2");
- clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3");
- clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index c6b40f3..d2da890 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -231,7 +231,6 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
- clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0");
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index ce37af2..c015e27 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -309,8 +309,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
- clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
- clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index 769563f..61a114c 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -83,7 +83,3 @@ extern const struct imx_spi_imx_data imx25_cspi_data[];
#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
-
-extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[];
-#define imx25_add_mxc_pwm(id) \
- imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
index deee5ba..26389f3 100644
--- a/arch/arm/mach-imx/devices-imx51.h
+++ b/arch/arm/mach-imx/devices-imx51.h
@@ -57,10 +57,6 @@ extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
#define imx51_add_imx2_wdt(id) \
imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
-extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
-#define imx51_add_mxc_pwm(id) \
- imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
-
extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
#define imx51_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 68c74fb..2d260a5 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -67,9 +67,6 @@ config IMX_HAVE_PLATFORM_MXC_MMC
config IMX_HAVE_PLATFORM_MXC_NAND
bool
-config IMX_HAVE_PLATFORM_MXC_PWM
- bool
-
config IMX_HAVE_PLATFORM_MXC_RNGA
bool
select ARCH_HAS_RNGA
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 67416fb..1cbc14c 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index c13b76b..61352a8 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -290,15 +290,6 @@ struct imx_pata_imx_data {
struct platform_device *__init imx_add_pata_imx(
const struct imx_pata_imx_data *data);
-struct imx_mxc_pwm_data {
- int id;
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_mxc_pwm(
- const struct imx_mxc_pwm_data *data);
-
/* mxc_rtc */
struct imx_mxc_rtc_data {
const char *devid;
diff --git a/arch/arm/mach-imx/devices/platform-mxc_pwm.c b/arch/arm/mach-imx/devices/platform-mxc_pwm.c
deleted file mode 100644
index dcd2897..0000000
--- a/arch/arm/mach-imx/devices/platform-mxc_pwm.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \
- { \
- .id = _id, \
- .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \
- .iosize = _size, \
- .irq = soc ## _INT_PWM ## _hwid, \
- }
-#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \
- [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst =
- imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = {
-#define imx25_mxc_pwm_data_entry(_id, _hwid) \
- imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K)
- imx25_mxc_pwm_data_entry(0, 1),
- imx25_mxc_pwm_data_entry(1, 2),
- imx25_mxc_pwm_data_entry(2, 3),
- imx25_mxc_pwm_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst =
- imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = {
-#define imx51_mxc_pwm_data_entry(_id, _hwid) \
- imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K)
- imx51_mxc_pwm_data_entry(0, 1),
- imx51_mxc_pwm_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-struct platform_device *__init imx_add_mxc_pwm(
- const struct imx_mxc_pwm_data *data)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return imx_add_platform_device("mxc_pwm", data->id,
- res, ARRAY_SIZE(res), NULL, 0);
-}
--
1.8.5.2
^ permalink raw reply related
* [PATCH] ARM: moxart: move fixed rate clock child node to board level dts
From: Jonas Jensen @ 2014-01-16 15:39 UTC (permalink / raw)
To: linux-arm-kernel
When a skeleton "clocks { .. }" remain in .dtsi, the child node can
be moved to .dts, "ref12" is then found by of_clk_get().
Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com>
---
Notes:
Applies to next-20140116
arch/arm/boot/dts/moxart-uc7112lx.dts | 8 ++++++++
arch/arm/boot/dts/moxart.dtsi | 6 ------
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts
index 90749d5..10d088d 100644
--- a/arch/arm/boot/dts/moxart-uc7112lx.dts
+++ b/arch/arm/boot/dts/moxart-uc7112lx.dts
@@ -17,6 +17,14 @@
reg = <0x0 0x2000000>;
};
+ clocks {
+ ref12: ref12M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+ };
+
flash at 80000000,0 {
compatible = "numonyx,js28f128", "cfi-flash";
reg = <0x80000000 0x1000000>;
diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi
index da1d8ef..1fd27ed 100644
--- a/arch/arm/boot/dts/moxart.dtsi
+++ b/arch/arm/boot/dts/moxart.dtsi
@@ -26,12 +26,6 @@
clocks {
#address-cells = <1>;
#size-cells = <0>;
-
- ref12: ref12M {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
};
soc {
--
1.8.2.1
^ permalink raw reply related
* [PATCH v2 4/4] ARM:STi: STiH415: Add interrupt support for pin controller
From: srinivas.kandagatla at st.com @ 2014-01-16 15:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389886545-31498-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds interrupt support for STiH415 pin controllers.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih415-pinctrl.dtsi | 75 ++++++++++++++++++++++++++++++++
1 files changed, 75 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index a9324fa..21b3b53 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -7,6 +7,7 @@
* publishhed by the Free Software Foundation.
*/
#include "st-pincfg.h"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
aliases {
@@ -45,35 +46,49 @@
#size-cells = <1>;
compatible = "st,stih415-sbc-pinctrl";
st,syscfg = <&syscfg_sbc>;
+ reg = <0xfe61f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfe610000 0x5000>;
PIO0: gpio at fe610000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO0";
};
PIO1: gpio at fe611000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO1";
};
PIO2: gpio at fe612000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO2";
};
PIO3: gpio at fe613000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x3000 0x100>;
st,bank-name = "PIO3";
};
PIO4: gpio at fe614000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x4000 0x100>;
st,bank-name = "PIO4";
};
@@ -169,53 +184,73 @@
#size-cells = <1>;
compatible = "st,stih415-front-pinctrl";
st,syscfg = <&syscfg_front>;
+ reg = <0xfee0f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfee00000 0x8000>;
PIO5: gpio at fee00000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO5";
};
PIO6: gpio at fee01000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO6";
};
PIO7: gpio at fee02000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO7";
};
PIO8: gpio at fee03000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x3000 0x100>;
st,bank-name = "PIO8";
};
PIO9: gpio at fee04000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x4000 0x100>;
st,bank-name = "PIO9";
};
PIO10: gpio at fee05000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x5000 0x100>;
st,bank-name = "PIO10";
};
PIO11: gpio at fee06000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x6000 0x100>;
st,bank-name = "PIO11";
};
PIO12: gpio at fee07000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x7000 0x100>;
st,bank-name = "PIO12";
};
@@ -244,41 +279,57 @@
#size-cells = <1>;
compatible = "st,stih415-rear-pinctrl";
st,syscfg = <&syscfg_rear>;
+ reg = <0xfe82f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfe820000 0x8000>;
PIO13: gpio at fe820000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO13";
};
PIO14: gpio at fe821000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO14";
};
PIO15: gpio at fe822000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO15";
};
PIO16: gpio at fe823000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x3000 0x100>;
st,bank-name = "PIO16";
};
PIO17: gpio at fe824000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x4000 0x100>;
st,bank-name = "PIO17";
};
PIO18: gpio at fe825000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x5000 0x100>;
st,bank-name = "PIO18";
};
@@ -329,23 +380,33 @@
#size-cells = <1>;
compatible = "st,stih415-left-pinctrl";
st,syscfg = <&syscfg_left>;
+ reg = <0xfd6bf080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfd6b0000 0x3000>;
PIO100: gpio at fd6b0000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO100";
};
PIO101: gpio at fd6b1000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO101";
};
PIO102: gpio at fd6b2000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO102";
};
@@ -356,35 +417,49 @@
#size-cells = <1>;
compatible = "st,stih415-right-pinctrl";
st,syscfg = <&syscfg_right>;
+ reg = <0xfd33f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfd330000 0x5000>;
PIO103: gpio at fd330000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO103";
};
PIO104: gpio at fd331000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO104";
};
PIO105: gpio at fd332000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO105";
};
PIO106: gpio at fd333000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x3000 0x100>;
st,bank-name = "PIO106";
};
PIO107: gpio at fd334000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x4000 0x100>;
st,bank-name = "PIO107";
};
--
1.7.6.5
^ permalink raw reply related
* [PATCH v2 3/4] ARM:STi: STiH416: Add interrupt support for pin controller
From: srinivas.kandagatla at st.com @ 2014-01-16 15:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389886545-31498-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds interrupt support for STiH416 pin controllers.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih416-pinctrl.dtsi | 81 ++++++++++++++++++++++++++++++++
1 files changed, 81 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 74f8cfc..3adbd98 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -8,6 +8,7 @@
* publishhed by the Free Software Foundation.
*/
#include "st-pincfg.h"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
aliases {
@@ -49,41 +50,57 @@
#size-cells = <1>;
compatible = "st,stih416-sbc-pinctrl";
st,syscfg = <&syscfg_sbc>;
+ reg = <0xfe61f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfe610000 0x6000>;
PIO0: gpio at fe610000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO0";
};
PIO1: gpio at fe611000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO1";
};
PIO2: gpio at fe612000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO2";
};
PIO3: gpio at fe613000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x3000 0x100>;
st,bank-name = "PIO3";
};
PIO4: gpio at fe614000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x4000 0x100>;
st,bank-name = "PIO4";
};
PIO40: gpio at fe615000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x5000 0x100>;
st,bank-name = "PIO40";
st,retime-pin-mask = <0x7f>;
@@ -181,65 +198,89 @@
#size-cells = <1>;
compatible = "st,stih416-front-pinctrl";
st,syscfg = <&syscfg_front>;
+ reg = <0xfee0f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfee00000 0x10000>;
PIO5: gpio at fee00000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO5";
};
PIO6: gpio at fee01000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO6";
};
PIO7: gpio at fee02000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO7";
};
PIO8: gpio at fee03000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x3000 0x100>;
st,bank-name = "PIO8";
};
PIO9: gpio at fee04000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x4000 0x100>;
st,bank-name = "PIO9";
};
PIO10: gpio at fee05000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x5000 0x100>;
st,bank-name = "PIO10";
};
PIO11: gpio at fee06000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x6000 0x100>;
st,bank-name = "PIO11";
};
PIO12: gpio at fee07000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x7000 0x100>;
st,bank-name = "PIO12";
};
PIO30: gpio at fee08000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x8000 0x100>;
st,bank-name = "PIO30";
};
PIO31: gpio at fee09000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x9000 0x100>;
st,bank-name = "PIO31";
};
@@ -276,41 +317,57 @@
#size-cells = <1>;
compatible = "st,stih416-rear-pinctrl";
st,syscfg = <&syscfg_rear>;
+ reg = <0xfe82f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfe820000 0x6000>;
PIO13: gpio at fe820000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO13";
};
PIO14: gpio at fe821000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO14";
};
PIO15: gpio at fe822000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO15";
};
PIO16: gpio at fe823000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x3000 0x100>;
st,bank-name = "PIO16";
};
PIO17: gpio at fe824000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x4000 0x100>;
st,bank-name = "PIO17";
};
PIO18: gpio at fe825000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x5000 0x100>;
st,bank-name = "PIO18";
st,retime-pin-mask = <0xf>;
@@ -384,23 +441,33 @@
#size-cells = <1>;
compatible = "st,stih416-fvdp-fe-pinctrl";
st,syscfg = <&syscfg_fvdp_fe>;
+ reg = <0xfd6bf080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfd6b0000 0x3000>;
PIO100: gpio at fd6b0000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO100";
};
PIO101: gpio at fd6b1000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO101";
};
PIO102: gpio at fd6b2000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO102";
};
@@ -411,29 +478,41 @@
#size-cells = <1>;
compatible = "st,stih416-fvdp-lite-pinctrl";
st,syscfg = <&syscfg_fvdp_lite>;
+ reg = <0xfd33f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfd330000 0x5000>;
PIO103: gpio at fd330000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO103";
};
PIO104: gpio at fd331000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x1000 0x100>;
st,bank-name = "PIO104";
};
PIO105: gpio at fd332000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x2000 0x100>;
st,bank-name = "PIO105";
};
PIO106: gpio at fd333000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x3000 0x100>;
st,bank-name = "PIO106";
};
@@ -441,6 +520,8 @@
PIO107: gpio at fd334000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0x4000 0x100>;
st,bank-name = "PIO107";
st,retime-pin-mask = <0xf>;
--
1.7.6.5
^ permalink raw reply related
* [PATCH v2 2/4] pinctrl: st: Add software edge trigger interrupt support.
From: srinivas.kandagatla at st.com @ 2014-01-16 15:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389886545-31498-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
ST pin controller does not have hardware support for detecting edge
triggered interrupts, It only has level triggering support.
This patch attempts to fake up edge triggers from hw level trigger
support in software. With this facility now the gpios can be easily used
for keypads, otherwise it would be difficult for drivers like keypads to
work with level trigger interrupts.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
drivers/pinctrl/pinctrl-st.c | 116 +++++++++++++++++++++++++++++++++++++++++-
1 files changed, 114 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 51e4f3a..9fb66aa 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -271,12 +271,59 @@ struct st_pctl_group {
struct st_pinconf *pin_conf;
};
+/*
+ * Edge triggers are not supported at hardware level, it is supported by
+ * software by exploiting the level trigger support in hardware.
+ * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
+ * of each gpio pin in a GPIO bank.
+ *
+ * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
+ * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
+ *
+ * bit allocation per pin is:
+ * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
+ * --------------------------------------------------------
+ * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
+ * --------------------------------------------------------
+ *
+ * A pin can have one of following the values in its edge configuration field.
+ *
+ * ------- ----------------------------
+ * [0-3] - Description
+ * ------- ----------------------------
+ * 0000 - No edge IRQ.
+ * 0001 - Falling edge IRQ.
+ * 0010 - Rising edge IRQ.
+ * 0011 - Rising and Falling edge IRQ.
+ * ------- ----------------------------
+ */
+
+#define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
+#define ST_IRQ_EDGE_MASK 0xf
+#define ST_IRQ_EDGE_FALLING BIT(0)
+#define ST_IRQ_EDGE_RISING BIT(1)
+#define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
+
+#define ST_IRQ_RISING_EDGE_CONF(pin) \
+ (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
+
+#define ST_IRQ_FALLING_EDGE_CONF(pin) \
+ (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
+
+#define ST_IRQ_BOTH_EDGE_CONF(pin) \
+ (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
+
+#define ST_IRQ_EDGE_CONF(conf, pin) \
+ (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
+
struct st_gpio_bank {
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range range;
void __iomem *base;
struct st_pio_control pc;
struct irq_domain *domain;
+ unsigned long irq_edge_conf;
+ spinlock_t lock;
};
struct st_pinctrl {
@@ -1262,18 +1309,37 @@ static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
unsigned long flags;
int comp, pin = d->hwirq;
u32 val;
+ u32 pin_edge_conf = 0;
switch (type) {
case IRQ_TYPE_LEVEL_HIGH:
comp = 0;
break;
+ case IRQ_TYPE_EDGE_FALLING:
+ comp = 0;
+ pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
+ break;
case IRQ_TYPE_LEVEL_LOW:
comp = 1;
break;
+ case IRQ_TYPE_EDGE_RISING:
+ comp = 1;
+ pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ comp = st_gpio_get(&bank->gpio_chip, pin);
+ pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
+ break;
default:
return -EINVAL;
}
+ spin_lock_irqsave(&bank->lock, flags);
+ bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
+ pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
+ bank->irq_edge_conf |= pin_edge_conf;
+ spin_unlock_irqrestore(&bank->lock, flags);
+
val = readl(bank->base + REG_PIO_PCOMP);
val &= ~BIT(pin);
val |= (comp << pin);
@@ -1282,10 +1348,39 @@ static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
return 0;
}
+/*
+ * As edge triggers are not supported at hardware level, it is supported by
+ * software by exploiting the level trigger support in hardware.
+ *
+ * Steps for detection raising edge interrupt in software.
+ *
+ * Step 1: CONFIGURE pin to detect level LOW interrupts.
+ *
+ * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
+ * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
+ * IGNORE calling the actual interrupt handler for the pin@this stage.
+ *
+ * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
+ * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
+ * DISPATCH the interrupt to the interrupt handler of the pin.
+ *
+ * step-1 ________ __________
+ * | | step - 3
+ * | |
+ * step -2 |_____|
+ *
+ * falling edge is also detected int the same way.
+ *
+ */
static void __gpio_irq_handler(struct st_gpio_bank *bank)
{
unsigned long port_in, port_mask, port_comp, active_irqs;
- int n;
+ unsigned long bank_edge_mask, flags;
+ int n, val, ecfg;
+
+ spin_lock_irqsave(&bank->lock, flags);
+ bank_edge_mask = bank->irq_edge_conf;
+ spin_unlock_irqrestore(&bank->lock, flags);
for (;;) {
port_in = readl(bank->base + REG_PIO_PIN);
@@ -1298,6 +1393,22 @@ static void __gpio_irq_handler(struct st_gpio_bank *bank)
break;
for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
+ /* check if we are detecting fake edges ... */
+ ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
+
+ if (ecfg) {
+ /* edge detection. */
+ val = st_gpio_get(&bank->gpio_chip, n);
+
+ writel(BIT(n),
+ val ? bank->base + REG_PIO_SET_PCOMP :
+ bank->base + REG_PIO_CLR_PCOMP);
+
+ if (ecfg != ST_IRQ_EDGE_BOTH &&
+ !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
+ continue;
+ }
+
generic_handle_irq(irq_find_mapping(bank->domain, n));
}
}
@@ -1359,7 +1470,7 @@ static int st_gpio_irq_domain_map(struct irq_domain *h,
struct st_gpio_bank *bank = h->host_data;
irq_set_chip(virq, &st_gpio_irqchip);
- irq_set_handler(virq, handle_level_irq);
+ irq_set_handler(virq, handle_simple_irq);
set_irq_flags(virq, IRQF_VALID);
irq_set_chip_data(virq, bank);
@@ -1392,6 +1503,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
bank->gpio_chip.of_node = np;
+ spin_lock_init(&bank->lock);
of_property_read_string(np, "st,bank-name", &range->name);
bank->gpio_chip.label = range->name;
--
1.7.6.5
^ permalink raw reply related
* [PATCH v2 1/4] pinctrl: st: Add Interrupt support.
From: srinivas.kandagatla at st.com @ 2014-01-16 15:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389886545-31498-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch add interrupt support to the pincontroller driver.
ST Pincontroller GPIO bank can have one of the two possible types of
interrupt-wirings.
First type is via irqmux, single interrupt is used by multiple gpio
banks. This reduces number of overall interrupts numbers required. All
these banks belong to a single pincontroller.
_________
| |----> [gpio-bank (n) ]
| |----> [gpio-bank (n + 1)]
[irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
| |----> [gpio-bank (... )]
|_________|----> [gpio-bank (n + 7)]
Second type has a dedicated interrupt per gpio bank.
[irqN]----> [gpio-bank (n)]
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
.../devicetree/bindings/pinctrl/pinctrl-st.txt | 73 ++++++-
drivers/pinctrl/pinctrl-st.c | 225 +++++++++++++++++++-
2 files changed, 290 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
index 05bf82a..4bd5be0 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
@@ -11,18 +11,68 @@ Pull Up (PU) are driven by the related PIO block.
ST pinctrl driver controls PIO multiplexing block and also interacts with
gpio driver to configure a pin.
-Required properties: (PIO multiplexing block)
+GPIO bank can have one of the two possible types of interrupt-wirings.
+
+First type is via irqmux, single interrupt is used by multiple gpio banks. This
+reduces number of overall interrupts numbers required. All these banks belong to
+a single pincontroller.
+ _________
+ | |----> [gpio-bank (n) ]
+ | |----> [gpio-bank (n + 1)]
+ [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
+ | |----> [gpio-bank (... )]
+ |_________|----> [gpio-bank (n + 7)]
+
+Second type has a dedicated interrupt per gpio bank.
+
+ [irqN]----> [gpio-bank (n)]
+
+
+Pin controller node:
+Required properties:
- compatible : should be "st,<SOC>-<pio-block>-pinctrl"
like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
-- gpio-controller : Indicates this device is a GPIO controller
-- #gpio-cells : Should be one. The first cell is the pin number.
+- st,syscfg : Should be a phandle of the syscfg node.
- st,retime-pin-mask : Should be mask to specify which pins can be retimed.
If the property is not present, it is assumed that all the pins in the
bank are capable of retiming. Retiming is mainly used to improve the
IO timing margins of external synchronous interfaces.
-- st,bank-name : Should be a name string for this bank as
- specified in datasheet.
-- st,syscfg : Should be a phandle of the syscfg node.
+- ranges : defines mapping between pin controller node (parent) to gpio-bank
+ node (children).
+
+Optional properties:
+- interrupts : Interrupt number of the irqmux. If the interrupt is shared
+ with other gpio banks via irqmux.
+ a irqline and gpio banks.
+- reg : irqmux memory resource. If irqmux is present.
+- reg-names : irqmux resource should be named as "irqmux".
+
+GPIO controller/bank node.
+Required properties:
+- gpio-controller : Indicates this device is a GPIO controller
+- #gpio-cells : Should be one. The first cell is the pin number.
+- st,bank-name : Should be a name string for this bank as specified in
+ datasheet.
+
+Optional properties:
+- interrupts : Interrupt number for this gpio bank. If there is a dedicated
+ interrupt wired up for this gpio bank.
+
+- interrupt-controller : Indicates this device is a interrupt controller. GPIO
+ bank can be an interrupt controller iff one of the interrupt type either via
+irqmux or a dedicated interrupt per bank is specified.
+
+- #interrupt-cells: the value of this property should be 2.
+ - First Cell: represents the external gpio interrupt number local to the
+ gpio interrupt space of the controller.
+ - Second Cell: flags to identify the type of the interrupt
+ - 1 = rising edge triggered
+ - 2 = falling edge triggered
+ - 3 = rising and falling edge triggered
+ - 4 = high level triggered
+ - 8 = low level triggered
+for related macros look in:
+include/dt-bindings/interrupt-controller/irq.h
Example:
pin-controller-sbc {
@@ -30,10 +80,17 @@ Example:
#size-cells = <1>;
compatible = "st,stih415-sbc-pinctrl";
st,syscfg = <&syscfg_sbc>;
+ reg = <0xfe61f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfe610000 0x5000>;
+
PIO0: gpio at fe610000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO0";
};
@@ -105,6 +162,10 @@ pin-controller {
sdhci0:sdhci at fe810000{
...
+ interrupt-parent = <&PIO3>;
+ #interrupt-cells = <2>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
+ interrupts-names = "card-detect";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc>;
};
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 320c273..51e4f3a 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -13,7 +13,12 @@
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdesc.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/of.h>
+#include <linux/of_irq.h>
#include <linux/of_gpio.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
@@ -271,6 +276,7 @@ struct st_gpio_bank {
struct pinctrl_gpio_range range;
void __iomem *base;
struct st_pio_control pc;
+ struct irq_domain *domain;
};
struct st_pinctrl {
@@ -284,6 +290,7 @@ struct st_pinctrl {
int ngroups;
struct regmap *regmap;
const struct st_pctl_data *data;
+ void __iomem *irqmux_base;
};
/* SOC specific data */
@@ -1200,6 +1207,130 @@ static int st_pctl_parse_functions(struct device_node *np,
return 0;
}
+static int st_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct st_gpio_bank *bank = gpio_chip_to_bank(chip);
+ int irq = -ENXIO;
+
+ if (offset < chip->ngpio)
+ irq = irq_find_mapping(bank->domain, offset);
+
+ dev_info(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
+ chip->label, offset + chip->base, irq);
+ return irq;
+}
+
+static void st_gpio_irq_mask(struct irq_data *d)
+{
+ struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+
+ writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
+}
+
+static void st_gpio_irq_unmask(struct irq_data *d)
+{
+ struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+
+ writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
+}
+
+static unsigned int st_gpio_irq_startup(struct irq_data *d)
+{
+ struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+
+ if (gpio_lock_as_irq(&bank->gpio_chip, d->hwirq))
+ dev_err(bank->gpio_chip.dev,
+ "unable to lock HW IRQ %lu for IRQ\n",
+ d->hwirq);
+
+ st_gpio_irq_unmask(d);
+
+ return 0;
+}
+
+static void st_gpio_irq_shutdown(struct irq_data *d)
+{
+ struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+
+ st_gpio_irq_mask(d);
+ gpio_unlock_as_irq(&bank->gpio_chip, d->hwirq);
+}
+
+static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
+{
+ struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
+ unsigned long flags;
+ int comp, pin = d->hwirq;
+ u32 val;
+
+ switch (type) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ comp = 0;
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ comp = 1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ val = readl(bank->base + REG_PIO_PCOMP);
+ val &= ~BIT(pin);
+ val |= (comp << pin);
+ writel(val, bank->base + REG_PIO_PCOMP);
+
+ return 0;
+}
+
+static void __gpio_irq_handler(struct st_gpio_bank *bank)
+{
+ unsigned long port_in, port_mask, port_comp, active_irqs;
+ int n;
+
+ for (;;) {
+ port_in = readl(bank->base + REG_PIO_PIN);
+ port_comp = readl(bank->base + REG_PIO_PCOMP);
+ port_mask = readl(bank->base + REG_PIO_PMASK);
+
+ active_irqs = (port_in ^ port_comp) & port_mask;
+
+ if (active_irqs == 0)
+ break;
+
+ for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
+ generic_handle_irq(irq_find_mapping(bank->domain, n));
+ }
+ }
+}
+
+static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+ /* interrupt dedicated per bank */
+ struct irq_chip *chip = irq_get_chip(irq);
+ struct st_gpio_bank *bank = irq_get_handler_data(irq);
+
+ chained_irq_enter(chip, desc);
+ __gpio_irq_handler(bank);
+ chained_irq_exit(chip, desc);
+}
+
+static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_get_chip(irq);
+ struct st_pinctrl *info = irq_get_handler_data(irq);
+ unsigned long status;
+ int n;
+
+ chained_irq_enter(chip, desc);
+
+ status = readl(info->irqmux_base);
+
+ for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK)
+ __gpio_irq_handler(&info->banks[n]);
+
+ chained_irq_exit(chip, desc);
+}
+
static struct gpio_chip st_gpio_template = {
.request = st_gpio_request,
.free = st_gpio_free,
@@ -1210,6 +1341,34 @@ static struct gpio_chip st_gpio_template = {
.ngpio = ST_GPIO_PINS_PER_BANK,
.of_gpio_n_cells = 1,
.of_xlate = st_gpio_xlate,
+ .to_irq = st_gpio_to_irq,
+};
+
+static struct irq_chip st_gpio_irqchip = {
+ .name = "GPIO",
+ .irq_mask = st_gpio_irq_mask,
+ .irq_unmask = st_gpio_irq_unmask,
+ .irq_set_type = st_gpio_irq_set_type,
+ .irq_startup = st_gpio_irq_startup,
+ .irq_shutdown = st_gpio_irq_shutdown,
+};
+
+static int st_gpio_irq_domain_map(struct irq_domain *h,
+ unsigned int virq, irq_hw_number_t hw)
+{
+ struct st_gpio_bank *bank = h->host_data;
+
+ irq_set_chip(virq, &st_gpio_irqchip);
+ irq_set_handler(virq, handle_level_irq);
+ set_irq_flags(virq, IRQF_VALID);
+ irq_set_chip_data(virq, bank);
+
+ return 0;
+}
+
+static struct irq_domain_ops st_gpio_irq_ops = {
+ .map = st_gpio_irq_domain_map,
+ .xlate = irq_domain_xlate_twocell,
};
static int st_gpiolib_register_bank(struct st_pinctrl *info,
@@ -1219,8 +1378,8 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
struct pinctrl_gpio_range *range = &bank->range;
struct device *dev = info->dev;
int bank_num = of_alias_get_id(np, "gpio");
- struct resource res;
- int err;
+ struct resource res, irq_res;
+ int gpio_irq = 0, err, i;
if (of_address_to_resource(np, 0, &res))
return -ENODEV;
@@ -1248,6 +1407,51 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
}
dev_info(dev, "%s bank added.\n", range->name);
+ /**
+ * GPIO bank can have one of the two possible types of
+ * interrupt-wirings.
+ *
+ * First type is via irqmux, single interrupt is used by multiple
+ * gpio banks. This reduces number of overall interrupts numbers
+ * required. All these banks belong to a single pincontroller.
+ * _________
+ * | |----> [gpio-bank (n) ]
+ * | |----> [gpio-bank (n + 1)]
+ * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
+ * | |----> [gpio-bank (... )]
+ * |_________|----> [gpio-bank (n + 7)]
+ *
+ * Second type has a dedicated interrupt per each gpio bank.
+ *
+ * [irqN]----> [gpio-bank (n)]
+ */
+
+ if (!of_irq_to_resource(np, 0, &irq_res)) {
+ gpio_irq = irq_res.start;
+ irq_set_chained_handler(gpio_irq, st_gpio_irq_handler);
+ irq_set_handler_data(gpio_irq, bank);
+ }
+
+ if (info->irqmux_base > 0 || gpio_irq > 0) {
+ /* Setup IRQ domain */
+ bank->domain = irq_domain_add_linear(np,
+ ST_GPIO_PINS_PER_BANK,
+ &st_gpio_irq_ops, bank);
+ if (!bank->domain) {
+ dev_err(dev, "Failed to add irq domain for %s\n",
+ np->full_name);
+ } else {
+ for (i = 0; i < ST_GPIO_PINS_PER_BANK; i++) {
+ if (irq_create_mapping(bank->domain, i) < 0)
+ dev_err(dev,
+ "Failed to map IRQ %i\n", i);
+ }
+ }
+
+ } else {
+ dev_info(dev, "No IRQ support for %s bank\n", np->full_name);
+ }
+
return 0;
}
@@ -1276,6 +1480,8 @@ static int st_pctl_probe_dt(struct platform_device *pdev,
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
int grp_index = 0;
+ int irq = 0;
+ struct resource *res;
st_pctl_dt_child_count(info, np);
if (!info->nbanks) {
@@ -1306,6 +1512,21 @@ static int st_pctl_probe_dt(struct platform_device *pdev,
}
info->data = of_match_node(st_pctl_of_match, np)->data;
+ irq = platform_get_irq(pdev, 0);
+
+ if (irq > 0) {
+ res = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, "irqmux");
+ info->irqmux_base = devm_ioremap_resource(&pdev->dev, res);
+
+ if (IS_ERR(info->irqmux_base))
+ return PTR_ERR(info->irqmux_base);
+
+ irq_set_chained_handler(irq, st_gpio_irqmux_handler);
+ irq_set_handler_data(irq, info);
+
+ }
+
pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
pdesc = devm_kzalloc(&pdev->dev,
sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL);
--
1.7.6.5
^ permalink raw reply related
* [PATCH v4 net-next 2/4] sh_eth: Add support for r7s72100
From: Sergei Shtylyov @ 2014-01-16 15:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140116004943.GF12550@verge.net.au>
Hello.
On 16-01-2014 4:49, Simon Horman wrote:
>>>>> This is a fast ethernet controller.
>>>>> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>>>> [...]
>>>>> diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
>>>>> index 4b38533..cc6d4af 100644
>>>>> --- a/drivers/net/ethernet/renesas/sh_eth.c
>>>>> +++ b/drivers/net/ethernet/renesas/sh_eth.c
>>>>> @@ -190,6 +190,59 @@ static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
>> [...]
>>>>> @@ -701,6 +762,35 @@ static struct sh_eth_cpu_data r8a7740_data = {
>>>>> .shift_rd0 = 1,
>>>>> };
>>>>>
>>>>> +/* R7S72100 */
>>>>> +static struct sh_eth_cpu_data r7s72100_data = {
>>>>> + .chip_reset = sh_eth_chip_reset,
>>>>> + .set_duplex = sh_eth_set_duplex,
>>>>> +
>>>>> + .register_type = SH_ETH_REG_FAST_RZ,
>>>>> +
>>>>> + .ecsr_value = ECSR_ICD,
>>>>> + .ecsipr_value = ECSIPR_ICDIP,
>>>>> + .eesipr_value = 0xff7f009f,
>>>>> +
>>>>> + .tx_check = EESR_TC1 | EESR_FTC,
>>>>> + .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
>>>>> + EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
>>>>> + EESR_TDE | EESR_ECI,
>>>>> + .fdr_value = 0x0000070f,
>>>>> + .rmcr_value = RMCR_RNC,
>>>>> +
>>>>> + .apr = 1,
>>>>> + .mpr = 1,
>>>>> + .tpauser = 1,
>>>>> + .hw_swap = 1,
>>>>> + .rpadir = 1,
>>>>> + .rpadir_value = 2 << 16,
>>>>> + .no_trimd = 1,
>>>>> + .tsu = 1,
>>>>> + .shift_rd0 = 1,
>>
>>>> Perhaps this field should be renamed to something talking about
>>>> check summing support (since bits 0..15 of RD0 contain a frame check
>>>> sum for those SoCs). Or maybe it should be just merged with the
>>>> 'hw_crc' field...
>>> I have no feelings about that one way or another.
>> Do you happen to have R8A7740 manual by chance? If so, does it
>> talk about RX check summing support and using RD0 for that?
> Yes and yes.
> I have taken a quick look and the documentation for RX checksumming on the
> R8A7740 appears to be very similar if not the same as that of the R7S72100.
> In particular both refer to using the bottom 16 bits of RD0 as
> containing the packet checksum.
OK, now if you had SH7734 manual to completely confirm that check sum is
stored in the same place there... most probably it is, of course, and we
should merge 'hw_crc' and 'shift_rd0' into a single field.
[...]
>>>>> diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
>>>>> index 0fe35b7..0bcde90 100644
>>>>> --- a/drivers/net/ethernet/renesas/sh_eth.h
>>>>> +++ b/drivers/net/ethernet/renesas/sh_eth.h
>> [...]
>>>>> @@ -191,6 +192,7 @@ enum DMAC_M_BIT {
>>>>> /* EDTRR */
>>>>> enum DMAC_T_BIT {
>>>>> EDTRR_TRNS_GETHER = 0x03,
>>>>> + EDTRR_TRNS_RZ_ETHER = 0x03,
>>>> I doubt we need a special case here. You didn't introduce one for
>>>> the software reset bits.
>>> True, but RZ is not Gigabit. So I think we either need two names
>>> or to choose a more generic name.
>> Well, R7S72100 manual calls these bits just TR[1:0]. Don't know
>> what SoCs having Gigabit call it in the manuals...
>>>>> EDTRR_TRNS_ETHER = 0x01,
>> R-Car manuals seem to call the bit TRNS (as well as the
>> prehistoric SH manuals probably). Perhaps we could use that
>> difference, TRNS vs TR, don't know...
> Perhaps we should just leave it as-is, using EDTRR_TRNS_GETHER and
> EDTRR_TRNS_RZ_ETHER, after all.
No, I liked your last version more. At least it's more consistent, not
adding separate values for either TR[1:0] or soft reset bits.
> At least until we can think of a better names :)
I doubt we can come up with something better.
WBR, Sergei
^ permalink raw reply
* [PATCH v2 0/4] pinctrl: st: Add interrupt controller support.
From: srinivas.kandagatla at st.com @ 2014-01-16 15:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389711077-20949-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Hi Linus W,
Thankyou for reviewing v1 of the patch-set the comments were very useful.
This series of v2 patches add interrupt controller support to ST pinctrl
driver incorporating all the review comments.
ST pin controller GPIO bank can have one of the two possible types of
interrupt-wirings.
First type is via irqmux, single interrupt is used by multiple gpio
banks. This reduces number of interrupts numbers required by pin controller.
All these gpio banks belong to a single pin controller.
Second type has a dedicated interrupt per gpio bank. Interrupt number usage is
very high in this case.
This patch adds support to both these wirings.
Also, ST pin controller hardware only supports level triggered interrupts.
However for drivers like gpio keypad requires edge trigger interrupt support,
so one of the patch adds edge trigger interrupt support in software by using
the existing level trigger support in hardware.
Patch 01: Adds level interrupt support to pin controller.
Patch 02 Adds software edge trigger support.
Patch 03,04 : Updates STiH415, STiH416 dts files for interrupt support.
Changes since v1:
Updated below changes suggest by Linus W.
- Added updated example in binding document.
- removed un-necessary varibles in st_gpio_bank and st_pinctrl struct.
- renamed irq disabled/enabled functions with masked/unmasked
functions.
- Fixed a issue in interrupt handler which could miss interrupts.
- Added new hooks startup and shutdown which can mark gpio lines.
- create irq mapping at probe stage instead of doing it in to_irq.
- removed driver specfic irq_domain xlate function with generic one.
- Added extra documention for software edge trigger support.
- reformated few debug messages.
I did skip the first patch from my last v1 patchset as you have already
applied it.
Thanks,
srini
Srinivas Kandagatla (4):
pinctrl: st: Add Interrupt support.
pinctrl: st: Add software edge trigger interrupt support.
ARM:STi: STiH416: Add interrupt support for pin controller
ARM:STi: STiH415: Add interrupt support for pin controller
.../devicetree/bindings/pinctrl/pinctrl-st.txt | 73 ++++-
arch/arm/boot/dts/stih415-pinctrl.dtsi | 75 +++++
arch/arm/boot/dts/stih416-pinctrl.dtsi | 81 +++++
drivers/pinctrl/pinctrl-st.c | 337 +++++++++++++++++++-
4 files changed, 558 insertions(+), 8 deletions(-)
--
1.7.6.5
^ permalink raw reply
* [PATCH] ARM: at91/dt: fix sama5d3 ohci hclk clock reference
From: Boris BREZILLON @ 2014-01-16 15:25 UTC (permalink / raw)
To: linux-arm-kernel
The hclk clock of the ohci node is referencing udphs_clk instead of
uhphs_clk.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
---
arch/arm/boot/dts/sama5d3.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index e398e5d..31356e2 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1195,7 +1195,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
+ clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
<&uhpck>;
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
--
1.7.9.5
^ permalink raw reply related
* [PATCH v6 net-next 1/4] sh_eth: Use bool as return type of sh_eth_is_gether()
From: Sergei Shtylyov @ 2014-01-16 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389839656-10932-2-git-send-email-horms+renesas@verge.net.au>
Hello.
On 16-01-2014 6:34, Simon Horman wrote:
> Return a boolean and use true and false.
You're not using them explicitly anymore. I'd update the changelog
with converting the function to one-liner.
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
WBR, Sergei
^ permalink raw reply
* [PATCH] ARM: orion: provide C-style interrupt handler for MULTI_IRQ_HANDLER
From: Andrew Lunn @ 2014-01-16 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389859831-9883-1-git-send-email-sebastian.hesselbarth@gmail.com>
On Thu, Jan 16, 2014 at 09:10:31AM +0100, Sebastian Hesselbarth wrote:
> DT-enabled Marvell Kirkwood and Dove SoCs make use of an irqchip
> driver. As expected for irqchip drivers, it uses a C-style
> interrupt handler and therefore selects MULTI_IRQ_HANDLER.
>
> Now, compiling a kernel with both non-DT and DT support enabled,
> selecting MULTI_IRQ_HANDLER will break ASM irq handler used by
> non-DT boards.
>
> Therefore, we provide a C-style irq handler even for non-DT boards,
> if MULTI_IRQ_HANDLER is set. By installing the C-style irq handler
> in orion_irq_init this is transparent to all non-DT board files.
>
> While the regression report was filed on Marvell Kirkwood, also
> Marvell Dove non-DT boards are affected and fixed by this patch.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Tested-by: Ian Campbell <ijc@hellion.org.uk>
> Reported-by: Ian Campbell <ijc@hellion.org.uk>
> Fixes: 2326f04321a9 ("ARM: kirkwood: convert to DT irqchip and clocksource")
> Fixes: f07d73e33d0e ("ARM: dove: convert to DT irqchip and clocksource")
Hi Sebastian
Makes sense and this version is much better than the previous.
Acked-by: Andrew Lunn <andrew@lunn.ch>
Andrew
> ---
> Compared to the two patch version sent on Ian's regression report,
> I cooked this down to a single patch only touching plat-orion/irq.c.
> I also dropped Orion5x and MV78x00, as they not yet select MULTI_IRQ_HANDLER
> at all. Instead I added a comment about taking care of them, as soon as
> they move over to an irqchip driver themselves.
>
> I have not yet Cc'ed this patch to -stable to get some discussion and
> an Acked-by from Jason or Andrew, too.
>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Ian Campbell <ijc@hellion.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
> arch/arm/plat-orion/irq.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
> index c492e1b3dfdb..807df142444b 100644
> --- a/arch/arm/plat-orion/irq.c
> +++ b/arch/arm/plat-orion/irq.c
> @@ -15,8 +15,51 @@
> #include <linux/io.h>
> #include <linux/of_address.h>
> #include <linux/of_irq.h>
> +#include <asm/exception.h>
> #include <plat/irq.h>
> #include <plat/orion-gpio.h>
> +#include <mach/bridge-regs.h>
> +
> +#ifdef CONFIG_MULTI_IRQ_HANDLER
> +/*
> + * Compiling with both non-DT and DT support enabled, will
> + * break asm irq handler used by non-DT boards. Therefore,
> + * we provide a C-style irq handler even for non-DT boards,
> + * if MULTI_IRQ_HANDLER is set.
> + *
> + * Notes:
> + * - this is prepared for Kirkwood and Dove only, update
> + * accordingly if you add Orion5x or MV78x00.
> + * - Orion5x uses different macro names and has only one
> + * set of CAUSE/MASK registers.
> + * - MV78x00 uses the same macro names but has a third
> + * set of CAUSE/MASK registers.
> + *
> + */
> +
> +static void __iomem *orion_irq_base = IRQ_VIRT_BASE;
> +
> +asmlinkage void
> +__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs)
> +{
> + u32 stat;
> +
> + stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF);
> + stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF);
> + if (stat) {
> + unsigned int hwirq = __fls(stat);
> + handle_IRQ(hwirq, regs);
> + return;
> + }
> + stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF);
> + stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF);
> + if (stat) {
> + unsigned int hwirq = 32 + __fls(stat);
> + handle_IRQ(hwirq, regs);
> + return;
> + }
> +}
> +#endif
>
> void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
> {
> @@ -35,6 +78,10 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
> ct->chip.irq_unmask = irq_gc_mask_set_bit;
> irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
> IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
> +
> +#ifdef CONFIG_MULTI_IRQ_HANDLER
> + set_handle_irq(orion_legacy_handle_irq);
> +#endif
> }
>
> #ifdef CONFIG_OF
> --
> 1.8.5.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] clk: turn rate change failed warning into pr_debug
From: Sascha Hauer @ 2014-01-16 15:12 UTC (permalink / raw)
To: linux-arm-kernel
If a rate change failed it's the opportunity of the caller to handle
this. Do not spam the log with a message.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/clk/clk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 2cf2ea6..f0124d4 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1460,7 +1460,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
/* notify that we are about to change rates */
fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
if (fail_clk) {
- pr_warn("%s: failed to set %s rate\n", __func__,
+ pr_debug("%s: failed to set %s rate\n", __func__,
fail_clk->name);
clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
ret = -EBUSY;
--
1.8.5.2
^ permalink raw reply related
* [PATCH] pwm: Remove obsolete HAVE_PWM Kconfig symbol
From: Sascha Hauer @ 2014-01-16 15:01 UTC (permalink / raw)
To: linux-arm-kernel
Before we had the PWM framework we used to have a barebone PWM api. The
HAVE_PWM Kconfig symbol used to be selected by the PWM drivers to specify
the PWM API is present in the kernel. Since the last legacy driver is gone
the HAVE_PWM symbol can go aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
I suggest that Thierry as PWM Maintainer takes the patch through his tree.
Is that ok for you Thierry?
arch/arm/Kconfig | 4 ----
arch/arm/mach-pxa/Kconfig | 15 ---------------
arch/mips/Kconfig | 1 -
drivers/input/misc/Kconfig | 4 ++--
include/linux/pwm.h | 2 +-
5 files changed, 3 insertions(+), 23 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c1f1a7e..1b6f499 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -109,9 +109,6 @@ config ARM_DMA_IOMMU_ALIGNMENT
endif
-config HAVE_PWM
- bool
-
config MIGHT_HAVE_PCI
bool
@@ -606,7 +603,6 @@ config ARCH_LPC32XX
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select HAVE_IDE
- select HAVE_PWM
select USB_ARCH_HAS_OHCI
select USE_OF
help
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 96100db..b96244c 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -7,7 +7,6 @@ comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
config MACH_PXA3XX_DT
bool "Support PXA3xx platforms from device tree"
select CPU_PXA300
- select HAVE_PWM
select POWER_SUPPLY
select PXA3xx
select USE_OF
@@ -23,12 +22,10 @@ config ARCH_LUBBOCK
config MACH_MAINSTONE
bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
- select HAVE_PWM
select PXA27x
config MACH_ZYLONITE
bool
- select HAVE_PWM
select PXA3xx
config MACH_ZYLONITE300
@@ -69,7 +66,6 @@ config ARCH_PXA_IDP
config ARCH_VIPER
bool "Arcom/Eurotech VIPER SBC"
select ARCOM_PCMCIA
- select HAVE_PWM
select I2C_GPIO
select ISA
select PXA25x
@@ -120,7 +116,6 @@ config MACH_CM_X300
bool "CompuLab CM-X300 modules"
select CPU_PXA300
select CPU_PXA310
- select HAVE_PWM
select PXA3xx
config MACH_CAPC7117
@@ -211,7 +206,6 @@ config TRIZEPS_PCMCIA
config MACH_LOGICPD_PXA270
bool "LogicPD PXA270 Card Engine Development Platform"
- select HAVE_PWM
select PXA27x
config MACH_PCM027
@@ -222,7 +216,6 @@ config MACH_PCM027
config MACH_PCM990_BASEBOARD
bool "PHYTEC PCM-990 development board"
depends on MACH_PCM027
- select HAVE_PWM
choice
prompt "display on pcm990"
@@ -246,7 +239,6 @@ config MACH_COLIBRI
config MACH_COLIBRI_PXA270_INCOME
bool "Income s.r.o. PXA270 SBC"
depends on MACH_COLIBRI
- select HAVE_PWM
select PXA27x
config MACH_COLIBRI300
@@ -275,7 +267,6 @@ comment "End-user Products (sorted by vendor name)"
config MACH_H4700
bool "HP iPAQ hx4700"
- select HAVE_PWM
select IWMMXT
select PXA27x
@@ -289,14 +280,12 @@ config MACH_HIMALAYA
config MACH_MAGICIAN
bool "Enable HTC Magician Support"
- select HAVE_PWM
select IWMMXT
select PXA27x
config MACH_MIOA701
bool "Mitac Mio A701 Support"
select GPIO_SYSFS
- select HAVE_PWM
select IWMMXT
select PXA27x
help
@@ -306,7 +295,6 @@ config MACH_MIOA701
config PXA_EZX
bool "Motorola EZX Platform"
- select HAVE_PWM
select IWMMXT
select PXA27x
@@ -346,7 +334,6 @@ config MACH_MP900C
config ARCH_PXA_PALM
bool "PXA based Palm PDAs"
- select HAVE_PWM
config MACH_PALM27X
bool
@@ -444,7 +431,6 @@ config MACH_TREO680
config MACH_RAUMFELD_RC
bool "Raumfeld Controller"
select CPU_PXA300
- select HAVE_PWM
select POWER_SUPPLY
select PXA3xx
@@ -608,7 +594,6 @@ config MACH_E800
config MACH_ZIPIT2
bool "Zipit Z2 Handheld"
- select HAVE_PWM
select PXA27x
endmenu
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 650de39..ce62af8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -233,7 +233,6 @@ config MACH_JZ4740
select IRQ_CPU
select ARCH_REQUIRE_GPIOLIB
select SYS_HAS_EARLY_PRINTK
- select HAVE_PWM
select HAVE_CLK
select GENERIC_IRQ_CHIP
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 5f4967d..bc6ec8e 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -156,7 +156,7 @@ config INPUT_MAX8925_ONKEY
config INPUT_MAX8997_HAPTIC
tristate "MAXIM MAX8997 haptic controller support"
- depends on PWM && HAVE_PWM && MFD_MAX8997
+ depends on PWM && MFD_MAX8997
select INPUT_FF_MEMLESS
help
This option enables device driver support for the haptic controller
@@ -461,7 +461,7 @@ config INPUT_PCF8574
config INPUT_PWM_BEEPER
tristate "PWM beeper support"
- depends on PWM && HAVE_PWM
+ depends on PWM
help
Say Y here to get support for PWM based beeper devices.
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index f0feafd..4717f54 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -7,7 +7,7 @@
struct pwm_device;
struct seq_file;
-#if IS_ENABLED(CONFIG_PWM) || IS_ENABLED(CONFIG_HAVE_PWM)
+#if IS_ENABLED(CONFIG_PWM)
/*
* pwm_request - request a PWM device
*/
--
1.8.5.2
^ permalink raw reply related
* [PATCH v6 1/6] dt-bindings: sram: describe option to reserve parts of the memory
From: Rob Herring @ 2014-01-16 14:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1433254.MeOmJHi2Mt@phil>
On Wed, Jan 15, 2014 at 3:40 PM, Heiko St?bner <heiko@sntech.de> wrote:
> Some SoCs need parts of their sram for special purposes. So while being part
> of the peripheral, it should not be part of the genpool controlling the sram.
>
> Therefore add an option mmio-sram-reserved to keep arbitrary portions of the
> sram from general usage.
>
> Suggested-by: Rob Herring <robherring2@gmail.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
> ---
> Documentation/devicetree/bindings/misc/sram.txt | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/misc/sram.txt b/Documentation/devicetree/bindings/misc/sram.txt
> index 4d0a00e..09ee7a3 100644
> --- a/Documentation/devicetree/bindings/misc/sram.txt
> +++ b/Documentation/devicetree/bindings/misc/sram.txt
> @@ -8,9 +8,17 @@ Required properties:
>
> - reg : SRAM iomem address range
>
> +Optional properties:
> +
> +- mmio-sram-reserved: ordered list of reserved chunks inside the sram that
> + should not be used by the operating system.
> + Format is <base size>, <base size>, ...; with base being relative to the
> + reg property base.
> +
> Example:
>
> sram: sram at 5c000000 {
> compatible = "mmio-sram";
> reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
> + mmio-sram-reserved = <0x0 0x100>; /* reserve 0x5c000000-0x5c000100 */
> };
> --
> 1.7.10.4
>
>
^ permalink raw reply
* How to support SDIO wifi/bt in DT
From: Russell King - ARM Linux @ 2014-01-16 14:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140116140858.GD27282@piout.net>
On Thu, Jan 16, 2014 at 03:08:58PM +0100, Alexandre Belloni wrote:
> I hit exactly the same issue trying to support a TiWi chip on SDIO. On
> my side, I used vmmc-supply to drive the reset GPIO with a fixed
> regulator. The other thing needed was the clock. That one, I put it in
> the board file. I guess we need a way to describe children of the SDIO
> host and the host driver would be responsible to manage power supplies,
> resets and clocks...
I thought about doing that, but the issue I run into is that I need
four regulators in total, and some way to combine them so that I get
the right sequence.
The sequence currently being done in the board in the FSL v3.0.35
kernel is:
- drive both reset gpio low
- power up wifi/bt via gpio
- power up oscillator via gpio
- wait 2ms
- drive both reset gpios high
- wait 2ms
- detect sdio device
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* [PATCH 06/11] documentation/iommu: Update description of ARM System MMU binding
From: Rob Herring @ 2014-01-16 14:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389876263-25759-7-git-send-email-andreas.herrmann@calxeda.com>
On Thu, Jan 16, 2014 at 6:44 AM, Andreas Herrmann
<andreas.herrmann@calxeda.com> wrote:
> This patch adds descriptions fore new properties of device tree
> binding for the ARM SMMU architecture. These properties control
> arm-smmu driver options.
>
> Cc: Rob Herring <robherring2@gmail.com>
> Cc: Grant Likely <grant.likely@linaro.org>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
> Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
Acked-by: Rob Herring <robh@kernel.org>
> ---
> .../devicetree/bindings/iommu/arm,smmu.txt | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> index e34c6cd..7ad8ff0 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> @@ -48,6 +48,16 @@ conditions.
> from the mmu-masters towards memory) node for this
> SMMU.
>
> +- arm,smmu-isolate-devices : Enable device isolation for all masters
> + of this SMMU. Ie. each master will be attached to
> + its own iommu domain.
> +
> +- calxeda,smmu-secure-config-access : Enable proper handling of buggy
> + implementations that always use secure access to
> + SMMU configuration registers. In this case
> + non-secure aliases of secure registers have to be
> + used during SMMU configuration.
> +
> Example:
>
> smmu {
> @@ -67,4 +77,5 @@ Example:
> */
> mmu-masters = <&dma0 0xd01d 0xd01e>,
> <&dma1 0xd11c>;
> + arm,smmu-isolate-devices;
> };
> --
> 1.7.9.5
>
^ permalink raw reply
* [PATCH 09/11] ARM: dts: Add nodes for SMMUs on Calxeda ECX-2000
From: Rob Herring @ 2014-01-16 14:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389876263-25759-10-git-send-email-andreas.herrmann@calxeda.com>
On Thu, Jan 16, 2014 at 6:44 AM, Andreas Herrmann
<andreas.herrmann@calxeda.com> wrote:
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
> Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
One minor comment, but otherwise:
Acked-by: Rob Herring <robh@kernel.org>
> ---
> arch/arm/boot/dts/ecx-2000.dts | 44 +++++++++++++++++++++++++++++++++++--
> arch/arm/boot/dts/ecx-common.dtsi | 9 +++++---
> 2 files changed, 48 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
> index 2ccbb57f..722de49 100644
> --- a/arch/arm/boot/dts/ecx-2000.dts
> +++ b/arch/arm/boot/dts/ecx-2000.dts
> @@ -76,10 +76,11 @@
> };
>
> soc {
> - ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
> + ranges = <0x0 0x0 0x0 0xffffffff>;
>
> timer {
> - compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
> + compatible = "arm,cortex-a15-timer", "arm,armv7-timer";
> + interrupts = <1 13 0xf08>,
> <1 14 0xf08>,
> <1 11 0xf08>,
> <1 10 0xf08>;
> @@ -109,6 +110,45 @@
> interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
> };
> };
> +
> + soc at 920000000 {
I believe this and the other > 32-bit addresses below should be
"soc at 9,20000000".
> + ranges = <0x9 0x20000000 0x9 0x20000000 0x290000>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + interrupt-parent = <&intc>;
> +
> + smmu_mac0: smmu at 920000000 {
> + compatible = "arm,mmu-400";
> + reg = <0x9 0x20000000 0x10000>;
> + #global-interrupts = <1>;
> + interrupts = <0 106 4 0 106 4>;
> + mmu-masters = <&mac0 0 1>;
> + calxeda,smmu-secure-config-access;
> + arm,smmu-isolate-devices;
> + };
> +
> + smmu_mac1: smmu at 920080000 {
> + compatible = "arm,mmu-400";
> + reg = <0x9 0x20080000 0x10000>;
> + #global-interrupts = <1>;
> + interrupts = <0 108 4 0 108 4>;
> + mmu-masters = <&mac1 0 1>;
> + calxeda,smmu-secure-config-access;
> + arm,smmu-isolate-devices;
> + };
> +
> + smmu_sata: smmu at 920180000 {
> + compatible = "arm,mmu-400";
> + reg = <0x00000009 0x20180000 0x10000>;
> + mmu-masters = <&sata 0 1 2 3 4 5 6 7 8 9>;
> + #global-interrupts = <1>;
> + interrupts = <0 114 4 0 114 4>;
> + calxeda,smmu-secure-config-access;
> + arm,smmu-isolate-devices;
> + };
> + };
> +
> };
>
> /include/ "ecx-common.dtsi"
> diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
> index b90045a..ad9b2fd 100644
> --- a/arch/arm/boot/dts/ecx-common.dtsi
> +++ b/arch/arm/boot/dts/ecx-common.dtsi
> @@ -33,7 +33,7 @@
> compatible = "simple-bus";
> interrupt-parent = <&intc>;
>
> - sata at ffe08000 {
> + sata: sata at ffe08000 {
> compatible = "calxeda,hb-ahci";
> reg = <0xffe08000 0x10000>;
> interrupts = <0 83 4>;
> @@ -43,6 +43,7 @@
> &combophy0 3>;
> calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
> calxeda,led-order = <4 0 1 2 3>;
> + #stream-id-cells = <10>;
> };
>
> sdhci at ffe0e000 {
> @@ -210,18 +211,20 @@
> clock-names = "apb_pclk";
> };
>
> - ethernet at fff50000 {
> + mac0: ethernet at fff50000 {
> compatible = "calxeda,hb-xgmac";
> reg = <0xfff50000 0x1000>;
> interrupts = <0 77 4 0 78 4 0 79 4>;
> dma-coherent;
> + #stream-id-cells = <2>;
> };
>
> - ethernet at fff51000 {
> + mac1: ethernet at fff51000 {
> compatible = "calxeda,hb-xgmac";
> reg = <0xfff51000 0x1000>;
> interrupts = <0 80 4 0 81 4 0 82 4>;
> dma-coherent;
> + #stream-id-cells = <2>;
> };
>
> combophy0: combo-phy at fff58000 {
> --
> 1.7.9.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 08/11] of: Increase MAX_PHANDLE_ARGS
From: Rob Herring @ 2014-01-16 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389876263-25759-9-git-send-email-andreas.herrmann@calxeda.com>
On Thu, Jan 16, 2014 at 6:44 AM, Andreas Herrmann
<andreas.herrmann@calxeda.com> wrote:
> arm-smmu driver uses of_parse_phandle_with_args when parsing DT
> information to determine stream IDs for a master device.
> Thus the number of stream IDs per master device is bound by
> MAX_PHANDLE_ARGS.
>
> To support Calxeda ECX-2000 hardware arm-smmu driver requires a
> slightly higher value for MAX_PHANDLE_ARGS as this hardware has 10
> stream IDs for one master device.
>
> Cc: Grant Likely <grant.likely@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree at vger.kernel.org
> Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
> Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
Acked-by: Rob Herring <robh@kernel.org>
One comment below...
> ---
> include/linux/of.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/linux/of.h b/include/linux/of.h
> index 276c546..0807af8 100644
> --- a/include/linux/of.h
> +++ b/include/linux/of.h
> @@ -67,7 +67,7 @@ struct device_node {
> #endif
> };
>
> -#define MAX_PHANDLE_ARGS 8
> +#define MAX_PHANDLE_ARGS 10
Just bump this to 16. This is normally just a temporary on the stack
and 8 more words on the stack is not going to cost much.
Rob
^ permalink raw reply
* How to support SDIO wifi/bt in DT
From: Alexandre Belloni @ 2014-01-16 14:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140116133649.GV15937@n2100.arm.linux.org.uk>
On Thu, Jan 16, 2014 at 01:36:49PM +0000, Russell King - ARM Linux wrote :
> Okay, I'm hitting something of a dead end with trying to work out how to
> support this in DT.
>
> The Wifi/BT (bcrmfmac) device has multiple connections to the host device
> - it has a SDIO connection, a UART connection, and an audio connection.
> In addition, a series of GPIOs are wired to control this device:
>
> - Reset for bluetooth plus two additional GPIOs (unused I think)
> - Reset for Wifi plus two additional GPIOs (again, I think unused)
> - GPIO to control regulator supplying power to the Wifi/BT chip
> - GPIO to control regulator supplying power to the oscillator for
> the Wifi/BT chip.
>
> The Wifi/BT chip can only be detected via probing the SDIO connection, and
> only when the device has been powered up and released from reset - so we
> have to power up and reset the bcrm device before we probe via the SDIO
> bus.
>
> While it's possible to attach the power supply for the Wifi/BT chip to the
> vmmc-supply property of the host, it's not possible to do that with the
> oscillator supply. Neither is there any provision for manipulating the
> GPIOs to deal with the resets.
>
> I can't find any examples of anything similar in our existing set of DT
> files, so I suspect either this is a device which no one supports on any
> DT platform, or there's some clever way to handle this.
>
> How do other people support this in DT? Do they hack up some platform
> specific code (which isn't nice)? What other solutions are there to get
> around this problem? How does this kind of thing get represented in DT?
>
> (Don't suggest adding DT support to the bcrmfmac driver - this is a
> chicken-and-egg problem. The driver isn't being probed at the moment
> because the device is powered down and/or held in reset, so is
> undetectable. The kernel needs to power it up and release the reset
> so it becomes detectable.)
I hit exactly the same issue trying to support a TiWi chip on SDIO. On
my side, I used vmmc-supply to drive the reset GPIO with a fixed
regulator. The other thing needed was the clock. That one, I put it in
the board file. I guess we need a way to describe children of the SDIO
host and the host driver would be responsible to manage power supplies,
resets and clocks...
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply
* How to support SDIO wifi/bt in DT
From: Arnd Bergmann @ 2014-01-16 14:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140116133649.GV15937@n2100.arm.linux.org.uk>
On Thursday 16 January 2014 13:36:49 Russell King - ARM Linux wrote:
>
> The Wifi/BT chip can only be detected via probing the SDIO connection, and
> only when the device has been powered up and released from reset - so we
> have to power up and reset the bcrm device before we probe via the SDIO
> bus.
This is indeed a common problem, and while we've talked about solving
it in the past, nothing has happened code-wise. It indeed needs an
implementation in the sdio framework.
> While it's possible to attach the power supply for the Wifi/BT chip to the
> vmmc-supply property of the host, it's not possible to do that with the
> oscillator supply. Neither is there any provision for manipulating the
> GPIOs to deal with the resets.
>
> I can't find any examples of anything similar in our existing set of DT
> files, so I suspect either this is a device which no one supports on any
> DT platform, or there's some clever way to handle this.
The former.
> How do other people support this in DT? Do they hack up some platform
> specific code (which isn't nice)? What other solutions are there to get
> around this problem? How does this kind of thing get represented in DT?
>
> (Don't suggest adding DT support to the bcrmfmac driver - this is a
> chicken-and-egg problem. The driver isn't being probed at the moment
> because the device is powered down and/or held in reset, so is
> undetectable. The kernel needs to power it up and release the reset
> so it becomes detectable.)
The problem is two-fold:
a) we need to add a generic mechanism to the SDIO probe code to
allow specifying clocks, regulators and resets (possibly more)
for an SDIO endpoint that get enabled before the probe starts.
This parts needs a DT binding for SDIO slots as well as code.
b) We need to add a way to attach a device_node to an sdio_func,
so that a function driver can find additional DT properties.
This part should be relatively simple once (a) is done and
should only need a little code but no new binding. The code
would be similar to what we do for amba, i2c or spi devices.
Note that the same problem exists for a number of other discoverable
buses that get used in nondiscoverable ways, e.g. USB, PCI,
or even SCSI. It's normally a spec violation if those devices
are wired up like this, but of course we still want to support
the hardware.
Arnd
^ permalink raw reply
* How to support SDIO wifi/bt in DT
From: Chen-Yu Tsai @ 2014-01-16 13:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140116133649.GV15937@n2100.arm.linux.org.uk>
Hi,
On Thu, Jan 16, 2014 at 9:36 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> Okay, I'm hitting something of a dead end with trying to work out how to
> support this in DT.
>
> The Wifi/BT (bcrmfmac) device has multiple connections to the host device
> - it has a SDIO connection, a UART connection, and an audio connection.
> In addition, a series of GPIOs are wired to control this device:
>
> - Reset for bluetooth plus two additional GPIOs (unused I think)
The other 2 are wake and host wake (interrupts in either direction) I suppose?
The device should support in-band signaling over the UART as well, and
we have no way to tie these 2 interrupts to the bluetooth device anyway.
> - Reset for Wifi plus two additional GPIOs (again, I think unused)
Again, should be out-of-band interrupts in both directions.
> - GPIO to control regulator supplying power to the Wifi/BT chip
> - GPIO to control regulator supplying power to the oscillator for
> the Wifi/BT chip.
>
> The Wifi/BT chip can only be detected via probing the SDIO connection, and
> only when the device has been powered up and released from reset - so we
> have to power up and reset the bcrm device before we probe via the SDIO
> bus.
>
> While it's possible to attach the power supply for the Wifi/BT chip to the
> vmmc-supply property of the host, it's not possible to do that with the
> oscillator supply. Neither is there any provision for manipulating the
> GPIOs to deal with the resets.
Android devices would probably use a custom rfkill device.
> I can't find any examples of anything similar in our existing set of DT
> files, so I suspect either this is a device which no one supports on any
> DT platform, or there's some clever way to handle this.
>
> How do other people support this in DT? Do they hack up some platform
> specific code (which isn't nice)? What other solutions are there to get
> around this problem? How does this kind of thing get represented in DT?
AFAIK, there is none at the moment.
I am working on a patch series that adds DT support to rfkill-gpio.
rfkill-gpio takes at most 2 GPIOs and 1 clock for each rfkill control.
You would register one for wifi, and one for bluetooth. The patches
should be posted by tomorrow, hopefully.
But the brcmfmac driver also registers one itself, so you would have
2 wifi rfkills in the system. So I register my wifi power as a regulator
that is always on, using fixed-regulator with the regulator-always-on DT
property.
> (Don't suggest adding DT support to the bcrmfmac driver - this is a
> chicken-and-egg problem. The driver isn't being probed at the moment
> because the device is powered down and/or held in reset, so is
> undetectable. The kernel needs to power it up and release the reset
> so it becomes detectable.)
The brcmfmac driver also has a platform device component, which one can
give power on/off callbacks through platform data. Maybe we can add DT
support to this bit as well.
I'v already completed device tree support for the SDIO device part, to
be able to use out-of-band interrupt signaling. However the sunxi GPIO
driver isn't well tested, and I am not getting interrupts. Still have to
sort this out to actually test my work.
Cheers,
ChenYu
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox