* How to support SDIO wifi/bt in DT
From: Andrew Lunn @ 2014-01-17 10:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140117093909.GB2348@piout.net>
> The TI wilink chips (TiWi, wl12xx, wl18xx) have wifi on SDIO and BT on
> UART but they share the same clock. So, the next question would be what
> if I just want to enable one or the other (and take that decision at
> runtime) ?
At least for the clock is it not an issue. The generic clock framework
does "reference" counting. It will only turn the clock off when all
users have said to turn it off. So put a phandle to the clock in all
nodes which use it.
I've not looked at regulators, but i would hope it also does reference
counting of a regulators users.
Andrew
^ permalink raw reply
* [PATCH] arm64: fix strnlen_user when count <= strlen
From: Will Deacon @ 2014-01-17 10:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140116234817.GP18705@redacted.bos.redhat.com>
Hi Kyle,
On Thu, Jan 16, 2014 at 11:48:17PM +0000, Kyle McMartin wrote:
> I received a bug report about the ruby test-suite failing on AArch64 when
> attempting to pass MAX_ARG_STRLEN sized args to execv[1]. It was
> expecting an E2BIG returned, but instead was receiving ENOMEM, and
> concatenating the argument strings in funky ways.
>
> The problem appeared to be in __strnlen_user on arm64, as when
> instrumenting fs/exec.c to compare the results of the asm-generic
> strnlen_user, I noticed an off-by-one on the result:
> long-param-test: optimized strnlen_user (131072) and naive (131073) disagree!
>
> As a result, fix strnlen_user to match expected behaviour as documented
> in lib/strnlen_user.c, and return count+1 when count would be exceeded.
>
> I didn't feel comfortable prodding the assembler, so I just worked
> around it in the wrapper.
Actually, I have removed strnlen_user for 3.14. Could you try your test case
with our for-next branch please?
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
As for the issue you spotted, we probably need a fix for that to go into
stable kernels. Does the following (smaller patch) work for you?
Will
--->8
diff --git a/arch/arm64/lib/strnlen_user.S b/arch/arm64/lib/strnlen_user.S
index 7f7b176a5646..73f3335a2a45 100644
--- a/arch/arm64/lib/strnlen_user.S
+++ b/arch/arm64/lib/strnlen_user.S
@@ -37,6 +37,7 @@ ENTRY(__strnlen_user)
USER(9f, ldrb w3, [x0], #1 )
cbnz w3, 1b
2: sub x0, x0, x2
+ cinc x0, x0, mi
ret
ENDPROC(__strnlen_user)
^ permalink raw reply related
* [PATCH 08/11] of: Increase MAX_PHANDLE_ARGS
From: Andreas Herrmann @ 2014-01-17 11:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_Jsq+fDUYne1OQAd4AeQw-JAoFBf0TCv4YVpy6Vt_UmdkA8A@mail.gmail.com>
On Thu, Jan 16, 2014 at 09:25:59AM -0500, Rob Herring wrote:
> On Thu, Jan 16, 2014 at 6:44 AM, Andreas Herrmann
> <andreas.herrmann@calxeda.com> wrote:
> > arm-smmu driver uses of_parse_phandle_with_args when parsing DT
> > information to determine stream IDs for a master device.
> > Thus the number of stream IDs per master device is bound by
> > MAX_PHANDLE_ARGS.
> >
> > To support Calxeda ECX-2000 hardware arm-smmu driver requires a
> > slightly higher value for MAX_PHANDLE_ARGS as this hardware has 10
> > stream IDs for one master device.
> >
> > Cc: Grant Likely <grant.likely@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: devicetree at vger.kernel.org
> > Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
> > Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
>
> Acked-by: Rob Herring <robh@kernel.org>
>
> One comment below...
>
> > ---
> > include/linux/of.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/linux/of.h b/include/linux/of.h
> > index 276c546..0807af8 100644
> > --- a/include/linux/of.h
> > +++ b/include/linux/of.h
> > @@ -67,7 +67,7 @@ struct device_node {
> > #endif
> > };
> >
> > -#define MAX_PHANDLE_ARGS 8
> > +#define MAX_PHANDLE_ARGS 10
>
> Just bump this to 16. This is normally just a temporary on the stack
> and 8 more words on the stack is not going to cost much.
Yes, that seems reasonable.
Thanks,
Andreas
^ permalink raw reply
* [PATCH 09/11] ARM: dts: Add nodes for SMMUs on Calxeda ECX-2000
From: Andreas Herrmann @ 2014-01-17 11:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqK2JUBEvCb-=eHFE_T=2AD0K_+V=NAeijzK2DrCwkaCOA@mail.gmail.com>
On Thu, Jan 16, 2014 at 09:30:26AM -0500, Rob Herring wrote:
> On Thu, Jan 16, 2014 at 6:44 AM, Andreas Herrmann
> <andreas.herrmann@calxeda.com> wrote:
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
> > Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
>
> One minor comment, but otherwise:
>
> Acked-by: Rob Herring <robh@kernel.org>
>
> > ---
> > arch/arm/boot/dts/ecx-2000.dts | 44 +++++++++++++++++++++++++++++++++++--
> > arch/arm/boot/dts/ecx-common.dtsi | 9 +++++---
> > 2 files changed, 48 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
> > index 2ccbb57f..722de49 100644
> > --- a/arch/arm/boot/dts/ecx-2000.dts
> > +++ b/arch/arm/boot/dts/ecx-2000.dts
> > @@ -76,10 +76,11 @@
> > };
> >
> > soc {
> > - ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
> > + ranges = <0x0 0x0 0x0 0xffffffff>;
> >
> > timer {
> > - compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
> > + compatible = "arm,cortex-a15-timer", "arm,armv7-timer";
> > + interrupts = <1 13 0xf08>,
> > <1 14 0xf08>,
> > <1 11 0xf08>,
> > <1 10 0xf08>;
> > @@ -109,6 +110,45 @@
> > interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
> > };
> > };
> > +
> > + soc at 920000000 {
>
> I believe this and the other > 32-bit addresses below should be
> "soc at 9,20000000".
Will fix this.
Thanks,
Andreas
^ permalink raw reply
* [PATCH v2 08/11] of: Increase MAX_PHANDLE_ARGS
From: Andreas Herrmann @ 2014-01-17 11:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389876263-25759-9-git-send-email-andreas.herrmann@calxeda.com>
arm-smmu driver uses of_parse_phandle_with_args when parsing DT
information to determine stream IDs for a master device.
Thus the number of stream IDs per master device is bound by
MAX_PHANDLE_ARGS.
To support Calxeda ECX-2000 hardware arm-smmu driver requires a
slightly higher value for MAX_PHANDLE_ARGS as this hardware has 10
stream IDs for one master device.
Increasing it to 16 seems a reasonable choice.
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree at vger.kernel.org
Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
---
include/linux/of.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/of.h b/include/linux/of.h
index 276c546..24e1b28 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -67,7 +67,7 @@ struct device_node {
#endif
};
-#define MAX_PHANDLE_ARGS 8
+#define MAX_PHANDLE_ARGS 16
struct of_phandle_args {
struct device_node *np;
int args_count;
--
1.7.9.5
^ permalink raw reply related
* [PATCH] arm64: mm: use ubfm for dcache_line_size
From: Will Deacon @ 2014-01-17 11:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <000301cf135a$c1390e40$43ab2ac0$%han@samsung.com>
On Fri, Jan 17, 2014 at 08:04:32AM +0000, Jingoo Han wrote:
> Use 'ubfm' for the bitfield move instruction; thus, single
> instruction can be used instead of two instructions, when
> getting the minimum D-cache line size from CTR_EL0 register.
>
> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
> ---
> arch/arm64/mm/proc-macros.S | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm64/mm/proc-macros.S b/arch/arm64/mm/proc-macros.S
> index 8957b82..c31f41e 100644
> --- a/arch/arm64/mm/proc-macros.S
> +++ b/arch/arm64/mm/proc-macros.S
> @@ -38,8 +38,7 @@
> */
> .macro dcache_line_size, reg, tmp
> mrs \tmp, ctr_el0 // read CTR
> - lsr \tmp, \tmp, #16
> - and \tmp, \tmp, #0xf // cache line size encoding
> + ubfm \tmp, \tmp, #0x16, 0x19 // cache line size encoding
0x16 and 0x19. Are you sure?
You can also grep for other occurences of this pattern and change those too
(pgtable stuff in head.S, clidr in cache.S).
Will
^ permalink raw reply
* [PATCH v2 09/11] ARM: dts: Add nodes for SMMUs on Calxeda ECX-2000
From: Andreas Herrmann @ 2014-01-17 11:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389876263-25759-10-git-send-email-andreas.herrmann@calxeda.com>
Add nodes for SMMUs on Calxeda ECX-2000.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
---
arch/arm/boot/dts/ecx-2000.dts | 44 +++++++++++++++++++++++++++++++++++--
arch/arm/boot/dts/ecx-common.dtsi | 9 +++++---
2 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
index 2ccbb57f..dde23bb 100644
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -76,10 +76,11 @@
};
soc {
- ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
+ ranges = <0x0 0x0 0x0 0xffffffff>;
timer {
- compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
+ compatible = "arm,cortex-a15-timer", "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
@@ -109,6 +110,45 @@
interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
};
};
+
+ soc at 9,20000000 {
+ ranges = <0x9 0x20000000 0x9 0x20000000 0x290000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&intc>;
+
+ smmu_mac0: smmu at 9,20000000 {
+ compatible = "arm,mmu-400";
+ reg = <0x9 0x20000000 0x10000>;
+ #global-interrupts = <1>;
+ interrupts = <0 106 4 0 106 4>;
+ mmu-masters = <&mac0 0 1>;
+ calxeda,smmu-secure-config-access;
+ arm,smmu-isolate-devices;
+ };
+
+ smmu_mac1: smmu at 9,20080000 {
+ compatible = "arm,mmu-400";
+ reg = <0x9 0x20080000 0x10000>;
+ #global-interrupts = <1>;
+ interrupts = <0 108 4 0 108 4>;
+ mmu-masters = <&mac1 0 1>;
+ calxeda,smmu-secure-config-access;
+ arm,smmu-isolate-devices;
+ };
+
+ smmu_sata: smmu at 9,20180000 {
+ compatible = "arm,mmu-400";
+ reg = <0x9 0x20180000 0x10000>;
+ mmu-masters = <&sata 0 1 2 3 4 5 6 7 8 9>;
+ #global-interrupts = <1>;
+ interrupts = <0 114 4 0 114 4>;
+ calxeda,smmu-secure-config-access;
+ arm,smmu-isolate-devices;
+ };
+ };
+
};
/include/ "ecx-common.dtsi"
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index b90045a..ad9b2fd 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -33,7 +33,7 @@
compatible = "simple-bus";
interrupt-parent = <&intc>;
- sata at ffe08000 {
+ sata: sata at ffe08000 {
compatible = "calxeda,hb-ahci";
reg = <0xffe08000 0x10000>;
interrupts = <0 83 4>;
@@ -43,6 +43,7 @@
&combophy0 3>;
calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
calxeda,led-order = <4 0 1 2 3>;
+ #stream-id-cells = <10>;
};
sdhci at ffe0e000 {
@@ -210,18 +211,20 @@
clock-names = "apb_pclk";
};
- ethernet at fff50000 {
+ mac0: ethernet at fff50000 {
compatible = "calxeda,hb-xgmac";
reg = <0xfff50000 0x1000>;
interrupts = <0 77 4 0 78 4 0 79 4>;
dma-coherent;
+ #stream-id-cells = <2>;
};
- ethernet at fff51000 {
+ mac1: ethernet at fff51000 {
compatible = "calxeda,hb-xgmac";
reg = <0xfff51000 0x1000>;
interrupts = <0 80 4 0 81 4 0 82 4>;
dma-coherent;
+ #stream-id-cells = <2>;
};
combophy0: combo-phy at fff58000 {
--
1.7.9.5
^ permalink raw reply related
* [PATCH] arm64: mm: use ubfm for dcache_line_size
From: Ard Biesheuvel @ 2014-01-17 11:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <000301cf135a$c1390e40$43ab2ac0$%han@samsung.com>
On 17 January 2014 09:04, Jingoo Han <jg1.han@samsung.com> wrote:
> Use 'ubfm' for the bitfield move instruction; thus, single
> instruction can be used instead of two instructions, when
> getting the minimum D-cache line size from CTR_EL0 register.
>
> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
> ---
> arch/arm64/mm/proc-macros.S | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm64/mm/proc-macros.S b/arch/arm64/mm/proc-macros.S
> index 8957b82..c31f41e 100644
> --- a/arch/arm64/mm/proc-macros.S
> +++ b/arch/arm64/mm/proc-macros.S
> @@ -38,8 +38,7 @@
> */
> .macro dcache_line_size, reg, tmp
> mrs \tmp, ctr_el0 // read CTR
> - lsr \tmp, \tmp, #16
> - and \tmp, \tmp, #0xf // cache line size encoding
> + ubfm \tmp, \tmp, #0x16, 0x19 // cache line size encoding
Even if the # is optional for immediates these days, perhaps it is
better to adhere to a single style in one line?
--
Ard.
^ permalink raw reply
* [PATCH 1/1] clk: samsung: Remove unneeded semicolon
From: Sachin Kamat @ 2014-01-17 11:35 UTC (permalink / raw)
To: linux-arm-kernel
Semicolon not needed after switch statement.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
drivers/clk/samsung/clk-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index f2372fca0136..8538ffe042ce 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -375,7 +375,7 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
break;
default:
break;
- };
+ }
/* Set new configuration. */
__raw_writel(con1, pll->con_reg + 0x4);
--
1.7.9.5
^ permalink raw reply related
* [PATCH] arch_timer: Move delay timer to drivers clocksource
From: Prashant Gaikwad @ 2014-01-17 11:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D902D6.3090208@linaro.org>
On Friday 17 January 2014 03:45 PM, Daniel Lezcano wrote:
> On 01/17/2014 11:11 AM, Prashant Gaikwad wrote:
>> On Friday 17 January 2014 02:42 PM, Daniel Lezcano wrote:
>>> On 01/17/2014 10:07 AM, Antti Miettinen wrote:
>>>> Will Deacon <will.deacon@arm.com> writes:
>>>>> Why can't you use the C3STOP feature so that the arch-timer isn't
>>>>> used when
>>>>> you go idle?
>>>> That would mean falling back to broadcast timer, right? That's not
>>>> necessarily on the local CPU so wakeups would often wake two CPUs.
>>> You can prevent that if the hardware supports it with the
>>> CLOCK_EVT_DYNIRQ flag on the broadcast timer.
>> Instead of falling back on broadcast timer, is it possible to fall back
>> on other per-CPU timer which is preserved across idle state?
> Is it what you are looking for ?
>
> http://lwn.net/Articles/580568/
>
If I understand correctly these patches enables us to use per-CPU timers
as broadcast timers. I do not want to use broadcast timer.
If I have 2 per-CPU timers T1 and T2, T1 is not preserved across idle
state and T2 is preserved. And I want to use T1 as scheduler timer.
Can I do following for idle state?
Idle entry:
clockevents_shutdown(T1);
clockevents_set_mode(T2, ONESHOT);
clockevents_program_event(T2, next_event);
Idle exit:
clockevents_shutdown(T2);
clockevents_set_mode(T1, ONESHOT);
>>>> Does
>>>> anyone have patches for using a CPU local timer as a fallback for
>>>> C3STOP timers?
>>>
>
^ permalink raw reply
* [PATCH V6 1/2] PHY: Exynos: Add Exynos5250 SATA PHY driver
From: Yuvaraj Kumar @ 2014-01-17 11:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D00C33.4060305@samsung.com>
Sorry for the late reply.
On Fri, Jan 10, 2014 at 8:35 PM, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Yuvaraj,
>
> In general this version looks pretty good, but I have some questions inline.
Please find my comments inline.
>
> On 10.01.2014 08:00, Yuvaraj Kumar C D wrote:
> [snip]
>
>> diff --git a/drivers/phy/phy-exynos5250-sata-i2c.c
>> b/drivers/phy/phy-exynos5250-sata-i2c.c
>> new file mode 100644
>> index 0000000..206e337
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos5250-sata-i2c.c
>> @@ -0,0 +1,40 @@
>> +/*
>> + * Copyright (C) 2013 Samsung Electronics Co.Ltd
>> + * Author:
>> + * Yuvaraj C D <yuvaraj.cd@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> it
>> + * under the terms of the GNU General Public License as published by
>> the
>> + * Free Software Foundation; either version 2 of the License, or (at
>> your
>> + * option) any later version.
>> + *
>> + */
>> +
>> +#include <linux/i2c.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +
>> +static int exynos_sata_i2c_probe(struct i2c_client *client,
>> + const struct i2c_device_id *i2c_id)
>> +{
>> + return 0;
>> +}
>> +
>> +static const struct i2c_device_id sataphy_i2c_device_match[] = {
>> + { "exynos-sataphy-i2c", 0 },
>> +};
>> +
>> +static struct i2c_driver sataphy_i2c_driver = {
>> + .probe = exynos_sata_i2c_probe,
>> + .id_table = sataphy_i2c_device_match,
>> + .driver = {
>> + .name = "exynos-sataphy-i2c",
>> + .owner = THIS_MODULE,
>> + },
>> +};
>> +
>> +static int __init exynos5250_phy_i2c_init(void)
>> +{
>> + return i2c_add_driver(&sataphy_i2c_driver);
>> +}
>> +module_init(exynos5250_phy_i2c_init);
>
>
> Hmm, is this driver even necessary now?
Yes.It will not necessary now with of_find_i2c_device_by_node.I will
remove phy-exynos5250-sata-i2c.c
>
> Wolfram, would it be possible to use an i2c_client without a driver bound to
> it?
>
>
>> diff --git a/drivers/phy/phy-exynos5250-sata.c
>> b/drivers/phy/phy-exynos5250-sata.c
>> new file mode 100644
>> index 0000000..6e5ff8d
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos5250-sata.c
>> @@ -0,0 +1,238 @@
>> +/*
>> + * Samsung SATA SerDes(PHY) driver
>> + *
>> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>> + * Authors: Girish K S <ks.giri@samsung.com>
>> + * Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/i2c.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/mfd/syscon.h>
>> +
>> +#define EXYNOS5_SATA_RESET 0x4
>> +#define RESET_CMN_RST_N (1 << 1)
>> +#define LINK_RESET 0xF0000
>
>
> nit: Lowercase is preferred in hexadecimal notation.
> + all other occurrences in this file.
Ok.
>
>
>> +#define EXYNOS5_SATA_MODE0 0x10
>> +#define EXYNOS5_SATAPHY_PMU_ENABLE (1 << 0)
>> +#define SATA_SPD_GEN3 (2 << 0)
>> +#define EXYNOS5_SATA_CTRL0 0x14
>> +#define CTRL0_P0_PHY_CALIBRATED_SEL (1 << 9)
>> +#define CTRL0_P0_PHY_CALIBRATED (1 << 8)
>> +#define EXYNOS5_SATA_PHSATA_CTRLM 0xE0
>> +#define PHCTRLM_REF_RATE (1 << 1)
>> +#define PHCTRLM_HIGH_SPEED (1 << 0)
>> +#define EXYNOS5_SATA_PHSATA_STATM 0xF0
>> +#define PHSTATM_PLL_LOCKED (1 << 0)
>> +#define EXYNOS_SATA_PHY_EN (1 << 0)
>> +#define SATAPHY_CONTROL_OFFSET 0x0724
>> +
>> +struct exynos_sata_phy {
>> + struct phy *phy;
>> + struct clk *phyclk;
>> + void __iomem *regs;
>> + void __iomem *pmureg;
>> + struct i2c_client *client;
>> +};
>> +
>> +static bool wait_for_reg_status(void __iomem *base, u32 reg, u32
>> checkbit,
>> + u32 status)
>> +{
>> + unsigned long timeout = jiffies + usecs_to_jiffies(1000);
>
>
> nit: It would be better to define the timeout using a macro to not use magic
> numbers.
Ok
>
>
>> +
>> + while (time_before(jiffies, timeout)) {
>> + if ((readl(base + reg) & checkbit) == status)
>> + return true;
>> + }
>> +
>> + return false;
>> +}
>> +
>> +static int exynos_sata_phy_power_on(struct phy *phy)
>> +{
>> + struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>> +
>> + regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
>> + EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
>
>
> regmap_update_bits can return an error. Wouldn't it be better to return it
> as return value of this function instead of returning 0 all the time? As a
> side effect, this would make the function smaller by two lines.
Yes.Will incorporate in next version.
>
>
>> +
>> + return 0;
>> +}
>> +
>> +static int exynos_sata_phy_power_off(struct phy *phy)
>> +{
>> + struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>> +
>> + regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
>> + EXYNOS5_SATAPHY_PMU_ENABLE, ~EXYNOS_SATA_PHY_EN);
>
>
> Same here.
Yes.Will incorporate in next version.
>
>
>> +
>> + return 0;
>> +}
>> +
>> +static int exynos_sata_phy_init(struct phy *phy)
>> +{
>> + u32 val = 0;
>> + int ret = 0;
>> + u8 buf[] = { 0x3A, 0x0B };
>> + struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
>> +
>> + regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
>> + EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
>
>
> regmap_update_bits returns an error code.
Yes.Will incorporate in next version.
>
>
>> +
>> + writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> + val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> + val |= 0xFF;
>> + writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> + val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> + val |= LINK_RESET;
>> + writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> + val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> + val |= RESET_CMN_RST_N;
>> + writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> + val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> + val &= ~PHCTRLM_REF_RATE;
>> + writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> +
>> + /* High speed enable for Gen3 */
>> + val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> + val |= PHCTRLM_HIGH_SPEED;
>> + writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
>> +
>> + val = readl(sata_phy->regs + EXYNOS5_SATA_CTRL0);
>> + val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
>> + writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
>> +
>> + val = readl(sata_phy->regs + EXYNOS5_SATA_MODE0);
>> + val |= SATA_SPD_GEN3;
>> + writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0);
>> +
>> + ret = i2c_master_send(sata_phy->client, buf, sizeof(buf));
>> + if (ret < 0)
>> + return -ENXIO;
>
>
> Wouldn't it be better to return the same error code as i2c_master_send
> returned?
Yes.Will incorporate in next version.
>
>
>> +
>> + /* release cmu reset */
>> + val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> + val &= ~RESET_CMN_RST_N;
>> + writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> + val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
>> + val |= RESET_CMN_RST_N;
>> + writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
>> +
>> + return (wait_for_reg_status(sata_phy->regs,
>> EXYNOS5_SATA_PHSATA_STATM,
>> + PHSTATM_PLL_LOCKED, 1)) ? 0 : -EINVAL;
>> +
>
>
> nit: Stray blank line.
Ok.will remove
>
> Also it might be more readable after making wait_for_reg_status() return an
> integer error code (0 and e.g. -EFAULT) and rewriting the last line to:
>
> ret = wait_for_reg_status(sata_phy->regs,
> EXYNOS5_SATA_PHSATA_STATM,
> PHSTATM_PLL_LOCKED, 1);
> if (ret < 0)
> dev_err(&sata_phy->client->dev,
> "PHY PLL locking failed\n");
>
> return ret;
>
Ok.
> By the way, isn't this initialization really needed whenever the PHY is
> powered on?
In Exynos5250, we do require to power on the phy before writing
anything into phy controller register space.
As you know,phy_ops have separate callbacks power_on and init .So I
just used those to separate these functionalities.
>
>
>> +}
>> +
>> +static struct phy_ops exynos_sata_phy_ops = {
>> + .init = exynos_sata_phy_init,
>> + .power_on = exynos_sata_phy_power_on,
>> + .power_off = exynos_sata_phy_power_off,
>> + .owner = THIS_MODULE,
>> +};
>> +
>> +static int exynos_sata_phy_probe(struct platform_device *pdev)
>> +{
>> + struct exynos_sata_phy *sata_phy;
>> + struct device *dev = &pdev->dev;
>> + struct resource *res;
>> + struct phy_provider *phy_provider;
>> + struct device_node *node;
>> + int ret = 0;
>> +
>> + sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL);
>> + if (!sata_phy)
>> + return -ENOMEM;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +
>> + sata_phy->regs = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(sata_phy->regs))
>> + return PTR_ERR(sata_phy->regs);
>> +
>> + sata_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
>> + "samsung,syscon-phandle");
>
>
> pmureg is defined as (void __iomem *) in struct exynos_sata_phy, but
> syscon_regmap_lookup_by_phandle() returns (struct regmap *). Moreover it
> does not return NULL on error, but rather ERR_PTR(). Please correct this.
Ohh!my mistake.Will correct in next version.
>
>
>> + if (!sata_phy->pmureg) {
>> + dev_err(dev, "syscon regmap lookup failed.\n");
>> + return PTR_ERR(sata_phy->pmureg);
>> + }
>> +
>> + node = of_parse_phandle(dev->of_node,
>> + "samsung,exynos-sataphy-i2c-phandle", 0);
>> + if (!node)
>> + return -ENODEV;
>
>
> An error here means that a required DT property was not specified or was
> specified incorrectly. IMHO -EINVAL would be better here.
ok
>
>
>> +
>> + sata_phy->client = of_find_i2c_device_by_node(node);
>> + if (!sata_phy->client)
>> + return -EPROBE_DEFER;
>> +
>> + dev_set_drvdata(dev, sata_phy);
>> +
>> + sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl");
>> + if (IS_ERR(sata_phy->phyclk)) {
>> + dev_err(dev, "failed to get clk for PHY\n");
>> + return PTR_ERR(sata_phy->phyclk);
>> + }
>> +
>> + ret = clk_prepare_enable(sata_phy->phyclk);
>> + if (ret < 0) {
>> + dev_err(dev, "failed to enable source clk\n");
>> + return ret;
>> + }
>> +
>> + sata_phy->phy = devm_phy_create(dev, &exynos_sata_phy_ops, NULL);
>> + if (IS_ERR(sata_phy->phy)) {
>> + clk_disable_unprepare(sata_phy->phyclk);
>> + dev_err(dev, "failed to create PHY\n");
>> + return PTR_ERR(sata_phy->phy);
>> + }
>> +
>> + phy_set_drvdata(sata_phy->phy, sata_phy);
>> +
>> + phy_provider = devm_of_phy_provider_register(dev,
>> + of_phy_simple_xlate);
>> + if (IS_ERR(phy_provider)) {
>> + clk_disable_unprepare(sata_phy->phyclk);
>> + return PTR_ERR(phy_provider);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id exynos_sata_phy_of_match[] = {
>> + { .compatible = "samsung,exynos5250-sata-phy" },
>> + { },
>> +};
>> +MODULE_DEVICE_TABLE(of, exynos_sata_phy_of_match);
>> +
>> +static struct platform_driver exynos_sata_phy_driver = {
>> + .probe = exynos_sata_phy_probe,
>
>
> If this driver can be compiled as module, don't you also need remove?
Will add in next version.
>
> Best regards,
> Tomasz
^ permalink raw reply
* [PATCH] ARM: sunxi: change the AllWinner A1X to sunxi
From: Maxime Ripard @ 2014-01-17 12:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3612364.BZBltgonI0@wuerfel>
Hi Arnd,
On Wed, Jan 15, 2014 at 10:40:56AM +0100, Arnd Bergmann wrote:
> On Wednesday 15 January 2014 10:10:06 Maxime Ripard wrote:
> > On Thu, Jan 09, 2014 at 04:34:04PM +0100, Gerardo Di Iorio wrote:
> > > Change the AllWinner A1X SOCs to Allwinner Sunxi SOCs
> > >
> > > Signed-off-by: Gerardo Di Iorio <arete74@gmail.com>
> > > ---
> > > arch/arm/mach-sunxi/Kconfig | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > > index 547004c..adb2574 100644
> > > --- a/arch/arm/mach-sunxi/Kconfig
> > > +++ b/arch/arm/mach-sunxi/Kconfig
> > > @@ -1,5 +1,5 @@
> > > config ARCH_SUNXI
> > > - bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
> > > + bool "Allwinner Sunxi SOCs" if ARCH_MULTI_V7
> >
> > I wonder if the sunxi (apart the weird letter case) is actually
> > needed. Maybe we can just put "Allwinner SoCs" (it would be great if
> > you could fix the SoCs case too).
>
> If you want to have exact naming, try to find something that excludes the
> old Sun3i (F20) and earlier chips (unless someone is already planning
> to work on them). Maybe also mention the "Boxchip" name, although that
> seems to be falling out of use these days.
I'm not sure that's good to exclude chips. We have a number of SoCs we
don't support even on later families (A31s, A23, mostly). I'm not sure
we want to have an ever growing list of SoCs supported (or
not-supported).
"sunXi" would be fine I guess, or "A-series" like suggested on IRC.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140117/adfff9d0/attachment.sig>
^ permalink raw reply
* [PATCH 1/3] ACPI / idle: Move idle_boot_override out of the arch directory
From: Sudeep Holla @ 2014-01-17 12:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389924207-7360-2-git-send-email-hanjun.guo@linaro.org>
On 17/01/14 02:03, Hanjun Guo wrote:
> Move idle_boot_override out of the arch directory to be a single enum
> including both platforms values, this will make it rather easier to
> avoid ifdefs around which definitions are for which processor in
> generally used ACPI code.
>
> IDLE_FORCE_MWAIT for IA64 is not used anywhere, so romove it.
>
> No functional change in this patch.
>
> Suggested-by: Alan <gnomes@lxorguk.ukuu.org.uk>
> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
> ---
> arch/ia64/include/asm/processor.h | 3 ---
> arch/powerpc/include/asm/processor.h | 1 -
> arch/x86/include/asm/processor.h | 3 ---
> arch/x86/kernel/process.c | 1 +
> include/linux/cpu.h | 8 ++++++++
> 5 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/arch/ia64/include/asm/processor.h b/arch/ia64/include/asm/processor.h
> index 5a84b3a..ccd63a0 100644
> --- a/arch/ia64/include/asm/processor.h
> +++ b/arch/ia64/include/asm/processor.h
> @@ -698,9 +698,6 @@ prefetchw (const void *x)
>
> extern unsigned long boot_option_idle_override;
>
> -enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,
> - IDLE_NOMWAIT, IDLE_POLL};
> -
> void default_idle(void);
>
> #define ia64_platform_is(x) (strcmp(x, ia64_platform_name) == 0)
> diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
> index fc14a38..06689c0 100644
> --- a/arch/powerpc/include/asm/processor.h
> +++ b/arch/powerpc/include/asm/processor.h
> @@ -440,7 +440,6 @@ static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
> #endif
>
> extern unsigned long cpuidle_disable;
> -enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
>
I don't think it is used in the context of ACPI. Though it's same variable name,
it looks like it just used as boot to override the cpuidle option.
Does it still make any sense to combine this ?
> extern int powersave_nap; /* set if nap mode can be used in idle loop */
> extern void power7_nap(void);
> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
> index 7b034a4..4bee51a 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -729,9 +729,6 @@ extern void init_amd_e400_c1e_mask(void);
> extern unsigned long boot_option_idle_override;
> extern bool amd_e400_c1e_detected;
>
> -enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
> - IDLE_POLL};
> -
> extern void enable_sep_cpu(void);
> extern int sysenter_setup(void);
>
> diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
> index 3fb8d95..62764ff 100644
> --- a/arch/x86/kernel/process.c
> +++ b/arch/x86/kernel/process.c
> @@ -17,6 +17,7 @@
> #include <linux/stackprotector.h>
> #include <linux/tick.h>
> #include <linux/cpuidle.h>
> +#include <linux/cpu.h>
> #include <trace/events/power.h>
> #include <linux/hw_breakpoint.h>
> #include <asm/cpu.h>
> diff --git a/include/linux/cpu.h b/include/linux/cpu.h
> index 03e235ad..e324561 100644
> --- a/include/linux/cpu.h
> +++ b/include/linux/cpu.h
> @@ -220,6 +220,14 @@ void cpu_idle(void);
>
> void cpu_idle_poll_ctrl(bool enable);
>
> +enum idle_boot_override {
> + IDLE_NO_OVERRIDE = 0,
> + IDLE_HALT,
> + IDLE_NOMWAIT,
> + IDLE_POLL,
> + IDLE_POWERSAVE_OFF
> +};
> +
I do understand the idea behind this change, but IMO HALT and MWAIT are x86
specific and may not make sense for other architectures.
It will also require every architecture using ACPI to export
boot_option_idle_override which may not be really required.
Further the only users of boot_option_idle_override(outside x86) are:
1. drivers/acpi/processor_core.c
Your second patch is moving this to x86 specific code anyway
2. drivers/acpi/processor_idle.c
Currently idle driver is bit x86 specific and needs modifications to get it
working on ARM
Regards,
Sudeep
^ permalink raw reply
* [PATCH 2/4] ARM: sun6i: dt: Add PLL6 and SPI module clocks
From: Maxime Ripard @ 2014-01-17 12:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140116181528.GY8153@joshc.qualcomm.com>
Hi Josh,
On Thu, Jan 16, 2014 at 12:15:28PM -0600, Josh Cartwright wrote:
> On Thu, Jan 16, 2014 at 06:11:23PM +0100, Maxime Ripard wrote:
> > The module clocks in the A31 are still compatible with the A10 one. Add the SPI
> > module clocks and the PLL6 in the device tree to allow their use by the SPI
> > controllers.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > arch/arm/boot/dts/sun6i-a31.dtsi | 48 +++++++++++++++++++++++++++++++---------
> > 1 file changed, 38 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> > index 5256ad9..ae058eb 100644
> > --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> > +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> > @@ -73,16 +73,12 @@
> > clocks = <&osc24M>;
> > };
> >
> > - /*
> > - * This is a dummy clock, to be used as placeholder on
> > - * other mux clocks when a specific parent clock is not
> > - * yet implemented. It should be dropped when the driver
> > - * is complete.
> > - */
> > - pll6: pll6 {
> > - #clock-cells = <0>;
> > - compatible = "fixed-clock";
> > - clock-frequency = <0>;
> > + pll6: clk at 01c20028 {
> > + #clock-cells = <1>;
> > + compatible = "allwinner,sun6i-a31-pll6-clk";
> > + reg = <0x01c20028 0x4>;
> > + clocks = <&osc24M>;
> > + clock-output-names = "pll6";
> > };
> >
> > cpu: cpu at 01c20050 {
> > @@ -182,6 +178,38 @@
> > "apb2_uart1", "apb2_uart2", "apb2_uart3",
> > "apb2_uart4", "apb2_uart5";
> > };
> > +
> > + spi0_clk: clk at 01c200a0 {
> > + #clock-cells = <0>;
> > + compatible = "allwinner,sun4i-mod0-clk";
> > + reg = <0x01c200a0 0x4>;
> > + clocks = <&osc24M>, <&pll6>;
>
> This looks weird. You've set the pll6 #clock-cells = <1>, but you
> aren't using a specifier here. Same below, as well. The binding
> documentation indicates that #clock-cells should be 0 for the pll6 node.
Ah, right, it's a dumb copy/paste mistake.
I'd expect dtc to output a warning/error in such case, but apparently
it doesn't.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140117/10c9df26/attachment.sig>
^ permalink raw reply
* [PATCH] arch_timer: Move delay timer to drivers clocksource
From: Daniel Lezcano @ 2014-01-17 12:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D915F3.3030500@nvidia.com>
On 01/17/2014 12:37 PM, Prashant Gaikwad wrote:
> On Friday 17 January 2014 03:45 PM, Daniel Lezcano wrote:
>> On 01/17/2014 11:11 AM, Prashant Gaikwad wrote:
>>> On Friday 17 January 2014 02:42 PM, Daniel Lezcano wrote:
>>>> On 01/17/2014 10:07 AM, Antti Miettinen wrote:
>>>>> Will Deacon <will.deacon@arm.com> writes:
>>>>>> Why can't you use the C3STOP feature so that the arch-timer isn't
>>>>>> used when
>>>>>> you go idle?
>>>>> That would mean falling back to broadcast timer, right? That's not
>>>>> necessarily on the local CPU so wakeups would often wake two CPUs.
>>>> You can prevent that if the hardware supports it with the
>>>> CLOCK_EVT_DYNIRQ flag on the broadcast timer.
>>> Instead of falling back on broadcast timer, is it possible to fall back
>>> on other per-CPU timer which is preserved across idle state?
>> Is it what you are looking for ?
>>
>> http://lwn.net/Articles/580568/
>>
>
> If I understand correctly these patches enables us to use per-CPU timers
> as broadcast timers. I do not want to use broadcast timer.
Why ?
> If I have 2 per-CPU timers T1 and T2, T1 is not preserved across idle
> state and T2 is preserved. And I want to use T1 as scheduler timer.
> Can I do following for idle state?
>
> Idle entry:
> clockevents_shutdown(T1);
> clockevents_set_mode(T2, ONESHOT);
> clockevents_program_event(T2, next_event);
>
> Idle exit:
> clockevents_shutdown(T2);
> clockevents_set_mode(T1, ONESHOT);
>>>>> Does
>>>>> anyone have patches for using a CPU local timer as a fallback for
>>>>> C3STOP timers?
>>>>
>>
>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH] arm64: mm: use ubfm for dcache_line_size
From: Will Deacon @ 2014-01-17 12:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKv+Gu8nnv-ePTyDGv0RiuFcJW7rWhOe0G1JFx439AjA28+wig@mail.gmail.com>
On Fri, Jan 17, 2014 at 11:22:27AM +0000, Ard Biesheuvel wrote:
> On 17 January 2014 09:04, Jingoo Han <jg1.han@samsung.com> wrote:
> > Use 'ubfm' for the bitfield move instruction; thus, single
> > instruction can be used instead of two instructions, when
> > getting the minimum D-cache line size from CTR_EL0 register.
> >
> > Signed-off-by: Jingoo Han <jg1.han@samsung.com>
> > ---
> > arch/arm64/mm/proc-macros.S | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/mm/proc-macros.S b/arch/arm64/mm/proc-macros.S
> > index 8957b82..c31f41e 100644
> > --- a/arch/arm64/mm/proc-macros.S
> > +++ b/arch/arm64/mm/proc-macros.S
> > @@ -38,8 +38,7 @@
> > */
> > .macro dcache_line_size, reg, tmp
> > mrs \tmp, ctr_el0 // read CTR
> > - lsr \tmp, \tmp, #16
> > - and \tmp, \tmp, #0xf // cache line size encoding
> > + ubfm \tmp, \tmp, #0x16, 0x19 // cache line size encoding
>
> Even if the # is optional for immediates these days, perhaps it is
> better to adhere to a single style in one line?
In ARM assembler syntax, the preferred prefix for decimal immediates is '#'
not 0x ;)
Will
^ permalink raw reply
* [PATCH 00/20] Make ACPI core running on ARM64
From: Hanjun Guo @ 2014-01-17 12:24 UTC (permalink / raw)
To: linux-arm-kernel
This patch set trys to make ACPI core running on ARM64.
1. Why ACPI is needed ?
ACPI provides standard interfaces for power managment, themal
control, device enumeration and configuration and etc. So ACPI
can make OS and hardware decoupling and make people upgrade
software or hardware more easily.
ACPI is more than that. It can provide standard error report
interface called ACPI Platform Error Interface (APEI) for
RAS features, and provide standard interface for dynamic
system device reconfigurations such as CPU/memory/computer
node hot-add and hot-remove, this is especially useful
for servers.
2. Does ACPI run propably on ARM64 ?
ACPI spec 5.0 introduces hardware reduced mode, GICC/GICD,
GTDT for arch timer and etc for Socs.
This makes it possible to run ACPI on ARM/ARM64. Some
company already did that (UEFI+ACPI) on ARM platforms.
ACPI spec for ARM/ARM64 is still need to be improved and
people are working on that, but for now, we can run ACPI
propably except for some new features such as PSCI and
GICv3.
3. What we did in this patch set
patch 1-8(Hanjun Guo) will make ACPI core running on ARM64 and
make the compilation is ok on ARM64.
patch 9-12 will enumeration cpus presented by MADT table.
since PSCI is not available for ACPI 5.0, we use spin-table
method for SMP initialization.
patch 13-16 will initialize GIC in the system. ACPI only
support one GIC and only report information about GICC and
GICD, so there will some limitations for GICv3 and GICH
for GICv2 for virtualization.
patch 17-19 and patch from Amit will finish the arch timer
initialization. We get informatiom from GTDT
(Generic Timer Description Table) to initialize arch timer
and introduce a macro CLOCKSOURCE_ACPI_DECLARE to do the
same job as CLOCKSOURCE_OF_DECLARE to make it scalable for
other timers.
All the ACPI tables are available with BSD license at:
git://git.linaro.org/arm/acpi/acpi-asl.git
Changs since last RFC version:
1) Introduce some PCI functions when PCI is enabled
2) Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled
3) Remove ACPI based CPU hotplug code
4) Use spin-table method for SMP initialization
5) Add macro CLOCKSOURCE_ACPI_DECLARE for ACPI timer init
6) Address lots of comments and suggestions in last RFC version
7) Remove RFC tag and make all the patches seperated as two
parts, one is "ACPI: Some patches to prepare for running ACPI
on !x86 and !ia64", and another is this one.
8) Rebased on 3.13-rc8.
Amit Daniel Kachhap (1):
clocksource / acpi: Add macro CLOCKSOURCE_ACPI_DECLARE
Hanjun Guo (19):
ARM64 / ACPI: Make PCI optional for ACPI on ARM64
ARM64 : Add dummy asm/cpu.h
ARM64 / ACPI: Introduce the skeleton of _PDC related for ARM64
ARM64 / ACPI: Introduce arm_core.c and its related head file
ARM64 / ACPI: Introduce lowlevel suspend function
ARM64 / ACPI: Introduce some PCI functions when PCI is enabled
ARM64 / ACPI: Enable ARM64 in Kconfig
ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on
ARM64
ARM64 / ACPI: Implement core functions for parsing MADT table
ARM64 / ACPI: Enumerate possible/present CPU set and map logical cpu
id to APIC id
ARM64 / ACPI: Get the enable method for SMP initialization
ARM64 / ACPI: Use Parked Address in GIC structure for spin table SMP
initialisation
ARM64 / ACPI: Define ACPI_IRQ_MODEL_GIC needed for arm
Irqchip / gic: Set as default domain so we can access from ACPI
ACPI / ARM64: Update acpi_register_gsi to register with the core IRQ
subsystem
ACPI / GIC: Initialize GIC using the information in MADT
clocksource / arch_timer: Use ACPI GTDT table to initialize arch
timer
clocksource / ACPI: Introduce clocksource_acpi_init() using
CLOCKSOURCE_ACPI_DECLARE
ARM64 / clocksource: Use clocksource_acpi_init()
arch/arm64/Kconfig | 3 +
arch/arm64/Makefile | 1 +
arch/arm64/include/asm/acpi.h | 112 +++++++
arch/arm64/include/asm/cpu.h | 25 ++
arch/arm64/include/asm/cpu_ops.h | 1 +
arch/arm64/include/asm/pci.h | 20 ++
arch/arm64/include/asm/processor.h | 2 +
arch/arm64/include/asm/smp.h | 2 +-
arch/arm64/kernel/cpu_ops.c | 2 +-
arch/arm64/kernel/irq.c | 6 +
arch/arm64/kernel/process.c | 3 +
arch/arm64/kernel/setup.c | 6 +
arch/arm64/kernel/smp.c | 42 ++-
arch/arm64/kernel/smp_spin_table.c | 12 +-
arch/arm64/kernel/time.c | 6 +
arch/arm64/pci/Makefile | 1 +
arch/arm64/pci/pci.c | 33 ++
drivers/acpi/Kconfig | 11 +-
drivers/acpi/Makefile | 4 +-
drivers/acpi/bus.c | 3 +
drivers/acpi/internal.h | 7 +
drivers/acpi/osl.c | 3 +-
drivers/acpi/plat/Makefile | 1 +
drivers/acpi/plat/arm-core.c | 599 ++++++++++++++++++++++++++++++++++
drivers/acpi/tables.c | 21 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/arm_arch_timer.c | 101 +++++-
drivers/clocksource/clksrc-acpi.c | 36 ++
drivers/irqchip/irq-gic.c | 7 +
include/asm-generic/vmlinux.lds.h | 10 +
include/linux/acpi.h | 7 +
include/linux/clocksource.h | 15 +
include/linux/pci.h | 33 +-
33 files changed, 1099 insertions(+), 37 deletions(-)
create mode 100644 arch/arm64/include/asm/acpi.h
create mode 100644 arch/arm64/include/asm/cpu.h
create mode 100644 arch/arm64/include/asm/pci.h
create mode 100644 arch/arm64/pci/Makefile
create mode 100644 arch/arm64/pci/pci.c
create mode 100644 drivers/acpi/plat/Makefile
create mode 100644 drivers/acpi/plat/arm-core.c
create mode 100644 drivers/clocksource/clksrc-acpi.c
--
1.7.9.5
^ permalink raw reply
* [PATCH 01/20] ARM64 / ACPI: Make PCI optional for ACPI on ARM64
From: Hanjun Guo @ 2014-01-17 12:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389961514-13562-1-git-send-email-hanjun.guo@linaro.org>
Not all the ARM64 targets that are using ACPI have PCI, so introduce
some stub functions to make PCI optional for ACPI, and make ACPI core
run without CONFIG_PCI on ARM64.
pcibios_penalize_isa_irq() is arch dependent, introduce asm/pci.h to
include it.
Since ACPI on X86 and IA64 depends on PCI, it will not break X86 and
IA64 with this patch.
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Al Stone <al.stone@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
arch/arm64/include/asm/pci.h | 20 ++++++++++++++++++++
drivers/acpi/Makefile | 2 +-
drivers/acpi/internal.h | 7 +++++++
drivers/acpi/osl.c | 3 ++-
include/linux/pci.h | 33 ++++++++++++++++++++++++---------
5 files changed, 54 insertions(+), 11 deletions(-)
create mode 100644 arch/arm64/include/asm/pci.h
diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h
new file mode 100644
index 0000000..455909d
--- /dev/null
+++ b/arch/arm64/include/asm/pci.h
@@ -0,0 +1,20 @@
+#ifndef __ASMARM64_PCI_H
+#define __ASMARM64_PCI_H
+
+#ifdef __KERNEL__
+
+static inline void pcibios_penalize_isa_irq(int irq, int active)
+{
+ /* We don't do dynamic PCI IRQ allocation */
+}
+
+/*
+ * The PCI address space does equal the physical memory address space.
+ * The networking and block device layers use this boolean for bounce
+ * buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS (1)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASMARM64_PCI_H */
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index 0331f91..d8cebe3 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -38,7 +38,7 @@ acpi-y += acpi_processor.o
acpi-y += processor_core.o
acpi-y += ec.o
acpi-$(CONFIG_ACPI_DOCK) += dock.o
-acpi-y += pci_root.o pci_link.o pci_irq.o
+acpi-$(CONFIG_PCI) += pci_root.o pci_link.o pci_irq.o
acpi-$(CONFIG_X86_INTEL_LPSS) += acpi_lpss.o
acpi-y += acpi_platform.o
acpi-y += power.o
diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h
index a29739c..52dff47 100644
--- a/drivers/acpi/internal.h
+++ b/drivers/acpi/internal.h
@@ -26,9 +26,16 @@
acpi_status acpi_os_initialize1(void);
int init_acpi_device_notify(void);
int acpi_scan_init(void);
+#ifdef CONFIG_PCI
void acpi_pci_root_init(void);
void acpi_pci_link_init(void);
void acpi_pci_root_hp_init(void);
+#else
+static inline void acpi_pci_root_init(void) {}
+static inline void acpi_pci_link_init(void) {}
+static inline void acpi_pci_root_hp_init(void) {}
+#endif /* CONFIG_PCI */
+
void acpi_processor_init(void);
void acpi_platform_init(void);
int acpi_sysfs_init(void);
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
index 54a20ff..14ee6fc 100644
--- a/drivers/acpi/osl.c
+++ b/drivers/acpi/osl.c
@@ -1050,7 +1050,8 @@ acpi_os_read_pci_configuration(struct acpi_pci_id * pci_id, u32 reg,
result = raw_pci_read(pci_id->segment, pci_id->bus,
PCI_DEVFN(pci_id->device, pci_id->function),
reg, size, &value32);
- *value = value32;
+ if (!result)
+ *value = value32;
return (result ? AE_ERROR : AE_OK);
}
diff --git a/include/linux/pci.h b/include/linux/pci.h
index a13d682..726cf2a 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -541,15 +541,6 @@ struct pci_ops {
int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
};
-/*
- * ACPI needs to be able to access PCI config space before we've done a
- * PCI bus scan and created pci_bus structures.
- */
-int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
- int reg, int len, u32 *val);
-int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
- int reg, int len, u32 val);
-
struct pci_bus_region {
resource_size_t start;
resource_size_t end;
@@ -1281,6 +1272,15 @@ typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
unsigned int command_bits, u32 flags);
void pci_register_set_vga_state(arch_set_vga_state_t func);
+/*
+ * ACPI needs to be able to access PCI config space before we've done a
+ * PCI bus scan and created pci_bus structures.
+ */
+int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
+ int reg, int len, u32 *val);
+int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
+ int reg, int len, u32 val);
+
#else /* CONFIG_PCI is not enabled */
/*
@@ -1477,6 +1477,21 @@ static inline int pci_domain_nr(struct pci_bus *bus)
static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
{ return NULL; }
+static inline struct pci_bus *pci_find_bus(int domain, int busnr)
+{ return NULL; }
+
+static inline int pci_bus_write_config_byte(struct pci_bus *bus,
+ unsigned int devfn, int where, u8 val)
+{ return -ENODEV; }
+
+static inline int raw_pci_read(unsigned int domain, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 *val)
+{ return -EINVAL; }
+
+static inline int raw_pci_write(unsigned int domain, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 val)
+{return -EINVAL; }
+
#define dev_is_pci(d) (false)
#define dev_is_pf(d) (false)
#define dev_num_vf(d) (0)
--
1.7.9.5
^ permalink raw reply related
* [PATCH 02/20] ARM64 : Add dummy asm/cpu.h
From: Hanjun Guo @ 2014-01-17 12:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389961514-13562-1-git-send-email-hanjun.guo@linaro.org>
ACPI requires a cpu.h, add a dummy one copied from arm. This will need
updated or replaced as ACPI based cpu hotplug or cpu topology for armv8
is worked out.
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
arch/arm64/include/asm/cpu.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 arch/arm64/include/asm/cpu.h
diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
new file mode 100644
index 0000000..8625eb1
--- /dev/null
+++ b/arch/arm64/include/asm/cpu.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2004-2005 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_CPU_H
+#define __ASM_ARM_CPU_H
+
+#include <linux/percpu.h>
+#include <linux/cpu.h>
+#include <linux/topology.h>
+
+struct cpuinfo_arm {
+ struct cpu cpu;
+ u64 cpuid;
+#ifdef CONFIG_SMP
+ unsigned int loops_per_jiffy;
+#endif
+};
+
+DECLARE_PER_CPU(struct cpuinfo_arm, cpu_data);
+
+#endif
--
1.7.9.5
^ permalink raw reply related
* [PATCH 03/20] ARM64 / ACPI: Introduce the skeleton of _PDC related for ARM64
From: Hanjun Guo @ 2014-01-17 12:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389961514-13562-1-git-send-email-hanjun.guo@linaro.org>
The _PDC (Processor Driver Capabilities) object provides OSPM a
mechanism to convey to the platform the capabilities supported
by OSPM for processor power management.
OSPM evaluates _PDC prior to evaluating any other processor
power management objects returning configuration information.
This patch introduces the skeleton of _PDC related file to make
ACPI core can be compiled on ARM64.
Signed-off-by: Al Stone <al.stone@linaro.org>
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
arch/arm64/include/asm/acpi.h | 32 ++++++++++++++++++++++++++++++++
arch/arm64/include/asm/processor.h | 2 ++
arch/arm64/kernel/process.c | 3 +++
3 files changed, 37 insertions(+)
create mode 100644 arch/arm64/include/asm/acpi.h
diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
new file mode 100644
index 0000000..cf19dc6
--- /dev/null
+++ b/arch/arm64/include/asm/acpi.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2013, Al Stone <al.stone@linaro.org>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#ifndef _ASM_ARM64_ACPI_H
+#define _ASM_ARM64_ACPI_H
+
+static inline bool arch_has_acpi_pdc(void)
+{
+ return false; /* always false for now */
+}
+
+static inline void arch_acpi_set_pdc_bits(u32 *buf)
+{
+ return;
+}
+
+#endif /*_ASM_ARM64_ACPI_H*/
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 45b20cd..50ce951 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -162,6 +162,8 @@ static inline void spin_lock_prefetch(const void *x)
#define HAVE_ARCH_PICK_MMAP_LAYOUT
+extern unsigned long boot_option_idle_override;
+
#endif
#endif /* __ASM_PROCESSOR_H */
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index de17c89..13d3d7f 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -89,6 +89,9 @@ void arch_cpu_idle_prepare(void)
local_fiq_enable();
}
+unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
+EXPORT_SYMBOL(boot_option_idle_override);
+
/*
* This is our default idle handler.
*/
--
1.7.9.5
^ permalink raw reply related
* [PATCH 04/20] ARM64 / ACPI: Introduce arm_core.c and its related head file
From: Hanjun Guo @ 2014-01-17 12:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389961514-13562-1-git-send-email-hanjun.guo@linaro.org>
Introduce arm_core.c and its related head file, after this patch,
we can get ACPI tables from firmware on ARM64 now.
Signed-off-by: Al Stone <al.stone@linaro.org>
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
arch/arm64/include/asm/acpi.h | 57 +++++++++++
arch/arm64/kernel/setup.c | 6 ++
drivers/acpi/Makefile | 2 +
drivers/acpi/plat/Makefile | 1 +
drivers/acpi/plat/arm-core.c | 209 +++++++++++++++++++++++++++++++++++++++++
5 files changed, 275 insertions(+)
create mode 100644 drivers/acpi/plat/Makefile
create mode 100644 drivers/acpi/plat/arm-core.c
diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
index cf19dc6..908d71b 100644
--- a/arch/arm64/include/asm/acpi.h
+++ b/arch/arm64/include/asm/acpi.h
@@ -19,6 +19,43 @@
#ifndef _ASM_ARM64_ACPI_H
#define _ASM_ARM64_ACPI_H
+#include <asm/cacheflush.h>
+
+#include <linux/init.h>
+
+#define COMPILER_DEPENDENT_INT64 s64
+#define COMPILER_DEPENDENT_UINT64 u64
+
+/*
+ * Calling conventions:
+ *
+ * ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads)
+ * ACPI_EXTERNAL_XFACE - External ACPI interfaces
+ * ACPI_INTERNAL_XFACE - Internal ACPI interfaces
+ * ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces
+ */
+#define ACPI_SYSTEM_XFACE
+#define ACPI_EXTERNAL_XFACE
+#define ACPI_INTERNAL_XFACE
+#define ACPI_INTERNAL_VAR_XFACE
+
+/* Asm macros */
+#define ACPI_FLUSH_CPU_CACHE() flush_cache_all()
+
+/* Basic configuration for ACPI */
+#ifdef CONFIG_ACPI
+extern int acpi_disabled;
+extern int acpi_noirq;
+extern int acpi_pci_disabled;
+extern int acpi_strict;
+
+static inline void disable_acpi(void)
+{
+ acpi_disabled = 1;
+ acpi_pci_disabled = 1;
+ acpi_noirq = 1;
+}
+
static inline bool arch_has_acpi_pdc(void)
{
return false; /* always false for now */
@@ -29,4 +66,24 @@ static inline void arch_acpi_set_pdc_bits(u32 *buf)
return;
}
+static inline void acpi_noirq_set(void) { acpi_noirq = 1; }
+static inline void acpi_disable_pci(void)
+{
+ acpi_pci_disabled = 1;
+ acpi_noirq_set();
+}
+
+/* FIXME: this function should be moved to topology.h when it's ready */
+void arch_fix_phys_package_id(int num, u32 slot);
+
+/* temperally define -1 to make acpi core compilerable */
+#define cpu_physical_id(cpu) -1
+
+#else /* !CONFIG_ACPI */
+#define acpi_disabled 1 /* ACPI sometimes enabled on ARM */
+#define acpi_noirq 1 /* ACPI sometimes enabled on ARM */
+#define acpi_pci_disabled 1 /* ACPI PCI sometimes enabled on ARM */
+#define acpi_strict 1 /* no ACPI spec workarounds on ARM */
+#endif
+
#endif /*_ASM_ARM64_ACPI_H*/
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index bd9bbd0..2210353 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -41,6 +41,7 @@
#include <linux/memblock.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
+#include <linux/acpi.h>
#include <asm/cputype.h>
#include <asm/elf.h>
@@ -225,6 +226,11 @@ void __init setup_arch(char **cmdline_p)
arm64_memblock_init();
+ /* Parse the ACPI tables for possible boot-time configuration */
+ acpi_boot_table_init();
+ early_acpi_boot_init();
+ acpi_boot_init();
+
paging_init();
request_standard_resources();
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index d8cebe3..9fbba50 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -83,3 +83,5 @@ obj-$(CONFIG_ACPI_PROCESSOR_AGGREGATOR) += acpi_pad.o
obj-$(CONFIG_ACPI_APEI) += apei/
obj-$(CONFIG_ACPI_EXTLOG) += acpi_extlog.o
+
+obj-y += plat/
diff --git a/drivers/acpi/plat/Makefile b/drivers/acpi/plat/Makefile
new file mode 100644
index 0000000..46bc65e
--- /dev/null
+++ b/drivers/acpi/plat/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARM64) += arm-core.o
diff --git a/drivers/acpi/plat/arm-core.c b/drivers/acpi/plat/arm-core.c
new file mode 100644
index 0000000..162a1ab
--- /dev/null
+++ b/drivers/acpi/plat/arm-core.c
@@ -0,0 +1,209 @@
+/*
+ * ARM/ARM64 Specific Low-Level ACPI Boot Support
+ *
+ * Copyright (C) 2013, Al Stone <al.stone@linaro.org>
+ * Copyright (C) 2013, Graeme Gregory <graeme.gregory@linaro.org>
+ * Copyright (C) 2013, Hanjun Guo <hanjun.guo@linaro.org>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/init.h>
+#include <linux/acpi.h>
+#include <linux/cpumask.h>
+#include <linux/memblock.h>
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/bootmem.h>
+#include <linux/smp.h>
+
+#include <asm/pgtable.h>
+
+/*
+ * We never plan to use RSDT on arm/arm64 as its deprecated in spec but this
+ * variable is still required by the ACPI core
+ */
+u32 acpi_rsdt_forced;
+
+int acpi_noirq; /* skip ACPI IRQ initialization */
+int acpi_strict;
+int acpi_disabled;
+EXPORT_SYMBOL(acpi_disabled);
+
+int acpi_pci_disabled; /* skip ACPI PCI scan and IRQ initialization */
+EXPORT_SYMBOL(acpi_pci_disabled);
+
+#define PREFIX "ACPI: "
+
+/* FIXME: this function should be moved to topology.c when it is ready */
+void arch_fix_phys_package_id(int num, u32 slot)
+{
+ return;
+}
+EXPORT_SYMBOL_GPL(arch_fix_phys_package_id);
+
+enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_PLATFORM;
+
+static unsigned int gsi_to_irq(unsigned int gsi)
+{
+ int irq = irq_create_mapping(NULL, gsi);
+
+ return irq;
+}
+
+/*
+ * __acpi_map_table() will be called before page_init(), so early_ioremap()
+ * or early_memremap() should be called here.
+ *
+ * FIXME: early_io/memremap()/early_iounmap() are not upstream yet on ARM64,
+ * just wait for Mark Salter's patchset accepted by mainline
+ */
+char *__init __acpi_map_table(unsigned long phys, unsigned long size)
+{
+ if (!phys || !size)
+ return NULL;
+
+ /*
+ * temporarily use phys_to_virt(),
+ * should be early_memremap(phys, size) here
+ */
+ return phys_to_virt(phys);
+}
+
+void __init __acpi_unmap_table(char *map, unsigned long size)
+{
+ if (!map || !size)
+ return;
+
+ /* should be early_iounmap(map, size); */
+ return;
+}
+
+int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
+{
+ *irq = gsi_to_irq(gsi);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
+
+/*
+ * success: return IRQ number (>0)
+ * failure: return =< 0
+ */
+int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
+{
+ return -1;
+}
+EXPORT_SYMBOL_GPL(acpi_register_gsi);
+
+void acpi_unregister_gsi(u32 gsi)
+{
+}
+EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
+
+static int __init acpi_parse_fadt(struct acpi_table_header *table)
+{
+ return 0;
+}
+
+static void __init early_acpi_process_madt(void)
+{
+ return;
+}
+
+static void __init acpi_process_madt(void)
+{
+ return;
+}
+
+/*
+ * acpi_boot_table_init() and acpi_boot_init()
+ * called from setup_arch(), always.
+ * 1. checksums all tables
+ * 2. enumerates lapics
+ * 3. enumerates io-apics
+ *
+ * acpi_table_init() is separated to allow reading SRAT without
+ * other side effects.
+ */
+void __init acpi_boot_table_init(void)
+{
+ /*
+ * If acpi_disabled, bail out
+ */
+ if (acpi_disabled)
+ return;
+
+ /*
+ * Initialize the ACPI boot-time table parser.
+ */
+ if (acpi_table_init()) {
+ disable_acpi();
+ return;
+ }
+}
+
+int __init early_acpi_boot_init(void)
+{
+ /*
+ * If acpi_disabled, bail out
+ */
+ if (acpi_disabled)
+ return -ENODEV;
+
+ /*
+ * Process the Multiple APIC Description Table (MADT), if present
+ */
+ early_acpi_process_madt();
+
+ return 0;
+}
+
+int __init acpi_boot_init(void)
+{
+ /*
+ * If acpi_disabled, bail out
+ */
+ if (acpi_disabled)
+ return -ENODEV;
+
+ acpi_table_parse(ACPI_SIG_FADT, acpi_parse_fadt);
+
+ /*
+ * Process the Multiple APIC Description Table (MADT), if present
+ */
+ acpi_process_madt();
+
+ return 0;
+}
+
+static int __init parse_acpi(char *arg)
+{
+ if (!arg)
+ return -EINVAL;
+
+ /* "acpi=off" disables both ACPI table parsing and interpreter */
+ if (strcmp(arg, "off") == 0) {
+ disable_acpi();
+ }
+ /* acpi=strict disables out-of-spec workarounds */
+ else if (strcmp(arg, "strict") == 0) {
+ acpi_strict = 1;
+ }
+ return 0;
+}
+early_param("acpi", parse_acpi);
--
1.7.9.5
^ permalink raw reply related
* [PATCH 05/20] ARM64 / ACPI: Introduce lowlevel suspend function
From: Hanjun Guo @ 2014-01-17 12:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389961514-13562-1-git-send-email-hanjun.guo@linaro.org>
Lowlevel suspend function is needed for ACPI based suspend/resume,
introduce ARM related lowlevel function in this patch.
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
arch/arm64/include/asm/acpi.h | 4 ++++
drivers/acpi/plat/arm-core.c | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
index 908d71b..e108d9c 100644
--- a/arch/arm64/include/asm/acpi.h
+++ b/arch/arm64/include/asm/acpi.h
@@ -79,6 +79,10 @@ void arch_fix_phys_package_id(int num, u32 slot);
/* temperally define -1 to make acpi core compilerable */
#define cpu_physical_id(cpu) -1
+/* Low-level suspend routine. */
+extern int (*acpi_suspend_lowlevel)(void);
+#define acpi_wakeup_address (0)
+
#else /* !CONFIG_ACPI */
#define acpi_disabled 1 /* ACPI sometimes enabled on ARM */
#define acpi_noirq 1 /* ACPI sometimes enabled on ARM */
diff --git a/drivers/acpi/plat/arm-core.c b/drivers/acpi/plat/arm-core.c
index 162a1ab..3c8521d 100644
--- a/drivers/acpi/plat/arm-core.c
+++ b/drivers/acpi/plat/arm-core.c
@@ -207,3 +207,10 @@ static int __init parse_acpi(char *arg)
return 0;
}
early_param("acpi", parse_acpi);
+
+/*
+ * acpi_suspend_lowlevel() - save kernel state and suspend.
+ *
+ * TBD when ARM/ARM64 starts to support suspend...
+ */
+int (*acpi_suspend_lowlevel)(void);
--
1.7.9.5
^ permalink raw reply related
* [PATCH 06/20] ARM64 / ACPI: Introduce some PCI functions when PCI is enabled
From: Hanjun Guo @ 2014-01-17 12:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389961514-13562-1-git-send-email-hanjun.guo@linaro.org>
Introduce some PCI functions to make ACPI can be compiled when
CONFIG_PCI is enabled, these functions should be revisited when
implemented on ARM64.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
arch/arm64/Makefile | 1 +
arch/arm64/pci/Makefile | 1 +
arch/arm64/pci/pci.c | 33 +++++++++++++++++++++++++++++++++
drivers/acpi/plat/arm-core.c | 19 +++++++++++++++++++
4 files changed, 54 insertions(+)
create mode 100644 arch/arm64/pci/Makefile
create mode 100644 arch/arm64/pci/pci.c
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 2fceb71..fcaa58e 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -45,6 +45,7 @@ export TEXT_OFFSET GZFLAGS
core-y += arch/arm64/kernel/ arch/arm64/mm/
core-$(CONFIG_KVM) += arch/arm64/kvm/
core-$(CONFIG_XEN) += arch/arm64/xen/
+drivers-$(CONFIG_PCI) += arch/arm64/pci/
libs-y := arch/arm64/lib/ $(libs-y)
libs-y += $(LIBGCC)
diff --git a/arch/arm64/pci/Makefile b/arch/arm64/pci/Makefile
new file mode 100644
index 0000000..b8d5dbd
--- /dev/null
+++ b/arch/arm64/pci/Makefile
@@ -0,0 +1 @@
+obj-y += pci.o
diff --git a/arch/arm64/pci/pci.c b/arch/arm64/pci/pci.c
new file mode 100644
index 0000000..4e46790
--- /dev/null
+++ b/arch/arm64/pci/pci.c
@@ -0,0 +1,33 @@
+#include <linux/acpi.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+
+/**
+ * raw_pci_read - Platform-specific PCI config space access.
+ *
+ * Default empty implementation. Replace with an architecture-specific setup
+ * routine, if necessary.
+ */
+int __weak raw_pci_read(unsigned int domain, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 *val)
+{
+ return -EINVAL;
+}
+
+int __weak raw_pci_write(unsigned int domain, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 val)
+{
+ return -EINVAL;
+}
+
+/* Root bridge scanning */
+struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
+{
+ return NULL;
+}
+
+void __init pci_acpi_crs_quirks(void)
+{
+ return;
+}
diff --git a/drivers/acpi/plat/arm-core.c b/drivers/acpi/plat/arm-core.c
index 3c8521d..1835b21 100644
--- a/drivers/acpi/plat/arm-core.c
+++ b/drivers/acpi/plat/arm-core.c
@@ -100,6 +100,25 @@ int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
}
EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
+int acpi_isa_irq_to_gsi(unsigned isa_irq, u32 *gsi)
+{
+ return -1;
+}
+
+int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base)
+{
+ /* TBD */
+ return -EINVAL;
+}
+EXPORT_SYMBOL(acpi_register_ioapic);
+
+int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base)
+{
+ /* TBD */
+ return -EINVAL;
+}
+EXPORT_SYMBOL(acpi_unregister_ioapic);
+
/*
* success: return IRQ number (>0)
* failure: return =< 0
--
1.7.9.5
^ permalink raw reply related
* [PATCH 07/20] ARM64 / ACPI: Enable ARM64 in Kconfig
From: Hanjun Guo @ 2014-01-17 12:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389961514-13562-1-git-send-email-hanjun.guo@linaro.org>
Add Kconfigs to build ACPI on ARM64, and make ACPI runable on ARM64.
acpi_idle driver is x86/IA64 dependent now, so make CONFIG_ACPI_PROCESSOR
depends on X86 || IA64, and implement it on ARM/ARM64 in the furture.
In order to make arm-core.c can both run on ARM and ARM64, introduce
CONFIG_ACPI_ARM to support it.
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Al Stone <al.stone@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
arch/arm64/Kconfig | 2 ++
drivers/acpi/Kconfig | 11 ++++++++---
drivers/acpi/plat/Makefile | 2 +-
3 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 6d4dd22..2b1fb1d 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -279,6 +279,8 @@ source "net/Kconfig"
source "drivers/Kconfig"
+source "drivers/acpi/Kconfig"
+
source "fs/Kconfig"
source "arch/arm64/kvm/Kconfig"
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index 4770de5..cae5dc9 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -2,13 +2,16 @@
# ACPI Configuration
#
+config ACPI_ARM
+ bool
+
menuconfig ACPI
bool "ACPI (Advanced Configuration and Power Interface) Support"
depends on !IA64_HP_SIM
- depends on IA64 || X86
- depends on PCI
+ depends on ((IA64 || X86) && PCI) || ARM64
select PNP
- default y
+ select ACPI_ARM if ARM64
+ default y if !ARM64
help
Advanced Configuration and Power Interface (ACPI) support for
Linux requires an ACPI-compliant platform (hardware/firmware),
@@ -149,6 +152,7 @@ config ACPI_PROCESSOR
tristate "Processor"
select THERMAL
select CPU_IDLE
+ depends on X86 || IA64
default y
help
This driver installs ACPI as the idle handler for Linux and uses
@@ -250,6 +254,7 @@ config ACPI_DEBUG
config ACPI_PCI_SLOT
bool "PCI slot detection driver"
depends on SYSFS
+ depends on PCI
default n
help
This driver creates entries in /sys/bus/pci/slots/ for all PCI
diff --git a/drivers/acpi/plat/Makefile b/drivers/acpi/plat/Makefile
index 46bc65e..3a61176 100644
--- a/drivers/acpi/plat/Makefile
+++ b/drivers/acpi/plat/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_ARM64) += arm-core.o
+obj-$(CONFIG_ACPI_ARM) += arm-core.o
--
1.7.9.5
^ permalink raw reply related
* [PATCH 08/20] ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64
From: Hanjun Guo @ 2014-01-17 12:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389961514-13562-1-git-send-email-hanjun.guo@linaro.org>
ACPI reduced hardware mode is disabled by default, but ARM64 can
only run properly in ACPI hardware reduced mode at now, so select
ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64.
Signed-off-by: Al Stone <al.stone@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
arch/arm64/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 2b1fb1d..741692c 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1,5 +1,6 @@
config ARM64
def_bool y
+ select ACPI_REDUCED_HARDWARE_ONLY if ACPI
select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select ARCH_USE_CMPXCHG_LOCKREF
select ARCH_WANT_OPTIONAL_GPIOLIB
--
1.7.9.5
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox