* More GPIO madness on iMX6 - and the crappy ARM port of Linux
From: Eric Nelson @ 2014-01-17 19:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D980C8.9020809@boundarydevices.com>
Hi Russell,
On 01/17/2014 12:13 PM, Eric Nelson wrote:
> Hi Russell,
>
> On 01/17/2014 11:47 AM, Russell King - ARM Linux wrote:
>>
>> <snip>
>>
>> So, this brings up three obvious questions:
>>
>> 1. What should gpio_get_value() return for an output?
>
> It seems that this is pretty well specified.
>
> To quote Documentation/gpio/gpio-legacy.txt:
> >> When reading the value of an output pin, the value
> >> returned should be what's seen on the pin ... that
> >> won't always match the specified output value, because
> >> of issues including open-drain signaling and output
> >> latencies.
>
> Documentation/gpio/gpio.txt is a little less clear, but implies
> the same:
> >> If you are "driving" the signal high but
> >> gpiod_get_value(gpio) reports a low value (after
> >> the appropriate rise time passes), you know some other
> >> component is driving the shared signal low
>
>> 2. What should be reported in /sys/kernel/debug/gpio for an output?
>> 3. Should iMX6 (and similar) GPIOs always have the SION bit set in
>> their DT descriptions?
>>
>> Discuss.
>>
>
> Each signal accessed using the GPIO subsystem **must** have
> the SION bit set and the values returned should be the value
> from the PSR registers.
>
Because the MUX registers are very consistent, it appears
that a fix for this that sets the SION bit is simple (almost
mechanical) in the imx*pinfunc.h files.
It seems that each of the declarations matching
#define MX*GPIO_something
should have bit four set in the mux_mode column.
I'd be happy to work up a patch if there's agreement here
(and I can't think of any rationale for not setting these).
Regards,
Eric
^ permalink raw reply
* Re: [PATCH v4 3/8] ARM: brcmstb: add debug UART for earlyprintk support
From: Alexander Shiyan @ 2014-01-17 19:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389986367-4010-4-git-send-email-marc.ceeeee@gmail.com>
???????, 17 ?????? 2014, 11:19 -08:00 ?? Marc Carino <marc.ceeeee@gmail.com>:
> Add the UART definitions needed to support earlyprintk on brcmstb machines.
>
> Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/arm/Kconfig.debug | 16 +++++++++++++++-
> 1 files changed, 15 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index 5765abf..266c699 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -94,6 +94,17 @@ choice
> depends on ARCH_BCM2835
> select DEBUG_UART_PL01X
>
> + config DEBUG_BRCMSTB_UART
> + bool "Use BRCMSTB UART for low-level debug"
> + depends on ARCH_BRCMSTB
> + select DEBUG_UART_8250
> + help
> + Say Y here if you want the debug print routines to direct
> + their output to the first serial port on these devices.
> +
> + If you have a Broadcom STB chip and would like early print
> + messages to appear over the UART, select this option.
> +
> config DEBUG_CLPS711X_UART1
> bool "Kernel low-level debugging messages via UART1"
> depends on ARCH_CLPS711X
> @@ -988,6 +999,7 @@ config DEBUG_UART_PHYS
> default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
> default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
> default 0x20201000 if DEBUG_BCM2835
> + default 0xf0406b00 if DEBUG_BRCMSTB_UART
This should be sorted by address.
---
^ permalink raw reply
* [PATCH v4 8/8] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445
From: Marc Carino @ 2014-01-17 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389986367-4010-1-git-send-email-marc.ceeeee@gmail.com>
Add a sample DTS which will allow bootup of a board populated
with the BCM7445 chip.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm7445.dts | 111 +++++++++++++++++++++++++++++++++++++++++
1 files changed, 111 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/bcm7445.dts
diff --git a/arch/arm/boot/dts/bcm7445.dts b/arch/arm/boot/dts/bcm7445.dts
new file mode 100644
index 0000000..6f2d532
--- /dev/null
+++ b/arch/arm/boot/dts/bcm7445.dts
@@ -0,0 +1,111 @@
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Broadcom STB (bcm7445)";
+ compatible = "brcm,bcm7445", "brcm,brcmstb";
+ interrupt-parent = <&gic>;
+
+ chosen {};
+
+ memory {
+ device_type = "memory";
+ reg = <0x00 0x00000000 0x00 0x40000000>,
+ <0x00 0x40000000 0x00 0x40000000>,
+ <0x00 0x80000000 0x00 0x40000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "brcm,brahma-b15";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu at 1 {
+ compatible = "brcm,brahma-b15";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu at 2 {
+ compatible = "brcm,brahma-b15";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu at 3 {
+ compatible = "brcm,brahma-b15";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ gic: interrupt-controller at ffd00000 {
+ compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic";
+ reg = <0x00 0xffd01000 0x00 0x1000>,
+ <0x00 0xffd02000 0x00 0x2000>,
+ <0x00 0xffd04000 0x00 0x2000>,
+ <0x00 0xffd06000 0x00 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ serial at f0406b00 {
+ compatible = "ns16550a";
+ reg = <0x00 0xf0406b00 0x00 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <0 75 0x4>;
+ clock-frequency = <0x4d3f640>;
+ };
+
+ rdb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x00 0xf0000000 0x1000000>;
+
+ sun_top_ctrl: syscon at 404000 {
+ compatible = "brcm,bcm7445-sun-top-ctrl",
+ "syscon";
+ reg = <0x404000 0x51c>;
+ };
+
+ hif_cpubiuctrl: syscon at 3e2400 {
+ compatible = "brcm,bcm7445-hif-cpubiuctrl",
+ "syscon";
+ reg = <0x3e2400 0x5b4>;
+ };
+
+ hif_continuation: syscon at 452000 {
+ compatible = "brcm,bcm7445-hif-continuation",
+ "syscon";
+ reg = <0x452000 0x100>;
+ };
+ };
+
+ smpboot {
+ compatible = "brcm,brcmstb-smpboot";
+ syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
+ syscon-cont = <&hif_continuation>;
+ };
+
+ reboot {
+ compatible = "brcm,brcmstb-reboot";
+ syscon = <&sun_top_ctrl 0x304 0x308>;
+ };
+};
--
1.7.1
^ permalink raw reply related
* [PATCH v4 7/8] ARM: brcmstb: gic: add compatible string for Broadcom Brahma15
From: Marc Carino @ 2014-01-17 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389986367-4010-1-git-send-email-marc.ceeeee@gmail.com>
Document the Broadcom Brahma B15 GIC implementation as compatible
with the ARM GIC standard.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
Documentation/devicetree/bindings/arm/gic.txt | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 3dfb0c0..d7409fd 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -15,6 +15,7 @@ Main node required properties:
"arm,cortex-a9-gic"
"arm,cortex-a7-gic"
"arm,arm11mp-gic"
+ "brcm,brahma-b15-gic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 3.
--
1.7.1
^ permalink raw reply related
* [PATCH v4 6/8] ARM: brcmstb: add misc. DT bindings for brcmstb
From: Marc Carino @ 2014-01-17 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389986367-4010-1-git-send-email-marc.ceeeee@gmail.com>
Document the bindings that the Broadcom STB platform needs
for proper bootup.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../devicetree/bindings/arm/brcm-brcmstb.txt | 95 ++++++++++++++++++++
1 files changed, 95 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
diff --git a/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
new file mode 100644
index 0000000..3c436cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
@@ -0,0 +1,95 @@
+ARM Broadcom STB platforms Device Tree Bindings
+-----------------------------------------------
+Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
+SoC shall have the following DT organization:
+
+Required root node properties:
+ - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
+
+example:
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Broadcom STB (bcm7445)";
+ compatible = "brcm,bcm7445", "brcm,brcmstb";
+
+Further, syscon nodes that map platform-specific registers used for general
+system control is required:
+
+ - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
+ - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
+ - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
+
+example:
+ rdb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x00 0xf0000000 0x1000000>;
+
+ sun_top_ctrl: syscon at 404000 {
+ compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
+ reg = <0x404000 0x51c>;
+ };
+
+ hif_cpubiuctrl: syscon at 3e2400 {
+ compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
+ reg = <0x3e2400 0x5b4>;
+ };
+
+ hif_continuation: syscon at 452000 {
+ compatible = "brcm,bcm7445-hif-continuation", "syscon";
+ reg = <0x452000 0x100>;
+ };
+ };
+
+Lastly, nodes that allow for support of SMP initialization and reboot are
+required:
+
+smpboot
+-------
+Required properties:
+
+ - compatible
+ The string "brcm,brcmstb-smpboot".
+
+ - syscon-cpu
+ A phandle / integer array property which lets the BSP know the location
+ of certain CPU power-on registers.
+
+ The layout of the property is as follows:
+ o a phandle to the "hif_cpubiuctrl" syscon node
+ o offset to the base CPU power zone register
+ o offset to the base CPU reset register
+
+ - syscon-cont
+ A phandle pointing to the syscon node which describes the CPU boot
+ continuation registers.
+ o a phandle to the "hif_continuation" syscon node
+
+example:
+ smpboot {
+ compatible = "brcm,brcmstb-smpboot";
+ syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
+ syscon-cont = <&hif_continuation>;
+ };
+
+reboot
+-------
+Required properties
+
+ - compatible
+ The string property "brcm,brcmstb-reboot".
+
+ - syscon
+ A phandle / integer array that points to the syscon node which describes
+ the general system reset registers.
+ o a phandle to "sun_top_ctrl"
+ o offset to the "reset source enable" register
+ o offset to the "software master reset" register
+
+example:
+ reboot {
+ compatible = "brcm,brcmstb-reboot";
+ syscon = <&sun_top_ctrl 0x304 0x308>;
+ };
--
1.7.1
^ permalink raw reply related
* [PATCH v4 5/8] ARM: brcmstb: add CPU binding for Broadcom Brahma15
From: Marc Carino @ 2014-01-17 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389986367-4010-1-git-send-email-marc.ceeeee@gmail.com>
Add the Broadcom Brahma B15 CPU to the DT CPU binding list.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 9130435..0cd1e25 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -163,6 +163,7 @@ nodes to be present and contain the properties described below.
"arm,cortex-r4"
"arm,cortex-r5"
"arm,cortex-r7"
+ "brcm,brahma-b15"
"faraday,fa526"
"intel,sa110"
"intel,sa1100"
--
1.7.1
^ permalink raw reply related
* [PATCH v4 4/8] ARM: do CPU-specific init for Broadcom Brahma15 cores
From: Marc Carino @ 2014-01-17 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389986367-4010-1-git-send-email-marc.ceeeee@gmail.com>
Perform any CPU-specific initialization required on the
Broadcom Brahma-15 core.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/mm/proc-v7.S | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index bd17819..98ea423 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -193,6 +193,7 @@ __v7_cr7mp_setup:
b 1f
__v7_ca7mp_setup:
__v7_ca15mp_setup:
+__v7_b15mp_setup:
mov r10, #0
1:
#ifdef CONFIG_SMP
@@ -494,6 +495,16 @@ __v7_ca15mp_proc_info:
.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
/*
+ * Broadcom Corporation Brahma-B15 processor.
+ */
+ .type __v7_b15mp_proc_info, #object
+__v7_b15mp_proc_info:
+ .long 0x420f00f0
+ .long 0xff0ffff0
+ __v7_proc __v7_b15mp_setup, hwcaps = HWCAP_IDIV
+ .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
+
+ /*
* Qualcomm Inc. Krait processors.
*/
.type __krait_proc_info, #object
--
1.7.1
^ permalink raw reply related
* [PATCH v4 3/8] ARM: brcmstb: add debug UART for earlyprintk support
From: Marc Carino @ 2014-01-17 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389986367-4010-1-git-send-email-marc.ceeeee@gmail.com>
Add the UART definitions needed to support earlyprintk on brcmstb machines.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/Kconfig.debug | 16 +++++++++++++++-
1 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5765abf..266c699 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -94,6 +94,17 @@ choice
depends on ARCH_BCM2835
select DEBUG_UART_PL01X
+ config DEBUG_BRCMSTB_UART
+ bool "Use BRCMSTB UART for low-level debug"
+ depends on ARCH_BRCMSTB
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the first serial port on these devices.
+
+ If you have a Broadcom STB chip and would like early print
+ messages to appear over the UART, select this option.
+
config DEBUG_CLPS711X_UART1
bool "Kernel low-level debugging messages via UART1"
depends on ARCH_CLPS711X
@@ -988,6 +999,7 @@ config DEBUG_UART_PHYS
default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
default 0x20201000 if DEBUG_BCM2835
+ default 0xf0406b00 if DEBUG_BRCMSTB_UART
default 0x4000e400 if DEBUG_LL_UART_EFM32
default 0x40090000 if ARCH_LPC32XX
default 0x40100000 if DEBUG_PXA_UART1
@@ -1029,6 +1041,7 @@ config DEBUG_UART_VIRT
default 0xf0009000 if DEBUG_CNS3XXX
default 0xf01fb000 if DEBUG_NOMADIK_UART
default 0xf0201000 if DEBUG_BCM2835
+ default 0xfc406b00 if DEBUG_BRCMSTB_UART
default 0xf11f1000 if ARCH_VERSATILE
default 0xf1600000 if ARCH_INTEGRATOR
default 0xf1c28000 if DEBUG_SUNXI_UART0
@@ -1091,7 +1104,8 @@ config DEBUG_UART_8250_WORD
default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
ARCH_KEYSTONE || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
- DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1
+ DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \
+ DEBUG_BRCMSTB_UART
config DEBUG_UART_8250_FLOW_CONTROL
bool "Enable flow control for 8250 UART"
--
1.7.1
^ permalink raw reply related
* [PATCH v4 2/8] power: reset: Add reboot driver for brcmstb
From: Marc Carino @ 2014-01-17 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389986367-4010-1-git-send-email-marc.ceeeee@gmail.com>
Add support for reboot functionality on boards with ARM-based
Broadcom STB chipsets.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
---
drivers/power/reset/Kconfig | 10 +++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/brcmstb-reboot.c | 120 ++++++++++++++++++++++++++++++++++
3 files changed, 131 insertions(+), 0 deletions(-)
create mode 100644 drivers/power/reset/brcmstb-reboot.c
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 9b3ea53..31b468b 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -6,6 +6,16 @@ menuconfig POWER_RESET
Say Y here to enable board reset and power off
+config POWER_RESET_BRCMSTB
+ bool "Broadcom STB reset driver"
+ depends on POWER_RESET && ARCH_BRCMSTB
+ help
+ This driver provides restart support for ARM-based Broadcom STB
+ boards.
+
+ Say Y here if you have an ARM-based Broadcom STB board and you wish
+ to have restart support.
+
config POWER_RESET_GPIO
bool "GPIO power-off driver"
depends on OF_GPIO && POWER_RESET
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 3e6ed88..806d056 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o
obj-$(CONFIG_POWER_RESET_XGENE) += xgene-reboot.o
+obj-$(CONFIG_POWER_RESET_BRCMSTB) += brcmstb-reboot.o
diff --git a/drivers/power/reset/brcmstb-reboot.c b/drivers/power/reset/brcmstb-reboot.c
new file mode 100644
index 0000000..3f23692
--- /dev/null
+++ b/drivers/power/reset/brcmstb-reboot.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/printk.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+#include <linux/smp.h>
+#include <linux/mfd/syscon.h>
+
+#include <asm/system_misc.h>
+
+#define RESET_SOURCE_ENABLE_REG 1
+#define SW_MASTER_RESET_REG 2
+
+static struct regmap *regmap;
+static u32 rst_src_en;
+static u32 sw_mstr_rst;
+
+static void brcmstb_reboot(enum reboot_mode mode, const char *cmd)
+{
+ int rc;
+ u32 tmp;
+
+ rc = regmap_write(regmap, rst_src_en, 1);
+ if (rc) {
+ pr_err("failed to write rst_src_en (%d)\n", rc);
+ return;
+ }
+
+ rc = regmap_read(regmap, rst_src_en, &tmp);
+ if (rc) {
+ pr_err("failed to read rst_src_en (%d)\n", rc);
+ return;
+ }
+
+ rc = regmap_write(regmap, sw_mstr_rst, 1);
+ if (rc) {
+ pr_err("failed to write sw_mstr_rst (%d)\n", rc);
+ return;
+ }
+
+ rc = regmap_read(regmap, sw_mstr_rst, &tmp);
+ if (rc) {
+ pr_err("failed to read sw_mstr_rst (%d)\n", rc);
+ return;
+ }
+
+ while (1)
+ ;
+}
+
+static int brcmstb_reboot_probe(struct platform_device *pdev)
+{
+ int rc;
+ struct device_node *np = pdev->dev.of_node;
+
+ regmap = syscon_regmap_lookup_by_phandle(np, "syscon");
+ if (IS_ERR(regmap)) {
+ pr_err("failed to get syscon phandle\n");
+ return -EINVAL;
+ }
+
+ rc = of_property_read_u32_index(np, "syscon", RESET_SOURCE_ENABLE_REG,
+ &rst_src_en);
+ if (rc) {
+ pr_err("can't get rst_src_en offset (%d)\n", rc);
+ return -EINVAL;
+ }
+
+ rc = of_property_read_u32_index(np, "syscon", SW_MASTER_RESET_REG,
+ &sw_mstr_rst);
+ if (rc) {
+ pr_err("can't get sw_mstr_rst offset (%d)\n", rc);
+ return -EINVAL;
+ }
+
+ arm_pm_restart = brcmstb_reboot;
+
+ return 0;
+}
+
+static const struct of_device_id of_match[] = {
+ { .compatible = "brcm,brcmstb-reboot", },
+ {},
+};
+
+static struct platform_driver brcmstb_reboot_driver = {
+ .probe = brcmstb_reboot_probe,
+ .driver = {
+ .name = "brcmstb-reboot",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match,
+ },
+};
+
+static int __init brcmstb_reboot_init(void)
+{
+ return platform_driver_probe(&brcmstb_reboot_driver,
+ brcmstb_reboot_probe);
+}
+subsys_initcall(brcmstb_reboot_init);
--
1.7.1
^ permalink raw reply related
* [PATCH v4 1/8] ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
From: Marc Carino @ 2014-01-17 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389986367-4010-1-git-send-email-marc.ceeeee@gmail.com>
The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes.
This patch adds machine support for the ARM-based Broadcom SoCs.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/mach-bcm/Kconfig | 14 ++
arch/arm/mach-bcm/Makefile | 4 +
arch/arm/mach-bcm/brcmstb.c | 110 ++++++++++++
arch/arm/mach-bcm/brcmstb.h | 38 ++++
arch/arm/mach-bcm/headsmp-brcmstb.S | 34 ++++
arch/arm/mach-bcm/hotplug-brcmstb.c | 334 +++++++++++++++++++++++++++++++++++
7 files changed, 535 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-bcm/brcmstb.c
create mode 100644 arch/arm/mach-bcm/brcmstb.h
create mode 100644 arch/arm/mach-bcm/headsmp-brcmstb.S
create mode 100644 arch/arm/mach-bcm/hotplug-brcmstb.c
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index c1df4e9..7028d11 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -7,6 +7,7 @@ CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_XP=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BRCMSTB=y
CONFIG_GPIO_PCA953X=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_KEYSTONE=y
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 9fe6d88..2c1ae83 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -31,6 +31,20 @@ config ARCH_BCM_MOBILE
BCM11130, BCM11140, BCM11351, BCM28145 and
BCM28155 variants.
+config ARCH_BRCMSTB
+ bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
+ depends on MMU
+ select ARM_GIC
+ select MIGHT_HAVE_PCI
+ select HAVE_SMP
+ select HAVE_ARM_ARCH_TIMER
+ help
+ Say Y if you intend to run the kernel on a Broadcom ARM-based STB
+ chipset.
+
+ This enables support for Broadcom ARM-based set-top box chipsets,
+ including the 7445 family of chips.
+
endmenu
endif
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index c2ccd5a..b744a12 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -13,3 +13,7 @@
obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec)
+
+obj-$(CONFIG_ARCH_BRCMSTB) := brcmstb.o
+obj-$(CONFIG_SMP) += headsmp-brcmstb.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug-brcmstb.o
diff --git a/arch/arm/mach-bcm/brcmstb.c b/arch/arm/mach-bcm/brcmstb.c
new file mode 100644
index 0000000..7a6093d
--- /dev/null
+++ b/arch/arm/mach-bcm/brcmstb.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/console.h>
+#include <linux/clocksource.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/printk.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+#include "brcmstb.h"
+
+/***********************************************************************
+ * STB CPU (main application processor)
+ ***********************************************************************/
+
+static const char *brcmstb_match[] __initconst = {
+ "brcm,bcm7445",
+ "brcm,brcmstb",
+ NULL
+};
+
+static void __init brcmstb_init_early(void)
+{
+ add_preferred_console("ttyS", 0, "115200");
+}
+
+/***********************************************************************
+ * SMP boot
+ ***********************************************************************/
+
+#ifdef CONFIG_SMP
+static DEFINE_SPINLOCK(boot_lock);
+
+static void __cpuinit brcmstb_secondary_init(unsigned int cpu)
+{
+ /*
+ * Synchronise with the boot thread.
+ */
+ spin_lock(&boot_lock);
+ spin_unlock(&boot_lock);
+}
+
+static int __cpuinit brcmstb_boot_secondary(unsigned int cpu,
+ struct task_struct *idle)
+{
+ /*
+ * set synchronisation state between this boot processor
+ * and the secondary one
+ */
+ spin_lock(&boot_lock);
+
+ /* Bring up power to the core if necessary */
+ if (brcmstb_cpu_get_power_state(cpu) == 0)
+ brcmstb_cpu_power_on(cpu);
+
+ brcmstb_cpu_boot(cpu);
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+
+ return 0;
+}
+
+struct smp_operations brcmstb_smp_ops __initdata = {
+ .smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
+ .smp_secondary_init = brcmstb_secondary_init,
+ .smp_boot_secondary = brcmstb_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_kill = brcmstb_cpu_kill,
+ .cpu_die = brcmstb_cpu_die,
+#endif
+};
+#endif
+
+DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
+ .dt_compat = brcmstb_match,
+#ifdef CONFIG_SMP
+ .smp = smp_ops(brcmstb_smp_ops),
+#endif
+ .init_early = brcmstb_init_early,
+MACHINE_END
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
new file mode 100644
index 0000000..e49bde6
--- /dev/null
+++ b/arch/arm/mach-bcm/brcmstb.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BRCMSTB_H__
+#define __BRCMSTB_H__
+
+#if !defined(__ASSEMBLY__)
+#include <linux/smp.h>
+#endif
+
+#if !defined(__ASSEMBLY__)
+extern void brcmstb_secondary_startup(void);
+extern void brcmstb_cpu_boot(unsigned int cpu);
+extern void brcmstb_cpu_power_on(unsigned int cpu);
+extern int brcmstb_cpu_get_power_state(unsigned int cpu);
+extern struct smp_operations brcmstb_smp_ops;
+#if defined(CONFIG_HOTPLUG_CPU)
+extern void brcmstb_cpu_die(unsigned int cpu);
+extern int brcmstb_cpu_kill(unsigned int cpu);
+void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus);
+#else
+static inline void brcmstb_cpu_die(unsigned int cpu) {}
+static inline int brcmstb_cpu_kill(unsigned int cpu) {}
+static inline void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus) {}
+#endif
+#endif
+
+#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
new file mode 100644
index 0000000..57ec438
--- /dev/null
+++ b/arch/arm/mach-bcm/headsmp-brcmstb.S
@@ -0,0 +1,34 @@
+/*
+ * SMP boot code for secondary CPUs
+ * Based on arch/arm/mach-tegra/headsmp.S
+ *
+ * Copyright (C) 2010 NVIDIA, Inc.
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/assembler.h>
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ .section ".text.head", "ax"
+ __CPUINIT
+
+ENTRY(brcmstb_secondary_startup)
+ /*
+ * Ensure CPU is in a sane state by disabling all IRQs and switching
+ * into SVC mode.
+ */
+ setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
+
+ bl v7_invalidate_l1
+ b secondary_startup
+ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-bcm/hotplug-brcmstb.c b/arch/arm/mach-bcm/hotplug-brcmstb.c
new file mode 100644
index 0000000..ff4a732
--- /dev/null
+++ b/arch/arm/mach-bcm/hotplug-brcmstb.c
@@ -0,0 +1,334 @@
+/*
+ * Broadcom STB CPU hotplug support for ARM
+ *
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/printk.h>
+#include <linux/regmap.h>
+#include <linux/smp.h>
+#include <linux/mfd/syscon.h>
+
+#include <asm/cacheflush.h>
+#include <asm/mach-types.h>
+
+#include "brcmstb.h"
+
+enum {
+ ZONE_MAN_CLKEN_MASK = BIT(0),
+ ZONE_MAN_RESET_CNTL_MASK = BIT(1),
+ ZONE_MAN_MEM_PWR_MASK = BIT(4),
+ ZONE_RESERVED_1_MASK = BIT(5),
+ ZONE_MAN_ISO_CNTL_MASK = BIT(6),
+ ZONE_MANUAL_CONTROL_MASK = BIT(7),
+ ZONE_PWR_DN_REQ_MASK = BIT(9),
+ ZONE_PWR_UP_REQ_MASK = BIT(10),
+ ZONE_BLK_RST_ASSERT_MASK = BIT(10),
+ ZONE_PWR_OFF_STATE_MASK = BIT(26),
+ ZONE_PWR_ON_STATE_MASK = BIT(26),
+ ZONE_DPG_PWR_STATE_MASK = BIT(28),
+ ZONE_MEM_PWR_STATE_MASK = BIT(29),
+ ZONE_RESET_STATE_MASK = BIT(31),
+};
+
+static void __iomem *cpubiuctrl_block;
+static void __iomem *hif_cont_block;
+static u32 cpu0_pwr_zone_ctrl_reg;
+static u32 cpu_rst_cfg_reg;
+static u32 hif_cont_reg;
+DEFINE_PER_CPU(int, per_cpu_sw_state);
+
+static void __iomem *pwr_ctrl_get_base(unsigned int cpu)
+{
+ void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
+ base += (cpu * 4);
+ return base;
+}
+
+static u32 pwr_ctrl_rd(unsigned int cpu)
+{
+ void __iomem *base = pwr_ctrl_get_base(cpu);
+ return readl_relaxed(base);
+}
+
+static void pwr_ctrl_wr(unsigned int cpu, u32 val)
+{
+ void __iomem *base = pwr_ctrl_get_base(cpu);
+ writel(val, base);
+}
+
+static void cpu_rst_cfg_set(int cpu, int set)
+{
+ u32 val;
+ val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
+ if (set)
+ val |= BIT(cpu);
+ else
+ val &= ~BIT(cpu);
+ writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
+}
+
+static void cpu_set_boot_addr(int cpu, unsigned long boot_addr)
+{
+ const int reg_ofs = cpu * 8;
+ writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
+ writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
+}
+
+void brcmstb_cpu_boot(unsigned int cpu)
+{
+ pr_info("SMP: Booting CPU%d...\n", cpu);
+
+ /*
+ * set the reset vector to point to the secondary_startup
+ * routine
+ */
+ cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
+
+ flush_cache_all();
+
+ /* unhalt the cpu */
+ cpu_rst_cfg_set(cpu, 0);
+}
+
+void brcmstb_cpu_power_on(unsigned int cpu)
+{
+ /*
+ * The secondary cores power was cut, so we must go through
+ * power-on initialization.
+ */
+ u32 tmp;
+
+ pr_info("SMP: Powering up CPU%d...\n", cpu);
+
+ /* Request zone power up */
+ pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
+
+ /* Wait for the power up FSM to complete */
+ do {
+ tmp = pwr_ctrl_rd(cpu);
+ } while (!(tmp & ZONE_PWR_ON_STATE_MASK));
+
+ per_cpu(per_cpu_sw_state, cpu) = 1;
+}
+
+int brcmstb_cpu_get_power_state(unsigned int cpu)
+{
+ int tmp = pwr_ctrl_rd(cpu);
+ return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
+}
+
+void __ref brcmstb_cpu_die(unsigned int cpu)
+{
+ /* Derived from misc_bpcm_arm.c */
+
+ /* Clear SCTLR.C bit */
+ __asm__(
+ "mrc p15, 0, r0, c1, c0, 0\n"
+ "bic r0, r0, #(1 << 2)\n"
+ "mcr p15, 0, r0, c1, c0, 0\n"
+ : /* no output */
+ : /* no input */
+ : "r0" /* clobber r0 */
+ );
+
+ /*
+ * Instruction barrier to ensure cache is really disabled before
+ * cleaning/invalidating the caches
+ */
+ isb();
+
+ flush_cache_all();
+
+ /* Invalidate all instruction caches to PoU (ICIALLU) */
+ /* Data sync. barrier to ensure caches have emptied out */
+ __asm__("mcr p15, 0, r0, c7, c5, 0\n" : : : "r0");
+ dsb();
+
+ /*
+ * Clear ACTLR.SMP bit to prevent broadcast TLB messages from reaching
+ * this core
+ */
+ __asm__(
+ "mrc p15, 0, r0, c1, c0, 1\n"
+ "bic r0, r0, #(1 << 6)\n"
+ "mcr p15, 0, r0, c1, c0, 1\n"
+ : /* no output */
+ : /* no input */
+ : "r0" /* clobber r0 */
+ );
+
+ /* Disable all IRQs for this CPU */
+ arch_local_irq_disable();
+
+ per_cpu(per_cpu_sw_state, cpu) = 0;
+
+ /*
+ * Final full barrier to ensure everything before this instruction has
+ * quiesced.
+ */
+ isb();
+ dsb();
+
+ /* Sit and wait to die */
+ wfi();
+
+ /* We should never get here... */
+ nop();
+ panic("Spurious interrupt on CPU %d received!\n", cpu);
+}
+
+int brcmstb_cpu_kill(unsigned int cpu)
+{
+ u32 tmp;
+
+ pr_info("SMP: Powering down CPU%d...\n", cpu);
+
+ while (per_cpu(per_cpu_sw_state, cpu))
+ ;
+
+ /* Program zone reset */
+ pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
+ ZONE_PWR_DN_REQ_MASK);
+
+ /* Verify zone reset */
+ tmp = pwr_ctrl_rd(cpu);
+ if (!(tmp & ZONE_RESET_STATE_MASK))
+ pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
+ __func__, cpu);
+
+ /* Wait for power down */
+ do {
+ tmp = pwr_ctrl_rd(cpu);
+ } while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
+
+ /* Settle-time from Broadcom-internal DVT reference code */
+ udelay(7);
+
+ /* Assert reset on the CPU */
+ cpu_rst_cfg_set(cpu, 1);
+
+ return 1;
+}
+
+static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
+{
+ int rc = 0;
+ char *name;
+ int index;
+ struct device_node *syscon_np = NULL;
+
+ name = "syscon-cpu";
+
+ syscon_np = of_parse_phandle(np, name, 0);
+ if (!syscon_np) {
+ pr_err("can't find phandle %s\n", name);
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+ cpubiuctrl_block = of_iomap(syscon_np, 0);
+ if (!cpubiuctrl_block) {
+ pr_err("iomap failed for cpubiuctrl_block\n");
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+ index = 1;
+ rc = of_property_read_u32_index(np, name, index,
+ &cpu0_pwr_zone_ctrl_reg);
+ if (rc) {
+ pr_err("failed to read %d from %s property (%d)\n", index, name,
+ rc);
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+ index = 2;
+ rc = of_property_read_u32_index(np, name, index, &cpu_rst_cfg_reg);
+ if (rc) {
+ pr_err("failed to read %d from %s property (%d)\n", index, name,
+ rc);
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+cleanup:
+ if (syscon_np)
+ of_node_put(syscon_np);
+
+ return rc;
+}
+
+static int __init setup_hifcont_regs(struct device_node *np)
+{
+ int rc = 0;
+ char *name;
+ struct device_node *syscon_np = NULL;
+
+ name = "syscon-cont";
+
+ syscon_np = of_parse_phandle(np, name, 0);
+ if (!syscon_np) {
+ pr_err("can't find phandle %s\n", name);
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+ hif_cont_block = of_iomap(syscon_np, 0);
+ if (!hif_cont_block) {
+ pr_err("iomap failed for hif_cont_block\n");
+ rc = -EINVAL;
+ goto cleanup;
+ }
+
+ /* offset is@top of hif_cont_block */
+ hif_cont_reg = 0;
+
+cleanup:
+ if (syscon_np)
+ of_node_put(syscon_np);
+
+ return rc;
+}
+
+void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
+{
+ int rc;
+ struct device_node *np;
+ char *name;
+
+ name = "brcm,brcmstb-smpboot";
+ np = of_find_compatible_node(NULL, NULL, name);
+ if (!np) {
+ pr_err("can't find compatible node %s\n", name);
+ return;
+ }
+
+ rc = setup_hifcpubiuctrl_regs(np);
+ if (rc)
+ return;
+
+ rc = setup_hifcont_regs(np);
+ if (rc)
+ return;
+}
+
--
1.7.1
^ permalink raw reply related
* [PATCH v4 0/8] ARM: brcmstb: Add Broadcom STB SoC support
From: Marc Carino @ 2014-01-17 19:19 UTC (permalink / raw)
To: linux-arm-kernel
This patchset contains the board support package for the
Broadcom BCM7445 ARM-based SoC [1]. These changes contain a
minimal set of code needed for a BCM7445-based board to boot
the Linux kernel.
These changes heavily leverage the OF/devicetree framework.
v4:
- make a reboot driver and put it in the drivers folder
- rework DT bindings to leverage 'syscon'
- rework BSP code to use 'syscon' for all register mappings
- misc. tweaks per suggestions from v3
v3:
- rebased to v3.13-rc8
- switched to using 'multi_v7_defconfig'
- eliminated dependence on compile-time peripheral register access
- moved DT node iomap out from 'init_early'
- misc. minor cleanups from mailing-list discussion for v2
v2:
- rebased to v3.13-rc1
- moved implementation to 'mach-bcm' folder
- added CPU init for B15
v1:
- initial submission
[1] http://www.broadcom.com/products/Cable/Cable-Set-Top-Box-Solutions/BCM7445
Marc Carino (8):
ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
power: reset: Add reboot driver for brcmstb
ARM: brcmstb: add debug UART for earlyprintk support
ARM: do CPU-specific init for Broadcom Brahma15 cores
ARM: brcmstb: add CPU binding for Broadcom Brahma15
ARM: brcmstb: add misc. DT bindings for brcmstb
ARM: brcmstb: gic: add compatible string for Broadcom Brahma15
ARM: brcmstb: dts: add a reference DTS for Broadcom 7445
.../devicetree/bindings/arm/brcm-brcmstb.txt | 95 ++++++
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
Documentation/devicetree/bindings/arm/gic.txt | 1 +
arch/arm/Kconfig.debug | 16 +-
arch/arm/boot/dts/bcm7445.dts | 111 +++++++
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/mach-bcm/Kconfig | 14 +
arch/arm/mach-bcm/Makefile | 4 +
arch/arm/mach-bcm/brcmstb.c | 110 +++++++
arch/arm/mach-bcm/brcmstb.h | 38 +++
arch/arm/mach-bcm/headsmp-brcmstb.S | 34 ++
arch/arm/mach-bcm/hotplug-brcmstb.c | 334 ++++++++++++++++++++
arch/arm/mm/proc-v7.S | 11 +
drivers/power/reset/Kconfig | 10 +
drivers/power/reset/Makefile | 1 +
drivers/power/reset/brcmstb-reboot.c | 120 +++++++
16 files changed, 900 insertions(+), 1 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
create mode 100644 arch/arm/boot/dts/bcm7445.dts
create mode 100644 arch/arm/mach-bcm/brcmstb.c
create mode 100644 arch/arm/mach-bcm/brcmstb.h
create mode 100644 arch/arm/mach-bcm/headsmp-brcmstb.S
create mode 100644 arch/arm/mach-bcm/hotplug-brcmstb.c
create mode 100644 drivers/power/reset/brcmstb-reboot.c
^ permalink raw reply
* More GPIO madness on iMX6 - and the crappy ARM port of Linux
From: Eric Nelson @ 2014-01-17 19:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140117184731.GE15937@n2100.arm.linux.org.uk>
Hi Russell,
On 01/17/2014 11:47 AM, Russell King - ARM Linux wrote:
> So, we have this wonderful GPIO layer which abstracts GPIO stuff and
> hides stuff. It's really wonderful, because you don't have to care
> about how the GPIOs are actually accessed in drivers anymore.
>
> However, what about the behaviour of GPIOs?
>
> What about... for example... this sequence:
>
> gpio_direction_output(gpio, 1);
> val = gpio_get_value(gpio);
>
> What value is "val"? More importantly, what value is reflected in
> /sys/kernel/debug/gpio ? Would it indicate that it's high or low?
>
> Now, while you can make reasonable assumptions, such as "it'll return
> that the output is being driven to the requested state" or "it'll
> return the actual state of the pin", what about this instead, which
> happens on iMX hardware - "it'll _always_ return zero".
>
> Yes, iMX6 at least has this behaviour. For any output, val as above
> will always be zero, and /proc/sys/kernel/debug/gpio will always
> report that an output is zero... unless the SION bit has been set for
> that GPIO signal.
>
> The reason is that on hardware such as iMX6, reading the GPIO is done
> by reading the pad state register, and this register is _only_ supplied
> the state of the pad when the input path is enabled. The input path
> is only enabled when the output is disabled, or the SION bit is set
> to force the GPIO input path.
>
> So, this brings up three obvious questions:
>
> 1. What should gpio_get_value() return for an output?
It seems that this is pretty well specified.
To quote Documentation/gpio/gpio-legacy.txt:
>> When reading the value of an output pin, the value
>> returned should be what's seen on the pin ... that
>> won't always match the specified output value, because
>> of issues including open-drain signaling and output
>> latencies.
Documentation/gpio/gpio.txt is a little less clear, but implies
the same:
>> If you are "driving" the signal high but
>> gpiod_get_value(gpio) reports a low value (after
>> the appropriate rise time passes), you know some other
>> component is driving the shared signal low
> 2. What should be reported in /sys/kernel/debug/gpio for an output?
> 3. Should iMX6 (and similar) GPIOs always have the SION bit set in
> their DT descriptions?
>
> Discuss.
>
Each signal accessed using the GPIO subsystem **must** have
the SION bit set and the values returned should be the value
from the PSR registers.
Regards,
Eric
^ permalink raw reply
* [PATCH 3/4] spi: sunxi: Add Allwinner A31 SPI controller driver
From: Mark Brown @ 2014-01-17 19:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140116211201.GC3351@lukather>
On Thu, Jan 16, 2014 at 10:12:01PM +0100, Maxime Ripard wrote:
> On Thu, Jan 16, 2014 at 07:40:03PM +0000, Mark Brown wrote:
> > > + if (status & SUN6I_INT_CTL_RF_OVF) {
> > > + sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
> > > + sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_OVF);
> > > + return IRQ_HANDLED;
> > > + }
> > This looks like an overflow - a log message would be helpful for users
> > and you should possibly be flagging an error on the current transfer.
> Hmmm, that was an attempt at receiving more bytes than the FIFO can
> handle, but I guess the FIFO full interrupt would be more appropriate
> for this.
If you've got an overflow interrupt that suggests that the data is
already corrupted, assuming the interrupt isn't misnamed.
> > > + ret = clk_set_rate(sspi->mclk, 100000000);
> > > + if (ret) {
> > > + dev_err(&pdev->dev, "Couldn't change module clock rate\n");
> > > + goto err2;
> > > + }
> > Does this really need to be fatal (or done at all)? There seems to be
> > another reasonably flexible divider in the IP and it's more common to
> > either set this per transfer to something that rounds nicely or just use
> > the default and rely on the dividers.
> The default parent of the module clock runs at 24MHz, that means that
> we won't be able to reach a spi clock higher than 12MHz, which seems
> quite low. We can always change the rate in the transfer setup code
> though, if needs be.
12MHz is actually quite a common limit for SPI interfaces (half of a
24MHz master clock like the IP itself has) but yeah, you want to go
higher if you can. Doing it on transfer setup is going to mean that
you save a little power when you don't need the extra speed too.
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^ permalink raw reply
* [PATCH] ARM: kirkwood: kirkwood_pm_init() should return void
From: Ezequiel Garcia @ 2014-01-17 18:52 UTC (permalink / raw)
To: linux-arm-kernel
This function was originally meant to return void as declared in the
common.h header. Fix it and include the header to catch these errors
in the future.
Reported-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
---
arch/arm/mach-kirkwood/pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-kirkwood/pm.c b/arch/arm/mach-kirkwood/pm.c
index 8783a71..c11f7f5 100644
--- a/arch/arm/mach-kirkwood/pm.c
+++ b/arch/arm/mach-kirkwood/pm.c
@@ -18,6 +18,7 @@
#include <linux/suspend.h>
#include <linux/io.h>
#include <mach/bridge-regs.h>
+#include "common.h"
static void __iomem *ddr_operation_base;
@@ -65,7 +66,7 @@ static const struct platform_suspend_ops kirkwood_suspend_ops = {
.valid = kirkwood_pm_valid_standby,
};
-int __init kirkwood_pm_init(void)
+void __init kirkwood_pm_init(void)
{
ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4);
suspend_set_ops(&kirkwood_suspend_ops);
--
1.8.1.5
^ permalink raw reply related
* [PATCH v3] ACPI: introduce CONFIG_ACPI_REDUCED_HARDWARE_ONLY to enable this ACPI mode
From: al.stone at linaro.org @ 2014-01-17 18:51 UTC (permalink / raw)
To: linux-arm-kernel
From: Al Stone <al.stone@linaro.org>
ACPI hardware reduced mode exists to allow newer platforms to use a
simpler form of ACPI that does not require supporting legacy versions
of the specification and their associated hardware. This mode was
introduced in the ACPI 5.0 specification.
To enable the hardware reduced mode of ACPI, we need to set the flag
ACPI_REDUCED_HARDWARE to TRUE in the ACPICA source. In order to do
that, we introduce a kernel configuration item to enable or disable
ACPI_REDUCED_HARDWARE. We can then change the kernel configuration
instead of having to modify the kernel source.
Introducing this configuration item is based on suggestions from Lv
Zheng saying that this does not belong in ACPICA, but rather to the
Linux kernel itself. Hence, we introduce this configuration item so
that we can make ACPI_REDUCED_HARDWARE configurable. For the details
of the discussion, please refer to:
http://www.spinics.net/lists/linux-acpi/msg46369.html
Changes for v3:
-- Minimize the changelog.
Changes for v2:
-- Changed test for EXPERT to avoid reported Kconfig warning
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: Al Stone <al.stone@linaro.org>
---
drivers/acpi/Kconfig | 13 +++++++++++++
include/acpi/platform/aclinux.h | 6 ++++++
2 files changed, 19 insertions(+)
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index 4770de5..9fd6a7a 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -343,6 +343,19 @@ config ACPI_BGRT
data from the firmware boot splash. It will appear under
/sys/firmware/acpi/bgrt/ .
+config ACPI_REDUCED_HARDWARE_ONLY
+ bool "Hardware-reduced ACPI support only" if EXPERT
+ def_bool n
+ depends on ACPI
+ help
+ This config item changes the way the ACPI code is built. When this
+ option is selected, the kernel will use a specialized version of
+ ACPICA that ONLY supports the ACPI "reduced hardware" mode. The
+ resulting kernel will be smaller but it will also be restricted to
+ running in ACPI reduced hardware mode ONLY.
+
+ If you are unsure what to do, do not enable this option.
+
source "drivers/acpi/apei/Kconfig"
config ACPI_EXTLOG
diff --git a/include/acpi/platform/aclinux.h b/include/acpi/platform/aclinux.h
index 28f4f4d..7d71f08 100644
--- a/include/acpi/platform/aclinux.h
+++ b/include/acpi/platform/aclinux.h
@@ -52,6 +52,12 @@
#ifdef __KERNEL__
+/* Compile for reduced hardware mode only with this kernel config */
+
+#ifdef CONFIG_ACPI_REDUCED_HARDWARE_ONLY
+#define ACPI_REDUCED_HARDWARE 1
+#endif
+
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/ctype.h>
--
1.8.4.2
^ permalink raw reply related
* [PATCH] pwm: Remove obsolete HAVE_PWM Kconfig symbol
From: Eric Miao @ 2014-01-17 18:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389884494-13729-1-git-send-email-s.hauer@pengutronix.de>
On Thu, Jan 16, 2014 at 7:01 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> Before we had the PWM framework we used to have a barebone PWM api. The
> HAVE_PWM Kconfig symbol used to be selected by the PWM drivers to specify
> the PWM API is present in the kernel. Since the last legacy driver is gone
> the HAVE_PWM symbol can go aswell.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Looks good to me, happy to see it gone.
> ---
>
> I suggest that Thierry as PWM Maintainer takes the patch through his tree.
> Is that ok for you Thierry?
>
> arch/arm/Kconfig | 4 ----
> arch/arm/mach-pxa/Kconfig | 15 ---------------
> arch/mips/Kconfig | 1 -
> drivers/input/misc/Kconfig | 4 ++--
> include/linux/pwm.h | 2 +-
> 5 files changed, 3 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index c1f1a7e..1b6f499 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -109,9 +109,6 @@ config ARM_DMA_IOMMU_ALIGNMENT
>
> endif
>
> -config HAVE_PWM
> - bool
> -
> config MIGHT_HAVE_PCI
> bool
>
> @@ -606,7 +603,6 @@ config ARCH_LPC32XX
> select CPU_ARM926T
> select GENERIC_CLOCKEVENTS
> select HAVE_IDE
> - select HAVE_PWM
> select USB_ARCH_HAS_OHCI
> select USE_OF
> help
> diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
> index 96100db..b96244c 100644
> --- a/arch/arm/mach-pxa/Kconfig
> +++ b/arch/arm/mach-pxa/Kconfig
> @@ -7,7 +7,6 @@ comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
> config MACH_PXA3XX_DT
> bool "Support PXA3xx platforms from device tree"
> select CPU_PXA300
> - select HAVE_PWM
> select POWER_SUPPLY
> select PXA3xx
> select USE_OF
> @@ -23,12 +22,10 @@ config ARCH_LUBBOCK
>
> config MACH_MAINSTONE
> bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
> - select HAVE_PWM
> select PXA27x
>
> config MACH_ZYLONITE
> bool
> - select HAVE_PWM
> select PXA3xx
>
> config MACH_ZYLONITE300
> @@ -69,7 +66,6 @@ config ARCH_PXA_IDP
> config ARCH_VIPER
> bool "Arcom/Eurotech VIPER SBC"
> select ARCOM_PCMCIA
> - select HAVE_PWM
> select I2C_GPIO
> select ISA
> select PXA25x
> @@ -120,7 +116,6 @@ config MACH_CM_X300
> bool "CompuLab CM-X300 modules"
> select CPU_PXA300
> select CPU_PXA310
> - select HAVE_PWM
> select PXA3xx
>
> config MACH_CAPC7117
> @@ -211,7 +206,6 @@ config TRIZEPS_PCMCIA
>
> config MACH_LOGICPD_PXA270
> bool "LogicPD PXA270 Card Engine Development Platform"
> - select HAVE_PWM
> select PXA27x
>
> config MACH_PCM027
> @@ -222,7 +216,6 @@ config MACH_PCM027
> config MACH_PCM990_BASEBOARD
> bool "PHYTEC PCM-990 development board"
> depends on MACH_PCM027
> - select HAVE_PWM
>
> choice
> prompt "display on pcm990"
> @@ -246,7 +239,6 @@ config MACH_COLIBRI
> config MACH_COLIBRI_PXA270_INCOME
> bool "Income s.r.o. PXA270 SBC"
> depends on MACH_COLIBRI
> - select HAVE_PWM
> select PXA27x
>
> config MACH_COLIBRI300
> @@ -275,7 +267,6 @@ comment "End-user Products (sorted by vendor name)"
>
> config MACH_H4700
> bool "HP iPAQ hx4700"
> - select HAVE_PWM
> select IWMMXT
> select PXA27x
>
> @@ -289,14 +280,12 @@ config MACH_HIMALAYA
>
> config MACH_MAGICIAN
> bool "Enable HTC Magician Support"
> - select HAVE_PWM
> select IWMMXT
> select PXA27x
>
> config MACH_MIOA701
> bool "Mitac Mio A701 Support"
> select GPIO_SYSFS
> - select HAVE_PWM
> select IWMMXT
> select PXA27x
> help
> @@ -306,7 +295,6 @@ config MACH_MIOA701
>
> config PXA_EZX
> bool "Motorola EZX Platform"
> - select HAVE_PWM
> select IWMMXT
> select PXA27x
>
> @@ -346,7 +334,6 @@ config MACH_MP900C
>
> config ARCH_PXA_PALM
> bool "PXA based Palm PDAs"
> - select HAVE_PWM
>
> config MACH_PALM27X
> bool
> @@ -444,7 +431,6 @@ config MACH_TREO680
> config MACH_RAUMFELD_RC
> bool "Raumfeld Controller"
> select CPU_PXA300
> - select HAVE_PWM
> select POWER_SUPPLY
> select PXA3xx
>
> @@ -608,7 +594,6 @@ config MACH_E800
>
> config MACH_ZIPIT2
> bool "Zipit Z2 Handheld"
> - select HAVE_PWM
> select PXA27x
> endmenu
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 650de39..ce62af8 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -233,7 +233,6 @@ config MACH_JZ4740
> select IRQ_CPU
> select ARCH_REQUIRE_GPIOLIB
> select SYS_HAS_EARLY_PRINTK
> - select HAVE_PWM
> select HAVE_CLK
> select GENERIC_IRQ_CHIP
>
> diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
> index 5f4967d..bc6ec8e 100644
> --- a/drivers/input/misc/Kconfig
> +++ b/drivers/input/misc/Kconfig
> @@ -156,7 +156,7 @@ config INPUT_MAX8925_ONKEY
>
> config INPUT_MAX8997_HAPTIC
> tristate "MAXIM MAX8997 haptic controller support"
> - depends on PWM && HAVE_PWM && MFD_MAX8997
> + depends on PWM && MFD_MAX8997
> select INPUT_FF_MEMLESS
> help
> This option enables device driver support for the haptic controller
> @@ -461,7 +461,7 @@ config INPUT_PCF8574
>
> config INPUT_PWM_BEEPER
> tristate "PWM beeper support"
> - depends on PWM && HAVE_PWM
> + depends on PWM
> help
> Say Y here to get support for PWM based beeper devices.
>
> diff --git a/include/linux/pwm.h b/include/linux/pwm.h
> index f0feafd..4717f54 100644
> --- a/include/linux/pwm.h
> +++ b/include/linux/pwm.h
> @@ -7,7 +7,7 @@
> struct pwm_device;
> struct seq_file;
>
> -#if IS_ENABLED(CONFIG_PWM) || IS_ENABLED(CONFIG_HAVE_PWM)
> +#if IS_ENABLED(CONFIG_PWM)
> /*
> * pwm_request - request a PWM device
> */
> --
> 1.8.5.2
>
^ permalink raw reply
* [PATCH] ARM: Make pgtbl macro more robust
From: Stephen Boyd @ 2014-01-17 18:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389015593-31716-1-git-send-email-cov@codeaurora.org>
On 01/06, Christopher Covington wrote:
> The pgtbl macro couldn't handle the specific
> (TEXT_OFFSET - PG_DIR_SIZE) value that the combination of
> MSM platforms and LPAE created:
>
> head.S:163: Error: invalid constant (203000) after fixup
>
> Regardless of whether this combination of configuration options
> will work on currently support platforms at run time, make it
> at least assemble properly.
>
> Signed-off-by: Christopher Covington <cov@codeaurora.org>
Looks good to me.
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
I think you can put it in the patch tracker. Russell?
> ---
> arch/arm/kernel/head.S | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 9cf6063..af30cac 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -52,7 +52,8 @@
> .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
>
> .macro pgtbl, rd, phys
> - add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
> + add \rd, \phys, #TEXT_OFFSET
> + sub \rd, \rd, #PG_DIR_SIZE
> .endm
>
> /*
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* More GPIO madness on iMX6 - and the crappy ARM port of Linux
From: Russell King - ARM Linux @ 2014-01-17 18:47 UTC (permalink / raw)
To: linux-arm-kernel
So, we have this wonderful GPIO layer which abstracts GPIO stuff and
hides stuff. It's really wonderful, because you don't have to care
about how the GPIOs are actually accessed in drivers anymore.
However, what about the behaviour of GPIOs?
What about... for example... this sequence:
gpio_direction_output(gpio, 1);
val = gpio_get_value(gpio);
What value is "val"? More importantly, what value is reflected in
/sys/kernel/debug/gpio ? Would it indicate that it's high or low?
Now, while you can make reasonable assumptions, such as "it'll return
that the output is being driven to the requested state" or "it'll
return the actual state of the pin", what about this instead, which
happens on iMX hardware - "it'll _always_ return zero".
Yes, iMX6 at least has this behaviour. For any output, val as above
will always be zero, and /proc/sys/kernel/debug/gpio will always
report that an output is zero... unless the SION bit has been set for
that GPIO signal.
The reason is that on hardware such as iMX6, reading the GPIO is done
by reading the pad state register, and this register is _only_ supplied
the state of the pad when the input path is enabled. The input path
is only enabled when the output is disabled, or the SION bit is set
to force the GPIO input path.
So, this brings up three obvious questions:
1. What should gpio_get_value() return for an output?
2. What should be reported in /sys/kernel/debug/gpio for an output?
3. Should iMX6 (and similar) GPIOs always have the SION bit set in
their DT descriptions?
Discuss.
Since I've wasted all afternoon trying to chase down why the GPIOs
controlling the regulators for USB appear to be disabled when reading
/sys/kernel/debug/gpio, I'm *FAR* from impressed by the current
confusing behaviour - and it's another nail in the "why the ARM Linux
kernel is turning to shit" coffin. I'm pleased to know that according
to google+, I'm not the only one with these feelings - so it's about
time we started fixing some of these idiotic and crap behaviours in
these layers of subsystems which make platform support unnecessarily
difficult.
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* [PATCH] arch_timer: Move delay timer to drivers clocksource
From: Stephen Boyd @ 2014-01-17 18:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D932B5.7020909@nvidia.com>
On 01/17/14 05:40, Prashant Gaikwad wrote:
>
> Another requirement:
>
> We have 3 timers T1, T2, T3 used as wake events for 3 idle states C1,
> C2, C3 respectively.
>
> Rating of T2 is better than T3. If I register T2 and T3 both as
> broadcast timers then T3 will not be used. But ...
> - T2 is not preserved in C3 idle state.
> - T3 resolution is very poor (ms) and can not be used as wake
> event for C2.
>
> Possible solution, register only T3 as broadcast device and use T2 as
> per-CPU fallback timer.
We have the same situation on MSM. I've been thinking about proposing we
allow multiple broadcast timers to exist in the system and then have the
clockevents_notify() caller indicate which C state is being entered. The
broadcast timers would need to indicate which C state they don't work in
though.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* [PATCH v2] usb: phy: msm: fix compilation errors when !CONFIG_PM_SLEEP
From: Josh Cartwright @ 2014-01-17 18:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389981531-15539-1-git-send-email-joshc@codeaurora.org>
On Fri, Jan 17, 2014 at 11:58:51AM -0600, Josh Cartwright wrote:
> Both the PM_RUNTIME and PM_SLEEP callbacks call into the common
> msm_otg_{suspend,resume} routines, however these routines are only being
> built when CONFIG_PM_SLEEP. In addition, msm_otg_{suspend,resume} also
> depends on msm_hsusb_config_vddcx(), which is only built when
> CONFIG_PM_SLEEP.
>
> Fix the CONFIG_PM_RUNTIME, !CONFIG_PM_SLEEP case by changing the
> preprocessor conditional, and moving msm_hsusb_config_vddcx().
>
> While we're here, eliminate the CONFIG_PM conditional for setting
> up the dev_pm_ops.
>
> This address the following errors Russell King has hit doing randconfig
> builds:
>
> drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_suspend':
> drivers/usb/phy/phy-msm-usb.c:1691:2: error: implicit declaration of function 'msm_otg_suspend'
> drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_resume':
> drivers/usb/phy/phy-msm-usb.c:1699:2: error: implicit declaration of function 'msm_otg_resume'
>
> Cc: Ivan T. Ivanov <iivanov@mm-sol.com>
> Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
> Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
> ---
> v1->v2: Change conditional to simply CONFIG_PM (thanks ccov and khilman!)
>
> drivers/usb/phy/phy-msm-usb.c | 57 ++++++++++++++++++++-----------------------
> 1 file changed, 26 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
> index 8546c8d..5b169a7 100644
> --- a/drivers/usb/phy/phy-msm-usb.c
> +++ b/drivers/usb/phy/phy-msm-usb.c
[..]
> @@ -440,7 +414,32 @@ static int msm_otg_reset(struct usb_phy *phy)
> #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
> #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
>
> -#ifdef CONFIG_PM_SLEEP
> +#if CONFIG_PM
*sigh*. This, of course, should have been #ifdef CONFIG_PM. Fixed
v3 below.
Thanks,
Josh
-- 8< --
Subject: [PATCH v3] usb: phy: msm: fix compilation errors when !CONFIG_PM_SLEEP
Both the PM_RUNTIME and PM_SLEEP callbacks call into the common
msm_otg_{suspend,resume} routines, however these routines are only being
built when CONFIG_PM_SLEEP. In addition, msm_otg_{suspend,resume} also
depends on msm_hsusb_config_vddcx(), which is only built when
CONFIG_PM_SLEEP.
Fix the CONFIG_PM_RUNTIME, !CONFIG_PM_SLEEP case by changing the
preprocessor conditional, and moving msm_hsusb_config_vddcx().
While we're here, eliminate the CONFIG_PM conditional for setting
up the dev_pm_ops.
This address the following errors Russell King has hit doing randconfig
builds:
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_suspend':
drivers/usb/phy/phy-msm-usb.c:1691:2: error: implicit declaration of function 'msm_otg_suspend'
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_resume':
drivers/usb/phy/phy-msm-usb.c:1699:2: error: implicit declaration of function 'msm_otg_resume'
Cc: Ivan T. Ivanov <iivanov@mm-sol.com>
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
---
drivers/usb/phy/phy-msm-usb.c | 57 ++++++++++++++++++++-----------------------
1 file changed, 26 insertions(+), 31 deletions(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 8546c8d..d204f74 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -159,32 +159,6 @@ put_3p3:
return rc;
}
-#ifdef CONFIG_PM_SLEEP
-#define USB_PHY_SUSP_DIG_VOL 500000
-static int msm_hsusb_config_vddcx(int high)
-{
- int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
- int min_vol;
- int ret;
-
- if (high)
- min_vol = USB_PHY_VDD_DIG_VOL_MIN;
- else
- min_vol = USB_PHY_SUSP_DIG_VOL;
-
- ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
- if (ret) {
- pr_err("%s: unable to set the voltage for regulator "
- "HSUSB_VDDCX\n", __func__);
- return ret;
- }
-
- pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
-
- return ret;
-}
-#endif
-
static int msm_hsusb_ldo_set_mode(int on)
{
int ret = 0;
@@ -440,7 +414,32 @@ static int msm_otg_reset(struct usb_phy *phy)
#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
#define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
-#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_PM
+
+#define USB_PHY_SUSP_DIG_VOL 500000
+static int msm_hsusb_config_vddcx(int high)
+{
+ int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
+ int min_vol;
+ int ret;
+
+ if (high)
+ min_vol = USB_PHY_VDD_DIG_VOL_MIN;
+ else
+ min_vol = USB_PHY_SUSP_DIG_VOL;
+
+ ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
+ if (ret) {
+ pr_err("%s: unable to set the voltage for regulator "
+ "HSUSB_VDDCX\n", __func__);
+ return ret;
+ }
+
+ pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
+
+ return ret;
+}
+
static int msm_otg_suspend(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
@@ -1733,22 +1732,18 @@ static int msm_otg_pm_resume(struct device *dev)
}
#endif
-#ifdef CONFIG_PM
static const struct dev_pm_ops msm_otg_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
msm_otg_runtime_idle)
};
-#endif
static struct platform_driver msm_otg_driver = {
.remove = msm_otg_remove,
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
-#ifdef CONFIG_PM
.pm = &msm_otg_dev_pm_ops,
-#endif
},
};
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related
* [PATCHv13 00/40] ARM: TI SoC clock DT conversion
From: Tero Kristo @ 2014-01-17 18:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140117175312.GH7993@atomide.com>
On 01/17/2014 07:53 PM, Tony Lindgren wrote:
> * Kevin Hilman <khilman@linaro.org> [140117 09:48]:
>> Mike Turquette <mturquette@linaro.org> writes:
>>
>> [...]
>>
>>> I took Tony's advice and fast-forwarded clk-next to -rc7 and applied
>>> Tero's series. This includes the AM3517 bits now. I've pushed this
>>> branch to clk-next-omap (force update) on my Linaro mirror. Can you do a
>>> final sanity test before I merge this into clk-next?
I think you accidentally merged wrong branch to clk-next-omap with the
latest refresh. This is one is missing the build-fixes now, when it
earlier had those in.
The correct branch to merge was 3.13-rc7-dt-clks-v13-build-fixes.
This also causes the build failure below for omap1.
-Tero
>>
>> I merged clk-next-omap into next-20140117 and build/boot tested
>> omap2plus_defconfig, multi_v7_defconfig and
>> multi_v7_defconfig+CONFIG_LPAE=y and all passed a basic boot test for
>> omap5uevm.
>>
>> I'll add OMAP5 to the automated boot testing starting with the next
>> linux-next.
>
> OK that's good news. Looks like omap1_defconfig build has now started
> failing though:
>
> vers/built-in.o: In function `omap5xxx_dt_clk_init':
> :(.init.text+0x846c): undefined reference to `omap2_clk_disable_autoidle_all'
> drivers/built-in.o: In function `am43xx_dt_clk_init':
> :(.init.text+0x856c): undefined reference to `omap2_clk_disable_autoidle_all'
> drivers/built-in.o:(.rodata+0xc3c4): undefined reference to `omap3_clkoutx2_recalc'
> drivers/built-in.o:(.rodata+0xc40c): undefined reference to `omap3_noncore_dpll_enable'
> drivers/built-in.o:(.rodata+0xc410): undefined reference to `omap3_noncore_dpll_disable'
> drivers/built-in.o:(.rodata+0xc41c): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc420): undefined reference to `omap2_dpll_round_rate'
> drivers/built-in.o:(.rodata+0xc42c): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc430): undefined reference to `omap3_noncore_dpll_set_rate'
> drivers/built-in.o:(.rodata+0xc470): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc474): undefined reference to `omap2_dpll_round_rate'
> drivers/built-in.o:(.rodata+0xc480): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc4a0): undefined reference to `omap3_noncore_dpll_enable'
> drivers/built-in.o:(.rodata+0xc4a4): undefined reference to `omap3_noncore_dpll_disable'
> drivers/built-in.o:(.rodata+0xc4b0): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc4b4): undefined reference to `omap2_dpll_round_rate'
> drivers/built-in.o:(.rodata+0xc4c0): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc4c4): undefined reference to `omap3_dpll4_set_rate'
> drivers/built-in.o:(.rodata+0xc4e0): undefined reference to `omap3_noncore_dpll_enable'
> drivers/built-in.o:(.rodata+0xc4e4): undefined reference to `omap3_noncore_dpll_disable'
> drivers/built-in.o:(.rodata+0xc4f0): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc4f4): undefined reference to `omap2_dpll_round_rate'
> drivers/built-in.o:(.rodata+0xc500): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc504): undefined reference to `omap3_noncore_dpll_set_rate'
> drivers/built-in.o:(.rodata+0xc530): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc540): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc560): undefined reference to `omap3_noncore_dpll_enable'
> drivers/built-in.o:(.rodata+0xc564): undefined reference to `omap3_noncore_dpll_disable'
> drivers/built-in.o:(.rodata+0xc570): undefined reference to `omap4_dpll_regm4xen_recalc'
> drivers/built-in.o:(.rodata+0xc574): undefined reference to `omap4_dpll_regm4xen_round_rate'
> drivers/built-in.o:(.rodata+0xc580): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc584): undefined reference to `omap3_noncore_dpll_set_rate'
> drivers/built-in.o:(.rodata+0xc5b0): undefined reference to `omap3_dpll_recalc'
> drivers/built-in.o:(.rodata+0xc5b4): undefined reference to `omap2_dpll_round_rate'
> drivers/built-in.o:(.rodata+0xc5c0): undefined reference to `omap2_init_dpll_parent'
> drivers/built-in.o:(.rodata+0xc5c4): undefined reference to `omap3_noncore_dpll_set_rate'
> drivers/built-in.o:(.rodata+0xc63c): undefined reference to `omap2_dflt_clk_enable'
> drivers/built-in.o:(.rodata+0xc640): undefined reference to `omap2_dflt_clk_disable'
> drivers/built-in.o:(.rodata+0xc644): undefined reference to `omap2_dflt_clk_is_enabled'
> drivers/built-in.o:(.rodata+0xc728): undefined reference to `omap2_clkops_enable_clkdm'
> drivers/built-in.o:(.rodata+0xc72c): undefined reference to `omap2_clkops_disable_clkdm'
> drivers/built-in.o:(.rodata+0xc754): undefined reference to `omap2_init_clk_clkdm'
> drivers/built-in.o:(.rodata+0xc784): undefined reference to `omap2_dflt_clk_disable'
> drivers/built-in.o:(.rodata+0xc788): undefined reference to `omap2_dflt_clk_is_enabled'
> drivers/built-in.o:(.rodata+0xc7ac): undefined reference to `omap2_init_clk_clkdm'
> drivers/built-in.o:(.rodata+0xc7c0): undefined reference to `omap2_dflt_clk_enable'
> drivers/built-in.o:(.rodata+0xc7c4): undefined reference to `omap2_dflt_clk_disable'
> drivers/built-in.o:(.rodata+0xc7c8): undefined reference to `omap2_dflt_clk_is_enabled'
> drivers/built-in.o:(.rodata+0xc7ec): undefined reference to `omap2_init_clk_clkdm'
> drivers/built-in.o:(.rodata+0xc838): undefined reference to `__clk_mux_determine_rate'
> drivers/built-in.o:(.rodata+0xc904): undefined reference to `omap2_dflt_clk_enable'
> drivers/built-in.o:(.rodata+0xc908): undefined reference to `omap2_dflt_clk_disable'
> drivers/built-in.o:(.rodata+0xc90c): undefined reference to `omap2_dflt_clk_is_enabled'
> drivers/built-in.o:(.rodata+0xc930): undefined reference to `omap2_init_clk_clkdm'
>
> Regards,
>
> Tony
>
^ permalink raw reply
* [PATCH v2 1/7] ARM: perf_event: Support percpu irqs for the CPU PMU
From: Will Deacon @ 2014-01-17 18:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D96E5C.4040506@codeaurora.org>
On Fri, Jan 17, 2014 at 05:54:36PM +0000, Stephen Boyd wrote:
> On 01/17/14 07:04, Will Deacon wrote:
> > Hi Stephen,
> >
> > On Wed, Jan 15, 2014 at 08:54:27PM +0000, Stephen Boyd wrote:
> >> On 01/15, Stephen Boyd wrote:
> >>> diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
> >>> index 789d846a9184..e76750980b38 100644
> >>> --- a/arch/arm/kernel/perf_event.c
> >>> +++ b/arch/arm/kernel/perf_event.c
> >>> @@ -295,9 +297,15 @@ validate_group(struct perf_event *event)
> >>>
> >>> static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
> >>> {
> >>> - struct arm_pmu *armpmu = (struct arm_pmu *) dev;
> >>> - struct platform_device *plat_device = armpmu->plat_device;
> >>> - struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
> >>> + struct arm_pmu *armpmu;
> >>> + struct platform_device *plat_device;
> >>> + struct arm_pmu_platdata *plat;
> >>> +
> >>> + if (irq_is_percpu(irq))
> >>> + dev = *(struct arm_pmu_cpu **)dev;
> >> Oh. I just realized that struct arm_pmu_cpu doesn't even exist. This
> >> still compiles though because we're dealing with a void pointer.
> >>
> >> Perhaps its better to just do
> >>
> >> dev = *(void **)dev;
> >>
> >> here. Can you fix that up when applying? Otherwise I'll do it on
> >> the next send if there are more comments.
> > Shouldn't that actually be some per_cpu accessor like this_cpu_ptr?
> >
>
> Nope. The genirq layer unwraps the per_cpu pointer and passes it to the
> handler.
Ah yeah, I forget the dispatcher is what genirq sees as the handler. In
which case your idea looks right.
Sorry for the noise.
Will
^ permalink raw reply
* [PATCH V3 2/2] mm/memblock: Add support for excluded memory areas
From: Strashko, Grygorii @ 2014-01-17 18:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140114195225.078f810a@lilie>
Hi Philipp,
On 01/14/2014 08:52 PM, Philipp Hachtmann wrote:
> Hello Grygorii,
>
> thank you for your comments.
>
> To clarify we have the following requirements for memblock:
>
> (1) Reserved areas can be declared before memory is added.
> (2) The physical memory is detected once only.
> (3) The free memory (i.e. not reserved) memory can be iterated to add
> it to the buddy allocator.
> (4) Memory designated to be mapped into the kernel address space can be
> iterated.
> (5) Kdump on s390 requires knowledge about the full system memory
> layout.
>
> The s390 kdump implementation works a bit different from the
> implementation on other architectures: The layout is not taken from the
> production system and saved for the kdump kernel. Instead the kdump
> kernel needs to gather information about the whole memory without
> respect to locked out areas (like mem= and OLDMEM etc.).
>
> Without kdump's requirement it would of course be suitable and easy
> just to remove memory from memblock.memory. But then this information
> is lost for later use by kdump.
>
> The patch does not change any behaviour of the current API - whether it
> is enabled or not.
Sorry, for the delayed reply.
My main concern here was that you are introducing new *generic* API,
but in fact it is not generic, because it can't be re-used without huge rework
of existing code.
(at least as of wide usage of for_each_memblock(memory,...),
because (if ARCH_MEMBLOCK_NOMAP=y) the meaning of "memory"
ranges will be changed form "mapped memory" to "real phys memory").
And therefore, I've proposed to keep things as is and introduce phys_memory
ranges instead, to store real phys memory configuration.
>
> The current patch seems to be overly complicated.
> The following patch contains only the nomap functionality without any
> cleanup and refactoring. I will post a V4 patch set which will contain
> this patch.
Regards,
-grygorii
^ permalink raw reply
* [PATCH] clocksource: timer-sun5i: Switch to sched_clock_register()
From: Daniel Lezcano @ 2014-01-17 18:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D96ED6.20508@codeaurora.org>
On 01/17/2014 06:56 PM, Stephen Boyd wrote:
> On 01/17/14 02:05, Daniel Lezcano wrote:
>> On 01/17/2014 02:38 AM, Stephen Boyd wrote:
>>> The 32 bit sched_clock interface supports 64 bits since 3.13-rc1.
>>> Upgrade to the 64 bit function to allow us to remove the 32 bit
>>> registration interface.
>>>
>>> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
>>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>>> ---
>>>
>>> Cc'in Ingo because this is simple enough to probably just apply to
>>> timers/core
>>
>> Hi Stephen,
>>
>> I applied your patch in my tree for 3.15.
>>
>
> I was hoping we could remove setup_sched_clock() in 3.14-rc1 timeline,
> but if we delay this until 3.15 we'll have to wait another 3 months. Is
> there any chance we can get this in for 3.14?
I am ok with that. It is up to Ingo.
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH v2] usb: phy: msm: fix compilation errors when !CONFIG_PM_SLEEP
From: Josh Cartwright @ 2014-01-17 17:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87lhyemr3y.fsf@linaro.org>
Both the PM_RUNTIME and PM_SLEEP callbacks call into the common
msm_otg_{suspend,resume} routines, however these routines are only being
built when CONFIG_PM_SLEEP. In addition, msm_otg_{suspend,resume} also
depends on msm_hsusb_config_vddcx(), which is only built when
CONFIG_PM_SLEEP.
Fix the CONFIG_PM_RUNTIME, !CONFIG_PM_SLEEP case by changing the
preprocessor conditional, and moving msm_hsusb_config_vddcx().
While we're here, eliminate the CONFIG_PM conditional for setting
up the dev_pm_ops.
This address the following errors Russell King has hit doing randconfig
builds:
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_suspend':
drivers/usb/phy/phy-msm-usb.c:1691:2: error: implicit declaration of function 'msm_otg_suspend'
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_resume':
drivers/usb/phy/phy-msm-usb.c:1699:2: error: implicit declaration of function 'msm_otg_resume'
Cc: Ivan T. Ivanov <iivanov@mm-sol.com>
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
---
v1->v2: Change conditional to simply CONFIG_PM (thanks ccov and khilman!)
drivers/usb/phy/phy-msm-usb.c | 57 ++++++++++++++++++++-----------------------
1 file changed, 26 insertions(+), 31 deletions(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 8546c8d..5b169a7 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -159,32 +159,6 @@ put_3p3:
return rc;
}
-#ifdef CONFIG_PM_SLEEP
-#define USB_PHY_SUSP_DIG_VOL 500000
-static int msm_hsusb_config_vddcx(int high)
-{
- int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
- int min_vol;
- int ret;
-
- if (high)
- min_vol = USB_PHY_VDD_DIG_VOL_MIN;
- else
- min_vol = USB_PHY_SUSP_DIG_VOL;
-
- ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
- if (ret) {
- pr_err("%s: unable to set the voltage for regulator "
- "HSUSB_VDDCX\n", __func__);
- return ret;
- }
-
- pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
-
- return ret;
-}
-#endif
-
static int msm_hsusb_ldo_set_mode(int on)
{
int ret = 0;
@@ -440,7 +414,32 @@ static int msm_otg_reset(struct usb_phy *phy)
#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
#define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
-#ifdef CONFIG_PM_SLEEP
+#if CONFIG_PM
+
+#define USB_PHY_SUSP_DIG_VOL 500000
+static int msm_hsusb_config_vddcx(int high)
+{
+ int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
+ int min_vol;
+ int ret;
+
+ if (high)
+ min_vol = USB_PHY_VDD_DIG_VOL_MIN;
+ else
+ min_vol = USB_PHY_SUSP_DIG_VOL;
+
+ ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
+ if (ret) {
+ pr_err("%s: unable to set the voltage for regulator "
+ "HSUSB_VDDCX\n", __func__);
+ return ret;
+ }
+
+ pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
+
+ return ret;
+}
+
static int msm_otg_suspend(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
@@ -1733,22 +1732,18 @@ static int msm_otg_pm_resume(struct device *dev)
}
#endif
-#ifdef CONFIG_PM
static const struct dev_pm_ops msm_otg_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
msm_otg_runtime_idle)
};
-#endif
static struct platform_driver msm_otg_driver = {
.remove = msm_otg_remove,
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
-#ifdef CONFIG_PM
.pm = &msm_otg_dev_pm_ops,
-#endif
},
};
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related
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