* [PATCH v2] dma: imx-sdma: clarify firmare not found warning
From: Lothar Waßmann @ 2014-01-21 6:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140120151152.GE15937@n2100.arm.linux.org.uk>
Hi,
Russell King - ARM Linux wrote:
> On Mon, Jan 20, 2014 at 03:09:02PM +0100, Lothar Wa?mann wrote:
> > Hi,
> >
> > Russell King - ARM Linux wrote:
> > > On Mon, Jan 20, 2014 at 12:36:27PM +0100, Lothar Wa?mann wrote:
> > > > In case user space firmware loading support (CONFIG_FW_LOADER) is
> > > > enabled, this message may still be inadequate, since the firmware may
> > > > very well be loaded lateron.
> > >
> > > I haven't worked out whether that's actually possible - I saw no way to
> > > re-trigger the firmware request, and once the firmware request expires,
> > > there seems to be no way for userspace to say "okay, the firmware is now
> > > available, please load it".
> > >
> > I can confirm that it does work, since I'm using it.
> > I have the following in my /etc/init.d/mdev.sh script:
> > | [ "$VERBOSE" = no ] || echo -n "Triggering firmware load"
> > | for dir in $(find /sys/class/firmware/ -type l);do
> > | echo add > "$dir/uevent"
> > | done
>
> I can't check on iMX6 at the moment, but I did look in that directory
> after the iMX6 SDMA reported that it hadn't found any firmware, and
> it was empty apart from the "timeout" file.
>
The file is automatically removed after the timeout has expired (or
the frimware has been loaded).
Thus you must check for it within the timeout period during boot.
Lothar Wa?mann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
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___________________________________________________________
^ permalink raw reply
* [PATCH v2] dma: imx-sdma: clarify firmare not found warning
From: Sascha Hauer @ 2014-01-21 7:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140120123627.1147f252@ipc1.ka-ro>
Hi Lothar,
On Mon, Jan 20, 2014 at 12:36:27PM +0100, Lothar Wa?mann wrote:
> Hi,
>
> Lothar Wa?mann wrote:
> > Hi,
> >
> erroneously pressed the 'Send' button...
>
> > Sascha Hauer wrote:
> > > When a firmware cannot be found for the SDMA engine then we can
> > > continue with the inernal ROM firmware.
> > >
> > > The meaning of this message is frequently asked for, so make clear
> > > that the driver still works with the internal ROM firmware and reduce
> > > the loglevel from err to info.
> > >
> In case user space firmware loading support (CONFIG_FW_LOADER) is
> enabled, this message may still be inadequate, since the firmware may
> very well be loaded lateron.
Then at least until the RAM firmware is loaded the message is still adequate,
no? We could add an addional message when the firmware is loaded if you
like.
Sascha
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply
* Question: about wm8904's regulator consumer nodes
From: Yang, Wenyou @ 2014-01-21 7:10 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark,
Sorry to bother you.
There a board with a act8865 PMIC and wm8904 codec chip. But wm8904's powers is not supplied by any regulators, it is supplied directly.
1./ If enabling the CONFIG_REGULATOR, the wm8904 fails to probe with following message.
wm8904 0-001a: Failed to get supply 'DCVDD': -19
2./ If adding the consumer nodes as below, the wm8904 works OK.
i2c1: i2c at f0018000 {
wm8904: wm8904 at 1a {
compatible = "wm8904";
reg = <0x1a>;
DCVDD-supply = <&vcc_1v8_reg>;
DBVDD-supply = <&vddana_reg>;
AVDD-supply = <&vcc_1v8_reg>;
CPVDD-supply = <&vcc_1v8_reg>;
MICVDD-supply = <&vddana_reg>;
};
};
But the power of DCVDD, DBVDD, AVDD, CPVDD and MICVDD is not supplied by any regulators, not the above regulator nodes.
How do I deal with this case? Could you give me some advice?
Thank you in advance.
Best Regards,
Wenyou Yang
^ permalink raw reply
* More GPIO madness on iMX6 - and the crappy ARM port of Linux
From: Lothar Waßmann @ 2014-01-21 7:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAAVeFuJhYv_vKqgyyaw7LOzRvErjf4u=5jJCvpoEgA0ZsMj-1Q@mail.gmail.com>
Hi,
Alexandre Courbot wrote:
> On Sat, Jan 18, 2014 at 7:43 AM, Linus Walleij <linus.walleij@linaro.org> wrote:
> > On Fri, Jan 17, 2014 at 9:53 PM, Russell King - ARM Linux
> > <linux@arm.linux.org.uk> wrote:
> >> On Fri, Jan 17, 2014 at 01:42:44PM -0700, Stephen Warren wrote:
> >
[...]
> > If the OPEN_DRAIN flag is set on that descriptor we should
> > always be able to read the input. But as this is not really what the
> > I2C core wants to know (it really would prefer not to bother with
> > such GPIO flag details) so is it better if we add a special call to
> > figure out if the input can be read? Like:
> >
> > bool gpiod_input_always_valid(const struct gpio_desc *desc);
> >
> > And leave it up to the core to look at flags, driver characteristics
> > etc and determine whether the input can be trusted?
>
> I am personally a little bit scared by the number of exported
> functions in the GPIO framework. It is a pretty large number for
> something that is supposed to be simple, so I'd like to avoid adding
> more. :) How about the following:
>
> 1) GPIOs configured as output without the open drain or open source
> flag either return -EINVAL on gpiod_get_value(), or a cached value
> tracked by gpiolib for consistency (probably the latter).
> 2) GPIOs configured as open drain or open source report the actual
> value read on the pin, like i2c-core needs. This requires that, for
> each GPIO that can be set open drain or open source,
> gpiod_input_always_valid() == true.
>
I would not bind this to the open drain configuration. Any GPIO output
pin may actually be in a different state than programmed when the
output is forcefully driven by another source (shortcut).
So it makes sense to be able to read back the real state of the pad
even for push pull outputs.
Lothar Wa?mann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________
^ permalink raw reply
* [patch] drm/exynos: potential use after free in exynos_drm_open()
From: Jingoo Han @ 2014-01-21 7:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140121065748.GC31535@elgon.mountain>
On Tuesday, January 21, 2014 3:58 PM, Dan Carpenter wrote:
>
> If exynos_drm_subdrv_open() fails then we re-use "file_priv".
>
> Fixes: 96f5421523df ('drm/exynos: use a new anon file for exynos gem mmaper')
> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Yes, right.
The freed 'file_priv' should not be re-used.
Best regards,
Jingoo Han
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> index 9d096a0c5f8d..3c845292845a 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> @@ -174,6 +174,7 @@ static int exynos_drm_open(struct drm_device *dev, struct drm_file *file)
> if (ret) {
> kfree(file_priv);
> file->driver_priv = NULL;
> + return ret;
> }
>
> anon_filp = anon_inode_getfile("exynos_gem", &exynos_drm_gem_fops,
> @@ -186,7 +187,7 @@ static int exynos_drm_open(struct drm_device *dev, struct drm_file *file)
> anon_filp->f_mode = FMODE_READ | FMODE_WRITE;
> file_priv->anon_filp = anon_filp;
>
> - return ret;
> + return 0;
> }
>
> static void exynos_drm_preclose(struct drm_device *dev,
^ permalink raw reply
* [patch] drm/exynos: potential use after free in exynos_drm_open()
From: Inki Dae @ 2014-01-21 7:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140121065748.GC31535@elgon.mountain>
Hi,
This issue had already been reported, and fixed by Sachin. And also
that patch has been merged to exynos-drm-next. Please see below link,
http://www.spinics.net/lists/dri-devel/msg51889.html
Thanks,
Inki Dae
2014/1/21 Dan Carpenter <dan.carpenter@oracle.com>:
> If exynos_drm_subdrv_open() fails then we re-use "file_priv".
>
> Fixes: 96f5421523df ('drm/exynos: use a new anon file for exynos gem mmaper')
> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> index 9d096a0c5f8d..3c845292845a 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> @@ -174,6 +174,7 @@ static int exynos_drm_open(struct drm_device *dev, struct drm_file *file)
> if (ret) {
> kfree(file_priv);
> file->driver_priv = NULL;
> + return ret;
> }
>
> anon_filp = anon_inode_getfile("exynos_gem", &exynos_drm_gem_fops,
> @@ -186,7 +187,7 @@ static int exynos_drm_open(struct drm_device *dev, struct drm_file *file)
> anon_filp->f_mode = FMODE_READ | FMODE_WRITE;
> file_priv->anon_filp = anon_filp;
>
> - return ret;
> + return 0;
> }
>
> static void exynos_drm_preclose(struct drm_device *dev,
> _______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [PATCH 1/3] mmc: add support for power-on sequencing through DT
From: Sascha Hauer @ 2014-01-21 7:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390190215-22700-2-git-send-email-olof@lixom.net>
On Sun, Jan 19, 2014 at 07:56:53PM -0800, Olof Johansson wrote:
> This patch enables support for power-on sequencing of SDIO peripherals through DT.
>
> In general, it's quite common that wifi modules and other similar
> peripherals have several signals in addition to the SDIO interface that
> needs wiggling before the module will power on. It's common to have a
> reference clock, one or several power rails and one or several lines
> for reset/enable type functions.
>
> The binding as written today introduces a number of reset gpios,
> a regulator and a clock specifier. The code will handle up to 2 gpio
> reset lines, but it's trivial to increase to more than that if needed
> at some point.
>
> Implementation-wise, the MMC core has been changed to handle this during
> host power up, before the host interface is powered on. I have not yet
> implemented the power-down side, I wanted people to have a chance for
> reporting back w.r.t. issues (or comments on the bindings) first.
>
> I have not tested the regulator portion, since the system and module
> I'm working on doesn't need one (Samsung Chromebook with Marvell
> 8797-based wifi). Testing of those portions (and reporting back) would
> be appreciated.
>
> Signed-off-by: Olof Johansson <olof@lixom.net>
> ---
> Documentation/devicetree/bindings/mmc/mmc.txt | 11 +++++++
> drivers/mmc/core/core.c | 42 +++++++++++++++++++++++++
> drivers/mmc/core/host.c | 30 +++++++++++++++++-
> include/linux/mmc/host.h | 5 +++
> 4 files changed, 87 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt
> index 458b57f..962e0ee 100644
> --- a/Documentation/devicetree/bindings/mmc/mmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/mmc.txt
> @@ -5,6 +5,8 @@ these definitions.
> Interpreted by the OF core:
> - reg: Registers location and length.
> - interrupts: Interrupts used by the MMC controller.
> +- clocks: Clocks needed for the host controller, if any.
> +- clock-names: Goes with clocks above.
>
> Card detection:
> If no property below is supplied, host native card detect is used.
> @@ -30,6 +32,15 @@ Optional properties:
> - cap-sdio-irq: enable SDIO IRQ signalling on this interface
> - full-pwr-cycle: full power cycle of the card is supported
>
> +Card power and reset control:
> +The following properties can be specified for cases where the MMC
> +peripheral needs additional reset, regulator and clock lines. It is for
> +example common for WiFi/BT adapters to have these separate from the main
> +MMC bus:
> + - card-reset-gpios: Specify GPIOs for card reset (reset active low)
We have GPIO_ACTIVE_LOW/HIGH. No need to hardcode this.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply
* [PATCH 1/3] mmc: add support for power-on sequencing through DT
From: Sascha Hauer @ 2014-01-21 7:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140121072447.GC19940@pengutronix.de>
On Tue, Jan 21, 2014 at 08:24:47AM +0100, Sascha Hauer wrote:
> On Sun, Jan 19, 2014 at 07:56:53PM -0800, Olof Johansson wrote:
> > +Card power and reset control:
> > +The following properties can be specified for cases where the MMC
> > +peripheral needs additional reset, regulator and clock lines. It is for
> > +example common for WiFi/BT adapters to have these separate from the main
> > +MMC bus:
> > + - card-reset-gpios: Specify GPIOs for card reset (reset active low)
>
> We have GPIO_ACTIVE_LOW/HIGH. No need to hardcode this.
Fabio already spotted that. Sorry for the noise.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply
* [PATCH v2 3/7] devicetree: bindings: add cpu clock configuration data binding for Exynos4/5
From: Thomas Abraham @ 2014-01-21 7:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqJSSW3DKQvcwzuapAYRbZMP3CP5vne-Bvg7-4z-rDGSxw@mail.gmail.com>
Hi Rob,
On Sat, Jan 18, 2014 at 8:52 PM, Rob Herring <robherring2@gmail.com> wrote:
> On Sat, Jan 18, 2014 at 6:10 AM, Thomas Abraham <ta.omasab@gmail.com> wrote:
>> From: Thomas Abraham <thomas.ab@samsung.com>
>>
>> The clk ops of the new Samsung cpu clock provider type requires configuration
>> data that will be programmed in the multiple clock blocks encapsulated within
>> the cpu clock provider type. This configuration data is held in the clock
>> controller node. Update clock binding documentation about this configuration
>> data format for Samsung Exynos4 and Exynos5 platforms.
>>
>> Cc: Rob Herring <robh+dt@kernel.org>
>
> Please copy all maintainers.
Okay.
>
>> Cc: Tomasz Figa <t.figa@samsung.com>
>> Cc: <devicetree@vger.kernel.org>
>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>> ---
>> .../devicetree/bindings/clock/exynos4-clock.txt | 30 ++++++++++++++++++++
>> .../devicetree/bindings/clock/exynos5250-clock.txt | 21 ++++++++++++++
>> 2 files changed, 51 insertions(+), 0 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> index a2ac2d9..c28aabd 100644
>> --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> @@ -15,6 +15,29 @@ Required Properties:
>>
>> - #clock-cells: should be 1.
>>
>> +- arm-frequency-table: defines the list of arm clock speeds supported and
>
> Seems like a Samsung specific property and nothing to do with ARM, so
> it should be named accordingly.
Okay.
>
>> + the associated configuration values required to setup the clock controller
>> + for generating those speeds. The format of each entry included in the
>> + arm-frequency-table should be as defined below (#cells per entry = 13)
>> +
>> + - for Exynos4210 and Exynos4212 based platforms:
>> + cell #1: arm clock frequency
>> + cell #2: expected arm clock parent frequency
>> + cell #3 ~ cell 12#: value of clock divider in the following order
>> + core_ratio, corem0_ratio, corem1_ratio, periph_ratio,
>> + atb_ratio, pclk_dbg_ratio, apll_ratio, core2_ratio,
>> + copy_ratio, hpm_ratio.
>> + cell #13: reserved (should be zero).
>> +
>> + - for Exynos4412 based platforms:
>> + cell #1: arm clock frequency
>> + cell #2: expected arm clock parent frequency
>> + cell #3 ~ cell #13: value of clock divider in the following order
>> + core_ratio, corem0_ratio, corem1_ratio, periph_ratio,
>> + atb_ratio, pclk_dbg_ratio, apll_ratio, core2_ratio,
>> + copy_ratio, hpm_ratio, cores_ratio
>
> You don't need voltages? Are the h/w limitations really ratios or each
> clock has a max frequency that must be maintained? I would expect the
> latter and think it would be better to specify maximum frequencies of
> each clock. Then you can calculate the dividers to keep frequencies in
> range.
Voltage is not needed here since the cpu clock speed is managed by the
cpufreq driver which will take care of setting appropriate voltage.
Any other users apart from cpufreq will have to setup the voltage
appropriately.
About the ratios, yes the user manual lists the optimal clock
frequency for these clocks. As suggested, I will remove the ratio list
for these clocks.
>
> How will this scale to multi-cluster chips with different frequency ranges?
Usually, each cluster would have its own independent clock input. So
there will be two or more cpu clocks in multi-cluster chips. So the
clocks can be independently programmed as required by the cluster.
>
> Rob
>
Thanks Rob for your review.
Thomas.
>> +
>> +
>> The following is the list of clocks generated by the controller. Each clock is
>> assigned an identifier and client nodes use this identifier to specify the
>> clock which they consume. Some of the clocks are available only on a particular
>> @@ -275,6 +298,13 @@ Example 1: An example of a clock controller node is listed below.
>> compatible = "samsung,exynos4210-clock";
>> reg = <0x10030000 0x20000>;
>> #clock-cells = <1>;
>> +
>> + arm-frequency-table = <1200000 1200000 0 3 7 3 4 1 7 0 5 0>,
>> + <1000000 1000000 0 3 7 3 4 1 7 0 4 0>,
>> + < 800000 800000 0 3 7 3 3 1 7 0 3 0>,
>> + < 500000 500000 0 3 7 3 3 1 7 0 3 0>,
>> + < 400000 400000 0 3 7 3 3 1 7 0 3 0>,
>> + < 200000 200000 0 1 3 1 1 1 0 0 3 0>;
>> };
>>
>> Example 2: UART controller node that consumes the clock generated by the clock
>> diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
>> index 72ce617..99eae9c 100644
>> --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
>> +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
>> @@ -13,6 +13,20 @@ Required Properties:
>>
>> - #clock-cells: should be 1.
>>
>> +- arm-frequency-table: defines the list of arm clock speeds supported and
>> + the associated configuration values required to setup the clock controller
>> + for generating those speeds. The format of each entry included in the
>> + arm-frequency-table should be as defined below (#cells per entry = 13)
>> +
>> + cell #1: arm clock frequency
>> + cell #2: expected arm clock parent frequency
>> + cell #3 ~ cell #12: value of clock divider in the following order
>> + arm_ratio, cpud_ratio, acp_ratio, periph_ratio,
>> + atb_ratio, pclk_dbg_ratio, apll_ratio, arm2_ratio,
>> + copy_ratio, hpm_ratio
>> + cell #13: reserved (should be zero)
>> +
>> +
>> The following is the list of clocks generated by the controller. Each clock is
>> assigned an identifier and client nodes use this identifier to specify the
>> clock which they consume.
>> @@ -177,6 +191,13 @@ Example 1: An example of a clock controller node is listed below.
>> compatible = "samsung,exynos5250-clock";
>> reg = <0x10010000 0x30000>;
>> #clock-cells = <1>;
>> +
>> + arm-frequency-table = <1700000 1700000 0 3 7 7 7 3 5 0 0 2>,
>> + <1600000 1600000 0 3 7 7 7 1 4 0 0 2>,
>> + <1500000 1500000 0 2 7 7 7 1 4 0 0 2>,
>> + <1400000 1400000 0 2 7 7 6 1 4 0 0 2>,
>> + <1300000 1300000 0 2 7 7 6 1 3 0 0 2>,
>> + <1200000 1200000 0 2 7 7 5 1 3 0 0 2>;
>> };
>>
>> Example 2: UART controller node that consumes the clock generated by the clock
>> --
>> 1.6.6.rc2
>>
^ permalink raw reply
* [PATCH v2 4/7] ARM: dts: Exynos: add cpu nodes, opp and cpu clock frequency table
From: Thomas Abraham @ 2014-01-21 7:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140120083228.72ecce4a@amdc2363>
Hi Lukasz,
On Mon, Jan 20, 2014 at 1:02 PM, Lukasz Majewski <l.majewski@samsung.com> wrote:
> Hi Thomas,
>
>> From: Thomas Abraham <thomas.ab@samsung.com>
>>
>> For all Exynos based platforms, add CPU nodes, operating points and
>> cpu clock frequency table for migrating from Exynos specific cpufreq
>> driver to using generic cpufreq-cpu0 driver.
>>
>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>> ---
>> arch/arm/boot/dts/exynos4210-origen.dts | 6 +++
>> arch/arm/boot/dts/exynos4210-trats.dts | 6 +++
>> arch/arm/boot/dts/exynos4210-universal_c210.dts | 6 +++
>> arch/arm/boot/dts/exynos4210.dtsi | 35
>> ++++++++++++++++++ arch/arm/boot/dts/exynos4212.dtsi
>> | 17 +++++++++ arch/arm/boot/dts/exynos4412-odroidx.dts |
>> 6 +++ arch/arm/boot/dts/exynos4412-origen.dts | 6 +++
>> arch/arm/boot/dts/exynos4412-trats2.dts | 6 +++
>> arch/arm/boot/dts/exynos4412.dtsi | 30
>> ++++++++++++++++ arch/arm/boot/dts/exynos4x12.dtsi |
>> 35 ++++++++++++++++++ arch/arm/boot/dts/exynos5250-arndale.dts
>> | 6 +++ arch/arm/boot/dts/exynos5250-cros-common.dtsi | 6 +++
>> arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 +++
>> arch/arm/boot/dts/exynos5250.dtsi | 43
>> ++++++++++++++++++++++- 14 files changed, 213 insertions(+), 1
>> deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
>> b/arch/arm/boot/dts/exynos4210-origen.dts index 2aa13cb..dd17e93
>> 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts
>> +++ b/arch/arm/boot/dts/exynos4210-origen.dts
>> @@ -32,6 +32,12 @@
>> bootargs ="root=/dev/ram0 rw ramdisk=8192
>> initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; };
>>
>> + cpus {
>> + cpu at 0 {
>> + cpu0-supply = <&buck1_reg>;
>> + };
>> + };
>> +
>> regulators {
>> compatible = "simple-bus";
>> #address-cells = <1>;
>> diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
>> b/arch/arm/boot/dts/exynos4210-trats.dts index 63cc571..25487d7 100644
>> --- a/arch/arm/boot/dts/exynos4210-trats.dts
>> +++ b/arch/arm/boot/dts/exynos4210-trats.dts
>> @@ -30,6 +30,12 @@
>> bootargs = "console=ttySAC2,115200N8
>> root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; };
>>
>> + cpus {
>> + cpu: cpu at 0 {
>> + cpu0-supply = <&varm_breg>;
>> + };
>> + };
>> +
>> regulators {
>> compatible = "simple-bus";
>>
>> diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
>> b/arch/arm/boot/dts/exynos4210-universal_c210.dts index
>> d2e3f5f..74d5a70 100644 ---
>> a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++
>> b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -28,6 +28,12 @@
>> bootargs = "console=ttySAC2,115200N8
>> root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; };
>>
>> + cpus {
>> + cpu: cpu at 0 {
>> + cpu0-supply = <&vdd_arm_reg>;
>> + };
>> + };
>> +
>> mct at 10050000 {
>> compatible = "none";
>> };
>> diff --git a/arch/arm/boot/dts/exynos4210.dtsi
>> b/arch/arm/boot/dts/exynos4210.dtsi index 48ecd7a..40cd663 100644
>> --- a/arch/arm/boot/dts/exynos4210.dtsi
>> +++ b/arch/arm/boot/dts/exynos4210.dtsi
>> @@ -36,6 +36,34 @@
>> reg = <0x10023CA0 0x20>;
>> };
>>
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cpu at 0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + reg = <0>;
>> + clocks = <&clock 12>;
>> + clock-names = "cpu";
>> +
>> + operating-points = <
>> + 200000 950000
>> + 400000 975000
>> + 500000 975000
>> + 800000 1075000
>> + 1000000 1150000
>> + 1200000 1250000
>
> Please be consistent with "operating-points" definition. Here you use
> increasing order, when below you use decreasing one.
Okay, missed this one. Will fix in the next version.
Thanks,
Thomas.
>
>> + >;
>> + safe-opp = <800000 1075000>;
>> + };
>> +
>> + cpu at 1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + reg = <1>;
>> + };
>> + };
>> +
>> gic: interrupt-controller at 10490000 {
>> cpu-offset = <0x8000>;
>> };
>> @@ -73,6 +101,13 @@
>> compatible = "samsung,exynos4210-clock";
>> reg = <0x10030000 0x20000>;
>> #clock-cells = <1>;
>> +
>> + arm-frequency-table = <1200000 1200000 0 3 7 3 4 1 7
>> 0 5 0 0>,
>> + <1000000 1000000 0 3 7 3 4 1 7
>> 0 4 0 0>,
>> + < 800000 800000 0 3 7 3 3 1 7
>> 0 3 0 0>,
>> + < 500000 500000 0 3 7 3 3 1 7
>> 0 3 0 0>,
>> + < 400000 400000 0 3 7 3 3 1 7
>> 0 3 0 0>,
>> + < 200000 200000 0 1 3 1 1 1 0
>> 0 3 0 0>; };
>>
>> pmu {
>> diff --git a/arch/arm/boot/dts/exynos4212.dtsi
>> b/arch/arm/boot/dts/exynos4212.dtsi index 94a43f9..2ea0f83 100644
>> --- a/arch/arm/boot/dts/exynos4212.dtsi
>> +++ b/arch/arm/boot/dts/exynos4212.dtsi
>> @@ -22,6 +22,23 @@
>> / {
>> compatible = "samsung,exynos4212";
>>
>> + clock: clock-controller at 10030000 {
>> + arm-frequency-table = <1500000 1500000 0 3 7 0 6 1 2
>> 0 6 2 0>,
>> + <1400000 1400000 0 3 7 0 6 1 2
>> 0 6 2 0>,
>> + <1300000 1300000 0 3 7 0 5 1 2
>> 0 5 2 0>,
>> + <1200000 1200000 0 3 7 0 5 1 2
>> 0 5 2 0>,
>> + <1100000 1100000 0 3 6 0 4 1 2
>> 0 4 2 0>,
>> + <1000000 1000000 0 2 5 0 4 1 1
>> 0 4 2 0>,
>> + < 900000 900000 0 2 5 0 3 1 1
>> 0 3 2 0>,
>> + < 800000 800000 0 2 5 0 3 1 1
>> 0 3 2 0>,
>> + < 700000 700000 0 2 4 0 3 1 1
>> 0 3 2 0>,
>> + < 600000 600000 0 2 4 0 3 1 1
>> 0 3 2 0>,
>> + < 500000 500000 0 2 4 0 3 1 1
>> 0 3 2 0>,
>> + < 400000 400000 0 2 4 0 3 1 1
>> 0 3 2 0>,
>> + < 300000 300000 0 2 4 0 2 1 1
>> 0 3 2 0>,
>> + < 200000 200000 0 1 3 0 1 1 1
>> 0 3 2 0>;
>> + };
>> +
>> gic: interrupt-controller at 10490000 {
>> cpu-offset = <0x8000>;
>> };
>> diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
>> b/arch/arm/boot/dts/exynos4412-odroidx.dts index 12459b0..1c751f9
>> 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts
>> +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
>> @@ -22,6 +22,12 @@
>> reg = <0x40000000 0x40000000>;
>> };
>>
>> + cpus {
>> + cpu at 0 {
>> + cpu0-supply = <&buck2_reg>;
>> + };
>> + };
>> +
>> leds {
>> compatible = "gpio-leds";
>> led1 {
>> diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
>> b/arch/arm/boot/dts/exynos4412-origen.dts index 388f035..36080e5
>> 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts
>> +++ b/arch/arm/boot/dts/exynos4412-origen.dts
>> @@ -27,6 +27,12 @@
>> bootargs ="console=ttySAC2,115200";
>> };
>>
>> + cpus {
>> + cpu at 0 {
>> + cpu0-supply = <&buck2_reg>;
>> + };
>> + };
>> +
>> firmware at 0203F000 {
>> compatible = "samsung,secure-firmware";
>> reg = <0x0203F000 0x1000>;
>> diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
>> b/arch/arm/boot/dts/exynos4412-trats2.dts index 4f851cc..4a4d446
>> 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts
>> +++ b/arch/arm/boot/dts/exynos4412-trats2.dts
>> @@ -31,6 +31,12 @@
>> bootargs = "console=ttySAC2,115200N8
>> root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; };
>>
>> + cpus {
>> + cpu at 0 {
>> + cpu0-supply = <&buck2_reg>;
>> + };
>> + };
>> +
>> firmware at 0204F000 {
>> compatible = "samsung,secure-firmware";
>> reg = <0x0204F000 0x1000>;
>> diff --git a/arch/arm/boot/dts/exynos4412.dtsi
>> b/arch/arm/boot/dts/exynos4412.dtsi index 87b339c..7e9eca7 100644
>> --- a/arch/arm/boot/dts/exynos4412.dtsi
>> +++ b/arch/arm/boot/dts/exynos4412.dtsi
>> @@ -22,6 +22,36 @@
>> / {
>> compatible = "samsung,exynos4412";
>>
>> + cpus {
>> + cpu at 2 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + reg = <2>;
>> + };
>> + cpu at 3 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + reg = <3>;
>> + };
>> + };
>> +
>> + clock: clock-controller at 10030000 {
>> + arm-frequency-table = <1500000 1500000 0 3 7 0 6 1 2
>> 0 6 0 7>,
>> + <1400000 1400000 0 3 7 0 6 1 2
>> 0 6 0 6>,
>> + <1300000 1300000 0 3 7 0 5 1 2
>> 0 5 0 6>,
>> + <1200000 1200000 0 3 7 0 5 1 2
>> 0 5 0 5>,
>> + <1100000 1100000 0 3 6 0 4 1 2
>> 0 4 0 5>,
>> + <1000000 1000000 0 2 5 0 4 1 1
>> 0 4 0 4>,
>> + < 900000 900000 0 2 5 0 3 1 1
>> 0 3 0 4>,
>> + < 800000 800000 0 2 5 0 3 1 1
>> 0 3 0 3>,
>> + < 700000 700000 0 2 4 0 3 1 1
>> 0 3 0 3>,
>> + < 600000 600000 0 2 4 0 3 1 1
>> 0 3 0 2>,
>> + < 500000 500000 0 2 4 0 3 1 1
>> 0 3 0 2>,
>> + < 400000 400000 0 2 4 0 3 1 1
>> 0 3 0 1>,
>> + < 300000 300000 0 2 4 0 2 1 1
>> 0 3 0 1>,
>> + < 200000 200000 0 1 3 0 1 1 1
>> 0 3 0 0>;
>> + };
>> +
>> gic: interrupt-controller at 10490000 {
>> cpu-offset = <0x4000>;
>> };
>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
>> b/arch/arm/boot/dts/exynos4x12.dtsi index 5c412aa..47e2195 100644
>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>> @@ -31,6 +31,41 @@
>> mshc0 = &mshc_0;
>> };
>>
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cpu at 0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + reg = <0>;
>> + clocks = <&clock 12>;
>> + clock-names = "cpu";
>> +
>> + operating-points = <
>> + 1400000 1350000
>> + 1300000 1287500
>> + 1200000 1250000
>> + 1100000 1187500
>> + 1000000 1137500
>> + 900000 1087500
>> + 800000 1037500
>> + 700000 1000000
>> + 600000 987500
>> + 500000 950000
>> + 400000 925000
>> + 300000 900000
>> + 200000 900000
>> + >;
>> + clock-latency = <200000>;
>> + safe-opp = <800000 1037500>;
>> + };
>> + cpu at 1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + reg = <1>;
>> + };
>> + };
>> +
>> pd_isp: isp-power-domain at 10023CA0 {
>> compatible = "samsung,exynos4210-pd";
>> reg = <0x10023CA0 0x20>;
>> diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
>> b/arch/arm/boot/dts/exynos5250-arndale.dts index b42e658..4716eef
>> 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts
>> +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
>> @@ -25,6 +25,12 @@
>> bootargs = "console=ttySAC2,115200";
>> };
>>
>> + cpus {
>> + cpu at 0 {
>> + cpu0-supply = <&buck2_reg>;
>> + };
>> + };
>> +
>> codec at 11000000 {
>> samsung,mfc-r = <0x43000000 0x800000>;
>> samsung,mfc-l = <0x51000000 0x800000>;
>> diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
>> b/arch/arm/boot/dts/exynos5250-cros-common.dtsi index
>> 2c1560d..4bde756 100644 ---
>> a/arch/arm/boot/dts/exynos5250-cros-common.dtsi +++
>> b/arch/arm/boot/dts/exynos5250-cros-common.dtsi @@ -19,6 +19,12 @@
>> chosen {
>> };
>>
>> + cpus {
>> + cpu at 0 {
>> + cpu0-supply = <&buck2_reg>;
>> + };
>> + };
>> +
>> pinctrl at 11400000 {
>> /*
>> * Disabled pullups since external part has its own
>> pullups and diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 5c1b7d9..7c228e2
>> 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> @@ -27,6 +27,12 @@
>> bootargs = "root=/dev/ram0 rw ramdisk=8192
>> initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; };
>>
>> + cpus {
>> + cpu at 0 {
>> + cpu0-supply = <&buck2_reg>;
>> + };
>> + };
>> +
>> i2c at 12C60000 {
>> samsung,i2c-sda-delay = <100>;
>> samsung,i2c-max-bus-freq = <20000>;
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
>> b/arch/arm/boot/dts/exynos5250.dtsi index b7dec41..d2f98dc 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -61,6 +61,30 @@
>> compatible = "arm,cortex-a15";
>> reg = <0>;
>> clock-frequency = <1700000000>;
>> +
>> + clocks = <&clock 12>;
>> + clock-names = "cpu";
>> +
>> + operating-points = <
>> + 1700000 1300000
>> + 1600000 1250000
>> + 1500000 1225000
>> + 1400000 1200000
>> + 1300000 1150000
>> + 1200000 1125000
>> + 1100000 1100000
>> + 1000000 1075000
>> + 900000 1050000
>> + 800000 1025000
>> + 700000 1012500
>> + 600000 1000000
>> + 500000 975000
>> + 400000 950000
>> + 300000 937500
>> + 200000 925000
>> + >;
>> + clock-latency = <200000>;
>> + safe-opp = <800000 1025000>;
>> };
>> cpu at 1 {
>> device_type = "cpu";
>> @@ -84,7 +108,24 @@
>> compatible = "samsung,exynos5250-clock";
>> reg = <0x10010000 0x30000>;
>> #clock-cells = <1>;
>> - };
>> +
>> + arm-frequency-table = <1700000 1700000 0 3 7 7 7 3 5
>> 0 0 2 0>,
>> + <1600000 1600000 0 3 7 7 7 1 4
>> 0 0 2 0>,
>> + <1500000 1500000 0 2 7 7 7 1 4
>> 0 0 2 0>,
>> + <1400000 1400000 0 2 7 7 6 1 4
>> 0 0 2 0>,
>> + <1300000 1300000 0 2 7 7 6 1 3
>> 0 0 2 0>,
>> + <1200000 1200000 0 2 7 7 5 1 3
>> 0 0 2 0>,
>> + <1100000 1100000 0 3 7 7 5 1 3
>> 0 0 2 0>,
>> + <1000000 1000000 0 1 7 7 4 1 2
>> 0 0 2 0>,
>> + < 900000 900000 0 1 7 7 4 1 2
>> 0 0 2 0>,
>> + < 800000 800000 0 1 7 7 4 1 2
>> 0 0 2 0>,
>> + < 700000 700000 0 1 7 7 3 1 1
>> 0 0 2 0>,
>> + < 600000 600000 0 1 7 7 3 1 1
>> 0 0 2 0>,
>> + < 500000 500000 0 1 7 7 2 1 1
>> 0 0 2 0>,
>> + < 400000 400000 0 1 7 7 2 1 1
>> 0 0 2 0>,
>> + < 300000 300000 0 1 7 7 1 1 1
>> 0 0 2 0>,
>> + < 200000 200000 0 1 7 7 1 1 1
>> 0 0 2 0>;
>> + };
>>
>> clock_audss: audss-clock-controller at 3810000 {
>> compatible = "samsung,exynos5250-audss-clock";
>
>
>
> --
> Best regards,
>
> Lukasz Majewski
>
> Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply
* [PATCHv13 27/40] ARM: dts: omap3 clock data
From: Tero Kristo @ 2014-01-21 7:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140120180053.GA25920@earth.universe>
On 01/20/2014 08:00 PM, Sebastian Reichel wrote:
> Hi,
>
> I just found some time to update my SSI driver adding DT clock
> support. It works, but I wonder if the alias of the ssi clocks
> can be changed to something like the following:
>
> /* omap3430es1-clocks.dtsi */
> ssi_ick: ssi_ick_3430es1 {};
> ssi_ssr_fck: ssi_ssr_fck_3430es1 {};
> ssi_sst_fck: ssi_sst_fck_3430es1 {};
>
> /* omap36xx-omap3430es2plus-clocks.dtsi */
> ssi_ick: ssi_ick_3430es2 {};
> ssi_ssr_fck: ssi_ssr_fck_3430es2 {};
> ssi_sst_fck: ssi_sst_fck_3430es2 {};
>
> With this change I can reference the ssi clocks in omap3.dtsi
> instead of creating files for omap3430es1 and omap3430es2+.
Yea looks like a valid change to me. Feel free to send a patch for it.
-Tero
^ permalink raw reply
* [PATCH v2 5/7] clk: exynos: use cpu-clock provider type to represent arm clock
From: Thomas Abraham @ 2014-01-21 7:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140120084721.7f0050ea@amdc2363>
On Mon, Jan 20, 2014 at 1:17 PM, Lukasz Majewski <l.majewski@samsung.com> wrote:
> Hi Thomas,
>
>> From: Thomas Abraham <thomas.ab@samsung.com>
>>
>> With the addition of the new Samsung specific cpu-clock type, the
>> arm clock can be represented as a cpu-clock type and the independent
>> clock blocks that made up the arm clock can be removed.
>>
>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>> ---
>> .../devicetree/bindings/clock/exynos5250-clock.txt | 1 +
>> drivers/clk/samsung/clk-exynos4.c | 11 +++++------
>> drivers/clk/samsung/clk-exynos5250.c | 8 ++++----
>> include/dt-bindings/clock/exynos5250.h | 1 +
>> 4 files changed, 11 insertions(+), 10 deletions(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
>> b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index
>> 99eae9c..acf867a 100644 ---
>> a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++
>> b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@
>> -38,6 +38,7 @@ clock which they consume. ----------------------------
>> fin_pll 1
>> + armclk 12
>>
>> [Clock Gate for Special Clocks]
>>
>> diff --git a/drivers/clk/samsung/clk-exynos4.c
>> b/drivers/clk/samsung/clk-exynos4.c index 010f071..efcf4a3 100644
>> --- a/drivers/clk/samsung/clk-exynos4.c
>> +++ b/drivers/clk/samsung/clk-exynos4.c
>> @@ -437,8 +437,6 @@ static struct samsung_mux_clock
>> exynos4x12_mux_clks[] __initdata = {
>> /* list of divider clocks supported in all exynos4 soc's */
>> static struct samsung_div_clock exynos4_div_clks[] __initdata = {
>> - DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
>> - DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
>> DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
>> DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
>> DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
>> @@ -484,8 +482,8 @@ static struct samsung_div_clock
>> exynos4_div_clks[] __initdata = { DIV(0, "div_spi_pre2", "div_spi2",
>> DIV_PERIL2, 8, 8), DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0,
>> 4), DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
>> - DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
>> - DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24,
>> 3),
>> + DIV_F(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24,
>> 3,
>> + CLK_GET_RATE_NOCACHE, 0),
>> DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
>> CLK_SET_RATE_PARENT, 0),
>> DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
>> @@ -870,7 +868,6 @@ static struct samsung_gate_clock
>> exynos4x12_gate_clks[] __initdata = {
>> static struct samsung_clock_alias exynos4_aliases[] __initdata = {
>> ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
>> - ALIAS(CLK_ARM_CLK, NULL, "armclk"),
>> ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
>> };
>>
>> @@ -1125,12 +1122,14 @@ static void __init exynos4_clk_init(struct
>> device_node *np, samsung_clk_register_alias(exynos4_aliases,
>> ARRAY_SIZE(exynos4_aliases));
>>
>> + samsung_register_arm_clock(np, CLK_ARM_CLK, "mout_apll",
>> reg_base); +
>
> I've got some doubts about allowing only the "mout_apll" clock to be the
> only parent for armclk Samsung clock.
>
> For the Exynos4412 it is also valid to have SCLK_MPLL_USER_C [*] as a
> parent for this clock.
>
> The problem is that you are reparenting the armclk to [*] with the
> register modification - no CCF involved.
The MUX_CORE mux is part of the larger cpu clock type and not
registered as a separate mux clock with CCF. So I would like to know
if there are any potential issues you see if this mux clock is
internally managed within the set_rate of the larger cpu clock type.
>
> I just would like to know if this is yours design decision or
> something, that we have overlooked in the v1 of this patch series.
I did overlook this one. This will be fixed in the next version by
ensuring that the dividers for SCLK_HPM clock will be updated only if
mout_apll is the parent of the MUX_HPM clock mux.
Thanks,
Thomas.
>
>> pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
>> "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk =
>> %ld\n", exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
>> _get_rate("sclk_apll"),
>> _get_rate("sclk_mpll"), _get_rate("sclk_epll"),
>> _get_rate("sclk_vpll"),
>> - _get_rate("arm_clk"));
>> + _get_rate("armclk"));
>> }
>>
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5250.c
>> b/drivers/clk/samsung/clk-exynos5250.c index ff4beeb..487be36 100644
>> --- a/drivers/clk/samsung/clk-exynos5250.c
>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>> @@ -298,9 +298,8 @@ static struct samsung_div_clock
>> exynos5250_div_clks[] __initdata = { /*
>> * CMU_CPU
>> */
>> - DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
>> - DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
>> - DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
>> + DIV_F(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
>> + CLK_GET_RATE_NOCACHE, 0),
>>
>> /*
>> * CMU_TOP
>> @@ -684,8 +683,9 @@ static void __init exynos5250_clk_init(struct
>> device_node *np) ARRAY_SIZE(exynos5250_div_clks));
>> samsung_clk_register_gate(exynos5250_gate_clks,
>> ARRAY_SIZE(exynos5250_gate_clks));
>> + samsung_register_arm_clock(np, CLK_ARM_CLK, "mout_apll",
>> reg_base);
>> pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
>> - _get_rate("div_arm2"));
>> + _get_rate("armclk"));
>> }
>> CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock",
>> exynos5250_clk_init); diff --git
>> a/include/dt-bindings/clock/exynos5250.h
>> b/include/dt-bindings/clock/exynos5250.h index 922f2dc..59a10fb
>> 100644 --- a/include/dt-bindings/clock/exynos5250.h +++
>> b/include/dt-bindings/clock/exynos5250.h @@ -21,6 +21,7 @@
>> #define CLK_FOUT_CPLL 6
>> #define CLK_FOUT_EPLL 7
>> #define CLK_FOUT_VPLL 8
>> +#define CLK_ARM_CLK 12
>>
>> /* gate for special clocks (sclk) */
>> #define CLK_SCLK_CAM_BAYER 128
>
>
>
> --
> Best regards,
>
> Lukasz Majewski
>
> Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply
* [linux-sunxi] Re: [PATCH RFC v4 00/10] ahci: library-ise ahci_platform, add sunxi driver and cleanup imx driver
From: Hans de Goede @ 2014-01-21 7:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b8dd9fd4-02ce-4656-8b92-49f2ab82cc69@googlegroups.com>
Hi,
On 01/20/2014 08:53 PM, Ezaul Zillmer wrote:
> hi Hans
>
> First wanted to thank his work with sunxi ... as they say here in Brazil you're the guy !
>
> I noticed the following after your upgrade .. 01/20/2014 my ATA does not look rose more !
> # # # # Here before UP ! # # # # #
>
> Image Name : Linux - 3.13.0 - rc7
>
> [ 1.150317 ] 8021Q : 802.1Q VLAN Support v1.8
> [ 1.154585 ] Key type dns_resolver registered
> [ 1.159130 ] Registering SWP / SWPB emulation handler
> [ 1.165146 ] ahci - 5v : 5000 mV
> [ 1.168509 ] usb1 - VBUS : 5000 mV
> [ 1.172082 ] usb2 - VBUS : 5000 mV
> [ 1.200799 ] ahci sunxi - 1c18000.ahci : controller can not do PMP , turning off CAP_PMP
> [ 1.208303 ] sunxi 1c18000.ahci - ahci : forcing PORTS_IMPL to 0x1
> [ 1.214179 ] sunxi 1c18000.ahci - ahci : AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl sunxi mode
> [ 1.222903 ] sunxi 1c18000.ahci - ahci : flags : NCQ SNTF pm led clo pio slum part ccc only
> [ 1.231594 ] scsi0 : sunxi_ahci
> [ 1.234955 ] ATA1 : SATA max UDMA/133 irq 88
> [ 1.239639 ] ehci - sunxi 1c14000.ehci0 : EHCI Host Controller
> [ 1.245171 ] ehci - sunxi 1c14000.ehci0 : new USB bus registered , assigned bus number 2
> [ 1.252978 ] ehci - sunxi 1c14000.ehci0 : irq 71 , io mem 0x01c14000
> [ 1.269124 ] ehci - sunxi 1c14000.ehci0 : USB 2.0 started , EHCI 1:00
> [ 1.275924 ] hub 2-0:1.0 : USB hub found
> [ 1.279773 ] hub 2-0:1.0 : 1 port detected
> [ 1.284455 ] ehci - sunxi 1c1c000.ehci1 : EHCI Host Controller
> [ 1.290026 ] ehci - sunxi 1c1c000.ehci1 : new USB bus registered , assigned bus number 3
> [ 1.297789 ] ehci - sunxi 1c1c000.ehci1 : irq 72 , io mem 0x01c1c000
> [ 1.319118 ] ehci - sunxi 1c1c000.ehci1 : USB 2.0 started , EHCI 1:00
> [ 1.325805 ] hub 3-0:1.0 : USB hub found
> [ 1.329639 ] hub 3-0:1.0 : 1 port detected
> [ 1.333894 ] rtc - sunxi 1c20d00.rtc : setting system clock to 1970-01-01 00:00:08 UTC ( 8 )
> [ 1.584180 ] mmc0 : new high speed SDHC card at address E624
> [ 1.590049 ] isa bounce pool size: 16 pages
> [ 1.594297 ] mmcblk0 : mmc0 : E624 SU08G 7:40 GiB
> [ 1.600605 ] mmcblk0 : p1
> [ 4.889135 ] ATA1 : SATA link up 3.0 Gbps ( sstatus 123 SControl 300 )
> [ 4.904967 ] ata1.00 : ATA - 8 : SAMSUNG HM320II , 2AC101C4 , max UDMA/133
> [ 4.911260 ] ata1.00 : 625142448 sectors , multi 0 : LBA48 NCQ (depth 31/32 )
> [ 4.927633 ] ata1.00 : configured for UDMA/133
> [ 4.932311 ] scsi 0:0:0:0 : Direct -Access ATA SAMSUNG HM320II 2AC1 PQ : 0 ANSI : 5
> [ 4.941156 ] sd 0:0:0:0 : [ sda ] 625142448 512 - byte logical blocks : ( 320 GB/298 GiB )
> [ 4.948875 ] sd 0:0:0:0 : [ sda ] Write Protect is off
> [ 4.953822 ] sd 0:0:0:0 : [ sda ] Write cache : enabled , read cache : enabled , does not support DPO or FUA
> [ 4.975349 ] sda : sda1
> [ 4.978721 ] sd 0:0:0:0 : [ sda ] Attached SCSI disk
> [ 5.000798 ] EXT4 - fs ( mmcblk0p1 ) : mounted filesystem with ordered data mode . Opts : ( null)
> [ 5.008962 ] VFS : Mounted root ( ext4 filesystem ) readonly on device 179:1 .
> [ 5.016841 ] devtmpfs : mounted
> [ 5.020432 ] Freeing unused kernel memory: 528k ( c0922000 - c09a6000 )
> INIT : version 2.88 booting
>
>
>
> # # # # NOW AFTER UP # # # # # # # # # # #
>
> Even . Config
> git pull
>
>
> [ 1.183099 ] ip6_tables : ( C ) 2000-2006 Netfilter Core Team
> [ 1.188522 ] sit : IPv6 over IPv4 tunneling driver
> [ 1.193777 ] NET : Registered protocol family 17
> [ 1.198369 ] Bridge firewalling registered
> [ 1.202495 ] l2tp_core : L2TP core driver , V2.0
> [ 1.206861 ] 8021Q : 802.1Q VLAN Support v1.8
> [ 1.210139 ] ATA1 : SATA link down ( sstatus 0 SControl 300 )
> [ 1.216491 ] lib80211 : common routines for IEEE802.11 drivers
> [ 1.222231 ] Key type dns_resolver registered
> [ 1.226770 ] Registering SWP / SWPB emulation handler
> [ 1.232696 ] ahci - 5v : 5000 mV
> [ 1.236057 ] usb1 - VBUS : 5000 mV
> [ 1.239504 ] usb2 - VBUS : 5000 mV
> [ 1.243904 ] rtc - sunxi 1c20d00.rtc : setting system clock to 1970-01-01 00:00:08 UTC ( 8 )
> [ 1.252615 ] Waiting for device / dev/mmcblk0p1 root ...
> [ 1.599045 ] mmc0 : new high speed SDHC card at address E624
> [ 1.604917 ] isa bounce pool size: 16 pages
> [ 1.609178 ] mmcblk0 : mmc0 : E624 SU08G 7:40 GiB
> [ 1.615470 ] mmcblk0 : p1
> [ 1.692426 ] EXT4 - fs ( mmcblk0p1 ) : INFO : recovery required on readonly filesystem
> [ 1.699757 ] EXT4 - fs ( mmcblk0p1 ) : write access will be enabled During recovery
> [ 2.423617 ] random: nonblocking pool is initialized
> [ 3.274181 ] EXT4 - fs ( mmcblk0p1 ) : recovery complete
> [ 3.286043 ] EXT4 - fs ( mmcblk0p1 ) : mounted filesystem with ordered data mode . Opts : ( null)
> [ 3.294229 ] VFS : Mounted root ( ext4 filesystem ) readonly on device 179:1 .
> [ 3.302179 ] devtmpfs : mounted
> [ 3.305714 ] Freeing unused kernel memory: 524K ( c0959000 - c09dc000 )
> INIT : version 2.88 booting
>
>
> What could it be? says Down !
> Copy your old uImage UP
> new uImage DOWN
Which kernel tree are you using ? Did you not only update the uImage but also the dtb? I'm not seeing
any ahci related messages at all in the new dmesg output, so it seems that either your dtb does not have
an ahci node (or not with the proper compatible= string), or sunxi-ahci is not build into your kernel.
Regards,
Hans
^ permalink raw reply
* [PATCH v2 1/2] dmaengine: add Qualcomm BAM dma driver
From: Arnd Bergmann @ 2014-01-21 8:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140120225245.GA3530@qualcomm.com>
On Monday 20 January 2014 16:52:45 Andy Gross wrote:
> > > +#ifdef CONFIG_OF
> > > +static const struct of_device_id bam_of_match[] = {
> > > + { .compatible = "qcom,bam-v1.4.0", },
> > > + { .compatible = "qcom,bam-v1.4.1", },
> > > + {}
> > > +};
> > > +MODULE_DEVICE_TABLE(of, bam_of_match);
> > > +#endif
> >
> > Also, you can remove the #ifdef here and the of_match_ptr() below.
> >
>
> If this is removed, then I'll have to add the OF dependency in the Kconfig,
> correct?
I believe it will still compile without the CONFIG_OF dependency, but
having the dependency still makes sense as it's impossible to use the
driver without CONFIG_OF.
The best dependency line is probably
depends on (ARCH_MSM && OF) || COMPILE_TEST"
If you expect the same driver to be used on non-MSM platforms from
qualcomm, e.g. some networking or server equipment, you can also just
drop the ARCH_MSM dependency.
Arnd
^ permalink raw reply
* [PATCH] clk: nomadik: fix multiplatform problem
From: Linus Walleij @ 2014-01-21 8:06 UTC (permalink / raw)
To: linux-arm-kernel
The Nomadik debugfs screws up multiplatform boots if debugfs
is enabled on the multiplatform image, since it's a simple
initcall that is unconditionally executed and reads from certain
memory locations.
Fix this by checking that the driver has been properly
initialized, so a base offset to the Nomadik SRC controller
exists, before proceeding to register debugfs files.
Reported-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/clk/clk-nomadik.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c
index 6a934a5296bd..05e04ce0f148 100644
--- a/drivers/clk/clk-nomadik.c
+++ b/drivers/clk/clk-nomadik.c
@@ -494,6 +494,9 @@ static const struct file_operations nomadik_src_clk_debugfs_ops = {
static int __init nomadik_src_clk_init_debugfs(void)
{
+ /* Vital for multiplatform */
+ if (!src_base)
+ return -ENODEV;
src_pcksr0_boot = readl(src_base + SRC_PCKSR0);
src_pcksr1_boot = readl(src_base + SRC_PCKSR1);
debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO,
--
1.8.4.2
^ permalink raw reply related
* Nomadik clk not MULTI_V5 friendly
From: Linus Walleij @ 2014-01-21 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140120220118.GN15169@lunn.ch>
On Mon, Jan 20, 2014 at 11:01 PM, Andrew Lunn <andrew@lunn.ch> wrote:
> It does not check if it is actually running on a Nomadik, so when this
> module_init() is executed on kirkwood as part of a MULTI_V5 kernel,
> bad things happen. Please could you add the necessary check.
Sure, fixed it, can you test and provide your Tested-by tag to Mike
so he can merge it?
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support
From: Thomas Abraham @ 2014-01-21 8:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140120090815.39e8c21a@amdc2363>
Hi Lukasz,
On Mon, Jan 20, 2014 at 1:38 PM, Lukasz Majewski <l.majewski@samsung.com> wrote:
> Hi Thomas,
>
>> From: Thomas Abraham <thomas.ab@samsung.com>
>>
>> Exynos4210, Exynos4x12 and Exynos5250 based platforms have switched
>> over to use cpufreq-cpu0 driver for cpufreq functionality. So the
>> Exynos specific cpufreq drivers for these platforms can be removed.
>>
>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>> Cc: Jaecheol Lee <jc.lee@samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>> ---
>> drivers/cpufreq/Kconfig.arm | 36 ----
>> drivers/cpufreq/Makefile | 4 -
>> drivers/cpufreq/exynos-cpufreq.c | 292
>> ----------------------------------
>> drivers/cpufreq/exynos-cpufreq.h | 91 -----------
>> drivers/cpufreq/exynos4210-cpufreq.c | 157 ------------------
>> drivers/cpufreq/exynos4x12-cpufreq.c | 211 ------------------------
>> drivers/cpufreq/exynos5250-cpufreq.c | 183 --------------------- 7
>> files changed, 0 insertions(+), 974 deletions(-) delete mode 100644
>> drivers/cpufreq/exynos-cpufreq.c delete mode 100644
>> drivers/cpufreq/exynos-cpufreq.h delete mode 100644
>> drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644
>> drivers/cpufreq/exynos4x12-cpufreq.c delete mode 100644
>> drivers/cpufreq/exynos5250-cpufreq.c
>>
>> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
>> index 3129749..704656d 100644
>> --- a/drivers/cpufreq/Kconfig.arm
>> +++ b/drivers/cpufreq/Kconfig.arm
>> @@ -16,42 +16,6 @@ config ARM_DT_BL_CPUFREQ
>> This enables probing via DT for Generic CPUfreq driver for
>> ARM big.LITTLE platform. This gets frequency tables from DT.
>>
>> -config ARM_EXYNOS_CPUFREQ
>> - bool
>> -
>> -config ARM_EXYNOS4210_CPUFREQ
>> - bool "SAMSUNG EXYNOS4210"
>> - depends on CPU_EXYNOS4210
>> - default y
>> - select ARM_EXYNOS_CPUFREQ
>> - help
>> - This adds the CPUFreq driver for Samsung EXYNOS4210
>> - SoC (S5PV310 or S5PC210).
>> -
>> - If in doubt, say N.
>> -
>> -config ARM_EXYNOS4X12_CPUFREQ
>> - bool "SAMSUNG EXYNOS4x12"
>> - depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
>> - default y
>> - select ARM_EXYNOS_CPUFREQ
>> - help
>> - This adds the CPUFreq driver for Samsung EXYNOS4X12
>> - SoC (EXYNOS4212 or EXYNOS4412).
>> -
>> - If in doubt, say N.
>> -
>> -config ARM_EXYNOS5250_CPUFREQ
>> - bool "SAMSUNG EXYNOS5250"
>> - depends on SOC_EXYNOS5250
>> - default y
>> - select ARM_EXYNOS_CPUFREQ
>> - help
>> - This adds the CPUFreq driver for Samsung EXYNOS5250
>> - SoC.
>> -
>> - If in doubt, say N.
>> -
>> config ARM_EXYNOS5440_CPUFREQ
>> bool "SAMSUNG EXYNOS5440"
>> depends on SOC_EXYNOS5440
>> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
>> index 7494565..3abfe05 100644
>> --- a/drivers/cpufreq/Makefile
>> +++ b/drivers/cpufreq/Makefile
>> @@ -49,10 +49,6 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) +=
>> arm_big_little_dt.o
>> obj-$(CONFIG_ARCH_DAVINCI_DA850) += davinci-cpufreq.o
>> obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
>> -obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
>> -obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
>> -obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
>> -obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
>> obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
>> obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
>> obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
>> diff --git a/drivers/cpufreq/exynos-cpufreq.c
>> b/drivers/cpufreq/exynos-cpufreq.c deleted file mode 100644
>> index fcd2914..0000000
>> --- a/drivers/cpufreq/exynos-cpufreq.c
>> +++ /dev/null
>> @@ -1,292 +0,0 @@
>> -/*
>> - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
>> - * http://www.samsung.com
>> - *
>> - * EXYNOS - CPU frequency scaling support for EXYNOS series
>> - *
>> - * This program is free software; you can redistribute it and/or
>> modify
>> - * it under the terms of the GNU General Public License version 2 as
>> - * published by the Free Software Foundation.
>> -*/
>> -
>> -#include <linux/kernel.h>
>> -#include <linux/err.h>
>> -#include <linux/clk.h>
>> -#include <linux/io.h>
>> -#include <linux/slab.h>
>> -#include <linux/regulator/consumer.h>
>> -#include <linux/cpufreq.h>
>> -#include <linux/suspend.h>
>> -#include <linux/platform_device.h>
>> -
>> -#include <plat/cpu.h>
>> -
>> -#include "exynos-cpufreq.h"
>> -
>> -static struct exynos_dvfs_info *exynos_info;
>> -
>> -static struct regulator *arm_regulator;
>> -
>> -static unsigned int locking_frequency;
>> -static bool frequency_locked;
>> -static DEFINE_MUTEX(cpufreq_lock);
>> -
>> -static int exynos_cpufreq_get_index(unsigned int freq)
>> -{
>> - struct cpufreq_frequency_table *freq_table =
>> exynos_info->freq_table;
>> - int index;
>> -
>> - for (index = 0;
>> - freq_table[index].frequency != CPUFREQ_TABLE_END;
>> index++)
>> - if (freq_table[index].frequency == freq)
>> - break;
>> -
>> - if (freq_table[index].frequency == CPUFREQ_TABLE_END)
>> - return -EINVAL;
>> -
>> - return index;
>> -}
>> -
>> -static int exynos_cpufreq_scale(unsigned int target_freq)
>> -{
>> - struct cpufreq_frequency_table *freq_table =
>> exynos_info->freq_table;
>> - unsigned int *volt_table = exynos_info->volt_table;
>> - struct cpufreq_policy *policy = cpufreq_cpu_get(0);
>> - unsigned int arm_volt, safe_arm_volt = 0;
>> - unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
>> - unsigned int old_freq;
>> - int index, old_index;
>> - int ret = 0;
>> -
>> - old_freq = policy->cur;
>> -
>> - /*
>> - * The policy max have been changed so that we cannot get
>> proper
>> - * old_index with cpufreq_frequency_table_target(). Thus,
>> ignore
>> - * policy and get the index from the raw frequency table.
>> - */
>> - old_index = exynos_cpufreq_get_index(old_freq);
>> - if (old_index < 0) {
>> - ret = old_index;
>> - goto out;
>> - }
>> -
>> - index = exynos_cpufreq_get_index(target_freq);
>> - if (index < 0) {
>> - ret = index;
>> - goto out;
>> - }
>> -
>> - /*
>> - * ARM clock source will be changed APLL to MPLL temporary
>> - * To support this level, need to control regulator for
>> - * required voltage level
>> - */
>> - if (exynos_info->need_apll_change != NULL) {
>> - if (exynos_info->need_apll_change(old_index, index)
>> &&
>> - (freq_table[index].frequency < mpll_freq_khz) &&
>> - (freq_table[old_index].frequency < mpll_freq_khz))
>> - safe_arm_volt =
>> volt_table[exynos_info->pll_safe_idx];
>> - }
>> - arm_volt = volt_table[index];
>> -
>> - /* When the new frequency is higher than current frequency */
>> - if ((target_freq > old_freq) && !safe_arm_volt) {
>> - /* Firstly, voltage up to increase frequency */
>> - ret = regulator_set_voltage(arm_regulator, arm_volt,
>> arm_volt);
>> - if (ret) {
>> - pr_err("%s: failed to set cpu voltage to
>> %d\n",
>> - __func__, arm_volt);
>> - return ret;
>> - }
>> - }
>> -
>> - if (safe_arm_volt) {
>> - ret = regulator_set_voltage(arm_regulator,
>> safe_arm_volt,
>> - safe_arm_volt);
>> - if (ret) {
>> - pr_err("%s: failed to set cpu voltage to
>> %d\n",
>> - __func__, safe_arm_volt);
>> - return ret;
>> - }
>> - }
>> -
>> - exynos_info->set_freq(old_index, index);
>> -
>> - /* When the new frequency is lower than current frequency */
>> - if ((target_freq < old_freq) ||
>> - ((target_freq > old_freq) && safe_arm_volt)) {
>> - /* down the voltage after frequency change */
>> - ret = regulator_set_voltage(arm_regulator, arm_volt,
>> - arm_volt);
>> - if (ret) {
>> - pr_err("%s: failed to set cpu voltage to
>> %d\n",
>> - __func__, arm_volt);
>> - goto out;
>> - }
>> - }
>> -
>> -out:
>> - cpufreq_cpu_put(policy);
>> -
>> - return ret;
>> -}
>> -
>> -static int exynos_target(struct cpufreq_policy *policy, unsigned int
>> index) -{
>> - struct cpufreq_frequency_table *freq_table =
>> exynos_info->freq_table;
>> - int ret = 0;
>> -
>> - mutex_lock(&cpufreq_lock);
>> -
>> - if (frequency_locked)
>> - goto out;
>> -
>> - ret = exynos_cpufreq_scale(freq_table[index].frequency);
>> -
>> -out:
>> - mutex_unlock(&cpufreq_lock);
>> -
>> - return ret;
>> -}
>> -
>> -#ifdef CONFIG_PM
>> -static int exynos_cpufreq_suspend(struct cpufreq_policy *policy)
>> -{
>> - return 0;
>> -}
>> -
>> -static int exynos_cpufreq_resume(struct cpufreq_policy *policy)
>> -{
>> - return 0;
>> -}
>> -#endif
>> -
>> -/**
>> - * exynos_cpufreq_pm_notifier - block CPUFREQ's activities in
>> suspend-resume
>> - * context
>> - * @notifier
>> - * @pm_event
>> - * @v
>> - *
>> - * While frequency_locked == true, target() ignores every frequency
>> but
>> - * locking_frequency. The locking_frequency value is the initial
>> frequency,
>> - * which is set by the bootloader. In order to eliminate possible
>> - * inconsistency in clock values, we save and restore frequencies
>> during
>> - * suspend and resume and block CPUFREQ activities. Note that the
>> standard
>> - * suspend/resume cannot be used as they are too deep (syscore_ops)
>> for
>> - * regulator actions.
>> - */
>> -static int exynos_cpufreq_pm_notifier(struct notifier_block
>> *notifier,
>> - unsigned long pm_event, void
>> *v) -{
>> - int ret;
>> -
>> - switch (pm_event) {
>> - case PM_SUSPEND_PREPARE:
>> - mutex_lock(&cpufreq_lock);
>> - frequency_locked = true;
>> - mutex_unlock(&cpufreq_lock);
>> -
>> - ret = exynos_cpufreq_scale(locking_frequency);
>> - if (ret < 0)
>> - return NOTIFY_BAD;
>> -
>> - break;
>> -
>> - case PM_POST_SUSPEND:
>> - mutex_lock(&cpufreq_lock);
>> - frequency_locked = false;
>> - mutex_unlock(&cpufreq_lock);
>> - break;
>> - }
>> -
>> - return NOTIFY_OK;
>> -}
>> -
>> -static struct notifier_block exynos_cpufreq_nb = {
>> - .notifier_call = exynos_cpufreq_pm_notifier,
>> -};
>> -
>> -static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
>> -{
>> - policy->clk = exynos_info->cpu_clk;
>> - return cpufreq_generic_init(policy, exynos_info->freq_table,
>> 100000); -}
>> -
>> -static struct cpufreq_driver exynos_driver = {
>> - .flags = CPUFREQ_STICKY |
>> CPUFREQ_NEED_INITIAL_FREQ_CHECK,
>> - .verify =
>> cpufreq_generic_frequency_table_verify,
>> - .target_index = exynos_target,
>> - .get = cpufreq_generic_get,
>> - .init = exynos_cpufreq_cpu_init,
>> - .exit = cpufreq_generic_exit,
>> - .name = "exynos_cpufreq",
>> - .attr = cpufreq_generic_attr,
>> -#ifdef CONFIG_ARM_EXYNOS_CPU_FREQ_BOOST_SW
>> - .boost_supported = true,
>> -#endif
>> -#ifdef CONFIG_PM
>> - .suspend = exynos_cpufreq_suspend,
>> - .resume = exynos_cpufreq_resume,
>> -#endif
>> -};
>> -
>> -static int exynos_cpufreq_probe(struct platform_device *pdev)
>> -{
>> - int ret = -EINVAL;
>> -
>> - exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL);
>> - if (!exynos_info)
>> - return -ENOMEM;
>> -
>> - if (soc_is_exynos4210())
>> - ret = exynos4210_cpufreq_init(exynos_info);
>> - else if (soc_is_exynos4212() || soc_is_exynos4412())
>> - ret = exynos4x12_cpufreq_init(exynos_info);
>> - else if (soc_is_exynos5250())
>> - ret = exynos5250_cpufreq_init(exynos_info);
>> - else
>> - return 0;
>> -
>> - if (ret)
>> - goto err_vdd_arm;
>> -
>> - if (exynos_info->set_freq == NULL) {
>> - pr_err("%s: No set_freq function (ERR)\n", __func__);
>> - goto err_vdd_arm;
>> - }
>> -
>> - arm_regulator = regulator_get(NULL, "vdd_arm");
>> - if (IS_ERR(arm_regulator)) {
>> - pr_err("%s: failed to get resource vdd_arm\n",
>> __func__);
>> - goto err_vdd_arm;
>> - }
>> -
>> - locking_frequency = clk_get_rate(exynos_info->cpu_clk) /
>> 1000; -
>> - register_pm_notifier(&exynos_cpufreq_nb);
>> -
>> - if (cpufreq_register_driver(&exynos_driver)) {
>> - pr_err("%s: failed to register cpufreq driver\n",
>> __func__);
>> - goto err_cpufreq;
>> - }
>> -
>> - return 0;
>> -err_cpufreq:
>> - unregister_pm_notifier(&exynos_cpufreq_nb);
>> -
>> - regulator_put(arm_regulator);
>> -err_vdd_arm:
>> - kfree(exynos_info);
>> - return -EINVAL;
>> -}
>> -
>> -static struct platform_driver exynos_cpufreq_platdrv = {
>> - .driver = {
>> - .name = "exynos-cpufreq",
>> - .owner = THIS_MODULE,
>> - },
>> - .probe = exynos_cpufreq_probe,
>> -};
>> -module_platform_driver(exynos_cpufreq_platdrv);
>> diff --git a/drivers/cpufreq/exynos-cpufreq.h
>> b/drivers/cpufreq/exynos-cpufreq.h deleted file mode 100644
>> index 3ddade8..0000000
>> --- a/drivers/cpufreq/exynos-cpufreq.h
>> +++ /dev/null
>> @@ -1,91 +0,0 @@
>> -/*
>> - * Copyright (c) 2010 Samsung Electronics Co., Ltd.
>> - * http://www.samsung.com
>> - *
>> - * EXYNOS - CPUFreq support
>> - *
>> - * This program is free software; you can redistribute it and/or
>> modify
>> - * it under the terms of the GNU General Public License version 2 as
>> - * published by the Free Software Foundation.
>> -*/
>> -
>> -enum cpufreq_level_index {
>> - L0, L1, L2, L3, L4,
>> - L5, L6, L7, L8, L9,
>> - L10, L11, L12, L13, L14,
>> - L15, L16, L17, L18, L19,
>> - L20,
>> -};
>> -
>> -#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m,
>> p, s) \
>> - { \
>> - .freq = (f) * 1000, \
>> - .clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3)
>> << 12 | \
>> - (a4) << 16 | (a5) << 20 | (a6) << 24 | (a7)
>> << 28), \
>> - .clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \
>> - .mps = ((m) << 16 | (p) << 8 | (s)), \
>> - }
>> -
>> -struct apll_freq {
>> - unsigned int freq;
>> - u32 clk_div_cpu0;
>> - u32 clk_div_cpu1;
>> - u32 mps;
>> -};
>> -
>> -struct exynos_dvfs_info {
>> - unsigned long mpll_freq_khz;
>> - unsigned int pll_safe_idx;
>> - struct clk *cpu_clk;
>> - unsigned int *volt_table;
>> - struct cpufreq_frequency_table *freq_table;
>> - void (*set_freq)(unsigned int, unsigned int);
>> - bool (*need_apll_change)(unsigned int, unsigned int);
>> -};
>> -
>> -#ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ
>> -extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
>> -#else
>> -static inline int exynos4210_cpufreq_init(struct exynos_dvfs_info
>> *info) -{
>> - return -EOPNOTSUPP;
>> -}
>> -#endif
>> -#ifdef CONFIG_ARM_EXYNOS4X12_CPUFREQ
>> -extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
>> -#else
>> -static inline int exynos4x12_cpufreq_init(struct exynos_dvfs_info
>> *info) -{
>> - return -EOPNOTSUPP;
>> -}
>> -#endif
>> -#ifdef CONFIG_ARM_EXYNOS5250_CPUFREQ
>> -extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
>> -#else
>> -static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info
>> *info) -{
>> - return -EOPNOTSUPP;
>> -}
>> -#endif
>> -
>> -#include <plat/cpu.h>
>> -#include <mach/map.h>
>> -
>> -#define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU +
>> 0x14200) -#define EXYNOS4_CLKMUX_STATCPU
>> (S5P_VA_CMU + 0x14400) -
>> -#define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU +
>> 0x14500) -#define EXYNOS4_CLKDIV_CPU1
>> (S5P_VA_CMU + 0x14504) -#define
>> EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU + 0x14600)
>> -#define EXYNOS4_CLKDIV_STATCPU1 (S5P_VA_CMU +
>> 0x14604) - -#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
>> -#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 <<
>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) -
>> -#define EXYNOS5_APLL_LOCK (S5P_VA_CMU +
>> 0x00000) -#define EXYNOS5_APLL_CON0
>> (S5P_VA_CMU + 0x00100) -#define
>> EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU + 0x00400)
>> -#define EXYNOS5_CLKDIV_CPU0 (S5P_VA_CMU +
>> 0x00500) -#define EXYNOS5_CLKDIV_CPU1
>> (S5P_VA_CMU + 0x00504) -#define
>> EXYNOS5_CLKDIV_STATCPU0 (S5P_VA_CMU + 0x00600)
>> -#define EXYNOS5_CLKDIV_STATCPU1 (S5P_VA_CMU +
>> 0x00604) diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
>> b/drivers/cpufreq/exynos4210-cpufreq.c deleted file mode 100644 index
>> 40d84c4..0000000 --- a/drivers/cpufreq/exynos4210-cpufreq.c
>> +++ /dev/null @@ -1,157 +0,0 @@
>> -/*
>> - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
>> - * http://www.samsung.com
>> - *
>> - * EXYNOS4210 - CPU frequency scaling support
>> - *
>> - * This program is free software; you can redistribute it and/or
>> modify
>> - * it under the terms of the GNU General Public License version 2 as
>> - * published by the Free Software Foundation.
>> -*/
>> -
>> -#include <linux/module.h>
>> -#include <linux/kernel.h>
>> -#include <linux/err.h>
>> -#include <linux/clk.h>
>> -#include <linux/io.h>
>> -#include <linux/slab.h>
>> -#include <linux/cpufreq.h>
>> -
>> -#include "exynos-cpufreq.h"
>> -
>> -static struct clk *cpu_clk;
>> -static struct clk *moutcore;
>> -static struct clk *mout_mpll;
>> -static struct clk *mout_apll;
>> -
>> -static unsigned int exynos4210_volt_table[] = {
>> - 1250000, 1150000, 1050000, 975000, 950000,
>> -};
>> -
>> -static struct cpufreq_frequency_table exynos4210_freq_table[] = {
>> - {L0, 1200 * 1000},
>> - {L1, 1000 * 1000},
>> - {L2, 800 * 1000},
>> - {L3, 500 * 1000},
>> - {L4, 200 * 1000},
>> - {0, CPUFREQ_TABLE_END},
>> -};
>> -
>> -static struct apll_freq apll_freq_4210[] = {
>> - /*
>> - * values:
>> - * freq
>> - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB,
>> PCLK_DBG, APLL, RESERVED
>> - * clock divider for COPY, HPM, RESERVED
>> - * PLL M, P, S
>> - */
>> - APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
>> - APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
>> - APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
>> - APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
>> - APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
>> -};
>> -
>> -static void exynos4210_set_clkdiv(unsigned int div_index)
>> -{
>> - unsigned int tmp;
>> -
>> - /* Change Divider - CPU0 */
>> -
>> - tmp = apll_freq_4210[div_index].clk_div_cpu0;
>> -
>> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
>> -
>> - do {
>> - tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
>> - } while (tmp & 0x1111111);
>> -
>> - /* Change Divider - CPU1 */
>> -
>> - tmp = apll_freq_4210[div_index].clk_div_cpu1;
>> -
>> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
>> -
>> - do {
>> - tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
>> - } while (tmp & 0x11);
>> -}
>> -
>> -static void exynos4210_set_apll(unsigned int index)
>> -{
>> - unsigned int tmp, freq = apll_freq_4210[index].freq;
>> -
>> - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
>> - clk_set_parent(moutcore, mout_mpll);
>> -
>> - do {
>> - tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
>> - >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
>> - tmp &= 0x7;
>> - } while (tmp != 0x2);
>> -
>> - clk_set_rate(mout_apll, freq * 1000);
>> -
>> - /* MUX_CORE_SEL = APLL */
>> - clk_set_parent(moutcore, mout_apll);
>> -
>> - do {
>> - tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
>> - tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
>> - } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
>> -}
>> -
>> -static void exynos4210_set_frequency(unsigned int old_index,
>> - unsigned int new_index)
>> -{
>> - if (old_index > new_index) {
>> - exynos4210_set_clkdiv(new_index);
>> - exynos4210_set_apll(new_index);
>> - } else if (old_index < new_index) {
>> - exynos4210_set_apll(new_index);
>> - exynos4210_set_clkdiv(new_index);
>> - }
>> -}
>> -
>> -int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
>> -{
>> - unsigned long rate;
>> -
>> - cpu_clk = clk_get(NULL, "armclk");
>> - if (IS_ERR(cpu_clk))
>> - return PTR_ERR(cpu_clk);
>> -
>> - moutcore = clk_get(NULL, "moutcore");
>> - if (IS_ERR(moutcore))
>> - goto err_moutcore;
>> -
>> - mout_mpll = clk_get(NULL, "mout_mpll");
>> - if (IS_ERR(mout_mpll))
>> - goto err_mout_mpll;
>> -
>> - rate = clk_get_rate(mout_mpll) / 1000;
>> -
>> - mout_apll = clk_get(NULL, "mout_apll");
>> - if (IS_ERR(mout_apll))
>> - goto err_mout_apll;
>> -
>> - info->mpll_freq_khz = rate;
>> - /* 800Mhz */
>> - info->pll_safe_idx = L2;
>> - info->cpu_clk = cpu_clk;
>> - info->volt_table = exynos4210_volt_table;
>> - info->freq_table = exynos4210_freq_table;
>> - info->set_freq = exynos4210_set_frequency;
>> -
>> - return 0;
>> -
>> -err_mout_apll:
>> - clk_put(mout_mpll);
>> -err_mout_mpll:
>> - clk_put(moutcore);
>> -err_moutcore:
>> - clk_put(cpu_clk);
>> -
>> - pr_debug("%s: failed initialization\n", __func__);
>> - return -EINVAL;
>> -}
>> diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c
>> b/drivers/cpufreq/exynos4x12-cpufreq.c deleted file mode 100644
>> index 7c11ace..0000000
>> --- a/drivers/cpufreq/exynos4x12-cpufreq.c
>> +++ /dev/null
>> @@ -1,211 +0,0 @@
>> -/*
>> - * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
>> - * http://www.samsung.com
>> - *
>> - * EXYNOS4X12 - CPU frequency scaling support
>> - *
>> - * This program is free software; you can redistribute it and/or
>> modify
>> - * it under the terms of the GNU General Public License version 2 as
>> - * published by the Free Software Foundation.
>> -*/
>> -
>> -#include <linux/module.h>
>> -#include <linux/kernel.h>
>> -#include <linux/err.h>
>> -#include <linux/clk.h>
>> -#include <linux/io.h>
>> -#include <linux/slab.h>
>> -#include <linux/cpufreq.h>
>> -
>> -#include "exynos-cpufreq.h"
>> -
>> -static struct clk *cpu_clk;
>> -static struct clk *moutcore;
>> -static struct clk *mout_mpll;
>> -static struct clk *mout_apll;
>> -
>> -static unsigned int exynos4x12_volt_table[] = {
>> - 1350000, 1287500, 1250000, 1187500, 1137500, 1087500,
>> 1037500,
>> - 1000000, 987500, 975000, 950000, 925000, 900000, 900000
>> -};
>> -
>> -static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
>> - {CPUFREQ_BOOST_FREQ, 1500 * 1000},
>
> Here, you are removing BOOST support for Exynos4412, without any code,
> which brings back this functionality in the new code.
Sorry, I did not notice this new feature in here.
>
> I'd propose adding new property to cpus node and during
> operating-points parsing mark the entry at the cpufreq_frequency_table
> accordingly.
Okay, would you be adding support for this or do you want me to do this?
Thanks,
Thomas.
>
>> - {L1, 1400 * 1000},
>> - {L2, 1300 * 1000},
>> - {L3, 1200 * 1000},
>> - {L4, 1100 * 1000},
>> - {L5, 1000 * 1000},
>> - {L6, 900 * 1000},
>> - {L7, 800 * 1000},
>> - {L8, 700 * 1000},
>> - {L9, 600 * 1000},
>> - {L10, 500 * 1000},
>> - {L11, 400 * 1000},
>> - {L12, 300 * 1000},
>> - {L13, 200 * 1000},
>> - {0, CPUFREQ_TABLE_END},
>> -};
>> -
>> -static struct apll_freq *apll_freq_4x12;
>> -
>> -static struct apll_freq apll_freq_4212[] = {
>> - /*
>> - * values:
>> - * freq
>> - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB,
>> PCLK_DBG, APLL, CORE2
>> - * clock divider for COPY, HPM, RESERVED
>> - * PLL M, P, S
>> - */
>> - APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
>> - APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
>> - APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
>> - APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
>> - APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
>> - APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
>> - APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
>> - APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
>> - APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
>> - APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
>> - APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
>> - APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
>> - APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
>> - APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
>> -};
>> -
>> -static struct apll_freq apll_freq_4412[] = {
>> - /*
>> - * values:
>> - * freq
>> - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB,
>> PCLK_DBG, APLL, CORE2
>> - * clock divider for COPY, HPM, CORES
>> - * PLL M, P, S
>> - */
>> - APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
>> - APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
>> - APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
>> - APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
>> - APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
>> - APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
>> - APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
>> - APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
>> - APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
>> - APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
>> - APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
>> - APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
>> - APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
>> - APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
>> -};
>> -
>> -static void exynos4x12_set_clkdiv(unsigned int div_index)
>> -{
>> - unsigned int tmp;
>> - unsigned int stat_cpu1;
>> -
>> - /* Change Divider - CPU0 */
>> -
>> - tmp = apll_freq_4x12[div_index].clk_div_cpu0;
>> -
>> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
>> -
>> - while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
>> - cpu_relax();
>> -
>> - /* Change Divider - CPU1 */
>> - tmp = apll_freq_4x12[div_index].clk_div_cpu1;
>> -
>> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
>> - if (soc_is_exynos4212())
>> - stat_cpu1 = 0x11;
>> - else
>> - stat_cpu1 = 0x111;
>> -
>> - while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
>> - cpu_relax();
>> -}
>> -
>> -static void exynos4x12_set_apll(unsigned int index)
>> -{
>> - unsigned int tmp, freq = apll_freq_4x12[index].freq;
>> -
>> - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
>> - clk_set_parent(moutcore, mout_mpll);
>> -
>> - do {
>> - cpu_relax();
>> - tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
>> - >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
>> - tmp &= 0x7;
>> - } while (tmp != 0x2);
>> -
>> - clk_set_rate(mout_apll, freq * 1000);
>> -
>> - /* MUX_CORE_SEL = APLL */
>> - clk_set_parent(moutcore, mout_apll);
>> -
>> - do {
>> - cpu_relax();
>> - tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
>> - tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
>> - } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
>> -}
>> -
>> -static void exynos4x12_set_frequency(unsigned int old_index,
>> - unsigned int new_index)
>> -{
>> - if (old_index > new_index) {
>> - exynos4x12_set_clkdiv(new_index);
>> - exynos4x12_set_apll(new_index);
>> - } else if (old_index < new_index) {
>> - exynos4x12_set_apll(new_index);
>> - exynos4x12_set_clkdiv(new_index);
>> - }
>> -}
>> -
>> -int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
>> -{
>> - unsigned long rate;
>> -
>> - cpu_clk = clk_get(NULL, "armclk");
>> - if (IS_ERR(cpu_clk))
>> - return PTR_ERR(cpu_clk);
>> -
>> - moutcore = clk_get(NULL, "moutcore");
>> - if (IS_ERR(moutcore))
>> - goto err_moutcore;
>> -
>> - mout_mpll = clk_get(NULL, "mout_mpll");
>> - if (IS_ERR(mout_mpll))
>> - goto err_mout_mpll;
>> -
>> - rate = clk_get_rate(mout_mpll) / 1000;
>> -
>> - mout_apll = clk_get(NULL, "mout_apll");
>> - if (IS_ERR(mout_apll))
>> - goto err_mout_apll;
>> -
>> - if (soc_is_exynos4212())
>> - apll_freq_4x12 = apll_freq_4212;
>> - else
>> - apll_freq_4x12 = apll_freq_4412;
>> -
>> - info->mpll_freq_khz = rate;
>> - /* 800Mhz */
>> - info->pll_safe_idx = L7;
>> - info->cpu_clk = cpu_clk;
>> - info->volt_table = exynos4x12_volt_table;
>> - info->freq_table = exynos4x12_freq_table;
>> - info->set_freq = exynos4x12_set_frequency;
>> -
>> - return 0;
>> -
>> -err_mout_apll:
>> - clk_put(mout_mpll);
>> -err_mout_mpll:
>> - clk_put(moutcore);
>> -err_moutcore:
>> - clk_put(cpu_clk);
>> -
>> - pr_debug("%s: failed initialization\n", __func__);
>> - return -EINVAL;
>> -}
>> diff --git a/drivers/cpufreq/exynos5250-cpufreq.c
>> b/drivers/cpufreq/exynos5250-cpufreq.c deleted file mode 100644
>> index 5f90b82..0000000
>> --- a/drivers/cpufreq/exynos5250-cpufreq.c
>> +++ /dev/null
>> @@ -1,183 +0,0 @@
>> -/*
>> - * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
>> - * http://www.samsung.com
>> - *
>> - * EXYNOS5250 - CPU frequency scaling support
>> - *
>> - * This program is free software; you can redistribute it and/or
>> modify
>> - * it under the terms of the GNU General Public License version 2 as
>> - * published by the Free Software Foundation.
>> -*/
>> -
>> -#include <linux/module.h>
>> -#include <linux/kernel.h>
>> -#include <linux/err.h>
>> -#include <linux/clk.h>
>> -#include <linux/io.h>
>> -#include <linux/slab.h>
>> -#include <linux/cpufreq.h>
>> -
>> -#include <mach/map.h>
>> -
>> -#include "exynos-cpufreq.h"
>> -
>> -static struct clk *cpu_clk;
>> -static struct clk *moutcore;
>> -static struct clk *mout_mpll;
>> -static struct clk *mout_apll;
>> -
>> -static unsigned int exynos5250_volt_table[] = {
>> - 1300000, 1250000, 1225000, 1200000, 1150000,
>> - 1125000, 1100000, 1075000, 1050000, 1025000,
>> - 1012500, 1000000, 975000, 950000, 937500,
>> - 925000
>> -};
>> -
>> -static struct cpufreq_frequency_table exynos5250_freq_table[] = {
>> - {L0, 1700 * 1000},
>> - {L1, 1600 * 1000},
>> - {L2, 1500 * 1000},
>> - {L3, 1400 * 1000},
>> - {L4, 1300 * 1000},
>> - {L5, 1200 * 1000},
>> - {L6, 1100 * 1000},
>> - {L7, 1000 * 1000},
>> - {L8, 900 * 1000},
>> - {L9, 800 * 1000},
>> - {L10, 700 * 1000},
>> - {L11, 600 * 1000},
>> - {L12, 500 * 1000},
>> - {L13, 400 * 1000},
>> - {L14, 300 * 1000},
>> - {L15, 200 * 1000},
>> - {0, CPUFREQ_TABLE_END},
>> -};
>> -
>> -static struct apll_freq apll_freq_5250[] = {
>> - /*
>> - * values:
>> - * freq
>> - * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG,
>> APLL, ARM2
>> - * clock divider for COPY, HPM, RESERVED
>> - * PLL M, P, S
>> - */
>> - APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
>> - APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
>> - APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
>> - APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
>> - APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
>> - APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
>> - APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
>> - APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
>> - APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
>> - APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
>> - APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
>> - APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
>> - APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
>> - APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
>> - APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
>> - APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
>> -};
>> -
>> -static void set_clkdiv(unsigned int div_index)
>> -{
>> - unsigned int tmp;
>> -
>> - /* Change Divider - CPU0 */
>> -
>> - tmp = apll_freq_5250[div_index].clk_div_cpu0;
>> -
>> - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
>> -
>> - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
>> - cpu_relax();
>> -
>> - /* Change Divider - CPU1 */
>> - tmp = apll_freq_5250[div_index].clk_div_cpu1;
>> -
>> - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
>> -
>> - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
>> - cpu_relax();
>> -}
>> -
>> -static void set_apll(unsigned int index)
>> -{
>> - unsigned int tmp;
>> - unsigned int freq = apll_freq_5250[index].freq;
>> -
>> - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
>> - clk_set_parent(moutcore, mout_mpll);
>> -
>> - do {
>> - cpu_relax();
>> - tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
>> - tmp &= 0x7;
>> - } while (tmp != 0x2);
>> -
>> - clk_set_rate(mout_apll, freq * 1000);
>> -
>> - /* MUX_CORE_SEL = APLL */
>> - clk_set_parent(moutcore, mout_apll);
>> -
>> - do {
>> - cpu_relax();
>> - tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
>> - tmp &= (0x7 << 16);
>> - } while (tmp != (0x1 << 16));
>> -}
>> -
>> -static void exynos5250_set_frequency(unsigned int old_index,
>> - unsigned int new_index)
>> -{
>> - if (old_index > new_index) {
>> - set_clkdiv(new_index);
>> - set_apll(new_index);
>> - } else if (old_index < new_index) {
>> - set_apll(new_index);
>> - set_clkdiv(new_index);
>> - }
>> -}
>> -
>> -int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
>> -{
>> - unsigned long rate;
>> -
>> - cpu_clk = clk_get(NULL, "armclk");
>> - if (IS_ERR(cpu_clk))
>> - return PTR_ERR(cpu_clk);
>> -
>> - moutcore = clk_get(NULL, "mout_cpu");
>> - if (IS_ERR(moutcore))
>> - goto err_moutcore;
>> -
>> - mout_mpll = clk_get(NULL, "mout_mpll");
>> - if (IS_ERR(mout_mpll))
>> - goto err_mout_mpll;
>> -
>> - rate = clk_get_rate(mout_mpll) / 1000;
>> -
>> - mout_apll = clk_get(NULL, "mout_apll");
>> - if (IS_ERR(mout_apll))
>> - goto err_mout_apll;
>> -
>> - info->mpll_freq_khz = rate;
>> - /* 800Mhz */
>> - info->pll_safe_idx = L9;
>> - info->cpu_clk = cpu_clk;
>> - info->volt_table = exynos5250_volt_table;
>> - info->freq_table = exynos5250_freq_table;
>> - info->set_freq = exynos5250_set_frequency;
>> -
>> - return 0;
>> -
>> -err_mout_apll:
>> - clk_put(mout_mpll);
>> -err_mout_mpll:
>> - clk_put(moutcore);
>> -err_moutcore:
>> - clk_put(cpu_clk);
>> -
>> - pr_err("%s: failed initialization\n", __func__);
>> - return -EINVAL;
>> -}
>
>
>
> --
> Best regards,
>
> Lukasz Majewski
>
> Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply
* [PATCH] arch_timer: Move delay timer to drivers clocksource
From: Prashant Gaikwad @ 2014-01-21 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52DD35B3.9000606@linaro.org>
On Monday 20 January 2014 08:11 PM, Daniel Lezcano wrote:
> On 01/17/2014 02:40 PM, Prashant Gaikwad wrote:
>> On Friday 17 January 2014 05:38 PM, Daniel Lezcano wrote:
>>> On 01/17/2014 12:37 PM, Prashant Gaikwad wrote:
>>>> On Friday 17 January 2014 03:45 PM, Daniel Lezcano wrote:
>>>>> On 01/17/2014 11:11 AM, Prashant Gaikwad wrote:
>>>>>> On Friday 17 January 2014 02:42 PM, Daniel Lezcano wrote:
>>>>>>> On 01/17/2014 10:07 AM, Antti Miettinen wrote:
>>>>>>>> Will Deacon <will.deacon@arm.com> writes:
>>>>>>>>> Why can't you use the C3STOP feature so that the arch-timer isn't
>>>>>>>>> used when
>>>>>>>>> you go idle?
>>>>>>>> That would mean falling back to broadcast timer, right? That's not
>>>>>>>> necessarily on the local CPU so wakeups would often wake two CPUs.
>>>>>>> You can prevent that if the hardware supports it with the
>>>>>>> CLOCK_EVT_DYNIRQ flag on the broadcast timer.
>>>>>> Instead of falling back on broadcast timer, is it possible to fall
>>>>>> back
>>>>>> on other per-CPU timer which is preserved across idle state?
>>>>> Is it what you are looking for ?
>>>>>
>>>>> http://lwn.net/Articles/580568/
>>>>>
>>>> If I understand correctly these patches enables us to use per-CPU timers
>>>> as broadcast timers. I do not want to use broadcast timer.
>>> Why ?
>>>
>> For some idle states it may be required to change the timer when
>> entering idle state to adjust the exit latency.
>>
>> It can be done for broadcast timer too but following scenario will not work
>>
>> 1. CPU1 enters in idle state:
>> Broadcast timer next event is in 2ms, CPU latency is 50us. So
>> we change the broadcast timer to send event after (2ms - 50us).
>>
>> 2. After 1ms CPU2 enters in idle state:
>> Next event is 5ms. Broadcast timer is already programmed to <
>> (5ms -50us) so we do nothing.
>>
>> 3. CPU1 exits from idle state because of timer interrupt
>>
>> 4. Broadcast event handler:
>> - Timer event is handled and CPU1 is switched back to local timer.
>> - Next CPU is CPU2 and next event for it is 4ms. So brodcast timer
>> is programmed to 4ms.
>>
>> We can not change brodcast timer here to adjust delay caused by CPU exit
>> latency.
> Thanks for the detailed explanation. IIUC, this not only related to your
> hardware only but with how is implemented the broadcast timer, no ?
Yes.
> I think there is a similar need with the scheduler when it needs to know
> what is the idlest cpu. One thing the scheduler wants to know is the
> wakeup latency in order to choose the cpu in the shallowest state.
>
>> CPU idle governors does help to solve the latency issue. I was thinking
>> this from sub-states perspective which are not exposed to CPU idle
>> governor.
> Could you elaborate what you mean by these sub-states ? Is it related to
> the cpuidle backend drivers choosing an intermediate state different
> from the one the governor choose ?
Yes.
>> Solution for this could be to expose those states to CPU idle governor
>> but just wanted to know if we can use timers this way
> IMO, that should be studied in a larger scope including the scheduler.
>
Is this about the per-core timer switching as proposed below ...
Idle entry:
clockevents_shutdown(T1);
clockevents_set_mode(T2, ONESHOT);
clockevents_program_event(T2, next_event - latency);
Idle exit:
clockevents_shutdown(T2);
clockevents_set_mode(T1, ONESHOT);
... or about overall approach for this requirement?
>> Another requirement:
>>
>> We have 3 timers T1, T2, T3 used as wake events for 3 idle states C1,
>> C2, C3 respectively.
>>
>> Rating of T2 is better than T3. If I register T2 and T3 both as
>> broadcast timers then T3 will not be used. But ...
>> - T2 is not preserved in C3 idle state.
>> - T3 resolution is very poor (ms) and can not be used as wake event
>> for C2.
>>
>> Possible solution, register only T3 as broadcast device and use T2 as
>> per-CPU fallback timer.
>>
>>>> If I have 2 per-CPU timers T1 and T2, T1 is not preserved across idle
>>>> state and T2 is preserved. And I want to use T1 as scheduler timer.
>>>> Can I do following for idle state?
>>>>
>>>> Idle entry:
>>>> clockevents_shutdown(T1);
>>>> clockevents_set_mode(T2, ONESHOT);
>>>> clockevents_program_event(T2, next_event);
>>>>
>>>> Idle exit:
>>>> clockevents_shutdown(T2);
>>>> clockevents_set_mode(T1, ONESHOT);
> See answer to Stephen.
>
>
^ permalink raw reply
* [PATCH 1/2] USB: at91: fix the number of endpoint parameter
From: Bo Shen @ 2014-01-21 8:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140121054932.GO9558@ns203013.ovh.net>
Hi J,
On 01/21/2014 01:49 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 11:39 Mon 20 Jan , Bo Shen wrote:
>> Hi J,
>>
>> On 01/18/2014 01:20 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> On 10:59 Fri 17 Jan , Bo Shen wrote:
>>>> In sama5d3 SoC, there are 16 endpoints. As the USBA_NR_ENDPOINTS
>>>> is only 7. So, fix it for sama5d3 SoC using the udc->num_ep.
>>>>
>>>> Signed-off-by: Bo Shen <voice.shen@atmel.com>
>>>> ---
>>>>
>>>> drivers/usb/gadget/atmel_usba_udc.c | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
>>>> index 2cb52e0..7e67a81 100644
>>>> --- a/drivers/usb/gadget/atmel_usba_udc.c
>>>> +++ b/drivers/usb/gadget/atmel_usba_udc.c
>>>> @@ -1670,7 +1670,7 @@ static irqreturn_t usba_udc_irq(int irq, void *devid)
>>>> if (ep_status) {
>>>> int i;
>>>>
>>>> - for (i = 0; i < USBA_NR_ENDPOINTS; i++)
>>>> + for (i = 0; i < udc->num_ep; i++)
>>>
>>> no the limit need to specified in the driver as a checkpoint by the compatible
>>> or platform driver id
>>
>> You mean, we should not trust the data passed from dt node or
>> platform data? Or do you think we should do double confirm?
>
> no base on the driver name or the compatible you will known the MAX EP
>
> not based on the dt ep description
>
> as we do on pinctrl-at91
I am sorry, I am not fully get it after reading the code of
pinctrl-at91.c, can you give the example code in pinctrl-at91.c?
Btw, the udc->num_ep is get from the following code.
for dt
--->8---
while ((pp = of_get_next_child(np, pp)))
udc->num_ep++;
---<8---
for non-dt
--->8---
udc->num_ep = pdata->num_ep;
---8<---
> Best Regards,
> J.
>>>> if (ep_status & (1 << i)) {
>>>> if (ep_is_control(&udc->usba_ep[i]))
>>>> usba_control_irq(udc, &udc->usba_ep[i]);
>>>> --
>>>> 1.8.5.2
>>>>
>>
>> Best Regards,
>> Bo Shen
Best Regards,
Bo Shen
^ permalink raw reply
* [PATCH] arch_timer: Move delay timer to drivers clocksource
From: Prashant Gaikwad @ 2014-01-21 8:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52DD35C2.3070809@linaro.org>
On Monday 20 January 2014 08:12 PM, Daniel Lezcano wrote:
> On 01/17/2014 07:36 PM, Stephen Boyd wrote:
>> On 01/17/14 05:40, Prashant Gaikwad wrote:
>>> Another requirement:
>>>
>>> We have 3 timers T1, T2, T3 used as wake events for 3 idle states C1,
>>> C2, C3 respectively.
>>>
>>> Rating of T2 is better than T3. If I register T2 and T3 both as
>>> broadcast timers then T3 will not be used. But ...
>>> - T2 is not preserved in C3 idle state.
>>> - T3 resolution is very poor (ms) and can not be used as wake
>>> event for C2.
>>>
>>> Possible solution, register only T3 as broadcast device and use T2 as
>>> per-CPU fallback timer.
>> We have the same situation on MSM. I've been thinking about proposing we
>> allow multiple broadcast timers to exist in the system and then have the
>> clockevents_notify() caller indicate which C state is being entered. The
>> broadcast timers would need to indicate which C state they don't work in
>> though.
> IMO, there are different solutions:
>
> 1. extend the C3STOP to C1STOP, C2STOP, etc ... and pass the idle state
> to the time framework where these flags are checked against. I don't
> like this approach but it is feasible.
>
> 2. use the generic power domain. When the power domain is shutdown via
> the cpuidle backend driver, it switches the timer.
I am aware of a way to attach idle state to GenPD where we enable an
idle state when that power domain is turned off but not the other way
where domain is shutdown via CPU idle driver. How do we do it?
Even though we shutdown power domain via cpuidle driver this still has
to happen from CPU idle state, is that correct assumption? and we switch
the timer here. So we still need a way to switch timer from CPU idle
state. Hence the question remains is how to switch timers from idle state?
>
>
^ permalink raw reply
* [patch] ARM: mvebu: checking for IS_ERR() instead of NULL
From: Gregory CLEMENT @ 2014-01-21 8:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140121065216.GA31535@elgon.mountain>
On 21/01/2014 07:52, Dan Carpenter wrote:
> of_iomap() returns NULL on error, it doesn't return error pointers.
>
Hi Dan,
Thanks for your patch but I already sent this fix yesterday and Jason have
applied. See: http://thread.gmane.org/gmane.linux.ports.arm.kernel/295642
Thanks,
Gregory
> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
>
> diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
> index fe4fc1cbdfaf..b4cfbd62709d 100644
> --- a/arch/arm/mach-mvebu/mvebu-soc-id.c
> +++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
> @@ -88,7 +88,7 @@ static int __init mvebu_soc_id_init(void)
> }
>
> pci_base = of_iomap(child, 0);
> - if (IS_ERR(pci_base)) {
> + if (!pci_base) {
> pr_err("cannot map registers\n");
> ret = -ENOMEM;
> goto res_ioremap;
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] arch_timer: Move delay timer to drivers clocksource
From: Daniel Lezcano @ 2014-01-21 8:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52DE2B7B.5060708@nvidia.com>
On 01/21/2014 09:10 AM, Prashant Gaikwad wrote:
> On Monday 20 January 2014 08:11 PM, Daniel Lezcano wrote:
>> On 01/17/2014 02:40 PM, Prashant Gaikwad wrote:
>>> On Friday 17 January 2014 05:38 PM, Daniel Lezcano wrote:
>>>> On 01/17/2014 12:37 PM, Prashant Gaikwad wrote:
>>>>> On Friday 17 January 2014 03:45 PM, Daniel Lezcano wrote:
>>>>>> On 01/17/2014 11:11 AM, Prashant Gaikwad wrote:
>>>>>>> On Friday 17 January 2014 02:42 PM, Daniel Lezcano wrote:
>>>>>>>> On 01/17/2014 10:07 AM, Antti Miettinen wrote:
>>>>>>>>> Will Deacon <will.deacon@arm.com> writes:
>>>>>>>>>> Why can't you use the C3STOP feature so that the arch-timer isn't
>>>>>>>>>> used when
>>>>>>>>>> you go idle?
>>>>>>>>> That would mean falling back to broadcast timer, right? That's not
>>>>>>>>> necessarily on the local CPU so wakeups would often wake two CPUs.
>>>>>>>> You can prevent that if the hardware supports it with the
>>>>>>>> CLOCK_EVT_DYNIRQ flag on the broadcast timer.
>>>>>>> Instead of falling back on broadcast timer, is it possible to fall
>>>>>>> back
>>>>>>> on other per-CPU timer which is preserved across idle state?
>>>>>> Is it what you are looking for ?
>>>>>>
>>>>>> http://lwn.net/Articles/580568/
>>>>>>
>>>>> If I understand correctly these patches enables us to use per-CPU
>>>>> timers
>>>>> as broadcast timers. I do not want to use broadcast timer.
>>>> Why ?
>>>>
>>> For some idle states it may be required to change the timer when
>>> entering idle state to adjust the exit latency.
>>>
>>> It can be done for broadcast timer too but following scenario will
>>> not work
>>>
>>> 1. CPU1 enters in idle state:
>>> Broadcast timer next event is in 2ms, CPU latency is 50us. So
>>> we change the broadcast timer to send event after (2ms - 50us).
>>>
>>> 2. After 1ms CPU2 enters in idle state:
>>> Next event is 5ms. Broadcast timer is already programmed to <
>>> (5ms -50us) so we do nothing.
>>>
>>> 3. CPU1 exits from idle state because of timer interrupt
>>>
>>> 4. Broadcast event handler:
>>> - Timer event is handled and CPU1 is switched back to local timer.
>>> - Next CPU is CPU2 and next event for it is 4ms. So brodcast timer
>>> is programmed to 4ms.
>>>
>>> We can not change brodcast timer here to adjust delay caused by CPU exit
>>> latency.
>> Thanks for the detailed explanation. IIUC, this not only related to your
>> hardware only but with how is implemented the broadcast timer, no ?
>
> Yes.
Hmm, interesting.
>
>> I think there is a similar need with the scheduler when it needs to know
>> what is the idlest cpu. One thing the scheduler wants to know is the
>> wakeup latency in order to choose the cpu in the shallowest state.
>>
>>> CPU idle governors does help to solve the latency issue. I was thinking
>>> this from sub-states perspective which are not exposed to CPU idle
>>> governor.
>> Could you elaborate what you mean by these sub-states ? Is it related to
>> the cpuidle backend drivers choosing an intermediate state different
>> from the one the governor choose ?
>
> Yes.
Ok.
Is there any tool to measure how the timers are far from the expected
expiration time ? It would be interesting to do some measurements on
this with and without cpuidle. That would help to check the future
improvements.
>>> Solution for this could be to expose those states to CPU idle governor
>>> but just wanted to know if we can use timers this way
>> IMO, that should be studied in a larger scope including the scheduler.
>>
>
> Is this about the per-core timer switching as proposed below ...
>
> Idle entry:
> clockevents_shutdown(T1);
> clockevents_set_mode(T2, ONESHOT);
> clockevents_program_event(T2, next_event - latency);
>
> Idle exit:
> clockevents_shutdown(T2);
> clockevents_set_mode(T1, ONESHOT);
>
> ... or about overall approach for this requirement?
It is about the overall approach.
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH v2 7/7] cpufreq: exynos: remove all exynos specific cpufreq driver support
From: Lukasz Majewski @ 2014-01-21 8:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJuA9aj8+7QE_btARWn-_t5btHXOM+EiChGzjR56Sfc6wZRNZQ@mail.gmail.com>
Hi Thomas,
> Hi Lukasz,
>
> On Mon, Jan 20, 2014 at 1:38 PM, Lukasz Majewski
> <l.majewski@samsung.com> wrote:
> > Hi Thomas,
> >
> >> From: Thomas Abraham <thomas.ab@samsung.com>
> >>
> >> Exynos4210, Exynos4x12 and Exynos5250 based platforms have switched
> >> over to use cpufreq-cpu0 driver for cpufreq functionality. So the
> >> Exynos specific cpufreq drivers for these platforms can be removed.
> >>
> >> Cc: Kukjin Kim <kgene.kim@samsung.com>
> >> Cc: Jaecheol Lee <jc.lee@samsung.com>
> >> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> >> ---
> >> drivers/cpufreq/Kconfig.arm | 36 ----
> >> drivers/cpufreq/Makefile | 4 -
> >> drivers/cpufreq/exynos-cpufreq.c | 292
> >> ----------------------------------
> >> drivers/cpufreq/exynos-cpufreq.h | 91 -----------
> >> drivers/cpufreq/exynos4210-cpufreq.c | 157 ------------------
> >> drivers/cpufreq/exynos4x12-cpufreq.c | 211
> >> ------------------------ drivers/cpufreq/exynos5250-cpufreq.c |
> >> 183 --------------------- 7 files changed, 0 insertions(+), 974
> >> deletions(-) delete mode 100644 drivers/cpufreq/exynos-cpufreq.c
> >> delete mode 100644 drivers/cpufreq/exynos-cpufreq.h delete mode
> >> 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644
> >> drivers/cpufreq/exynos4x12-cpufreq.c delete mode 100644
> >> drivers/cpufreq/exynos5250-cpufreq.c
> >>
> >> diff --git a/drivers/cpufreq/Kconfig.arm
> >> b/drivers/cpufreq/Kconfig.arm index 3129749..704656d 100644
> >> --- a/drivers/cpufreq/Kconfig.arm
> >> +++ b/drivers/cpufreq/Kconfig.arm
> >> @@ -16,42 +16,6 @@ config ARM_DT_BL_CPUFREQ
> >> This enables probing via DT for Generic CPUfreq driver for
> >> ARM big.LITTLE platform. This gets frequency tables from DT.
> >>
> >> -config ARM_EXYNOS_CPUFREQ
> >> - bool
> >> -
> >> -config ARM_EXYNOS4210_CPUFREQ
> >> - bool "SAMSUNG EXYNOS4210"
> >> - depends on CPU_EXYNOS4210
> >> - default y
> >> - select ARM_EXYNOS_CPUFREQ
> >> - help
> >> - This adds the CPUFreq driver for Samsung EXYNOS4210
> >> - SoC (S5PV310 or S5PC210).
> >> -
> >> - If in doubt, say N.
> >> -
> >> -config ARM_EXYNOS4X12_CPUFREQ
> >> - bool "SAMSUNG EXYNOS4x12"
> >> - depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
> >> - default y
> >> - select ARM_EXYNOS_CPUFREQ
> >> - help
> >> - This adds the CPUFreq driver for Samsung EXYNOS4X12
> >> - SoC (EXYNOS4212 or EXYNOS4412).
> >> -
> >> - If in doubt, say N.
> >> -
> >> -config ARM_EXYNOS5250_CPUFREQ
> >> - bool "SAMSUNG EXYNOS5250"
> >> - depends on SOC_EXYNOS5250
> >> - default y
> >> - select ARM_EXYNOS_CPUFREQ
> >> - help
> >> - This adds the CPUFreq driver for Samsung EXYNOS5250
> >> - SoC.
> >> -
> >> - If in doubt, say N.
> >> -
> >> config ARM_EXYNOS5440_CPUFREQ
> >> bool "SAMSUNG EXYNOS5440"
> >> depends on SOC_EXYNOS5440
> >> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> >> index 7494565..3abfe05 100644
> >> --- a/drivers/cpufreq/Makefile
> >> +++ b/drivers/cpufreq/Makefile
> >> @@ -49,10 +49,6 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) +=
> >> arm_big_little_dt.o
> >> obj-$(CONFIG_ARCH_DAVINCI_DA850) += davinci-cpufreq.o
> >> obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
> >> -obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
> >> -obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
> >> -obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
> >> -obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
> >> obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
> >> obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
> >> obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
> >> diff --git a/drivers/cpufreq/exynos-cpufreq.c
> >> b/drivers/cpufreq/exynos-cpufreq.c deleted file mode 100644
> >> index fcd2914..0000000
> >> --- a/drivers/cpufreq/exynos-cpufreq.c
> >> +++ /dev/null
> >> @@ -1,292 +0,0 @@
> >> -/*
> >> - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> >> - * http://www.samsung.com
> >> - *
> >> - * EXYNOS - CPU frequency scaling support for EXYNOS series
> >> - *
> >> - * This program is free software; you can redistribute it and/or
> >> modify
> >> - * it under the terms of the GNU General Public License version 2
> >> as
> >> - * published by the Free Software Foundation.
> >> -*/
> >> -
> >> -#include <linux/kernel.h>
> >> -#include <linux/err.h>
> >> -#include <linux/clk.h>
> >> -#include <linux/io.h>
> >> -#include <linux/slab.h>
> >> -#include <linux/regulator/consumer.h>
> >> -#include <linux/cpufreq.h>
> >> -#include <linux/suspend.h>
> >> -#include <linux/platform_device.h>
> >> -
> >> -#include <plat/cpu.h>
> >> -
> >> -#include "exynos-cpufreq.h"
> >> -
> >> -static struct exynos_dvfs_info *exynos_info;
> >> -
> >> -static struct regulator *arm_regulator;
> >> -
> >> -static unsigned int locking_frequency;
> >> -static bool frequency_locked;
> >> -static DEFINE_MUTEX(cpufreq_lock);
> >> -
> >> -static int exynos_cpufreq_get_index(unsigned int freq)
> >> -{
> >> - struct cpufreq_frequency_table *freq_table =
> >> exynos_info->freq_table;
> >> - int index;
> >> -
> >> - for (index = 0;
> >> - freq_table[index].frequency != CPUFREQ_TABLE_END;
> >> index++)
> >> - if (freq_table[index].frequency == freq)
> >> - break;
> >> -
> >> - if (freq_table[index].frequency == CPUFREQ_TABLE_END)
> >> - return -EINVAL;
> >> -
> >> - return index;
> >> -}
> >> -
> >> -static int exynos_cpufreq_scale(unsigned int target_freq)
> >> -{
> >> - struct cpufreq_frequency_table *freq_table =
> >> exynos_info->freq_table;
> >> - unsigned int *volt_table = exynos_info->volt_table;
> >> - struct cpufreq_policy *policy = cpufreq_cpu_get(0);
> >> - unsigned int arm_volt, safe_arm_volt = 0;
> >> - unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
> >> - unsigned int old_freq;
> >> - int index, old_index;
> >> - int ret = 0;
> >> -
> >> - old_freq = policy->cur;
> >> -
> >> - /*
> >> - * The policy max have been changed so that we cannot get
> >> proper
> >> - * old_index with cpufreq_frequency_table_target(). Thus,
> >> ignore
> >> - * policy and get the index from the raw frequency table.
> >> - */
> >> - old_index = exynos_cpufreq_get_index(old_freq);
> >> - if (old_index < 0) {
> >> - ret = old_index;
> >> - goto out;
> >> - }
> >> -
> >> - index = exynos_cpufreq_get_index(target_freq);
> >> - if (index < 0) {
> >> - ret = index;
> >> - goto out;
> >> - }
> >> -
> >> - /*
> >> - * ARM clock source will be changed APLL to MPLL temporary
> >> - * To support this level, need to control regulator for
> >> - * required voltage level
> >> - */
> >> - if (exynos_info->need_apll_change != NULL) {
> >> - if (exynos_info->need_apll_change(old_index, index)
> >> &&
> >> - (freq_table[index].frequency < mpll_freq_khz) &&
> >> - (freq_table[old_index].frequency < mpll_freq_khz))
> >> - safe_arm_volt =
> >> volt_table[exynos_info->pll_safe_idx];
> >> - }
> >> - arm_volt = volt_table[index];
> >> -
> >> - /* When the new frequency is higher than current frequency */
> >> - if ((target_freq > old_freq) && !safe_arm_volt) {
> >> - /* Firstly, voltage up to increase frequency */
> >> - ret = regulator_set_voltage(arm_regulator, arm_volt,
> >> arm_volt);
> >> - if (ret) {
> >> - pr_err("%s: failed to set cpu voltage to
> >> %d\n",
> >> - __func__, arm_volt);
> >> - return ret;
> >> - }
> >> - }
> >> -
> >> - if (safe_arm_volt) {
> >> - ret = regulator_set_voltage(arm_regulator,
> >> safe_arm_volt,
> >> - safe_arm_volt);
> >> - if (ret) {
> >> - pr_err("%s: failed to set cpu voltage to
> >> %d\n",
> >> - __func__, safe_arm_volt);
> >> - return ret;
> >> - }
> >> - }
> >> -
> >> - exynos_info->set_freq(old_index, index);
> >> -
> >> - /* When the new frequency is lower than current frequency */
> >> - if ((target_freq < old_freq) ||
> >> - ((target_freq > old_freq) && safe_arm_volt)) {
> >> - /* down the voltage after frequency change */
> >> - ret = regulator_set_voltage(arm_regulator, arm_volt,
> >> - arm_volt);
> >> - if (ret) {
> >> - pr_err("%s: failed to set cpu voltage to
> >> %d\n",
> >> - __func__, arm_volt);
> >> - goto out;
> >> - }
> >> - }
> >> -
> >> -out:
> >> - cpufreq_cpu_put(policy);
> >> -
> >> - return ret;
> >> -}
> >> -
> >> -static int exynos_target(struct cpufreq_policy *policy, unsigned
> >> int index) -{
> >> - struct cpufreq_frequency_table *freq_table =
> >> exynos_info->freq_table;
> >> - int ret = 0;
> >> -
> >> - mutex_lock(&cpufreq_lock);
> >> -
> >> - if (frequency_locked)
> >> - goto out;
> >> -
> >> - ret = exynos_cpufreq_scale(freq_table[index].frequency);
> >> -
> >> -out:
> >> - mutex_unlock(&cpufreq_lock);
> >> -
> >> - return ret;
> >> -}
> >> -
> >> -#ifdef CONFIG_PM
> >> -static int exynos_cpufreq_suspend(struct cpufreq_policy *policy)
> >> -{
> >> - return 0;
> >> -}
> >> -
> >> -static int exynos_cpufreq_resume(struct cpufreq_policy *policy)
> >> -{
> >> - return 0;
> >> -}
> >> -#endif
> >> -
> >> -/**
> >> - * exynos_cpufreq_pm_notifier - block CPUFREQ's activities in
> >> suspend-resume
> >> - * context
> >> - * @notifier
> >> - * @pm_event
> >> - * @v
> >> - *
> >> - * While frequency_locked == true, target() ignores every
> >> frequency but
> >> - * locking_frequency. The locking_frequency value is the initial
> >> frequency,
> >> - * which is set by the bootloader. In order to eliminate possible
> >> - * inconsistency in clock values, we save and restore frequencies
> >> during
> >> - * suspend and resume and block CPUFREQ activities. Note that the
> >> standard
> >> - * suspend/resume cannot be used as they are too deep
> >> (syscore_ops) for
> >> - * regulator actions.
> >> - */
> >> -static int exynos_cpufreq_pm_notifier(struct notifier_block
> >> *notifier,
> >> - unsigned long pm_event, void
> >> *v) -{
> >> - int ret;
> >> -
> >> - switch (pm_event) {
> >> - case PM_SUSPEND_PREPARE:
> >> - mutex_lock(&cpufreq_lock);
> >> - frequency_locked = true;
> >> - mutex_unlock(&cpufreq_lock);
> >> -
> >> - ret = exynos_cpufreq_scale(locking_frequency);
> >> - if (ret < 0)
> >> - return NOTIFY_BAD;
> >> -
> >> - break;
> >> -
> >> - case PM_POST_SUSPEND:
> >> - mutex_lock(&cpufreq_lock);
> >> - frequency_locked = false;
> >> - mutex_unlock(&cpufreq_lock);
> >> - break;
> >> - }
> >> -
> >> - return NOTIFY_OK;
> >> -}
> >> -
> >> -static struct notifier_block exynos_cpufreq_nb = {
> >> - .notifier_call = exynos_cpufreq_pm_notifier,
> >> -};
> >> -
> >> -static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
> >> -{
> >> - policy->clk = exynos_info->cpu_clk;
> >> - return cpufreq_generic_init(policy, exynos_info->freq_table,
> >> 100000); -}
> >> -
> >> -static struct cpufreq_driver exynos_driver = {
> >> - .flags = CPUFREQ_STICKY |
> >> CPUFREQ_NEED_INITIAL_FREQ_CHECK,
> >> - .verify =
> >> cpufreq_generic_frequency_table_verify,
> >> - .target_index = exynos_target,
> >> - .get = cpufreq_generic_get,
> >> - .init = exynos_cpufreq_cpu_init,
> >> - .exit = cpufreq_generic_exit,
> >> - .name = "exynos_cpufreq",
> >> - .attr = cpufreq_generic_attr,
> >> -#ifdef CONFIG_ARM_EXYNOS_CPU_FREQ_BOOST_SW
> >> - .boost_supported = true,
> >> -#endif
> >> -#ifdef CONFIG_PM
> >> - .suspend = exynos_cpufreq_suspend,
> >> - .resume = exynos_cpufreq_resume,
> >> -#endif
> >> -};
> >> -
> >> -static int exynos_cpufreq_probe(struct platform_device *pdev)
> >> -{
> >> - int ret = -EINVAL;
> >> -
> >> - exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL);
> >> - if (!exynos_info)
> >> - return -ENOMEM;
> >> -
> >> - if (soc_is_exynos4210())
> >> - ret = exynos4210_cpufreq_init(exynos_info);
> >> - else if (soc_is_exynos4212() || soc_is_exynos4412())
> >> - ret = exynos4x12_cpufreq_init(exynos_info);
> >> - else if (soc_is_exynos5250())
> >> - ret = exynos5250_cpufreq_init(exynos_info);
> >> - else
> >> - return 0;
> >> -
> >> - if (ret)
> >> - goto err_vdd_arm;
> >> -
> >> - if (exynos_info->set_freq == NULL) {
> >> - pr_err("%s: No set_freq function (ERR)\n", __func__);
> >> - goto err_vdd_arm;
> >> - }
> >> -
> >> - arm_regulator = regulator_get(NULL, "vdd_arm");
> >> - if (IS_ERR(arm_regulator)) {
> >> - pr_err("%s: failed to get resource vdd_arm\n",
> >> __func__);
> >> - goto err_vdd_arm;
> >> - }
> >> -
> >> - locking_frequency = clk_get_rate(exynos_info->cpu_clk) /
> >> 1000; -
> >> - register_pm_notifier(&exynos_cpufreq_nb);
> >> -
> >> - if (cpufreq_register_driver(&exynos_driver)) {
> >> - pr_err("%s: failed to register cpufreq driver\n",
> >> __func__);
> >> - goto err_cpufreq;
> >> - }
> >> -
> >> - return 0;
> >> -err_cpufreq:
> >> - unregister_pm_notifier(&exynos_cpufreq_nb);
> >> -
> >> - regulator_put(arm_regulator);
> >> -err_vdd_arm:
> >> - kfree(exynos_info);
> >> - return -EINVAL;
> >> -}
> >> -
> >> -static struct platform_driver exynos_cpufreq_platdrv = {
> >> - .driver = {
> >> - .name = "exynos-cpufreq",
> >> - .owner = THIS_MODULE,
> >> - },
> >> - .probe = exynos_cpufreq_probe,
> >> -};
> >> -module_platform_driver(exynos_cpufreq_platdrv);
> >> diff --git a/drivers/cpufreq/exynos-cpufreq.h
> >> b/drivers/cpufreq/exynos-cpufreq.h deleted file mode 100644
> >> index 3ddade8..0000000
> >> --- a/drivers/cpufreq/exynos-cpufreq.h
> >> +++ /dev/null
> >> @@ -1,91 +0,0 @@
> >> -/*
> >> - * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> >> - * http://www.samsung.com
> >> - *
> >> - * EXYNOS - CPUFreq support
> >> - *
> >> - * This program is free software; you can redistribute it and/or
> >> modify
> >> - * it under the terms of the GNU General Public License version 2
> >> as
> >> - * published by the Free Software Foundation.
> >> -*/
> >> -
> >> -enum cpufreq_level_index {
> >> - L0, L1, L2, L3, L4,
> >> - L5, L6, L7, L8, L9,
> >> - L10, L11, L12, L13, L14,
> >> - L15, L16, L17, L18, L19,
> >> - L20,
> >> -};
> >> -
> >> -#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2,
> >> m, p, s) \
> >> - { \
> >> - .freq = (f) * 1000, \
> >> - .clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3)
> >> << 12 | \
> >> - (a4) << 16 | (a5) << 20 | (a6) << 24 | (a7)
> >> << 28), \
> >> - .clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \
> >> - .mps = ((m) << 16 | (p) << 8 | (s)), \
> >> - }
> >> -
> >> -struct apll_freq {
> >> - unsigned int freq;
> >> - u32 clk_div_cpu0;
> >> - u32 clk_div_cpu1;
> >> - u32 mps;
> >> -};
> >> -
> >> -struct exynos_dvfs_info {
> >> - unsigned long mpll_freq_khz;
> >> - unsigned int pll_safe_idx;
> >> - struct clk *cpu_clk;
> >> - unsigned int *volt_table;
> >> - struct cpufreq_frequency_table *freq_table;
> >> - void (*set_freq)(unsigned int, unsigned int);
> >> - bool (*need_apll_change)(unsigned int, unsigned int);
> >> -};
> >> -
> >> -#ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ
> >> -extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
> >> -#else
> >> -static inline int exynos4210_cpufreq_init(struct exynos_dvfs_info
> >> *info) -{
> >> - return -EOPNOTSUPP;
> >> -}
> >> -#endif
> >> -#ifdef CONFIG_ARM_EXYNOS4X12_CPUFREQ
> >> -extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
> >> -#else
> >> -static inline int exynos4x12_cpufreq_init(struct exynos_dvfs_info
> >> *info) -{
> >> - return -EOPNOTSUPP;
> >> -}
> >> -#endif
> >> -#ifdef CONFIG_ARM_EXYNOS5250_CPUFREQ
> >> -extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
> >> -#else
> >> -static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info
> >> *info) -{
> >> - return -EOPNOTSUPP;
> >> -}
> >> -#endif
> >> -
> >> -#include <plat/cpu.h>
> >> -#include <mach/map.h>
> >> -
> >> -#define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU +
> >> 0x14200) -#define EXYNOS4_CLKMUX_STATCPU
> >> (S5P_VA_CMU + 0x14400) -
> >> -#define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU +
> >> 0x14500) -#define EXYNOS4_CLKDIV_CPU1
> >> (S5P_VA_CMU + 0x14504) -#define
> >> EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU +
> >> 0x14600) -#define EXYNOS4_CLKDIV_STATCPU1
> >> (S5P_VA_CMU + 0x14604) - -#define
> >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) -#define
> >> EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 <<
> >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) - -#define
> >> EXYNOS5_APLL_LOCK (S5P_VA_CMU + 0x00000)
> >> -#define EXYNOS5_APLL_CON0 (S5P_VA_CMU + 0x00100) -#define
> >> EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU +
> >> 0x00400) -#define EXYNOS5_CLKDIV_CPU0 (S5P_VA_CMU
> >> + 0x00500) -#define EXYNOS5_CLKDIV_CPU1
> >> (S5P_VA_CMU + 0x00504) -#define
> >> EXYNOS5_CLKDIV_STATCPU0 (S5P_VA_CMU +
> >> 0x00600) -#define EXYNOS5_CLKDIV_STATCPU1
> >> (S5P_VA_CMU + 0x00604) diff --git
> >> a/drivers/cpufreq/exynos4210-cpufreq.c
> >> b/drivers/cpufreq/exynos4210-cpufreq.c deleted file mode 100644
> >> index 40d84c4..0000000 --- a/drivers/cpufreq/exynos4210-cpufreq.c
> >> +++ /dev/null @@ -1,157 +0,0 @@ -/*
> >> - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> >> - * http://www.samsung.com
> >> - *
> >> - * EXYNOS4210 - CPU frequency scaling support
> >> - *
> >> - * This program is free software; you can redistribute it and/or
> >> modify
> >> - * it under the terms of the GNU General Public License version 2
> >> as
> >> - * published by the Free Software Foundation.
> >> -*/
> >> -
> >> -#include <linux/module.h>
> >> -#include <linux/kernel.h>
> >> -#include <linux/err.h>
> >> -#include <linux/clk.h>
> >> -#include <linux/io.h>
> >> -#include <linux/slab.h>
> >> -#include <linux/cpufreq.h>
> >> -
> >> -#include "exynos-cpufreq.h"
> >> -
> >> -static struct clk *cpu_clk;
> >> -static struct clk *moutcore;
> >> -static struct clk *mout_mpll;
> >> -static struct clk *mout_apll;
> >> -
> >> -static unsigned int exynos4210_volt_table[] = {
> >> - 1250000, 1150000, 1050000, 975000, 950000,
> >> -};
> >> -
> >> -static struct cpufreq_frequency_table exynos4210_freq_table[] = {
> >> - {L0, 1200 * 1000},
> >> - {L1, 1000 * 1000},
> >> - {L2, 800 * 1000},
> >> - {L3, 500 * 1000},
> >> - {L4, 200 * 1000},
> >> - {0, CPUFREQ_TABLE_END},
> >> -};
> >> -
> >> -static struct apll_freq apll_freq_4210[] = {
> >> - /*
> >> - * values:
> >> - * freq
> >> - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB,
> >> PCLK_DBG, APLL, RESERVED
> >> - * clock divider for COPY, HPM, RESERVED
> >> - * PLL M, P, S
> >> - */
> >> - APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
> >> - APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
> >> - APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
> >> - APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
> >> - APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
> >> -};
> >> -
> >> -static void exynos4210_set_clkdiv(unsigned int div_index)
> >> -{
> >> - unsigned int tmp;
> >> -
> >> - /* Change Divider - CPU0 */
> >> -
> >> - tmp = apll_freq_4210[div_index].clk_div_cpu0;
> >> -
> >> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
> >> -
> >> - do {
> >> - tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
> >> - } while (tmp & 0x1111111);
> >> -
> >> - /* Change Divider - CPU1 */
> >> -
> >> - tmp = apll_freq_4210[div_index].clk_div_cpu1;
> >> -
> >> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
> >> -
> >> - do {
> >> - tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
> >> - } while (tmp & 0x11);
> >> -}
> >> -
> >> -static void exynos4210_set_apll(unsigned int index)
> >> -{
> >> - unsigned int tmp, freq = apll_freq_4210[index].freq;
> >> -
> >> - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
> >> - clk_set_parent(moutcore, mout_mpll);
> >> -
> >> - do {
> >> - tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
> >> - >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
> >> - tmp &= 0x7;
> >> - } while (tmp != 0x2);
> >> -
> >> - clk_set_rate(mout_apll, freq * 1000);
> >> -
> >> - /* MUX_CORE_SEL = APLL */
> >> - clk_set_parent(moutcore, mout_apll);
> >> -
> >> - do {
> >> - tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
> >> - tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
> >> - } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
> >> -}
> >> -
> >> -static void exynos4210_set_frequency(unsigned int old_index,
> >> - unsigned int new_index)
> >> -{
> >> - if (old_index > new_index) {
> >> - exynos4210_set_clkdiv(new_index);
> >> - exynos4210_set_apll(new_index);
> >> - } else if (old_index < new_index) {
> >> - exynos4210_set_apll(new_index);
> >> - exynos4210_set_clkdiv(new_index);
> >> - }
> >> -}
> >> -
> >> -int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
> >> -{
> >> - unsigned long rate;
> >> -
> >> - cpu_clk = clk_get(NULL, "armclk");
> >> - if (IS_ERR(cpu_clk))
> >> - return PTR_ERR(cpu_clk);
> >> -
> >> - moutcore = clk_get(NULL, "moutcore");
> >> - if (IS_ERR(moutcore))
> >> - goto err_moutcore;
> >> -
> >> - mout_mpll = clk_get(NULL, "mout_mpll");
> >> - if (IS_ERR(mout_mpll))
> >> - goto err_mout_mpll;
> >> -
> >> - rate = clk_get_rate(mout_mpll) / 1000;
> >> -
> >> - mout_apll = clk_get(NULL, "mout_apll");
> >> - if (IS_ERR(mout_apll))
> >> - goto err_mout_apll;
> >> -
> >> - info->mpll_freq_khz = rate;
> >> - /* 800Mhz */
> >> - info->pll_safe_idx = L2;
> >> - info->cpu_clk = cpu_clk;
> >> - info->volt_table = exynos4210_volt_table;
> >> - info->freq_table = exynos4210_freq_table;
> >> - info->set_freq = exynos4210_set_frequency;
> >> -
> >> - return 0;
> >> -
> >> -err_mout_apll:
> >> - clk_put(mout_mpll);
> >> -err_mout_mpll:
> >> - clk_put(moutcore);
> >> -err_moutcore:
> >> - clk_put(cpu_clk);
> >> -
> >> - pr_debug("%s: failed initialization\n", __func__);
> >> - return -EINVAL;
> >> -}
> >> diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c
> >> b/drivers/cpufreq/exynos4x12-cpufreq.c deleted file mode 100644
> >> index 7c11ace..0000000
> >> --- a/drivers/cpufreq/exynos4x12-cpufreq.c
> >> +++ /dev/null
> >> @@ -1,211 +0,0 @@
> >> -/*
> >> - * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
> >> - * http://www.samsung.com
> >> - *
> >> - * EXYNOS4X12 - CPU frequency scaling support
> >> - *
> >> - * This program is free software; you can redistribute it and/or
> >> modify
> >> - * it under the terms of the GNU General Public License version 2
> >> as
> >> - * published by the Free Software Foundation.
> >> -*/
> >> -
> >> -#include <linux/module.h>
> >> -#include <linux/kernel.h>
> >> -#include <linux/err.h>
> >> -#include <linux/clk.h>
> >> -#include <linux/io.h>
> >> -#include <linux/slab.h>
> >> -#include <linux/cpufreq.h>
> >> -
> >> -#include "exynos-cpufreq.h"
> >> -
> >> -static struct clk *cpu_clk;
> >> -static struct clk *moutcore;
> >> -static struct clk *mout_mpll;
> >> -static struct clk *mout_apll;
> >> -
> >> -static unsigned int exynos4x12_volt_table[] = {
> >> - 1350000, 1287500, 1250000, 1187500, 1137500, 1087500,
> >> 1037500,
> >> - 1000000, 987500, 975000, 950000, 925000, 900000, 900000
> >> -};
> >> -
> >> -static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
> >> - {CPUFREQ_BOOST_FREQ, 1500 * 1000},
> >
> > Here, you are removing BOOST support for Exynos4412, without any
> > code, which brings back this functionality in the new code.
>
> Sorry, I did not notice this new feature in here.
>
> >
> > I'd propose adding new property to cpus node and during
> > operating-points parsing mark the entry at the
> > cpufreq_frequency_table accordingly.
>
> Okay, would you be adding support for this or do you want me to do
> this?
I think, that BOOST support shall be preserved in the clean up patches.
Otherwise your work introduce regression.
Please add support for boost in the next version of this patch series.
>
> Thanks,
> Thomas.
>
> >
> >> - {L1, 1400 * 1000},
> >> - {L2, 1300 * 1000},
> >> - {L3, 1200 * 1000},
> >> - {L4, 1100 * 1000},
> >> - {L5, 1000 * 1000},
> >> - {L6, 900 * 1000},
> >> - {L7, 800 * 1000},
> >> - {L8, 700 * 1000},
> >> - {L9, 600 * 1000},
> >> - {L10, 500 * 1000},
> >> - {L11, 400 * 1000},
> >> - {L12, 300 * 1000},
> >> - {L13, 200 * 1000},
> >> - {0, CPUFREQ_TABLE_END},
> >> -};
> >> -
> >> -static struct apll_freq *apll_freq_4x12;
> >> -
> >> -static struct apll_freq apll_freq_4212[] = {
> >> - /*
> >> - * values:
> >> - * freq
> >> - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB,
> >> PCLK_DBG, APLL, CORE2
> >> - * clock divider for COPY, HPM, RESERVED
> >> - * PLL M, P, S
> >> - */
> >> - APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
> >> - APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
> >> - APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
> >> - APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
> >> - APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
> >> - APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
> >> - APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
> >> - APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
> >> - APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
> >> - APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
> >> - APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
> >> - APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
> >> - APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
> >> - APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
> >> -};
> >> -
> >> -static struct apll_freq apll_freq_4412[] = {
> >> - /*
> >> - * values:
> >> - * freq
> >> - * clock divider for CORE, COREM0, COREM1, PERIPH, ATB,
> >> PCLK_DBG, APLL, CORE2
> >> - * clock divider for COPY, HPM, CORES
> >> - * PLL M, P, S
> >> - */
> >> - APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
> >> - APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
> >> - APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
> >> - APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
> >> - APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
> >> - APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
> >> - APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
> >> - APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
> >> - APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
> >> - APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
> >> - APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
> >> - APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
> >> - APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
> >> - APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
> >> -};
> >> -
> >> -static void exynos4x12_set_clkdiv(unsigned int div_index)
> >> -{
> >> - unsigned int tmp;
> >> - unsigned int stat_cpu1;
> >> -
> >> - /* Change Divider - CPU0 */
> >> -
> >> - tmp = apll_freq_4x12[div_index].clk_div_cpu0;
> >> -
> >> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
> >> -
> >> - while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
> >> - cpu_relax();
> >> -
> >> - /* Change Divider - CPU1 */
> >> - tmp = apll_freq_4x12[div_index].clk_div_cpu1;
> >> -
> >> - __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
> >> - if (soc_is_exynos4212())
> >> - stat_cpu1 = 0x11;
> >> - else
> >> - stat_cpu1 = 0x111;
> >> -
> >> - while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
> >> - cpu_relax();
> >> -}
> >> -
> >> -static void exynos4x12_set_apll(unsigned int index)
> >> -{
> >> - unsigned int tmp, freq = apll_freq_4x12[index].freq;
> >> -
> >> - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
> >> - clk_set_parent(moutcore, mout_mpll);
> >> -
> >> - do {
> >> - cpu_relax();
> >> - tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
> >> - >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
> >> - tmp &= 0x7;
> >> - } while (tmp != 0x2);
> >> -
> >> - clk_set_rate(mout_apll, freq * 1000);
> >> -
> >> - /* MUX_CORE_SEL = APLL */
> >> - clk_set_parent(moutcore, mout_apll);
> >> -
> >> - do {
> >> - cpu_relax();
> >> - tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
> >> - tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
> >> - } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
> >> -}
> >> -
> >> -static void exynos4x12_set_frequency(unsigned int old_index,
> >> - unsigned int new_index)
> >> -{
> >> - if (old_index > new_index) {
> >> - exynos4x12_set_clkdiv(new_index);
> >> - exynos4x12_set_apll(new_index);
> >> - } else if (old_index < new_index) {
> >> - exynos4x12_set_apll(new_index);
> >> - exynos4x12_set_clkdiv(new_index);
> >> - }
> >> -}
> >> -
> >> -int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
> >> -{
> >> - unsigned long rate;
> >> -
> >> - cpu_clk = clk_get(NULL, "armclk");
> >> - if (IS_ERR(cpu_clk))
> >> - return PTR_ERR(cpu_clk);
> >> -
> >> - moutcore = clk_get(NULL, "moutcore");
> >> - if (IS_ERR(moutcore))
> >> - goto err_moutcore;
> >> -
> >> - mout_mpll = clk_get(NULL, "mout_mpll");
> >> - if (IS_ERR(mout_mpll))
> >> - goto err_mout_mpll;
> >> -
> >> - rate = clk_get_rate(mout_mpll) / 1000;
> >> -
> >> - mout_apll = clk_get(NULL, "mout_apll");
> >> - if (IS_ERR(mout_apll))
> >> - goto err_mout_apll;
> >> -
> >> - if (soc_is_exynos4212())
> >> - apll_freq_4x12 = apll_freq_4212;
> >> - else
> >> - apll_freq_4x12 = apll_freq_4412;
> >> -
> >> - info->mpll_freq_khz = rate;
> >> - /* 800Mhz */
> >> - info->pll_safe_idx = L7;
> >> - info->cpu_clk = cpu_clk;
> >> - info->volt_table = exynos4x12_volt_table;
> >> - info->freq_table = exynos4x12_freq_table;
> >> - info->set_freq = exynos4x12_set_frequency;
> >> -
> >> - return 0;
> >> -
> >> -err_mout_apll:
> >> - clk_put(mout_mpll);
> >> -err_mout_mpll:
> >> - clk_put(moutcore);
> >> -err_moutcore:
> >> - clk_put(cpu_clk);
> >> -
> >> - pr_debug("%s: failed initialization\n", __func__);
> >> - return -EINVAL;
> >> -}
> >> diff --git a/drivers/cpufreq/exynos5250-cpufreq.c
> >> b/drivers/cpufreq/exynos5250-cpufreq.c deleted file mode 100644
> >> index 5f90b82..0000000
> >> --- a/drivers/cpufreq/exynos5250-cpufreq.c
> >> +++ /dev/null
> >> @@ -1,183 +0,0 @@
> >> -/*
> >> - * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
> >> - * http://www.samsung.com
> >> - *
> >> - * EXYNOS5250 - CPU frequency scaling support
> >> - *
> >> - * This program is free software; you can redistribute it and/or
> >> modify
> >> - * it under the terms of the GNU General Public License version 2
> >> as
> >> - * published by the Free Software Foundation.
> >> -*/
> >> -
> >> -#include <linux/module.h>
> >> -#include <linux/kernel.h>
> >> -#include <linux/err.h>
> >> -#include <linux/clk.h>
> >> -#include <linux/io.h>
> >> -#include <linux/slab.h>
> >> -#include <linux/cpufreq.h>
> >> -
> >> -#include <mach/map.h>
> >> -
> >> -#include "exynos-cpufreq.h"
> >> -
> >> -static struct clk *cpu_clk;
> >> -static struct clk *moutcore;
> >> -static struct clk *mout_mpll;
> >> -static struct clk *mout_apll;
> >> -
> >> -static unsigned int exynos5250_volt_table[] = {
> >> - 1300000, 1250000, 1225000, 1200000, 1150000,
> >> - 1125000, 1100000, 1075000, 1050000, 1025000,
> >> - 1012500, 1000000, 975000, 950000, 937500,
> >> - 925000
> >> -};
> >> -
> >> -static struct cpufreq_frequency_table exynos5250_freq_table[] = {
> >> - {L0, 1700 * 1000},
> >> - {L1, 1600 * 1000},
> >> - {L2, 1500 * 1000},
> >> - {L3, 1400 * 1000},
> >> - {L4, 1300 * 1000},
> >> - {L5, 1200 * 1000},
> >> - {L6, 1100 * 1000},
> >> - {L7, 1000 * 1000},
> >> - {L8, 900 * 1000},
> >> - {L9, 800 * 1000},
> >> - {L10, 700 * 1000},
> >> - {L11, 600 * 1000},
> >> - {L12, 500 * 1000},
> >> - {L13, 400 * 1000},
> >> - {L14, 300 * 1000},
> >> - {L15, 200 * 1000},
> >> - {0, CPUFREQ_TABLE_END},
> >> -};
> >> -
> >> -static struct apll_freq apll_freq_5250[] = {
> >> - /*
> >> - * values:
> >> - * freq
> >> - * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG,
> >> APLL, ARM2
> >> - * clock divider for COPY, HPM, RESERVED
> >> - * PLL M, P, S
> >> - */
> >> - APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
> >> - APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
> >> - APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
> >> - APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
> >> - APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
> >> - APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
> >> - APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
> >> - APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
> >> - APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
> >> - APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
> >> - APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
> >> - APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
> >> - APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
> >> - APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
> >> - APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
> >> - APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
> >> -};
> >> -
> >> -static void set_clkdiv(unsigned int div_index)
> >> -{
> >> - unsigned int tmp;
> >> -
> >> - /* Change Divider - CPU0 */
> >> -
> >> - tmp = apll_freq_5250[div_index].clk_div_cpu0;
> >> -
> >> - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
> >> -
> >> - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
> >> - cpu_relax();
> >> -
> >> - /* Change Divider - CPU1 */
> >> - tmp = apll_freq_5250[div_index].clk_div_cpu1;
> >> -
> >> - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
> >> -
> >> - while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
> >> - cpu_relax();
> >> -}
> >> -
> >> -static void set_apll(unsigned int index)
> >> -{
> >> - unsigned int tmp;
> >> - unsigned int freq = apll_freq_5250[index].freq;
> >> -
> >> - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
> >> - clk_set_parent(moutcore, mout_mpll);
> >> -
> >> - do {
> >> - cpu_relax();
> >> - tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
> >> - tmp &= 0x7;
> >> - } while (tmp != 0x2);
> >> -
> >> - clk_set_rate(mout_apll, freq * 1000);
> >> -
> >> - /* MUX_CORE_SEL = APLL */
> >> - clk_set_parent(moutcore, mout_apll);
> >> -
> >> - do {
> >> - cpu_relax();
> >> - tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
> >> - tmp &= (0x7 << 16);
> >> - } while (tmp != (0x1 << 16));
> >> -}
> >> -
> >> -static void exynos5250_set_frequency(unsigned int old_index,
> >> - unsigned int new_index)
> >> -{
> >> - if (old_index > new_index) {
> >> - set_clkdiv(new_index);
> >> - set_apll(new_index);
> >> - } else if (old_index < new_index) {
> >> - set_apll(new_index);
> >> - set_clkdiv(new_index);
> >> - }
> >> -}
> >> -
> >> -int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
> >> -{
> >> - unsigned long rate;
> >> -
> >> - cpu_clk = clk_get(NULL, "armclk");
> >> - if (IS_ERR(cpu_clk))
> >> - return PTR_ERR(cpu_clk);
> >> -
> >> - moutcore = clk_get(NULL, "mout_cpu");
> >> - if (IS_ERR(moutcore))
> >> - goto err_moutcore;
> >> -
> >> - mout_mpll = clk_get(NULL, "mout_mpll");
> >> - if (IS_ERR(mout_mpll))
> >> - goto err_mout_mpll;
> >> -
> >> - rate = clk_get_rate(mout_mpll) / 1000;
> >> -
> >> - mout_apll = clk_get(NULL, "mout_apll");
> >> - if (IS_ERR(mout_apll))
> >> - goto err_mout_apll;
> >> -
> >> - info->mpll_freq_khz = rate;
> >> - /* 800Mhz */
> >> - info->pll_safe_idx = L9;
> >> - info->cpu_clk = cpu_clk;
> >> - info->volt_table = exynos5250_volt_table;
> >> - info->freq_table = exynos5250_freq_table;
> >> - info->set_freq = exynos5250_set_frequency;
> >> -
> >> - return 0;
> >> -
> >> -err_mout_apll:
> >> - clk_put(mout_mpll);
> >> -err_mout_mpll:
> >> - clk_put(moutcore);
> >> -err_moutcore:
> >> - clk_put(cpu_clk);
> >> -
> >> - pr_err("%s: failed initialization\n", __func__);
> >> - return -EINVAL;
> >> -}
> >
> >
> >
> > --
> > Best regards,
> >
> > Lukasz Majewski
> >
> > Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
--
Best regards,
Lukasz Majewski
Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply
* [PATCH v2] dma: imx-sdma: clarify firmare not found warning
From: Lothar Waßmann @ 2014-01-21 8:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140121070649.GT16215@pengutronix.de>
Hi,
Sascha Hauer wrote:
> Hi Lothar,
>
> On Mon, Jan 20, 2014 at 12:36:27PM +0100, Lothar Wa?mann wrote:
> > Hi,
> >
> > Lothar Wa?mann wrote:
> > > Hi,
> > >
> > erroneously pressed the 'Send' button...
> >
> > > Sascha Hauer wrote:
> > > > When a firmware cannot be found for the SDMA engine then we can
> > > > continue with the inernal ROM firmware.
> > > >
> > > > The meaning of this message is frequently asked for, so make clear
> > > > that the driver still works with the internal ROM firmware and reduce
> > > > the loglevel from err to info.
> > > >
> > In case user space firmware loading support (CONFIG_FW_LOADER) is
> > enabled, this message may still be inadequate, since the firmware may
> > very well be loaded lateron.
>
> Then at least until the RAM firmware is loaded the message is still adequate,
> no? We could add an addional message when the firmware is loaded if you
> like.
>
There is already a message printed upon successful firmware load:
|imx-sdma 63fb0000.sdma: loaded firmware 1.1
But one message saying 'firmware load failed' and another saying the
opposite is a bit confusing. There actually is also a message saying
'firmware not found' when the timeout expires without any firmware
being loaded. Thus at least in case CONFIG_FW_LOADER is enabled the
message 'Direct firmware load failed' could be omitted.
Lothar Wa?mann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________
^ permalink raw reply
* Question: xilinx_zynq_defconfig
From: Masahiro Yamada @ 2014-01-21 8:34 UTC (permalink / raw)
To: linux-arm-kernel
Hello Michal,
I have a Zynq ZC706 board.
I have a simple question about Zynq support.
There exist device tree sources for Zynq in the mainline of Kernel,
whereas xilinx_zynq_defconfig is missing.
(I know it is maintained in a Xilinx repository.)
Why have the defconfig files not been merged yet?
Best Regards
Masahiro Yamada
^ permalink raw reply
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