* [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445
From: Michal Simek @ 2014-01-23 8:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201401171804.30572.arnd@arndb.de>
On 01/17/2014 06:04 PM, Arnd Bergmann wrote:
> On Thursday 16 January 2014, Mark Brown wrote:
>> On Thu, Jan 16, 2014 at 12:19:00PM +0100, Arnd Bergmann wrote:
>>
>>> 1. Other platforms also require the syscon driver to be active before
>>> the regular device driver probing starts. Michal Simek has the same
>>> issue in the zynq clock driver that you have for SMP initialization.
>>> We have talked about this with Mark Brown already, and I think we will
>>> find a solution for this in the end, but it's not as straightforward
>>> as I first hoped. We can probably use help in this area.
>>
>> I thought the solution with deferring registration of the resource for
>> dev_get_regmap() until a proper device materialised seemed simple and
>> enough, did you folks run into any problems with that? I had assumed a
>> patch was likely to materialise so wasn't worrying about it myself.
>
> I'm still hoping that Michal will do that patch.
And what was the resolution/recommendation how to do it?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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^ permalink raw reply
* [PATCH v2 RESEND] vt8500: pinctrl: Change devicetree data parsing
From: Tony Prisk @ 2014-01-23 8:57 UTC (permalink / raw)
To: linux-arm-kernel
Due to an assumption in the VT8500 pinctrl driver, the value passed
from devicetree for 'wm,pull' was not explicitly translated before
being passed to pinconf.
Since v3.10, changes to 'enum pin_config_param', PIN_CONFIG_BIAS_PULL_(UP/DOWN)
no longer map 1-to-1 with the expected values in devicetree.
This patch adds a small translation between the devicetree values (0..2)
and the enum pin_config_param equivalent values.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
v2:
Minor change in commit message to indicate time since problem occurred.
Change assigned variable to configs[0] rather than reassigning to pull.
Add a default case to the switch to prevent static checker errors.
v2 resend:
Correct Linus' email address
drivers/pinctrl/vt8500/pinctrl-wmt.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c
index 39aec08..25ab2ee 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wmt.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c
@@ -276,7 +276,20 @@ static int wmt_pctl_dt_node_to_map_pull(struct wmt_pinctrl_data *data,
if (!configs)
return -ENOMEM;
- configs[0] = pull;
+ switch (pull) {
+ case 0:
+ configs[0] = PIN_CONFIG_BIAS_DISABLE;
+ break;
+ case 1:
+ configs[0] = PIN_CONFIG_BIAS_PULL_DOWN;
+ break;
+ case 2:
+ configs[0] = PIN_CONFIG_BIAS_PULL_UP;
+ break;
+ default:
+ configs[0] = PIN_CONFIG_BIAS_DISABLE;
+ dev_err(data->dev, "invalid pull state %d - disabling\n", pull);
+ }
map->type = PIN_MAP_TYPE_CONFIGS_PIN;
map->data.configs.group_or_pin = data->groups[group];
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2] vt8500: pinctrl: Change devicetree data parsing
From: Tony Prisk @ 2014-01-23 8:55 UTC (permalink / raw)
To: linux-arm-kernel
Due to an assumption in the VT8500 pinctrl driver, the value passed
from devicetree for 'wm,pull' was not explicitly translated before
being passed to pinconf.
Since v3.10, changes to 'enum pin_config_param', PIN_CONFIG_BIAS_PULL_(UP/DOWN)
no longer map 1-to-1 with the expected values in devicetree.
This patch adds a small translation between the devicetree values (0..2)
and the enum pin_config_param equivalent values.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
v2:
Minor change in commit message to indicate time since problem occurred.
Change assigned variable to configs[0] rather than reassigning to pull.
Add a default case to the switch to prevent static checker errors.
drivers/pinctrl/vt8500/pinctrl-wmt.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c
index 39aec08..25ab2ee 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wmt.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c
@@ -276,7 +276,20 @@ static int wmt_pctl_dt_node_to_map_pull(struct wmt_pinctrl_data *data,
if (!configs)
return -ENOMEM;
- configs[0] = pull;
+ switch (pull) {
+ case 0:
+ configs[0] = PIN_CONFIG_BIAS_DISABLE;
+ break;
+ case 1:
+ configs[0] = PIN_CONFIG_BIAS_PULL_DOWN;
+ break;
+ case 2:
+ configs[0] = PIN_CONFIG_BIAS_PULL_UP;
+ break;
+ default:
+ configs[0] = PIN_CONFIG_BIAS_DISABLE;
+ dev_err(data->dev, "invalid pull state %d - disabling\n", pull);
+ }
map->type = PIN_MAP_TYPE_CONFIGS_PIN;
map->data.configs.group_or_pin = data->groups[group];
--
1.7.9.5
^ permalink raw reply related
* [PATCH] vt8500: pinctrl: Change devicetree data parsing
From: Linus Walleij @ 2014-01-23 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390458701-30238-1-git-send-email-linux@prisktech.co.nz>
On Thu, Jan 23, 2014 at 7:31 AM, Tony Prisk <linux@prisktech.co.nz> wrote:
> Due to an assumption in the VT8500 pinctrl driver, the value passed
> from devicetree for 'wm,pull' was not explicitly translated before
> being passed to pinconf.
>
> With changes to 'enum pin_config_param', PIN_CONFIG_BIAS_PULL_(UP/DOWN)
> no longer map 1-to-1 with the expected values in devicetree.
>
> This patch adds a small translation between the devicetree values (0..2)
> and the enum pin_config_param equivalent values.
>
> Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Isn't this a regression fix for stable?
> + switch (pull) {
> + case 0:
> + pull = PIN_CONFIG_BIAS_DISABLE;
> + break;
> + case 1:
> + pull = PIN_CONFIG_BIAS_PULL_DOWN;
> + break;
> + case 2:
> + pull = PIN_CONFIG_BIAS_PULL_UP;
> + break;
> + }
> configs[0] = pull;
1. You're not adding a default: clause (I bet the static checkers will
warn about this!)
2. Please conjure a different variable name for the thing that
actually gets set in the config so we see we are mapping one
thing to another and not just altering an existing variable.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 2/2] clocksource: Make clocksource register functions void
From: Daniel Lezcano @ 2014-01-23 8:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390461166-36440-1-git-send-email-wangyijing@huawei.com>
On 01/23/2014 08:12 AM, Yijing Wang wrote:
> Currently, clocksource_register() and __clocksource_register_scale()
> functions always return 0, it's pointless, make functions void.
> And remove the dead code that check the clocksource_register_hz()
> return value.
>
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Well, do we really want to change all these files to not take care of a
return value ? What about is we have to check it again later ?
I would recommend to investigate __clocksource_register_scale and the
underneath functions if there is not an error to be returned in the call
stack somewhere which is ignored today.
The same applies for clocksource_register.
Thanks
-- Daniel
> ---
> arch/arm/mach-davinci/time.c | 5 ++---
> arch/arm/mach-msm/timer.c | 4 +---
> arch/arm/mach-omap2/timer.c | 8 +++-----
> arch/avr32/kernel/time.c | 4 +---
> arch/blackfin/kernel/time-ts.c | 6 ++----
> arch/microblaze/kernel/timer.c | 3 +--
> arch/mips/jz4740/time.c | 6 +-----
> arch/mips/loongson/common/cs5536/cs5536_mfgpt.c | 3 ++-
> arch/openrisc/kernel/time.c | 3 +--
> arch/powerpc/kernel/time.c | 6 +-----
> arch/um/kernel/time.c | 6 +-----
> arch/x86/platform/uv/uv_time.c | 14 ++++++--------
> drivers/clocksource/acpi_pm.c | 3 ++-
> drivers/clocksource/cadence_ttc_timer.c | 6 +-----
> drivers/clocksource/exynos_mct.c | 4 +---
> drivers/clocksource/i8253.c | 3 ++-
> drivers/clocksource/mmio.c | 3 ++-
> drivers/clocksource/samsung_pwm_timer.c | 5 +----
> drivers/clocksource/scx200_hrt.c | 3 ++-
> drivers/clocksource/tcb_clksrc.c | 8 +-------
> drivers/clocksource/timer-marco.c | 2 +-
> drivers/clocksource/timer-prima2.c | 2 +-
> drivers/clocksource/vt8500_timer.c | 4 +---
> include/linux/clocksource.h | 8 ++++----
> kernel/time/clocksource.c | 6 ++----
> kernel/time/jiffies.c | 3 ++-
> 26 files changed, 45 insertions(+), 83 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
> index 56c6eb5..9536f85 100644
> --- a/arch/arm/mach-davinci/time.c
> +++ b/arch/arm/mach-davinci/time.c
> @@ -387,9 +387,8 @@ void __init davinci_timer_init(void)
>
> /* setup clocksource */
> clocksource_davinci.name = id_to_name[clocksource_id];
> - if (clocksource_register_hz(&clocksource_davinci,
> - davinci_clock_tick_rate))
> - printk(err, clocksource_davinci.name);
> + clocksource_register_hz(&clocksource_davinci,
> + davinci_clock_tick_rate);
>
> setup_sched_clock(davinci_read_sched_clock, 32,
> davinci_clock_tick_rate);
> diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
> index 1e9c338..c96e034 100644
> --- a/arch/arm/mach-msm/timer.c
> +++ b/arch/arm/mach-msm/timer.c
> @@ -226,9 +226,7 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
>
> err:
> writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
> - res = clocksource_register_hz(cs, dgt_hz);
> - if (res)
> - pr_err("clocksource_register failed\n");
> + clocksource_register_hz(cs, dgt_hz);
> setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
> }
>
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 3ca81e0..beaf7c7 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -473,11 +473,9 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
> OMAP_TIMER_NONPOSTED);
> setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
>
> - if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
> - pr_err("Could not register clocksource %s\n",
> - clocksource_gpt.name);
> - else
> - pr_info("OMAP clocksource: %s at %lu Hz\n",
> + clocksource_register_hz(&clocksource_gpt, clksrc.rate);
> +
> + pr_info("OMAP clocksource: %s at %lu Hz\n",
> clocksource_gpt.name, clksrc.rate);
> }
>
> diff --git a/arch/avr32/kernel/time.c b/arch/avr32/kernel/time.c
> index d0f771b..51b4a66 100644
> --- a/arch/avr32/kernel/time.c
> +++ b/arch/avr32/kernel/time.c
> @@ -134,9 +134,7 @@ void __init time_init(void)
>
> /* figure rate for counter */
> counter_hz = clk_get_rate(boot_cpu_data.clk);
> - ret = clocksource_register_hz(&counter, counter_hz);
> - if (ret)
> - pr_debug("timer: could not register clocksource: %d\n", ret);
> + clocksource_register_hz(&counter, counter_hz);
>
> /* setup COMPARE clockevent */
> comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
> diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
> index cb0a484..df3bb08 100644
> --- a/arch/blackfin/kernel/time-ts.c
> +++ b/arch/blackfin/kernel/time-ts.c
> @@ -51,8 +51,7 @@ static inline unsigned long long bfin_cs_cycles_sched_clock(void)
>
> static int __init bfin_cs_cycles_init(void)
> {
> - if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
> - panic("failed to register clocksource");
> + clocksource_register_hz(&bfin_cs_cycles, get_cclk());
>
> return 0;
> }
> @@ -103,8 +102,7 @@ static int __init bfin_cs_gptimer0_init(void)
> {
> setup_gptimer0();
>
> - if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
> - panic("failed to register clocksource");
> + clocksource_register_hz(&bfin_cs_gptimer0, get_sclk());
>
> return 0;
> }
> diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
> index 3e39b10..6a2417e 100644
> --- a/arch/microblaze/kernel/timer.c
> +++ b/arch/microblaze/kernel/timer.c
> @@ -208,8 +208,7 @@ static struct clocksource clocksource_microblaze = {
>
> static int __init xilinx_clocksource_init(void)
> {
> - if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq))
> - panic("failed to register clocksource");
> + clocksource_register_hz(&clocksource_microblaze, timer_clock_freq);
>
> /* stop timer1 */
> out_be32(timer_baseaddr + TCSR1,
> diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
> index 5e430ce..041cdff 100644
> --- a/arch/mips/jz4740/time.c
> +++ b/arch/mips/jz4740/time.c
> @@ -105,7 +105,6 @@ static struct irqaction timer_irqaction = {
>
> void __init plat_time_init(void)
> {
> - int ret;
> uint32_t clk_rate;
> uint16_t ctrl;
>
> @@ -121,10 +120,7 @@ void __init plat_time_init(void)
>
> clockevents_register_device(&jz4740_clockevent);
>
> - ret = clocksource_register_hz(&jz4740_clocksource, clk_rate);
> -
> - if (ret)
> - printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
> + clocksource_register_hz(&jz4740_clocksource, clk_rate);
>
> setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
>
> diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
> index c639b9d..9fa6d99 100644
> --- a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
> +++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
> @@ -208,7 +208,8 @@ int __init init_mfgpt_clocksource(void)
> if (num_possible_cpus() > 1) /* MFGPT does not scale! */
> return 0;
>
> - return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
> + clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
> + return 0;
> }
>
> arch_initcall(init_mfgpt_clocksource);
> diff --git a/arch/openrisc/kernel/time.c b/arch/openrisc/kernel/time.c
> index 7c52e94..3f789aa 100644
> --- a/arch/openrisc/kernel/time.c
> +++ b/arch/openrisc/kernel/time.c
> @@ -156,8 +156,7 @@ static struct clocksource openrisc_timer = {
>
> static int __init openrisc_timer_init(void)
> {
> - if (clocksource_register_hz(&openrisc_timer, cpuinfo.clock_frequency))
> - panic("failed to register clocksource");
> + clocksource_register_hz(&openrisc_timer, cpuinfo.clock_frequency);
>
> /* Enable the incrementer: 'continuous' mode with interrupt disabled */
> mtspr(SPR_TTMR, SPR_TTMR_CR);
> diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
> index b3b1441..27c0627 100644
> --- a/arch/powerpc/kernel/time.c
> +++ b/arch/powerpc/kernel/time.c
> @@ -788,11 +788,7 @@ static void __init clocksource_init(void)
> else
> clock = &clocksource_timebase;
>
> - if (clocksource_register_hz(clock, tb_ticks_per_sec)) {
> - printk(KERN_ERR "clocksource: %s is already registered\n",
> - clock->name);
> - return;
> - }
> + clocksource_register_hz(clock, tb_ticks_per_sec);
>
> printk(KERN_INFO "clocksource: %s mult[%x] shift[%d] registered\n",
> clock->name, clock->mult, clock->shift);
> diff --git a/arch/um/kernel/time.c b/arch/um/kernel/time.c
> index 117568d..2034b58 100644
> --- a/arch/um/kernel/time.c
> +++ b/arch/um/kernel/time.c
> @@ -92,11 +92,7 @@ static void __init setup_itimer(void)
> clockevent_delta2ns(60 * HZ, &itimer_clockevent);
> itimer_clockevent.min_delta_ns =
> clockevent_delta2ns(1, &itimer_clockevent);
> - err = clocksource_register_hz(&itimer_clocksource, USEC_PER_SEC);
> - if (err) {
> - printk(KERN_ERR "clocksource_register_hz returned %d\n", err);
> - return;
> - }
> + clocksource_register_hz(&itimer_clocksource, USEC_PER_SEC);
> clockevents_register_device(&itimer_clockevent);
> }
>
> diff --git a/arch/x86/platform/uv/uv_time.c b/arch/x86/platform/uv/uv_time.c
> index 5c86786..b963774 100644
> --- a/arch/x86/platform/uv/uv_time.c
> +++ b/arch/x86/platform/uv/uv_time.c
> @@ -379,15 +379,13 @@ static __init int uv_rtc_setup_clock(void)
> if (!is_uv_system())
> return -ENODEV;
>
> - rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
> - if (rc)
> - printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
> - else
> - printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
> - sn_rtc_cycles_per_second/(unsigned long)1E6);
> + clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
> +
> + pr_info("UV RTC clocksource registered freq %lu MHz\n",
> + sn_rtc_cycles_per_second/(unsigned long)1E6);
>
> - if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback)
> - return rc;
> + if (!uv_rtc_evt_enable || x86_platform_ipi_callback)
> + return 0;
>
> /* Setup and register clockevents */
> rc = uv_rtc_allocate_timers();
> diff --git a/drivers/clocksource/acpi_pm.c b/drivers/clocksource/acpi_pm.c
> index 6eab889..ab1dc63 100644
> --- a/drivers/clocksource/acpi_pm.c
> +++ b/drivers/clocksource/acpi_pm.c
> @@ -218,8 +218,9 @@ static int __init init_acpi_pm_clocksource(void)
> return -ENODEV;
> }
>
> - return clocksource_register_hz(&clocksource_acpi_pm,
> + clocksource_register_hz(&clocksource_acpi_pm,
> PMTMR_TICKS_PER_SEC);
> + return 0;
> }
>
> /* We use fs_initcall because we want the PCI fixups to have run
> diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
> index 63f176d..b9b56ed 100644
> --- a/drivers/clocksource/cadence_ttc_timer.c
> +++ b/drivers/clocksource/cadence_ttc_timer.c
> @@ -301,11 +301,7 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
> __raw_writel(CNT_CNTRL_RESET,
> ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
>
> - err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
> - if (WARN_ON(err)) {
> - kfree(ttccs);
> - return;
> - }
> + clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
>
> ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
> sched_clock_register(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
> diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
> index 62b0de6..98649c7 100644
> --- a/drivers/clocksource/exynos_mct.c
> +++ b/drivers/clocksource/exynos_mct.c
> @@ -193,9 +193,7 @@ struct clocksource mct_frc = {
> static void __init exynos4_clocksource_init(void)
> {
> exynos4_mct_frc_start(0, 0);
> -
> - if (clocksource_register_hz(&mct_frc, clk_rate))
> - panic("%s: can't register clocksource\n", mct_frc.name);
> + clocksource_register_hz(&mct_frc, clk_rate);
> }
>
> static void exynos4_mct_comp0_stop(void)
> diff --git a/drivers/clocksource/i8253.c b/drivers/clocksource/i8253.c
> index 14ee3ef..9c45f0a 100644
> --- a/drivers/clocksource/i8253.c
> +++ b/drivers/clocksource/i8253.c
> @@ -95,7 +95,8 @@ static struct clocksource i8253_cs = {
>
> int __init clocksource_i8253_init(void)
> {
> - return clocksource_register_hz(&i8253_cs, PIT_TICK_RATE);
> + clocksource_register_hz(&i8253_cs, PIT_TICK_RATE);
> + return 0;
> }
> #endif
>
> diff --git a/drivers/clocksource/mmio.c b/drivers/clocksource/mmio.c
> index c0e2512..6e0b530 100644
> --- a/drivers/clocksource/mmio.c
> +++ b/drivers/clocksource/mmio.c
> @@ -69,5 +69,6 @@ int __init clocksource_mmio_init(void __iomem *base, const char *name,
> cs->clksrc.mask = CLOCKSOURCE_MASK(bits);
> cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
>
> - return clocksource_register_hz(&cs->clksrc, hz);
> + clocksource_register_hz(&cs->clksrc, hz);
> + return 0;
> }
> diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c
> index 5645cfc..c59292f 100644
> --- a/drivers/clocksource/samsung_pwm_timer.c
> +++ b/drivers/clocksource/samsung_pwm_timer.c
> @@ -340,7 +340,6 @@ static void __init samsung_clocksource_init(void)
> {
> unsigned long pclk;
> unsigned long clock_rate;
> - int ret;
>
> pclk = clk_get_rate(pwm.timerclk);
>
> @@ -361,9 +360,7 @@ static void __init samsung_clocksource_init(void)
> pwm.variant.bits, clock_rate);
>
> samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
> - ret = clocksource_register_hz(&samsung_clocksource, clock_rate);
> - if (ret)
> - panic("samsung_clocksource_timer: can't register clocksource\n");
> + clocksource_register_hz(&samsung_clocksource, clock_rate);
> }
>
> static void __init samsung_timer_resources(void)
> diff --git a/drivers/clocksource/scx200_hrt.c b/drivers/clocksource/scx200_hrt.c
> index 64f9e82..57bdc04 100644
> --- a/drivers/clocksource/scx200_hrt.c
> +++ b/drivers/clocksource/scx200_hrt.c
> @@ -83,7 +83,8 @@ static int __init init_hrt_clocksource(void)
>
> pr_info("enabling scx200 high-res timer (%s MHz +%d ppm)\n", mhz27 ? "27":"1", ppm);
>
> - return clocksource_register_hz(&cs_hrt, freq);
> + clocksource_register_hz(&cs_hrt, freq);
> + return 0;
> }
>
> module_init(init_hrt_clocksource);
> diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
> index 00fdd11..805245d 100644
> --- a/drivers/clocksource/tcb_clksrc.c
> +++ b/drivers/clocksource/tcb_clksrc.c
> @@ -340,9 +340,7 @@ static int __init tcb_clksrc_init(void)
> }
>
> /* and away we go! */
> - ret = clocksource_register_hz(&clksrc, divided_rate);
> - if (ret)
> - goto err_disable_t1;
> + clocksource_register_hz(&clksrc, divided_rate);
>
> /* channel 2: periodic and oneshot timer support */
> ret = setup_clkevents(tc, clk32k_divisor_idx);
> @@ -354,10 +352,6 @@ static int __init tcb_clksrc_init(void)
> err_unregister_clksrc:
> clocksource_unregister(&clksrc);
>
> -err_disable_t1:
> - if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
> - clk_disable_unprepare(tc->clk[1]);
> -
> err_disable_t0:
> clk_disable_unprepare(t0_clk);
>
> diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
> index 09a17d9..ae78ce0 100644
> --- a/drivers/clocksource/timer-marco.c
> +++ b/drivers/clocksource/timer-marco.c
> @@ -283,7 +283,7 @@ static void __init sirfsoc_marco_timer_init(void)
> /* Clear all interrupts */
> writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
>
> - BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
> + clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE);
>
> sirfsoc_clockevent_init();
> }
> diff --git a/drivers/clocksource/timer-prima2.c b/drivers/clocksource/timer-prima2.c
> index 8a492d3..c9cc307 100644
> --- a/drivers/clocksource/timer-prima2.c
> +++ b/drivers/clocksource/timer-prima2.c
> @@ -204,7 +204,7 @@ static void __init sirfsoc_prima2_timer_init(struct device_node *np)
> writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
> writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
>
> - BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
> + clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE);
>
> sched_clock_register(sirfsoc_read_sched_clock, 64, CLOCK_TICK_RATE);
>
> diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/vt8500_timer.c
> index 1098ed3..13f5fa4 100644
> --- a/drivers/clocksource/vt8500_timer.c
> +++ b/drivers/clocksource/vt8500_timer.c
> @@ -150,9 +150,7 @@ static void __init vt8500_timer_init(struct device_node *np)
> writel(0xf, regbase + TIMER_STATUS_VAL);
> writel(~0, regbase + TIMER_MATCH_VAL);
>
> - if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
> - pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
> - __func__, clocksource.name);
> + clocksource_register_hz(&clocksource, VT8500_TIMER_HZ);
>
> clockevent.cpumask = cpumask_of(0);
>
> diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
> index 67301a4..5a17c5e 100644
> --- a/include/linux/clocksource.h
> +++ b/include/linux/clocksource.h
> @@ -282,7 +282,7 @@ static inline s64 clocksource_cyc2ns(cycle_t cycles, u32 mult, u32 shift)
> }
>
>
> -extern int clocksource_register(struct clocksource*);
> +extern void clocksource_register(struct clocksource *);
> extern int clocksource_unregister(struct clocksource*);
> extern void clocksource_touch_watchdog(void);
> extern struct clocksource* clocksource_get_next(void);
> @@ -301,17 +301,17 @@ clocks_calc_mult_shift(u32 *mult, u32 *shift, u32 from, u32 to, u32 minsec);
> * Don't call __clocksource_register_scale directly, use
> * clocksource_register_hz/khz
> */
> -extern int
> +extern void
> __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq);
> extern void
> __clocksource_updatefreq_scale(struct clocksource *cs, u32 scale, u32 freq);
>
> -static inline int clocksource_register_hz(struct clocksource *cs, u32 hz)
> +static inline void clocksource_register_hz(struct clocksource *cs, u32 hz)
> {
> return __clocksource_register_scale(cs, 1, hz);
> }
>
> -static inline int clocksource_register_khz(struct clocksource *cs, u32 khz)
> +static inline void clocksource_register_khz(struct clocksource *cs, u32 khz)
> {
> return __clocksource_register_scale(cs, 1000, khz);
> }
> diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c
> index 9951575..686ff72 100644
> --- a/kernel/time/clocksource.c
> +++ b/kernel/time/clocksource.c
> @@ -782,7 +782,7 @@ EXPORT_SYMBOL_GPL(__clocksource_updatefreq_scale);
> * This *SHOULD NOT* be called directly! Please use the
> * clocksource_register_hz() or clocksource_register_khz helper functions.
> */
> -int __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq)
> +void __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq)
> {
>
> /* Initialize mult/shift and max_idle_ns */
> @@ -794,7 +794,6 @@ int __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq)
> clocksource_enqueue_watchdog(cs);
> clocksource_select();
> mutex_unlock(&clocksource_mutex);
> - return 0;
> }
> EXPORT_SYMBOL_GPL(__clocksource_register_scale);
>
> @@ -804,7 +803,7 @@ EXPORT_SYMBOL_GPL(__clocksource_register_scale);
> * @cs: clocksource to be registered
> *
> */
> -int clocksource_register(struct clocksource *cs)
> +void clocksource_register(struct clocksource *cs)
> {
> /* calculate max adjustment for given mult/shift */
> cs->maxadj = clocksource_max_adjustment(cs);
> @@ -820,7 +819,6 @@ int clocksource_register(struct clocksource *cs)
> clocksource_enqueue_watchdog(cs);
> clocksource_select();
> mutex_unlock(&clocksource_mutex);
> - return 0;
> }
> EXPORT_SYMBOL(clocksource_register);
>
> diff --git a/kernel/time/jiffies.c b/kernel/time/jiffies.c
> index 7a925ba..ae4c534 100644
> --- a/kernel/time/jiffies.c
> +++ b/kernel/time/jiffies.c
> @@ -88,7 +88,8 @@ EXPORT_SYMBOL(jiffies);
>
> static int __init init_jiffies_clocksource(void)
> {
> - return clocksource_register(&clocksource_jiffies);
> + clocksource_register(&clocksource_jiffies);
> + return 0;
> }
>
> core_initcall(init_jiffies_clocksource);
>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH] pinctrl: Rename Broadcom Capri pinctrl driver
From: Linus Walleij @ 2014-01-23 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdZ+3MC8XpfD-vumvq3yQACzFn89DQjWQeXbdBK+9JmfLQ@mail.gmail.com>
On Thu, Jan 23, 2014 at 9:17 AM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Tue, Jan 21, 2014 at 11:38 PM, Sherman Yin <syin@broadcom.com> wrote:
>
>> To be consistent with other Broadcom drivers, the Broadcom Capri pinctrl
>> driver and its related CONFIG option are renamed to bcm281xx.
>>
>> Devicetree compatible string and binding documentation use
>> "brcm,bcm11351-pinctrl" to match the machine binding here:
>> Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
>>
>> This driver supports pinctrl on BCM11130, BCM11140, BCM11351, BCM28145
>> and BCM28155 SoCs.
>>
>> Signed-off-by: Sherman Yin <syin@broadcom.com>
>> Reviewed-by: Matt Porter <mporter@linaro.org>
>
> Patch applied for fixes.
No wait. I took the patch out.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
This driver is already causing a messy conflict situation in ARM SoC.
I don't want to escalate their problem.
Either you merge this through ARM SoC or split off the arch/arm/*
changes into a separate patch for ARM SoC.
Yours,
Linus Walleij
^ permalink raw reply
* [linux-sunxi] [PATCH v5 13/14] ARM: sun4i: dts: Add ahci / sata support
From: Chen-Yu Tsai @ 2014-01-23 8:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390417489-5354-14-git-send-email-hdegoede@redhat.com>
Hi,
On Thu, Jan 23, 2014 at 3:04 AM, Hans de Goede <hdegoede@redhat.com> wrote:
> From: Oliver Schinagl <oliver@schinagl.nl>
>
> This patch adds sunxi sata support to A10 boards that have such a connector.
> Some boards also feature a regulator via a GPIO and support for this is also
> added.
>
> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> arch/arm/boot/dts/sun4i-a10-a1000.dts | 4 ++++
> arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 6 +++++
> arch/arm/boot/dts/sun4i-a10.dtsi | 8 +++++++
> arch/arm/boot/dts/sunxi-ahci-reg.dtsi | 38 ++++++++++++++++++++++++++++++
> 4 files changed, 56 insertions(+)
> create mode 100644 arch/arm/boot/dts/sunxi-ahci-reg.dtsi
>
> diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
> index aef8207..3fb7305 100644
> --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
> @@ -48,6 +48,10 @@
> status = "okay";
> };
>
> + ahci: sata at 01c18000 {
> + status = "okay";
> + };
> +
> pinctrl at 01c20800 {
> mmc0_cd_pin_a1000: mmc0_cd_pin at 0 {
> allwinner,pins = "PH1";
> diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> index f50fb2b..6ae1110 100644
> --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> @@ -12,6 +12,7 @@
>
> /dts-v1/;
> /include/ "sun4i-a10.dtsi"
> +/include/ "sunxi-ahci-reg.dtsi"
>
> / {
> model = "Cubietech Cubieboard";
> @@ -51,6 +52,11 @@
> status = "okay";
> };
>
> + ahci: sata at 01c18000 {
> + target-supply = <®_ahci_5v>;
> + status = "okay";
> + };
> +
> pinctrl at 01c20800 {
> mmc0_cd_pin_cubieboard: mmc0_cd_pin at 0 {
> allwinner,pins = "PH1";
> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
> index 4736dd2..198dcda 100644
> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> @@ -331,6 +331,14 @@
> status = "disabled";
> };
>
> + ahci: sata at 01c18000 {
> + compatible = "allwinner,sun4i-a10-ahci";
> + reg = <0x01c18000 0x1000>;
> + interrupts = <56>;
> + clocks = <&pll6 0>, <&ahb_gates 25>;
> + status = "disabled";
> + };
> +
Consider adding
pinctrl-names = "default";
in the ahci node to suppress "default pin state not found" warnings.
Same goes for sun7i-a20.dtsi.
> intc: interrupt-controller at 01c20400 {
> compatible = "allwinner,sun4i-ic";
> reg = <0x01c20400 0x400>;
> diff --git a/arch/arm/boot/dts/sunxi-ahci-reg.dtsi b/arch/arm/boot/dts/sunxi-ahci-reg.dtsi
> new file mode 100644
> index 0000000..955b197
> --- /dev/null
> +++ b/arch/arm/boot/dts/sunxi-ahci-reg.dtsi
> @@ -0,0 +1,38 @@
> +/*
> + * sunxi boards sata target power supply common code
> + *
> + * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/ {
> + soc at 01c00000 {
This block needs to be under
pinctrl at 01c20800 {
> + ahci_pwr_pin_a: ahci_pwr_pin at 0 {
> + allwinner,pins = "PB8";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
};
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + pinctrl-names = "default";
> +
> + reg_ahci_5v: ahci-5v {
> + compatible = "regulator-fixed";
> + regulator-name = "ahci-5v";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + pinctrl-0 = <&ahci_pwr_pin_a>;
> + gpio = <&pio 1 8 0>;
> + enable-active-high;
> + };
> + };
> +};
> --
> 1.8.5.3
>
Great work! Thanks!
ChenYu
^ permalink raw reply
* [BUG] FL1009: xHCI host not responding to stop endpoint command.
From: Arnaud Ebalard @ 2014-01-23 8:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140122235620.GC20359@xanatos>
Hi Sarah,
Sarah Sharp <sarah.a.sharp@linux.intel.com> writes:
>> > Can you pinpoint the commit that introduced the regression?
>>
>> f5182b4155b9d686c5540a6822486400e34ddd98 "xhci: Disable MSI for some Fresco Logic hosts."
>>
>> Technically, this is not per se the commit which introduced the
>> regression but the one that *partially* fixed it by introducing the XHCI
>> quirk to skip MSI enabling for Fresco Logic chips. The thing is it
>> should have included the FL1009 in the targets. Sarah, can you confirm
>> this?
>
> I don't know if it should have included FL1009, it was just a guess,
> based on the fact that the 0x1000 and 0x1400 devices did need MSI
> disabled. I can attempt to ask the Fresco Logic folks I know, but I'm
> not sure if/when I'll get a response back.
>
> That still doesn't necessarily rule out MSI issues in the Marvell PCI
> host controller code. Can you attach another PCI device with MSI
> support under the host and see if it works?
The various Armada-based devices I have are NAS which do not have PCIe
slots to plug additional devices (everything is soldered). I don't know
which device Thomas used for its tests. Just in case, I also added Willy
in CC: who have various boards and may also have done more test with
additional PCIe devices and CONFIG_PCI_MSI enabled on 3.13 kernel.
Cheers,
a+
^ permalink raw reply
* [PATCH 2/2] clocksource: Make clocksource register functions void
From: Yijing Wang @ 2014-01-23 8:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E0CD18.5080104@prisktech.co.nz>
On 2014/1/23 16:04, Tony Prisk wrote:
> On 23/01/14 20:58, Geert Uytterhoeven wrote:
>> On Thu, Jan 23, 2014 at 8:45 AM, Tony Prisk <linux@prisktech.co.nz> wrote:
>>>> -static inline int clocksource_register_hz(struct clocksource *cs, u32
>>>> hz)
>>>> +static inline void clocksource_register_hz(struct clocksource *cs, u32
>>>> hz)
>>>> {
>>>> return __clocksource_register_scale(cs, 1, hz);
>>>> }
>>>
>>> This doesn't make sense - you are still returning a value on a function
>>> declared void, and the return is now from a function that doesn't return
>>> anything either ?!?!
>>> Doesn't this throw a compile-time warning??
>> No, passing on void in functions returning void doesn't cause compiler
>> warnings.
>>
>> Gr{oetje,eeting}s,
>>
>> Geert
>>
>> --
>> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
>>
>> In personal conversations with technical people, I call myself a hacker. But
>> when I'm talking to journalists I just say "programmer" or something like that.
>> -- Linus Torvalds
> Doesn't seem right to me (even if there is no warning) but that's probably because I used to program in Pascal where functions with no return were 'procedures' :)
> Whether it needs to be changed or not:
>
> For the vt8500 part -
> Acked-by: Tony Prisk <linux@prisktech.co.nz>
Thanks!
>
> Regards
> Tony Prisk
>
>
> .
>
--
Thanks!
Yijing
^ permalink raw reply
* [PATCH] pinctrl: Rename Broadcom Capri pinctrl driver
From: Linus Walleij @ 2014-01-23 8:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390343886-25852-1-git-send-email-syin@broadcom.com>
On Tue, Jan 21, 2014 at 11:38 PM, Sherman Yin <syin@broadcom.com> wrote:
> To be consistent with other Broadcom drivers, the Broadcom Capri pinctrl
> driver and its related CONFIG option are renamed to bcm281xx.
>
> Devicetree compatible string and binding documentation use
> "brcm,bcm11351-pinctrl" to match the machine binding here:
> Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
>
> This driver supports pinctrl on BCM11130, BCM11140, BCM11351, BCM28145
> and BCM28155 SoCs.
>
> Signed-off-by: Sherman Yin <syin@broadcom.com>
> Reviewed-by: Matt Porter <mporter@linaro.org>
Patch applied for fixes.
If it was only the DT bindings that were rushed to change
you *could* have made a patch just changing these and the
binding doc, and give me the option to defer the changing of
variables and function names, but whatever.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 2/2] clocksource: Make clocksource register functions void
From: Tony Prisk @ 2014-01-23 8:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdUcKb8m71Z7dUo86MQ_KZgPujxsduUUt3Mz8Oke+DLSVw@mail.gmail.com>
On 23/01/14 20:58, Geert Uytterhoeven wrote:
> On Thu, Jan 23, 2014 at 8:45 AM, Tony Prisk <linux@prisktech.co.nz> wrote:
>>> -static inline int clocksource_register_hz(struct clocksource *cs, u32
>>> hz)
>>> +static inline void clocksource_register_hz(struct clocksource *cs, u32
>>> hz)
>>> {
>>> return __clocksource_register_scale(cs, 1, hz);
>>> }
>>
>> This doesn't make sense - you are still returning a value on a function
>> declared void, and the return is now from a function that doesn't return
>> anything either ?!?!
>> Doesn't this throw a compile-time warning??
> No, passing on void in functions returning void doesn't cause compiler
> warnings.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
Doesn't seem right to me (even if there is no warning) but that's
probably because I used to program in Pascal where functions with no
return were 'procedures' :)
Whether it needs to be changed or not:
For the vt8500 part -
Acked-by: Tony Prisk <linux@prisktech.co.nz>
Regards
Tony Prisk
^ permalink raw reply
* [PATCH 2/2] clocksource: Make clocksource register functions void
From: Geert Uytterhoeven @ 2014-01-23 7:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E0C889.6000106@prisktech.co.nz>
On Thu, Jan 23, 2014 at 8:45 AM, Tony Prisk <linux@prisktech.co.nz> wrote:
>> -static inline int clocksource_register_hz(struct clocksource *cs, u32
>> hz)
>> +static inline void clocksource_register_hz(struct clocksource *cs, u32
>> hz)
>> {
>> return __clocksource_register_scale(cs, 1, hz);
>> }
>
>
> This doesn't make sense - you are still returning a value on a function
> declared void, and the return is now from a function that doesn't return
> anything either ?!?!
> Doesn't this throw a compile-time warning??
No, passing on void in functions returning void doesn't cause compiler
warnings.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH 2/2] clocksource: Make clocksource register functions void
From: Tony Prisk @ 2014-01-23 7:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390461166-36440-1-git-send-email-wangyijing@huawei.com>
On 23/01/14 20:12, Yijing Wang wrote:
> Currently, clocksource_register() and __clocksource_register_scale()
> functions always return 0, it's pointless, make functions void.
> And remove the dead code that check the clocksource_register_hz()
> return value.
>
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
......
> diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
> index 67301a4..5a17c5e 100644
> --- a/include/linux/clocksource.h
> +++ b/include/linux/clocksource.h
> @@ -282,7 +282,7 @@ static inline s64 clocksource_cyc2ns(cycle_t cycles, u32 mult, u32 shift)
> }
>
>
> -extern int clocksource_register(struct clocksource*);
> +extern void clocksource_register(struct clocksource *);
> extern int clocksource_unregister(struct clocksource*);
> extern void clocksource_touch_watchdog(void);
> extern struct clocksource* clocksource_get_next(void);
> @@ -301,17 +301,17 @@ clocks_calc_mult_shift(u32 *mult, u32 *shift, u32 from, u32 to, u32 minsec);
> * Don't call __clocksource_register_scale directly, use
> * clocksource_register_hz/khz
> */
> -extern int
> +extern void
> __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq);
> extern void
> __clocksource_updatefreq_scale(struct clocksource *cs, u32 scale, u32 freq);
>
> -static inline int clocksource_register_hz(struct clocksource *cs, u32 hz)
> +static inline void clocksource_register_hz(struct clocksource *cs, u32 hz)
> {
> return __clocksource_register_scale(cs, 1, hz);
> }
This doesn't make sense - you are still returning a value on a function
declared void, and the return is now from a function that doesn't return
anything either ?!?!
Doesn't this throw a compile-time warning??
Regards
Tony Prisk
^ permalink raw reply
* [PATCH 2/2] clocksource: Make clocksource register functions void
From: Hans-Christian Egtvedt @ 2014-01-23 7:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390461166-36440-1-git-send-email-wangyijing@huawei.com>
Around Thu 23 Jan 2014 15:12:46 +0800 or thereabout, Yijing Wang wrote:
> Currently, clocksource_register() and __clocksource_register_scale()
> functions always return 0, it's pointless, make functions void.
> And remove the dead code that check the clocksource_register_hz()
> return value.
>
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
For the avr32 related change
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
> ---
> arch/arm/mach-davinci/time.c | 5 ++---
> arch/arm/mach-msm/timer.c | 4 +---
> arch/arm/mach-omap2/timer.c | 8 +++-----
> arch/avr32/kernel/time.c | 4 +---
> arch/blackfin/kernel/time-ts.c | 6 ++----
> arch/microblaze/kernel/timer.c | 3 +--
> arch/mips/jz4740/time.c | 6 +-----
> arch/mips/loongson/common/cs5536/cs5536_mfgpt.c | 3 ++-
> arch/openrisc/kernel/time.c | 3 +--
> arch/powerpc/kernel/time.c | 6 +-----
> arch/um/kernel/time.c | 6 +-----
> arch/x86/platform/uv/uv_time.c | 14 ++++++--------
> drivers/clocksource/acpi_pm.c | 3 ++-
> drivers/clocksource/cadence_ttc_timer.c | 6 +-----
> drivers/clocksource/exynos_mct.c | 4 +---
> drivers/clocksource/i8253.c | 3 ++-
> drivers/clocksource/mmio.c | 3 ++-
> drivers/clocksource/samsung_pwm_timer.c | 5 +----
> drivers/clocksource/scx200_hrt.c | 3 ++-
> drivers/clocksource/tcb_clksrc.c | 8 +-------
> drivers/clocksource/timer-marco.c | 2 +-
> drivers/clocksource/timer-prima2.c | 2 +-
> drivers/clocksource/vt8500_timer.c | 4 +---
> include/linux/clocksource.h | 8 ++++----
> kernel/time/clocksource.c | 6 ++----
> kernel/time/jiffies.c | 3 ++-
> 26 files changed, 45 insertions(+), 83 deletions(-)
<snipp diffs>
--
HcE
^ permalink raw reply
* [PATCH] pinctrl: at91: use locked variant of irq_set_handler
From: Linus Walleij @ 2014-01-23 7:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390319718-12285-1-git-send-email-nicolas.ferre@atmel.com>
On Tue, Jan 21, 2014 at 4:55 PM, Nicolas Ferre <nicolas.ferre@atmel.com> wrote:
> When setting the gpio irq type, use the __irq_set_handler_locked()
> variant instead of the irq_set_handler() to prevent false
> spinlock recursion warning.
>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> Cc: stable <stable@vger.kernel.org> # v3.12
Patch applied for fixes.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 5/5] ARM: tegra: cpuidle: use firmware call for power down
From: Alexandre Courbot @ 2014-01-23 7:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E02DCC.1000404@wwwdotorg.org>
On Thu, Jan 23, 2014 at 5:45 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 01/21/2014 03:10 AM, Alexandre Courbot wrote:
>> Invoke the do_idle() firmware call before suspending a CPU so that the
>> underlying firmware (if any) can take necessary action.
>
>> diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
>
>> @@ -45,6 +46,8 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
>>
>> clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
>>
>> + call_firmware_op(do_idle);
>> +
>> cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
>>
>> clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
>
> Don't you need to have the kernel also *not* do something when entering
> idle; doesn't the FW op replace some of the register writes that the
> kernel would otherwise be doing?
It seems like the operation is actually to inform the firmware that we
are going to suspend the CPU. Downstream kernel also uses it that way.
But you are right in that we should expect do_idle() to actually
perform the suspend operation. Maybe a prepare_idle() operation should
be added to the firmware interface for this purpose?
^ permalink raw reply
* [PATCH 4/5] ARM: trusted_foundations: implement do_idle()
From: Alexandre Courbot @ 2014-01-23 7:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E02D8C.7090309@wwwdotorg.org>
On Thu, Jan 23, 2014 at 5:43 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 01/21/2014 03:10 AM, Alexandre Courbot wrote:
>> Support the do_idle() firmware call, which is necessary to properly
>> support cpuidle.
>
>> diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c
>
>> +#define TF_CPU_PM 0xfffffffc
>> +#define TF_CPU_PM_LP0 0xffffffe3
>> +#define TF_CPU_PM_LP1 0xffffffe6
>> +#define TF_CPU_PM_LP1_NO_MC_CLK 0xffffffe5
>> +#define TF_CPU_PM_LP2 0xffffffe4
>> +#define TF_CPU_PM_LP2_NOFLUSH_L2 0xffffffe7
>
> Hmm. This must be Tegra-specific, not generic to any TF client, since
> aren't the names of the suspend states (LP0, LP1, LP2) entirely specific
> to Tegra?
The names are negligence on my part, actually. I arbitrarily named
them that way without thinking this was Tegra-only denomination. The
downstream kernel does not even use these, they hardcode the values
directly. Will fix that, thanks for spotting it.
^ permalink raw reply
* [PATCH 3/5] ARM: firmware: enable Trusted Foundations by default
From: Alexandre Courbot @ 2014-01-23 7:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E02D40.3090803@wwwdotorg.org>
On Thu, Jan 23, 2014 at 5:42 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 01/21/2014 03:10 AM, Alexandre Courbot wrote:
>> As discussed previously (https://lkml.org/lkml/2013/11/26/289), enable
>> Trusted Foundation support by default since it already depends on a
>> supporting architecture being selected.
>>
>> Doing so allows us to remove it from tegra_defconfig.
>
>> arch/arm/configs/tegra_defconfig | 1 -
>> arch/arm/firmware/Kconfig | 1 +
>
> Can we split out the defconfig and code changes into separate patches?
> They need to go through seperate branches, possibly even separate repos.
>
> The defconfig change might not even be necessary; at some point I'll
> just rebuild it via "make tegra_defconfig; make savedefconfig" on top of
> some linux-next that includes the Kconfig change, and it'll happen
> automatically. Still, I guess there's no harm explicitly sending the patch.
If we can do without the defconfig change then I will just omit it in
the next version - I don't like sending too many oneliners. :P
^ permalink raw reply
* [PATCHv2 2/2] pwm: imx: support polarity inversion
From: Lothar Waßmann @ 2014-01-23 7:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140116160356.GY16215@pengutronix.de>
Hi,
Sascha Hauer wrote:
> On Thu, Jan 16, 2014 at 09:06:25AM +0100, Lothar Wa?mann wrote:
> > The i.MX PWM controller supports inverting the polarity of the PWM
> > output. Make this feature available in the pxm-imx driver.
> >
> > Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
> > ---
> > Documentation/devicetree/bindings/pwm/imx-pwm.txt | 5 +-
> > drivers/pwm/pwm-imx.c | 42 +++++++++++++++++++++
> > 2 files changed, 45 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> > index b50d7a6d..d0b04b5 100644
> > --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> > +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> > @@ -3,8 +3,9 @@ Freescale i.MX PWM controller
> > Required properties:
> > - compatible: should be "fsl,<soc>-pwm"
> > - reg: physical base address and length of the controller's registers
> > -- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
> > - the cells format.
> > +- #pwm-cells: may be 2 for backwards compatibility or 3 to support
> > + switching the output polarity. See pwm.txt in this directory for a
> > + description of the cells format.
> > - interrupts: The interrupt for the pwm controller
> >
> > Example:
> > diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> > index 3b00a82..05461bb 100644
> > --- a/drivers/pwm/pwm-imx.c
> > +++ b/drivers/pwm/pwm-imx.c
> > @@ -36,6 +36,7 @@
> > #define MX3_PWMCR_DOZEEN (1 << 24)
> > #define MX3_PWMCR_WAITEN (1 << 23)
> > #define MX3_PWMCR_DBGEN (1 << 22)
> > +#define MX3_PWMCR_POUTC (1 << 18)
> > #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
> > #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
> > #define MX3_PWMCR_EN (1 << 0)
> > @@ -138,6 +139,9 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
> > if (test_bit(PWMF_ENABLED, &pwm->flags))
> > cr |= MX3_PWMCR_EN;
> >
> > + if (pwm->polarity == PWM_POLARITY_INVERSED)
> > + cr |= MX3_PWMCR_POUTC;
> > +
> > writel(cr, imx->mmio_base + MX3_PWMCR);
> >
> > return 0;
> > @@ -155,6 +159,11 @@ static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
> > else
> > val &= ~MX3_PWMCR_EN;
> >
> > + if (chip->pwms[0].polarity == PWM_POLARITY_INVERSED)
> > + val |= MX3_PWMCR_POUTC;
> > + else
> > + val &= ~MX3_PWMCR_POUTC;
> > +
> > writel(val, imx->mmio_base + MX3_PWMCR);
> > }
> >
> > @@ -198,6 +207,17 @@ static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
> > clk_disable_unprepare(imx->clk_per);
> > }
> >
> > +static int imx_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
> > + enum pwm_polarity polarity)
> > +{
> > + struct imx_chip *imx = to_imx_chip(chip);
> > +
> > + dev_dbg(imx->chip.dev, "%s: polarity set to %s\n", __func__,
> > + polarity == PWM_POLARITY_INVERSED ? "inverted" : "normal");
> > +
> > + return 0;
> > +}
> > +
> > static struct pwm_ops imx_pwm_ops = {
> > .enable = imx_pwm_enable,
> > .disable = imx_pwm_disable,
> > @@ -209,6 +229,7 @@ struct imx_pwm_data {
> > int (*config)(struct pwm_chip *chip,
> > struct pwm_device *pwm, int duty_ns, int period_ns);
> > void (*set_enable)(struct pwm_chip *chip, bool enable);
> > + unsigned output_polarity:1;
> > };
> >
> > static struct imx_pwm_data imx_pwm_data_v1 = {
> > @@ -219,6 +240,7 @@ static struct imx_pwm_data imx_pwm_data_v1 = {
> > static struct imx_pwm_data imx_pwm_data_v2 = {
> > .config = imx_pwm_config_v2,
> > .set_enable = imx_pwm_set_enable_v2,
> > + .output_polarity = 1,
> > };
> >
> > static const struct of_device_id imx_pwm_dt_ids[] = {
> > @@ -271,6 +293,26 @@ static int imx_pwm_probe(struct platform_device *pdev)
> > return PTR_ERR(imx->mmio_base);
> >
> > data = of_id->data;
> > + if (data->output_polarity) {
> > + const struct device_node *np = pdev->dev.of_node;
> > + u32 num_cells;
> > +
> > + dev_dbg(&pdev->dev, "PWM supports output inversion\n");
> > + ret = of_property_read_u32(np, "#pwm-cells", &num_cells);
> > + if (ret < 0) {
> > + dev_err(&pdev->dev, "missing property '#pwm-cells'\n");
> > + return ret;
> > + }
> > + if (num_cells == 3) {
> > + imx_pwm_ops.set_polarity = imx_pwm_set_polarity;
> > + imx->chip.of_xlate = of_pwm_xlate_with_flags;
> > + } else if (num_cells != 2) {
> > + dev_err(&pdev->dev, "'#pwm-cells' must be <2> or <3>\n");
> > + return -EINVAL;
> > + }
> > + imx->chip.of_pwm_n_cells = num_cells;
> > + }
>
> Can't this be done in the PWM core? Right now the PWM core checks for
> of_pwm_n_cells before calling ->of_xlate. IMO this check should be done
> in the of_xlate hook. Then of_pwm_simple_xlate and
> of_pwm_xlate_with_flags can be merged into something like:
>
This wouldn't buy much without a material change to of_pwm_get().
The function of_parse_phandle_with_args() called by of_pwm_get()
requires the number of args in the pwms property be greater or equal to
the #pwm-cells property in the pwm node. Thus, the interesting case of
having #pwm-cells = <3> without changing the existing users is
prohibited by of_parse_phandle_with_args().
of_pwm_get() would have to be changed to something like below to allow
this:
struct pwm_device *of_pwm_get(struct device_node *np, const char *con_id)
{
struct pwm_device *pwm = NULL;
struct of_phandle_args args;
struct pwm_chip *pc;
int index = 0;
int err;
struct property *prop;
u32 num_cells;
int i;
const __be32 *list;
if (con_id) {
index = of_property_match_string(np, "pwm-names", con_id);
if (index < 0)
return ERR_PTR(index);
}
args.np = of_parse_phandle(np, "pwms", index);
if (!args.np) {
pr_err("%s(): property 'pwms' not found in '%s'\n",
__func__, np->full_name);
return ERR_PTR(-ENOENT);
}
err = of_property_read_u32(args.np, "#pwm-cells", &num_cells);
if (err) {
pr_err("%s(): could not read property '#pwm-cells' in '%s': %d\n",
__func__, args.np->full_name, err);
return ERR_PTR(err);
}
prop = of_find_property(np, "pwms", NULL);
if (WARN_ON(!prop))
return ERR_PTR(-EINVAL);
args.args_count = prop->length / sizeof(u32) - 1;
list = prop->value;
for (i = 0; i < args.args_count; i++)
args.args[i] = be32_to_cpup(++list);
pc = of_node_to_pwmchip(args.np);
if (IS_ERR(pc)) {
pr_err("%s(): PWM chip not found\n", __func__);
pwm = ERR_CAST(pc);
goto put;
}
[...]
Lothar Wa?mann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________
^ permalink raw reply
* [PATCH v2 4/4] ARM:STi: STiH415: Add interrupt support for pin controller
From: Linus Walleij @ 2014-01-23 7:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389886665-32076-1-git-send-email-srinivas.kandagatla@st.com>
On Thu, Jan 16, 2014 at 4:37 PM, <srinivas.kandagatla@st.com> wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
>
> This patch adds interrupt support for STiH415 pin controllers.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Merge this through ARM SoC.
> + reg = <0xfe61f080 0x4>;
> + reg-names = "irqmux";
Aha so that is how it looks when you handle the separate
mux reg, well I can't think of anything better and this works
fine for me.
The alternative would be to have a syscon thing using regmap
such as drivers/mfd/syscon.c but I really cannot decide
between these two design patterns for odd registers.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 3/4] ARM:STi: STiH416: Add interrupt support for pin controller
From: Linus Walleij @ 2014-01-23 7:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389886657-32035-1-git-send-email-srinivas.kandagatla@st.com>
On Thu, Jan 16, 2014 at 4:37 PM, <srinivas.kandagatla@st.com> wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
>
> This patch adds interrupt support for STiH416 pin controllers.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Please merge this through the ARM SoC tree with the rest of
your device tree stuff.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 2/4] pinctrl: st: Add software edge trigger interrupt support.
From: Linus Walleij @ 2014-01-23 7:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389886651-31990-1-git-send-email-srinivas.kandagatla@st.com>
On Thu, Jan 16, 2014 at 4:37 PM, <srinivas.kandagatla@st.com> wrote:
> ST pin controller does not have hardware support for detecting edge
> triggered interrupts, It only has level triggering support.
> This patch attempts to fake up edge triggers from hw level trigger
> support in software.
(...)
> +/*
> + * Edge triggers are not supported at hardware level, it is supported by
> + * software by exploiting the level trigger support in hardware.
> + * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
> + * of each gpio pin in a GPIO bank.
(...)
> +/*
> + * As edge triggers are not supported at hardware level, it is supported by
> + * software by exploiting the level trigger support in hardware.
(...)
All this is quite hard to understand. Maybe it's just because
it's hard overall. Edge triggers are not supported by hardware
so we use the hardware edge trigger support?
That is a bit oxymoronic...
> + * Steps for detection raising edge interrupt in software.
> + *
> + * Step 1: CONFIGURE pin to detect level LOW interrupts.
> + *
> + * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
> + * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
> + * IGNORE calling the actual interrupt handler for the pin at this stage.
> + *
> + * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
> + * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
> + * DISPATCH the interrupt to the interrupt handler of the pin.
But I do understand this, that's VERY clever and may be something
that can be exploited on other hardware as well some day.
So patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 1/4] pinctrl: st: Add Interrupt support.
From: Linus Walleij @ 2014-01-23 7:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389886613-31945-1-git-send-email-srinivas.kandagatla@st.com>
On Thu, Jan 16, 2014 at 4:36 PM, <srinivas.kandagatla@st.com> wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
>
> This patch add interrupt support to the pincontroller driver.
>
> ST Pincontroller GPIO bank can have one of the two possible types of
> interrupt-wirings.
>
> First type is via irqmux, single interrupt is used by multiple gpio
> banks. This reduces number of overall interrupts numbers required. All
> these banks belong to a single pincontroller.
> _________
> | |----> [gpio-bank (n) ]
> | |----> [gpio-bank (n + 1)]
> [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
> | |----> [gpio-bank (... )]
> |_________|----> [gpio-bank (n + 7)]
>
> Second type has a dedicated interrupt per gpio bank.
>
> [irqN]----> [gpio-bank (n)]
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
I've applied this patch so that it won't just sit idle.
Besides you've done a real good job on it Srinivas.
It'll be for v3.15 though and I'm still waiting to see if
the device tree people say something about it.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 2/2] clocksource: Make clocksource register functions void
From: Yijing Wang @ 2014-01-23 7:12 UTC (permalink / raw)
To: linux-arm-kernel
Currently, clocksource_register() and __clocksource_register_scale()
functions always return 0, it's pointless, make functions void.
And remove the dead code that check the clocksource_register_hz()
return value.
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
---
arch/arm/mach-davinci/time.c | 5 ++---
arch/arm/mach-msm/timer.c | 4 +---
arch/arm/mach-omap2/timer.c | 8 +++-----
arch/avr32/kernel/time.c | 4 +---
arch/blackfin/kernel/time-ts.c | 6 ++----
arch/microblaze/kernel/timer.c | 3 +--
arch/mips/jz4740/time.c | 6 +-----
arch/mips/loongson/common/cs5536/cs5536_mfgpt.c | 3 ++-
arch/openrisc/kernel/time.c | 3 +--
arch/powerpc/kernel/time.c | 6 +-----
arch/um/kernel/time.c | 6 +-----
arch/x86/platform/uv/uv_time.c | 14 ++++++--------
drivers/clocksource/acpi_pm.c | 3 ++-
drivers/clocksource/cadence_ttc_timer.c | 6 +-----
drivers/clocksource/exynos_mct.c | 4 +---
drivers/clocksource/i8253.c | 3 ++-
drivers/clocksource/mmio.c | 3 ++-
drivers/clocksource/samsung_pwm_timer.c | 5 +----
drivers/clocksource/scx200_hrt.c | 3 ++-
drivers/clocksource/tcb_clksrc.c | 8 +-------
drivers/clocksource/timer-marco.c | 2 +-
drivers/clocksource/timer-prima2.c | 2 +-
drivers/clocksource/vt8500_timer.c | 4 +---
include/linux/clocksource.h | 8 ++++----
kernel/time/clocksource.c | 6 ++----
kernel/time/jiffies.c | 3 ++-
26 files changed, 45 insertions(+), 83 deletions(-)
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 56c6eb5..9536f85 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -387,9 +387,8 @@ void __init davinci_timer_init(void)
/* setup clocksource */
clocksource_davinci.name = id_to_name[clocksource_id];
- if (clocksource_register_hz(&clocksource_davinci,
- davinci_clock_tick_rate))
- printk(err, clocksource_davinci.name);
+ clocksource_register_hz(&clocksource_davinci,
+ davinci_clock_tick_rate);
setup_sched_clock(davinci_read_sched_clock, 32,
davinci_clock_tick_rate);
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 1e9c338..c96e034 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -226,9 +226,7 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
err:
writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
- res = clocksource_register_hz(cs, dgt_hz);
- if (res)
- pr_err("clocksource_register failed\n");
+ clocksource_register_hz(cs, dgt_hz);
setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
}
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 3ca81e0..beaf7c7 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -473,11 +473,9 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
OMAP_TIMER_NONPOSTED);
setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
- if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
- pr_err("Could not register clocksource %s\n",
- clocksource_gpt.name);
- else
- pr_info("OMAP clocksource: %s at %lu Hz\n",
+ clocksource_register_hz(&clocksource_gpt, clksrc.rate);
+
+ pr_info("OMAP clocksource: %s at %lu Hz\n",
clocksource_gpt.name, clksrc.rate);
}
diff --git a/arch/avr32/kernel/time.c b/arch/avr32/kernel/time.c
index d0f771b..51b4a66 100644
--- a/arch/avr32/kernel/time.c
+++ b/arch/avr32/kernel/time.c
@@ -134,9 +134,7 @@ void __init time_init(void)
/* figure rate for counter */
counter_hz = clk_get_rate(boot_cpu_data.clk);
- ret = clocksource_register_hz(&counter, counter_hz);
- if (ret)
- pr_debug("timer: could not register clocksource: %d\n", ret);
+ clocksource_register_hz(&counter, counter_hz);
/* setup COMPARE clockevent */
comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
index cb0a484..df3bb08 100644
--- a/arch/blackfin/kernel/time-ts.c
+++ b/arch/blackfin/kernel/time-ts.c
@@ -51,8 +51,7 @@ static inline unsigned long long bfin_cs_cycles_sched_clock(void)
static int __init bfin_cs_cycles_init(void)
{
- if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
- panic("failed to register clocksource");
+ clocksource_register_hz(&bfin_cs_cycles, get_cclk());
return 0;
}
@@ -103,8 +102,7 @@ static int __init bfin_cs_gptimer0_init(void)
{
setup_gptimer0();
- if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
- panic("failed to register clocksource");
+ clocksource_register_hz(&bfin_cs_gptimer0, get_sclk());
return 0;
}
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index 3e39b10..6a2417e 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -208,8 +208,7 @@ static struct clocksource clocksource_microblaze = {
static int __init xilinx_clocksource_init(void)
{
- if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq))
- panic("failed to register clocksource");
+ clocksource_register_hz(&clocksource_microblaze, timer_clock_freq);
/* stop timer1 */
out_be32(timer_baseaddr + TCSR1,
diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
index 5e430ce..041cdff 100644
--- a/arch/mips/jz4740/time.c
+++ b/arch/mips/jz4740/time.c
@@ -105,7 +105,6 @@ static struct irqaction timer_irqaction = {
void __init plat_time_init(void)
{
- int ret;
uint32_t clk_rate;
uint16_t ctrl;
@@ -121,10 +120,7 @@ void __init plat_time_init(void)
clockevents_register_device(&jz4740_clockevent);
- ret = clocksource_register_hz(&jz4740_clocksource, clk_rate);
-
- if (ret)
- printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
+ clocksource_register_hz(&jz4740_clocksource, clk_rate);
setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
index c639b9d..9fa6d99 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -208,7 +208,8 @@ int __init init_mfgpt_clocksource(void)
if (num_possible_cpus() > 1) /* MFGPT does not scale! */
return 0;
- return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
+ clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
+ return 0;
}
arch_initcall(init_mfgpt_clocksource);
diff --git a/arch/openrisc/kernel/time.c b/arch/openrisc/kernel/time.c
index 7c52e94..3f789aa 100644
--- a/arch/openrisc/kernel/time.c
+++ b/arch/openrisc/kernel/time.c
@@ -156,8 +156,7 @@ static struct clocksource openrisc_timer = {
static int __init openrisc_timer_init(void)
{
- if (clocksource_register_hz(&openrisc_timer, cpuinfo.clock_frequency))
- panic("failed to register clocksource");
+ clocksource_register_hz(&openrisc_timer, cpuinfo.clock_frequency);
/* Enable the incrementer: 'continuous' mode with interrupt disabled */
mtspr(SPR_TTMR, SPR_TTMR_CR);
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index b3b1441..27c0627 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -788,11 +788,7 @@ static void __init clocksource_init(void)
else
clock = &clocksource_timebase;
- if (clocksource_register_hz(clock, tb_ticks_per_sec)) {
- printk(KERN_ERR "clocksource: %s is already registered\n",
- clock->name);
- return;
- }
+ clocksource_register_hz(clock, tb_ticks_per_sec);
printk(KERN_INFO "clocksource: %s mult[%x] shift[%d] registered\n",
clock->name, clock->mult, clock->shift);
diff --git a/arch/um/kernel/time.c b/arch/um/kernel/time.c
index 117568d..2034b58 100644
--- a/arch/um/kernel/time.c
+++ b/arch/um/kernel/time.c
@@ -92,11 +92,7 @@ static void __init setup_itimer(void)
clockevent_delta2ns(60 * HZ, &itimer_clockevent);
itimer_clockevent.min_delta_ns =
clockevent_delta2ns(1, &itimer_clockevent);
- err = clocksource_register_hz(&itimer_clocksource, USEC_PER_SEC);
- if (err) {
- printk(KERN_ERR "clocksource_register_hz returned %d\n", err);
- return;
- }
+ clocksource_register_hz(&itimer_clocksource, USEC_PER_SEC);
clockevents_register_device(&itimer_clockevent);
}
diff --git a/arch/x86/platform/uv/uv_time.c b/arch/x86/platform/uv/uv_time.c
index 5c86786..b963774 100644
--- a/arch/x86/platform/uv/uv_time.c
+++ b/arch/x86/platform/uv/uv_time.c
@@ -379,15 +379,13 @@ static __init int uv_rtc_setup_clock(void)
if (!is_uv_system())
return -ENODEV;
- rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
- if (rc)
- printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
- else
- printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
- sn_rtc_cycles_per_second/(unsigned long)1E6);
+ clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
+
+ pr_info("UV RTC clocksource registered freq %lu MHz\n",
+ sn_rtc_cycles_per_second/(unsigned long)1E6);
- if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback)
- return rc;
+ if (!uv_rtc_evt_enable || x86_platform_ipi_callback)
+ return 0;
/* Setup and register clockevents */
rc = uv_rtc_allocate_timers();
diff --git a/drivers/clocksource/acpi_pm.c b/drivers/clocksource/acpi_pm.c
index 6eab889..ab1dc63 100644
--- a/drivers/clocksource/acpi_pm.c
+++ b/drivers/clocksource/acpi_pm.c
@@ -218,8 +218,9 @@ static int __init init_acpi_pm_clocksource(void)
return -ENODEV;
}
- return clocksource_register_hz(&clocksource_acpi_pm,
+ clocksource_register_hz(&clocksource_acpi_pm,
PMTMR_TICKS_PER_SEC);
+ return 0;
}
/* We use fs_initcall because we want the PCI fixups to have run
diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
index 63f176d..b9b56ed 100644
--- a/drivers/clocksource/cadence_ttc_timer.c
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -301,11 +301,7 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
__raw_writel(CNT_CNTRL_RESET,
ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
- err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
- if (WARN_ON(err)) {
- kfree(ttccs);
- return;
- }
+ clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
sched_clock_register(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 62b0de6..98649c7 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -193,9 +193,7 @@ struct clocksource mct_frc = {
static void __init exynos4_clocksource_init(void)
{
exynos4_mct_frc_start(0, 0);
-
- if (clocksource_register_hz(&mct_frc, clk_rate))
- panic("%s: can't register clocksource\n", mct_frc.name);
+ clocksource_register_hz(&mct_frc, clk_rate);
}
static void exynos4_mct_comp0_stop(void)
diff --git a/drivers/clocksource/i8253.c b/drivers/clocksource/i8253.c
index 14ee3ef..9c45f0a 100644
--- a/drivers/clocksource/i8253.c
+++ b/drivers/clocksource/i8253.c
@@ -95,7 +95,8 @@ static struct clocksource i8253_cs = {
int __init clocksource_i8253_init(void)
{
- return clocksource_register_hz(&i8253_cs, PIT_TICK_RATE);
+ clocksource_register_hz(&i8253_cs, PIT_TICK_RATE);
+ return 0;
}
#endif
diff --git a/drivers/clocksource/mmio.c b/drivers/clocksource/mmio.c
index c0e2512..6e0b530 100644
--- a/drivers/clocksource/mmio.c
+++ b/drivers/clocksource/mmio.c
@@ -69,5 +69,6 @@ int __init clocksource_mmio_init(void __iomem *base, const char *name,
cs->clksrc.mask = CLOCKSOURCE_MASK(bits);
cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
- return clocksource_register_hz(&cs->clksrc, hz);
+ clocksource_register_hz(&cs->clksrc, hz);
+ return 0;
}
diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c
index 5645cfc..c59292f 100644
--- a/drivers/clocksource/samsung_pwm_timer.c
+++ b/drivers/clocksource/samsung_pwm_timer.c
@@ -340,7 +340,6 @@ static void __init samsung_clocksource_init(void)
{
unsigned long pclk;
unsigned long clock_rate;
- int ret;
pclk = clk_get_rate(pwm.timerclk);
@@ -361,9 +360,7 @@ static void __init samsung_clocksource_init(void)
pwm.variant.bits, clock_rate);
samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
- ret = clocksource_register_hz(&samsung_clocksource, clock_rate);
- if (ret)
- panic("samsung_clocksource_timer: can't register clocksource\n");
+ clocksource_register_hz(&samsung_clocksource, clock_rate);
}
static void __init samsung_timer_resources(void)
diff --git a/drivers/clocksource/scx200_hrt.c b/drivers/clocksource/scx200_hrt.c
index 64f9e82..57bdc04 100644
--- a/drivers/clocksource/scx200_hrt.c
+++ b/drivers/clocksource/scx200_hrt.c
@@ -83,7 +83,8 @@ static int __init init_hrt_clocksource(void)
pr_info("enabling scx200 high-res timer (%s MHz +%d ppm)\n", mhz27 ? "27":"1", ppm);
- return clocksource_register_hz(&cs_hrt, freq);
+ clocksource_register_hz(&cs_hrt, freq);
+ return 0;
}
module_init(init_hrt_clocksource);
diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
index 00fdd11..805245d 100644
--- a/drivers/clocksource/tcb_clksrc.c
+++ b/drivers/clocksource/tcb_clksrc.c
@@ -340,9 +340,7 @@ static int __init tcb_clksrc_init(void)
}
/* and away we go! */
- ret = clocksource_register_hz(&clksrc, divided_rate);
- if (ret)
- goto err_disable_t1;
+ clocksource_register_hz(&clksrc, divided_rate);
/* channel 2: periodic and oneshot timer support */
ret = setup_clkevents(tc, clk32k_divisor_idx);
@@ -354,10 +352,6 @@ static int __init tcb_clksrc_init(void)
err_unregister_clksrc:
clocksource_unregister(&clksrc);
-err_disable_t1:
- if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
- clk_disable_unprepare(tc->clk[1]);
-
err_disable_t0:
clk_disable_unprepare(t0_clk);
diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
index 09a17d9..ae78ce0 100644
--- a/drivers/clocksource/timer-marco.c
+++ b/drivers/clocksource/timer-marco.c
@@ -283,7 +283,7 @@ static void __init sirfsoc_marco_timer_init(void)
/* Clear all interrupts */
writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
- BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
+ clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE);
sirfsoc_clockevent_init();
}
diff --git a/drivers/clocksource/timer-prima2.c b/drivers/clocksource/timer-prima2.c
index 8a492d3..c9cc307 100644
--- a/drivers/clocksource/timer-prima2.c
+++ b/drivers/clocksource/timer-prima2.c
@@ -204,7 +204,7 @@ static void __init sirfsoc_prima2_timer_init(struct device_node *np)
writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
- BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
+ clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE);
sched_clock_register(sirfsoc_read_sched_clock, 64, CLOCK_TICK_RATE);
diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/vt8500_timer.c
index 1098ed3..13f5fa4 100644
--- a/drivers/clocksource/vt8500_timer.c
+++ b/drivers/clocksource/vt8500_timer.c
@@ -150,9 +150,7 @@ static void __init vt8500_timer_init(struct device_node *np)
writel(0xf, regbase + TIMER_STATUS_VAL);
writel(~0, regbase + TIMER_MATCH_VAL);
- if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
- pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
- __func__, clocksource.name);
+ clocksource_register_hz(&clocksource, VT8500_TIMER_HZ);
clockevent.cpumask = cpumask_of(0);
diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
index 67301a4..5a17c5e 100644
--- a/include/linux/clocksource.h
+++ b/include/linux/clocksource.h
@@ -282,7 +282,7 @@ static inline s64 clocksource_cyc2ns(cycle_t cycles, u32 mult, u32 shift)
}
-extern int clocksource_register(struct clocksource*);
+extern void clocksource_register(struct clocksource *);
extern int clocksource_unregister(struct clocksource*);
extern void clocksource_touch_watchdog(void);
extern struct clocksource* clocksource_get_next(void);
@@ -301,17 +301,17 @@ clocks_calc_mult_shift(u32 *mult, u32 *shift, u32 from, u32 to, u32 minsec);
* Don't call __clocksource_register_scale directly, use
* clocksource_register_hz/khz
*/
-extern int
+extern void
__clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq);
extern void
__clocksource_updatefreq_scale(struct clocksource *cs, u32 scale, u32 freq);
-static inline int clocksource_register_hz(struct clocksource *cs, u32 hz)
+static inline void clocksource_register_hz(struct clocksource *cs, u32 hz)
{
return __clocksource_register_scale(cs, 1, hz);
}
-static inline int clocksource_register_khz(struct clocksource *cs, u32 khz)
+static inline void clocksource_register_khz(struct clocksource *cs, u32 khz)
{
return __clocksource_register_scale(cs, 1000, khz);
}
diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c
index 9951575..686ff72 100644
--- a/kernel/time/clocksource.c
+++ b/kernel/time/clocksource.c
@@ -782,7 +782,7 @@ EXPORT_SYMBOL_GPL(__clocksource_updatefreq_scale);
* This *SHOULD NOT* be called directly! Please use the
* clocksource_register_hz() or clocksource_register_khz helper functions.
*/
-int __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq)
+void __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq)
{
/* Initialize mult/shift and max_idle_ns */
@@ -794,7 +794,6 @@ int __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq)
clocksource_enqueue_watchdog(cs);
clocksource_select();
mutex_unlock(&clocksource_mutex);
- return 0;
}
EXPORT_SYMBOL_GPL(__clocksource_register_scale);
@@ -804,7 +803,7 @@ EXPORT_SYMBOL_GPL(__clocksource_register_scale);
* @cs: clocksource to be registered
*
*/
-int clocksource_register(struct clocksource *cs)
+void clocksource_register(struct clocksource *cs)
{
/* calculate max adjustment for given mult/shift */
cs->maxadj = clocksource_max_adjustment(cs);
@@ -820,7 +819,6 @@ int clocksource_register(struct clocksource *cs)
clocksource_enqueue_watchdog(cs);
clocksource_select();
mutex_unlock(&clocksource_mutex);
- return 0;
}
EXPORT_SYMBOL(clocksource_register);
diff --git a/kernel/time/jiffies.c b/kernel/time/jiffies.c
index 7a925ba..ae4c534 100644
--- a/kernel/time/jiffies.c
+++ b/kernel/time/jiffies.c
@@ -88,7 +88,8 @@ EXPORT_SYMBOL(jiffies);
static int __init init_jiffies_clocksource(void)
{
- return clocksource_register(&clocksource_jiffies);
+ clocksource_register(&clocksource_jiffies);
+ return 0;
}
core_initcall(init_jiffies_clocksource);
--
1.7.1
^ permalink raw reply related
* [PATCH 1/2] clocksource: Remove outdated comments
From: Yijing Wang @ 2014-01-23 7:12 UTC (permalink / raw)
To: linux-arm-kernel
clocksource_register() and __clocksource_register_scale()
always return 0, so the comment is just pointless, it's
outdated, remove it.
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
---
kernel/time/clocksource.c | 3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c
index ba3e502..9951575 100644
--- a/kernel/time/clocksource.c
+++ b/kernel/time/clocksource.c
@@ -779,8 +779,6 @@ EXPORT_SYMBOL_GPL(__clocksource_updatefreq_scale);
* @scale: Scale factor multiplied against freq to get clocksource hz
* @freq: clocksource frequency (cycles per second) divided by scale
*
- * Returns -EBUSY if registration fails, zero otherwise.
- *
* This *SHOULD NOT* be called directly! Please use the
* clocksource_register_hz() or clocksource_register_khz helper functions.
*/
@@ -805,7 +803,6 @@ EXPORT_SYMBOL_GPL(__clocksource_register_scale);
* clocksource_register - Used to install new clocksources
* @cs: clocksource to be registered
*
- * Returns -EBUSY if registration fails, zero otherwise.
*/
int clocksource_register(struct clocksource *cs)
{
--
1.7.1
^ permalink raw reply related
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