* [RFC/PATCH] ARM: dove: Remove UBI support from defconfig
From: Ezequiel Garcia @ 2014-01-27 15:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140127150040.GH29184@titan.lakedaemon.net>
On Mon, Jan 27, 2014 at 10:00:40AM -0500, Jason Cooper wrote:
> On Mon, Jan 27, 2014 at 10:26:29AM -0300, Ezequiel Garcia wrote:
> > As NAND support is not enabled by default, it's hard to see
> > why we'd want to have UBI support. Let's remove it.
>
> I'd rather add support for the nand.
>
Well, there isn't any Dove board (that we currently support) with a NAND
device. Would you still want to add it?
In that case, we should consider adding UBIFS as well. Having CONFIG_UBI
by itself doesn't make any sense.
--
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
^ permalink raw reply
* [Q] block / zynq: DMA bouncing
From: Guennadi Liakhovetski @ 2014-01-27 15:13 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
I'm working on an MMC driver with a DMA capability. All has been working
well, until at some point I've got a bus error, when the mmc driver had
been handed in a buffer at 0x3000 physical RAM address. The reason is,
that on Zynq arch bus masters cannot access RAM below 0x80000. Therefore
my question: how shall I configure this in software?
The way I found was to use ARM-specific struct dmabounce_device_info and
implement its .needs_bounce() method to return true for those addresses.
Is this the right way or is there a better / more straight-forward one?
To do the above I have to enable CONFIG_DMABOUNCE, which then selects
CONFIG_ZONE_DMA. Having done just that I suddenly discover, that 0x3000
buffers aren't used any more, so, I cannot actually verify my
implementation :) Looking at ZONE_DMA it looks like it is still covering
the whole RAM range (/proc/zoneinfo shows start_pfn=0 in zone DMA), so, I
don't see why 0x3000 should be excluded now.
So, is using the .needs_bounce() method the correct way to support DMA on
this arch or is there a better one?
Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
^ permalink raw reply
* [PATCH 1/2] usb: dwc3: core: continue probing if usb phy library returns -ENODEV/-ENXIO
From: Heikki Krogerus @ 2014-01-27 15:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140121144725.GF30451@saruman.home>
Hi Felipe,
On Tue, Jan 21, 2014 at 08:47:25AM -0600, Felipe Balbi wrote:
> On Tue, Jan 21, 2014 at 03:41:38PM +0530, Kishon Vijay Abraham I wrote:
> > Since PHYs for dwc3 is optional (not all SoCs that have DWC3 use PHYs),
> > do not return from probe if the USB PHY library returns -ENODEV as that
>
> this isn't correct, they all have PHYs, some of them might not be
> controllable.
>
> > indicates the platform does not have PHY.
>
> not really, that indicates the current platform tried to grab a PHY and
> the PHY doesn't exist. If there's anybody with a non-controllable PHY
> and someone gives me a really good reason for not using the generic
> no-op PHY, then we should add a flag and we could:
>
> if (!likely(dwc->flags & DWC3_USB2PHY_DRIVER_NOT_NEEDED))
> dwc3_grab_phys(dwc);
Why would you need to know if the PHY drivers are needed or not
explicitly in your controller driver?
> But I really want to see the argument against using no-op. As far as I
> could see, everybody needs a PHY driver one way or another, some
> platforms just haven't sent any PHY driver upstream and have their own
> hacked up solution to avoid using the PHY layer.
Not true in our case. Platforms using Intel's SoCs and chip sets may
or may not have controllable USB PHY. Quite often they don't. The
Baytrails have usually ULPI PHY for USB2, but that does not mean they
provide any vendor specific functions or any need for a driver in any
case.
Are we talking about the old USB PHY library or the new PHY framework
with the no-op PHY driver?
Well, in any case, I don't understand what is the purpose of the no-op
PHY driver. What are you drying to achieve with that?
Thanks,
--
heikki
^ permalink raw reply
* [PATCH 1/9] ARM: dts: imx6qdl: remove the use of pingrp macros
From: Shawn Guo @ 2014-01-27 15:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140127143745.GM15937@n2100.arm.linux.org.uk>
On Mon, Jan 27, 2014 at 02:37:45PM +0000, Russell King - ARM Linux wrote:
> On Sun, Jan 26, 2014 at 12:43:03AM +0800, Shawn Guo wrote:
> > arch/arm/boot/dts/imx6dl-hummingboard.dts | 5 +-
> > arch/arm/boot/dts/imx6qdl-microsom.dtsi | 5 +-
>
> I've merged your changes here into my local copy of these just to reduce
> the conflicts - unfortunately, it's taken soo long to deal with the above
> that the cubox-i has now been released, which has prompted some
> reorganisation between the above two files.
>
> I would much rather you dropped these two entirely, and let me push them
> upstream, rather than having some nasty conflicts which result from this.
So you're basically asking me to drop patch [1] from imx/dt branch (tag
imx-dt-3.14), which I have sent to Olof for 3.14 inclusion. Yes, I
still hope Olof can pull it with this turn-around series applied on top.
So please let's wait for Olof's word to see if we can make it. If it's
still a NO for some reason, I will be certainly fine with you pushing
hummingboard stuff upstream, and will drop it from my tree.
Shawn
[1] https://git.linaro.org/people/shawn.guo/linux-2.6.git/commit/8544f6c92801b1ba70f790cc17f543f7aa13f17f
^ permalink raw reply
* [PATCH v2 0/5] ARM: sun6i: Add support for the A31 I2C controller
From: Maxime Ripard @ 2014-01-27 15:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389609293-2824-1-git-send-email-maxime.ripard@free-electrons.com>
Hi Wolfram,
On Mon, Jan 13, 2014 at 11:34:48AM +0100, Maxime Ripard wrote:
> Hi everyone,
>
> This patchset adds support the A31 i2c controller. This is mostly the
> same controller as the one found in the other Allwinner SoCs, except
> for the interrupts acking.
>
> On the other SoCs using this driver, the interrupts are acked by
> clearing the INT_FLAG bit in the control register, while on the A31,
> the interrupt is acked by writing that bit into the control register.
>
> The other difference is that the I2C IP is maintained in reset by a
> reset controller, so we're adding optionnal support for the reset
> framework in the driver to deassert the device from reset.
Do you have any comments on this?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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* [PATCH 1/4] clk: sunxi: Add support for PLL6 on the A31
From: Maxime Ripard @ 2014-01-27 15:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140117221402.4167.78251@quantum>
Hi Mike,
On Fri, Jan 17, 2014 at 02:14:02PM -0800, Mike Turquette wrote:
> Quoting Maxime Ripard (2014-01-16 09:11:22)
> > The A31 has a slightly different PLL6 clock. Add support for this new clock in
> > our driver.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> This looks good to me. I guess it will be going in for 3.15 based on the
> comments in the coverletter.
Yes, indeed it is 3.15 materials.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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* [RFC/PATCH] ARM: dove: Remove UBI support from defconfig
From: Jason Cooper @ 2014-01-27 15:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390829189-25073-1-git-send-email-ezequiel.garcia@free-electrons.com>
On Mon, Jan 27, 2014 at 10:26:29AM -0300, Ezequiel Garcia wrote:
> As NAND support is not enabled by default, it's hard to see
> why we'd want to have UBI support. Let's remove it.
I'd rather add support for the nand.
thx,
Jason.
>
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> ---
> arch/arm/configs/dove_defconfig | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
> index 1101054..7242b11 100644
> --- a/arch/arm/configs/dove_defconfig
> +++ b/arch/arm/configs/dove_defconfig
> @@ -48,7 +48,6 @@ CONFIG_MTD_CFI_INTELEXT=y
> CONFIG_MTD_CFI_STAA=y
> CONFIG_MTD_PHYSMAP=y
> CONFIG_MTD_M25P80=y
> -CONFIG_MTD_UBI=y
> CONFIG_BLK_DEV_LOOP=y
> CONFIG_BLK_DEV_RAM=y
> CONFIG_BLK_DEV_RAM_COUNT=1
> --
> 1.8.1.5
>
^ permalink raw reply
* [PATCH] sunxi: dts: add a note that memory size is adjusted by boot loader.
From: Maxime Ripard @ 2014-01-27 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E399F4.1040300@redhat.com>
Hi Ian, Hans,
On Sat, Jan 25, 2014 at 12:03:16PM +0100, Hans de Goede wrote:
> Hmm, I've no idea what the default / preferred way of handling this is,
> I assume Maxime knows, so lets wait for his input on this.
I got the habit of setting the memory node to the max size the RAM
controller can handle from previous work on imx, but I don't really
have a preferrence here.
If that confuses people, we can just remove it from the DTSI
altogether. It will be patched by u-boot anyway, and we won't have to
create DTS variants this way.
Just don't do it for the A31 for the moment, since we don't have
DT-enabled u-boot for now.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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* [PATCH v2 2/5] clk: sunxi: Add USB clock register defintions
From: Hans de Goede @ 2014-01-27 14:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140127144349.GJ3867@lukather>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hi,
On 01/27/2014 03:43 PM, Maxime Ripard wrote:
> Hi Hans,
>
> Mostly looking good, but I have a few comments below.
>
> On Wed, Jan 22, 2014 at 10:36:24PM +0100, Hans de Goede wrote:
>> From: Roman Byshko <rbyshko@gmail.com>
>>
>> Add register definitions for the usb-clk register found on sun4i, sun5i and sun7i SoCs.
>>
>> Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- Documentation/devicetree/bindings/clock/sunxi.txt | 5 +++++ drivers/clk/sunxi/clk-sunxi.c | 12 ++++++++++++ 2 files changed, 17 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 79c7197..8bccb6a 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -37,6 +37,8 @@ Required properties: "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks "allwinner,sun7i-a20-out-clk" - for the external output clocks + "allwinner,sun4i-usb-gates-clk" - for usb gates + resets on A10 / A20 +
>> "allwinner,sun5i-a13-usb-gates-clk" - for usb gates + resets on A13
>
> Maybe we can just remove the gates from there? Even though they are gates, they are also (a bit) more than that.
To be clear you mean s/usb-gates-clk/usb-clk/ right ?
That sounds reasonable :)
>
>> Required properties for all clocks: - reg : shall be the control register address for the clock. @@ -49,6 +51,9 @@ Required properties for all clocks: Additionally, "allwinner,*-gates-clk" clocks require: - clock-output-names : the corresponding gate names that the clock controls
>>
>> +And "allwinner,*-usb-gates-clk" clocks also require: +- reset-cells : shall be set to 1 +
>
> You should also document what value we should put in the cells, and where to refer to to find the right one.
Ok.
>
>> Clock consumers should specify the desired clocks they use with a "clocks" phandle cell. Consumers that are using a gated clock should provide an additional ID in their clock property. This ID is the diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index f1a147c..18cbc3c 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -813,6 +813,16 @@ static const struct gates_data sun4i_ahb_gates_data __initconst = { .mask = {0x7F77FFF, 0x14FB3F}, };
>>
>> +static const struct gates_data sun4i_usb_gates_data __initconst = { + .mask = {0x1C0}, + .reset_mask = 0x07, +}; + +static const struct gates_data sun5i_a13_usb_gates_data __initconst = { + .mask = {0x140}, + .reset_mask = 0x03, +}; +
>
> I guess that means that we will have the OHCI0 gate declared with <&...-gates-clk 6>, while it's actually the first gate for this clock?
Correct.
> Maybe introducing an offset field in the gates_data would be a good idea, so that we always start from indexing the gates from 0 in the DT?
Well for the other "gates" type clks we also have holes in the range, and
we always refer to the clk with the bit number in the reg as the clock-cell
value.
Here the hole just happens to be at the start, but it seems best to me
to be consistent and keep using the bit nr inside the reg as clock-cell
value, without an offset.
>
>> static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = { .mask = {0x147667e7, 0x185915}, }; @@ -1159,6 +1169,8 @@ static const struct of_device_id clk_gates_match[] __initconst = { {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,}, {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,}, {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,}, + {.compatible = "allwinner,sun4i-usb-gates-clk", .data = &sun4i_usb_gates_data,}, + {.compatible =
>> "allwinner,sun5i-a13-usb-gates-clk", .data = &sun5i_a13_usb_gates_data,}, {} };
>
> Thanks a lot! Maxime
Regards,
Hans
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* [PATCH v4 00/18] Armada 370/XP watchdog support
From: Ezequiel Garcia @ 2014-01-27 14:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E19A44.7040308@gmail.com>
Hi Sebastian,
On Thu, Jan 23, 2014 at 11:40:04PM +0100, Sebastian Hesselbarth wrote:
> On 01/23/2014 12:04 AM, Ezequiel Garcia wrote:
> > After some lengthy discussion on the [v2] and [v3] patchsets, here's a new
> > round. I hope I haven't forgotten anything.
> >
>
> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>
As currently Dove doesn't have watchdog support in the devicetree, I've added
it to the v5 (which I'll submit now) with your Tested-by on all the patchset.
Thanks a lot for the test,
--
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2 1/6] audit: Enable arm64 support
From: Catalin Marinas @ 2014-01-27 14:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E5EAC1.2070306@linaro.org>
On Mon, Jan 27, 2014 at 05:12:33AM +0000, AKASHI Takahiro wrote:
> [To audit maintainers]
>
> On 01/23/2014 11:18 PM, Catalin Marinas wrote:
> > On Fri, Jan 17, 2014 at 08:13:14AM +0000, AKASHI Takahiro wrote:
> >> --- a/include/uapi/linux/audit.h
> >> +++ b/include/uapi/linux/audit.h
> >> @@ -327,6 +327,8 @@ enum {
> >> /* distinguish syscall tables */
> >> #define __AUDIT_ARCH_64BIT 0x80000000
> >> #define __AUDIT_ARCH_LE 0x40000000
> >> +#define AUDIT_ARCH_AARCH64 (EM_AARCH64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
> >> +#define AUDIT_ARCH_AARCH64EB (EM_AARCH64|__AUDIT_ARCH_64BIT)
> >> #define AUDIT_ARCH_ALPHA (EM_ALPHA|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
> >> #define AUDIT_ARCH_ARM (EM_ARM|__AUDIT_ARCH_LE)
> >> #define AUDIT_ARCH_ARMEB (EM_ARM)
> >> diff --git a/init/Kconfig b/init/Kconfig
> >> index 79383d3..3aae602 100644
> >> --- a/init/Kconfig
> >> +++ b/init/Kconfig
> >> @@ -284,7 +284,7 @@ config AUDIT
> >>
> >> config AUDITSYSCALL
> >> bool "Enable system-call auditing support"
> >> - depends on AUDIT && (X86 || PARISC || PPC || S390 || IA64 || UML || SPARC64 || SUPERH || (ARM && AEABI && !OABI_COMPAT))
> >> + depends on AUDIT && (X86 || PARISC || PPC || S390 || IA64 || UML || SPARC64 || SUPERH || (ARM && AEABI && !OABI_COMPAT) || ARM64)
> >
> > The usual comment for such changes: could you please clean this up and
> > just use something like "depends on HAVE_ARCH_AUDITSYSCALL"?
>
> Do you agree to this change?
>
> If so, I can create a patch, but have some concerns:
> 1) I can't verify it on other architectures than (arm &) arm64.
You could try to build. It's really a trivial change, could get away
with code inspection (and some automatic building when it gets to
linux-next).
In init/Kconfig:
config HAVE_ARCH_AUDITSYSCALL
bool
and:
- depends on AUDIT && (X86 || PARISC || PPC || S390 || IA64 || UML || SPARC64 || SUPERH || (ARM && AEABI && !OABI_COMPAT))
+ depends on HAVE_ARCH_AUDITSYSCALL
In the corresponding arch/*/Kconfig:
select HAVE_ARCH_AUDITSYSCALL
> 2) Some architectures (microblaze, mips, openrisc) are not listed here, but
For those, you don't need to select HAVE_ARCH_AUDITSYSCALL.
> their ptrace.c have a call to audit_syscall_entry/exit().
> (audit_syscall_entry/exit are null if !AUDITSYSCALL, though)
They are not NULL but empty inline functions, so they don't have any
effect.
> So I'm afraid that the change might break someone's assumption.
I'm pretty sure it won't ;).
--
Catalin
^ permalink raw reply
* [PATCH v2 0/5] clk: sunxi: Add support for USB clocks and reset bits
From: Maxime Ripard @ 2014-01-27 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390426587-16287-1-git-send-email-hdegoede@redhat.com>
On Wed, Jan 22, 2014 at 10:36:22PM +0100, Hans de Goede wrote:
> Hi Emilio, Maxime, et al,
>
> Emilio, here is v2 of my patch-set adding support for sunxi-clk USB clocks and
> reset bits. This addresses all your review comments from v1.
>
> Can you add the first 2 patches to your queue of patches for Mike for 3.15 ?
>
> Maxime, can you add patch 3-5 which add the dt bindings for this to your
> tree please ?
Apart from the comments I had on patch 2, it looks good for me. Once
we agree on something, you have my Acked-by.
Thanks for working on this!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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* [PATCH 05/11] pinctrl: mvebu: fix misdesigned resource allocation
From: Thomas Petazzoni @ 2014-01-27 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390674856-4993-6-git-send-email-sebastian.hesselbarth@gmail.com>
Dear Sebastian Hesselbarth,
On Sat, 25 Jan 2014 19:34:10 +0100, Sebastian Hesselbarth wrote:
> Allocating the pinctrl resource in common pinctrl-mvebu was a misdesign,
> as it does not allow SoC specific parts to access the allocated resource.
> This moves resource allocation from mvebu_pinctrl_probe to SoC specific
> _probe functions and passes the base address to common pinctrl driver
> instead.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
I definitely agree with that: I had the same problem several months ago
when I started doing the pinctrl driver for Orion5x, which has a
non-linear MPP register set.
However, I'd like this to go a little bit further if possible. See
below.
> - return mvebu_pinctrl_probe(pdev);
> + return mvebu_pinctrl_probe(pdev, base);
I think there is no need to pass "base" to mvebu_pinctrl_probe(). The
only reason we have this is because the base gets stored in the
mvebu_pinctrl structure so that the mvebu_common_mpp_get() and
mvebu_common_mpp_set() functions that are the default behavior
for mvebu_pinconf_group_get() and mvebu_pinconf_group_set() work
properly.
Shouldn't we turn these functions mvebu_common_mpp_get() and
mvebu_common_mpp_set() into helper functions, accessible from the
per-SoC pinctrl drivers, so that they can easily implement their
->mpp_get() and ->mpp_set() callbacks?
This way, the "base" thing is completely owned by the per-SoC driver,
which would be more logical I believe.
Thanks!
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2 2/5] clk: sunxi: Add USB clock register defintions
From: Maxime Ripard @ 2014-01-27 14:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390426587-16287-3-git-send-email-hdegoede@redhat.com>
Hi Hans,
Mostly looking good, but I have a few comments below.
On Wed, Jan 22, 2014 at 10:36:24PM +0100, Hans de Goede wrote:
> From: Roman Byshko <rbyshko@gmail.com>
>
> Add register definitions for the usb-clk register found on sun4i, sun5i and
> sun7i SoCs.
>
> Signed-off-by: Roman Byshko <rbyshko@gmail.com>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 5 +++++
> drivers/clk/sunxi/clk-sunxi.c | 12 ++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 79c7197..8bccb6a 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -37,6 +37,8 @@ Required properties:
> "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
> "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
> "allwinner,sun7i-a20-out-clk" - for the external output clocks
> + "allwinner,sun4i-usb-gates-clk" - for usb gates + resets on A10 / A20
> + "allwinner,sun5i-a13-usb-gates-clk" - for usb gates + resets on A13
Maybe we can just remove the gates from there? Even though they are
gates, they are also (a bit) more than that.
> Required properties for all clocks:
> - reg : shall be the control register address for the clock.
> @@ -49,6 +51,9 @@ Required properties for all clocks:
> Additionally, "allwinner,*-gates-clk" clocks require:
> - clock-output-names : the corresponding gate names that the clock controls
>
> +And "allwinner,*-usb-gates-clk" clocks also require:
> +- reset-cells : shall be set to 1
> +
You should also document what value we should put in the cells, and
where to refer to to find the right one.
> Clock consumers should specify the desired clocks they use with a
> "clocks" phandle cell. Consumers that are using a gated clock should
> provide an additional ID in their clock property. This ID is the
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index f1a147c..18cbc3c 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -813,6 +813,16 @@ static const struct gates_data sun4i_ahb_gates_data __initconst = {
> .mask = {0x7F77FFF, 0x14FB3F},
> };
>
> +static const struct gates_data sun4i_usb_gates_data __initconst = {
> + .mask = {0x1C0},
> + .reset_mask = 0x07,
> +};
> +
> +static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
> + .mask = {0x140},
> + .reset_mask = 0x03,
> +};
> +
I guess that means that we will have the OHCI0 gate declared with
<&...-gates-clk 6>, while it's actually the first gate for this clock?
Maybe introducing an offset field in the gates_data would be a good
idea, so that we always start from indexing the gates from 0 in the DT?
> static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
> .mask = {0x147667e7, 0x185915},
> };
> @@ -1159,6 +1169,8 @@ static const struct of_device_id clk_gates_match[] __initconst = {
> {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
> {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
> {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
> + {.compatible = "allwinner,sun4i-usb-gates-clk", .data = &sun4i_usb_gates_data,},
> + {.compatible = "allwinner,sun5i-a13-usb-gates-clk", .data = &sun5i_a13_usb_gates_data,},
> {}
> };
Thanks a lot!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 0/4] clk: mvebu: fix clk init order
From: Thomas Petazzoni @ 2014-01-27 14:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390673950-4521-1-git-send-email-sebastian.hesselbarth@gmail.com>
Dear Sebastian Hesselbarth,
On Sat, 25 Jan 2014 19:19:06 +0100, Sebastian Hesselbarth wrote:
> This patch set fixes clk init order that went upside-down with
> v3.14. I haven't really investigated what caused this, but I assume
> it is related with DT node reordering by addresses.
>
> Anyway, with v3.14 for MVEBU SoCs, the clock gating driver gets
> registered before core clocks driver. Unfortunately, we cannot
> return -EPROBE_DEFER in drivers initialized by clk_of_init. As the
> init order for our drivers is always core clocks before clock gating,
> we maintain init order ourselves by hooking CLK_OF_DECLARE to one
> init function that will register core clocks before clock gating
> driver.
>
> This patch is based on pre-v3.14-rc1 mainline and should go in as
> fixes for it. As we now send MVEBU clk pull-requests to Mike directly,
> I suggest Jason picks it up as a topic branch.
I'm not sure I really like the solution you're proposing here. I'd very
much prefer to keep one CLK_OF_DECLARE() per clock type, associated to
one function registering only this clock type.
Instead, shouldn't the clock framework be improved to *not* register a
clock until its parent have been registered? If the DT you have the
gatable clocks that depend on the core clocks, then the gatable clocks
should not be registered if the core clocks have not yet been
registered.
Do you think this is possible? Am I missing something here?
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH 1/9] ARM: dts: imx6qdl: remove the use of pingrp macros
From: Russell King - ARM Linux @ 2014-01-27 14:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390668191-20289-2-git-send-email-shawn.guo@linaro.org>
On Sun, Jan 26, 2014 at 12:43:03AM +0800, Shawn Guo wrote:
> arch/arm/boot/dts/imx6dl-hummingboard.dts | 5 +-
> arch/arm/boot/dts/imx6qdl-microsom.dtsi | 5 +-
I've merged your changes here into my local copy of these just to reduce
the conflicts - unfortunately, it's taken soo long to deal with the above
that the cubox-i has now been released, which has prompted some
reorganisation between the above two files.
I would much rather you dropped these two entirely, and let me push them
upstream, rather than having some nasty conflicts which result from this.
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* [PATCH v5 07/14] ahci-platform: "Library-ise" ahci_probe functionality
From: Roger Quadros @ 2014-01-27 14:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E642F7.3000308@redhat.com>
On 01/27/2014 01:28 PM, Hans de Goede wrote:
> Hi,
>
> On 01/27/2014 12:03 PM, Roger Quadros wrote:
>> On 01/27/2014 12:51 PM, Hans de Goede wrote:
>>> Hi,
>>>
>>> On 01/27/2014 11:39 AM, Roger Quadros wrote:
>>>> Hi,
>>>>
>>>> On 01/22/2014 09:04 PM, Hans de Goede wrote:
>>>
>>> <snip>
>>>
>>>>> --- a/include/linux/ahci_platform.h
>>>>> +++ b/include/linux/ahci_platform.h
>>>>> @@ -20,7 +20,13 @@
>>>>> struct device;
>>>>> struct ata_port_info;
>>>>> struct ahci_host_priv;
>>>>> +struct platform_device;
>>>>>
>>>>> +/*
>>>>> + * Note ahci_platform_data is deprecated. New drivers which need to override
>>>>> + * any of these, should instead declare there own platform_driver struct, and
>>>>> + * use ahci_platform* functions in their own probe, suspend and resume methods.
>>>>> + */
>>>>> struct ahci_platform_data {
>>>>> int (*init)(struct device *dev, struct ahci_host_priv *hpriv);
>>>>> void (*exit)(struct device *dev);
>>>>> @@ -35,5 +41,13 @@ int ahci_platform_enable_clks(struct ahci_host_priv *hpriv);
>>>>> void ahci_platform_disable_clks(struct ahci_host_priv *hpriv);
>>>>> int ahci_platform_enable_resources(struct ahci_host_priv *hpriv);
>>>>> void ahci_platform_disable_resources(struct ahci_host_priv *hpriv);
>>>>> +struct ahci_host_priv *ahci_platform_get_resources(
>>>>> + struct platform_device *pdev);
>>>>
>>>> Why not use 'struct device' as the argument?
>>>
>>> Because of calls to platform_get_resource inside the function.
>>>
>>>>> +void ahci_platform_put_resources(struct ahci_host_priv *hpriv);
>>>>
>>>> Can we have 'struct device' as the argument? Else it becomes
>>>> impossible to get 'struct device' from 'hpriv' if we need to call e.g.
>>>> pm_runtime_*() APIs.
>>>
>>> The plan for is for this function to go away once we have a
>>> devm version of of_clk_get, so if you need to put pm_runtime_calls
>>> somewhere, please don't put them here. This sounds like something which
>>> should go in enable / disable resources instead ?
>>
>> OK. I need to add pm_runtime_enable() + pm_runtime_get_sync() during
>> initialization and pm_runtime_put_sync() + pm_runtime_disable() during cleanup.
>
> Note that enable / disable resources will get called by (the default implementations
> of) suspend / resume too.
>
> If that is undesirable then I take back what I said before and
> ahci_platform_put_resources' prototype should be changed to:
>
> void ahci_platform_put_resources(struct device *dev, struct ahci_host_priv *hpriv);
>
> And we will need to keep it around even after we get devm_of_clk_get.
>
>> If ahci_platform_enable/disable_resources is the right place then we must be
>> able to access struct device from there.
>
> Right, and if not we need to access it from ahci_platform_put_resources(),
> which is in essence the same problem.
>
>> Is it a good to add 'struct device *dev' into the 'struct ahci_host_priv'?
>> Then you can leave this series as is and i'll add a new patch for that.
>
> Normally we get a device * as argument, and get to hpriv like this:
>
> struct ata_host *host = dev_get_drvdata(dev);
> struct ahci_host_priv *hpriv = host->private_data;
>
> So having a dev * in hpriv is normally not useful.
>
> But the ata_host gets allocated after the first ahci_platform_enable_resources
> call, so we cannot use this there. Likewise disable_resources / put_resources
> is used in error handling paths in probe where we don't have an ata_host yet,
> so my vote goes to adding a "struct device *dev" as first argument, like I
> suggested above for ahci_platform_put_resources.
>
> This can be done as an add-on patch (if you do don't forget to also fix
> ahci_sunxi.c and ahci_imx.c), or I can respin my series to have this from
> day one.
>
> If you want me to do a respin, please let me know which fix you'll need
> (the put_resources or the enable/disable one).
>
For now I'm using get/put_resources to enable runtime PM and enable the device
like in the below patch.
I'll make the necessary changes to ahci_platform_put_resources();
cheers,
-roger
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index 5ec6fe6..965f4b4 100644
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -23,6 +23,7 @@
#include <linux/platform_device.h>
#include <linux/libata.h>
#include <linux/ahci_platform.h>
+#include <linux/pm_runtime.h>
#include "ahci.h"
static void ahci_host_stop(struct ata_host *host);
@@ -233,6 +234,9 @@ struct ahci_host_priv *ahci_platform_get_resources(
}
}
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
return hpriv;
free_clk:
@@ -246,6 +250,9 @@ void ahci_platform_put_resources(struct ahci_host_priv *hpriv)
{
int c;
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
+
for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++)
clk_put(hpriv->clks[c]);
}
@@ -478,6 +485,11 @@ int ahci_platform_resume(struct device *dev)
if (rc)
goto disable_resources;
+ /* We resumed so update PM runtime state */
+ pm_runtime_disable(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
return 0;
disable_resources:
^ permalink raw reply related
* [PATCH RFC 4/6] net: rfkill: gpio: add device tree support
From: Maxime Ripard @ 2014-01-27 14:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389941251-32692-5-git-send-email-wens@csie.org>
Hi,
On Fri, Jan 17, 2014 at 02:47:29PM +0800, Chen-Yu Tsai wrote:
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> .../devicetree/bindings/rfkill/rfkill-gpio.txt | 26 ++++++++++++++++++++++
> net/rfkill/rfkill-gpio.c | 23 +++++++++++++++++++
> 2 files changed, 49 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
>
> diff --git a/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt b/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
> new file mode 100644
> index 0000000..8a07ea4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rfkill/rfkill-gpio.txt
> @@ -0,0 +1,26 @@
> +GPIO controlled RFKILL devices
> +
> +Required properties:
> +- compatible : Must be "rfkill-gpio".
> +- rfkill-name : Name of RFKILL device
> +- rfkill-type : Type of RFKILL device: 1 for WiFi, 2 for BlueTooth
> +- NAME_shutdown-gpios : GPIO phandle to shutdown control
> + (phandle must be the second)
Can't it be handled by a regulator?
> +- NAME_reset-gpios : GPIO phandle to reset control
And this one using the reset framework?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 2/2] dmaengine: at_hdmac: run callback function with no lock held nor interrupts disabled
From: Nicolas Ferre @ 2014-01-27 14:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1390832343.git.nicolas.ferre@atmel.com>
Now, submission from callbacks are permitted as per dmaengine framework. So we
shouldn't hold any spinlock nor disable IRQs while calling callbacks.
As locks were taken by parent routines, spin_lock_irqsave() has to be called
inside all routines, wherever they are required.
The little used atc_issue_pending() function is made void.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
drivers/dma/at_hdmac.c | 121 +++++++++++++++++++++++++++++--------------------
1 file changed, 71 insertions(+), 50 deletions(-)
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index b28759b6d1ca..f7bf4065636c 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -268,10 +268,14 @@ static struct at_desc *atc_get_current_descriptors(struct at_dma_chan *atchan,
static int atc_get_bytes_left(struct dma_chan *chan)
{
struct at_dma_chan *atchan = to_at_dma_chan(chan);
- struct at_desc *desc_first = atc_first_active(atchan);
+ struct at_desc *desc_first;
struct at_desc *desc_cur;
+ unsigned long flags;
int ret = 0, count = 0;
+ spin_lock_irqsave(&atchan->lock, flags);
+ desc_first = atc_first_active(atchan);
+
/*
* Initialize necessary values in the first time.
* remain_desc record remain desc length.
@@ -311,6 +315,7 @@ static int atc_get_bytes_left(struct dma_chan *chan)
}
out:
+ spin_unlock_irqrestore(&atchan->lock, flags);
return ret;
}
@@ -318,12 +323,14 @@ out:
* atc_chain_complete - finish work for one transaction chain
* @atchan: channel we work on
* @desc: descriptor at the head of the chain we want do complete
- *
- * Called with atchan->lock held and bh disabled */
+ */
static void
atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
{
struct dma_async_tx_descriptor *txd = &desc->txd;
+ unsigned long flags;
+
+ spin_lock_irqsave(&atchan->lock, flags);
dev_vdbg(chan2dev(&atchan->chan_common),
"descriptor %u complete\n", txd->cookie);
@@ -337,6 +344,8 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
/* move myself to free_list */
list_move(&desc->desc_node, &atchan->free_list);
+ spin_unlock_irqrestore(&atchan->lock, flags);
+
dma_descriptor_unmap(txd);
/* for cyclic transfers,
* no need to replay callback function while stopping */
@@ -344,10 +353,6 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
dma_async_tx_callback callback = txd->callback;
void *param = txd->callback_param;
- /*
- * The API requires that no submissions are done from a
- * callback, so we don't need to drop the lock here
- */
if (callback)
callback(param);
}
@@ -362,15 +367,17 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
* Eventually submit queued descriptors if any
*
* Assume channel is idle while calling this function
- * Called with atchan->lock held and bh disabled
*/
static void atc_complete_all(struct at_dma_chan *atchan)
{
struct at_desc *desc, *_desc;
LIST_HEAD(list);
+ unsigned long flags;
dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n");
+ spin_lock_irqsave(&atchan->lock, flags);
+
/*
* Submit queued descriptors ASAP, i.e. before we go through
* the completed ones.
@@ -382,6 +389,8 @@ static void atc_complete_all(struct at_dma_chan *atchan)
/* empty queue list by moving descriptors (if any) to active_list */
list_splice_init(&atchan->queue, &atchan->active_list);
+ spin_unlock_irqrestore(&atchan->lock, flags);
+
list_for_each_entry_safe(desc, _desc, &list, desc_node)
atc_chain_complete(atchan, desc);
}
@@ -389,23 +398,35 @@ static void atc_complete_all(struct at_dma_chan *atchan)
/**
* atc_advance_work - at the end of a transaction, move forward
* @atchan: channel where the transaction ended
- *
- * Called with atchan->lock held and bh disabled
*/
static void atc_advance_work(struct at_dma_chan *atchan)
{
+ unsigned long flags;
+
dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");
- if (atc_chan_is_enabled(atchan))
+ spin_lock_irqsave(&atchan->lock, flags);
+
+ if (atc_chan_is_enabled(atchan)) {
+ spin_unlock_irqrestore(&atchan->lock, flags);
return;
+ }
if (list_empty(&atchan->active_list) ||
list_is_singular(&atchan->active_list)) {
+ spin_unlock_irqrestore(&atchan->lock, flags);
atc_complete_all(atchan);
} else {
- atc_chain_complete(atchan, atc_first_active(atchan));
+ struct at_desc *desc_first = atc_first_active(atchan);
+
+ spin_unlock_irqrestore(&atchan->lock, flags);
+ atc_chain_complete(atchan, desc_first);
+ barrier();
/* advance work */
- atc_dostart(atchan, atc_first_active(atchan));
+ spin_lock_irqsave(&atchan->lock, flags);
+ desc_first = atc_first_active(atchan);
+ atc_dostart(atchan, desc_first);
+ spin_unlock_irqrestore(&atchan->lock, flags);
}
}
@@ -413,13 +434,14 @@ static void atc_advance_work(struct at_dma_chan *atchan)
/**
* atc_handle_error - handle errors reported by DMA controller
* @atchan: channel where error occurs
- *
- * Called with atchan->lock held and bh disabled
*/
static void atc_handle_error(struct at_dma_chan *atchan)
{
struct at_desc *bad_desc;
struct at_desc *child;
+ unsigned long flags;
+
+ spin_lock_irqsave(&atchan->lock, flags);
/*
* The descriptor currently at the head of the active list is
@@ -452,6 +474,8 @@ static void atc_handle_error(struct at_dma_chan *atchan)
list_for_each_entry(child, &bad_desc->tx_list, desc_node)
atc_dump_lli(atchan, &child->lli);
+ spin_unlock_irqrestore(&atchan->lock, flags);
+
/* Pretend the descriptor completed successfully */
atc_chain_complete(atchan, bad_desc);
}
@@ -459,19 +483,27 @@ static void atc_handle_error(struct at_dma_chan *atchan)
/**
* atc_handle_cyclic - at the end of a period, run callback function
* @atchan: channel used for cyclic operations
- *
- * Called with atchan->lock held and bh disabled
*/
static void atc_handle_cyclic(struct at_dma_chan *atchan)
{
- struct at_desc *first = atc_first_active(atchan);
- struct dma_async_tx_descriptor *txd = &first->txd;
- dma_async_tx_callback callback = txd->callback;
- void *param = txd->callback_param;
+ struct at_desc *first;
+ struct dma_async_tx_descriptor *txd;
+ dma_async_tx_callback callback;
+ void *param;
+ u32 dscr;
+ unsigned long flags;
+
+ spin_lock_irqsave(&atchan->lock, flags);
+ first = atc_first_active(atchan);
+ dscr = channel_readl(atchan, DSCR);
+ spin_unlock_irqrestore(&atchan->lock, flags);
+
+ txd = &first->txd;
+ callback = txd->callback;
+ param = txd->callback_param;
dev_vdbg(chan2dev(&atchan->chan_common),
- "new cyclic period llp 0x%08x\n",
- channel_readl(atchan, DSCR));
+ "new cyclic period llp 0x%08x\n", dscr);
if (callback)
callback(param);
@@ -482,17 +514,13 @@ static void atc_handle_cyclic(struct at_dma_chan *atchan)
static void atc_tasklet(unsigned long data)
{
struct at_dma_chan *atchan = (struct at_dma_chan *)data;
- unsigned long flags;
- spin_lock_irqsave(&atchan->lock, flags);
if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
atc_handle_error(atchan);
else if (atc_chan_is_cyclic(atchan))
atc_handle_cyclic(atchan);
else
atc_advance_work(atchan);
-
- spin_unlock_irqrestore(&atchan->lock, flags);
}
static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
@@ -1013,6 +1041,11 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
spin_unlock_irqrestore(&atchan->lock, flags);
} else if (cmd == DMA_TERMINATE_ALL) {
struct at_desc *desc, *_desc;
+
+ /* Disable interrupts */
+ atc_disable_chan_irq(atdma, chan->chan_id);
+ tasklet_disable(&atchan->tasklet);
+
/*
* This is only called when something went wrong elsewhere, so
* we don't really care about the data. Just disable the
@@ -1033,14 +1066,22 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
list_splice_init(&atchan->active_list, &list);
/* Flush all pending and queued descriptors */
- list_for_each_entry_safe(desc, _desc, &list, desc_node)
+ list_for_each_entry_safe(desc, _desc, &list, desc_node) {
+ spin_unlock_irqrestore(&atchan->lock, flags);
atc_chain_complete(atchan, desc);
+ spin_lock_irqsave(&atchan->lock, flags);
+ }
clear_bit(ATC_IS_PAUSED, &atchan->status);
/* if channel dedicated to cyclic operations, free it */
clear_bit(ATC_IS_CYCLIC, &atchan->status);
spin_unlock_irqrestore(&atchan->lock, flags);
+
+ /* Re-enable channel for future operations */
+ tasklet_enable(&atchan->tasklet);
+ atc_enable_chan_irq(atdma, chan->chan_id);
+
} else if (cmd == DMA_SLAVE_CONFIG) {
return set_runtime_config(chan, (struct dma_slave_config *)arg);
} else {
@@ -1065,8 +1106,6 @@ atc_tx_status(struct dma_chan *chan,
dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
- struct at_dma_chan *atchan = to_at_dma_chan(chan);
- unsigned long flags;
enum dma_status ret;
int bytes = 0;
@@ -1080,13 +1119,9 @@ atc_tx_status(struct dma_chan *chan,
if (!txstate)
return DMA_ERROR;
- spin_lock_irqsave(&atchan->lock, flags);
-
/* Get number of bytes left in the active transactions */
bytes = atc_get_bytes_left(chan);
- spin_unlock_irqrestore(&atchan->lock, flags);
-
if (unlikely(bytes < 0)) {
dev_vdbg(chan2dev(chan), "get residual bytes error\n");
return DMA_ERROR;
@@ -1101,24 +1136,10 @@ atc_tx_status(struct dma_chan *chan,
}
/**
- * atc_issue_pending - try to finish work
+ * atc_issue_pending - void function
* @chan: target DMA channel
*/
-static void atc_issue_pending(struct dma_chan *chan)
-{
- struct at_dma_chan *atchan = to_at_dma_chan(chan);
- unsigned long flags;
-
- dev_vdbg(chan2dev(chan), "issue_pending\n");
-
- /* Not needed for cyclic transfers */
- if (atc_chan_is_cyclic(atchan))
- return;
-
- spin_lock_irqsave(&atchan->lock, flags);
- atc_advance_work(atchan);
- spin_unlock_irqrestore(&atchan->lock, flags);
-}
+static void atc_issue_pending(struct dma_chan *chan) {}
/**
* atc_alloc_chan_resources - allocate resources for DMA channel
--
1.8.2.2
^ permalink raw reply related
* [PATCH 1/2] dmaengine: at_hdmac: remove the call to issue_pending from tx_status
From: Nicolas Ferre @ 2014-01-27 14:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1390832343.git.nicolas.ferre@atmel.com>
Triggering the dmaengine from tx_status call seems awkward.
If data are remaining in the DMA FIFO, the normal operations
should drain them anyway.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
drivers/dma/at_hdmac.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index e2c04dc81e2a..b28759b6d1ca 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -268,8 +268,6 @@ static struct at_desc *atc_get_current_descriptors(struct at_dma_chan *atchan,
static int atc_get_bytes_left(struct dma_chan *chan)
{
struct at_dma_chan *atchan = to_at_dma_chan(chan);
- struct at_dma *atdma = to_at_dma(chan->device);
- int chan_id = atchan->chan_common.chan_id;
struct at_desc *desc_first = atc_first_active(atchan);
struct at_desc *desc_cur;
int ret = 0, count = 0;
@@ -311,11 +309,6 @@ static int atc_get_bytes_left(struct dma_chan *chan)
<< (desc_first->tx_width);
ret = atchan->remain_desc - count;
}
- /*
- * Check fifo empty.
- */
- if (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id)))
- atc_issue_pending(chan);
out:
return ret;
--
1.8.2.2
^ permalink raw reply related
* [RFC PATCH 0/2] dmaengine: at_hdmac: fix locking according to slave DMA requirements
From: Nicolas Ferre @ 2014-01-27 14:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <C9F8415089354E4FB76F4548B3515AF484286F61@edb1.wapice.localdomain>
Hi,
This is an attempt to solve the locking issue that we currently have with the
Atmel at_hdmac dmaengine driver.
I tested these patches with several drivers but may need more coverage before
making them permanent...
Comments welcome.
Nicolas Ferre (2):
dmaengine: at_hdmac: remove the call to issue_pending from tx_status
dmaengine: at_hdmac: run callback function with no lock held nor
interrupts disabled
drivers/dma/at_hdmac.c | 128 +++++++++++++++++++++++++++----------------------
1 file changed, 71 insertions(+), 57 deletions(-)
--
1.8.2.2
^ permalink raw reply
* [PATCH V7 2/2] ARM: dts: Enable ahci sata and sata phy
From: Yuvaraj Kumar C D @ 2014-01-27 14:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390832366-23454-1-git-send-email-yuvaraj.cd@samsung.com>
This patch adds dt entry for ahci sata controller and its
corresponding phy controller.phy node has been added w.r.t
new generic phy framework.
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
---
Changes since V6:none
Changes since V5:none
Changes since V4:
1.Used the new phandle "sata_phy_i2c" in the DT entry.
2.Updated binding document.
Changes since V3:
1.Moved the binding info to the /bindings/phy/
Changes since V2:
1.Used syscon interface to PMU handling.
2.Changed "sata-phy-i2c" to "exynos-sataphy-i2c".
Changes since V1:
1.Minor changes to node name convention.
2.Updated binding document.
.../devicetree/bindings/ata/exynos-sata-phy.txt | 14 --------
.../devicetree/bindings/ata/exynos-sata.txt | 25 +++++++++-----
.../devicetree/bindings/phy/samsung-phy.txt | 36 ++++++++++++++++++++
arch/arm/boot/dts/exynos5250-arndale.dts | 11 ++++++
arch/arm/boot/dts/exynos5250-smdk5250.dts | 8 ++---
arch/arm/boot/dts/exynos5250.dtsi | 17 ++++++---
6 files changed, 78 insertions(+), 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
deleted file mode 100644
index 37824fa..0000000
--- a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Samsung SATA PHY Controller
-
-SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
-Each SATA PHY controller should have its own node.
-
-Required properties:
-- compatible : compatible list, contains "samsung,exynos5-sata-phy"
-- reg : <registers mapping>
-
-Example:
- sata at ffe07000 {
- compatible = "samsung,exynos5-sata-phy";
- reg = <0xffe07000 0x1000>;
- };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
index 0849f10..b2adb1f 100644
--- a/Documentation/devicetree/bindings/ata/exynos-sata.txt
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -4,14 +4,21 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
-- compatible : compatible list, contains "samsung,exynos5-sata"
-- interrupts : <interrupt mapping for SATA IRQ>
-- reg : <registers mapping>
-- samsung,sata-freq : <frequency in MHz>
+- compatible : compatible list, contains "samsung,exynos5-sata"
+- interrupts : <interrupt mapping for SATA IRQ>
+- reg : <registers mapping>
+- samsung,sata-freq : <frequency in MHz>
+- phys : as mentioned in phy-bindings.txt
+- phy-names : as mentioned in phy-bindings.txt
Example:
- sata at ffe08000 {
- compatible = "samsung,exynos5-sata";
- reg = <0xffe08000 0x1000>;
- interrupts = <115>;
- };
+ sata at 122f0000 {
+ compatible = "snps,dwc-ahci";
+ samsung,sata-freq = <66>;
+ reg = <0x122f0000 0x1ff>;
+ interrupts = <0 115 0>;
+ clocks = <&clock 277>, <&clock 143>;
+ clock-names = "sata", "sclk_sata";
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+ };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa..a937f75 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,39 @@ Required properties:
- compatible : should be "samsung,exynos5250-dp-video-phy";
- reg : offset and length of the Display Port PHY register set;
- #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung SATA PHY Controller
+---------------------------
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible : compatible list, contains "samsung,exynos5250-sata-phy"
+- reg : offset and length of the SATA PHY register set;
+- #phy-cells : from the generic phy bindings;
+
+Example:
+ sata_phy: sata-phy at 12170000 {
+ compatible = "samsung,exynos5250-sata-phy";
+ reg = <0x12170000 0x1ff>;
+ clocks = <&clock 287>;
+ clock-names = "sata_phyctrl";
+ #phy-cells = <0>;
+ samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+ samsung,syscon-phandle = <&pmu_syscon>;
+ };
+
+Device-Tree bindings for sataphy i2c client driver
+--------------------------------------------------
+
+Required properties:
+compatible: Should be "samsung,exynos-sataphy-i2c"
+- reg: I2C address of the sataphy i2c device.
+
+Example:
+
+ sata_phy_i2c:sata-phy at 38 {
+ compatible = "samsung,exynos-sataphy-i2c";
+ reg = <0x38>;
+ };
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index b42e658..d9c9eaf 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -370,6 +370,17 @@
};
};
+ i2c at 121D0000 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <40000>;
+ samsung,i2c-slave-addr = <0x38>;
+
+ sata_phy_i2c:sata-phy at 38 {
+ compatible = "samsung,exynos-sataphy-i2c";
+ reg = <0x38>;
+ };
+ };
+
mmc_0: mmc at 12200000 {
status = "okay";
num-slots = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e69837..e52eed8 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -96,16 +96,12 @@
samsung,i2c-slave-addr = <0x38>;
status = "okay";
- sata-phy {
- compatible = "samsung,sata-phy";
+ sata_phy_i2c:sata-phy at 38 {
+ compatible = "samsung,exynos-sataphy-i2c";
reg = <0x38>;
};
};
- sata at 122F0000 {
- samsung,sata-freq = <66>;
- };
-
i2c at 12C80000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dbb4a47..550d59e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -46,6 +46,7 @@
i2c6 = &i2c_6;
i2c7 = &i2c_7;
i2c8 = &i2c_8;
+ i2c9 = &i2c_9;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -231,16 +232,24 @@
};
sata at 122F0000 {
- compatible = "samsung,exynos5-sata-ahci";
+ compatible = "snps,dwc-ahci";
+ samsung,sata-freq = <66>;
reg = <0x122F0000 0x1ff>;
interrupts = <0 115 0>;
clocks = <&clock 277>, <&clock 143>;
clock-names = "sata", "sclk_sata";
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
};
- sata-phy at 12170000 {
- compatible = "samsung,exynos5-sata-phy";
+ sata_phy: sata-phy at 12170000 {
+ compatible = "samsung,exynos5250-sata-phy";
reg = <0x12170000 0x1ff>;
+ clocks = <&clock 287>;
+ clock-names = "sata_phyctrl";
+ #phy-cells = <0>;
+ samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+ samsung,syscon-phandle = <&pmu_syscon>;
};
i2c_0: i2c at 12C60000 {
@@ -358,7 +367,7 @@
status = "disabled";
};
- i2c at 121D0000 {
+ i2c_9: i2c at 121D0000 {
compatible = "samsung,exynos5-sata-phy-i2c";
reg = <0x121D0000 0x100>;
#address-cells = <1>;
--
1.7.9.5
^ permalink raw reply related
* [PATCH V7 1/2] PHY: Exynos: Add Exynos5250 SATA PHY driver
From: Yuvaraj Kumar C D @ 2014-01-27 14:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390832366-23454-1-git-send-email-yuvaraj.cd@samsung.com>
This patch adds the SATA PHY driver for Exynos5250.Exynos5250 SATA
PHY comprises of CMU and TRSV blocks which are of I2C register Map.
So this patch also adds a i2c client driver, which is used configure
the CMU and TRSV block of exynos5250 SATA PHY.
This patch incorporates the generic PHY framework to deal with SATA
PHY.
This patch depends on the below patches
[1].drivers: phy: add generic PHY framework
by Kishon Vijay Abraham I<kishon@ti.com>
[2].ata: ahci_platform: Manage SATA PHY
by Roger Quadros <rogerq@ti.com>
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Girish K S <ks.giri@samsung.com>
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
---
Changes from V6:
1.Removed phy-exynos5250-sata-i2c.c,as it is not required
after moving to of_find_i2c_device_by_node().
2.Changed struct __iomem *pmureg tp struct regmap *pmureg.
3.Changed the wait_for_reg_status() to return 0 or -EFAULT.
Changes from V5:
1.Rebased on latest generic PHY framework for-next tree.
2.Minor nits such as indentations.
Changes from V4:
1.Made Exynos5250 SATA PHY driver by default selects
CONFIG_I2C and CONFIG_I2C_S3C2410, as SATA PHY driver
depends on I2C.
2.struct i2c_driver sataphy_i2c_driver made static which
was earlier global type.
3.Renamed the files to phy-exynos5250-sata.c and
phy-exynos5250-sata-i2c.c and CONFIG_EXYNOS5250_SATA_PHY
to CONFIG_PHY_EXYNOS5250_SATA.
Changes from V3:
1.Moved devm_phy_create before to devm_phy_provider_register.
Changes from V2:
1.Removed of_match_table
2.Moved to syscon interface for PMU handling.
Changes from V1:
1.Adapted to latest version of Generic PHY framework
2.Removed exynos_sata_i2c_remove function.
drivers/phy/Kconfig | 13 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-exynos5250-sata.c | 244 +++++++++++++++++++++++++++++++++++++
3 files changed, 258 insertions(+)
create mode 100644 drivers/phy/phy-exynos5250-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index d0611b8..df79150 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -57,4 +57,17 @@ config PHY_EXYNOS_DP_VIDEO
help
Support for Display Port PHY found on Samsung EXYNOS SoCs.
+config PHY_EXYNOS5250_SATA
+ tristate "Exynos5250 Sata SerDes/PHY driver"
+ depends on SOC_EXYNOS5250
+ select GENERIC_PHY
+ select I2C
+ select I2C_S3C2410
+ select MFD_SYSCON
+ help
+ Enable this to support SATA SerDes/Phy found on Samsung's
+ Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
+ SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host
+ port to accept one SATA device.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 4e4adc9..5d93dc9 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
+obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o
diff --git a/drivers/phy/phy-exynos5250-sata.c b/drivers/phy/phy-exynos5250-sata.c
new file mode 100644
index 0000000..b35168d
--- /dev/null
+++ b/drivers/phy/phy-exynos5250-sata.c
@@ -0,0 +1,244 @@
+/*
+ * Samsung SATA SerDes(PHY) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Authors: Girish K S <ks.giri@samsung.com>
+ * Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/spinlock.h>
+#include <linux/mfd/syscon.h>
+
+#define EXYNOS5_SATA_RESET 0x4
+#define RESET_CMN_RST_N (1 << 1)
+#define LINK_RESET 0xf0000
+#define EXYNOS5_SATA_MODE0 0x10
+#define EXYNOS5_SATAPHY_PMU_ENABLE (1 << 0)
+#define SATA_SPD_GEN3 (2 << 0)
+#define EXYNOS5_SATA_CTRL0 0x14
+#define CTRL0_P0_PHY_CALIBRATED_SEL (1 << 9)
+#define CTRL0_P0_PHY_CALIBRATED (1 << 8)
+#define EXYNOS5_SATA_PHSATA_CTRLM 0xe0
+#define PHCTRLM_REF_RATE (1 << 1)
+#define PHCTRLM_HIGH_SPEED (1 << 0)
+#define EXYNOS5_SATA_PHSATA_STATM 0xf0
+#define PHSTATM_PLL_LOCKED (1 << 0)
+#define EXYNOS_SATA_PHY_EN (1 << 0)
+#define SATAPHY_CONTROL_OFFSET 0x0724
+
+#define PHY_PLL_TIMEOUT (usecs_to_jiffies(1000))
+
+struct exynos_sata_phy {
+ struct phy *phy;
+ struct clk *phyclk;
+ void __iomem *regs;
+ struct regmap *pmureg;
+ struct i2c_client *client;
+};
+
+static int wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
+ u32 status)
+{
+ unsigned long timeout = jiffies + PHY_PLL_TIMEOUT;
+
+ while (time_before(jiffies, timeout)) {
+ if ((readl(base + reg) & checkbit) == status)
+ return 0;
+ }
+
+ return -EFAULT;
+}
+
+static int exynos_sata_phy_power_on(struct phy *phy)
+{
+ struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
+
+ return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
+ EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
+
+}
+
+static int exynos_sata_phy_power_off(struct phy *phy)
+{
+ struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
+
+ return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
+ EXYNOS5_SATAPHY_PMU_ENABLE, ~EXYNOS_SATA_PHY_EN);
+
+}
+
+static int exynos_sata_phy_init(struct phy *phy)
+{
+ u32 val = 0;
+ int ret = 0;
+ u8 buf[] = { 0x3a, 0x0b };
+ struct exynos_sata_phy *sata_phy = phy_get_drvdata(phy);
+
+ ret = regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET,
+ EXYNOS5_SATAPHY_PMU_ENABLE, EXYNOS_SATA_PHY_EN);
+ if (ret != 0)
+ dev_err(&sata_phy->phy->dev, "phy init failed\n");
+
+ writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+
+ val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
+ val |= 0xff;
+ writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+
+ val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
+ val |= LINK_RESET;
+ writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+
+ val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
+ val |= RESET_CMN_RST_N;
+ writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+
+ val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
+ val &= ~PHCTRLM_REF_RATE;
+ writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
+
+ /* High speed enable for Gen3 */
+ val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
+ val |= PHCTRLM_HIGH_SPEED;
+ writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
+
+ val = readl(sata_phy->regs + EXYNOS5_SATA_CTRL0);
+ val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
+ writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
+
+ val = readl(sata_phy->regs + EXYNOS5_SATA_MODE0);
+ val |= SATA_SPD_GEN3;
+ writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0);
+
+ ret = i2c_master_send(sata_phy->client, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ /* release cmu reset */
+ val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
+ val &= ~RESET_CMN_RST_N;
+ writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+
+ val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
+ val |= RESET_CMN_RST_N;
+ writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
+
+ ret = wait_for_reg_status(sata_phy->regs,
+ EXYNOS5_SATA_PHSATA_STATM,
+ PHSTATM_PLL_LOCKED, 1);
+ if (ret < 0)
+ dev_err(&sata_phy->phy->dev,
+ "PHY PLL locking failed\n");
+ return ret;
+}
+
+static struct phy_ops exynos_sata_phy_ops = {
+ .init = exynos_sata_phy_init,
+ .power_on = exynos_sata_phy_power_on,
+ .power_off = exynos_sata_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int exynos_sata_phy_probe(struct platform_device *pdev)
+{
+ struct exynos_sata_phy *sata_phy;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct phy_provider *phy_provider;
+ struct device_node *node;
+ int ret = 0;
+
+ sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL);
+ if (!sata_phy)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ sata_phy->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(sata_phy->regs))
+ return PTR_ERR(sata_phy->regs);
+
+ sata_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "samsung,syscon-phandle");
+ if (IS_ERR(sata_phy->pmureg)) {
+ dev_err(dev, "syscon regmap lookup failed.\n");
+ return PTR_ERR(sata_phy->pmureg);
+ }
+
+ node = of_parse_phandle(dev->of_node,
+ "samsung,exynos-sataphy-i2c-phandle", 0);
+ if (!node)
+ return -EINVAL;
+
+ sata_phy->client = of_find_i2c_device_by_node(node);
+ if (!sata_phy->client)
+ return -EPROBE_DEFER;
+
+ dev_set_drvdata(dev, sata_phy);
+
+ sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl");
+ if (IS_ERR(sata_phy->phyclk)) {
+ dev_err(dev, "failed to get clk for PHY\n");
+ return PTR_ERR(sata_phy->phyclk);
+ }
+
+ ret = clk_prepare_enable(sata_phy->phyclk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable source clk\n");
+ return ret;
+ }
+
+ sata_phy->phy = devm_phy_create(dev, &exynos_sata_phy_ops, NULL);
+ if (IS_ERR(sata_phy->phy)) {
+ clk_disable_unprepare(sata_phy->phyclk);
+ dev_err(dev, "failed to create PHY\n");
+ return PTR_ERR(sata_phy->phy);
+ }
+
+ phy_set_drvdata(sata_phy->phy, sata_phy);
+
+ phy_provider = devm_of_phy_provider_register(dev,
+ of_phy_simple_xlate);
+ if (IS_ERR(phy_provider)) {
+ clk_disable_unprepare(sata_phy->phyclk);
+ return PTR_ERR(phy_provider);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id exynos_sata_phy_of_match[] = {
+ { .compatible = "samsung,exynos5250-sata-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, exynos_sata_phy_of_match);
+
+static struct platform_driver exynos_sata_phy_driver = {
+ .probe = exynos_sata_phy_probe,
+ .driver = {
+ .of_match_table = exynos_sata_phy_of_match,
+ .name = "samsung,sata-phy",
+ .owner = THIS_MODULE,
+ }
+};
+module_platform_driver(exynos_sata_phy_driver);
+
+MODULE_DESCRIPTION("Samsung SerDes PHY driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>");
+MODULE_AUTHOR("Yuvaraj C D <yuvaraj.cd@samsung.com>");
--
1.7.9.5
^ permalink raw reply related
* [PATCH V7 0/2] Exynos5250 SATA Support
From: Yuvaraj Kumar C D @ 2014-01-27 14:19 UTC (permalink / raw)
To: linux-arm-kernel
This patch series enable the SATA support on Exynos5250 based boards.
It incorporates the generic phy framework to deal with sata phy.
This patch depends on the below patches
[1]. drivers: phy: add generic PHY framework
by Kishon Vijay Abraham I<kishon@ti.com>
[2]. ata: ahci_platform: Manage SATA PHY
by Roger Quadros <rogerq@ti.com>
[3].ARM: dts: Add pmu sysreg node to exynos5250 and
exynos5420 dtsi files
by Leela Krishna Amudala <l.krishna@samsung.com>
[4]. i2c: s3c2410 : Add polling mode support
by Vasanth Ananthan <vasanth.a@samsung.com>
Changes from V6:
1.Removed phy-exynos5250-sata-i2c.c,as it is not required
after moving to of_find_i2c_device_by_node().
2.Changed struct __iomem pmureg tp struct regmap pmureg.
3.Changed the wait_for_reg_status() to return 0 or -EFAULT.
Changes from V5:
1.Rebased on latest generic PHY framework for-next tree.
2.Minor nits such as indentations.
Changes from V4:
1.Made Exynos5250 SATA PHY driver by default selects
CONFIG_I2C and CONFIG_I2C_S3C2410, as SATA PHY driver
depends on I2C.
2.Used the new phandle "sata_phy_i2c" in the DT entry.
3.struct i2c_driver sataphy_i2c_driver made static which
was earlier global type.
Changes from V3:
1.Moved the devicetree binding documentation
from /bindings/ata/ to bindings/phy/ .
2.Moved devm_phy_create call before to
the devm_phy_provider_register.
Changes from V2:
1.Removed of_match_table
2.Moved to syscon interface for PMU handling.
Changes from V1:
1. Dropped the patch
ahci: exynos: add ahci sata support on Exynos platform
2.Adapt to latest generic PHY framework available in
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git next
Yuvaraj Kumar C D (2):
PHY: Exynos: Add Exynos5250 SATA PHY driver
ARM: dts: Enable ahci sata and sata phy
.../devicetree/bindings/ata/exynos-sata-phy.txt | 14 --
.../devicetree/bindings/ata/exynos-sata.txt | 25 +-
.../devicetree/bindings/phy/samsung-phy.txt | 36 +++
arch/arm/boot/dts/exynos5250-arndale.dts | 11 +
arch/arm/boot/dts/exynos5250-smdk5250.dts | 8 +-
arch/arm/boot/dts/exynos5250.dtsi | 17 +-
drivers/phy/Kconfig | 13 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-exynos5250-sata.c | 244 ++++++++++++++++++++
9 files changed, 336 insertions(+), 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
create mode 100644 drivers/phy/phy-exynos5250-sata.c
--
1.7.9.5
^ permalink raw reply
* at_hdmac does not release lock before the callback - deadlock
From: Jouko Haapaluoma @ 2014-01-27 14:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <C9F8415089354E4FB76F4548B3515AF484286F61@edb1.wapice.localdomain>
After further investigation it seems that the deadlocks would happen only when CONFIG_SMP is enabled or RT_PREEMPT patch is used. When CONFIG_SMP or RT_PREEMPT is not used, the spinlocks will only disable preemption which does not cause a deadlock. However, with the CONFIG_SMP or the RT_PREEMPT patch spinlocks are actual locks and deadlocks can occur.
This might explain why this problem hasn't been noticed before. At least the Atmel serial driver from linux4sam git causes deadlocks with the RT_PREEMPT because of this issue.
BR,
Jouko Haapaluoma
^ permalink raw reply
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