* [PATCH v2 08/11] of: Increase MAX_PHANDLE_ARGS
From: Andreas Herrmann @ 2014-01-29 17:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E93360.1000904@amd.com>
On Wed, Jan 29, 2014 at 11:59:12AM -0500, Suravee Suthikulanit wrote:
> On 1/29/2014 10:57 AM, Rob Herring wrote:
> >>> diff --git a/include/linux/of.h b/include/linux/of.h
> >>> >>index 276c546..24e1b28 100644
> >>> >>--- a/include/linux/of.h
> >>> >>+++ b/include/linux/of.h
> >>> >>@@ -67,7 +67,7 @@ struct device_node {
> >>> >> #endif
> >>> >> };
> >>> >>
> >>> >>-#define MAX_PHANDLE_ARGS 8
> >>> >>+#define MAX_PHANDLE_ARGS 16
> >> >
> >> >
> >> >Since the MMU-500 specify "Number of SMRs" upto 128 registers, shouldn't
> >> >this be changed to be able to support 128 StreamIDs as well? Although I am
> >> >not sure if this would be too big to have on the stack per Rob's comment in
> >> >the previous patch set.
> > Do you actually need 128 now? If not, then we can deal with that when
> > we get there. There are lots of things in spec's that are not actually
> > implemented or supported.
>
> Actually, we are using 32 on the AMD system. So, do you think we can set
> this to 32 instead?
I think that's ok.
But are we really talking about number of SMRs or number of StreamIDs
per master device here? Ie. are you just having 32 SMRs for an SMMU on
your AMD system or do you have master devices which have 32 StreamIDs?
If it's just number of SMRs we don't need to modify this macro.
Andreas
^ permalink raw reply
* [RFC PATCH v2 09/14] mtd: nand: add sunxi NFC dt bindings doc
From: Rob Herring @ 2014-01-29 17:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqLVr1gSLArqtfOiHce+u6ZK8FiKMX0o9bvMrMoGGhATvg@mail.gmail.com>
On Wed, Jan 29, 2014 at 11:11 AM, Rob Herring <robherring2@gmail.com> wrote:
> On Wed, Jan 29, 2014 at 8:34 AM, Boris BREZILLON
> <b.brezillon.dev@gmail.com> wrote:
>> Add the sunxi NAND Flash Controller dt bindings documentation.
>>
[snip]
>> +- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
>> + standard.
>
> Add to generic nand binding.
NM, I see you did this.
Rob
^ permalink raw reply
* [RFC PATCH v2 09/14] mtd: nand: add sunxi NFC dt bindings doc
From: Rob Herring @ 2014-01-29 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391006064-28890-10-git-send-email-b.brezillon.dev@gmail.com>
On Wed, Jan 29, 2014 at 8:34 AM, Boris BREZILLON
<b.brezillon.dev@gmail.com> wrote:
> Add the sunxi NAND Flash Controller dt bindings documentation.
>
> Signed-off-by: Boris BREZILLON <b.brezillon.dev@gmail.com>
> ---
> .../devicetree/bindings/mtd/sunxi-nand.txt | 46 ++++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/sunxi-nand.txt
>
> diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
> new file mode 100644
> index 0000000..b0e55a3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
> @@ -0,0 +1,46 @@
> +Allwinner NAND Flash Controller (NFC)
> +
> +Required properties:
> +- compatible : "allwinner,sun4i-nand".
> +- reg : shall contain registers location and length for data and reg.
> +- interrupts : shall define the nand controller interrupt.
> +- #address-cells: shall be set to 1. Encode the nand CS.
> +- #size-cells : shall be set to 0.
> +- clocks : shall reference nand controller clocks.
> +- clock-names : nand controller internal clock names. Shall contain :
> + * "ahb_clk" : AHB gating clock
> + * "sclk" : nand controller clock
> +
> +Optional children nodes:
> +Children nodes represent the available nand chips.
> +
> +Optional properties:
For the controller or per nand chip?
> +- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
> + standard.
Add to generic nand binding.
> +- allwinner,rb : shall contain the native Ready/Busy ids.
> + or
> +- rb-gpios : shall contain the gpios used as R/B pins.
Isn't allwinner,rb implied by a lack of rb-gpios property. Or no R/B
pin is an option? If so, don't you need some fixed time delay
properties like max erase time?
rb-gpios could be added to the generic nand binding as well.
Rob
^ permalink raw reply
* [PATCH v2 08/11] of: Increase MAX_PHANDLE_ARGS
From: Suravee Suthikulanit @ 2014-01-29 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqLhzp5jUJPA91rNkQ07kCDYCDZLxw8LxxFEVP9b12e1Jw@mail.gmail.com>
On 1/29/2014 10:57 AM, Rob Herring wrote:
>>> diff --git a/include/linux/of.h b/include/linux/of.h
>>> >>index 276c546..24e1b28 100644
>>> >>--- a/include/linux/of.h
>>> >>+++ b/include/linux/of.h
>>> >>@@ -67,7 +67,7 @@ struct device_node {
>>> >> #endif
>>> >> };
>>> >>
>>> >>-#define MAX_PHANDLE_ARGS 8
>>> >>+#define MAX_PHANDLE_ARGS 16
>> >
>> >
>> >Since the MMU-500 specify "Number of SMRs" upto 128 registers, shouldn't
>> >this be changed to be able to support 128 StreamIDs as well? Although I am
>> >not sure if this would be too big to have on the stack per Rob's comment in
>> >the previous patch set.
> Do you actually need 128 now? If not, then we can deal with that when
> we get there. There are lots of things in spec's that are not actually
> implemented or supported.
Actually, we are using 32 on the AMD system. So, do you think we can set
this to 32 instead?
Thanks,
Suravee
^ permalink raw reply
* [PATCH v2 08/11] of: Increase MAX_PHANDLE_ARGS
From: Rob Herring @ 2014-01-29 16:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52E92842.3000001@amd.com>
On Wed, Jan 29, 2014 at 10:11 AM, Suravee Suthikulanit
<suravee.suthikulpanit@amd.com> wrote:
> On 1/17/2014 5:08 AM, Andreas Herrmann wrote:
>>
>>
>> arm-smmu driver uses of_parse_phandle_with_args when parsing DT
>> information to determine stream IDs for a master device.
>> Thus the number of stream IDs per master device is bound by
>> MAX_PHANDLE_ARGS.
>>
>> To support Calxeda ECX-2000 hardware arm-smmu driver requires a
>> slightly higher value for MAX_PHANDLE_ARGS as this hardware has 10
>> stream IDs for one master device.
>>
>> Increasing it to 16 seems a reasonable choice.
>>
>> Cc: Grant Likely <grant.likely@linaro.org>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: devicetree at vger.kernel.org
>> Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
>> Acked-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
>> ---
>> include/linux/of.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/include/linux/of.h b/include/linux/of.h
>> index 276c546..24e1b28 100644
>> --- a/include/linux/of.h
>> +++ b/include/linux/of.h
>> @@ -67,7 +67,7 @@ struct device_node {
>> #endif
>> };
>>
>> -#define MAX_PHANDLE_ARGS 8
>> +#define MAX_PHANDLE_ARGS 16
>
>
> Since the MMU-500 specify "Number of SMRs" upto 128 registers, shouldn't
> this be changed to be able to support 128 StreamIDs as well? Although I am
> not sure if this would be too big to have on the stack per Rob's comment in
> the previous patch set.
Do you actually need 128 now? If not, then we can deal with that when
we get there. There are lots of things in spec's that are not actually
implemented or supported.
Rob
^ permalink raw reply
* [PATCH] ARM: dts: OMAP5: add pmu node
From: Nathan Lynch @ 2014-01-29 16:56 UTC (permalink / raw)
To: linux-arm-kernel
Expose the PMU on OMAP5.
Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
---
Notes:
Briefly tested with perf on OMAP5 UEVM with next-20140124.
arch/arm/boot/dts/omap5.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index a72813a9663e..fbf4661436e2 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -76,6 +76,12 @@
<GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
};
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts = <0 131 4>,
+ <0 132 4>;
+ };
+
gic: interrupt-controller at 48211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
--
1.8.3.1
^ permalink raw reply related
* [PATCH 5/5] arm64: add Crypto Extensions based synchronous core AES cipher
From: Ard Biesheuvel @ 2014-01-29 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391014246-9715-1-git-send-email-ard.biesheuvel@linaro.org>
This implements the core AES cipher using the Crypto Extensions,
using only NEON registers q0 and q1.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/Makefile | 1 +
arch/arm64/crypto/Makefile | 13 +++++
arch/arm64/crypto/aes-ce-cipher.c | 103 ++++++++++++++++++++++++++++++++++++++
crypto/Kconfig | 6 +++
4 files changed, 123 insertions(+)
create mode 100644 arch/arm64/crypto/Makefile
create mode 100644 arch/arm64/crypto/aes-ce-cipher.c
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 2fceb71ac3b7..8185a913c5ed 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -45,6 +45,7 @@ export TEXT_OFFSET GZFLAGS
core-y += arch/arm64/kernel/ arch/arm64/mm/
core-$(CONFIG_KVM) += arch/arm64/kvm/
core-$(CONFIG_XEN) += arch/arm64/xen/
+core-$(CONFIG_CRYPTO) += arch/arm64/crypto/
libs-y := arch/arm64/lib/ $(libs-y)
libs-y += $(LIBGCC)
diff --git a/arch/arm64/crypto/Makefile b/arch/arm64/crypto/Makefile
new file mode 100644
index 000000000000..ac58945c50b3
--- /dev/null
+++ b/arch/arm64/crypto/Makefile
@@ -0,0 +1,13 @@
+#
+# linux/arch/arm64/crypto/Makefile
+#
+# Copyright (C) 2013 Linaro Ltd <ard.biesheuvel@linaro.org>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation.
+#
+
+obj-$(CONFIG_CRYPTO_AES_ARM64_CE) += aes-ce-cipher.o
+
+CFLAGS_aes-ce-cipher.o += -march=armv8-a+crypto
diff --git a/arch/arm64/crypto/aes-ce-cipher.c b/arch/arm64/crypto/aes-ce-cipher.c
new file mode 100644
index 000000000000..b5a5d5d6e4b8
--- /dev/null
+++ b/arch/arm64/crypto/aes-ce-cipher.c
@@ -0,0 +1,103 @@
+/*
+ * linux/arch/arm64/crypto/aes-ce-cipher.c
+ *
+ * Copyright (C) 2013 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/neon.h>
+#include <crypto/aes.h>
+#include <linux/crypto.h>
+#include <linux/module.h>
+#include <linux/cpufeature.h>
+
+MODULE_DESCRIPTION("Synchronous AES cipher using ARMv8 Crypto Extensions");
+MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
+MODULE_LICENSE("GPL");
+
+static void aes_cipher_encrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[])
+{
+ struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+ u32 rounds = 6 + ctx->key_length / 4;
+
+ kernel_neon_begin();
+
+ __asm__(" ld1 {v0.16b}, [%[in]] ;"
+ " ld1 {v1.16b}, [%[key]], #16 ;"
+ "0: aese v0.16b, v1.16b ;"
+ " subs %[rounds], %[rounds], #1 ;"
+ " ld1 {v1.16b}, [%[key]], #16 ;"
+ " beq 1f ;"
+ " aesmc v0.16b, v0.16b ;"
+ " b 0b ;"
+ "1: eor v0.16b, v0.16b, v1.16b ;"
+ " st1 {v0.16b}, [%[out]] ;"
+ : :
+ [out] "r"(dst),
+ [in] "r"(src),
+ [rounds] "r"(rounds),
+ [key] "r"(ctx->key_enc)
+ : "cc");
+
+ kernel_neon_end();
+}
+
+static void aes_cipher_decrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[])
+{
+ struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+ u32 rounds = 6 + ctx->key_length / 4;
+
+ kernel_neon_begin();
+
+ __asm__(" ld1 {v0.16b}, [%[in]] ;"
+ " ld1 {v1.16b}, [%[key]], #16 ;"
+ "0: aesd v0.16b, v1.16b ;"
+ " ld1 {v1.16b}, [%[key]], #16 ;"
+ " subs %[rounds], %[rounds], #1 ;"
+ " beq 1f ;"
+ " aesimc v0.16b, v0.16b ;"
+ " b 0b ;"
+ "1: eor v0.16b, v0.16b, v1.16b ;"
+ " st1 {v0.16b}, [%[out]] ;"
+ : :
+ [out] "r"(dst),
+ [in] "r"(src),
+ [rounds] "r"(rounds),
+ [key] "r"(ctx->key_dec)
+ : "cc");
+
+ kernel_neon_end();
+}
+
+static struct crypto_alg aes_alg = {
+ .cra_name = "aes",
+ .cra_driver_name = "aes-ce",
+ .cra_priority = 300,
+ .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct crypto_aes_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_cipher = {
+ .cia_min_keysize = AES_MIN_KEY_SIZE,
+ .cia_max_keysize = AES_MAX_KEY_SIZE,
+ .cia_setkey = crypto_aes_set_key,
+ .cia_encrypt = aes_cipher_encrypt,
+ .cia_decrypt = aes_cipher_decrypt
+ }
+};
+
+static int __init aes_mod_init(void)
+{
+ return crypto_register_alg(&aes_alg);
+}
+
+static void __exit aes_mod_exit(void)
+{
+ crypto_unregister_alg(&aes_alg);
+}
+
+module_cpu_feature_match(AES, aes_mod_init);
+module_exit(aes_mod_exit);
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 7bcb70d216e1..f1d98bc346b6 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -791,6 +791,12 @@ config CRYPTO_AES_ARM_BS
This implementation does not rely on any lookup tables so it is
believed to be invulnerable to cache timing attacks.
+config CRYPTO_AES_ARM64_CE
+ tristate "Synchronous AES cipher using ARMv8 Crypto Extensions"
+ depends on ARM64 && KERNEL_MODE_NEON
+ select CRYPTO_ALGAPI
+ select CRYPTO_AES
+
config CRYPTO_ANUBIS
tristate "Anubis cipher algorithm"
select CRYPTO_ALGAPI
--
1.8.3.2
^ permalink raw reply related
* [PATCH 4/5] arm64: enable generic CPU feature modalias matching for this arch
From: Ard Biesheuvel @ 2014-01-29 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391014246-9715-1-git-send-email-ard.biesheuvel@linaro.org>
This enables support for the generic CPU feature modalias implementation that
wires up optional CPU features to udev based module autoprobing.
A file <asm/cpufeatures.h> is provided that maps CPU feature numbers to
elf_hwcap bits, which is the standard way on arm64 to advertise optional CPU
features both internally and to user space.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/cpufeature.h | 30 ++++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
create mode 100644 arch/arm64/include/asm/cpufeature.h
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index dd4327f09ba4..e339099b6fbd 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -16,6 +16,7 @@ config ARM64
select DCACHE_WORD_ACCESS
select GENERIC_CLOCKEVENTS
select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+ select GENERIC_CPU_AUTOPROBE
select GENERIC_IOMAP
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
new file mode 100644
index 000000000000..1d902efa201d
--- /dev/null
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_CPUFEATURE_H
+#define __ASM_CPUFEATURE_H
+
+#include <asm/elf.h>
+#include <asm/hwcap.h>
+
+/*
+ * In the arm64 world (as in the ARM world), elf_hwcap is used both internally
+ * in the kernel and for user space to keep track of which optional features
+ * are supported by the current system. So let's map feature 'x' to HWCAP_x.
+ * Note that HWCAP_x constants are bit fields so we need to take the log.
+ */
+
+#define MAX_CPU_FEATURES sizeof(elf_hwcap)
+#define cpu_feature(x) ((unsigned int)ilog2(HWCAP_ ## x))
+
+static inline bool cpu_have_feature(unsigned int num)
+{
+ return !!(elf_hwcap & (1 << num));
+}
+
+#endif
--
1.8.3.2
^ permalink raw reply related
* [PATCH 3/5] x86: align x86 arch with generic CPU modalias handling
From: Ard Biesheuvel @ 2014-01-29 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391014246-9715-1-git-send-email-ard.biesheuvel@linaro.org>
The x86 CPU feature modalias handling existed before it was reimplemented
generically. This patch aligns the x86 handling so that it
(a) reuses some more code that is now generic;
(b) uses the generic format for the modalias module metadata entry, i.e., it
now uses 'cpu:type:x86,venVVVVfamFFFFmodMMMM:feature:,XXXX,YYYY' instead of
the 'x86cpu:vendor:VVVV:family:FFFF:model:MMMM:feature,XXXX,YYYY' that was
used before.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/x86/Kconfig | 4 +---
arch/x86/include/asm/cpufeature.h | 7 +++++++
arch/x86/kernel/cpu/match.c | 31 -------------------------------
drivers/base/Kconfig | 5 -----
drivers/base/cpu.c | 10 +++-------
include/linux/cpu.h | 6 ------
scripts/mod/file2alias.c | 10 +++++-----
7 files changed, 16 insertions(+), 57 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 940e50ebfafa..7d3b7907a10c 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -127,6 +127,7 @@ config X86
select HAVE_DEBUG_STACKOVERFLOW
select HAVE_IRQ_EXIT_ON_IRQ_STACK if X86_64
select HAVE_CC_STACKPROTECTOR
+ select GENERIC_CPU_AUTOPROBE
config INSTRUCTION_DECODER
def_bool y
@@ -195,9 +196,6 @@ config ARCH_HAS_CPU_RELAX
config ARCH_HAS_CACHE_LINE_SIZE
def_bool y
-config ARCH_HAS_CPU_AUTOPROBE
- def_bool y
-
config HAVE_SETUP_PER_CPU_AREA
def_bool y
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index e099f9502ace..d86dc3deea6a 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -541,6 +541,13 @@ static __always_inline __pure bool _static_cpu_has_safe(u16 bit)
#define static_cpu_has_bug(bit) static_cpu_has((bit))
#define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit))
+#define MAX_CPU_FEATURES (NCAPINTS * 32)
+#define cpu_have_feature boot_cpu_has
+
+#define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X"
+#define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \
+ boot_cpu_data.x86_model
+
#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
#endif /* _ASM_X86_CPUFEATURE_H */
diff --git a/arch/x86/kernel/cpu/match.c b/arch/x86/kernel/cpu/match.c
index ab6082a9020e..afa9f0d487ea 100644
--- a/arch/x86/kernel/cpu/match.c
+++ b/arch/x86/kernel/cpu/match.c
@@ -47,34 +47,3 @@ const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *match)
return NULL;
}
EXPORT_SYMBOL(x86_match_cpu);
-
-ssize_t arch_print_cpu_modalias(struct device *dev,
- struct device_attribute *attr,
- char *bufptr)
-{
- int size = PAGE_SIZE;
- int i, n;
- char *buf = bufptr;
-
- n = snprintf(buf, size, "x86cpu:vendor:%04X:family:%04X:"
- "model:%04X:feature:",
- boot_cpu_data.x86_vendor,
- boot_cpu_data.x86,
- boot_cpu_data.x86_model);
- size -= n;
- buf += n;
- size -= 1;
- for (i = 0; i < NCAPINTS*32; i++) {
- if (boot_cpu_has(i)) {
- n = snprintf(buf, size, ",%04X", i);
- if (n >= size) {
- WARN(1, "x86 features overflow page\n");
- break;
- }
- size -= n;
- buf += n;
- }
- }
- *buf++ = '\n';
- return buf - bufptr;
-}
diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index 3f0d3732df7f..8fa8deab6449 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
@@ -185,13 +185,8 @@ config GENERIC_CPU_DEVICES
bool
default n
-config HAVE_CPU_AUTOPROBE
- def_bool ARCH_HAS_CPU_AUTOPROBE
-
config GENERIC_CPU_AUTOPROBE
bool
- depends on !ARCH_HAS_CPU_AUTOPROBE
- select HAVE_CPU_AUTOPROBE
config SOC_BUS
bool
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index 8a38bf8c792f..006b1bc5297d 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -287,7 +287,6 @@ static void cpu_device_release(struct device *dev)
*/
}
-#ifdef CONFIG_HAVE_CPU_AUTOPROBE
#ifdef CONFIG_GENERIC_CPU_AUTOPROBE
static ssize_t print_cpu_modalias(struct device *dev,
struct device_attribute *attr,
@@ -310,9 +309,6 @@ static ssize_t print_cpu_modalias(struct device *dev,
buf[n++] = '\n';
return n;
}
-#else
-#define print_cpu_modalias arch_print_cpu_modalias
-#endif
static int cpu_uevent(struct device *dev, struct kobj_uevent_env *env)
{
@@ -346,7 +342,7 @@ int register_cpu(struct cpu *cpu, int num)
cpu->dev.offline_disabled = !cpu->hotpluggable;
cpu->dev.offline = !cpu_online(num);
cpu->dev.of_node = of_get_cpu_node(num, NULL);
-#ifdef CONFIG_HAVE_CPU_AUTOPROBE
+#ifdef CONFIG_GENERIC_CPU_AUTOPROBE
cpu->dev.bus->uevent = cpu_uevent;
#endif
cpu->dev.groups = common_cpu_attr_groups;
@@ -370,7 +366,7 @@ struct device *get_cpu_device(unsigned cpu)
}
EXPORT_SYMBOL_GPL(get_cpu_device);
-#ifdef CONFIG_HAVE_CPU_AUTOPROBE
+#ifdef CONFIG_GENERIC_CPU_AUTOPROBE
static DEVICE_ATTR(modalias, 0444, print_cpu_modalias, NULL);
#endif
@@ -384,7 +380,7 @@ static struct attribute *cpu_root_attrs[] = {
&cpu_attrs[2].attr.attr,
&dev_attr_kernel_max.attr,
&dev_attr_offline.attr,
-#ifdef CONFIG_HAVE_CPU_AUTOPROBE
+#ifdef CONFIG_GENERIC_CPU_AUTOPROBE
&dev_attr_modalias.attr,
#endif
NULL
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index dcc4a0d9c45f..03e962e23eaf 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -46,12 +46,6 @@ extern ssize_t arch_cpu_release(const char *, size_t);
#endif
struct notifier_block;
-#ifdef CONFIG_ARCH_HAS_CPU_AUTOPROBE
-extern ssize_t arch_print_cpu_modalias(struct device *dev,
- struct device_attribute *attr,
- char *bufptr);
-#endif
-
/*
* CPU notifier priorities.
*/
diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
index 8a69005228d8..5fdad833f951 100644
--- a/scripts/mod/file2alias.c
+++ b/scripts/mod/file2alias.c
@@ -1110,7 +1110,7 @@ static int do_amba_entry(const char *filename,
}
ADD_TO_DEVTABLE("amba", amba_id, do_amba_entry);
-/* LOOKS like x86cpu:vendor:VVVV:family:FFFF:model:MMMM:feature:*,FEAT,*
+/* LOOKS like cpu:type:x86,venVVVVfamFFFFmodMMMM:feature:*,FEAT,*
* All fields are numbers. It would be nicer to use strings for vendor
* and feature, but getting those out of the build system here is too
* complicated.
@@ -1124,10 +1124,10 @@ static int do_x86cpu_entry(const char *filename, void *symval,
DEF_FIELD(symval, x86_cpu_id, model);
DEF_FIELD(symval, x86_cpu_id, vendor);
- strcpy(alias, "x86cpu:");
- ADD(alias, "vendor:", vendor != X86_VENDOR_ANY, vendor);
- ADD(alias, ":family:", family != X86_FAMILY_ANY, family);
- ADD(alias, ":model:", model != X86_MODEL_ANY, model);
+ strcpy(alias, "cpu:type:x86,");
+ ADD(alias, "ven", vendor != X86_VENDOR_ANY, vendor);
+ ADD(alias, "fam", family != X86_FAMILY_ANY, family);
+ ADD(alias, "mod", model != X86_MODEL_ANY, model);
strcat(alias, ":feature:*");
if (feature != X86_FEATURE_ANY)
sprintf(alias + strlen(alias), "%04X*", feature);
--
1.8.3.2
^ permalink raw reply related
* [PATCH 2/5] cpu: add generic support for CPU feature based module autoloading
From: Ard Biesheuvel @ 2014-01-29 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391014246-9715-1-git-send-email-ard.biesheuvel@linaro.org>
This patch adds support for advertising optional CPU features over udev using
the modalias, and for declaring compatibility with/dependency upon such a
feature in a module.
This feature can be enabled by setting CONFIG_GENERIC_CPU_AUTOPROBE for the
architecture, and supplying a file <asm/cpufeature.h> which defines how the
numbers used in the modalias string map to actual CPU features.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
drivers/base/Kconfig | 8 ++++++
drivers/base/cpu.c | 39 +++++++++++++++++++++----
include/linux/cpufeature.h | 60 +++++++++++++++++++++++++++++++++++++++
include/linux/mod_devicetable.h | 9 ++++++
scripts/mod/devicetable-offsets.c | 3 ++
scripts/mod/file2alias.c | 10 +++++++
6 files changed, 123 insertions(+), 6 deletions(-)
create mode 100644 include/linux/cpufeature.h
diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index ec36e7772e57..3f0d3732df7f 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
@@ -185,6 +185,14 @@ config GENERIC_CPU_DEVICES
bool
default n
+config HAVE_CPU_AUTOPROBE
+ def_bool ARCH_HAS_CPU_AUTOPROBE
+
+config GENERIC_CPU_AUTOPROBE
+ bool
+ depends on !ARCH_HAS_CPU_AUTOPROBE
+ select HAVE_CPU_AUTOPROBE
+
config SOC_BUS
bool
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index 270649012e64..8a38bf8c792f 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -15,6 +15,7 @@
#include <linux/percpu.h>
#include <linux/acpi.h>
#include <linux/of.h>
+#include <linux/cpufeature.h>
#include "base.h"
@@ -286,12 +287,38 @@ static void cpu_device_release(struct device *dev)
*/
}
-#ifdef CONFIG_ARCH_HAS_CPU_AUTOPROBE
+#ifdef CONFIG_HAVE_CPU_AUTOPROBE
+#ifdef CONFIG_GENERIC_CPU_AUTOPROBE
+static ssize_t print_cpu_modalias(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ ssize_t n;
+ u32 i;
+
+ n = sprintf(buf, "cpu:type:" CPU_FEATURE_TYPEFMT ":feature:",
+ CPU_FEATURE_TYPEVAL);
+
+ for (i = 0; i < MAX_CPU_FEATURES; i++)
+ if (cpu_have_feature(i)) {
+ if (PAGE_SIZE < n + sizeof(",XXXX\n")) {
+ WARN(1, "CPU features overflow page\n");
+ break;
+ }
+ n += sprintf(&buf[n], ",%04X", i);
+ }
+ buf[n++] = '\n';
+ return n;
+}
+#else
+#define print_cpu_modalias arch_print_cpu_modalias
+#endif
+
static int cpu_uevent(struct device *dev, struct kobj_uevent_env *env)
{
char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
if (buf) {
- arch_print_cpu_modalias(NULL, NULL, buf);
+ print_cpu_modalias(NULL, NULL, buf);
add_uevent_var(env, "MODALIAS=%s", buf);
kfree(buf);
}
@@ -319,7 +346,7 @@ int register_cpu(struct cpu *cpu, int num)
cpu->dev.offline_disabled = !cpu->hotpluggable;
cpu->dev.offline = !cpu_online(num);
cpu->dev.of_node = of_get_cpu_node(num, NULL);
-#ifdef CONFIG_ARCH_HAS_CPU_AUTOPROBE
+#ifdef CONFIG_HAVE_CPU_AUTOPROBE
cpu->dev.bus->uevent = cpu_uevent;
#endif
cpu->dev.groups = common_cpu_attr_groups;
@@ -343,8 +370,8 @@ struct device *get_cpu_device(unsigned cpu)
}
EXPORT_SYMBOL_GPL(get_cpu_device);
-#ifdef CONFIG_ARCH_HAS_CPU_AUTOPROBE
-static DEVICE_ATTR(modalias, 0444, arch_print_cpu_modalias, NULL);
+#ifdef CONFIG_HAVE_CPU_AUTOPROBE
+static DEVICE_ATTR(modalias, 0444, print_cpu_modalias, NULL);
#endif
static struct attribute *cpu_root_attrs[] = {
@@ -357,7 +384,7 @@ static struct attribute *cpu_root_attrs[] = {
&cpu_attrs[2].attr.attr,
&dev_attr_kernel_max.attr,
&dev_attr_offline.attr,
-#ifdef CONFIG_ARCH_HAS_CPU_AUTOPROBE
+#ifdef CONFIG_HAVE_CPU_AUTOPROBE
&dev_attr_modalias.attr,
#endif
NULL
diff --git a/include/linux/cpufeature.h b/include/linux/cpufeature.h
new file mode 100644
index 000000000000..c4d4eb8ac9fe
--- /dev/null
+++ b/include/linux/cpufeature.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_CPUFEATURE_H
+#define __LINUX_CPUFEATURE_H
+
+#ifdef CONFIG_GENERIC_CPU_AUTOPROBE
+
+#include <linux/mod_devicetable.h>
+#include <asm/cpufeature.h>
+
+/*
+ * Macros imported from <asm/cpufeature.h>:
+ * - cpu_feature(x) ordinal value of feature called 'x'
+ * - cpu_have_feature(u32 n) whether feature #n is available
+ * - MAX_CPU_FEATURES upper bound for feature ordinal values
+ * Optional:
+ * - CPU_FEATURE_TYPEFMT format string fragment for printing the cpu type
+ * - CPU_FEATURE_TYPEVAL set of values matching the format string above
+ */
+
+#ifndef CPU_FEATURE_TYPEFMT
+#define CPU_FEATURE_TYPEFMT "%s"
+#endif
+
+#ifndef CPU_FEATURE_TYPEVAL
+#define CPU_FEATURE_TYPEVAL ELF_PLATFORM
+#endif
+
+/*
+ * Use module_cpu_feature_match(feature, module_init_function) to
+ * declare that
+ * a) the module shall be probed upon discovery of CPU feature 'feature'
+ * (typically at boot time using udev)
+ * b) the module must not be loaded if CPU feature 'feature' is not present
+ * (not even by manual insmod).
+ *
+ * For a list of legal values for 'feature', please consult the file
+ * 'asm/cpufeature.h' of your favorite architecture.
+ */
+#define module_cpu_feature_match(x, __init) \
+static struct cpu_feature const cpu_feature_match_ ## x[] = \
+ { { .feature = cpu_feature(x) }, { } }; \
+MODULE_DEVICE_TABLE(cpu, cpu_feature_match_ ## x); \
+ \
+static int cpu_feature_match_ ## x ## _init(void) \
+{ \
+ if (!cpu_have_feature(cpu_feature(x))) \
+ return -ENODEV; \
+ return __init(); \
+} \
+module_init(cpu_feature_match_ ## x ## _init)
+
+#endif
+#endif
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 45e921401b06..f2ac87c613a5 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -564,6 +564,15 @@ struct x86_cpu_id {
#define X86_MODEL_ANY 0
#define X86_FEATURE_ANY 0 /* Same as FPU, you can't test for that */
+/*
+ * Generic table type for matching CPU features.
+ * @feature: the bit number of the feature (0 - 65535)
+ */
+
+struct cpu_feature {
+ __u16 feature;
+};
+
#define IPACK_ANY_FORMAT 0xff
#define IPACK_ANY_ID (~0)
struct ipack_device_id {
diff --git a/scripts/mod/devicetable-offsets.c b/scripts/mod/devicetable-offsets.c
index bb5d115ca671..f282516acc7b 100644
--- a/scripts/mod/devicetable-offsets.c
+++ b/scripts/mod/devicetable-offsets.c
@@ -174,6 +174,9 @@ int main(void)
DEVID_FIELD(x86_cpu_id, model);
DEVID_FIELD(x86_cpu_id, vendor);
+ DEVID(cpu_feature);
+ DEVID_FIELD(cpu_feature, feature);
+
DEVID(mei_cl_device_id);
DEVID_FIELD(mei_cl_device_id, name);
diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
index 23708636b05c..8a69005228d8 100644
--- a/scripts/mod/file2alias.c
+++ b/scripts/mod/file2alias.c
@@ -1135,6 +1135,16 @@ static int do_x86cpu_entry(const char *filename, void *symval,
}
ADD_TO_DEVTABLE("x86cpu", x86_cpu_id, do_x86cpu_entry);
+/* LOOKS like cpu:type:*:feature:*FEAT* */
+static int do_cpu_entry(const char *filename, void *symval, char *alias)
+{
+ DEF_FIELD(symval, cpu_feature, feature);
+
+ sprintf(alias, "cpu:type:*:feature:*%04X*", feature);
+ return 1;
+}
+ADD_TO_DEVTABLE("cpu", cpu_feature, do_cpu_entry);
+
/* Looks like: mei:S */
static int do_mei_entry(const char *filename, void *symval,
char *alias)
--
1.8.3.2
^ permalink raw reply related
* [PATCH 1/5] cpu: move arch_cpu_uevent() to generic code
From: Ard Biesheuvel @ 2014-01-29 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391014246-9715-1-git-send-email-ard.biesheuvel@linaro.org>
Only x86 implements arch_cpu_uevent(), and there is nothing arch
specific about it, so move it to drivers/base/cpu.c and rename
it to cpu_uevent().
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/x86/kernel/cpu/match.c | 11 -----------
drivers/base/cpu.c | 15 ++++++++++++++-
include/linux/cpu.h | 1 -
3 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/arch/x86/kernel/cpu/match.c b/arch/x86/kernel/cpu/match.c
index 36565373af87..ab6082a9020e 100644
--- a/arch/x86/kernel/cpu/match.c
+++ b/arch/x86/kernel/cpu/match.c
@@ -78,14 +78,3 @@ ssize_t arch_print_cpu_modalias(struct device *dev,
*buf++ = '\n';
return buf - bufptr;
}
-
-int arch_cpu_uevent(struct device *dev, struct kobj_uevent_env *env)
-{
- char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
- if (buf) {
- arch_print_cpu_modalias(NULL, NULL, buf);
- add_uevent_var(env, "MODALIAS=%s", buf);
- kfree(buf);
- }
- return 0;
-}
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index f48370dfc908..270649012e64 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -286,6 +286,19 @@ static void cpu_device_release(struct device *dev)
*/
}
+#ifdef CONFIG_ARCH_HAS_CPU_AUTOPROBE
+static int cpu_uevent(struct device *dev, struct kobj_uevent_env *env)
+{
+ char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
+ if (buf) {
+ arch_print_cpu_modalias(NULL, NULL, buf);
+ add_uevent_var(env, "MODALIAS=%s", buf);
+ kfree(buf);
+ }
+ return 0;
+}
+#endif
+
/*
* register_cpu - Setup a sysfs device for a CPU.
* @cpu - cpu->hotpluggable field set to 1 will generate a control file in
@@ -307,7 +320,7 @@ int register_cpu(struct cpu *cpu, int num)
cpu->dev.offline = !cpu_online(num);
cpu->dev.of_node = of_get_cpu_node(num, NULL);
#ifdef CONFIG_ARCH_HAS_CPU_AUTOPROBE
- cpu->dev.bus->uevent = arch_cpu_uevent;
+ cpu->dev.bus->uevent = cpu_uevent;
#endif
cpu->dev.groups = common_cpu_attr_groups;
if (cpu->hotpluggable)
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 03e235ad1bba..dcc4a0d9c45f 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -47,7 +47,6 @@ extern ssize_t arch_cpu_release(const char *, size_t);
struct notifier_block;
#ifdef CONFIG_ARCH_HAS_CPU_AUTOPROBE
-extern int arch_cpu_uevent(struct device *dev, struct kobj_uevent_env *env);
extern ssize_t arch_print_cpu_modalias(struct device *dev,
struct device_attribute *attr,
char *bufptr);
--
1.8.3.2
^ permalink raw reply related
* [PATCH 0/5] generic CPU feature based udev module autoprobing
From: Ard Biesheuvel @ 2014-01-29 16:50 UTC (permalink / raw)
To: linux-arm-kernel
This series is a slightly expanded version of the series that I have proposed
before. It implements a generic way to wire up udev module autoprobing to
optional CPU features.
Patch #1 moves some code around to prevent duplication later.
Patch #2 implements the actual generic part. It relies on the include file
<asm/cpufeature.h> to be supplied by the architecture to map CPU features to
the number based scheme used by modalias.
Patch #3 aligns x86 with the generic code. As x86 allows matching on CPU vendor,
family and model IDs, it still retains most of the original code for creating
and matching the module metadata.
Patch #4 enables the generic implementation of patch #2 for arm64 by supplying
an 'asm/cpufeatures.h' that maps CPU feature numbers to bit offsets in
elf_hwcap, and by setting CONFIG_GENERIC_CPU_AUTOPROBE for the architecture.
Patch #5 is an example that maps an AES crypto module to the optional AES
feature found on arm64.
Ard Biesheuvel (5):
cpu: move arch_cpu_uevent() to generic code
cpu: add generic support for CPU feature based module autoloading
x86: align x86 arch with generic CPU modalias handling
arm64: enable generic CPU feature modalias matching for this
architecture
arm64: add Crypto Extensions based synchronous core AES cipher
arch/arm64/Kconfig | 1 +
arch/arm64/Makefile | 1 +
arch/arm64/crypto/Makefile | 13 +++++
arch/arm64/crypto/aes-ce-cipher.c | 103 ++++++++++++++++++++++++++++++++++++
arch/arm64/include/asm/cpufeature.h | 30 +++++++++++
arch/x86/Kconfig | 4 +-
arch/x86/include/asm/cpufeature.h | 7 +++
arch/x86/kernel/cpu/match.c | 42 ---------------
crypto/Kconfig | 6 +++
drivers/base/Kconfig | 3 ++
drivers/base/cpu.c | 46 ++++++++++++++--
include/linux/cpu.h | 7 ---
include/linux/cpufeature.h | 60 +++++++++++++++++++++
include/linux/mod_devicetable.h | 9 ++++
scripts/mod/devicetable-offsets.c | 3 ++
scripts/mod/file2alias.c | 20 +++++--
16 files changed, 293 insertions(+), 62 deletions(-)
create mode 100644 arch/arm64/crypto/Makefile
create mode 100644 arch/arm64/crypto/aes-ce-cipher.c
create mode 100644 arch/arm64/include/asm/cpufeature.h
create mode 100644 include/linux/cpufeature.h
--
1.8.3.2
^ permalink raw reply
* [PATCH v2 3/5] spi: sunxi: Add Allwinner A31 SPI controller driver
From: Mark Brown @ 2014-01-29 16:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140129133227.GQ3867@lukather>
On Wed, Jan 29, 2014 at 02:32:27PM +0100, Maxime Ripard wrote:
> On Wed, Jan 29, 2014 at 12:25:20PM +0000, Mark Brown wrote:
> > A select of PM_RUNTIME is both surprising and odd - why is that there?
> > The usual idiom is that the device starts out powered up (flagged using
> > pm_runtime_set_active()) and then runtime PM then suspends it when it's
> > compiled in. That way if for some reason people want to avoid runtime
> > PM they can still use the device.
> Since pm_runtime_set_active and all the pm_runtime* callbacks in
> general are defined to pretty much empty functions, how the
> suspend/resume callbacks are called then? Obviously, we need them to
> be run, hence why I added the select here, but now I'm seeing a
> construct like what's following acceptable then?
> pm_runtime_enable(&pdev->dev);
> if (!pm_runtime_enabled(&pdev->dev))
> sun6i_spi_runtime_resume(&pdev->dev);
I think you're looking for pm_request_idle() - just leave the device
started by default and kick the system to suspend it.
> Actually the IP asserts the CS automatically, the only thing you need
> to do is to set which CS to use for your next transfer in some
> register (which is what I'm doing after the !enable), and the CS will
> be managed directly by the controller. Hence, there's no way to say
> wether you want to enable it or not.
> The controller allows to control the CS manually also, if that's the
> preferred way of doing things.
Yes, that's required to provide set_cs() - it's there so that things
like the cs_change option in transfers can be factored out into the
core. We may in future want to integrate the ability to switch between
manual and automatic management but it's likely to be more trouble than
it's worth.
> > This means we can only transfer a single FIFO of data? I didn't see a
> > check on the transfer length.
> At the moment, indeed. And that's the first thing I check in the
> transfer_one function.
Oh, so it is - sorry.
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^ permalink raw reply
* imx6 power consumption
From: Bjørn Erik Nilsen @ 2014-01-29 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5DGxN9C_fOxZTmh0ev7wnpL9YP1g4tQjw4wpL2AmQPcog@mail.gmail.com>
On Wed, 2014-01-29 at 17:21 +0100, Fabio Estevam wrote:
> On Wed, Jan 29, 2014 at 2:17 PM, Bj?rn Erik Nilsen <ben@datarespons.no> wrote:
>
> >> I successfully managed to cherry-pick a handful of commits from
> >> freescale 3.10 and got down to approximately half the consumption.
> >> That's already very good news.
> >>
> >> Looking forward to see these patches upstream. Will you be able upstream
> >> them before 3.14 you think?
> >
> >
> > Any updates on this?
>
> Take a look at http://git.linaro.org/people/shawn.guo/linux-2.6.git/shortlog/refs/heads/for-next
> .
> There are some patches for low power support from Anson.
Excellent news!
It looks like these patches are exactly what is needed. I'm going to try
them out tomorrow.
Great piece of work, thank you!
^ permalink raw reply
* imx-drm: screen flickering
From: Russell King - ARM Linux @ 2014-01-29 16:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201401291553.15040.marex@denx.de>
On Wed, Jan 29, 2014 at 03:53:14PM +0100, Marek Vasut wrote:
> Isn't it the clock polarity being inverted thing again [1]?
>
> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-
> December/215536.html
>
> The easiest way to check this would be to try sig_cfg.clk_pol = 0
> or = 1 and see if it changes anything.
It seems that the pixel clock polarity on iMX hardware is something of
a mess. Some hardware blocks require one polarity, others require a
different polarity.
I think what would make sense is if the various output connectors/
encoders (in other words, imx-hdmi, imx-ldb, etc supplied their
properties concerning the clock polarity to the IPU layer.
We already have something like this in place already: we have the encoder
prepare functions calling into the ipuv3-crtc layer (via imx-drm-core) to
set the interface format, vsync/hsync pins, and clock flags - all of which
get used in the CRTC's mode_set method. Adding the clock polarity into
that path doesn't sound too difficult.
The only issue is that there's a lack of conflict management here - but
that's not a new problem with this approach - it exists with the existing
data.
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* [PATCH v3 0/2] Qualcomm Universal Peripheral (QUP) I2C controller
From: Bjorn Andersson @ 2014-01-29 16:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390983246.28998.24.camel@iivanov-dev.int.mm-sol.com>
On Wed, Jan 29, 2014 at 12:14 AM, Ivan T. Ivanov <iivanov@mm-sol.com> wrote:
>
> Hi Bjorn,
>
> On Fri, 2014-01-17 at 15:03 -0800, Bjorn Andersson wrote:
>> Continuing on Ivans i2c-qup series.
>>
>
> Do you plan to send v4 of this driver? I would like to address
> the remaining errors and suggestions and send a new version.
>
Hi Ivan,
Yes I'm planning to send out a new revision of the patch set.
I've incorporated fixes from the review comments here and my colleague
concluded through some testing that block read did not work, so we've
fixed that as well.
What have been holding me from submitting a new patchset is the 3
functions that does polling of state and status updates;
* qup_i2c_poll_state() reads the state register up to 1000 times,
hoping we reach the expected state, will delay 100uS and then continue
with 1000 more retries.
According to the data sheet a state transition is supposed to take
up to 2 bus cycles. Only time I can see that this would take longer
time are all error states, but the data sheet is not very clear
regarding this.
* qup_i2c_wait_idle() reads the status register up to 1000 times,
hoping the fifo gets drained and the bus go idle, if that fails it
sleeps for the time we expect it to take to drain a full fifo and then
loops another 1000 times. This waits for the fifo to have drained and
the bus to go idle. On a read we get to this state if we issue the
write and then hit the error state, so we would reset the entire
block. On write we will only wait for the buffer not to be full before
returning.
* qup_i2c_wait_clock_ready() waits up to 300 bus-clocks for the i2c
bus to go idle or forced low, I don't know why it retries 300 times.
This is called at the end of a write, possibly to wait for the fifo to
drain.
All three loops are in line with how it's been in codeaurora since the
beginning of time, but I at least need to figure out some good names
for those "magic numbers".
Regards,
Bjorn
^ permalink raw reply
* [PATCH 3/3] clk: divider: Optimize clk_divider_bestdiv loop
From: Maxime COQUELIN @ 2014-01-29 16:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391012648-12481-1-git-send-email-maxime.coquelin@st.com>
Currently, the for-loop used to try all the different dividers to find the
one that best fit tries all the values from 1 to max_div, incrementing by one.
In case of power-of-two, or table based divider, the loop isn't optimal.
Instead of incrementing by one, this patch provides directly the next divider.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
---
drivers/clk/clk-divider.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 1eaa5d8..4aabf4f 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -240,6 +240,18 @@ static bool _is_best_div(struct clk_divider *divider,
return now <= rate && now > best;
}
+static int _next_div(struct clk_divider *divider, int div)
+{
+ div++;
+
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ return __roundup_pow_of_two(div);
+ if (divider->table)
+ return _round_up_table(divider->table, div);
+
+ return div;
+}
+
static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
unsigned long *best_parent_rate)
{
@@ -267,7 +279,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
*/
maxdiv = min(ULONG_MAX / rate, maxdiv);
- for (i = 1; i <= maxdiv; i++) {
+ for (i = 1; i <= maxdiv; i = _next_div(divider, i)) {
if (!_is_valid_div(divider, i))
continue;
if (rate * i == parent_rate_saved) {
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/3] clk: divider: Add round to closest divider
From: Maxime COQUELIN @ 2014-01-29 16:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391012648-12481-1-git-send-email-maxime.coquelin@st.com>
In some cases, we want to be able to round the divider to the closest one,
instead than rounding up.
This patch adds a new CLK_DIVIDER_ROUND_CLOSEST flag to specify the divider
has to round to closest div, keeping rounding up as de default behaviour.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
---
drivers/clk/clk-divider.c | 69 ++++++++++++++++++++++++++++++++++++++++--
include/linux/clk-provider.h | 3 ++
2 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 2137d58..1eaa5d8 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -43,6 +43,17 @@ static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
return maxdiv;
}
+static unsigned int _get_table_mindiv(const struct clk_div_table *table)
+{
+ unsigned int mindiv = UINT_MAX;
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div < mindiv)
+ mindiv = clkt->div;
+ return mindiv;
+}
+
static unsigned int _get_maxdiv(struct clk_divider *divider)
{
if (divider->flags & CLK_DIVIDER_ONE_BASED)
@@ -162,6 +173,24 @@ static int _round_up_table(const struct clk_div_table *table, int div)
return up;
}
+static int _round_down_table(const struct clk_div_table *table, int div)
+{
+ const struct clk_div_table *clkt;
+ int down = _get_table_mindiv(table);
+
+ for (clkt = table; clkt->div; clkt++) {
+ if (clkt->div == div)
+ return clkt->div;
+ else if (clkt->div > div)
+ continue;
+
+ if ((div - clkt->div) < (div - down))
+ down = clkt->div;
+ }
+
+ return down;
+}
+
static int _div_round_up(struct clk_divider *divider,
unsigned long parent_rate, unsigned long rate)
{
@@ -175,6 +204,42 @@ static int _div_round_up(struct clk_divider *divider,
return div;
}
+static int _div_round_closest(struct clk_divider *divider,
+ unsigned long parent_rate, unsigned long rate)
+{
+ int up, down, div;
+
+ up = down = div = DIV_ROUND_CLOSEST(parent_rate, rate);
+
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) {
+ up = __roundup_pow_of_two(div);
+ down = __rounddown_pow_of_two(div);
+ } else if (divider->table) {
+ up = _round_up_table(divider->table, div);
+ down = _round_down_table(divider->table, div);
+ }
+
+ return (up - div) <= (div - down) ? up : down;
+}
+
+static int _div_round(struct clk_divider *divider, unsigned long parent_rate,
+ unsigned long rate)
+{
+ if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
+ return _div_round_closest(divider, parent_rate, rate);
+
+ return _div_round_up(divider, parent_rate, rate);
+}
+
+static bool _is_best_div(struct clk_divider *divider,
+ int rate, int now, int best)
+{
+ if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
+ return abs(rate - now) < abs(rate - best);
+
+ return now <= rate && now > best;
+}
+
static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
unsigned long *best_parent_rate)
{
@@ -190,7 +255,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
parent_rate = *best_parent_rate;
- bestdiv = _div_round_up(divider, parent_rate, rate);
+ bestdiv = _div_round(divider, parent_rate, rate);
bestdiv = bestdiv == 0 ? 1 : bestdiv;
bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
return bestdiv;
@@ -217,7 +282,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
MULT_ROUND_UP(rate, i));
now = parent_rate / i;
- if (now <= rate && now > best) {
+ if (_is_best_div(divider, rate, now, best)) {
bestdiv = i;
best = now;
*best_parent_rate = parent_rate;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7e59253..595f0ba 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -275,6 +275,8 @@ struct clk_div_table {
* of this register, and mask of divider bits are in higher 16-bit of this
* register. While setting the divider bits, higher 16-bit should also be
* updated to indicate changing divider bits.
+ * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
+ * to the closest integer instead of the up one.
*/
struct clk_divider {
struct clk_hw hw;
@@ -290,6 +292,7 @@ struct clk_divider {
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
#define CLK_DIVIDER_HIWORD_MASK BIT(3)
+#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
extern const struct clk_ops clk_divider_ops;
struct clk *clk_register_divider(struct device *dev, const char *name,
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/3] clk: divider: Fix best div calculation for power-of-two and table dividers
From: Maxime COQUELIN @ 2014-01-29 16:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391012648-12481-1-git-send-email-maxime.coquelin@st.com>
The divider returned by clk_divider_bestdiv() is likely to be invalid in case
of power-of-two and table dividers when CLK_SET_RATE_PARENT flag isn't set.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
---
drivers/clk/clk-divider.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 5543b7d..2137d58 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -144,6 +144,37 @@ static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
return true;
}
+static int _round_up_table(const struct clk_div_table *table, int div)
+{
+ const struct clk_div_table *clkt;
+ int up = _get_table_maxdiv(table);
+
+ for (clkt = table; clkt->div; clkt++) {
+ if (clkt->div == div)
+ return clkt->div;
+ else if (clkt->div < div)
+ continue;
+
+ if ((clkt->div - div) < (up - div))
+ up = clkt->div;
+ }
+
+ return up;
+}
+
+static int _div_round_up(struct clk_divider *divider,
+ unsigned long parent_rate, unsigned long rate)
+{
+ int div = DIV_ROUND_UP(parent_rate, rate);
+
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ div = __roundup_pow_of_two(div);
+ if (divider->table)
+ div = _round_up_table(divider->table, div);
+
+ return div;
+}
+
static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
unsigned long *best_parent_rate)
{
@@ -159,7 +190,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
parent_rate = *best_parent_rate;
- bestdiv = DIV_ROUND_UP(parent_rate, rate);
+ bestdiv = _div_round_up(divider, parent_rate, rate);
bestdiv = bestdiv == 0 ? 1 : bestdiv;
bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
return bestdiv;
@@ -219,6 +250,10 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
u32 val;
div = parent_rate / rate;
+
+ if (!_is_valid_div(divider, div))
+ return -EINVAL;
+
value = _get_val(divider, div);
if (value > div_mask(divider))
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/3] CCF clock divider changes
From: Maxime COQUELIN @ 2014-01-29 16:24 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mike,
First patch fixes round_rate for power-of-two and table-based dividers when
the CLK_SET_RATE_PARENT flag isn't set.
Second patch introduces a new flag to give the possibility to round the
divider to the closest one, instead of rounding up by default.
Third patch optimizes the for-loop when CLK_SET_RATE_PARENT is set for
power-of-two and table-based dividers.
The series applies on top of v3.13 tag.
Maxime Coquelin (3):
clk: divider: Fix best div calculation for power-of-two and table
dividers
clk: divider: Add round to closest divider
clk: divider: Optimize clk_divider_bestdiv loop
drivers/clk/clk-divider.c | 118 ++++++++++++++++++++++++++++++++++++++++--
include/linux/clk-provider.h | 3 ++
2 files changed, 118 insertions(+), 3 deletions(-)
--
1.7.9.5
^ permalink raw reply
* imx6 power consumption
From: Fabio Estevam @ 2014-01-29 16:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1W8XqE-0000Ml-GE@merlin.infradead.org>
On Wed, Jan 29, 2014 at 2:17 PM, Bj?rn Erik Nilsen <ben@datarespons.no> wrote:
>> I successfully managed to cherry-pick a handful of commits from
>> freescale 3.10 and got down to approximately half the consumption.
>> That's already very good news.
>>
>> Looking forward to see these patches upstream. Will you be able upstream
>> them before 3.14 you think?
>
>
> Any updates on this?
Take a look at http://git.linaro.org/people/shawn.guo/linux-2.6.git/shortlog/refs/heads/for-next
.
There are some patches for low power support from Anson.
Regards,
Fabio Estevam
^ permalink raw reply
* imx6 power consumption
From: Bjørn Erik Nilsen @ 2014-01-29 16:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1387440914.4131.4.camel@bnilsen-HP>
Hi guys,
On Thu, 2013-12-19 at 09:15 +0100, Bj?rn Erik Nilsen wrote:
> Hi Anson,
>
> On Thu, 2013-12-19 at 03:28 +0100, Anson.Huang at freescale.com wrote:
> >
> > Best Regards.
> > Anson huang ???
> >
> > Freescale Semiconductor Shanghai
> > ?????????192?A?2?
> > 201203
> > Tel:021-28937058
> >
> >
> > >-----Original Message-----
> > >From: linux-arm-kernel [mailto:linux-arm-kernel-bounces at lists.infradead.org]
> > >On Behalf Of Shawn Guo
> > >Sent: Wednesday, December 18, 2013 7:33 PM
> > >To: Bj?rn Erik Nilsen
> > >Cc: linux-arm-kernel at lists.infradead.org
> > >Subject: Re: imx6 power consumption
> > >
> > >On Wed, Dec 18, 2013 at 12:12:05PM +0100, Bj?rn Erik Nilsen wrote:
> > >> As far as I can tell, commit e95dddb34c8 "ARM: imx: enable anatop
> > >> suspend/resume" is the common ancestor for mainline and freescale, and
> > >> from there pm-imx6q.c starts to diverge.
> > >>
> > >> I haven not looked at it in great detail yet, but it seems there are
> > >> not too many patches missing in mainline. Any idea why remaining
> > >> patches haven't been upstreamed?
> > >
> > >Probably because no one cares and would spend time to upstream these patches.
> >
> > This root cause is we did NOT put the DSM code in IRAM and free DDR IO in DSM.
> > We have done this in our internal v3.10 kernel, so I will do the upstream soon,
> > Below is the DSM number of i.MX6Q SabreSD we got on v3.10 release:
> >
> > VDDARM_IN(R27) 0mA at 0.97V
> > VDDSOC_IN(R21) 4.2 at 0.97V
> > DDR(R25) 14.8mA at 1.5V
> > VDDHIGH_IN + SNVS(SH17) 0.35mA at 2.98V, 0.9mA
>
>
> I successfully managed to cherry-pick a handful of commits from
> freescale 3.10 and got down to approximately half the consumption.
> That's already very good news.
>
> Looking forward to see these patches upstream. Will you be able upstream
> them before 3.14 you think?
Any updates on this?
^ permalink raw reply
* [PATCH v2 08/11] of: Increase MAX_PHANDLE_ARGS
From: Suravee Suthikulanit @ 2014-01-29 16:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140117110830.GW3471@alberich>
On 1/17/2014 5:08 AM, Andreas Herrmann wrote:
>
> arm-smmu driver uses of_parse_phandle_with_args when parsing DT
> information to determine stream IDs for a master device.
> Thus the number of stream IDs per master device is bound by
> MAX_PHANDLE_ARGS.
>
> To support Calxeda ECX-2000 hardware arm-smmu driver requires a
> slightly higher value for MAX_PHANDLE_ARGS as this hardware has 10
> stream IDs for one master device.
>
> Increasing it to 16 seems a reasonable choice.
>
> Cc: Grant Likely <grant.likely@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree at vger.kernel.org
> Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
> ---
> include/linux/of.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/linux/of.h b/include/linux/of.h
> index 276c546..24e1b28 100644
> --- a/include/linux/of.h
> +++ b/include/linux/of.h
> @@ -67,7 +67,7 @@ struct device_node {
> #endif
> };
>
> -#define MAX_PHANDLE_ARGS 8
> +#define MAX_PHANDLE_ARGS 16
Since the MMU-500 specify "Number of SMRs" upto 128 registers, shouldn't
this be changed to be able to support 128 StreamIDs as well? Although I
am not sure if this would be too big to have on the stack per Rob's
comment in the previous patch set.
Thank you,
Suravee
^ permalink raw reply
* [PATCH] ARM: imx6: Initialize low-power mode early again
From: Philipp Zabel @ 2014-01-29 16:10 UTC (permalink / raw)
To: linux-arm-kernel
Since commit 9e8147bb5ec5d1dda2141da70f96b98985a306cb
"ARM: imx6q: move low-power code out of clock driver"
the kernel fails to boot on i.MX6Q/D if preemption is
enabled (CONFIG_PREEMPT=y). The kernel just hangs
before the console comes up.
The above commit moved the initalization of the low-power
mode setting (enabling clocked WAIT states), which was
introduced in commit 83ae20981ae924c37d02a42c829155fc3851260c
"ARM: imx: correct low-power mode setting", from
imx6q_clks_init to imx6q_pm_init. Now it is called
much later, after all cores are enabled.
This patch moves the low-power mode initialization back
to imx6q_clks_init again (and to imx6sl_clks_init).
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
arch/arm/mach-imx/clk-imx6q.c | 3 +++
arch/arm/mach-imx/clk-imx6sl.c | 3 +++
arch/arm/mach-imx/pm-imx6q.c | 2 --
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index af2e582..4d677f4 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -482,6 +482,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
if (IS_ENABLED(CONFIG_PCI_IMX6))
clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
+ /* Set initial power mode */
+ imx6q_set_lpm(WAIT_CLOCKED);
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 78f3bd6..6617ac8 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -299,6 +299,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
/* Audio-related clocks configuration */
clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
+ /* Set initial power mode */
+ imx6q_set_lpm(WAIT_CLOCKED);
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index c8fea8f..a9a187d 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -532,8 +532,6 @@ static void __init imx6_pm_common_init(const struct imx6_pm_socdata
regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
IMX6Q_GPR1_GINT);
- /* Set initial power mode */
- imx6q_set_lpm(WAIT_CLOCKED);
suspend_set_ops(&imx6q_pm_ops);
}
--
1.8.5.3
^ permalink raw reply related
* PCIe trouble on imx6q
From: Kamel BOUHARA @ 2014-01-29 15:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAErSpo6MnY74S=jEemQ9xKDg0xik616MeNE67vROap3orQohGA@mail.gmail.com>
2014-01-29 Bjorn Helgaas <bhelgaas@google.com>:
> [+cc linux-arm, Richard, Shawn (please keep the cc list)]
>
> On Wed, Jan 29, 2014 at 2:28 AM, Kamel BOUHARA <k.bouhara@gmail.com> wrote:
>> ---------- Forwarded message ----------
>> From: Kamel BOUHARA <k.bouhara@gmail.com>
>> Date: 2014-01-29
>> Subject: Re: PCIe trouble on imx6q
>> To: Bjorn Helgaas <bhelgaas@google.com>
>>
>>
>> 2014-01-28 Bjorn Helgaas <bhelgaas@google.com>:
>>> [+cc Richard, Shawn, linux-arm-kernel (all from MAINTAINERS)]
>>>
>>> On Tue, Jan 28, 2014 at 1:02 AM, Kamel BOUHARA <k.bouhara@gmail.com> wrote:
>>>> Hello,
>>>>
>>>> Im getting trouble with kernel 3.13 at boot time, the pcie link failed
>>>> to get up with the following log:
>>>> ------------[ cut here ]------------
>>>> WARNING: CPU: 0 PID: 1 at drivers/gpio/gpiolib.c:159 gpio_to_desc+0x34/0x48()
>>>> invalid GPIO -2
>>>> Modules linked in:
>>>> CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0+ #4
>>>> Backtrace:
>>>> [<8001217c>] (dump_backtrace) from [<80012460>] (show_stack+0x18/0x1c)
>>>> r6:802b9548 r5:00000000 r4:808d3060 r3:00000000
>>>> [<80012448>] (show_stack) from [<806414fc>] (dump_stack+0x84/0x9c)
>>>> [<80641478>] (dump_stack) from [<800289f8>] (warn_slowpath_common+0x70/0x94)
>>>> r5:00000009 r4:bf05bcb0
>>>> [<80028988>] (warn_slowpath_common) from [<80028a54>]
>>>> (warn_slowpath_fmt+0x38/0x40)
>>>> r8:01f00000 r7:00000000 r6:0011cc11 r5:808b68c0 r4:bf24fa30
>>>> [<80028a20>] (warn_slowpath_fmt) from [<802b9548>] (gpio_to_desc+0x34/0x48)
>>>> r3:fffffffe r2:807d23fc
>>>> [<802b9514>] (gpio_to_desc) from [<802d9de0>] (imx6_pcie_host_init+0x174/0x434)
>>>> [<802d9c6c>] (imx6_pcie_host_init) from [<80886dbc>]
>>>> (dw_pcie_host_init+0x348/0x41c)
>>>> r6:00000000 r5:808d52cc r4:00000020 r3:802d9c6c
>>>> [<80886a74>] (dw_pcie_host_init) from [<808871d4>] (imx6_pcie_probe+0x320/0x3dc)
>>>> r10:00000000 r9:000000c4 r8:808d539c r7:bf7e3384 r6:bf24fa30 r5:bf135810
>>>> r4:bf24fa10
>>>> [<80886eb4>] (imx6_pcie_probe) from [<8034b670>] (platform_drv_probe+0x20/0x50)
>>>> r8:808d539c r7:00000000 r6:00000000 r5:808d539c r4:bf135810
>>>> [<8034b650>] (platform_drv_probe) from [<80349c74>]
>>>> (driver_probe_device+0x118/0x234)
>>>> r5:bf135810 r4:80e526b8
>>>> [<80349b5c>] (driver_probe_device) from [<80349e78>] (__driver_attach+0x9c/0xa0)
>>>> r8:80886e90 r7:00000000 r6:bf135844 r5:808d539c r4:bf135810 r3:00000000
>>>> [<80349ddc>] (__driver_attach) from [<8034806c>] (bus_for_each_dev+0x68/0x9c)
>>>> r6:80349ddc r5:808d539c r4:00000000 r3:00000000
>>>> [<80348004>] (bus_for_each_dev) from [<8034972c>] (driver_attach+0x20/0x28)
>>>> r6:808df6a8 r5:bf1f5e00 r4:808d539c
>>>> [<8034970c>] (driver_attach) from [<803493b0>] (bus_add_driver+0x148/0x1f4)
>>>> [<80349268>] (bus_add_driver) from [<8034a4c8>] (driver_register+0x80/0x100)
>>>> r7:8090e640 r6:8090e640 r5:00000005 r4:808d539c
>>>> [<8034a448>] (driver_register) from [<8034b63c>]
>>>> (__platform_driver_register+0x50/0x64)
>>>> r5:00000005 r4:808d5388
>>>> [<8034b5ec>] (__platform_driver_register) from [<8034b6e0>]
>>>> (platform_driver_probe+0x28/0xac)
>>>> [<8034b6b8>] (platform_driver_probe) from [<80886ea8>]
>>>> (imx6_pcie_init+0x18/0x24)
>>>> r5:00000005 r4:808aa104
>>>> [<80886e90>] (imx6_pcie_init) from [<80008978>] (do_one_initcall+0x100/0x164)
>>>> [<80008878>] (do_one_initcall) from [<8085ecc0>]
>>>> (kernel_init_freeable+0x10c/0x1d0)
>>>> r10:8089e060 r9:000000c4 r8:8089e050 r7:8090e640 r6:8090e640 r5:00000005
>>>> r4:808aa104
>>>> [<8085ebb4>] (kernel_init_freeable) from [<8063b67c>] (kernel_init+0x10/0x120)
>>>> r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:8063b66c
>>>> r4:00000000
>>>> [<8063b66c>] (kernel_init) from [<8000e9c8>] (ret_from_fork+0x14/0x2c)
>>>> r4:00000000 r3:ffffffff
>>>> ---[ end trace b5e746dfc2398cd6 ]---
>>>> ------------[ cut here ]------------
>>>> WARNING: CPU: 0 PID: 1 at drivers/gpio/gpiolib.c:159 gpio_to_desc+0x34/0x48()
>>>> invalid GPIO -2
>>>> Modules linked in:
>>>> CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.13.0+ #4
>>>> Backtrace:
>>>> [<8001217c>] (dump_backtrace) from [<80012460>] (show_stack+0x18/0x1c)
>>>> r6:802b9548 r5:00000000 r4:808d3060 r3:00000000
>>>> [<80012448>] (show_stack) from [<806414fc>] (dump_stack+0x84/0x9c)
>>>> [<80641478>] (dump_stack) from [<800289f8>] (warn_slowpath_common+0x70/0x94)
>>>> r5:00000009 r4:bf05bcb0
>>>> [<80028988>] (warn_slowpath_common) from [<80028a54>]
>>>> (warn_slowpath_fmt+0x38/0x40)
>>>> r8:01f00000 r7:00000000 r6:0011cc11 r5:808b68c0 r4:bf24fa30
>>>> [<80028a20>] (warn_slowpath_fmt) from [<802b9548>] (gpio_to_desc+0x34/0x48)
>>>> r3:fffffffe r2:807d23fc
>>>> [<802b9514>] (gpio_to_desc) from [<802d9df8>] (imx6_pcie_host_init+0x18c/0x434)
>>>> [<802d9c6c>] (imx6_pcie_host_init) from [<80886dbc>]
>>>> (dw_pcie_host_init+0x348/0x41c)
>>>> r6:00000000 r5:808d52cc r4:00000020 r3:802d9c6c
>>>> [<80886a74>] (dw_pcie_host_init) from [<808871d4>] (imx6_pcie_probe+0x320/0x3dc)
>>>> r10:00000000 r9:000000c4 r8:808d539c r7:bf7e3384 r6:bf24fa30 r5:bf135810
>>>> r4:bf24fa10
>>>> [<80886eb4>] (imx6_pcie_probe) from [<8034b670>] (platform_drv_probe+0x20/0x50)
>>>> r8:808d539c r7:00000000 r6:00000000 r5:808d539c r4:bf135810
>>>> [<8034b650>] (platform_drv_probe) from [<80349c74>]
>>>> (driver_probe_device+0x118/0x234)
>>>> r5:bf135810 r4:80e526b8
>>>> [<80349b5c>] (driver_probe_device) from [<80349e78>] (__driver_attach+0x9c/0xa0)
>>>> r8:80886e90 r7:00000000 r6:bf135844 r5:808d539c r4:bf135810 r3:00000000
>>>> [<80349ddc>] (__driver_attach) from [<8034806c>] (bus_for_each_dev+0x68/0x9c)
>>>> r6:80349ddc r5:808d539c r4:00000000 r3:00000000
>>>> [<80348004>] (bus_for_each_dev) from [<8034972c>] (driver_attach+0x20/0x28)
>>>> r6:808df6a8 r5:bf1f5e00 r4:808d539c
>>>> [<8034970c>] (driver_attach) from [<803493b0>] (bus_add_driver+0x148/0x1f4)
>>>> [<80349268>] (bus_add_driver) from [<8034a4c8>] (driver_register+0x80/0x100)
>>>> r7:8090e640 r6:8090e640 r5:00000005 r4:808d539c
>>>> [<8034a448>] (driver_register) from [<8034b63c>]
>>>> (__platform_driver_register+0x50/0x64)
>>>> r5:00000005 r4:808d5388
>>>> [<8034b5ec>] (__platform_driver_register) from [<8034b6e0>]
>>>> (platform_driver_probe+0x28/0xac)
>>>> [<8034b6b8>] (platform_driver_probe) from [<80886ea8>]
>>>> (imx6_pcie_init+0x18/0x24)
>>>> r5:00000005 r4:808aa104
>>>> [<80886e90>] (imx6_pcie_init) from [<80008978>] (do_one_initcall+0x100/0x164)
>>>> [<80008878>] (do_one_initcall) from [<8085ecc0>]
>>>> (kernel_init_freeable+0x10c/0x1d0)
>>>> r10:8089e060 r9:000000c4 r8:8089e050 r7:8090e640 r6:8090e640 r5:00000005
>>>> r4:808aa104
>>>> [<8085ebb4>] (kernel_init_freeable) from [<8063b67c>] (kernel_init+0x10/0x120)
>>>> r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:8063b66c
>>>> r4:00000000
>>>> [<8063b66c>] (kernel_init) from [<8000e9c8>] (ret_from_fork+0x14/0x2c)
>>>> r4:00000000 r3:ffffffff
>>>> ---[ end trace b5e746dfc2398cd7 ]---
>>>> imx6q-pcie 1ffc000.pcie: phy link never came up
>>>> PCI host bridge to bus 0000:00
>>>> pci_bus 0000:00: root bus resource [io 0x1000-0x10000]
>>>> pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]
>>>> pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
>>>
>>> Not related to the GPIO/link problem, but something's wrong here --
>>> the host bridge driver should be telling us what bus numbers are
>>> behind the host bridge. Since it didn't, the PCI core had to guess.
>>>
>>>> PCI: bus0: Fast back to back transfers disabled
>>>> PCI: bus1: Fast back to back transfers enabled
>>>> pci 0000:00:00.0: BAR 0: assigned [mem 0x01000000-0x010fffff]
>>>> pci 0000:00:00.0: BAR 6: assigned [mem 0x01100000-0x0110ffff pref]
>>>> pci 0000:00:00.0: PCI bridge to [bus 01]
>>>> pci 0000:00:00.0: PCI bridge to [bus 01]
>>>>
>>>> Please, any help is welcome.
>>>> Regards,
>>>> Kamel.B
>>>> --
>>>> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>>>> the body of a message to majordomo at vger.kernel.org
>>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>> So I suppose, this is not a hardware issue rather a bad configuration ?
>> Maybe the following log from lspci will be helpful ?
>
> It looks like a configuration issue or an imx6q host bridge issue. In
> either case, it looks like something *before* we get to PCIe, so
> something like your DT description of the host bridge is more likely
> to be useful.
>
>> root at phyFLEX-i:~ lspci -vvv
>> 00:00.0 PCI bridge: Device 16c3:abcd (rev 01) (prog-if 00 [Normal decode])
>> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
>> ParErr+ Stepping- SERR+ FastB2B- DisINTx+
>> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
>> <TAbort- <MAbort- >SERR- <PERR- INTx-
>> Latency: 0, Cache Line Size: 64 bytes
>> Region 0: Memory at 01000000 (32-bit, non-prefetchable) [size=1M]
>> Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
>> I/O behind bridge: 0000f000-00000fff
>> Memory behind bridge: fff00000-000fffff
>> Prefetchable memory behind bridge: fff00000-000fffff
>> Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort-
>> <TAbort- <MAbort- <SERR- <PERR-
>> [virtual] Expansion ROM at 01100000 [disabled] [size=64K]
>> BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
>> PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
>> Capabilities: [40] Power Management version 3
>> Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA
>> PME(D0+,D1+,D2-,D3hot+,D3cold+)
>> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
>> Capabilities: [50] MSI: Mask+ 64bit+ Count=1/1 Enable+
>> Address: 0000000090000000 Data: 0000
>> Masking: 00000000 Pending: 00000000
>> Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
>> DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s
>> <64ns, L1 <1us
>> ExtTag- RBE+ FLReset-
>> DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+
>> Unsupported+
>> RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
>> MaxPayload 128 bytes, MaxReadReq 512 bytes
>> DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq-
>> AuxPwr+ TransPend-
>> LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1,
>> Latency L0 <1us, L1 <8us
>> ClockPM- Surprise- LLActRep+ BwNot-
>> LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
>> ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
>> LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train-
>> SlotClk+ DLActive- BWMgmt- ABWMgmt-
>> RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal-
>> PMEIntEna+ CRSVisible-
>> RootCap: CRSVisible-
>> RootSta: PME ReqID 0000, PMEStatus- PMEPending-
>> DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd-
>> DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd-
>> LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance-
>> SpeedDis-, Selectable De-emphasis: -6dB
>> Transmit Margin: Normal Operating Range,
>> EnterModifiedCompliance- ComplianceSOS-
>> Compliance De-emphasis: -6dB
>> LnkSta2: Current De-emphasis Level: -3.5dB
>> Capabilities: [100] Advanced Error Reporting
>> UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt-
>> UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
>> UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt-
>> UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
>> UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt-
>> UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
>> CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
>> CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
>> AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
>> Capabilities: [140] Virtual Channel <?>
>> Kernel driver in use: pcieport
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
Ok, actually I didn't get the host bridge set properly for my board,
here is my DT:
/dts-v1/;
#include "imx6q-phytec-pfla02.dtsi"
/ {
model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board";
compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q";
};
&fec {
status = "okay";
};
&uart4 {
status = "okay";
};
&usdhc2 {
status = "okay";
};
&usdhc3 {
status = "okay";
};
&pcie {
status = "okay";
};
Can you give me a example of host configuration ?
BR, Kamel.B
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