* [PATCH] ARM: keystone: dts: disable "msmcsram" clock
From: Santosh Shilimkar @ 2014-01-30 14:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52EA5A8F.7070107@ti.com>
On Thursday 30 January 2014 08:58 AM, Ivan Khoronzhuk wrote:
> Ok. I will delete node for this clock from DT and send v1
>
Sorry for the html reply first of all. That node should never have
been actually added since the clock is not suppose to be touched even
in low power states. Change log should say something like this ...
"MSMC is the coherency interconnect and all the coherent masters are
connected to it including devices which are not under Linux OS control.
MSMC clock should not be toched even in low power states."
So drop the clock node o.w without 'clk_ignore_unused' will disable
the clock leading to system stall.
I wil try get these in rc's since its a bug fix
Regards,
Santosh
^ permalink raw reply
* 'unannotated irqs-on' lockdep warning
From: Christian Gmeiner @ 2014-01-30 14:31 UTC (permalink / raw)
To: linux-arm-kernel
I got this lockdep warning on an imx6q with 3.12.4
uncompressing Linux... done, booting the kernel.
Loading, please wait...
[ 19.835411] ------------[ cut here ]------------
[ 19.840069] WARNING: CPU: 0 PID: 1848 at kernel/lockdep.c:3539
check_flags.part.26+0xb4/0x1e4()
[ 19.848775] DEBUG_LOCKS_WARN_ON(!current->hardirqs_enabled)
[ 19.854180] Modules linked in: ipv6 rotary_encoder
[ 19.859234] CPU: 0 PID: 1848 Comm: mkdir Not tainted 3.12.4 #44
[ 19.865190] [<c0013900>] (unwind_backtrace+0x0/0xe0) from
[<c00113b8>] (show_stack+0x10/0x14)
[ 19.873739] [<c00113b8>] (show_stack+0x10/0x14) from [<c044e040>]
(dump_stack+0x64/0xa4)
[ 19.881851] [<c044e040>] (dump_stack+0x64/0xa4) from [<c0022718>]
(warn_slowpath_common+0x64/0x84)
[ 19.890828] [<c0022718>] (warn_slowpath_common+0x64/0x84) from
[<c00227b8>] (warn_slowpath_fmt+0x2c/0x3c)
[ 19.900413] [<c00227b8>] (warn_slowpath_fmt+0x2c/0x3c) from
[<c0076c84>] (check_flags.part.26+0xb4/0x1e4)
[ 19.910001] [<c0076c84>] (check_flags.part.26+0xb4/0x1e4) from
[<c0079654>] (lock_release+0x3c/0x100)
[ 19.919243] [<c0079654>] (lock_release+0x3c/0x100) from
[<c00485b4>] (lg_local_unlock+0x18/0x6c)
[ 19.928055] [<c00485b4>] (lg_local_unlock+0x18/0x6c) from
[<c012a2cc>] (free_fs_struct+0x18/0x30)
[ 19.936947] [<c012a2cc>] (free_fs_struct+0x18/0x30) from
[<c0024e24>] (do_exit+0x2ac/0x3f0)
[ 19.945316] [<c0024e24>] (do_exit+0x2ac/0x3f0) from [<c002501c>]
(do_group_exit+0x88/0xb4)
[ 19.953596] [<c002501c>] (do_group_exit+0x88/0xb4) from
[<c0025058>] (__wake_up_parent+0x0/0x18)
[ 19.962391] ---[ end trace 98a70b5cdc7b49fe ]---
[ 19.967017] possible reason: unannotated irqs-on.
[ 19.971729] irq event stamp: 2910
[ 19.975050] hardirqs last enabled at (2909): [<c044a160>]
__slab_free+0x1c0/0x390
[ 19.982661] hardirqs last disabled at (2910): [<c0456d14>]
__dabt_svc+0x34/0x60
[ 19.990007] softirqs last enabled at (2788): [<c0026ed4>]
__do_softirq+0x2a0/0x2e0
[ 19.997696] softirqs last disabled at (2763): [<c0026fac>]
do_softirq+0x48/0x6c
[ 20.573919] fec 2188000.ethernet eth0: Freescale FEC PHY driver
[Generic PHY] (mii_bus:phy_addr=fixed-0:00, irq=-1)
[ 20.592644] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 21.790278] input: frontkey-keyboard as /devices/virtual/input/input2
[ 21.815455] input: rotary-keyboard as /devices/virtual/input/input3
[ 22.572591] libphy: fixed-0:00 - Link is Up - 100/Full
[ 22.577819] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
--
Christian Gmeiner, MSc
^ permalink raw reply
* NFS client broken in Linus' tip
From: Christoph Hellwig @ 2014-01-30 14:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140130142752.GX15937@n2100.arm.linux.org.uk>
On Thu, Jan 30, 2014 at 02:27:52PM +0000, Russell King - ARM Linux wrote:
> Yes and no. I still end up with an empty /etc/mtab, but the file now
> exists. However, I can create and echo data into /etc/mtab, but it seems
> that can't happen at boot time.
Odd. Can you disable CONFIG_NFSD_V3_ACL for now to isolate the issue?
I'll be out for a long weekend soon, so I have very limited time to
debug things until Monday.
^ permalink raw reply
* [PATCH] clk: keystone: gate: fix clk_init_data initialization
From: Santosh Shilimkar @ 2014-01-30 14:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52EA5866.3090706@ti.com>
On Thursday 30 January 2014 08:49 AM, Ivan Khoronzhuk wrote:
> Yes. As result the clk->flag field contains garbage. In my case it leads
> that flag CLK_IGNORE_UNUSED is set for most of clocks. As result a bunch
> of unused clocks cannot be disabled.
>
Can you please update the change log with above information.
> On 01/30/2014 03:26 PM, Shilimkar, Santosh wrote:
>> Can u capture the issue withiout this fix?
>>
>> Sent from my Android phone using TouchDown (www.nitrodesk.com)
>>
>> -----Original Message-----
>> *From:* Khoronzhuk, Ivan [ivan.khoronzhuk at ti.com]
>> *Received:* Thursday, 30 Jan 2014, 6:37am
>> *To:* Shilimkar, Santosh [santosh.shilimkar at ti.com]
>> *CC:* mturquette at linaro.org [mturquette at linaro.org];
>> linux-arm-kernel at lists.infradead.org [linux-arm-kernel at lists.infradead.org];
>> linux-kernel at vger.kernel.org [linux-kernel at vger.kernel.org]; Khoronzhuk, Ivan
>> [ivan.khoronzhuk at ti.com]
>> *Subject:* [PATCH] clk: keystone: gate: fix clk_init_data initialization
>>
>> In clk_register_psc() function clk_init_data struct is allocated
>> in the stack. All members of this struct should be initialized
>> before using otherwise it will contain garbage. So initialize flags
>> in this structure too.
>>
>> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
>> ---
>> drivers/clk/keystone/gate.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/clk/keystone/gate.c b/drivers/clk/keystone/gate.c
>> index 17a5983..86f1e36 100644
>> --- a/drivers/clk/keystone/gate.c
>> +++ b/drivers/clk/keystone/gate.c
>> @@ -179,6 +179,7 @@ static struct clk *clk_register_psc(struct device *dev,
>>
>> init.name = name;
>> init.ops = &clk_psc_ops;
>> + init.flags = 0;
>> init.parent_names = (parent_name ? &parent_name : NULL);
>> init.num_parents = (parent_name ? 1 : 0);
>>
>> --
>> 1.8.3.2
>>
>
^ permalink raw reply
* [PATCH V2 0/4] misc: xgene: Add support for APM X-Gene SoC Queue Manager/Traffic Manager
From: Arnd Bergmann @ 2014-01-30 14:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAN1v_Ps9U=yjG-G40FK+L9SLaAQp7s8j9mg9DNoiGwqjMiGtiQ@mail.gmail.com>
On Tuesday 28 January 2014, Ravi Patel wrote:
> On Tue, Jan 14, 2014 at 7:15 AM, Arnd Bergmann <arnd@arndb.de> wrote:
-
> > For the DT binding, I would suggest using something along the lines of
> > what we have for clocks, pinctrl and dmaengine. OMAP doesn't use this
> > (yet), but now would be a good time to standardize it. The QMTM node
> > should define a "#mailbox-cells" property that indicates how many
> > 32-bit cells a qmtm needs to describe the connection between the
> > controller and the slave. My best guess is that this would be hardcoded
> > to <3>, using two cells for a 64-bit FIFO bus address, and a 32-bit cell
> > for the slave-id signal number. All other parameters that you have in
> > the big table in the qmtm driver at the moment can then get moved into
> > the slave drivers, as they are constant per type of slave. This will
> > simplify the QMTM driver.
> >
> > In the slave, you should have a "mailboxes" property with a phandle
> > to the qmtm followed by the three cells to identify the actual
> > queue. If it's possible that a device uses more than one rx and
> > one tx queue, we also need a "mailbox-names" property to identify
> > the individual queues.
>
> We explored on DT bindings suggestion given by you. We have come
> up with a sample DT binding for how it will look like. Herewith we have
> provided the same. Would you please review and give us your
> comments before we change our driver and DTS file to accomodate it?
>
> Sample DTS node for QM:
> qmlite: qmtm at 17030000 {
> compatible = "apm,xgene-qmtm-lite";
I would use 'mailbox at 17030000' as the node name, as the name part
is supposed to be descriptive of the function rather than the implemention.
> reg = <0x0 0x17030000 0x0 0x10000>,
> <0x0 0x10000000 0x0 0x400000>;
> interrupts = <0x0 0x40 0x4>,
> <0x0 0x3c 0x4>;
> status = "ok";
> #clock-cells = <1>;
> clocks = <&qmlclk 0>;
> #mailbox-cells = <3>;
> };
The #clock-cells seems misplaced here, unless this is also a clock
provider, which I don't think it is.
>
> Sample DTS node for Ethernet:
> menet: ethernet at 17020000 {
> compatible = "apm,xgene-enet";
> status = "disabled";
> reg = <0x0 0x17020000 0x0 0x30>,
> <0x0 0x17020000 0x0 0x10000>,
> <0x0 0x17020000 0x0 0x20>;
Unrelated, but it seems strange to have three register sets of different
sizes at the same offset.
> mailboxes = <&qmlite 0x0 0x1000002c 0x0000>,
> <&qmlite 0x0 0x10000052 0x0020>,
> <&qmlite 0x0 0x10000060 0x0f00>
> mailbox-names = "mb-tx", "mb-fp", "mb-rx";
I would leave out the "mb-" part of the strings and just document them
as "tx", "rx" and "fp".
> interrupts = <0x0 0x38 0x4>,
> <0x0 0x39 0x4>,
> <0x0 0x3a 0x4>;
> #clock-cells = <1>;
Same comment about #clock-cells here.
> clocks = <ð8clk 0>;
> local-mac-address = <0x0 0x11 0x3a 0x8a 0x5a 0x78>;
> max-frame-size = <0x233a>;
> phyid = <3>;
> phy-mode = "rgmii";
> };
>
> The mailbox node in DTS has following format:
> mailbox = <&parent 'higher 32 bit bus address' 'lower 32 bit bus
> address' 'signal id'>
sounds good.
> Ethernet driver will call following function in platform_probe:
> mailbox_get(dev, "mb-tx");
> mailbox_get API will return the the context of allocated and configured mailbox.
> For now, mailbox_get API will be implemented in xgene QMTM driver.
> Eventually when mailbox framework in Linux will be standardized, we
> will use it instead.
Ok.
> > For the in-kernel interfaces, we should probably start a conversation
> > with the owners of the mailbox drivers to get a common API, for now
> > I'd suggest you just leave it as it is, and only adapt for the new
> > binding.
>
> Sure. For now we will put our driver mostly as is in the
> drivers/mailbox. Can you please help us identify the owners of the
> mailbox drivers? As you suggested, we can start conversation with them
> to define common in kernel APIs.
Please talk to "Suman Anna" <s-anna@ti.com> for the TI part and Rob
Herring <robh@kernel.org> for pl320. The pl320 driver was written
by Mark Langsdorf for Calxeda, but I don't have an updated email
address for him and assume that the calxeda address is no longer
functional.
Arnd
^ permalink raw reply
* [RFC PATCH pre-v3 08/14] mtd: nand: add sunxi NAND flash controller support
From: Russell King - ARM Linux @ 2014-01-30 14:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391089176-8147-1-git-send-email-b.brezillon.dev@gmail.com>
Boris,
Can you please explain to me why you mail all your patches _To:_ me?
As in, why do I appear in the To: line of all the patches you seem to
mail out, whether or not they're relevant to me. I see this very
regularly from you - virtually all patches I see on the LAKML mailing
list from you are always sent To: me as well.
Take for instance this one. It doesn't match up with anything in
MAINTAINERS for me. It doesn't even touch a file that I've touched.
Yet somehow you think that I should be in the To: header.
Being in the To: header means that you expect the recipient to do
something with your email. The Cc: header is to circulate copies of
your email to people who may be interested.
I'm neither for this stuff. Please stop this.
Thanks.
On Thu, Jan 30, 2014 at 02:39:36PM +0100, Boris BREZILLON wrote:
> Add support for the sunxi NAND Flash Controller (NFC).
>
> Signed-off-by: Boris BREZILLON <b.brezillon.dev@gmail.com>
> ---
> Hello,
>
> This version fixes a bug in the R/B GPIO config block.
> The timing config order is now respected, but I'll wait for Jason work
> regarding timing config in NAND core code before posting the 3rd version
> of this series.
>
> Best Regards,
>
> Boris
>
> Changes since v2:
> - fix R/B GPIO retrieval/config bug
> - fix timings configuration order (set mode 0 -> scan -> set best supported
> mode)
>
> drivers/mtd/nand/Kconfig | 6 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/sunxi_nand.c | 758 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 765 insertions(+)
> create mode 100644 drivers/mtd/nand/sunxi_nand.c
>
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 93ae6a6..784dd42 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -510,4 +510,10 @@ config MTD_NAND_XWAY
> Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
> to the External Bus Unit (EBU).
>
> +config MTD_NAND_SUNXI
> + tristate "Support for NAND on Allwinner SoCs"
> + depends on ARCH_SUNXI
> + help
> + Enables support for NAND Flash chips on Allwinner SoCs.
> +
> endif # MTD_NAND
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index bbea7a6..e3b4a34 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
> obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
> obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
> obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
> +obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
>
> nand-objs := nand_base.o nand_bbt.o
> diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
> new file mode 100644
> index 0000000..1014b2a
> --- /dev/null
> +++ b/drivers/mtd/nand/sunxi_nand.c
> @@ -0,0 +1,758 @@
> +/*
> + * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
> + *
> + * Derived from:
> + * https://github.com/yuq/sunxi-nfc-mtd
> + * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
> + *
> + * https://github.com/hno/Allwinner-Info
> + * Copyright (C) 2013 Henrik Nordstr?m <Henrik Nordstr?m>
> + *
> + * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
> + * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/slab.h>
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_mtd.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/dmaengine.h>
> +#include <linux/gpio.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +
> +#define NFC_REG_CTL 0x0000
> +#define NFC_REG_ST 0x0004
> +#define NFC_REG_INT 0x0008
> +#define NFC_REG_TIMING_CTL 0x000C
> +#define NFC_REG_TIMING_CFG 0x0010
> +#define NFC_REG_ADDR_LOW 0x0014
> +#define NFC_REG_ADDR_HIGH 0x0018
> +#define NFC_REG_SECTOR_NUM 0x001C
> +#define NFC_REG_CNT 0x0020
> +#define NFC_REG_CMD 0x0024
> +#define NFC_REG_RCMD_SET 0x0028
> +#define NFC_REG_WCMD_SET 0x002C
> +#define NFC_REG_IO_DATA 0x0030
> +#define NFC_REG_ECC_CTL 0x0034
> +#define NFC_REG_ECC_ST 0x0038
> +#define NFC_REG_DEBUG 0x003C
> +#define NFC_REG_ECC_CNT0 0x0040
> +#define NFC_REG_ECC_CNT1 0x0044
> +#define NFC_REG_ECC_CNT2 0x0048
> +#define NFC_REG_ECC_CNT3 0x004c
> +#define NFC_REG_USER_DATA_BASE 0x0050
> +#define NFC_REG_SPARE_AREA 0x00A0
> +#define NFC_RAM0_BASE 0x0400
> +#define NFC_RAM1_BASE 0x0800
> +
> +/*define bit use in NFC_CTL*/
> +#define NFC_EN (1 << 0)
> +#define NFC_RESET (1 << 1)
> +#define NFC_BUS_WIDYH (1 << 2)
> +#define NFC_RB_SEL (1 << 3)
> +#define NFC_CE_SEL (7 << 24)
> +#define NFC_CE_CTL (1 << 6)
> +#define NFC_CE_CTL1 (1 << 7)
> +#define NFC_PAGE_SIZE (0xf << 8)
> +#define NFC_SAM (1 << 12)
> +#define NFC_RAM_METHOD (1 << 14)
> +#define NFC_DEBUG_CTL (1 << 31)
> +
> +/*define bit use in NFC_ST*/
> +#define NFC_RB_B2R (1 << 0)
> +#define NFC_CMD_INT_FLAG (1 << 1)
> +#define NFC_DMA_INT_FLAG (1 << 2)
> +#define NFC_CMD_FIFO_STATUS (1 << 3)
> +#define NFC_STA (1 << 4)
> +#define NFC_NATCH_INT_FLAG (1 << 5)
> +#define NFC_RB_STATE0 (1 << 8)
> +#define NFC_RB_STATE1 (1 << 9)
> +#define NFC_RB_STATE2 (1 << 10)
> +#define NFC_RB_STATE3 (1 << 11)
> +
> +/*define bit use in NFC_INT*/
> +#define NFC_B2R_INT_ENABLE (1 << 0)
> +#define NFC_CMD_INT_ENABLE (1 << 1)
> +#define NFC_DMA_INT_ENABLE (1 << 2)
> +#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
> + NFC_CMD_INT_ENABLE | \
> + NFC_DMA_INT_ENABLE)
> +
> +
> +/*define bit use in NFC_CMD*/
> +#define NFC_CMD_LOW_BYTE (0xff << 0)
> +#define NFC_CMD_HIGH_BYTE (0xff << 8)
> +#define NFC_ADR_NUM (0x7 << 16)
> +#define NFC_SEND_ADR (1 << 19)
> +#define NFC_ACCESS_DIR (1 << 20)
> +#define NFC_DATA_TRANS (1 << 21)
> +#define NFC_SEND_CMD1 (1 << 22)
> +#define NFC_WAIT_FLAG (1 << 23)
> +#define NFC_SEND_CMD2 (1 << 24)
> +#define NFC_SEQ (1 << 25)
> +#define NFC_DATA_SWAP_METHOD (1 << 26)
> +#define NFC_ROW_AUTO_INC (1 << 27)
> +#define NFC_SEND_CMD3 (1 << 28)
> +#define NFC_SEND_CMD4 (1 << 29)
> +#define NFC_CMD_TYPE (3 << 30)
> +
> +/* define bit use in NFC_RCMD_SET*/
> +#define NFC_READ_CMD (0xff << 0)
> +#define NFC_RANDOM_READ_CMD0 (0xff << 8)
> +#define NFC_RANDOM_READ_CMD1 (0xff << 16)
> +
> +/*define bit use in NFC_WCMD_SET*/
> +#define NFC_PROGRAM_CMD (0xff << 0)
> +#define NFC_RANDOM_WRITE_CMD (0xff << 8)
> +#define NFC_READ_CMD0 (0xff << 16)
> +#define NFC_READ_CMD1 (0xff << 24)
> +
> +/*define bit use in NFC_ECC_CTL*/
> +#define NFC_ECC_EN (1 << 0)
> +#define NFC_ECC_PIPELINE (1 << 3)
> +#define NFC_ECC_EXCEPTION (1 << 4)
> +#define NFC_ECC_BLOCK_SIZE (1 << 5)
> +#define NFC_RANDOM_EN (1 << 9)
> +#define NFC_RANDOM_DIRECTION (1 << 10)
> +#define NFC_ECC_MODE_SHIFT 12
> +#define NFC_ECC_MODE (0xf << NFC_ECC_MODE_SHIFT)
> +#define NFC_RANDOM_SEED (0x7fff << 16)
> +
> +
> +
> +enum sunxi_nand_rb_type {
> + RB_NONE,
> + RB_NATIVE,
> + RB_GPIO,
> +};
> +
> +struct sunxi_nand_rb {
> + enum sunxi_nand_rb_type type;
> + union {
> + int gpio;
> + int nativeid;
> + } info;
> +};
> +
> +struct sunxi_nand_chip_sel {
> + u8 cs;
> + struct sunxi_nand_rb rb;
> +};
> +
> +#define DEFAULT_NAME_FORMAT "nand@%d"
> +#define MAX_NAME_SIZE (sizeof("nand@") + 2)
> +
> +struct sunxi_nand_chip {
> + struct list_head node;
> + struct nand_chip nand;
> + struct mtd_info mtd;
> + char default_name[MAX_NAME_SIZE];
> + unsigned long clk_rate;
> + int selected;
> + int nsels;
> + struct sunxi_nand_chip_sel sels[0];
> +};
> +
> +static inline struct sunxi_nand_chip *to_sunxi_nand(struct mtd_info *mtd)
> +{
> + return container_of(mtd, struct sunxi_nand_chip, mtd);
> +}
> +
> +struct sunxi_nfc {
> + struct nand_hw_control controller;
> + void __iomem *regs;
> + int irq;
> + struct clk *ahb_clk;
> + struct clk *sclk;
> + unsigned long assigned_cs;
> + unsigned long clk_rate;
> + struct list_head chips;
> + struct completion complete;
> +};
> +
> +static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
> +{
> + return container_of(ctrl, struct sunxi_nfc, controller);
> +}
> +
> +static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
> +{
> + struct sunxi_nfc *nfc = dev_id;
> + u32 st = readl(nfc->regs + NFC_REG_ST);
> + u32 ien = readl(nfc->regs + NFC_REG_INT);
> +
> + if (!(ien & st))
> + return IRQ_NONE;
> +
> + if ((ien & st) == ien)
> + complete(&nfc->complete);
> +
> + writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
> + writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
> + unsigned int timeout_ms)
> +{
> + init_completion(&nfc->complete);
> +
> + writel(flags, nfc->regs + NFC_REG_INT);
> + if (!timeout_ms)
> + wait_for_completion(&nfc->complete);
> + else if (!wait_for_completion_timeout(&nfc->complete,
> + msecs_to_jiffies(timeout_ms)))
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
> +{
> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
> + struct sunxi_nand_rb *rb;
> + unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
> + int ret;
> +
> + if (sunxi_nand->selected < 0)
> + return 0;
> +
> + rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
> +
> + switch (rb->type) {
> + case RB_NATIVE:
> + ret = !!(readl(nfc->regs + NFC_REG_ST) &
> + (NFC_RB_STATE0 << rb->info.nativeid));
> + if (ret)
> + break;
> +
> + sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
> + ret = !!(readl(nfc->regs + NFC_REG_ST) &
> + (NFC_RB_STATE0 << rb->info.nativeid));
> + break;
> + case RB_GPIO:
> + ret = gpio_get_value(rb->info.gpio);
> + break;
> + case RB_NONE:
> + default:
> + ret = 0;
> + dev_err(&mtd->dev, "cannot check R/B NAND status!");
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
> +{
> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
> + struct nand_chip *nand = &sunxi_nand->nand;
> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
> + struct sunxi_nand_chip_sel *sel;
> + u32 ctl;
> +
> + if (chip > 0 && chip >= sunxi_nand->nsels)
> + return;
> +
> + if (chip == sunxi_nand->selected)
> + return;
> +
> + ctl = readl(nfc->regs + NFC_REG_CTL) &
> + ~(NFC_CE_SEL | NFC_RB_SEL | NFC_EN);
> +
> + if (chip >= 0) {
> + sel = &sunxi_nand->sels[chip];
> +
> + ctl |= (sel->cs << 24) | NFC_EN |
> + (((nand->page_shift - 10) & 0xf) << 8);
> + if (sel->rb.type == RB_NONE) {
> + nand->dev_ready = NULL;
> + } else {
> + nand->dev_ready = sunxi_nfc_dev_ready;
> + if (sel->rb.type == RB_NATIVE)
> + ctl |= (sel->rb.info.nativeid << 3);
> + }
> +
> + writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
> +
> + if (nfc->clk_rate != sunxi_nand->clk_rate) {
> + clk_set_rate(nfc->sclk, sunxi_nand->clk_rate);
> + nfc->clk_rate = sunxi_nand->clk_rate;
> + }
> + }
> +
> + writel(ctl, nfc->regs + NFC_REG_CTL);
> +
> + sunxi_nand->selected = chip;
> +}
> +
> +static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
> +{
> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
> + int cnt;
> + int offs = 0;
> + u32 tmp;
> +
> + while (len > offs) {
> + cnt = len - offs;
> + if (cnt > 1024)
> + cnt = 1024;
> +
> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
> + ;
> + writel(cnt, nfc->regs + NFC_REG_CNT);
> + tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
> + writel(tmp, nfc->regs + NFC_REG_CMD);
> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
> + if (buf)
> + memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
> + cnt);
> + offs += cnt;
> + }
> +}
> +
> +static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
> + int len)
> +{
> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
> + int cnt;
> + int offs = 0;
> + u32 tmp;
> +
> + while (len > offs) {
> + cnt = len - offs;
> + if (cnt > 1024)
> + cnt = 1024;
> +
> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
> + ;
> + writel(cnt, nfc->regs + NFC_REG_CNT);
> + memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
> + tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
> + NFC_ACCESS_DIR;
> + writel(tmp, nfc->regs + NFC_REG_CMD);
> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
> + offs += cnt;
> + }
> +}
> +
> +static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
> +{
> + uint8_t ret;
> +
> + sunxi_nfc_read_buf(mtd, &ret, 1);
> +
> + return ret;
> +}
> +
> +static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
> + unsigned int ctrl)
> +{
> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
> + u32 tmp;
> +
> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
> + ;
> +
> + if (ctrl & NAND_CTRL_CHANGE) {
> + tmp = readl(nfc->regs + NFC_REG_CTL);
> + if (ctrl & NAND_NCE)
> + tmp |= NFC_CE_CTL;
> + else
> + tmp &= ~NFC_CE_CTL;
> + writel(tmp, nfc->regs + NFC_REG_CTL);
> + }
> +
> + if (dat == NAND_CMD_NONE)
> + return;
> +
> + if (ctrl & NAND_CLE) {
> + writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
> + } else {
> + writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
> + writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
> + }
> +
> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
> +}
> +
> +static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
> + const struct nand_sdr_timings *timings)
> +{
> + u32 min_clk_period = 0;
> +
> + /* T1 <=> tCLS */
> + if (timings->tCLS_min > min_clk_period)
> + min_clk_period = timings->tCLS_min;
> +
> + /* T2 <=> tCLH */
> + if (timings->tCLH_min > min_clk_period)
> + min_clk_period = timings->tCLH_min;
> +
> + /* T3 <=> tCS */
> + if (timings->tCS_min > min_clk_period)
> + min_clk_period = timings->tCS_min;
> +
> + /* T4 <=> tCH */
> + if (timings->tCH_min > min_clk_period)
> + min_clk_period = timings->tCH_min;
> +
> + /* T5 <=> tWP */
> + if (timings->tWP_min > min_clk_period)
> + min_clk_period = timings->tWP_min;
> +
> + /* T6 <=> tWH */
> + if (timings->tWH_min > min_clk_period)
> + min_clk_period = timings->tWH_min;
> +
> + /* T7 <=> tALS */
> + if (timings->tALS_min > min_clk_period)
> + min_clk_period = timings->tALS_min;
> +
> + /* T8 <=> tDS */
> + if (timings->tDS_min > min_clk_period)
> + min_clk_period = timings->tDS_min;
> +
> + /* T9 <=> tDH */
> + if (timings->tDH_min > min_clk_period)
> + min_clk_period = timings->tDH_min;
> +
> + /* T10 <=> tRR */
> + if (timings->tRR_min > (min_clk_period * 3))
> + min_clk_period = (timings->tRR_min + 2) / 3;
> +
> + /* T11 <=> tALH */
> + if (timings->tALH_min > min_clk_period)
> + min_clk_period = timings->tALH_min;
> +
> + /* T12 <=> tRP */
> + if (timings->tRP_min > min_clk_period)
> + min_clk_period = timings->tRP_min;
> +
> + /* T13 <=> tREH */
> + if (timings->tREH_min > min_clk_period)
> + min_clk_period = timings->tREH_min;
> +
> + /* T14 <=> tRC */
> + if (timings->tRC_min > (min_clk_period * 2))
> + min_clk_period = (timings->tRC_min + 1) / 2;
> +
> + /* T15 <=> tWC */
> + if (timings->tWC_min > (min_clk_period * 2))
> + min_clk_period = (timings->tWC_min + 1) / 2;
> +
> +
> + /* min_clk_period = (NAND-clk-period * 2) */
> + if (min_clk_period < 1000)
> + min_clk_period = 1000;
> +
> + min_clk_period /= 1000;
> + chip->clk_rate = (2 * 1000000000) / min_clk_period;
> +
> + /* TODO: configure T16-T19 */
> +
> + return 0;
> +}
> +
> +static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
> + struct device_node *np)
> +{
> + const struct nand_sdr_timings *timings;
> + int ret;
> +
> + ret = onfi_get_async_timing_mode(&chip->nand);
> + if (ret == ONFI_TIMING_MODE_UNKNOWN) {
> + ret = of_get_nand_onfi_timing_mode(np);
> + if (ret < 0)
> + return ret;
> + }
> +
> + ret = fls(ret);
> + if (!ret)
> + return -EINVAL;
> +
> + timings = onfi_async_timing_mode_to_sdr_timings(ret - 1);
> + if (IS_ERR(timings))
> + return PTR_ERR(timings);
> +
> + return sunxi_nand_chip_set_timings(chip, timings);
> +}
> +
> +static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
> + struct device_node *np)
> +{
> + const struct nand_sdr_timings *timings;
> + struct sunxi_nand_chip *chip;
> + struct mtd_part_parser_data ppdata;
> + struct mtd_info *mtd;
> + struct nand_chip *nand;
> + u32 strength;
> + u32 blk_size;
> + int nsels;
> + int ret;
> + int i;
> + u32 tmp;
> +
> + if (!of_get_property(np, "reg", &nsels))
> + return -EINVAL;
> +
> + nsels /= sizeof(u32);
> + if (!nsels)
> + return -EINVAL;
> +
> + chip = devm_kzalloc(dev,
> + sizeof(*chip) +
> + (nsels * sizeof(struct sunxi_nand_chip_sel)),
> + GFP_KERNEL);
> + if (!chip)
> + return -ENOMEM;
> +
> + chip->nsels = nsels;
> + chip->selected = -1;
> +
> + for (i = 0; i < nsels; i++) {
> + ret = of_property_read_u32_index(np, "reg", i, &tmp);
> + if (ret)
> + return ret;
> +
> + if (tmp > 7)
> + return -EINVAL;
> +
> + if (test_and_set_bit(tmp, &nfc->assigned_cs))
> + return -EINVAL;
> +
> + chip->sels[i].cs = tmp;
> +
> + if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
> + tmp < 2) {
> + chip->sels[i].rb.type = RB_NATIVE;
> + chip->sels[i].rb.info.nativeid = tmp;
> + } else {
> + ret = of_get_named_gpio(np, "rb-gpios", i);
> + if (ret >= 0) {
> + tmp = ret;
> + chip->sels[i].rb.type = RB_GPIO;
> + chip->sels[i].rb.info.gpio = tmp;
> + ret = devm_gpio_request(dev, tmp, "nand-rb");
> + if (ret)
> + return ret;
> +
> + ret = gpio_direction_input(tmp);
> + if (ret)
> + return ret;
> + } else {
> + chip->sels[i].rb.type = RB_NONE;
> + }
> + }
> + }
> +
> + timings = onfi_async_timing_mode_to_sdr_timings(0);
> + if (IS_ERR(timings))
> + return PTR_ERR(timings);
> +
> + ret = sunxi_nand_chip_set_timings(chip, timings);
> +
> + nand = &chip->nand;
> + nand->controller = &nfc->controller;
> + nand->select_chip = sunxi_nfc_select_chip;
> + nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
> + nand->read_buf = sunxi_nfc_read_buf;
> + nand->write_buf = sunxi_nfc_write_buf;
> + nand->read_byte = sunxi_nfc_read_byte;
> +
> + nand->ecc.mode = of_get_nand_ecc_mode(np);
> + if (of_get_nand_on_flash_bbt(np))
> + nand->bbt_options |= NAND_BBT_USE_FLASH;
> +
> + mtd = &chip->mtd;
> + mtd->priv = nand;
> + mtd->owner = THIS_MODULE;
> +
> + ret = nand_scan_ident(mtd, nsels, NULL);
> + if (ret)
> + return ret;
> +
> + ret = sunxi_nand_chip_init_timings(chip, np);
> + if (ret)
> + return ret;
> +
> + if (nand->ecc.mode == NAND_ECC_SOFT_BCH) {
> + if (!of_get_nand_ecc_level(np, &strength, &blk_size)) {
> + nand->ecc_step_ds = blk_size;
> + nand->ecc_strength_ds = strength;
> + }
> +
> + nand->ecc.size = nand->ecc_step_ds;
> + nand->ecc.bytes = (((nand->ecc_strength_ds *
> + fls(8 * nand->ecc_step_ds)) + 7) / 8);
> + }
> +
> + ret = nand_scan_tail(mtd);
> + if (ret)
> + return ret;
> +
> + if (of_property_read_string(np, "nand-name", &mtd->name)) {
> + snprintf(chip->default_name, MAX_NAME_SIZE,
> + DEFAULT_NAME_FORMAT, chip->sels[i].cs);
> + mtd->name = chip->default_name;
> + }
> +
> + ppdata.of_node = np;
> + ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
> + if (!ret)
> + return ret;
> +
> + list_add_tail(&chip->node, &nfc->chips);
> +
> + return 0;
> +}
> +
> +static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
> +{
> + struct device_node *np = dev->of_node;
> + struct device_node *nand_np;
> + int nchips = of_get_child_count(np);
> + int ret;
> +
> + if (nchips > 8)
> + return -EINVAL;
> +
> + for_each_child_of_node(np, nand_np) {
> + ret = sunxi_nand_chip_init(dev, nfc, nand_np);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int sunxi_nfc_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *r;
> + struct sunxi_nfc *nfc;
> + int ret;
> +
> + nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
> + if (!nfc) {
> + dev_err(dev, "failed to allocate NFC struct\n");
> + return -ENOMEM;
> + }
> +
> + spin_lock_init(&nfc->controller.lock);
> + init_waitqueue_head(&nfc->controller.wq);
> + INIT_LIST_HEAD(&nfc->chips);
> +
> + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + nfc->regs = devm_ioremap_resource(dev, r);
> + if (IS_ERR(nfc->regs)) {
> + dev_err(dev, "failed to remap iomem\n");
> + return PTR_ERR(nfc->regs);
> + }
> +
> + nfc->irq = platform_get_irq(pdev, 0);
> + if (nfc->irq < 0) {
> + dev_err(dev, "failed to retrieve irq\n");
> + return nfc->irq;
> + }
> +
> + nfc->ahb_clk = devm_clk_get(dev, "ahb_clk");
> + if (IS_ERR(nfc->ahb_clk)) {
> + dev_err(dev, "failed to retrieve ahb_clk\n");
> + return PTR_ERR(nfc->ahb_clk);
> + }
> +
> + ret = clk_prepare_enable(nfc->ahb_clk);
> + if (ret)
> + return ret;
> +
> + nfc->sclk = devm_clk_get(dev, "sclk");
> + if (IS_ERR(nfc->sclk)) {
> + dev_err(dev, "failed to retrieve nand_clk\n");
> + ret = PTR_ERR(nfc->sclk);
> + goto out_ahb_clk_unprepare;
> + }
> +
> + ret = clk_prepare_enable(nfc->sclk);
> + if (ret)
> + goto out_ahb_clk_unprepare;
> +
> + /* Reset NFC */
> + writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RESET,
> + nfc->regs + NFC_REG_CTL);
> + while (readl(nfc->regs + NFC_REG_CTL) & NFC_RESET)
> + ;
> +
> + writel(0, nfc->regs + NFC_REG_INT);
> + ret = devm_request_irq(dev, nfc->irq, sunxi_nfc_interrupt,
> + 0, "sunxi-nand", nfc);
> + if (ret)
> + goto out_sclk_unprepare;
> +
> + platform_set_drvdata(pdev, nfc);
> +
> + writel(0x100, nfc->regs + NFC_REG_TIMING_CTL);
> + writel(0x7ff, nfc->regs + NFC_REG_TIMING_CFG);
> +
> + ret = sunxi_nand_chips_init(dev, nfc);
> + if (ret) {
> + dev_err(dev, "failed to init nand chips\n");
> + goto out_sclk_unprepare;
> + }
> +
> + return 0;
> +
> +out_sclk_unprepare:
> + clk_disable_unprepare(nfc->sclk);
> +out_ahb_clk_unprepare:
> + clk_disable_unprepare(nfc->ahb_clk);
> +
> + return ret;
> +}
> +
> +static const struct of_device_id sunxi_nfc_ids[] = {
> + { .compatible = "allwinner,sun4i-nand" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
> +
> +static struct platform_driver sunxi_nfc_driver = {
> + .driver = {
> + .name = "sunxi_nand",
> + .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(sunxi_nfc_ids),
> + },
> + .probe = sunxi_nfc_probe,
> +};
> +module_platform_driver(sunxi_nfc_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Boris BREZILLON");
> +MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
> +MODULE_ALIAS("platform:sunxi_nfc");
> --
> 1.7.9.5
>
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* NFS client broken in Linus' tip
From: Trond Myklebust @ 2014-01-30 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140130143054.GY15937@n2100.arm.linux.org.uk>
On Jan 30, 2014, at 9:30, Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:
> On Thu, Jan 30, 2014 at 09:17:00AM -0500, Trond Myklebust wrote:
>>
>> On Jan 30, 2014, at 9:08, Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:
>>
>>> I just booted Linus' tip (plus a few other patches to imx-drm and imx
>>> code), and stumbled into this interesting scenario:
>>>
>>> # touch test
>>> touch: cannot touch `test': Operation not supported
>>>
>>> I also tried mkdir and mknod, all result in the same error. Hard and
>>> symlinks links are creatable.
>>>
>>> However, I can chmod existing files and rename them. Files can also be
>>> deleted, and the combination of this has left me without a /etc/mtab !
>>>
>>> The machine is a iMX6 based ARM, running root-nfs, which was mounted via
>>> ubuntu's initramfs (so not using the kernel's built-in root-nfs.)
>>>
>>> /proc/mounts for the root mount gives:
>>> 192.168.1.123:/var/boot/ci / nfs rw,relatime,vers=3,rsize=65536,wsize=65536,namlen=255,hard,nolock,proto=tcp,port=2049,timeo=7,retrans=10,sec=sys,local_lock=all,addr=192.168.1.123 0 0
>>>
>>> CONFIG_NFS_FS=y
>>> CONFIG_NFS_V2=y
>>> CONFIG_NFS_V3=y
>>> CONFIG_NFS_V3_ACL=y
>>> CONFIG_NFS_V4=y
>>> # CONFIG_NFS_SWAP is not set
>>> # CONFIG_NFS_V4_1 is not set
>>> CONFIG_ROOT_NFS=y
>>> # CONFIG_NFS_USE_LEGACY_DNS is not set
>>> CONFIG_NFS_USE_KERNEL_DNS=y
>>> # CONFIG_NFSD is not set
>>> CONFIG_LOCKD=y
>>> CONFIG_LOCKD_V4=y
>>> CONFIG_NFS_ACL_SUPPORT=y
>>> CONFIG_NFS_COMMON=y
>>> CONFIG_SUNRPC=y
>>> CONFIG_SUNRPC_GSS=y
>>>
>>> tcpdumping, I see:
>>>
>>> 13:59:51.713523 IP 192.168.1.252.1341245608 > 192.168.1.123.2049: 132 lookup fh Unknown/010007011040840000000000CC238FC8FBA0475D9D9F8356B4C44166CDC38700 "test"
>>> 13:59:51.714345 IP 192.168.1.123.2049 > 192.168.1.252.1341245608: reply ok 120 lookup ERROR: No such file or directory
>>> 13:59:51.751303 IP 192.168.1.252.797 > 192.168.1.123.nfs: . ack 3381 win 2625 <nop,nop,timestamp 474136 3431312924>
>>>
>>> which is the only NFS packet(s) I see which mention "test".
>>>
>>> and stracing touch:
>>>
>>> open("test", O_WRONLY|O_CREAT|O_NOCTTY|O_NONBLOCK|O_LARGEFILE, 0666) = -1 EOPNOTSUPP (Operation not supported)
>>> utimensat(AT_FDCWD, "test", NULL, 0) = -1 ENOENT (No such file or directory)
>>> write(2, "touch: ", 7touch: ) = 7
>>> write(2, "cannot touch `test'", 19cannot touch `test') = 19
>>> write(2, ": Operation not supported", 25: Operation not supported) = 25
>>> write(2, "\n", 1
>>> ) = 1
>>>
>>> I think it's down to this:
>>>
>>> commit 013cdf1088d7235da9477a2375654921d9b9ba9f
>>> Author: Christoph Hellwig <hch@infradead.org>
>>> Date: Fri Dec 20 05:16:53 2013 -0800
>>>
>>> nfs: use generic posix ACL infrastructure for v3 Posix ACLs
>>>
>>> This causes a small behaviour change in that we don't bother to set
>>> ACLs on file creation if the mode bit can express the access permissions
>>> fully, and thus behaving identical to local filesystems.
>>>
>>> Signed-off-by: Christoph Hellwig <hch@lst.de>
>>> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
>>>
>>> which adds:
>>>
>>> + status = posix_acl_create(dir, &sattr->ia_mode, &default_acl, &acl);
>>> + if (status)
>>> + goto out;
>>
>> Right, this should clearly not cause nfs4_proc_create to fail if it
>> returns EOPNOTSUPP.
>
> NFS3 :)
Sorry. I fat fingered that one. I intended to write nfs3_...
>>> into nfs3_proc_create(), but this ends up calling down into nfs3_get_acl(),
>>> which does this:
>>>
>>> if (!nfs_server_capable(inode, NFS_CAP_ACLS))
>>> return ERR_PTR(-EOPNOTSUPP);
>>
>> Just for completeness sake: is the server you were running against supposed to support POSIX acls?
>
> The server is an old 3.1.8 kernel with this NFS config:
>
> CONFIG_NFS_FS=m
> CONFIG_NFS_V3=y
> # CONFIG_NFS_V3_ACL is not set
> # CONFIG_NFS_V4 is not set
> # CONFIG_NFS_FSCACHE is not set
> CONFIG_NFSD=m
> CONFIG_NFSD_V3=y
> # CONFIG_NFSD_V3_ACL is not set
> # CONFIG_NFSD_V4 is not set
> CONFIG_LOCKD=m
> CONFIG_LOCKD_V4=y
> CONFIG_NFS_COMMON=y
>
> which has worked fine with NFS clients for the last 1800 odd days... until
> now.
>
OK. I?m guessing that you?re hitting the auto-probing code further down in nfs3_get_acl(), which also returns EOPNOTSUPP in those cases. Those probably need to return NULL too, then?
However, there seems to be an inconsistency in the whole API here: posix_acl_create() and posix_acl_chmod() seem to want to return ?0? both when acls are not supported and when they are not set, however posix_acl_xattr_get() wants to return EOPNOTSUPP in the first case, and ENODATA in the second. How is the filesystem supposed to know what to return?
--
Trond Myklebust
Linux NFS client maintainer
^ permalink raw reply
* [PATCH 0/4] ARM:sti: Add STiD127 platform and board support
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
This patch-set adds basic support for STMicroelectronics STiD127
with B2112 board support. STiD127 is dual-core ARM Cortex-A9 CPU
to function as a cable modem or in combination with a back end
as a gateway set top box.
Alexandre TORGUE (4):
ARM: STi: add stid127 soc support
pinctrl: st: add stid127 support
ARM: dts: Add support of STid127 Soc.
ARM: dts: add B2112 board support
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/stid127-b2112.dts | 35 +++++
arch/arm/boot/dts/stid127-clock.dtsi | 31 ++++
arch/arm/boot/dts/stid127-pinctrl.dtsi | 245 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stid127.dtsi | 130 +++++++++++++++++
arch/arm/mach-sti/board-dt.c | 6 +
drivers/pinctrl/pinctrl-st.c | 25 ++++
7 files changed, 474 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/stid127-b2112.dts
create mode 100644 arch/arm/boot/dts/stid127-clock.dtsi
create mode 100644 arch/arm/boot/dts/stid127-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stid127.dtsi
--
1.7.9.5
^ permalink raw reply
* [PATCH 1/4] ARM: STi: add stid127 soc support
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391093744-19905-1-git-send-email-patrice.chotard@st.com>
From: Alexandre TORGUE <alexandre.torgue@st.com>
This patch adds support to STiD127 SoC.
The main adaptation is the L2 cache way size compare to STiH41x SoCs.
Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/mach-sti/board-dt.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
index 1217fb5..be018a9 100644
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -9,6 +9,7 @@
#include <linux/irq.h>
#include <linux/of_platform.h>
+#include <linux/of.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
@@ -18,6 +19,10 @@ void __init stih41x_l2x0_init(void)
{
u32 way_size = 0x4;
u32 aux_ctrl;
+
+ if (of_machine_is_compatible("st,stid127"))
+ way_size = 0x3;
+
/* may be this can be encoded in macros like BIT*() */
aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
@@ -36,6 +41,7 @@ static void __init stih41x_machine_init(void)
static const char *stih41x_dt_match[] __initdata = {
"st,stih415",
"st,stih416",
+ "st,stid127",
NULL
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/4] pinctrl: st: add stid127 support
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391093744-19905-1-git-send-email-patrice.chotard@st.com>
From: Alexandre TORGUE <alexandre.torgue@st.com>
Add STid127 PIOs (psouth, pwest, peast) in pinctrl.
Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
---
drivers/pinctrl/pinctrl-st.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 9cadc68..01227de 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -336,6 +336,27 @@ static const struct st_pctl_data stih416_data = {
.alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
};
+/* STid127 data */
+static const struct st_pctl_data stid127_data = {
+ .rt_style = st_retime_style_dedicated,
+ /* reuse stih416 delays as they are identical */
+ .input_delays = stih416_delays,
+ .ninput_delays = 14,
+ /* reuse stih416 delays as they are identical */
+ .output_delays = stih416_delays,
+ .noutput_delays = 14,
+ .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 14,
+};
+
+static const struct st_pctl_data stid127_psouth_data = {
+ .rt_style = st_retime_style_dedicated,
+ .input_delays = stid127_delays,
+ .ninput_delays = 14,
+ .output_delays = stid127_delays,
+ .noutput_delays = 14,
+ .alt = 0, .oe = 7, .pu = 9, .od = 11, .rt = 13,
+};
+
/* Low level functions.. */
static inline int st_gpio_bank(int gpio)
{
@@ -1264,6 +1285,10 @@ static struct of_device_id st_pctl_of_match[] = {
{ .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data},
{ .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data},
{ .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data},
+ { .compatible = "st,stid127-pwest-pinctrl", .data = &stid127_data },
+ { .compatible = "st,stid127-psouth-pinctrl",
+ .data = &stid127_psouth_data },
+ { .compatible = "st,stid127-peast-pinctrl", .data = &stid127_data },
{ /* sentinel */ }
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: Add support of STid127 Soc.
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391093744-19905-1-git-send-email-patrice.chotard@st.com>
From: Alexandre TORGUE <alexandre.torgue@st.com>
The STid127 integrates all harware components to function as a cable modem
or, in combination with a back end device, as a Gateway set top boxe.
Supported devices:
-UART0
-UART2
Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stid127-clock.dtsi | 31 ++++
arch/arm/boot/dts/stid127-pinctrl.dtsi | 245 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stid127.dtsi | 130 +++++++++++++++++
3 files changed, 406 insertions(+)
create mode 100644 arch/arm/boot/dts/stid127-clock.dtsi
create mode 100644 arch/arm/boot/dts/stid127-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stid127.dtsi
diff --git a/arch/arm/boot/dts/stid127-clock.dtsi b/arch/arm/boot/dts/stid127-clock.dtsi
new file mode 100644
index 0000000..c6cafa9
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-clock.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ * Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+ clocks {
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: arm_periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+ /*
+ * Bootloader initialized system infrastructure clock for
+ * serial devices.
+ */
+ CLK_IC_LP_HD: clockgenA0 at 29 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "CLK_IC_LP_HD";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stid127-pinctrl.dtsi b/arch/arm/boot/dts/stid127-pinctrl.dtsi
new file mode 100644
index 0000000..3fa66f3
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-pinctrl.dtsi
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2012 STMicroelectronics Limited.
+ * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ * Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+ aliases {
+ gpio0 = &PIO0;
+ gpio1 = &PIO1;
+ gpio2 = &PIO2;
+ gpio3 = &PIO3;
+ gpio4 = &PIO4;
+ gpio5 = &PIO5;
+ gpio6 = &PIO6;
+ gpio7 = &PIO7;
+ gpio8 = &PIO8;
+ gpio9 = &PIO9;
+ gpio10 = &PIO10;
+ gpio11 = &PIO11;
+ gpio12 = &PIO12;
+ gpio13 = &PIO13;
+ gpio14 = &PIO14;
+ gpio15 = &PIO15;
+ gpio16 = &PIO16;
+ gpio17 = &PIO17;
+ gpio18 = &PIO18;
+ gpio19 = &PIO19;
+ gpio20 = &PIO20;
+ gpio21 = &PIO21;
+ gpio22 = &PIO22;
+
+ };
+
+ soc {
+ pin-controller-pwest {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-pwest-pinctrl";
+ st,syscfg = <&syscfg_pwest>;
+ ranges = <0 0xfebe0000 0x8000>;
+
+ PIO0: gpio at febe0000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ interrupts = <0 149 0>;
+ st,bank-name = "PIO0";
+ };
+ PIO1: gpio at febe1000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 150 0>;
+ st,bank-name = "PIO1";
+ };
+ PIO2: gpio at febe2000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 151 0>;
+ st,bank-name = "PIO2";
+ };
+ PIO3: gpio at febe3000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 152 0>;
+ st,bank-name = "PIO3";
+ };
+ PIO4: gpio at febe4000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 153 0>;
+ st,bank-name = "PIO4";
+ };
+ PIO5: gpio at febe5000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 154 0>;
+ st,bank-name = "PIO5";
+ };
+ PIO6: gpio at febe6000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 155 0>;
+ st,bank-name = "PIO6";
+ };
+ PIO7: gpio at febe7000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x7000 0x100>;
+ interrupts = <0 156 0>;
+ st,bank-name = "PIO7";
+ };
+ uart0 {
+ pinctrl_uart0: uart0 {
+ st,pins {
+ tx = <&PIO3 2 ALT2 OUT>;
+ rx = <&PIO3 0 ALT2 IN>;
+ };
+ };
+ };
+
+ };
+
+ pin-controller-psouth {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-psouth-pinctrl";
+ st,syscfg = <&syscfg_psouth>;
+ ranges = <0 0xfef70000 0x7000>;
+
+ PIO8: gpio at fef70000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ interrupts = <0 157 0>;
+ st,bank-name = "PIO8";
+ };
+ PIO9: gpio at fef71000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 158 0>;
+ st,bank-name = "PIO9";
+ };
+ PIO10: gpio at fef72000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 159 0>;
+ st,bank-name = "PIO10";
+ };
+ PIO11: gpio at fef73000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 160 0>;
+ st,bank-name = "PIO11";
+ };
+ PIO12: gpio at fef74000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 161 0>;
+ st,bank-name = "PIO12";
+ };
+ PIO13: gpio at fef75000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 162 0>;
+ st,bank-name = "PIO13";
+ };
+ PIO14: gpio at fef76000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 163 0>;
+ st,bank-name = "PIO14";
+ };
+ };
+
+ pin-controller-peast {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-peast-pinctrl";
+ st,syscfg = <&syscfg_peast>;
+ ranges = <0 0xfebc0000 0x8000>;
+
+ PIO15: gpio at febc0000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = < 0 0x100>;
+ interrupts = <0 164 0>;
+ st,bank-name = "PIO15";
+ };
+ PIO16: gpio at febc1000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 165 0>;
+ st,bank-name = "PIO16";
+ };
+ PIO17: gpio at febc2000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 166 0>;
+ st,bank-name = "PIO17";
+ };
+ PIO18: gpio at febc3000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 167 0>;
+ st,bank-name = "PIO18";
+ };
+ PIO19: gpio at febc4000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 168 0>;
+ st,bank-name = "PIO19";
+ };
+ PIO20: gpio at febc5000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 169 0>;
+ st,bank-name = "PIO20";
+ };
+ PIO21: gpio at febc6000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 170 0>;
+ st,bank-name = "PIO21";
+ };
+ PIO22: gpio at febc7000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x7000 0x100>;
+ interrupts = <0 171 0>;
+ st,bank-name = "PIO22";
+ };
+ uart2 {
+ pinctrl_uart2: uart2-0 {
+ st,pins {
+ tx = <&PIO20 1 ALT3 OUT>;
+ rx = <&PIO20 2 ALT3 IN>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stid127.dtsi b/arch/arm/boot/dts/stid127.dtsi
new file mode 100644
index 0000000..a6f0b8fe
--- /dev/null
+++ b/arch/arm/boot/dts/stid127.dtsi
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited.
+ * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ * Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stid127-pinctrl.dtsi"
+#include "stid127-clock.dtsi"
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ intc: interrupt-controller at fffe1000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xfffe1000 0x1000>,
+ <0xfffe0100 0x100>;
+ };
+
+ scu at fffe0000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xfffe0000 0x1000>;
+ };
+
+ timer at fffe0200 {
+ interrupt-parent = <&intc>;
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xfffe0200 0x100>;
+ interrupts = <1 11 0x04>;
+ clocks = <&arm_periph_clk>;
+ };
+
+ L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xfffe2000 0x1000>;
+ arm,data-latency = <3 2 2>;
+ arm,tag-latency = <1 1 1>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+ compatible = "simple-bus";
+
+ syscfg_west:west-syscfg at febf0000{
+ compatible = "st,stid127-west-syscfg", "syscon";
+ reg = <0xfebf0000 0x1000>;
+ };
+
+ syscfg_south:south-syscfg at fefa0000{
+ compatible = "st,stid127-south-syscfg", "syscon";
+ reg = <0xfefa0000 0x1000>;
+ };
+
+ syscfg_docsis:docsis-syscfg at fef90000{
+ compatible = "st,stid127-docsys-syscfg", "syscon";
+ reg = <0xfef90000 0x1000>;
+ };
+
+ syscfg_cpu:cpu-syscfg at fe9a0000{
+ compatible = "st,stid127-cpu-syscfg", "syscon";
+ reg = <0xfe9a0000 0x1000>;
+ };
+
+ syscfg_hd:hd-syscfg at fe930000{
+ compatible = "st,stid127-hd-syscfg", "syscon";
+ reg = <0xfe930000 0x1000>;
+ };
+
+ syscfg_pwest:pwest-syscfg at fec00000{
+ compatible = "st,stid127-pwest-syscfg", "syscon";
+ reg = <0xfec00000 0x1000>;
+ };
+
+ syscfg_psouth:psouth-syscfg at fefd0000{
+ compatible = "st,stid127-psouth-syscfg", "syscon";
+ reg = <0xfefd0000 0x1000>;
+ };
+
+ syscfg_peast:peast-syscfg at febd0000{
+ compatible = "st,stid127-peast-syscfg", "syscon";
+ reg = <0xfebd0000 0x1000>;
+ };
+
+ /* Comms block ASCs in SASG2 */
+ uart0: serial at fe530000{
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfe530000 0x2c>;
+ interrupts = <0 25 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&CLK_IC_LP_HD>;
+ };
+
+ uart2: serial at fe532000{
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfe532000 0x2c>;
+ interrupts = <0 27 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&CLK_IC_LP_HD>;
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 4/4] ARM: dts: add B2112 board support
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391093744-19905-1-git-send-email-patrice.chotard@st.com>
From: Alexandre TORGUE <alexandre.torgue@st.com>
Add support for B2112 board based on STiD127 SoC.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/stid127-b2112.dts | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/stid127-b2112.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..7173dca 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -247,7 +247,8 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
stih416-b2000.dtb \
stih415-b2020.dtb \
- stih416-b2020.dtb
+ stih416-b2020.dtb \
+ stid127-b2112.dtb
dtb-$(CONFIG_ARCH_SUNXI) += \
sun4i-a10-a1000.dtb \
sun4i-a10-cubieboard.dtb \
diff --git a/arch/arm/boot/dts/stid127-b2112.dts b/arch/arm/boot/dts/stid127-b2112.dts
new file mode 100644
index 0000000..b4507e3
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-b2112.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited.
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stid127.dtsi"
+
+/ {
+ model = "STiD127 B2112 Board";
+ compatible = "st,stid127", "st,stid127-b2112";
+
+ memory{
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyAS0,115200";
+ linux,stdout-path = &uart2;
+ };
+
+ aliases {
+ ttyAS0 = &uart2;
+ };
+
+ soc {
+ uart2: serial at fe532000{
+ status = "okay";
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/2] ARM: imx_v4_v5_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
From: Fabio Estevam @ 2014-01-30 15:04 UTC (permalink / raw)
To: linux-arm-kernel
PM subsystem treats mmc card as removed during suspend.
If MMC is used to store the root file system, it is better to tell the kernel
not to treat it as a removable media, so select CONFIG_MMC_UNSAFE_RESUME for
such purpose.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/configs/imx_v4_v5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 6309ee5..f1aeb7d 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -154,6 +154,7 @@ CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
--
1.8.1.2
^ permalink raw reply related
* [PATCH 2/2] ARM: imx_v6_v7_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
From: Fabio Estevam @ 2014-01-30 15:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391094252-10599-1-git-send-email-fabio.estevam@freescale.com>
PM subsystem treats mmc card as removed during suspend.
If MMC is used to store the root file system, it is better to tell the kernel
not to treat it as a removable media, so select CONFIG_MMC_UNSAFE_RESUME for
such purpose.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 82ab3cc..7b76794 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -215,6 +215,7 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ETH=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
--
1.8.1.2
^ permalink raw reply related
* [RFC PATCH pre-v3 08/14] mtd: nand: add sunxi NAND flash controller support
From: Boris BREZILLON @ 2014-01-30 15:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140130143641.GZ15937@n2100.arm.linux.org.uk>
Hello Russel,
On 30/01/2014 15:36, Russell King - ARM Linux wrote:
> Boris,
>
> Can you please explain to me why you mail all your patches _To:_ me?
> As in, why do I appear in the To: line of all the patches you seem to
> mail out, whether or not they're relevant to me. I see this very
> regularly from you - virtually all patches I see on the LAKML mailing
> list from you are always sent To: me as well.
>
> Take for instance this one. It doesn't match up with anything in
> MAINTAINERS for me. It doesn't even touch a file that I've touched.
> Yet somehow you think that I should be in the To: header.
>
> Being in the To: header means that you expect the recipient to do
> something with your email. The Cc: header is to circulate copies of
> your email to people who may be interested.
>
> I'm neither for this stuff. Please stop this.
Sorry for the inconvenience.
I'm using get_maintainer.pl script to retrieve the list of concerned
people, and you appears in that list for patches 10,11,12 and 14 of this
series.
Moreover I was told to send the whole series (not just specific patches
to people who might be concerned).
I obviously misuse this script, so please tell me how I should know which
patch I should send to whom.
Thanks.
Best Regards,
Boris
>
> Thanks.
>
> On Thu, Jan 30, 2014 at 02:39:36PM +0100, Boris BREZILLON wrote:
>> Add support for the sunxi NAND Flash Controller (NFC).
>>
>> Signed-off-by: Boris BREZILLON <b.brezillon.dev@gmail.com>
>> ---
>> Hello,
>>
>> This version fixes a bug in the R/B GPIO config block.
>> The timing config order is now respected, but I'll wait for Jason work
>> regarding timing config in NAND core code before posting the 3rd version
>> of this series.
>>
>> Best Regards,
>>
>> Boris
>>
>> Changes since v2:
>> - fix R/B GPIO retrieval/config bug
>> - fix timings configuration order (set mode 0 -> scan -> set best supported
>> mode)
>>
>> drivers/mtd/nand/Kconfig | 6 +
>> drivers/mtd/nand/Makefile | 1 +
>> drivers/mtd/nand/sunxi_nand.c | 758 +++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 765 insertions(+)
>> create mode 100644 drivers/mtd/nand/sunxi_nand.c
>>
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index 93ae6a6..784dd42 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -510,4 +510,10 @@ config MTD_NAND_XWAY
>> Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
>> to the External Bus Unit (EBU).
>>
>> +config MTD_NAND_SUNXI
>> + tristate "Support for NAND on Allwinner SoCs"
>> + depends on ARCH_SUNXI
>> + help
>> + Enables support for NAND Flash chips on Allwinner SoCs.
>> +
>> endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>> index bbea7a6..e3b4a34 100644
>> --- a/drivers/mtd/nand/Makefile
>> +++ b/drivers/mtd/nand/Makefile
>> @@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
>> obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
>> obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
>> obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
>> +obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
>>
>> nand-objs := nand_base.o nand_bbt.o
>> diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
>> new file mode 100644
>> index 0000000..1014b2a
>> --- /dev/null
>> +++ b/drivers/mtd/nand/sunxi_nand.c
>> @@ -0,0 +1,758 @@
>> +/*
>> + * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
>> + *
>> + * Derived from:
>> + * https://github.com/yuq/sunxi-nfc-mtd
>> + * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
>> + *
>> + * https://github.com/hno/Allwinner-Info
>> + * Copyright (C) 2013 Henrik Nordstr?m <Henrik Nordstr?m>
>> + *
>> + * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
>> + * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/dma-mapping.h>
>> +#include <linux/slab.h>
>> +#include <linux/module.h>
>> +#include <linux/moduleparam.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/of_gpio.h>
>> +#include <linux/of_mtd.h>
>> +#include <linux/mtd/mtd.h>
>> +#include <linux/mtd/nand.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/dmaengine.h>
>> +#include <linux/gpio.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +
>> +#define NFC_REG_CTL 0x0000
>> +#define NFC_REG_ST 0x0004
>> +#define NFC_REG_INT 0x0008
>> +#define NFC_REG_TIMING_CTL 0x000C
>> +#define NFC_REG_TIMING_CFG 0x0010
>> +#define NFC_REG_ADDR_LOW 0x0014
>> +#define NFC_REG_ADDR_HIGH 0x0018
>> +#define NFC_REG_SECTOR_NUM 0x001C
>> +#define NFC_REG_CNT 0x0020
>> +#define NFC_REG_CMD 0x0024
>> +#define NFC_REG_RCMD_SET 0x0028
>> +#define NFC_REG_WCMD_SET 0x002C
>> +#define NFC_REG_IO_DATA 0x0030
>> +#define NFC_REG_ECC_CTL 0x0034
>> +#define NFC_REG_ECC_ST 0x0038
>> +#define NFC_REG_DEBUG 0x003C
>> +#define NFC_REG_ECC_CNT0 0x0040
>> +#define NFC_REG_ECC_CNT1 0x0044
>> +#define NFC_REG_ECC_CNT2 0x0048
>> +#define NFC_REG_ECC_CNT3 0x004c
>> +#define NFC_REG_USER_DATA_BASE 0x0050
>> +#define NFC_REG_SPARE_AREA 0x00A0
>> +#define NFC_RAM0_BASE 0x0400
>> +#define NFC_RAM1_BASE 0x0800
>> +
>> +/*define bit use in NFC_CTL*/
>> +#define NFC_EN (1 << 0)
>> +#define NFC_RESET (1 << 1)
>> +#define NFC_BUS_WIDYH (1 << 2)
>> +#define NFC_RB_SEL (1 << 3)
>> +#define NFC_CE_SEL (7 << 24)
>> +#define NFC_CE_CTL (1 << 6)
>> +#define NFC_CE_CTL1 (1 << 7)
>> +#define NFC_PAGE_SIZE (0xf << 8)
>> +#define NFC_SAM (1 << 12)
>> +#define NFC_RAM_METHOD (1 << 14)
>> +#define NFC_DEBUG_CTL (1 << 31)
>> +
>> +/*define bit use in NFC_ST*/
>> +#define NFC_RB_B2R (1 << 0)
>> +#define NFC_CMD_INT_FLAG (1 << 1)
>> +#define NFC_DMA_INT_FLAG (1 << 2)
>> +#define NFC_CMD_FIFO_STATUS (1 << 3)
>> +#define NFC_STA (1 << 4)
>> +#define NFC_NATCH_INT_FLAG (1 << 5)
>> +#define NFC_RB_STATE0 (1 << 8)
>> +#define NFC_RB_STATE1 (1 << 9)
>> +#define NFC_RB_STATE2 (1 << 10)
>> +#define NFC_RB_STATE3 (1 << 11)
>> +
>> +/*define bit use in NFC_INT*/
>> +#define NFC_B2R_INT_ENABLE (1 << 0)
>> +#define NFC_CMD_INT_ENABLE (1 << 1)
>> +#define NFC_DMA_INT_ENABLE (1 << 2)
>> +#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
>> + NFC_CMD_INT_ENABLE | \
>> + NFC_DMA_INT_ENABLE)
>> +
>> +
>> +/*define bit use in NFC_CMD*/
>> +#define NFC_CMD_LOW_BYTE (0xff << 0)
>> +#define NFC_CMD_HIGH_BYTE (0xff << 8)
>> +#define NFC_ADR_NUM (0x7 << 16)
>> +#define NFC_SEND_ADR (1 << 19)
>> +#define NFC_ACCESS_DIR (1 << 20)
>> +#define NFC_DATA_TRANS (1 << 21)
>> +#define NFC_SEND_CMD1 (1 << 22)
>> +#define NFC_WAIT_FLAG (1 << 23)
>> +#define NFC_SEND_CMD2 (1 << 24)
>> +#define NFC_SEQ (1 << 25)
>> +#define NFC_DATA_SWAP_METHOD (1 << 26)
>> +#define NFC_ROW_AUTO_INC (1 << 27)
>> +#define NFC_SEND_CMD3 (1 << 28)
>> +#define NFC_SEND_CMD4 (1 << 29)
>> +#define NFC_CMD_TYPE (3 << 30)
>> +
>> +/* define bit use in NFC_RCMD_SET*/
>> +#define NFC_READ_CMD (0xff << 0)
>> +#define NFC_RANDOM_READ_CMD0 (0xff << 8)
>> +#define NFC_RANDOM_READ_CMD1 (0xff << 16)
>> +
>> +/*define bit use in NFC_WCMD_SET*/
>> +#define NFC_PROGRAM_CMD (0xff << 0)
>> +#define NFC_RANDOM_WRITE_CMD (0xff << 8)
>> +#define NFC_READ_CMD0 (0xff << 16)
>> +#define NFC_READ_CMD1 (0xff << 24)
>> +
>> +/*define bit use in NFC_ECC_CTL*/
>> +#define NFC_ECC_EN (1 << 0)
>> +#define NFC_ECC_PIPELINE (1 << 3)
>> +#define NFC_ECC_EXCEPTION (1 << 4)
>> +#define NFC_ECC_BLOCK_SIZE (1 << 5)
>> +#define NFC_RANDOM_EN (1 << 9)
>> +#define NFC_RANDOM_DIRECTION (1 << 10)
>> +#define NFC_ECC_MODE_SHIFT 12
>> +#define NFC_ECC_MODE (0xf << NFC_ECC_MODE_SHIFT)
>> +#define NFC_RANDOM_SEED (0x7fff << 16)
>> +
>> +
>> +
>> +enum sunxi_nand_rb_type {
>> + RB_NONE,
>> + RB_NATIVE,
>> + RB_GPIO,
>> +};
>> +
>> +struct sunxi_nand_rb {
>> + enum sunxi_nand_rb_type type;
>> + union {
>> + int gpio;
>> + int nativeid;
>> + } info;
>> +};
>> +
>> +struct sunxi_nand_chip_sel {
>> + u8 cs;
>> + struct sunxi_nand_rb rb;
>> +};
>> +
>> +#define DEFAULT_NAME_FORMAT "nand@%d"
>> +#define MAX_NAME_SIZE (sizeof("nand@") + 2)
>> +
>> +struct sunxi_nand_chip {
>> + struct list_head node;
>> + struct nand_chip nand;
>> + struct mtd_info mtd;
>> + char default_name[MAX_NAME_SIZE];
>> + unsigned long clk_rate;
>> + int selected;
>> + int nsels;
>> + struct sunxi_nand_chip_sel sels[0];
>> +};
>> +
>> +static inline struct sunxi_nand_chip *to_sunxi_nand(struct mtd_info *mtd)
>> +{
>> + return container_of(mtd, struct sunxi_nand_chip, mtd);
>> +}
>> +
>> +struct sunxi_nfc {
>> + struct nand_hw_control controller;
>> + void __iomem *regs;
>> + int irq;
>> + struct clk *ahb_clk;
>> + struct clk *sclk;
>> + unsigned long assigned_cs;
>> + unsigned long clk_rate;
>> + struct list_head chips;
>> + struct completion complete;
>> +};
>> +
>> +static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
>> +{
>> + return container_of(ctrl, struct sunxi_nfc, controller);
>> +}
>> +
>> +static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
>> +{
>> + struct sunxi_nfc *nfc = dev_id;
>> + u32 st = readl(nfc->regs + NFC_REG_ST);
>> + u32 ien = readl(nfc->regs + NFC_REG_INT);
>> +
>> + if (!(ien & st))
>> + return IRQ_NONE;
>> +
>> + if ((ien & st) == ien)
>> + complete(&nfc->complete);
>> +
>> + writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
>> + writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
>> + unsigned int timeout_ms)
>> +{
>> + init_completion(&nfc->complete);
>> +
>> + writel(flags, nfc->regs + NFC_REG_INT);
>> + if (!timeout_ms)
>> + wait_for_completion(&nfc->complete);
>> + else if (!wait_for_completion_timeout(&nfc->complete,
>> + msecs_to_jiffies(timeout_ms)))
>> + return -ETIMEDOUT;
>> +
>> + return 0;
>> +}
>> +
>> +static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
>> +{
>> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
>> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
>> + struct sunxi_nand_rb *rb;
>> + unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
>> + int ret;
>> +
>> + if (sunxi_nand->selected < 0)
>> + return 0;
>> +
>> + rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
>> +
>> + switch (rb->type) {
>> + case RB_NATIVE:
>> + ret = !!(readl(nfc->regs + NFC_REG_ST) &
>> + (NFC_RB_STATE0 << rb->info.nativeid));
>> + if (ret)
>> + break;
>> +
>> + sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
>> + ret = !!(readl(nfc->regs + NFC_REG_ST) &
>> + (NFC_RB_STATE0 << rb->info.nativeid));
>> + break;
>> + case RB_GPIO:
>> + ret = gpio_get_value(rb->info.gpio);
>> + break;
>> + case RB_NONE:
>> + default:
>> + ret = 0;
>> + dev_err(&mtd->dev, "cannot check R/B NAND status!");
>> + break;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
>> +{
>> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
>> + struct nand_chip *nand = &sunxi_nand->nand;
>> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
>> + struct sunxi_nand_chip_sel *sel;
>> + u32 ctl;
>> +
>> + if (chip > 0 && chip >= sunxi_nand->nsels)
>> + return;
>> +
>> + if (chip == sunxi_nand->selected)
>> + return;
>> +
>> + ctl = readl(nfc->regs + NFC_REG_CTL) &
>> + ~(NFC_CE_SEL | NFC_RB_SEL | NFC_EN);
>> +
>> + if (chip >= 0) {
>> + sel = &sunxi_nand->sels[chip];
>> +
>> + ctl |= (sel->cs << 24) | NFC_EN |
>> + (((nand->page_shift - 10) & 0xf) << 8);
>> + if (sel->rb.type == RB_NONE) {
>> + nand->dev_ready = NULL;
>> + } else {
>> + nand->dev_ready = sunxi_nfc_dev_ready;
>> + if (sel->rb.type == RB_NATIVE)
>> + ctl |= (sel->rb.info.nativeid << 3);
>> + }
>> +
>> + writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
>> +
>> + if (nfc->clk_rate != sunxi_nand->clk_rate) {
>> + clk_set_rate(nfc->sclk, sunxi_nand->clk_rate);
>> + nfc->clk_rate = sunxi_nand->clk_rate;
>> + }
>> + }
>> +
>> + writel(ctl, nfc->regs + NFC_REG_CTL);
>> +
>> + sunxi_nand->selected = chip;
>> +}
>> +
>> +static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>> +{
>> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
>> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
>> + int cnt;
>> + int offs = 0;
>> + u32 tmp;
>> +
>> + while (len > offs) {
>> + cnt = len - offs;
>> + if (cnt > 1024)
>> + cnt = 1024;
>> +
>> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
>> + ;
>> + writel(cnt, nfc->regs + NFC_REG_CNT);
>> + tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
>> + writel(tmp, nfc->regs + NFC_REG_CMD);
>> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
>> + if (buf)
>> + memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
>> + cnt);
>> + offs += cnt;
>> + }
>> +}
>> +
>> +static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
>> + int len)
>> +{
>> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
>> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
>> + int cnt;
>> + int offs = 0;
>> + u32 tmp;
>> +
>> + while (len > offs) {
>> + cnt = len - offs;
>> + if (cnt > 1024)
>> + cnt = 1024;
>> +
>> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
>> + ;
>> + writel(cnt, nfc->regs + NFC_REG_CNT);
>> + memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
>> + tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
>> + NFC_ACCESS_DIR;
>> + writel(tmp, nfc->regs + NFC_REG_CMD);
>> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
>> + offs += cnt;
>> + }
>> +}
>> +
>> +static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
>> +{
>> + uint8_t ret;
>> +
>> + sunxi_nfc_read_buf(mtd, &ret, 1);
>> +
>> + return ret;
>> +}
>> +
>> +static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
>> + unsigned int ctrl)
>> +{
>> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
>> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
>> + u32 tmp;
>> +
>> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
>> + ;
>> +
>> + if (ctrl & NAND_CTRL_CHANGE) {
>> + tmp = readl(nfc->regs + NFC_REG_CTL);
>> + if (ctrl & NAND_NCE)
>> + tmp |= NFC_CE_CTL;
>> + else
>> + tmp &= ~NFC_CE_CTL;
>> + writel(tmp, nfc->regs + NFC_REG_CTL);
>> + }
>> +
>> + if (dat == NAND_CMD_NONE)
>> + return;
>> +
>> + if (ctrl & NAND_CLE) {
>> + writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
>> + } else {
>> + writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
>> + writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
>> + }
>> +
>> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
>> +}
>> +
>> +static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
>> + const struct nand_sdr_timings *timings)
>> +{
>> + u32 min_clk_period = 0;
>> +
>> + /* T1 <=> tCLS */
>> + if (timings->tCLS_min > min_clk_period)
>> + min_clk_period = timings->tCLS_min;
>> +
>> + /* T2 <=> tCLH */
>> + if (timings->tCLH_min > min_clk_period)
>> + min_clk_period = timings->tCLH_min;
>> +
>> + /* T3 <=> tCS */
>> + if (timings->tCS_min > min_clk_period)
>> + min_clk_period = timings->tCS_min;
>> +
>> + /* T4 <=> tCH */
>> + if (timings->tCH_min > min_clk_period)
>> + min_clk_period = timings->tCH_min;
>> +
>> + /* T5 <=> tWP */
>> + if (timings->tWP_min > min_clk_period)
>> + min_clk_period = timings->tWP_min;
>> +
>> + /* T6 <=> tWH */
>> + if (timings->tWH_min > min_clk_period)
>> + min_clk_period = timings->tWH_min;
>> +
>> + /* T7 <=> tALS */
>> + if (timings->tALS_min > min_clk_period)
>> + min_clk_period = timings->tALS_min;
>> +
>> + /* T8 <=> tDS */
>> + if (timings->tDS_min > min_clk_period)
>> + min_clk_period = timings->tDS_min;
>> +
>> + /* T9 <=> tDH */
>> + if (timings->tDH_min > min_clk_period)
>> + min_clk_period = timings->tDH_min;
>> +
>> + /* T10 <=> tRR */
>> + if (timings->tRR_min > (min_clk_period * 3))
>> + min_clk_period = (timings->tRR_min + 2) / 3;
>> +
>> + /* T11 <=> tALH */
>> + if (timings->tALH_min > min_clk_period)
>> + min_clk_period = timings->tALH_min;
>> +
>> + /* T12 <=> tRP */
>> + if (timings->tRP_min > min_clk_period)
>> + min_clk_period = timings->tRP_min;
>> +
>> + /* T13 <=> tREH */
>> + if (timings->tREH_min > min_clk_period)
>> + min_clk_period = timings->tREH_min;
>> +
>> + /* T14 <=> tRC */
>> + if (timings->tRC_min > (min_clk_period * 2))
>> + min_clk_period = (timings->tRC_min + 1) / 2;
>> +
>> + /* T15 <=> tWC */
>> + if (timings->tWC_min > (min_clk_period * 2))
>> + min_clk_period = (timings->tWC_min + 1) / 2;
>> +
>> +
>> + /* min_clk_period = (NAND-clk-period * 2) */
>> + if (min_clk_period < 1000)
>> + min_clk_period = 1000;
>> +
>> + min_clk_period /= 1000;
>> + chip->clk_rate = (2 * 1000000000) / min_clk_period;
>> +
>> + /* TODO: configure T16-T19 */
>> +
>> + return 0;
>> +}
>> +
>> +static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
>> + struct device_node *np)
>> +{
>> + const struct nand_sdr_timings *timings;
>> + int ret;
>> +
>> + ret = onfi_get_async_timing_mode(&chip->nand);
>> + if (ret == ONFI_TIMING_MODE_UNKNOWN) {
>> + ret = of_get_nand_onfi_timing_mode(np);
>> + if (ret < 0)
>> + return ret;
>> + }
>> +
>> + ret = fls(ret);
>> + if (!ret)
>> + return -EINVAL;
>> +
>> + timings = onfi_async_timing_mode_to_sdr_timings(ret - 1);
>> + if (IS_ERR(timings))
>> + return PTR_ERR(timings);
>> +
>> + return sunxi_nand_chip_set_timings(chip, timings);
>> +}
>> +
>> +static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
>> + struct device_node *np)
>> +{
>> + const struct nand_sdr_timings *timings;
>> + struct sunxi_nand_chip *chip;
>> + struct mtd_part_parser_data ppdata;
>> + struct mtd_info *mtd;
>> + struct nand_chip *nand;
>> + u32 strength;
>> + u32 blk_size;
>> + int nsels;
>> + int ret;
>> + int i;
>> + u32 tmp;
>> +
>> + if (!of_get_property(np, "reg", &nsels))
>> + return -EINVAL;
>> +
>> + nsels /= sizeof(u32);
>> + if (!nsels)
>> + return -EINVAL;
>> +
>> + chip = devm_kzalloc(dev,
>> + sizeof(*chip) +
>> + (nsels * sizeof(struct sunxi_nand_chip_sel)),
>> + GFP_KERNEL);
>> + if (!chip)
>> + return -ENOMEM;
>> +
>> + chip->nsels = nsels;
>> + chip->selected = -1;
>> +
>> + for (i = 0; i < nsels; i++) {
>> + ret = of_property_read_u32_index(np, "reg", i, &tmp);
>> + if (ret)
>> + return ret;
>> +
>> + if (tmp > 7)
>> + return -EINVAL;
>> +
>> + if (test_and_set_bit(tmp, &nfc->assigned_cs))
>> + return -EINVAL;
>> +
>> + chip->sels[i].cs = tmp;
>> +
>> + if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
>> + tmp < 2) {
>> + chip->sels[i].rb.type = RB_NATIVE;
>> + chip->sels[i].rb.info.nativeid = tmp;
>> + } else {
>> + ret = of_get_named_gpio(np, "rb-gpios", i);
>> + if (ret >= 0) {
>> + tmp = ret;
>> + chip->sels[i].rb.type = RB_GPIO;
>> + chip->sels[i].rb.info.gpio = tmp;
>> + ret = devm_gpio_request(dev, tmp, "nand-rb");
>> + if (ret)
>> + return ret;
>> +
>> + ret = gpio_direction_input(tmp);
>> + if (ret)
>> + return ret;
>> + } else {
>> + chip->sels[i].rb.type = RB_NONE;
>> + }
>> + }
>> + }
>> +
>> + timings = onfi_async_timing_mode_to_sdr_timings(0);
>> + if (IS_ERR(timings))
>> + return PTR_ERR(timings);
>> +
>> + ret = sunxi_nand_chip_set_timings(chip, timings);
>> +
>> + nand = &chip->nand;
>> + nand->controller = &nfc->controller;
>> + nand->select_chip = sunxi_nfc_select_chip;
>> + nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
>> + nand->read_buf = sunxi_nfc_read_buf;
>> + nand->write_buf = sunxi_nfc_write_buf;
>> + nand->read_byte = sunxi_nfc_read_byte;
>> +
>> + nand->ecc.mode = of_get_nand_ecc_mode(np);
>> + if (of_get_nand_on_flash_bbt(np))
>> + nand->bbt_options |= NAND_BBT_USE_FLASH;
>> +
>> + mtd = &chip->mtd;
>> + mtd->priv = nand;
>> + mtd->owner = THIS_MODULE;
>> +
>> + ret = nand_scan_ident(mtd, nsels, NULL);
>> + if (ret)
>> + return ret;
>> +
>> + ret = sunxi_nand_chip_init_timings(chip, np);
>> + if (ret)
>> + return ret;
>> +
>> + if (nand->ecc.mode == NAND_ECC_SOFT_BCH) {
>> + if (!of_get_nand_ecc_level(np, &strength, &blk_size)) {
>> + nand->ecc_step_ds = blk_size;
>> + nand->ecc_strength_ds = strength;
>> + }
>> +
>> + nand->ecc.size = nand->ecc_step_ds;
>> + nand->ecc.bytes = (((nand->ecc_strength_ds *
>> + fls(8 * nand->ecc_step_ds)) + 7) / 8);
>> + }
>> +
>> + ret = nand_scan_tail(mtd);
>> + if (ret)
>> + return ret;
>> +
>> + if (of_property_read_string(np, "nand-name", &mtd->name)) {
>> + snprintf(chip->default_name, MAX_NAME_SIZE,
>> + DEFAULT_NAME_FORMAT, chip->sels[i].cs);
>> + mtd->name = chip->default_name;
>> + }
>> +
>> + ppdata.of_node = np;
>> + ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
>> + if (!ret)
>> + return ret;
>> +
>> + list_add_tail(&chip->node, &nfc->chips);
>> +
>> + return 0;
>> +}
>> +
>> +static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
>> +{
>> + struct device_node *np = dev->of_node;
>> + struct device_node *nand_np;
>> + int nchips = of_get_child_count(np);
>> + int ret;
>> +
>> + if (nchips > 8)
>> + return -EINVAL;
>> +
>> + for_each_child_of_node(np, nand_np) {
>> + ret = sunxi_nand_chip_init(dev, nfc, nand_np);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int sunxi_nfc_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct resource *r;
>> + struct sunxi_nfc *nfc;
>> + int ret;
>> +
>> + nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
>> + if (!nfc) {
>> + dev_err(dev, "failed to allocate NFC struct\n");
>> + return -ENOMEM;
>> + }
>> +
>> + spin_lock_init(&nfc->controller.lock);
>> + init_waitqueue_head(&nfc->controller.wq);
>> + INIT_LIST_HEAD(&nfc->chips);
>> +
>> + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + nfc->regs = devm_ioremap_resource(dev, r);
>> + if (IS_ERR(nfc->regs)) {
>> + dev_err(dev, "failed to remap iomem\n");
>> + return PTR_ERR(nfc->regs);
>> + }
>> +
>> + nfc->irq = platform_get_irq(pdev, 0);
>> + if (nfc->irq < 0) {
>> + dev_err(dev, "failed to retrieve irq\n");
>> + return nfc->irq;
>> + }
>> +
>> + nfc->ahb_clk = devm_clk_get(dev, "ahb_clk");
>> + if (IS_ERR(nfc->ahb_clk)) {
>> + dev_err(dev, "failed to retrieve ahb_clk\n");
>> + return PTR_ERR(nfc->ahb_clk);
>> + }
>> +
>> + ret = clk_prepare_enable(nfc->ahb_clk);
>> + if (ret)
>> + return ret;
>> +
>> + nfc->sclk = devm_clk_get(dev, "sclk");
>> + if (IS_ERR(nfc->sclk)) {
>> + dev_err(dev, "failed to retrieve nand_clk\n");
>> + ret = PTR_ERR(nfc->sclk);
>> + goto out_ahb_clk_unprepare;
>> + }
>> +
>> + ret = clk_prepare_enable(nfc->sclk);
>> + if (ret)
>> + goto out_ahb_clk_unprepare;
>> +
>> + /* Reset NFC */
>> + writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RESET,
>> + nfc->regs + NFC_REG_CTL);
>> + while (readl(nfc->regs + NFC_REG_CTL) & NFC_RESET)
>> + ;
>> +
>> + writel(0, nfc->regs + NFC_REG_INT);
>> + ret = devm_request_irq(dev, nfc->irq, sunxi_nfc_interrupt,
>> + 0, "sunxi-nand", nfc);
>> + if (ret)
>> + goto out_sclk_unprepare;
>> +
>> + platform_set_drvdata(pdev, nfc);
>> +
>> + writel(0x100, nfc->regs + NFC_REG_TIMING_CTL);
>> + writel(0x7ff, nfc->regs + NFC_REG_TIMING_CFG);
>> +
>> + ret = sunxi_nand_chips_init(dev, nfc);
>> + if (ret) {
>> + dev_err(dev, "failed to init nand chips\n");
>> + goto out_sclk_unprepare;
>> + }
>> +
>> + return 0;
>> +
>> +out_sclk_unprepare:
>> + clk_disable_unprepare(nfc->sclk);
>> +out_ahb_clk_unprepare:
>> + clk_disable_unprepare(nfc->ahb_clk);
>> +
>> + return ret;
>> +}
>> +
>> +static const struct of_device_id sunxi_nfc_ids[] = {
>> + { .compatible = "allwinner,sun4i-nand" },
>> + { /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
>> +
>> +static struct platform_driver sunxi_nfc_driver = {
>> + .driver = {
>> + .name = "sunxi_nand",
>> + .owner = THIS_MODULE,
>> + .of_match_table = of_match_ptr(sunxi_nfc_ids),
>> + },
>> + .probe = sunxi_nfc_probe,
>> +};
>> +module_platform_driver(sunxi_nfc_driver);
>> +
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_AUTHOR("Boris BREZILLON");
>> +MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
>> +MODULE_ALIAS("platform:sunxi_nfc");
>> --
>> 1.7.9.5
>>
^ permalink raw reply
* [PATCH v2 1/7] cpufreq: cpufreq-cpu0: allow optional safe voltage during frequency transitions
From: Heiko Stübner @ 2014-01-30 15:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJuA9ajLUPtsReomPuuzMpshTEiUz81sc4584DEVQnG=iwGb-g@mail.gmail.com>
On Thursday, 30. January 2014 18:23:44 Thomas Abraham wrote:
> Hi Mike,
>
> On Wed, Jan 29, 2014 at 12:17 AM, Mike Turquette <mturquette@linaro.org>
wrote:
> > On Mon, Jan 27, 2014 at 9:30 PM, Thomas Abraham <ta.omasab@gmail.com>
wrote:
> >> Hi Mike,
> >>
> >> On Tue, Jan 28, 2014 at 1:55 AM, Mike Turquette <mturquette@linaro.org>
wrote:
> >>> Quoting Thomas Abraham (2014-01-18 04:10:51)
> >>>
> > As far as I can tell
> > the remux does not happen because it is necessary to generate the
> > required clock rate, but because we don't want to run the ARM core out
> > of spec for a short time while the PLL relocks. Assuming I have that
> > part of it right, I prefer for the parent mux operation to be a part
> > of the CPUfreq driver's .target callback instead of hidden away in the
> > clock driver.
>
> The re-parenting is mostly done to keep the ARM CPU clocked while the
> PLL is stopped, reprogrammed and restarted. One of the side effects of
> that is, the clock speed of the temporary parent could be higher then
> what is allowed due to the ARM voltage at the time of re-parenting.
> That is the reason to use the safe voltage.
The Rockchip-SoCs use something similar, so I'm following quite closely what
Thomas is trying to do here, as similar solution would also solve this issue
for me.
On some Rockchip-SoCs even stuff like pclk and hclk seems to be sourced from
the divided armclk, creating additional constraints.
But on the RKs (at least in the upstream sources) the armclk is simply equal
to the pll output. A divider exists, but is only used to make sure that the
armclk stays below the original rate when sourced from the temp-parent, like
if (clk_get_rate(temp_parent) > clk_get_rate(main_parent)
set_divider(something so that rate(temp) <= rate(main)
clk_set_parent(...)
Isn't there a similar possiblity on your platform, as it would remove the need
for the safe-voltage?
In general I also like the approach of hiding the rate-change logic inside
this composite clock, as the depending clocks can be easily kept in sync. As
with the Rockchips the depending clocks are different for each of the three
Cortex-A9 SoCs I looked at, it would be "interesting" if all of this would
need to be done in a cpufreq driver.
Heiko
^ permalink raw reply
* Root NFS panicing on Linus' tip (Re: NFS client broken in Linus' tip)
From: Ezequiel Garcia @ 2014-01-30 15:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140130140834.GW15937@n2100.arm.linux.org.uk>
Hi Russell, Trond:
On Thu, Jan 30, 2014 at 02:08:34PM +0000, Russell King - ARM Linux wrote:
> I just booted Linus' tip (plus a few other patches to imx-drm and imx
> code), and stumbled into this interesting scenario:
>
[..]
> CONFIG_NFS_FS=y
> CONFIG_NFS_V2=y
> CONFIG_NFS_V3=y
> CONFIG_NFS_V3_ACL=y
Just came across another issue, but a bit more problematic, as my
kernel (Linus' tip as well) panics, after mounting the rootfs:
IP-Config: Complete:
device=eth0, hwaddr=00:50:43:50:1c:15, ipaddr=192.168.0.159, mask=255.255.255.0, gw=192.168.0.1
host=develboard, domain=, nis-domain=(none)
bootserver=192.168.0.45, rootserver=192.168.0.45, rootpath=
VFS: Mounted root (nfs filesystem) on device 0:11.
devtmpfs: mounted
Freeing unused kernel memory: 136K (c0465000 - c0487000)
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 5 [#1] ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper Tainted: G W 3.13.0-10094-g9b0cd30 #276
task: ed839a40 ti: ed83a000 task.ti: ed83a000
PC is at xattr_resolve_name+0x14/0x94
LR is at generic_getxattr+0x2c/0x64
pc : [<c00a7ab0>] lr : [<c00a7b5c>] psr: a0000113
sp : ed83be5c ip : ed83be74 fp : ed10ebc0
r10: ed83a000 r9 : ed43d980 r8 : ed81b800
r7 : c034dad8 r6 : 00000000 r5 : c03f3dcc r4 : ed43d980
r3 : 00000014 r2 : ed83be8c r1 : ed83be74 r0 : 00000000
Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 00004059 DAC: 00000015
Process swapper (pid: 1, stack limit = 0xed83a238)
Stack: (0xed83be5c to 0xed83c000)
be40: ed43d980
be60: 00000014 ed83be8c 00000000 00000000 c04bc22c c03f3dcc ed83bf14 ed43f340
be80: ed43d980 c01115cc 00000000 00000041 c04bba6c 00000000 00000000 002040d0
bea0: ed81bc00 ed10ebc0 ed81bc30 c01116f8 00000000 000004d0 ed8172d0 ed43d980
bec0: 45878fd4 00000007 bfe01007 ef7f8fc0 c04bba6c ed43d6d8 c04bba6c 00000101
bee0: 00000000 ed809fd0 ed809fc0 ed809f50 ed809f40 00000000 edb045d8 c0078bcc
bf00: ed0e5dc0 edb045d8 00000000 bf000000 ed0e5dc0 00000000 00000000 00000000
bf20: 00000000 00000000 bf000000 ed10ebc0 ed0e5dc0 00000001 edb045d8 c04926d0
bf40: ed83a000 c0492758 ed10ebc0 c008fc54 00000001 ed0e5dc0 00000002 c0090cec
bf60: c03ec85c ed0e5df4 00000000 ed839c00 c0487000 c04bcec0 c03e4f08 00000000
bf80: 00000000 00000000 00000000 00000000 00000000 c00086a8 00000000 c04bcec0
bfa0: c0344f5c c0345004 00000000 c000e398 00000000 00000000 00000000 00000000
bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
bfe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
[<c00a7ab0>] (xattr_resolve_name) from [<00000000>] ( (null))
Code: e1a06000 e5915000 e3550000 0a00001d (e5900000)
---[ end trace 15c15b4afa9eff90 ]---
swapper (1) used greatest stack depth: 5104 bytes left
Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
Adding a little hack, and could produce a better strack trace.
See the diff and the stack trace below:
diff --git a/fs/xattr.c b/fs/xattr.c
index 3377dff..bd2b173 100644
--- a/fs/xattr.c
+++ b/fs/xattr.c
@@ -740,6 +740,10 @@ xattr_resolve_name(const struct xattr_handler **handlers, const char **name)
if (!*name)
return NULL;
+ if(!handlers) {
+ dump_stack();
+ panic("ouch");
+ }
for_each_xattr_handler(handlers, handler) {
const char *n = strcmp_prefix(*name, handler->prefix);
CPU: 0 PID: 1 Comm: swapper Tainted: G W 3.13.0-10094-g9b0cd30-dirty #279
[<c0012f40>] (unwind_backtrace) from [<c00107b8>] (show_stack+0x10/0x14)
[<c00107b8>] (show_stack) from [<c00a8160>] (xattr_resolve_name+0x9c/0xa8)
[<c00a8160>] (xattr_resolve_name) from [<c00a8274>] (generic_getxattr+0x2c/0x64)
[<c00a8274>] (generic_getxattr) from [<c01115e0>] (get_vfs_caps_from_disk+0x4c/0xf4)
[<c01115e0>] (get_vfs_caps_from_disk) from [<c011170c>] (cap_bprm_set_creds+0x84/0x408)
[<c011170c>] (cap_bprm_set_creds) from [<c008fc54>] (prepare_binprm+0x80/0x11c)
[<c008fc54>] (prepare_binprm) from [<c0090cec>] (do_execve+0x33c/0x46c)
[<c0090cec>] (do_execve) from [<c00086a8>] (try_to_run_init_process+0x1c/0x50)
[<c00086a8>] (try_to_run_init_process) from [<c0345024>] (kernel_init+0xa8/0x110)
[<c0345024>] (kernel_init) from [<c000e398>] (ret_from_fork+0x14/0x3c)
Kernel panic - not syncing: ouch
FWIW, here's my piece of NFS config:
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_SWAP is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
> I think it's down to this:
>
> commit 013cdf1088d7235da9477a2375654921d9b9ba9f
> Author: Christoph Hellwig <hch@infradead.org>
> Date: Fri Dec 20 05:16:53 2013 -0800
>
> nfs: use generic posix ACL infrastructure for v3 Posix ACLs
>
> This causes a small behaviour change in that we don't bother to set
> ACLs on file creation if the mode bit can express the access permissions
> fully, and thus behaving identical to local filesystems.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
And also here, reverting the above seem to fix the panic.
Ideas?
--
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
^ permalink raw reply related
* [PATCH v2 1/2] drivers/media: v4l2: Add settings for Horizontal and Vertical MV Search Range
From: Kamil Debski @ 2014-01-30 15:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52EA00E5.10303@xs4all.nl>
Hi Hans, Amit,
> From: Hans Verkuil [mailto:hverkuil at xs4all.nl]
> Sent: Thursday, January 30, 2014 8:36 AM
>
> On 01/30/2014 06:42 AM, Amit Grover wrote:
> > Adding V4L2 controls for horizontal and vertical search range in
> > pixels for motion estimation module in video encoder.
> >
> > Signed-off-by: Swami Nathan <swaminath.p@samsung.com>
> > Signed-off-by: Amit Grover <amit.grover@samsung.com>
> > ---
> > Documentation/DocBook/media/v4l/controls.xml | 20
> ++++++++++++++++++++
> > drivers/media/v4l2-core/v4l2-ctrls.c | 14 ++++++++++++++
> > include/uapi/linux/v4l2-controls.h | 2 ++
> > 3 files changed, 36 insertions(+)
> >
> > diff --git a/Documentation/DocBook/media/v4l/controls.xml
> > b/Documentation/DocBook/media/v4l/controls.xml
> > index 7a3b49b..be04d18 100644
> > --- a/Documentation/DocBook/media/v4l/controls.xml
> > +++ b/Documentation/DocBook/media/v4l/controls.xml
> > @@ -2258,6 +2258,26 @@ Applicable to the MPEG1, MPEG2, MPEG4
> > encoders.</entry> VBV buffer control.</entry>
> > </row>
> >
> > + <row><entry></entry></row>
> > + <row id=""v4l2-mpeg-video-hor-search-range">
> > + <entry
> spanname="id"><constant>V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE</constant
> > </entry>
> > + <entry>integer</entry>
> > + </row>
> > + <row><entry spanname="descr">Horizontal search range
> defines
> > +maximum horizontal search area in pixels to search and match for the
> > +present Macroblock (MB) in the reference picture. This V4L2 control
> macro is used to set horizontal search range for motion estimation
> module in video encoder.</entry>
> > + </row>
> > +
> > + <row><entry></entry></row>
> > + <row id="v4l2-mpeg-video-vert-search-range">
> > + <entry
> spanname="id"><constant>V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE</constant
> > </entry>
> > + <entry>integer</entry>
>
> These two controls sound very mfc specific as opposed to being part of
> the standard.
> If so, then they should be named V4L2_CID_MPEG_MFC51_*.
mencoder has an option to set motion vector search radius.
>From man mencoder:
me_range=<4-64>
radius of exhaustive or multi-hexagon motion search
(default:
16)
So I think it could be applicable to other hardware codecs as well.
> Also, for which codecs are these controls applicable?
Isn't the choice of motion estimation algorithm (and its parameters)
codec agnostic, as long as the restrictions of the standard are honoured?
>
> > + </row>
> > + <row><entry spanname="descr">Vertical search range defines
> maximum
> > +vertical search area in pixels to search and match for the present
> > +Macroblock (MB) in the reference picture. This V4L2 control macro is
> used to set vertical search range for motion estimation module in video
> encoder.</entry>
> > + </row>
> > +
> > <row><entry></entry></row>
> > <row>
> > <entry
> >
> spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE</constant>&n
> > bsp;</entry> diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c
> > b/drivers/media/v4l2-core/v4l2-ctrls.c
> > index fb46790..e775388 100644
> > --- a/drivers/media/v4l2-core/v4l2-ctrls.c
> > +++ b/drivers/media/v4l2-core/v4l2-ctrls.c
> > @@ -735,6 +735,8 @@ const char *v4l2_ctrl_get_name(u32 id)
> > case V4L2_CID_MPEG_VIDEO_DEC_PTS: return
"Video
> Decoder PTS";
> > case V4L2_CID_MPEG_VIDEO_DEC_FRAME: return
"Video
> Decoder Frame Count";
> > case V4L2_CID_MPEG_VIDEO_VBV_DELAY: return
"Initial
> Delay for VBV Control";
> > + case V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE: return
> "Horizontal MV Search Range";
> > + case V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE: return
> "Vertical MV Search Range";
> > case V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER: return
> "Repeat Sequence Header";
> >
> > /* VPX controls */
> > @@ -905,6 +907,18 @@ void v4l2_ctrl_fill(u32 id, const char **name,
> enum v4l2_ctrl_type *type,
> > *min = 0;
> > *max = *step = 1;
> > break;
> > + case V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE:
> > + *type = V4L2_CTRL_TYPE_INTEGER;
> > + *min = 16;
> > + *max = 128;
> > + *step = 16;
>
> Weird range, why not use range 1-8?
If the search range is represented in pixels, then pixels should be used.
It the control is also used in other hardware, then I think it the values
should not be limited in this way here. For example mencoder accepts the
value between 4 and 64. The range and step could be limited in the
s5p_mfc_enc.c.
>
> > + break;
> > + case V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE:
> > + *type = V4L2_CTRL_TYPE_INTEGER;
> > + *min = 16;
> > + *max = 128;
> > + *step = 16;
> > + break;
> > case V4L2_CID_PAN_RESET:
> > case V4L2_CID_TILT_RESET:
> > case V4L2_CID_FLASH_STROBE:
> > diff --git a/include/uapi/linux/v4l2-controls.h
> > b/include/uapi/linux/v4l2-controls.h
> > index 1666aab..80e1def 100644
> > --- a/include/uapi/linux/v4l2-controls.h
> > +++ b/include/uapi/linux/v4l2-controls.h
> > @@ -372,6 +372,8 @@ enum v4l2_mpeg_video_multi_slice_mode {
> > #define V4L2_CID_MPEG_VIDEO_DEC_FRAME
> (V4L2_CID_MPEG_BASE+224)
> > #define V4L2_CID_MPEG_VIDEO_VBV_DELAY
> (V4L2_CID_MPEG_BASE+225)
> > #define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER
> (V4L2_CID_MPEG_BASE+226)
> > +#define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE
> (V4L2_CID_MPEG_BASE+227)
> > +#define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE
> (V4L2_CID_MPEG_BASE+228)
> >
> > #define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP
> (V4L2_CID_MPEG_BASE+300)
> > #define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP
> (V4L2_CID_MPEG_BASE+301)
> >
>
> Regards,
>
> Hans
Best wishes,
--
Kamil Debski
Samsung R&D Institute Poland
^ permalink raw reply
* [PATCH v2 6/6] cpu/idle.c: move to sched/idle.c
From: Peter Zijlstra @ 2014-01-30 15:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391017513-12995-7-git-send-email-nicolas.pitre@linaro.org>
On Wed, Jan 29, 2014 at 12:45:13PM -0500, Nicolas Pitre wrote:
> Integration of cpuidle with the scheduler requires that the idle loop be
> closely integrated with the scheduler proper. Moving cpu/idle.c into the
> sched directory will allow for a smoother integration, and eliminate a
> subdirectory which contained only one source file.
>
> Signed-off-by: Nicolas Pitre <nico@linaro.org>
> ---
> kernel/Makefile | 1 -
> kernel/cpu/Makefile | 1 -
> kernel/sched/Makefile | 2 +-
> kernel/{cpu => sched}/idle.c | 0
> 4 files changed, 1 insertion(+), 3 deletions(-)
> delete mode 100644 kernel/cpu/Makefile
> rename kernel/{cpu => sched}/idle.c (100%)
> --- a/kernel/sched/Makefile
> +++ b/kernel/sched/Makefile
> @@ -11,7 +11,7 @@ ifneq ($(CONFIG_SCHED_OMIT_FRAME_POINTER),y)
> CFLAGS_core.o := $(PROFILING) -fno-omit-frame-pointer
> endif
>
> -obj-y += core.o proc.o clock.o cputime.o idle_task.o fair.o rt.o stop_task.o
> +obj-y += core.o proc.o clock.o cputime.o idle_task.o idle.o fair.o rt.o stop_task.o
> obj-y += wait.o completion.o
> obj-$(CONFIG_SMP) += cpupri.o
> obj-$(CONFIG_SCHED_AUTOGROUP) += auto_group.o
> diff --git a/kernel/cpu/idle.c b/kernel/sched/idle.c
> similarity index 100%
> rename from kernel/cpu/idle.c
> rename to kernel/sched/idle.c
This is not a valid patch for PATCH(1). Please try again.
^ permalink raw reply
* [PATCH v3 0/2] Qualcomm Universal Peripheral (QUP) I2C controller
From: Ivan T. Ivanov @ 2014-01-30 15:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJAp7Oj_D1QvG9nBWTVrW1QVEpqi2cTTc9c6Um25DDzidCjW1w@mail.gmail.com>
Hi Bjorn,
On Wed, 2014-01-29 at 08:32 -0800, Bjorn Andersson wrote:
> On Wed, Jan 29, 2014 at 12:14 AM, Ivan T. Ivanov <iivanov@mm-sol.com> wrote:
> >
> > Hi Bjorn,
> >
> > On Fri, 2014-01-17 at 15:03 -0800, Bjorn Andersson wrote:
> >> Continuing on Ivans i2c-qup series.
> >>
> >
> > Do you plan to send v4 of this driver? I would like to address
> > the remaining errors and suggestions and send a new version.
> >
> Hi Ivan,
>
> Yes I'm planning to send out a new revision of the patch set.
>
> I've incorporated fixes from the review comments here and my colleague
> concluded through some testing that block read did not work, so we've
> fixed that as well.
Busted. I have not test it.
>
> What have been holding me from submitting a new patchset is the 3
> functions that does polling of state and status updates;
> * qup_i2c_poll_state() reads the state register up to 1000 times,
> hoping we reach the expected state, will delay 100uS and then continue
> with 1000 more retries.
> According to the data sheet a state transition is supposed to take
> up to 2 bus cycles. Only time I can see that this would take longer
> time are all error states, but the data sheet is not very clear
> regarding this.
>
> * qup_i2c_wait_idle() reads the status register up to 1000 times,
> hoping the fifo gets drained and the bus go idle, if that fails it
> sleeps for the time we expect it to take to drain a full fifo and then
> loops another 1000 times. This waits for the fifo to have drained and
> the bus to go idle. On a read we get to this state if we issue the
> write and then hit the error state, so we would reset the entire
> block. On write we will only wait for the buffer not to be full before
> returning.
>
> * qup_i2c_wait_clock_ready() waits up to 300 bus-clocks for the i2c
> bus to go idle or forced low, I don't know why it retries 300 times.
> This is called at the end of a write, possibly to wait for the fifo to
> drain.
>
>
> All three loops are in line with how it's been in codeaurora since the
> beginning of time, but I at least need to figure out some good names
> for those "magic numbers".
Sure. I have keep them this way, just because I don't have information
for internal trickery of the block.
Thanks,
Ivan
>
> Regards,
> Bjorn
^ permalink raw reply
* NFS client broken in Linus' tip
From: Russell King - ARM Linux @ 2014-01-30 15:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140130143208.GB9573@infradead.org>
On Thu, Jan 30, 2014 at 06:32:08AM -0800, Christoph Hellwig wrote:
> On Thu, Jan 30, 2014 at 02:27:52PM +0000, Russell King - ARM Linux wrote:
> > Yes and no. I still end up with an empty /etc/mtab, but the file now
> > exists. However, I can create and echo data into /etc/mtab, but it seems
> > that can't happen at boot time.
>
> Odd. Can you disable CONFIG_NFSD_V3_ACL for now to isolate the issue?
Unfortunately, that results in some problem at boot time, which
ultimately ends up with the other three CPUs being stopped, and
hence the original reason scrolls off the screen before it can be
read... even at 1920p.
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* [PATCH v3 2/8] clk: sunxi: update clock-output-names dt binding documentation
From: Maxime Ripard @ 2014-01-30 15:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v66+N9tgOO4X093WdiR4J+7Sk2TDVsMffDGo46iTezPQwA@mail.gmail.com>
Hi Chen-Yu,
On Wed, Jan 29, 2014 at 09:52:57AM +0800, Chen-Yu Tsai wrote:
> Hi Maxime,
>
> On Fri, Jan 17, 2014 at 10:55 AM, Emilio L?pez <emilio@elopez.com.ar> wrote:
> > Hi,
> >
> > El 09/01/14 05:52, Chen-Yu Tsai escribi?:
> >
> >> clock-output-names is now required for most of sunxi clock nodes, to
> >> provide the name of the corresponding clock. Add the new requirements,
> >> exceptions, as well as examples.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> ---
> >> Documentation/devicetree/bindings/clock/sunxi.txt | 36
> >> +++++++++++++++++++----
> >> 1 file changed, 31 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
> >> b/Documentation/devicetree/bindings/clock/sunxi.txt
> >> index 0c127cd..8a9147d 100644
> >> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> >> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> >> @@ -44,10 +44,18 @@ Required properties for all clocks:
> >> multiplexed clocks, the list order must match the hardware
> >> programming order.
> >> - #clock-cells : from common clock binding; shall be set to 0 except for
> >> - "allwinner,*-gates-clk" where it shall be set to 1
> >> + "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
> >> + "allwinner,sun4i-pll6-clk" where it shall be set to 1
> >>
> >> -Additionally, "allwinner,*-gates-clk" clocks require:
> >> -- clock-output-names : the corresponding gate names that the clock
> >> controls
> >> +Additionally, most clocks require "clock-output-names":
> >> +- "allwinner,*-gates-clk" : the corresponding gate names that the clock
> >> controls
> >> +- "allwinner,sun4i-pll5-clk" : "pll5_ddr", "pll5_mbus"
> >> +- "allwinner,sun4i-pll6-clk" : "pll6_sata", "pll6_other"
> >> +- "allwinner,sun4i-cpu-clk", "allwinner,sun4i-axi-clk",
> >> + "allwinner,sun4i-ahb-clk", "allwinner,sun4i-ahb-clk",
> >> + "allwinner,sun4i-apb1-mux-clk", "allwinner,sun4i-apb1-clk"
> >> + do not need "clock-output-names"
> >> +- all others clocks : the corresponding module name of that clock
> >
> >
> > As we discussed on IRC, I wonder if such verbosity is actually needed. Maybe
> > we should dictate that all clocks must list their corresponding outputs on
> > clock-output-names (with it being the module name if it only has one
> > output).
>
> Maxime, could we get your input on this?
I didn't get it was a question for me. But I'm fine with both. If
making clock-output-names mandatory makes our life easier, let's do
it.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply
* 'unannotated irqs-on' lockdep warning
From: Russell King - ARM Linux @ 2014-01-30 15:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAH9NwWcVrjV1=rFnHJhDH0yoEkTwUTcq-Tn=R0aaiTr70Fs3hA@mail.gmail.com>
On Thu, Jan 30, 2014 at 03:31:46PM +0100, Christian Gmeiner wrote:
> [ 19.859234] CPU: 0 PID: 1848 Comm: mkdir Not tainted 3.12.4 #44
> [ 19.865190] [<c0013900>] (unwind_backtrace+0x0/0xe0) from
> [<c00113b8>] (show_stack+0x10/0x14)
> [ 19.873739] [<c00113b8>] (show_stack+0x10/0x14) from [<c044e040>]
> (dump_stack+0x64/0xa4)
> [ 19.881851] [<c044e040>] (dump_stack+0x64/0xa4) from [<c0022718>]
> (warn_slowpath_common+0x64/0x84)
> [ 19.890828] [<c0022718>] (warn_slowpath_common+0x64/0x84) from
> [<c00227b8>] (warn_slowpath_fmt+0x2c/0x3c)
> [ 19.900413] [<c00227b8>] (warn_slowpath_fmt+0x2c/0x3c) from
> [<c0076c84>] (check_flags.part.26+0xb4/0x1e4)
> [ 19.910001] [<c0076c84>] (check_flags.part.26+0xb4/0x1e4) from
> [<c0079654>] (lock_release+0x3c/0x100)
> [ 19.919243] [<c0079654>] (lock_release+0x3c/0x100) from
> [<c00485b4>] (lg_local_unlock+0x18/0x6c)
> [ 19.928055] [<c00485b4>] (lg_local_unlock+0x18/0x6c) from
> [<c012a2cc>] (free_fs_struct+0x18/0x30)
> [ 19.936947] [<c012a2cc>] (free_fs_struct+0x18/0x30) from
> [<c0024e24>] (do_exit+0x2ac/0x3f0)
> [ 19.945316] [<c0024e24>] (do_exit+0x2ac/0x3f0) from [<c002501c>]
> (do_group_exit+0x88/0xb4)
> [ 19.953596] [<c002501c>] (do_group_exit+0x88/0xb4) from
> [<c0025058>] (__wake_up_parent+0x0/0x18)
> [ 19.962391] ---[ end trace 98a70b5cdc7b49fe ]---
> [ 19.967017] possible reason: unannotated irqs-on.
> [ 19.971729] irq event stamp: 2910
> [ 19.975050] hardirqs last enabled at (2909): [<c044a160>]
> __slab_free+0x1c0/0x390
> [ 19.982661] hardirqs last disabled at (2910): [<c0456d14>]
> __dabt_svc+0x34/0x60
So, I wonder how we got from __dabt_svc to __wake_up_parent. It looks
like the unwinder has failed to do a proper job of unwinding, which
makes this undebuggable.
Can you rebuild in ARM mode with frame pointers enabled please?
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* [PATCH v2 6/6] cpu/idle.c: move to sched/idle.c
From: Nicolas Pitre @ 2014-01-30 16:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140130152500.GB5002@laptop.programming.kicks-ass.net>
On Thu, 30 Jan 2014, Peter Zijlstra wrote:
> On Wed, Jan 29, 2014 at 12:45:13PM -0500, Nicolas Pitre wrote:
> > Integration of cpuidle with the scheduler requires that the idle loop be
> > closely integrated with the scheduler proper. Moving cpu/idle.c into the
> > sched directory will allow for a smoother integration, and eliminate a
> > subdirectory which contained only one source file.
> >
> > Signed-off-by: Nicolas Pitre <nico@linaro.org>
> > ---
> > kernel/Makefile | 1 -
> > kernel/cpu/Makefile | 1 -
> > kernel/sched/Makefile | 2 +-
> > kernel/{cpu => sched}/idle.c | 0
> > 4 files changed, 1 insertion(+), 3 deletions(-)
> > delete mode 100644 kernel/cpu/Makefile
> > rename kernel/{cpu => sched}/idle.c (100%)
>
> > --- a/kernel/sched/Makefile
> > +++ b/kernel/sched/Makefile
> > @@ -11,7 +11,7 @@ ifneq ($(CONFIG_SCHED_OMIT_FRAME_POINTER),y)
> > CFLAGS_core.o := $(PROFILING) -fno-omit-frame-pointer
> > endif
> >
> > -obj-y += core.o proc.o clock.o cputime.o idle_task.o fair.o rt.o stop_task.o
> > +obj-y += core.o proc.o clock.o cputime.o idle_task.o idle.o fair.o rt.o stop_task.o
> > obj-y += wait.o completion.o
> > obj-$(CONFIG_SMP) += cpupri.o
> > obj-$(CONFIG_SCHED_AUTOGROUP) += auto_group.o
> > diff --git a/kernel/cpu/idle.c b/kernel/sched/idle.c
> > similarity index 100%
> > rename from kernel/cpu/idle.c
> > rename to kernel/sched/idle.c
>
> This is not a valid patch for PATCH(1). Please try again.
Don't you use git? ;-)
Here's a plain patch:
----- >8
>From 1bf40eb80a44633094e94986a74bd5ffa222f9d4 Mon Sep 17 00:00:00 2001
From: Nicolas Pitre <nicolas.pitre@linaro.org>
Date: Sun, 26 Jan 2014 23:42:01 -0500
Subject: [PATCH] cpu/idle.c: move to sched/idle.c
Integration of cpuidle with the scheduler requires that the idle loop be
closely integrated with the scheduler proper. Moving cpu/idle.c into the
sched directory will allow for a smoother integration, and eliminate a
subdirectory which contained only one source file.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
---
kernel/Makefile | 1 -
kernel/cpu/Makefile | 1 -
kernel/cpu/idle.c | 144 --------------------------------------------------
kernel/sched/Makefile | 2 +-
kernel/sched/idle.c | 144 ++++++++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 145 insertions(+), 147 deletions(-)
delete mode 100644 kernel/cpu/Makefile
delete mode 100644 kernel/cpu/idle.c
create mode 100644 kernel/sched/idle.c
diff --git a/kernel/Makefile b/kernel/Makefile
index bc010ee272..6f1c7e5cfc 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -22,7 +22,6 @@ obj-y += sched/
obj-y += locking/
obj-y += power/
obj-y += printk/
-obj-y += cpu/
obj-y += irq/
obj-y += rcu/
diff --git a/kernel/cpu/Makefile b/kernel/cpu/Makefile
deleted file mode 100644
index 59ab052ef7..0000000000
--- a/kernel/cpu/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y = idle.o
diff --git a/kernel/cpu/idle.c b/kernel/cpu/idle.c
deleted file mode 100644
index 14ca43430a..0000000000
--- a/kernel/cpu/idle.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Generic entry point for the idle threads
- */
-#include <linux/sched.h>
-#include <linux/cpu.h>
-#include <linux/cpuidle.h>
-#include <linux/tick.h>
-#include <linux/mm.h>
-#include <linux/stackprotector.h>
-
-#include <asm/tlb.h>
-
-#include <trace/events/power.h>
-
-static int __read_mostly cpu_idle_force_poll;
-
-void cpu_idle_poll_ctrl(bool enable)
-{
- if (enable) {
- cpu_idle_force_poll++;
- } else {
- cpu_idle_force_poll--;
- WARN_ON_ONCE(cpu_idle_force_poll < 0);
- }
-}
-
-#ifdef CONFIG_GENERIC_IDLE_POLL_SETUP
-static int __init cpu_idle_poll_setup(char *__unused)
-{
- cpu_idle_force_poll = 1;
- return 1;
-}
-__setup("nohlt", cpu_idle_poll_setup);
-
-static int __init cpu_idle_nopoll_setup(char *__unused)
-{
- cpu_idle_force_poll = 0;
- return 1;
-}
-__setup("hlt", cpu_idle_nopoll_setup);
-#endif
-
-static inline int cpu_idle_poll(void)
-{
- rcu_idle_enter();
- trace_cpu_idle_rcuidle(0, smp_processor_id());
- local_irq_enable();
- while (!tif_need_resched())
- cpu_relax();
- trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
- rcu_idle_exit();
- return 1;
-}
-
-/* Weak implementations for optional arch specific functions */
-void __weak arch_cpu_idle_prepare(void) { }
-void __weak arch_cpu_idle_enter(void) { }
-void __weak arch_cpu_idle_exit(void) { }
-void __weak arch_cpu_idle_dead(void) { }
-void __weak arch_cpu_idle(void)
-{
- cpu_idle_force_poll = 1;
- local_irq_enable();
-}
-
-/*
- * Generic idle loop implementation
- */
-static void cpu_idle_loop(void)
-{
- while (1) {
- tick_nohz_idle_enter();
-
- while (!need_resched()) {
- check_pgt_cache();
- rmb();
-
- if (cpu_is_offline(smp_processor_id()))
- arch_cpu_idle_dead();
-
- local_irq_disable();
- arch_cpu_idle_enter();
-
- /*
- * In poll mode we reenable interrupts and spin.
- *
- * Also if we detected in the wakeup from idle
- * path that the tick broadcast device expired
- * for us, we don't want to go deep idle as we
- * know that the IPI is going to arrive right
- * away
- */
- if (cpu_idle_force_poll || tick_check_broadcast_expired()) {
- cpu_idle_poll();
- } else {
- if (!current_clr_polling_and_test()) {
- stop_critical_timings();
- rcu_idle_enter();
- if (cpuidle_idle_call())
- arch_cpu_idle();
- if (WARN_ON_ONCE(irqs_disabled()))
- local_irq_enable();
- rcu_idle_exit();
- start_critical_timings();
- } else {
- local_irq_enable();
- }
- __current_set_polling();
- }
- arch_cpu_idle_exit();
- /*
- * We need to test and propagate the TIF_NEED_RESCHED
- * bit here because we might not have send the
- * reschedule IPI to idle tasks.
- */
- if (tif_need_resched())
- set_preempt_need_resched();
- }
- tick_nohz_idle_exit();
- schedule_preempt_disabled();
- }
-}
-
-void cpu_startup_entry(enum cpuhp_state state)
-{
- /*
- * This #ifdef needs to die, but it's too late in the cycle to
- * make this generic (arm and sh have never invoked the canary
- * init for the non boot cpus!). Will be fixed in 3.11
- */
-#ifdef CONFIG_X86
- /*
- * If we're the non-boot CPU, nothing set the stack canary up
- * for us. The boot CPU already has it initialized but no harm
- * in doing it again. This is a good place for updating it, as
- * we wont ever return from this function (so the invalid
- * canaries already on the stack wont ever trigger).
- */
- boot_init_stack_canary();
-#endif
- __current_set_polling();
- arch_cpu_idle_prepare();
- cpu_idle_loop();
-}
diff --git a/kernel/sched/Makefile b/kernel/sched/Makefile
index 7b621409cf..ac3e0ea68f 100644
--- a/kernel/sched/Makefile
+++ b/kernel/sched/Makefile
@@ -11,7 +11,7 @@ ifneq ($(CONFIG_SCHED_OMIT_FRAME_POINTER),y)
CFLAGS_core.o := $(PROFILING) -fno-omit-frame-pointer
endif
-obj-y += core.o proc.o clock.o cputime.o idle_task.o fair.o rt.o stop_task.o
+obj-y += core.o proc.o clock.o cputime.o idle_task.o idle.o fair.o rt.o stop_task.o
obj-y += wait.o completion.o
obj-$(CONFIG_SMP) += cpupri.o
obj-$(CONFIG_SCHED_AUTOGROUP) += auto_group.o
diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c
new file mode 100644
index 0000000000..14ca43430a
--- /dev/null
+++ b/kernel/sched/idle.c
@@ -0,0 +1,144 @@
+/*
+ * Generic entry point for the idle threads
+ */
+#include <linux/sched.h>
+#include <linux/cpu.h>
+#include <linux/cpuidle.h>
+#include <linux/tick.h>
+#include <linux/mm.h>
+#include <linux/stackprotector.h>
+
+#include <asm/tlb.h>
+
+#include <trace/events/power.h>
+
+static int __read_mostly cpu_idle_force_poll;
+
+void cpu_idle_poll_ctrl(bool enable)
+{
+ if (enable) {
+ cpu_idle_force_poll++;
+ } else {
+ cpu_idle_force_poll--;
+ WARN_ON_ONCE(cpu_idle_force_poll < 0);
+ }
+}
+
+#ifdef CONFIG_GENERIC_IDLE_POLL_SETUP
+static int __init cpu_idle_poll_setup(char *__unused)
+{
+ cpu_idle_force_poll = 1;
+ return 1;
+}
+__setup("nohlt", cpu_idle_poll_setup);
+
+static int __init cpu_idle_nopoll_setup(char *__unused)
+{
+ cpu_idle_force_poll = 0;
+ return 1;
+}
+__setup("hlt", cpu_idle_nopoll_setup);
+#endif
+
+static inline int cpu_idle_poll(void)
+{
+ rcu_idle_enter();
+ trace_cpu_idle_rcuidle(0, smp_processor_id());
+ local_irq_enable();
+ while (!tif_need_resched())
+ cpu_relax();
+ trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
+ rcu_idle_exit();
+ return 1;
+}
+
+/* Weak implementations for optional arch specific functions */
+void __weak arch_cpu_idle_prepare(void) { }
+void __weak arch_cpu_idle_enter(void) { }
+void __weak arch_cpu_idle_exit(void) { }
+void __weak arch_cpu_idle_dead(void) { }
+void __weak arch_cpu_idle(void)
+{
+ cpu_idle_force_poll = 1;
+ local_irq_enable();
+}
+
+/*
+ * Generic idle loop implementation
+ */
+static void cpu_idle_loop(void)
+{
+ while (1) {
+ tick_nohz_idle_enter();
+
+ while (!need_resched()) {
+ check_pgt_cache();
+ rmb();
+
+ if (cpu_is_offline(smp_processor_id()))
+ arch_cpu_idle_dead();
+
+ local_irq_disable();
+ arch_cpu_idle_enter();
+
+ /*
+ * In poll mode we reenable interrupts and spin.
+ *
+ * Also if we detected in the wakeup from idle
+ * path that the tick broadcast device expired
+ * for us, we don't want to go deep idle as we
+ * know that the IPI is going to arrive right
+ * away
+ */
+ if (cpu_idle_force_poll || tick_check_broadcast_expired()) {
+ cpu_idle_poll();
+ } else {
+ if (!current_clr_polling_and_test()) {
+ stop_critical_timings();
+ rcu_idle_enter();
+ if (cpuidle_idle_call())
+ arch_cpu_idle();
+ if (WARN_ON_ONCE(irqs_disabled()))
+ local_irq_enable();
+ rcu_idle_exit();
+ start_critical_timings();
+ } else {
+ local_irq_enable();
+ }
+ __current_set_polling();
+ }
+ arch_cpu_idle_exit();
+ /*
+ * We need to test and propagate the TIF_NEED_RESCHED
+ * bit here because we might not have send the
+ * reschedule IPI to idle tasks.
+ */
+ if (tif_need_resched())
+ set_preempt_need_resched();
+ }
+ tick_nohz_idle_exit();
+ schedule_preempt_disabled();
+ }
+}
+
+void cpu_startup_entry(enum cpuhp_state state)
+{
+ /*
+ * This #ifdef needs to die, but it's too late in the cycle to
+ * make this generic (arm and sh have never invoked the canary
+ * init for the non boot cpus!). Will be fixed in 3.11
+ */
+#ifdef CONFIG_X86
+ /*
+ * If we're the non-boot CPU, nothing set the stack canary up
+ * for us. The boot CPU already has it initialized but no harm
+ * in doing it again. This is a good place for updating it, as
+ * we wont ever return from this function (so the invalid
+ * canaries already on the stack wont ever trigger).
+ */
+ boot_init_stack_canary();
+#endif
+ __current_set_polling();
+ arch_cpu_idle_prepare();
+ cpu_idle_loop();
+}
--
1.8.4.108.g55ea5f6
^ permalink raw reply related
* [PATCH v2 1/6] idle: move the cpuidle entry point to the generic idle loop
From: Nicolas Pitre @ 2014-01-30 16:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52EA5720.8010000@linaro.org>
On Thu, 30 Jan 2014, Daniel Lezcano wrote:
> On 01/30/2014 06:28 AM, Nicolas Pitre wrote:
> > On Thu, 30 Jan 2014, Preeti U Murthy wrote:
> >
> > > Hi Nicolas,
> > >
> > > On 01/30/2014 02:01 AM, Nicolas Pitre wrote:
> > > > On Wed, 29 Jan 2014, Nicolas Pitre wrote:
> > > >
> > > > > In order to integrate cpuidle with the scheduler, we must have a
> > > > > better
> > > > > proximity in the core code with what cpuidle is doing and not delegate
> > > > > such interaction to arch code.
> > > > >
> > > > > Architectures implementing arch_cpu_idle() should simply enter
> > > > > a cheap idle mode in the absence of a proper cpuidle driver.
> > > > >
> > > > > Signed-off-by: Nicolas Pitre <nico@linaro.org>
> > > > > Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> > > >
> > > > As mentioned in my reply to Olof's comment on patch #5/6, here's a new
> > > > version of this patch adding the safety local_irq_enable() to the core
> > > > code.
> > > >
> > > > ----- >8
> > > >
> > > > From: Nicolas Pitre <nicolas.pitre@linaro.org>
> > > > Subject: idle: move the cpuidle entry point to the generic idle loop
> > > >
> > > > In order to integrate cpuidle with the scheduler, we must have a better
> > > > proximity in the core code with what cpuidle is doing and not delegate
> > > > such interaction to arch code.
> > > >
> > > > Architectures implementing arch_cpu_idle() should simply enter
> > > > a cheap idle mode in the absence of a proper cpuidle driver.
> > > >
> > > > In both cases i.e. whether it is a cpuidle driver or the default
> > > > arch_cpu_idle(), the calling convention expects IRQs to be disabled
> > > > on entry and enabled on exit. There is a warning in place already but
> > > > let's add a forced IRQ enable here as well. This will allow for
> > > > removing the forced IRQ enable some implementations do locally and
> > >
> > > Why would this patch allow for removing the forced IRQ enable that are
> > > being done on some archs in arch_cpu_idle()? Isn't this patch expecting
> > > the default arch_cpu_idle() to have re-enabled the interrupts after
> > > exiting from the default idle state? Its supposed to only catch faulty
> > > cpuidle drivers that haven't enabled IRQs on exit from idle state but
> > > are expected to have done so, isn't it?
> >
> > Exact. However x86 currently does this:
> >
> > if (cpuidle_idle_call())
> > x86_idle();
> > else
> > local_irq_enable();
> >
> > So whenever cpuidle_idle_call() is successful then IRQs are
> > unconditionally enabled whether or not the underlying cpuidle driver has
> > properly done it or not. And the reason is that some of the x86 cpuidle
> > do fail to enable IRQs before returning.
> >
> > So the idea is to get rid of this unconditional IRQ enabling and let the
> > core issue a warning instead (as well as enabling IRQs to allow the
> > system to run).
>
> But what I don't get with your comment is the local_irq_enable is done from
> the cpuidle common framework in 'cpuidle_enter_state' it is not done from the
> arch specific backend cpuidle driver.
Oh well... This certainly means we'll have to clean this mess as some
drivers do it on their own while some others don't. Some drivers also
loop on !need_resched() while some others simply return on the first
interrupt.
> So the code above could be:
>
> if (cpuidle_idle_call())
> x86_idle();
>
> without the else section, this local_irq_enable is pointless. Or may be I
> missed something ?
A later patch removes it anyway. But if it is really necessary to
enable interrupts then the core will do it but with a warning now.
Nicolas
^ permalink raw reply
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