* [PATCH 0/6] iommu/arm-smmu: Misc modifications to support SMMUs on Calxeda ECX-2000
From: Andreas Herrmann @ 2014-01-30 18:18 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This is v5 of my arm-smmu changes (to support SMMUs on Calxeda ECX-2000).
Patches are based on v3.13.
Changes to previous version are
- use iommu_group notifier instead of bus notifier
- remove superfluous call to arm_smmu_add_device in
notifier function
- free bitmap that's used for checking of duplicate stream IDs
- hopefully addressed all issues for the "SMR allocator" patch
(see http://marc.info/?l=linux-arm-kernel&m=139040446813960)
- reorder patches to put the notifier change last (in case there are
still objections to this the rest could be merged I think)
I omitted the patches that are device-tree related (of, dts,
documentation) or ARM dma-mapping.c related. I'll work on an update of
the dma-mapping change (to automatically increase the mapping size)
separately.
Changelog:
v4:
http://marc.info/?l=linux-arm-kernel&m=138988209913055
v3:
http://marc.info/?l=linux-arm-kernel&m=138212725606348
v2:
http://marc.info/?l=linux-arm-kernel&m=138135834704855
v1:
http://marc.info/?l=linux-arm-kernel&m=138122450023564
Regards,
Andreas
^ permalink raw reply
* [PATCH 1/6] iommu/arm-smmu: Introduce driver option handling
From: Andreas Herrmann @ 2014-01-30 18:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391105889-32718-1-git-send-email-andreas.herrmann@calxeda.com>
Introduce handling of driver options. Options are set based on DT
information when probing an SMMU device. The first option introduced
is "arm,smmu-isolate-devices". (It will be used in the iommu_group
notifier block.)
Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
---
drivers/iommu/arm-smmu.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 879da20..7111461 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -348,6 +348,9 @@ struct arm_smmu_device {
#define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
#define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
u32 features;
+
+#define ARM_SMMU_OPT_ISOLATE_DEVICES (1 << 0)
+ u32 options;
int version;
u32 num_context_banks;
@@ -398,6 +401,29 @@ struct arm_smmu_domain {
static DEFINE_SPINLOCK(arm_smmu_devices_lock);
static LIST_HEAD(arm_smmu_devices);
+struct arm_smmu_option_prop {
+ u32 opt;
+ const char *prop;
+};
+
+static struct arm_smmu_option_prop arm_smmu_options [] = {
+ { ARM_SMMU_OPT_ISOLATE_DEVICES, "arm,smmu-isolate-devices" },
+ { 0, NULL},
+};
+
+static void parse_driver_options(struct arm_smmu_device *smmu)
+{
+ int i = 0;
+ do {
+ if (of_property_read_bool(smmu->dev->of_node,
+ arm_smmu_options[i].prop)) {
+ smmu->options |= arm_smmu_options[i].opt;
+ dev_notice(smmu->dev, "option %s\n",
+ arm_smmu_options[i].prop);
+ }
+ } while (arm_smmu_options[++i].opt);
+}
+
static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
struct device_node *dev_node)
{
@@ -1864,6 +1890,8 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
if (err)
goto out_put_parent;
+ parse_driver_options(smmu);
+
if (smmu->version > 1 &&
smmu->num_context_banks != smmu->num_context_irqs) {
dev_err(dev,
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/6] iommu/arm-smmu: Support buggy implementation where all config accesses are secure
From: Andreas Herrmann @ 2014-01-30 18:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391105889-32718-1-git-send-email-andreas.herrmann@calxeda.com>
In such a case we have to use secure aliases of some non-secure
registers.
This handling is switched on by DT property
"calxeda,smmu-secure-config-access" for an SMMU node.
Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
---
drivers/iommu/arm-smmu.c | 31 +++++++++++++++++++++----------
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 7111461..0438ec1 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -60,6 +60,15 @@
#define ARM_SMMU_GR0(smmu) ((smmu)->base)
#define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
+/*
+ * SMMU global address space with conditional offset to access secure aliases of
+ * non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448, nsGFSYNR0: 0x450)
+ */
+#define ARM_SMMU_GR0_NS(smmu) \
+ ((smmu)->base + \
+ ((smmu->options & ARM_SMMU_OPT_SECURE_CONFIG_ACCESS) \
+ ? 0x400 : 0))
+
/* Page table bits */
#define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0)
#define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
@@ -350,6 +359,7 @@ struct arm_smmu_device {
u32 features;
#define ARM_SMMU_OPT_ISOLATE_DEVICES (1 << 0)
+#define ARM_SMMU_OPT_SECURE_CONFIG_ACCESS (1 << 1)
u32 options;
int version;
@@ -408,6 +418,7 @@ struct arm_smmu_option_prop {
static struct arm_smmu_option_prop arm_smmu_options [] = {
{ ARM_SMMU_OPT_ISOLATE_DEVICES, "arm,smmu-isolate-devices" },
+ { ARM_SMMU_OPT_SECURE_CONFIG_ACCESS, "calxeda,smmu-secure-config-access" },
{ 0, NULL},
};
@@ -637,16 +648,16 @@ static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
{
u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
struct arm_smmu_device *smmu = dev;
- void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
+ void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
- if (!gfsr)
- return IRQ_NONE;
-
gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
+ if (!gfsr)
+ return IRQ_NONE;
+
dev_err_ratelimited(smmu->dev,
"Unexpected global fault, this could be serious\n");
dev_err_ratelimited(smmu->dev,
@@ -1601,9 +1612,9 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
int i = 0;
u32 reg;
- /* Clear Global FSR */
- reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
- writel(reg, gr0_base + ARM_SMMU_GR0_sGFSR);
+ /* clear global FSR */
+ reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
+ writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
/* Mark all SMRn as invalid and all S2CRn as bypass */
for (i = 0; i < smmu->num_mapping_groups; ++i) {
@@ -1623,7 +1634,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
- reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0);
+ reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
/* Enable fault reporting */
reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
@@ -1642,7 +1653,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
/* Push the button */
arm_smmu_tlb_sync(smmu);
- writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sCR0);
+ writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
}
static int arm_smmu_id_size_to_bits(int size)
@@ -1976,7 +1987,7 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
free_irq(smmu->irqs[i], smmu);
/* Turn the thing off */
- writel_relaxed(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);
+ writel(sCR0_CLIENTPD,ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
return 0;
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/6] iommu/arm-smmu: Check for duplicate stream IDs when registering master devices
From: Andreas Herrmann @ 2014-01-30 18:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391105889-32718-1-git-send-email-andreas.herrmann@calxeda.com>
If DT information lists one stream ID twice for the master devices of
an SMMU this can cause a multi match when stream ID matching is used.
For stream ID indexing this might trigger an overwrite of an S2CR that
is already in use.
So better check for duplicates when DT information is parsed.
Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
---
drivers/iommu/arm-smmu.c | 31 ++++++++++++++++++++++++++-----
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 0438ec1..4a32fde 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -50,6 +50,9 @@
/* Maximum number of stream IDs assigned to a single device */
#define MAX_MASTER_STREAMIDS 8
+/* Maximum stream ID */
+#define ARM_SMMU_MAX_STREAMID (SZ_64K - 1)
+
/* Maximum number of context banks per SMMU */
#define ARM_SMMU_MAX_CBS 128
@@ -482,9 +485,10 @@ static int insert_smmu_master(struct arm_smmu_device *smmu,
static int register_smmu_master(struct arm_smmu_device *smmu,
struct device *dev,
- struct of_phandle_args *masterspec)
+ struct of_phandle_args *masterspec,
+ unsigned long *smmu_sids)
{
- int i;
+ int i, sid;
struct arm_smmu_master *master;
master = find_smmu_master(smmu, masterspec->np);
@@ -509,8 +513,14 @@ static int register_smmu_master(struct arm_smmu_device *smmu,
master->of_node = masterspec->np;
master->num_streamids = masterspec->args_count;
- for (i = 0; i < master->num_streamids; ++i)
- master->streamids[i] = masterspec->args[i];
+ for (i = 0; i < master->num_streamids; ++i) {
+ sid = masterspec->args[i];
+ if (test_and_set_bit(sid, smmu_sids)) {
+ dev_err(dev, "duplicate stream ID (%d)\n", sid);
+ return -EEXIST;
+ }
+ master->streamids[i] = sid;
+ }
return insert_smmu_master(smmu, master);
}
@@ -1828,6 +1838,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct rb_node *node;
struct of_phandle_args masterspec;
+ unsigned long *smmu_sids;
int num_irqs, i, err;
smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
@@ -1878,20 +1889,30 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
smmu->irqs[i] = irq;
}
+ smmu_sids = kzalloc(BITS_TO_LONGS(ARM_SMMU_MAX_STREAMID) *
+ sizeof(long), GFP_KERNEL);
+ if (!smmu_sids) {
+ dev_err(dev,
+ "failed to allocate bitmap for stream ID tracking\n");
+ return -ENOMEM;
+ }
+
i = 0;
smmu->masters = RB_ROOT;
while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
"#stream-id-cells", i,
&masterspec)) {
- err = register_smmu_master(smmu, dev, &masterspec);
+ err = register_smmu_master(smmu, dev, &masterspec, smmu_sids);
if (err) {
dev_err(dev, "failed to add master %s\n",
masterspec.np->name);
+ kfree(smmu_sids);
goto out_put_masters;
}
i++;
}
+ kfree(smmu_sids);
dev_notice(dev, "registered %d master devices\n", i);
if ((dev_node = of_parse_phandle(dev->of_node, "smmu-parent", 0)))
--
1.7.9.5
^ permalink raw reply related
* [PATCH 4/6] iommu/arm-smmu: Introduce automatic stream-id-masking
From: Andreas Herrmann @ 2014-01-30 18:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391105889-32718-1-git-send-email-andreas.herrmann@calxeda.com>
Try to determine mask/id values that match several stream IDs of a
master device when doing Stream ID matching. Thus the number of used
SMR groups that are required to map all stream IDs of a master device
to a context should be less than the number of SMR groups used so far
(currently one SMR group is used for one stream ID).
Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
---
drivers/iommu/arm-smmu.c | 172 ++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 157 insertions(+), 15 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 4a32fde..31d9458 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -42,6 +42,7 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
+#include <linux/bitops.h>
#include <linux/amba/bus.h>
@@ -336,8 +337,9 @@ struct arm_smmu_master {
* SMMU chain.
*/
struct rb_node node;
- int num_streamids;
+ u32 num_streamids;
u16 streamids[MAX_MASTER_STREAMIDS];
+ int num_s2crs;
/*
* We only need to allocate these on the root SMMU, as we
@@ -382,6 +384,9 @@ struct arm_smmu_device {
u32 num_context_irqs;
unsigned int *irqs;
+ u32 smr_mask_mask;
+ u32 smr_id_mask;
+
struct list_head list;
struct rb_root masters;
};
@@ -1033,10 +1038,140 @@ static void arm_smmu_domain_destroy(struct iommu_domain *domain)
kfree(smmu_domain);
}
+/*
+ * For a given set N of 2**order different stream IDs (no duplicates
+ * please!) we determine values mask and id such that
+ *
+ * (1) (x & mask) == id
+ *
+ * for each stream ID x from the given set N.
+ *
+ * If the number of bits that are set in mask equals n, then there
+ * exist 2**n different values y for which
+ *
+ * (2) (y & mask) == id
+ *
+ * Thus if n equals order we know that for the calculated mask and id
+ * values there are exactly 2**order == 2**n stream IDs for which (1)
+ * is true. And we finally can use mask and id to configure an SMR to
+ * match all stream IDs in the set N.
+ */
+static int determine_smr_mask(struct arm_smmu_device *smmu,
+ struct arm_smmu_master *master,
+ struct arm_smmu_smr *smr, int start, int order)
+{
+ u16 i, zero_bits_mask, one_bits_mask, const_mask;
+ int nr;
+
+ nr = 1 << order;
+
+ if (nr == 1) {
+ /* no mask, use streamid to match and be done with it */
+ smr->mask = 0;
+ smr->id = master->streamids[start];
+ return 0;
+ }
+
+ zero_bits_mask = 0;
+ one_bits_mask = 0xffff;
+ for (i = start; i < start + nr; i++) {
+ zero_bits_mask |= master->streamids[i]; /* const 0 bits */
+ one_bits_mask &= master->streamids[i]; /* const 1 bits */
+ }
+ zero_bits_mask = ~zero_bits_mask;
+
+ /* bits having constant values (either 0 or 1) */
+ const_mask = zero_bits_mask | one_bits_mask;
+
+ i = hweight16(~const_mask);
+ if (i == order) {
+ /*
+ * We have found a mask/id pair that matches exactly
+ * nr = 2**order stream IDs which we used for its
+ * calculation.
+ */
+ smr->mask = ~const_mask;
+ smr->id = one_bits_mask;
+ } else {
+ /*
+ * No usable mask/id pair for this set of streamids.
+ * If i > order then mask/id would match more than nr
+ * streamids.
+ * If i < order then mask/id would match less than nr
+ * streamids. (In this case we potentially have used
+ * some duplicate streamids for the calculation.)
+ */
+ return 1;
+ }
+
+ if (((smr->mask & smmu->smr_mask_mask) != smr->mask) ||
+ ((smr->id & smmu->smr_id_mask) != smr->id))
+ /* insufficient number of mask/id bits */
+ return 1;
+
+ return 0;
+}
+
+static int determine_smr_mapping(struct arm_smmu_device *smmu,
+ struct arm_smmu_master *master,
+ struct arm_smmu_smr *smrs, int max_smrs)
+{
+ int nr_sid, nr, i, bit, start;
+
+ /*
+ * This function is called only once -- when a master is added
+ * to a domain. If master->num_s2crs != 0 then this master
+ * was already added to a domain.
+ */
+ if (master->num_s2crs)
+ return -EINVAL;
+
+ start = nr = 0;
+ nr_sid = master->num_streamids;
+ do {
+ /*
+ * largest power-of-2 number of streamids for which to
+ * determine a usable mask/id pair for stream matching
+ */
+ bit = __fls(nr_sid);
+ if (bit < 0)
+ return 0;
+
+ /*
+ * iterate over power-of-2 numbers to determine
+ * largest possible mask/id pair for stream matching
+ * of next 2**i streamids
+ */
+ for (i = bit; i >= 0; i--) {
+ if (!determine_smr_mask(smmu, master,
+ &smrs[master->num_s2crs],
+ start, i))
+ break;
+ }
+
+ if (i < 0)
+ goto out;
+
+ nr = 1 << i;
+ nr_sid -= nr;
+ start += nr;
+ master->num_s2crs++;
+ } while (master->num_s2crs <= max_smrs);
+
+out:
+ if (nr_sid) {
+ /* not enough mapping groups available */
+ master->num_s2crs = 0;
+ return -ENOSPC;
+ }
+
+ return 0;
+}
+
static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
struct arm_smmu_master *master)
{
- int i;
+ int i, max_smrs, ret;
struct arm_smmu_smr *smrs;
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
@@ -1046,31 +1181,31 @@ static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
if (master->smrs)
return -EEXIST;
- smrs = kmalloc(sizeof(*smrs) * master->num_streamids, GFP_KERNEL);
+ max_smrs = min(smmu->num_mapping_groups, master->num_streamids);
+ smrs = kmalloc(sizeof(*smrs) * max_smrs, GFP_KERNEL);
if (!smrs) {
dev_err(smmu->dev, "failed to allocate %d SMRs for master %s\n",
- master->num_streamids, master->of_node->name);
+ max_smrs, master->of_node->name);
return -ENOMEM;
}
+ ret = determine_smr_mapping(smmu, master, smrs, max_smrs);
+ if (ret)
+ goto err_free_smrs;
+
/* Allocate the SMRs on the root SMMU */
- for (i = 0; i < master->num_streamids; ++i) {
+ for (i = 0; i < master->num_s2crs; ++i) {
int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
smmu->num_mapping_groups);
if (IS_ERR_VALUE(idx)) {
dev_err(smmu->dev, "failed to allocate free SMR\n");
- goto err_free_smrs;
+ goto err_free_bitmap;
}
-
- smrs[i] = (struct arm_smmu_smr) {
- .idx = idx,
- .mask = 0, /* We don't currently share SMRs */
- .id = master->streamids[i],
- };
+ smrs[i].idx = idx;
}
/* It worked! Now, poke the actual hardware */
- for (i = 0; i < master->num_streamids; ++i) {
+ for (i = 0; i < master->num_s2crs; ++i) {
u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
smrs[i].mask << SMR_MASK_SHIFT;
writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
@@ -1079,9 +1214,11 @@ static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
master->smrs = smrs;
return 0;
-err_free_smrs:
+err_free_bitmap:
while (--i >= 0)
__arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
+ master->num_s2crs = 0;
+err_free_smrs:
kfree(smrs);
return -ENOSPC;
}
@@ -1144,11 +1281,14 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
}
/* Now we're at the root, time to point at our context bank */
- for (i = 0; i < master->num_streamids; ++i) {
+ if (!master->num_s2crs)
+ master->num_s2crs = master->num_streamids;
+ for (i = 0; i < master->num_s2crs; ++i) {
u32 idx, s2cr;
idx = master->smrs ? master->smrs[i].idx : master->streamids[i];
s2cr = (S2CR_TYPE_TRANS << S2CR_TYPE_SHIFT) |
(smmu_domain->root_cfg.cbndx << S2CR_CBNDX_SHIFT);
+ dev_dbg(smmu->dev, "S2CR%d: 0x%x\n", idx, s2cr);
writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
}
@@ -1758,6 +1898,8 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
mask, sid);
return -ENODEV;
}
+ smmu->smr_mask_mask = mask;
+ smmu->smr_id_mask = sid;
dev_notice(smmu->dev,
"\tstream matching with %u register groups, mask 0x%x",
--
1.7.9.5
^ permalink raw reply related
* [PATCH 5/6] iommu/arm-smmu: Set MAX_MASTER_STREAMIDS to MAX_PHANDLE_ARGS
From: Andreas Herrmann @ 2014-01-30 18:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391105889-32718-1-git-send-email-andreas.herrmann@calxeda.com>
The DT parsing code that determines stream IDs uses
of_parse_phandle_with_args and thus MAX_MASTER_STREAMIDS
is always bound by MAX_PHANDLE_ARGS.
Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
---
drivers/iommu/arm-smmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 31d9458..d1f166f 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -49,7 +49,7 @@
#include <asm/pgalloc.h>
/* Maximum number of stream IDs assigned to a single device */
-#define MAX_MASTER_STREAMIDS 8
+#define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
/* Maximum stream ID */
#define ARM_SMMU_MAX_STREAMID (SZ_64K - 1)
--
1.7.9.5
^ permalink raw reply related
* [PATCH 6/6] iommu/arm-smmu: Introduce iommu_group notifier block
From: Andreas Herrmann @ 2014-01-30 18:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391105889-32718-1-git-send-email-andreas.herrmann@calxeda.com>
At the moment just handle IOMMU_GROUP_NOTIFY_BIND_DRIVER to
conditionally isolate all master devices for an SMMU.
Depending on DT information each device is put into its own protection
domain (if possible). For configuration with one or just a few
masters per SMMU that is easy to achieve.
In case of many devices per SMMU (e.g. MMU-500 with it's distributed
translation support) isolation of each device might not be possible --
depending on number of available SMR groups and/or context banks.
Default is that device isolation is contolled per SMMU with SMMU node
property "arm,smmu-isolate-devices" in a DT. If this property is set
for an SMMU node, device isolation is performed.
W/o device isolation the driver detects SMMUs but no translation is
configured (transactions just bypass translation process).
Note that for device isolation dma_base and size are fixed as 0 and
SZ_128M at the moment. Additional patches will address this
restriction and allow automatic growth of mapping size.
Cc: Varun Sethi <Varun.Sethi@freescale.com>
Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
---
drivers/iommu/arm-smmu.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index d1f166f..bee88c8 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -47,6 +47,7 @@
#include <linux/amba/bus.h>
#include <asm/pgalloc.h>
+#include <asm/dma-iommu.h>
/* Maximum number of stream IDs assigned to a single device */
#define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
@@ -1677,6 +1678,47 @@ static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
return !!(cap & caps);
}
+static int arm_smmu_group_notifier(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct device *dev = data;
+ struct dma_iommu_mapping *mapping;
+ struct arm_smmu_device *smmu;
+ int ret;
+
+ switch (action) {
+ case IOMMU_GROUP_NOTIFY_BIND_DRIVER:
+
+ smmu = dev->archdata.iommu;
+ if (!smmu || !(smmu->options & ARM_SMMU_OPT_ISOLATE_DEVICES))
+ break;
+
+ mapping = arm_iommu_create_mapping(&platform_bus_type,
+ 0, SZ_128M, 0);
+ if (IS_ERR(mapping)) {
+ ret = PTR_ERR(mapping);
+ dev_info(dev, "arm_iommu_create_mapping failed\n");
+ break;
+ }
+
+ ret = arm_iommu_attach_device(dev, mapping);
+ if (ret < 0) {
+ dev_info(dev, "arm_iommu_attach_device failed\n");
+ arm_iommu_release_mapping(mapping);
+ }
+
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static struct notifier_block group_nb = {
+ .notifier_call = arm_smmu_group_notifier,
+};
+
static int arm_smmu_add_device(struct device *dev)
{
struct arm_smmu_device *child, *parent, *smmu;
@@ -1726,6 +1768,8 @@ static int arm_smmu_add_device(struct device *dev)
return PTR_ERR(group);
}
+ iommu_group_register_notifier(group, &group_nb);
+
ret = iommu_group_add_device(group, dev);
iommu_group_put(group);
dev->archdata.iommu = smmu;
--
1.7.9.5
^ permalink raw reply related
* [linux-pm] ARM hibernation / suspend-to-disk
From: Sebastian Capella @ 2014-01-30 18:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140130180639.GC16503@amd.pavel.ucw.cz>
Quoting Pavel Machek (2014-01-30 10:06:39)
> Yeah, but those are driver problems, right? 1400 suspends is very
> nice, and it shows that the core is working. That should be enough for
> merge; driver problems can be solved later.
Hi Pavel,
I spoke to Russ, and he's ok with me sending this on his behalf.
Let me prepare it for review and I'll send it out.
Thanks,
Sebastian
^ permalink raw reply
* [PATCH v2 00/21] pinctrl: mvebu: restructure and remove hardcoded addresses from Dove pinctrl
From: Andrew Lunn @ 2014-01-30 18:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390869573-27624-1-git-send-email-sebastian.hesselbarth@gmail.com>
On Tue, Jan 28, 2014 at 01:39:12AM +0100, Sebastian Hesselbarth wrote:
> This patch set is one required step for Dove to hop into mach-mvebu.
> Until now, pinctrl-dove was hardcoding some registers that do not
> directly belong to MPP core registers. This is not compatible with
> what we want for mach-mvebu.
Hi Sebastian
I think there might be something wrong here....
/debug/pinctrl/f1010000.pinctrl/pinconf-groups used to contain:
Pin config settings per pin group
Format: group (name): configs
0 (mpp0):current: spi(cs), available = [ gpio(io) nand(io2) ]
1 (mpp1):current: spi(mosi), available = [ gpo(o) nand(io3) ]
2 (mpp2):current: spi(sck), available = [ gpo(o) nand(io4) ]
3 (mpp3):current: spi(miso), available = [ gpo(o) nand(io5) ]
4 (mpp4):current: sata1(act), available = [ gpio(io) nand(io6) uart0(rxd) lcd(hsync) ]
5 (mpp5):current: sata0(act), available = [ gpo(o) nand(io7) uart0(txd) lcd(vsync) ]
6 (mpp6):current: sysrst(out), available = [ spi(mosi) ]
...
It now has:
Pin config settings per pin group
Format: group (name): configs
0 (mpp0):current: gpio(io), available = [ nand(io2) spi(cs) ]
1 (mpp1):current: gpo(o), available = [ nand(io3) spi(mosi) ]
2 (mpp2):current: gpo(o), available = [ nand(io4) spi(sck) ]
3 (mpp3):current: gpo(o), available = [ nand(io5) spi(miso) ]
4 (mpp4):current: gpio(io), available = [ nand(io6) uart0(rxd) sata1(act) lcd(hsync) ]
5 (mpp5):current: gpo(o), available = [ nand(io7) uart0(txd) sata0(act) lcd(vsync) ]
6 (mpp6):current: UNKNOWN, available = [ sysrst(out) spi(mosi) ]
The device i'm testing on does use spi and sata, so i would say the
old contents was correct and the new is wrong.
Andrew
^ permalink raw reply
* [PATCH 1/4] ARM: STi: add stid127 soc support
From: Arnd Bergmann @ 2014-01-30 18:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391093744-19905-2-git-send-email-patrice.chotard@st.com>
On Thursday 30 January 2014, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <alexandre.torgue@st.com>
>
> This patch adds support to STiD127 SoC.
> The main adaptation is the L2 cache way size compare to STiH41x SoCs.
>
> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
> arch/arm/mach-sti/board-dt.c | 6 ++++++
> 1 file changed, 6 insertions(+)
Wouldn't it be better to read this value from the l2 cache
controller node? I'd assume there might be more SoCs that
will need a similar change, so it's better to come up with
a solution that doesn't involve changing the kernel every
time.
Arnd
^ permalink raw reply
* [PATCH 0/4] Split mach-msm into legacy and mach-qcom (multiplatform)
From: Kumar Gala @ 2014-01-30 18:36 UTC (permalink / raw)
To: linux-arm-kernel
This is the starts of splitting the Qualcomm MSM platform into legacy support
that we will not try and convert to multiplatform and multiplatform support.
These patches are based on the 'CPU enable method based SMP' patches.
I wanted to get these out for review, will add a few more patches for defconfig
updates/additions, as well as some additional driver being enabled for ARCH_QCOM.
- k
arch/arm/mach-msm/board-dt.c | 27 --
arch/arm/mach-msm/hotplug.c | 51 ----
arch/arm/mach-msm/platsmp.c | 371 ------------------------------------
arch/arm/mach-msm/scm-boot.c | 39 ---
arch/arm/mach-msm/scm-boot.h | 24 --
arch/arm/mach-msm/scm.c | 299 -----------------------------
arch/arm/mach-msm/scm.h | 25 --
arch/arm/mach-msm/timer.c | 333 --------------------------------
b/MAINTAINERS | 7
b/arch/arm/Kconfig | 7
b/arch/arm/Makefile | 1
b/arch/arm/boot/dts/Makefile | 6
b/arch/arm/mach-msm/Kconfig | 54 -----
b/arch/arm/mach-msm/Makefile | 8
b/arch/arm/mach-qcom/Kconfig | 34 +++
b/arch/arm/mach-qcom/Makefile | 5
b/arch/arm/mach-qcom/board.c | 26 ++
b/arch/arm/mach-qcom/scm-boot.c | 39 +++
b/arch/arm/mach-qcom/scm-boot.h | 24 ++
b/arch/arm/mach-qcom/scm.c | 299 +++++++++++++++++++++++++++++
b/arch/arm/mach-qcom/scm.h | 25 ++
b/arch/arm/mach-qcom/smp.c | 380 +++++++++++++++++++++++++++++++++++++
b/drivers/clocksource/Kconfig | 4
b/drivers/clocksource/Makefile | 1
b/drivers/clocksource/qcom-timer.c | 330 ++++++++++++++++++++++++++++++++
b/drivers/tty/serial/Kconfig | 2
26 files changed, 1188 insertions(+), 1233 deletions(-)
^ permalink raw reply
* [PATCH 1/4] clocksource: qcom: Move clocksource code out of mach-msm
From: Kumar Gala @ 2014-01-30 18:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391107002-21470-1-git-send-email-galak@codeaurora.org>
We intent to share the clocksource code for MSM platforms between legacy
and multiplatform supported qcom SoCs.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
---
arch/arm/mach-msm/Kconfig | 13 +++++--------
arch/arm/mach-msm/Makefile | 1 -
drivers/clocksource/Kconfig | 4 ++++
drivers/clocksource/Makefile | 1 +
.../mach-msm/timer.c => drivers/clocksource/qcom-timer.c | 6 +-----
5 files changed, 11 insertions(+), 14 deletions(-)
rename arch/arm/mach-msm/timer.c => drivers/clocksource/qcom-timer.c (98%)
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 9625cf3..3c4eca7 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -21,7 +21,7 @@ config ARCH_MSM8X60
select CPU_V7
select HAVE_SMP
select MSM_SCM if SMP
- select MSM_TIMER
+ select CLKSRC_QCOM
config ARCH_MSM8960
bool "Enable support for MSM8960"
@@ -29,7 +29,7 @@ config ARCH_MSM8960
select CPU_V7
select HAVE_SMP
select MSM_SCM if SMP
- select MSM_TIMER
+ select CLKSRC_QCOM
config ARCH_MSM8974
bool "Enable support for MSM8974"
@@ -54,7 +54,7 @@ config ARCH_MSM7X00A
select MACH_TROUT if !MACH_HALIBUT
select MSM_PROC_COMM
select MSM_SMD
- select MSM_TIMER
+ select CLKSRC_QCOM
select MSM_SMD_PKG3
config ARCH_MSM7X30
@@ -66,7 +66,7 @@ config ARCH_MSM7X30
select MSM_GPIOMUX
select MSM_PROC_COMM
select MSM_SMD
- select MSM_TIMER
+ select CLKSRC_QCOM
select MSM_VIC
config ARCH_QSD8X50
@@ -78,7 +78,7 @@ config ARCH_QSD8X50
select MSM_GPIOMUX
select MSM_PROC_COMM
select MSM_SMD
- select MSM_TIMER
+ select CLKSRC_QCOM
select MSM_VIC
endchoice
@@ -153,7 +153,4 @@ config MSM_GPIOMUX
config MSM_SCM
bool
-config MSM_TIMER
- bool
-
endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 721f27f..4baff13 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,4 +1,3 @@
-obj-$(CONFIG_MSM_TIMER) += timer.o
obj-$(CONFIG_MSM_PROC_COMM) += clock.o
obj-$(CONFIG_MSM_VIC) += irq-vic.o
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index cd6950f..81caa16 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -140,3 +140,7 @@ config VF_PIT_TIMER
bool
help
Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
+
+config CLKSRC_QCOM
+ bool
+ depends on ARCH_MSM
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index c7ca50a..2e0c0cc 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o
obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
+obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/arch/arm/mach-msm/timer.c b/drivers/clocksource/qcom-timer.c
similarity index 98%
rename from arch/arm/mach-msm/timer.c
rename to drivers/clocksource/qcom-timer.c
index fd16449..dca829e 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/drivers/clocksource/qcom-timer.c
@@ -1,7 +1,7 @@
/*
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -26,10 +26,6 @@
#include <linux/of_irq.h>
#include <linux/sched_clock.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-
#define TIMER_MATCH_VAL 0x0000
#define TIMER_COUNT_VAL 0x0004
#define TIMER_ENABLE 0x0008
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH 2/4] arm: qcom: Split Qualcomm support into legacy and multiplatform
From: Kumar Gala @ 2014-01-30 18:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391107002-21470-1-git-send-email-galak@codeaurora.org>
Introduce a new mach-qcom that will support SoCs that intend to be
multiplatform compatiable while keeping mach-msm to legacy SoC/board
support that will not transition over to multiplatform.
As part of this, we move support for MSM8X60, MSM8960 and MSM8974 over
to mach-qcom.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
---
MAINTAINERS | 7 +++
arch/arm/Kconfig | 7 +--
arch/arm/Makefile | 1 +
arch/arm/boot/dts/Makefile | 6 +--
arch/arm/mach-msm/Kconfig | 45 +------------------
arch/arm/mach-msm/Makefile | 7 ---
arch/arm/mach-msm/hotplug.c | 51 ----------------------
arch/arm/mach-qcom/Kconfig | 34 +++++++++++++++
arch/arm/mach-qcom/Makefile | 5 +++
.../arm/{mach-msm/board-dt.c => mach-qcom/board.c} | 9 ++--
arch/arm/{mach-msm => mach-qcom}/scm-boot.c | 0
arch/arm/{mach-msm => mach-qcom}/scm-boot.h | 0
arch/arm/{mach-msm => mach-qcom}/scm.c | 0
arch/arm/{mach-msm => mach-qcom}/scm.h | 0
arch/arm/{mach-msm/platsmp.c => mach-qcom/smp.c} | 11 ++++-
15 files changed, 70 insertions(+), 113 deletions(-)
delete mode 100644 arch/arm/mach-msm/hotplug.c
create mode 100644 arch/arm/mach-qcom/Kconfig
create mode 100644 arch/arm/mach-qcom/Makefile
rename arch/arm/{mach-msm/board-dt.c => mach-qcom/board.c} (71%)
rename arch/arm/{mach-msm => mach-qcom}/scm-boot.c (100%)
rename arch/arm/{mach-msm => mach-qcom}/scm-boot.h (100%)
rename arch/arm/{mach-msm => mach-qcom}/scm.c (100%)
rename arch/arm/{mach-msm => mach-qcom}/scm.h (100%)
rename arch/arm/{mach-msm/platsmp.c => mach-qcom/smp.c} (97%)
diff --git a/MAINTAINERS b/MAINTAINERS
index a31a6e3..1817078 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1174,6 +1174,13 @@ L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
W: http://www.arm.linux.org.uk/
S: Maintained
+ARM/QUALCOMM SUPPORT
+M: David Brown <davidb@codeaurora.org>
+M: Kumar Gala <galak@codeaurora.org>
+L: linux-arm-msm at vger.kernel.org
+S: Maintained
+F: arch/arm/mach-qcom/
+
ARM/RADISYS ENP2611 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dc6ef9a..9be7483 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -657,9 +657,8 @@ config ARCH_PXA
help
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
-config ARCH_MSM_NODT
- bool "Qualcomm MSM"
- select ARCH_MSM
+config ARCH_MSM
+ bool "Qualcomm MSM (non-multiplatform)"
select ARCH_REQUIRE_GPIOLIB
select COMMON_CLK
select GENERIC_CLOCKEVENTS
@@ -1005,6 +1004,8 @@ source "arch/arm/plat-pxa/Kconfig"
source "arch/arm/mach-mmp/Kconfig"
+source "arch/arm/mach-qcom/Kconfig"
+
source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 08a9ef5..51e5bed 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell
machine-$(CONFIG_ARCH_PXA) += pxa
+machine-$(CONFIG_ARCH_QCOM) += qcom
machine-$(CONFIG_ARCH_REALVIEW) += realview
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_RPC) += rpc
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9d6a8b..c9eaf1f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -118,9 +118,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
kirkwood-ts219-6282.dtb
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
-dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \
- qcom-msm8960-cdp.dtb \
- qcom-apq8074-dragonboard.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
armada-370-mirabox.dtb \
armada-370-netgear-rn102.dtb \
@@ -232,6 +229,9 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
+ qcom-msm8960-cdp.dtb \
+ qcom-apq8074-dragonboard.dtb
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
ste-hrefprev60-stuib.dtb \
ste-hrefprev60-tvk.dtb \
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 3c4eca7..a7f959e 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1,50 +1,9 @@
-config ARCH_MSM
- bool
-
-config ARCH_MSM_DT
- bool "Qualcomm MSM DT Support" if ARCH_MULTI_V7
- select ARCH_MSM
- select ARCH_REQUIRE_GPIOLIB
- select CLKSRC_OF
- select GENERIC_CLOCKEVENTS
- help
- Support for Qualcomm's devicetree based MSM systems.
-
if ARCH_MSM
-menu "Qualcomm MSM SoC Selection"
- depends on ARCH_MSM_DT
-
-config ARCH_MSM8X60
- bool "Enable support for MSM8X60"
- select ARM_GIC
- select CPU_V7
- select HAVE_SMP
- select MSM_SCM if SMP
- select CLKSRC_QCOM
-
-config ARCH_MSM8960
- bool "Enable support for MSM8960"
- select ARM_GIC
- select CPU_V7
- select HAVE_SMP
- select MSM_SCM if SMP
- select CLKSRC_QCOM
-
-config ARCH_MSM8974
- bool "Enable support for MSM8974"
- select ARM_GIC
- select CPU_V7
- select HAVE_ARM_ARCH_TIMER
- select HAVE_SMP
- select MSM_SCM if SMP
-
-endmenu
-
choice
prompt "Qualcomm MSM SoC Type"
default ARCH_MSM7X00A
- depends on ARCH_MSM_NODT
+ depends on ARCH_MSM
config ARCH_MSM7X00A
bool "MSM7x00A / MSM7x01A"
@@ -99,7 +58,7 @@ config MSM_VIC
bool
menu "Qualcomm MSM Board Type"
- depends on ARCH_MSM_NODT
+ depends on ARCH_MSM
config MACH_HALIBUT
depends on ARCH_MSM
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 4baff13..27c078a 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -13,18 +13,11 @@ obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
obj-$(CONFIG_MSM_SMD) += last_radio_log.o
-obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
-
-CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
-
-obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
-obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o
obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
deleted file mode 100644
index cea80fc..0000000
--- a/arch/arm/mach-msm/hotplug.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2002 ARM Ltd.
- * All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-
-#include <asm/smp_plat.h>
-
-#include "common.h"
-
-static inline void cpu_enter_lowpower(void)
-{
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-}
-
-static inline void platform_do_lowpower(unsigned int cpu)
-{
- asm("wfi"
- :
- :
- : "memory", "cc");
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void __ref msm_cpu_die(unsigned int cpu)
-{
- /*
- * we're ready for shutdown now, so do it
- */
- cpu_enter_lowpower();
- platform_do_lowpower(cpu);
-
- /*
- * bring this CPU back into the world of cache
- * coherency, and then restore interrupts
- */
- cpu_leave_lowpower();
-}
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
new file mode 100644
index 0000000..8830431
--- /dev/null
+++ b/arch/arm/mach-qcom/Kconfig
@@ -0,0 +1,34 @@
+config ARCH_QCOM
+ bool "Qualcomm Support" if ARCH_MULTI_V7
+ select ARCH_REQUIRE_GPIOLIB
+ select CLKSRC_OF
+ select GENERIC_CLOCKEVENTS
+ select ARM_GIC
+ select CPU_V7
+ select HAVE_SMP
+ select QCOM_SCM if SMP
+ help
+ Support for Qualcomm's devicetree based systems.
+
+if ARCH_QCOM
+
+menu "Qualcomm SoC Selection"
+
+config ARCH_MSM8X60
+ bool "Enable support for MSM8X60"
+ select CLKSRC_QCOM
+
+config ARCH_MSM8960
+ bool "Enable support for MSM8960"
+ select CLKSRC_QCOM
+
+config ARCH_MSM8974
+ bool "Enable support for MSM8974"
+ select HAVE_ARM_ARCH_TIMER
+
+endmenu
+
+config QCOM_SCM
+ bool
+
+endif
diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile
new file mode 100644
index 0000000..c0ba0ef
--- /dev/null
+++ b/arch/arm/mach-qcom/Makefile
@@ -0,0 +1,5 @@
+obj-y := board.o
+obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_QCOM_SCM) += scm.o scm-boot.o
+
+CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-qcom/board.c
similarity index 71%
rename from arch/arm/mach-msm/board-dt.c
rename to arch/arm/mach-qcom/board.c
index 1e3af2b..bae617e 100644
--- a/arch/arm/mach-msm/board-dt.c
+++ b/arch/arm/mach-qcom/board.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2014 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -14,14 +14,13 @@
#include <asm/mach/arch.h>
-static const char * const msm_dt_match[] __initconst = {
- "qcom,msm8660-fluid",
+static const char * const qcom_dt_match[] __initconst = {
"qcom,msm8660-surf",
"qcom,msm8960-cdp",
"qcom,apq8074-dragonboard",
NULL
};
-DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
- .dt_compat = msm_dt_match,
+DT_MACHINE_START(QCOM_DT, "Qualcomm (Flattened Device Tree)")
+ .dt_compat = qcom_dt_match,
MACHINE_END
diff --git a/arch/arm/mach-msm/scm-boot.c b/arch/arm/mach-qcom/scm-boot.c
similarity index 100%
rename from arch/arm/mach-msm/scm-boot.c
rename to arch/arm/mach-qcom/scm-boot.c
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-qcom/scm-boot.h
similarity index 100%
rename from arch/arm/mach-msm/scm-boot.h
rename to arch/arm/mach-qcom/scm-boot.h
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-qcom/scm.c
similarity index 100%
rename from arch/arm/mach-msm/scm.c
rename to arch/arm/mach-qcom/scm.c
diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-qcom/scm.h
similarity index 100%
rename from arch/arm/mach-msm/scm.h
rename to arch/arm/mach-qcom/scm.h
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-qcom/smp.c
similarity index 97%
rename from arch/arm/mach-msm/platsmp.c
rename to arch/arm/mach-qcom/smp.c
index 42eb6b7..28364cb 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-qcom/smp.c
@@ -2,6 +2,7 @@
* Copyright (C) 2002 ARM Ltd.
* All Rights Reserved
* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -20,7 +21,6 @@
#include <asm/smp_plat.h>
#include "scm-boot.h"
-#include "common.h"
#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0
#define SCSS_CPU1CORE_RESET 0x2d80
@@ -48,6 +48,15 @@ extern void secondary_startup(void);
static DEFINE_SPINLOCK(boot_lock);
+static void __ref msm_cpu_die(unsigned int cpu)
+{
+
+ asm("wfi"
+ :
+ :
+ : "memory", "cc");
+}
+
static void msm_secondary_init(unsigned int cpu)
{
/*
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH 3/4] clocksource: qcom: split building of legacy vs multiplatform support
From: Kumar Gala @ 2014-01-30 18:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391107002-21470-1-git-send-email-galak@codeaurora.org>
The majority of the clocksource code for the Qualcomm platform is shared
between newer (multiplatform) and older platforms. However there is a bit
of code that isn't, so only build it for the appropriate config.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
---
drivers/clocksource/qcom-timer.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/clocksource/qcom-timer.c b/drivers/clocksource/qcom-timer.c
index dca829e..e807acf 100644
--- a/drivers/clocksource/qcom-timer.c
+++ b/drivers/clocksource/qcom-timer.c
@@ -106,15 +106,6 @@ static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
return readl_relaxed(source_base + TIMER_COUNT_VAL);
}
-static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
-{
- /*
- * Shift timer count down by a constant due to unreliable lower bits
- * on some targets.
- */
- return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
-}
-
static struct clocksource msm_clocksource = {
.name = "dg_timer",
.rating = 300,
@@ -228,7 +219,7 @@ err:
sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
}
-#ifdef CONFIG_OF
+#ifdef CONFIG_ARCH_QCOM
static void __init msm_dt_timer_init(struct device_node *np)
{
u32 freq;
@@ -281,7 +272,7 @@ static void __init msm_dt_timer_init(struct device_node *np)
}
CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
-#endif
+#else
static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
u32 sts)
@@ -301,6 +292,15 @@ static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
return 0;
}
+static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
+{
+ /*
+ * Shift timer count down by a constant due to unreliable lower bits
+ * on some targets.
+ */
+ return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
+}
+
void __init msm7x01_timer_init(void)
{
struct clocksource *cs = &msm_clocksource;
@@ -327,3 +327,4 @@ void __init qsd8x50_timer_init(void)
return;
msm_timer_init(19200000 / 4, 32, 7, false);
}
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH 1/4] ARM: STi: add stid127 soc support
From: Arnd Bergmann @ 2014-01-30 18:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201401301935.16463.arnd@arndb.de>
On Thursday 30 January 2014, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Patrice CHOTARD wrote:
> > From: Alexandre TORGUE <alexandre.torgue@st.com>
> >
> > This patch adds support to STiD127 SoC.
> > The main adaptation is the L2 cache way size compare to STiH41x SoCs.
> >
> > Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> > Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> > ---
> > arch/arm/mach-sti/board-dt.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
>
> Wouldn't it be better to read this value from the l2 cache
> controller node? I'd assume there might be more SoCs that
> will need a similar change, so it's better to come up with
> a solution that doesn't involve changing the kernel every
> time.
Actually reading the code in this file shows that the L2 cache
initialization is the only nonstandard thing in there. We should
really find a way to get rid of the entire function.
Sorry if I missed the initial review, but can you explain
why this is needed to start with?
Arnd
^ permalink raw reply
* [PATCH v2 00/21] pinctrl: mvebu: restructure and remove hardcoded addresses from Dove pinctrl
From: Sebastian Hesselbarth @ 2014-01-30 18:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140130182925.GM10864@lunn.ch>
On 01/30/2014 07:29 PM, Andrew Lunn wrote:
> On Tue, Jan 28, 2014 at 01:39:12AM +0100, Sebastian Hesselbarth wrote:
>> This patch set is one required step for Dove to hop into mach-mvebu.
>> Until now, pinctrl-dove was hardcoding some registers that do not
>> directly belong to MPP core registers. This is not compatible with
>> what we want for mach-mvebu.
>
> I think there might be something wrong here....
There _is_ something wrong. I'll have a look at it. For the record,
what SoC are you testing with? From the base address, I guess it is
Kirkwood?
Sebastian
> /debug/pinctrl/f1010000.pinctrl/pinconf-groups used to contain:
>
> Pin config settings per pin group
> Format: group (name): configs
> 0 (mpp0):current: spi(cs), available = [ gpio(io) nand(io2) ]
> 1 (mpp1):current: spi(mosi), available = [ gpo(o) nand(io3) ]
> 2 (mpp2):current: spi(sck), available = [ gpo(o) nand(io4) ]
> 3 (mpp3):current: spi(miso), available = [ gpo(o) nand(io5) ]
> 4 (mpp4):current: sata1(act), available = [ gpio(io) nand(io6) uart0(rxd) lcd(hsync) ]
> 5 (mpp5):current: sata0(act), available = [ gpo(o) nand(io7) uart0(txd) lcd(vsync) ]
> 6 (mpp6):current: sysrst(out), available = [ spi(mosi) ]
> ...
>
> It now has:
>
> Pin config settings per pin group
> Format: group (name): configs
> 0 (mpp0):current: gpio(io), available = [ nand(io2) spi(cs) ]
> 1 (mpp1):current: gpo(o), available = [ nand(io3) spi(mosi) ]
> 2 (mpp2):current: gpo(o), available = [ nand(io4) spi(sck) ]
> 3 (mpp3):current: gpo(o), available = [ nand(io5) spi(miso) ]
> 4 (mpp4):current: gpio(io), available = [ nand(io6) uart0(rxd) sata1(act) lcd(hsync) ]
> 5 (mpp5):current: gpo(o), available = [ nand(io7) uart0(txd) sata0(act) lcd(vsync) ]
> 6 (mpp6):current: UNKNOWN, available = [ sysrst(out) spi(mosi) ]
>
> The device i'm testing on does use spi and sata, so i would say the
> old contents was correct and the new is wrong.
^ permalink raw reply
* [RFC] arm: vdso: Convert sigpage to vdso implementation
From: Will Deacon @ 2014-01-30 18:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140129142235.GA12965@linaro.org>
On Wed, Jan 29, 2014 at 02:22:36PM +0000, Steve Capper wrote:
> On Tue, Jan 26, 2014 at 05:10:15PM +0000, Russell King - ARM Linux wrote:
> > I'm not happy with this removing much of the work I pushed into the
> > kernel to work around the security issues which were identified with
> > the fixed-address placement of stuff in the vectors page. Particularly
> > the random placement of the signal return stubs within the new signal
> > page is gone with the VDSO approach, which means if someone can discover
> > the VDSO page, they can issue any system call they please by knowing
> > the appropriate offset into the page to call.
[...]
> > While the VDSO page will be placed randomly, I'd also like to have the
> > signal handlers placed randomly within that page as well - there's no
> > need for them to be at a fixed offset. The only thing which needs to
> > know where they are after all is the kernel.
>
> I was considering a larger segment containing the trampoline at random
> offset, but came to the conclusion that the VA randomisation of the
> vdso page location was in itself sufficient?
Whilst randomising within a page could potentially be beneficial, I question
just how much use it is doing it only for the signal page. For example, for
a system running a given version of libc, if you know where libc is mapped,
then you can easily find syscall sequences in there. Similarly for
gettimeofday() in the vDSO, there is a syscall fallback path too.
Dynamically randomising the layout of shared libraries is likely to confuse
the dynamic linker and completely break debugging with GDB. It's also not
something that I'm aware of being done by any other architectures in the
kernel.
I think there's a trade-off between the measurable performance advantage of
exporting functions such as gtod in the vDSO and the unclear security gains
of randomising the sigreturn code within a page when the page address is
already randomised.
> > I believe x86 eventually ended up going down the path of trapping and
> > emulating calls to the VDSO page because VDSO became too much of a
> > problem (though I think it does provide the option for having it back
> > but not by default.)
Hmm, do you have any pointers to more information about that? I know that
the vsyscall page went the way of the dodo because it was placed at a fixed
address, but I thought that the vDSO was still alive and kicking.
Will
^ permalink raw reply
* [PATCH 5/5] arm64: add Crypto Extensions based synchronous core AES cipher
From: Will Deacon @ 2014-01-30 18:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391014246-9715-6-git-send-email-ard.biesheuvel@linaro.org>
Hi Ard,
On Wed, Jan 29, 2014 at 04:50:46PM +0000, Ard Biesheuvel wrote:
> diff --git a/arch/arm64/crypto/aes-ce-cipher.c b/arch/arm64/crypto/aes-ce-cipher.c
> new file mode 100644
> index 000000000000..b5a5d5d6e4b8
> --- /dev/null
> +++ b/arch/arm64/crypto/aes-ce-cipher.c
> @@ -0,0 +1,103 @@
> +/*
> + * linux/arch/arm64/crypto/aes-ce-cipher.c
> + *
> + * Copyright (C) 2013 Linaro Ltd <ard.biesheuvel@linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <asm/neon.h>
> +#include <crypto/aes.h>
> +#include <linux/crypto.h>
> +#include <linux/module.h>
> +#include <linux/cpufeature.h>
> +
> +MODULE_DESCRIPTION("Synchronous AES cipher using ARMv8 Crypto Extensions");
> +MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
> +MODULE_LICENSE("GPL");
> +
> +static void aes_cipher_encrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[])
> +{
> + struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
> + u32 rounds = 6 + ctx->key_length / 4;
Can you document these constants please?
> +
> + kernel_neon_begin();
> +
> + __asm__(" ld1 {v0.16b}, [%[in]] ;"
> + " ld1 {v1.16b}, [%[key]], #16 ;"
> + "0: aese v0.16b, v1.16b ;"
> + " subs %[rounds], %[rounds], #1 ;"
> + " ld1 {v1.16b}, [%[key]], #16 ;"
> + " beq 1f ;"
> + " aesmc v0.16b, v0.16b ;"
> + " b 0b ;"
> + "1: eor v0.16b, v0.16b, v1.16b ;"
> + " st1 {v0.16b}, [%[out]] ;"
> + : :
> + [out] "r"(dst),
> + [in] "r"(src),
> + [rounds] "r"(rounds),
> + [key] "r"(ctx->key_enc)
> + : "cc");
You probably need a memory output to stop this being re-ordered by the
compiler. Can GCC not generate the addressing modes you need directly,
allowing you to avoid moving everything into registers?
> + kernel_neon_end();
> +}
> +
> +static void aes_cipher_decrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[])
> +{
> + struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
> + u32 rounds = 6 + ctx->key_length / 4;
> +
> + kernel_neon_begin();
> +
> + __asm__(" ld1 {v0.16b}, [%[in]] ;"
> + " ld1 {v1.16b}, [%[key]], #16 ;"
> + "0: aesd v0.16b, v1.16b ;"
> + " ld1 {v1.16b}, [%[key]], #16 ;"
> + " subs %[rounds], %[rounds], #1 ;"
> + " beq 1f ;"
> + " aesimc v0.16b, v0.16b ;"
> + " b 0b ;"
> + "1: eor v0.16b, v0.16b, v1.16b ;"
> + " st1 {v0.16b}, [%[out]] ;"
> + : :
> + [out] "r"(dst),
> + [in] "r"(src),
> + [rounds] "r"(rounds),
> + [key] "r"(ctx->key_dec)
> + : "cc");
Same comments here.
FWIW: I spoke to the guy at ARM who designed the crypto instructions and he
reckons your code works :)
Cheers,
Will "got a B in maths" Deacon
^ permalink raw reply
* [PATCH 5/5] arm64: add Crypto Extensions based synchronous core AES cipher
From: Ard Biesheuvel @ 2014-01-30 19:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140130185645.GC4437@mudshark.cambridge.arm.com>
On 30 January 2014 19:56, Will Deacon <will.deacon@arm.com> wrote:
> Hi Ard,
>
> On Wed, Jan 29, 2014 at 04:50:46PM +0000, Ard Biesheuvel wrote:
>> diff --git a/arch/arm64/crypto/aes-ce-cipher.c b/arch/arm64/crypto/aes-ce-cipher.c
>> new file mode 100644
>> index 000000000000..b5a5d5d6e4b8
>> --- /dev/null
>> +++ b/arch/arm64/crypto/aes-ce-cipher.c
>> @@ -0,0 +1,103 @@
>> +/*
>> + * linux/arch/arm64/crypto/aes-ce-cipher.c
>> + *
>> + * Copyright (C) 2013 Linaro Ltd <ard.biesheuvel@linaro.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <asm/neon.h>
>> +#include <crypto/aes.h>
>> +#include <linux/crypto.h>
>> +#include <linux/module.h>
>> +#include <linux/cpufeature.h>
>> +
>> +MODULE_DESCRIPTION("Synchronous AES cipher using ARMv8 Crypto Extensions");
>> +MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
>> +MODULE_LICENSE("GPL");
>> +
>> +static void aes_cipher_encrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[])
>> +{
>> + struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
>> + u32 rounds = 6 + ctx->key_length / 4;
>
> Can you document these constants please?
>
Sure.
>> +
>> + kernel_neon_begin();
>> +
>> + __asm__(" ld1 {v0.16b}, [%[in]] ;"
>> + " ld1 {v1.16b}, [%[key]], #16 ;"
>> + "0: aese v0.16b, v1.16b ;"
>> + " subs %[rounds], %[rounds], #1 ;"
>> + " ld1 {v1.16b}, [%[key]], #16 ;"
>> + " beq 1f ;"
>> + " aesmc v0.16b, v0.16b ;"
>> + " b 0b ;"
>> + "1: eor v0.16b, v0.16b, v1.16b ;"
>> + " st1 {v0.16b}, [%[out]] ;"
>> + : :
>> + [out] "r"(dst),
>> + [in] "r"(src),
>> + [rounds] "r"(rounds),
>> + [key] "r"(ctx->key_enc)
>> + : "cc");
>
> You probably need a memory output to stop this being re-ordered by the
> compiler. Can GCC not generate the addressing modes you need directly,
> allowing you to avoid moving everything into registers?
>
Would a memory clobber work as well?
Re addressing modes: I would prefer to explicitly use v0 and v1, I
have another patch pending that allows partial saves/restores of the
NEON register file when called from interrupt context. I suppose I
could use 'register asm("v0")' or something like that, but that won't
make it any prettier.
>
>> + kernel_neon_end();
>> +}
>> +
>> +static void aes_cipher_decrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[])
>> +{
>> + struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
>> + u32 rounds = 6 + ctx->key_length / 4;
>> +
>> + kernel_neon_begin();
>> +
>> + __asm__(" ld1 {v0.16b}, [%[in]] ;"
>> + " ld1 {v1.16b}, [%[key]], #16 ;"
>> + "0: aesd v0.16b, v1.16b ;"
>> + " ld1 {v1.16b}, [%[key]], #16 ;"
>> + " subs %[rounds], %[rounds], #1 ;"
>> + " beq 1f ;"
>> + " aesimc v0.16b, v0.16b ;"
>> + " b 0b ;"
>> + "1: eor v0.16b, v0.16b, v1.16b ;"
>> + " st1 {v0.16b}, [%[out]] ;"
>> + : :
>> + [out] "r"(dst),
>> + [in] "r"(src),
>> + [rounds] "r"(rounds),
>> + [key] "r"(ctx->key_dec)
>> + : "cc");
>
> Same comments here.
>
> FWIW: I spoke to the guy at ARM who designed the crypto instructions and he
> reckons your code works :)
>
Good!
Care to comment on the rest of the series?
Cheers.
Ard.
^ permalink raw reply
* [PATCH v2 1/6] idle: move the cpuidle entry point to the generic idle loop
From: Nicolas Pitre @ 2014-01-30 19:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52EA8BD4.6020803@linaro.org>
On Thu, 30 Jan 2014, Daniel Lezcano wrote:
> On 01/30/2014 05:07 PM, Nicolas Pitre wrote:
> > On Thu, 30 Jan 2014, Daniel Lezcano wrote:
> > > But what I don't get with your comment is the local_irq_enable is done
> > > from
> > > the cpuidle common framework in 'cpuidle_enter_state' it is not done from
> > > the
> > > arch specific backend cpuidle driver.
> >
> > Oh well... This certainly means we'll have to clean this mess as some
> > drivers do it on their own while some others don't. Some drivers also
> > loop on !need_resched() while some others simply return on the first
> > interrupt.
>
> Ok, I think the mess is coming from 'default_idle' which does not re-enable
> the local_irq but used from different places like amd_e400_idle and
> apm_cpu_idle.
Yet if you look at the code path before my patches you'll see that IRQs
were enabled only after cpuidle_idle_call() had returned success.
> void default_idle(void)
> {
> trace_cpu_idle_rcuidle(1, smp_processor_id());
> safe_halt();
> trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
> }
>
> Considering the system configured without cpuidle because this one *always*
> enable the local irq,
Yet this is discutable. Given that some hardware do have IRQs turned on
upon exiting idle mode, I think we should generalize it so that
the explicit enabling
of IRQs, when needed, should be done as close as possible to the
operation that caused idle mode to be entered.
> we have the different cases:
>
> x86_idle = default_idle();
> ==> local_irq_enable is missing
According to Peter it is not.
> x86_idle = amd_e400_idle();
> ==> it calls local_irq_disable(); but in the idle loop context where the
> local irqs are already disabled.
Since it returned from default_idle() then IRQs are enabled.
> ==> if amd_e400_c1e_detected is true, the local_irq are enabled
> ==> otherwise no
> ==> default_idle is called from there and does not enable local_irqs
Again, it does.
> > > So the code above could be:
> > >
> > > if (cpuidle_idle_call())
> > > x86_idle();
> > >
> > > without the else section, this local_irq_enable is pointless. Or may be I
> > > missed something ?
> >
> > A later patch removes it anyway. But if it is really necessary to
> > enable interrupts then the core will do it but with a warning now.
>
> This WARN should disappear. It was there because it was up to the backend
> cpuidle driver to enable the irq. But in the meantime, that was consolidated
> into a single place in the cpuidle framework so no need to try to catch
> errors.
And that consolidation was a mistake IMHO. We should assume that the
exiting of idle mode has IRQs enabled already, and do so manually in the
backend driver if it is not the case on particular hardware. That's the
only way to ensure uniformity at a higher level.
Yet, if a code path is buggy in that regard, whether this is through
cpuidle when enabled, or the default idle function otherwise, then the
warning is there in cpu_idle_loop() to catch them all.
> What about (based on this patchset).
>
> diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
> index 4505e2a..2d60cbb 100644
> --- a/arch/x86/kernel/process.c
> +++ b/arch/x86/kernel/process.c
> @@ -299,6 +299,7 @@ void arch_cpu_idle_dead(void)
> void arch_cpu_idle(void)
> {
> x86_idle();
> + local_irq_enable();
> }
Again this is redundant.
Nicolas
^ permalink raw reply
* [PATCH RFC] Remove ARM-specific set_irq_flags usage from irqdomain implementations
From: Josh Cartwright @ 2014-01-30 19:29 UTC (permalink / raw)
To: linux-arm-kernel
Hey all-
Looking through a bunch of irqdomain implementations (and in some other
places), it appears that the following pattern is distressingly common:
static int foo_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
/*...*/
#ifdef CONFIG_ARM
set_irq_flags(irq, IRQF_VALID);
#else
irq_set_noprobe(irq);
#endif
return 0;
}
Which, to someone unfamiliar with how ARM's set_irq_flags() (and ARM's
ARCH_IRQ_INIT_FLAGS), is just confusing and ugly[1].
I think there is an opportunity for some simplification here, based on
the following assumptions[2]:
1. The irqdomain core already manages the IRQ_NOREQUEST bit, clearing
it after creating a association, and setting it on disassociation
2. No existing irqdomain implementations are relying on
set_irq_flags() to clear the IRQ_NOAUTOEN bit
If these two assumptions hold, then the following simplification can
take place[3]:
-#if CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
The first assumption fairly clearly holds, looking at the irqdomain
core. I'm confident that the fact that IRQF_NOAUTOEN is not in
ARCH_IRQ_INIT_FLAGS and that no existing IRQF_NOAUTOEN users appear to
muck with irqdomains that it's a safe bet. And...any code relying
AUTOEN to be cleared would currently be broken on non-ARM platforms.
Thoughts? If this is a worthwhile simplification and my analysis is
sane, I'll cook up the proper patches.
Thanks,
Josh
[1]: git grep 'kill me now'
[2]: For reference, here's a truth table establishing the mapping between
ARM's IRQF_{VALID,PROBE,NOAUTOEN} flags and the generic flags:
V P NA | NR NP NA
0 0 0 | 1 1 0
ARM-specific 0 0 1 | 1 1 1 genirq irqflag
irqflags 0 1 0 | 1 0 0 definitions
V - IRQF_VALID 0 1 1 | 1 0 1 NR - IRQ_NOREQUEST
P - IRQF_PROBE 1 0 0 | 0 1 0 NP - IRQ_NOPROBE
NA - IRQF_NOAUTOEN 1 0 1 | 0 1 1 NA - IRQ_NOAUTOEN
1 1 0 | 0 0 0
1 1 1 | 0 0 1
[3]: With the same justifications, on unmap:
-#if CONFIG_ARM
- set_irq_flags(irq, 0);
-#endif
---
drivers/base/regmap/regmap-irq.c | 8 --------
drivers/gpio/gpio-adnp.c | 6 ------
drivers/gpio/gpio-bcm-kona.c | 5 -----
drivers/gpio/gpio-grgpio.c | 8 --------
drivers/gpio/gpio-pca953x.c | 5 -----
drivers/gpio/gpio-pcf857x.c | 4 ----
drivers/gpio/gpio-stmpe.c | 8 --------
drivers/gpio/gpio-tc3589x.c | 8 --------
drivers/mfd/88pm860x-core.c | 4 ----
drivers/mfd/ab8500-core.c | 5 -----
drivers/mfd/arizona-irq.c | 8 --------
drivers/mfd/lp8788-irq.c | 6 ------
drivers/mfd/max77686-irq.c | 4 ----
drivers/mfd/max77693-irq.c | 4 ----
drivers/mfd/max8925-core.c | 4 ----
drivers/mfd/max8997-irq.c | 4 ----
drivers/mfd/max8998-irq.c | 4 ----
drivers/mfd/stmpe.c | 8 --------
drivers/mfd/tc3589x.c | 8 --------
drivers/mfd/tps6586x.c | 8 --------
drivers/mfd/twl6030-irq.c | 14 --------------
drivers/mfd/wm831x-irq.c | 8 --------
drivers/mfd/wm8994-irq.c | 8 --------
drivers/pinctrl/pinctrl-single.c | 4 ----
24 files changed, 153 deletions(-)
diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c
index 763c60d..cd3add8 100644
--- a/drivers/base/regmap/regmap-irq.c
+++ b/drivers/base/regmap/regmap-irq.c
@@ -306,15 +306,7 @@ static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
irq_set_chip_data(virq, data);
irq_set_chip(virq, &data->irq_chip);
irq_set_nested_thread(virq, 1);
-
- /* ARM needs us to explicitly flag the IRQ as valid
- * and will set them noprobe when we do so. */
-#ifdef CONFIG_ARM
- set_irq_flags(virq, IRQF_VALID);
-#else
irq_set_noprobe(virq);
-#endif
-
return 0;
}
diff --git a/drivers/gpio/gpio-adnp.c b/drivers/gpio/gpio-adnp.c
index b204033..d34f41d 100644
--- a/drivers/gpio/gpio-adnp.c
+++ b/drivers/gpio/gpio-adnp.c
@@ -423,13 +423,7 @@ static int adnp_irq_map(struct irq_domain *domain, unsigned int irq,
irq_set_chip_data(irq, domain->host_data);
irq_set_chip(irq, &adnp_irq_chip);
irq_set_nested_thread(irq, true);
-
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
-
return 0;
}
diff --git a/drivers/gpio/gpio-bcm-kona.c b/drivers/gpio/gpio-bcm-kona.c
index 54c18c2..61dff06 100644
--- a/drivers/gpio/gpio-bcm-kona.c
+++ b/drivers/gpio/gpio-bcm-kona.c
@@ -480,12 +480,7 @@ static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
return ret;
irq_set_lockdep_class(irq, &gpio_lock_class);
irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
-
return 0;
}
diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c
index 84d2478..3f5496e 100644
--- a/drivers/gpio/gpio-grgpio.c
+++ b/drivers/gpio/gpio-grgpio.c
@@ -282,12 +282,7 @@ static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
irq_set_chip_and_handler(irq, &grgpio_irq_chip,
handle_simple_irq);
irq_clear_status_flags(irq, IRQ_NOREQUEST);
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
-
return ret;
}
@@ -301,9 +296,6 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
int ngpio = priv->bgc.gc.ngpio;
int i;
-#ifdef CONFIG_ARM
- set_irq_flags(irq, 0);
-#endif
irq_set_chip_and_handler(irq, NULL, NULL);
irq_set_chip_data(irq, NULL);
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index 6e48c07..05cbfa2 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -525,12 +525,7 @@ static int pca953x_gpio_irq_map(struct irq_domain *d, unsigned int irq,
irq_set_chip_data(irq, d->host_data);
irq_set_chip(irq, &pca953x_irq_chip);
irq_set_nested_thread(irq, true);
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
-
return 0;
}
diff --git a/drivers/gpio/gpio-pcf857x.c b/drivers/gpio/gpio-pcf857x.c
index 1535686..5b3ab60 100644
--- a/drivers/gpio/gpio-pcf857x.c
+++ b/drivers/gpio/gpio-pcf857x.c
@@ -226,11 +226,7 @@ static int pcf857x_irq_domain_map(struct irq_domain *domain, unsigned int irq,
irq_set_chip_and_handler(irq,
&dummy_irq_chip,
handle_level_irq);
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
gpio->irq_mapped |= (1 << hw);
return 0;
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index 2647e24..dd661a99 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -284,20 +284,12 @@ static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int irq,
irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
handle_simple_irq);
irq_set_nested_thread(irq, 1);
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
-
return 0;
}
static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
{
-#ifdef CONFIG_ARM
- set_irq_flags(irq, 0);
-#endif
irq_set_chip_and_handler(irq, NULL, NULL);
irq_set_chip_data(irq, NULL);
}
diff --git a/drivers/gpio/gpio-tc3589x.c b/drivers/gpio/gpio-tc3589x.c
index ddb5fef..e5402f7 100644
--- a/drivers/gpio/gpio-tc3589x.c
+++ b/drivers/gpio/gpio-tc3589x.c
@@ -263,20 +263,12 @@ static int tc3589x_gpio_irq_map(struct irq_domain *d, unsigned int irq,
irq_set_chip_and_handler(irq, &tc3589x_gpio_irq_chip,
handle_simple_irq);
irq_set_nested_thread(irq, 1);
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
-
return 0;
}
static void tc3589x_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
{
-#ifdef CONFIG_ARM
- set_irq_flags(irq, 0);
-#endif
irq_set_chip_and_handler(irq, NULL, NULL);
irq_set_chip_data(irq, NULL);
}
diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c
index c9b1f64..49d29ab 100644
--- a/drivers/mfd/88pm860x-core.c
+++ b/drivers/mfd/88pm860x-core.c
@@ -552,11 +552,7 @@ static int pm860x_irq_domain_map(struct irq_domain *d, unsigned int virq,
irq_set_chip_data(virq, d->host_data);
irq_set_chip_and_handler(virq, &pm860x_irq_chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
-#ifdef CONFIG_ARM
- set_irq_flags(virq, IRQF_VALID);
-#else
irq_set_noprobe(virq);
-#endif
return 0;
}
diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c
index b6c2cdc..f6b2b1e 100644
--- a/drivers/mfd/ab8500-core.c
+++ b/drivers/mfd/ab8500-core.c
@@ -563,12 +563,7 @@ static int ab8500_irq_map(struct irq_domain *d, unsigned int virq,
irq_set_chip_and_handler(virq, &ab8500_irq_chip,
handle_simple_irq);
irq_set_nested_thread(virq, 1);
-#ifdef CONFIG_ARM
- set_irq_flags(virq, IRQF_VALID);
-#else
irq_set_noprobe(virq);
-#endif
-
return 0;
}
diff --git a/drivers/mfd/arizona-irq.c b/drivers/mfd/arizona-irq.c
index 88758ab..31e9c20 100644
--- a/drivers/mfd/arizona-irq.c
+++ b/drivers/mfd/arizona-irq.c
@@ -166,15 +166,7 @@ static int arizona_irq_map(struct irq_domain *h, unsigned int virq,
irq_set_chip_data(virq, data);
irq_set_chip_and_handler(virq, &arizona_irq_chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
-
- /* ARM needs us to explicitly flag the IRQ as valid
- * and will set them noprobe when we do so. */
-#ifdef CONFIG_ARM
- set_irq_flags(virq, IRQF_VALID);
-#else
irq_set_noprobe(virq);
-#endif
-
return 0;
}
diff --git a/drivers/mfd/lp8788-irq.c b/drivers/mfd/lp8788-irq.c
index c84ded5..26b25ec 100644
--- a/drivers/mfd/lp8788-irq.c
+++ b/drivers/mfd/lp8788-irq.c
@@ -139,13 +139,7 @@ static int lp8788_irq_map(struct irq_domain *d, unsigned int virq,
irq_set_chip_data(virq, irqd);
irq_set_chip_and_handler(virq, chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
-
-#ifdef CONFIG_ARM
- set_irq_flags(virq, IRQF_VALID);
-#else
irq_set_noprobe(virq);
-#endif
-
return 0;
}
diff --git a/drivers/mfd/max77686-irq.c b/drivers/mfd/max77686-irq.c
index cdc3280..12fbbcb 100644
--- a/drivers/mfd/max77686-irq.c
+++ b/drivers/mfd/max77686-irq.c
@@ -230,11 +230,7 @@ static int max77686_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_set_chip_data(irq, max77686);
irq_set_chip_and_handler(irq, &max77686_irq_chip, handle_edge_irq);
irq_set_nested_thread(irq, 1);
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
return 0;
}
diff --git a/drivers/mfd/max77693-irq.c b/drivers/mfd/max77693-irq.c
index 66b58fe..8c9c9e8 100644
--- a/drivers/mfd/max77693-irq.c
+++ b/drivers/mfd/max77693-irq.c
@@ -246,11 +246,7 @@ static int max77693_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_set_chip_data(irq, max77693);
irq_set_chip_and_handler(irq, &max77693_irq_chip, handle_edge_irq);
irq_set_nested_thread(irq, 1);
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
return 0;
}
diff --git a/drivers/mfd/max8925-core.c b/drivers/mfd/max8925-core.c
index f0cc402..f1d9b1e 100644
--- a/drivers/mfd/max8925-core.c
+++ b/drivers/mfd/max8925-core.c
@@ -648,11 +648,7 @@ static int max8925_irq_domain_map(struct irq_domain *d, unsigned int virq,
irq_set_chip_data(virq, d->host_data);
irq_set_chip_and_handler(virq, &max8925_irq_chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
-#ifdef CONFIG_ARM
- set_irq_flags(virq, IRQF_VALID);
-#else
irq_set_noprobe(virq);
-#endif
return 0;
}
diff --git a/drivers/mfd/max8997-irq.c b/drivers/mfd/max8997-irq.c
index 43fa614..9425f80 100644
--- a/drivers/mfd/max8997-irq.c
+++ b/drivers/mfd/max8997-irq.c
@@ -295,11 +295,7 @@ static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_set_chip_data(irq, max8997);
irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
irq_set_nested_thread(irq, 1);
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
return 0;
}
diff --git a/drivers/mfd/max8998-irq.c b/drivers/mfd/max8998-irq.c
index c469477..ef74d2a 100644
--- a/drivers/mfd/max8998-irq.c
+++ b/drivers/mfd/max8998-irq.c
@@ -206,11 +206,7 @@ static int max8998_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_set_chip_data(irq, max8998);
irq_set_chip_and_handler(irq, &max8998_irq_chip, handle_edge_irq);
irq_set_nested_thread(irq, 1);
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
return 0;
}
diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c
index fff63a4..e65d36e 100644
--- a/drivers/mfd/stmpe.c
+++ b/drivers/mfd/stmpe.c
@@ -957,20 +957,12 @@ static int stmpe_irq_map(struct irq_domain *d, unsigned int virq,
irq_set_chip_data(virq, stmpe);
irq_set_chip_and_handler(virq, chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
-#ifdef CONFIG_ARM
- set_irq_flags(virq, IRQF_VALID);
-#else
irq_set_noprobe(virq);
-#endif
-
return 0;
}
static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq)
{
-#ifdef CONFIG_ARM
- set_irq_flags(virq, 0);
-#endif
irq_set_chip_and_handler(virq, NULL, NULL);
irq_set_chip_data(virq, NULL);
}
diff --git a/drivers/mfd/tc3589x.c b/drivers/mfd/tc3589x.c
index 87ea51d..a1e8d7b 100644
--- a/drivers/mfd/tc3589x.c
+++ b/drivers/mfd/tc3589x.c
@@ -213,20 +213,12 @@ static int tc3589x_irq_map(struct irq_domain *d, unsigned int virq,
irq_set_chip_and_handler(virq, &dummy_irq_chip,
handle_edge_irq);
irq_set_nested_thread(virq, 1);
-#ifdef CONFIG_ARM
- set_irq_flags(virq, IRQF_VALID);
-#else
irq_set_noprobe(virq);
-#endif
-
return 0;
}
static void tc3589x_irq_unmap(struct irq_domain *d, unsigned int virq)
{
-#ifdef CONFIG_ARM
- set_irq_flags(virq, 0);
-#endif
irq_set_chip_and_handler(virq, NULL, NULL);
irq_set_chip_data(virq, NULL);
}
diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index ee61fd7..5d46fea 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -290,15 +290,7 @@ static int tps6586x_irq_map(struct irq_domain *h, unsigned int virq,
irq_set_chip_data(virq, tps6586x);
irq_set_chip_and_handler(virq, &tps6586x_irq_chip, handle_simple_irq);
irq_set_nested_thread(virq, 1);
-
- /* ARM needs us to explicitly flag the IRQ as valid
- * and will set them noprobe when we do so. */
-#ifdef CONFIG_ARM
- set_irq_flags(virq, IRQF_VALID);
-#else
irq_set_noprobe(virq);
-#endif
-
return 0;
}
diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
index 517eda8..b355c20 100644
--- a/drivers/mfd/twl6030-irq.c
+++ b/drivers/mfd/twl6030-irq.c
@@ -349,26 +349,12 @@ static int twl6030_irq_map(struct irq_domain *d, unsigned int virq,
irq_set_chip_and_handler(virq, &pdata->irq_chip, handle_simple_irq);
irq_set_nested_thread(virq, true);
irq_set_parent(virq, pdata->twl_irq);
-
-#ifdef CONFIG_ARM
- /*
- * ARM requires an extra step to clear IRQ_NOREQUEST, which it
- * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
- */
- set_irq_flags(virq, IRQF_VALID);
-#else
- /* same effect on other architectures */
irq_set_noprobe(virq);
-#endif
-
return 0;
}
static void twl6030_irq_unmap(struct irq_domain *d, unsigned int virq)
{
-#ifdef CONFIG_ARM
- set_irq_flags(virq, 0);
-#endif
irq_set_chip_and_handler(virq, NULL, NULL);
irq_set_chip_data(virq, NULL);
}
diff --git a/drivers/mfd/wm831x-irq.c b/drivers/mfd/wm831x-irq.c
index 64e512e..bd7635e 100644
--- a/drivers/mfd/wm831x-irq.c
+++ b/drivers/mfd/wm831x-irq.c
@@ -552,15 +552,7 @@ static int wm831x_irq_map(struct irq_domain *h, unsigned int virq,
irq_set_chip_data(virq, h->host_data);
irq_set_chip_and_handler(virq, &wm831x_irq_chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
-
- /* ARM needs us to explicitly flag the IRQ as valid
- * and will set them noprobe when we do so. */
-#ifdef CONFIG_ARM
- set_irq_flags(virq, IRQF_VALID);
-#else
irq_set_noprobe(virq);
-#endif
-
return 0;
}
diff --git a/drivers/mfd/wm8994-irq.c b/drivers/mfd/wm8994-irq.c
index e74dedd..3d81759 100644
--- a/drivers/mfd/wm8994-irq.c
+++ b/drivers/mfd/wm8994-irq.c
@@ -172,15 +172,7 @@ static int wm8994_edge_irq_map(struct irq_domain *h, unsigned int virq,
irq_set_chip_data(virq, wm8994);
irq_set_chip_and_handler(virq, &wm8994_edge_irq_chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
-
- /* ARM needs us to explicitly flag the IRQ as valid
- * and will set them noprobe when we do so. */
-#ifdef CONFIG_ARM
- set_irq_flags(virq, IRQF_VALID);
-#else
irq_set_noprobe(virq);
-#endif
-
return 0;
}
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 829b98c..9755e01 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -1744,11 +1744,7 @@ static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_set_chip_and_handler(irq, &pcs->chip,
handle_level_irq);
-#ifdef CONFIG_ARM
- set_irq_flags(irq, IRQF_VALID);
-#else
irq_set_noprobe(irq);
-#endif
return 0;
}
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v2] pwm: add CSR SiRFSoC PWM driver
From: Arnd Bergmann @ 2014-01-30 19:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391061145-2078-1-git-send-email-21cnbao@gmail.com>
On Thursday 30 January 2014, Barry Song wrote:
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 7acab93..0a252f8 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -166,6 +166,15 @@ config PWM_SAMSUNG
> To compile this driver as a module, choose M here: the module
> will be called pwm-samsung.
>
> +config PWM_SIRF
> + tristate "SiRF PWM support"
> + depends on ARCH_SIRF
> + help
please make this "depends on ARCH_SIRF || COMPILE_TEST" if you can, so we
can build it on other platforms for test purposes. If you do this, you
have to list the full set of dependencies, so probably another
"depends on HAVE_CLK".
> +
> +#define to_sirf_chip(chip) container_of(chip, struct sirf_pwm, chip)
> +
> +static unsigned int sirf_pwm_ns_to_cycles(struct pwm_chip *chip, unsigned int time_ns)
> +{
> + u64 dividend;
> + unsigned int cycle;
> + /*
> + * on SiRFSoC, OSC input is const, we use it as the source to generate
> + * PWM wave
> + */
> +#define SRC_OSC_RATE 26000000ULL
> + dividend = SRC_OSC_RATE * time_ns + NSEC_PER_SEC / 2;
> + do_div(dividend, NSEC_PER_SEC);
> +
> + cycle = dividend & 0xFFFFFFFFUL;
> +
> + return cycle > 1 ? cycle : 1;
> +}
> +
Is SRC_OSC_RATE the rate of spwm->clk? If so, it would be nice to just call
clk_get_rate() here, in case you ever have a chip with a different rate.
This is a very nice driver otherwise!
Arnd
^ permalink raw reply
* [PATCH] documentation/iommu: Update description of ARM System MMU binding
From: Andreas Herrmann @ 2014-01-30 20:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391105889-32718-1-git-send-email-andreas.herrmann@calxeda.com>
This patch adds descriptions fore new properties of device tree
binding for the ARM SMMU architecture. These properties control
arm-smmu driver options.
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Andreas Herrmann <herrmann.der.user@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
---
.../devicetree/bindings/iommu/arm,smmu.txt | 11 +++++++++++
1 file changed, 11 insertions(+)
Hi Will,
I should have included this patch in the series as it describes the
options introduced there.
Andreas
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index e34c6cd..7ad8ff0 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -48,6 +48,16 @@ conditions.
from the mmu-masters towards memory) node for this
SMMU.
+- arm,smmu-isolate-devices : Enable device isolation for all masters
+ of this SMMU. Ie. each master will be attached to
+ its own iommu domain.
+
+- calxeda,smmu-secure-config-access : Enable proper handling of buggy
+ implementations that always use secure access to
+ SMMU configuration registers. In this case
+ non-secure aliases of secure registers have to be
+ used during SMMU configuration.
+
Example:
smmu {
@@ -67,4 +77,5 @@ Example:
*/
mmu-masters = <&dma0 0xd01d 0xd01e>,
<&dma1 0xd11c>;
+ arm,smmu-isolate-devices;
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 00/21] pinctrl: mvebu: restructure and remove hardcoded addresses from Dove pinctrl
From: Andrew Lunn @ 2014-01-30 20:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52EA9EFA.1030609@gmail.com>
On Thu, Jan 30, 2014 at 07:50:34PM +0100, Sebastian Hesselbarth wrote:
> On 01/30/2014 07:29 PM, Andrew Lunn wrote:
> >On Tue, Jan 28, 2014 at 01:39:12AM +0100, Sebastian Hesselbarth wrote:
> >>This patch set is one required step for Dove to hop into mach-mvebu.
> >>Until now, pinctrl-dove was hardcoding some registers that do not
> >>directly belong to MPP core registers. This is not compatible with
> >>what we want for mach-mvebu.
> >
> >I think there might be something wrong here....
>
> There _is_ something wrong. I'll have a look at it. For the record,
> what SoC are you testing with? From the base address, I guess it is
> Kirkwood?
Yes, Kirkwood. Sorry for not saying.
Andrew
^ permalink raw reply
* recommended action for bootloaders regarding modifying device-tree nodes
From: Jason Cooper @ 2014-01-30 20:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJ+vNU366GiY4k_rnh1Jf0kra+PU99w4tDdM2sNioUAJCiZqOA@mail.gmail.com>
Hi Tim,
On Thu, Jan 30, 2014 at 01:11:18AM -0800, Tim Harvey wrote:
> My approach has been to define a per-baseboard device-tree in Linux
> for a 'fully loaded' board, then remove nodes which the EEPROM claims
> are not present in the bootloader before it passes the DTB to the
> kernel. I do this by defining aliases in the device-tree for the
> peripherals that are 'optional' so that the bootloader itself does not
> need to know the details about how the device is connected.
This is more of a process question: Is there any information captured
in your EEPROM that can't be represented in the dtb? iow, at the point
when you write the EEPROM, why not write the dtb to it as configured?
You could have pre-configured dtsi fragments for each config option, and
then dynamically create the board dts from the order.
I only ask because it would solve the problem below. However, there's a
lot more to changing a manufacturing process than meets the eye. :)
> Is it more appropriate for the bootloader to 'remove' nodes for
> devices that are not physically present or should I be setting their
> status property to 'disabled' instead? I'm not clear if either option
> really has any pros or cons.
That depends on how you have it structured. Is it a valid dtb?
Meaning, do you have four nodes all at the same register address?
Perhaps you could provide an example dts?
thx,
Jason.
> Tim Harvey - Principal Software Engineer
> Gateworks Corporation
btw - one of my first embedded projects was on one of your boards. An
ixp425 with 4 mini-pci slots.
^ permalink raw reply
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