* [PATCH v2] clk: keystone: gate: fix clk_init_data initialization
From: Santosh Shilimkar @ 2014-01-31 14:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391104991-15000-1-git-send-email-ivan.khoronzhuk@ti.com>
On Thursday 30 January 2014 01:03 PM, Ivan Khoronzhuk wrote:
> The clk_init_data struct is allocated in the stack. All members of
> this struct should be initialized before using otherwise it will
> lead to unpredictable situation as it can contain garbage.
>
> Ultimately the clk->flag field contains garbage. In my case it leads
> that flag CLK_IGNORE_UNUSED is set for most of clocks. As result a
> bunch of unused clocks cannot be disabled.
>
> So initialize flags in this structure too.
>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> ---
> Based on
> git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
> keystone/master
>
> v1..v2:
> - updated commit description only
>
Thanks for the update.
> drivers/clk/keystone/gate.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/keystone/gate.c b/drivers/clk/keystone/gate.c
> index 17a5983..86f1e36 100644
> --- a/drivers/clk/keystone/gate.c
> +++ b/drivers/clk/keystone/gate.c
> @@ -179,6 +179,7 @@ static struct clk *clk_register_psc(struct device *dev,
>
> init.name = name;
> init.ops = &clk_psc_ops;
> + init.flags = 0;
> init.parent_names = (parent_name ? &parent_name : NULL);
> init.num_parents = (parent_name ? 1 : 0);
>
>
^ permalink raw reply
* [PATCH v2] ARM: keystone: dts: drop "msmcsram" clock node
From: Santosh Shilimkar @ 2014-01-31 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391105400-31602-1-git-send-email-ivan.khoronzhuk@ti.com>
On Thursday 30 January 2014 01:10 PM, Ivan Khoronzhuk wrote:
> At late init all unused clocks are disabled. So clocks that were not
> get before will be gated. In Keysone 2 SoC we have at least one
> necessary clock that is not used by any driver - "msmcsram". This
> clock is necessary, because it supplies the Multicore Shared Memory
> Controller (MSMC). MSMC is the coherency interconnect and all the
> coherent masters are connected to it including devices which are not
> under Linux OS control. MSMC clock should not be touched even in low
> power states.
>
> So drop the clock node, otherwise 'clk_ignore_unused' parameter will
> disable the clock leading to system stall.
>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> ---
> Based on
> git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
> keystone/master
>
> v1..v2:
> - dropped "msmcsram" clock node, instead disabling
> - updated comment message
>
Thanks for the update. Would be good to get blessing from DT folks.
I want to send this one during the rc's since its a bug fix.
> arch/arm/boot/dts/keystone-clocks.dtsi | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
> index 2363593..98ad488 100644
> --- a/arch/arm/boot/dts/keystone-clocks.dtsi
> +++ b/arch/arm/boot/dts/keystone-clocks.dtsi
> @@ -327,16 +327,6 @@ clocks {
> domain-id = <6>;
> };
>
> - clkmsmcsram: clkmsmcsram {
> - #clock-cells = <0>;
> - compatible = "ti,keystone,psc-clock";
> - clocks = <&chipclk1>;
> - clock-output-names = "msmcsram";
> - reg = <0x02350038 0xb00>, <0x0235001c 0x400>;
> - reg-names = "control", "domain";
> - domain-id = <7>;
> - };
> -
> clkgem0: clkgem0 {
> #clock-cells = <0>;
> compatible = "ti,keystone,psc-clock";
>
^ permalink raw reply
* [PATCH] ARM: dts: k2hk-evm: rename clock node to clocks
From: Santosh Shilimkar @ 2014-01-31 14:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391175066-13862-1-git-send-email-grygorii.strashko@ti.com>
On Friday 31 January 2014 08:31 AM, Grygorii Strashko wrote:
> Fix type in clock(s) node name: "clock"-->"clocks".
>
s/type/typo ;-)
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
> ---
No need to resend, I will fix it up while applying it
> arch/arm/boot/dts/k2hk-evm.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
> index eaefdfe..c02c3a8 100644
> --- a/arch/arm/boot/dts/k2hk-evm.dts
> +++ b/arch/arm/boot/dts/k2hk-evm.dts
> @@ -15,7 +15,7 @@
> compatible = "ti,keystone-evm";
>
> soc {
> - clock {
> + clocks {
> refclksys: refclksys {
> #clock-cells = <0>;
> compatible = "fixed-clock";
>
^ permalink raw reply
* [PATCH] usb: dwc3: keystone: switch to use runtime pm
From: Santosh Shilimkar @ 2014-01-31 14:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391174426-13773-1-git-send-email-grygorii.strashko@ti.com>
On Friday 31 January 2014 08:20 AM, Grygorii Strashko wrote:
> The Keystone PM management layer has been implemented using PM bus for
> power management clocks. As result, most of Keystone drivers don't need
> to manage clocks directly. They just need to enable runtime PM and use it
> to handle their PM state and clocks.
>
> Hence, remove clock management code and switch to use runtime PM.
>
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
> ---
Please capture why now it allowes us to remove the clock code.
Commit 8a6720e {PM / clock_ops: fix up clk prepare/unprepare count}
Without that information, the change log will be miss-leading
> drivers/usb/dwc3/dwc3-keystone.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-keystone.c b/drivers/usb/dwc3/dwc3-keystone.c
> index 1fad161..a810b41 100644
> --- a/drivers/usb/dwc3/dwc3-keystone.c
> +++ b/drivers/usb/dwc3/dwc3-keystone.c
> @@ -23,6 +23,7 @@
> #include <linux/dma-mapping.h>
> #include <linux/io.h>
> #include <linux/of_platform.h>
> +#include <linux/pm_runtime.h>
>
> /* USBSS register offsets */
> #define USBSS_REVISION 0x0000
> @@ -116,12 +117,10 @@ static int kdwc3_probe(struct platform_device *pdev)
> kdwc3_dma_mask = dma_get_mask(dev);
> dev->dma_mask = &kdwc3_dma_mask;
>
> - kdwc->clk = devm_clk_get(kdwc->dev, "usb");
> -
> - error = clk_prepare_enable(kdwc->clk);
> + pm_runtime_enable(dev);
> + error = pm_runtime_get_sync(dev);
> if (error < 0) {
> - dev_dbg(kdwc->dev, "unable to enable usb clock, err %d\n",
> - error);
> + dev_dbg(dev, "unable to enable usb dev, err %d\n", error);
> return error;
> }
>
> @@ -152,7 +151,8 @@ static int kdwc3_probe(struct platform_device *pdev)
> err_core:
> kdwc3_disable_irqs(kdwc);
> err_irq:
> - clk_disable_unprepare(kdwc->clk);
> + pm_runtime_put_sync(dev);
> + pm_runtime_disable(dev);
>
> return error;
> }
> @@ -172,7 +172,8 @@ static int kdwc3_remove(struct platform_device *pdev)
>
> kdwc3_disable_irqs(kdwc);
> device_for_each_child(&pdev->dev, NULL, kdwc3_remove_core);
> - clk_disable_unprepare(kdwc->clk);
> + pm_runtime_put_sync(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> platform_set_drvdata(pdev, NULL);
>
> return 0;
>
^ permalink raw reply
* [PATCH 09/10] watchdog: xilinx: Add missing binding
From: Michal Simek @ 2014-01-31 14:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ed4cb31c9a549343e6b492cf62fc962d39034bd0.1391177880.git.michal.simek@xilinx.com>
Document current driver binding.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
.../devicetree/bindings/watchdog/of-xilinx-wdt.txt | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt b/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
new file mode 100644
index 0000000..6d63782
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
@@ -0,0 +1,23 @@
+Xilinx AXI/PLB soft-core watchdog Device Tree Bindings
+---------------------------------------------------------
+
+Required properties:
+- compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or
+ "xlnx,xps-timebase-wdt-1.01.a".
+- reg : Physical base address and size
+
+Optional properties:
+- clock-frequency : Frequency of clock in Hz
+- xlnx,wdt-enable-once : 0 - Watchdog can be restarted
+ 1 - Watchdog can be enabled just once
+- xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,
+ <val> is integer from 8 to 31.
+
+Example:
+axi-timebase-wdt at 40100000 {
+ clock-frequency = <50000000>;
+ compatible = "xlnx,xps-timebase-wdt-1.00.a";
+ reg = <0x40100000 0x10000>;
+ xlnx,wdt-enable-once = <0x0>;
+ xlnx,wdt-interval = <0x1b>;
+} ;
--
1.8.2.3
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* [PATCH 08/10] watchdog: xilinx: Use correct comment indentation
From: Michal Simek @ 2014-01-31 14:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ed4cb31c9a549343e6b492cf62fc962d39034bd0.1391177880.git.michal.simek@xilinx.com>
No functional changes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/watchdog/of_xilinx_wdt.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index 475440a6..7948def 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -190,10 +190,10 @@ static int xwdt_probe(struct platform_device *pdev)
watchdog_set_nowayout(xilinx_wdt_wdd, true);
}
-/*
- * Twice of the 2^wdt_interval / freq because the first wdt overflow is
- * ignored (interrupt), reset is only generated at second wdt overflow
- */
+ /*
+ * Twice of the 2^wdt_interval / freq because the first wdt overflow is
+ * ignored (interrupt), reset is only generated at second wdt overflow
+ */
if (!no_timeout)
xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
pfreq);
--
1.8.2.3
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* [PATCH 07/10] watchdog: xilinx: Fix OF binding
From: Michal Simek @ 2014-01-31 14:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ed4cb31c9a549343e6b492cf62fc962d39034bd0.1391177880.git.michal.simek@xilinx.com>
Use of_property_read_u32 functions to clean OF probing.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/watchdog/of_xilinx_wdt.c | 25 ++++++++++---------------
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index c229cc4..475440a6 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -147,8 +147,7 @@ static u32 xwdt_selftest(struct xwdt_device *xdev)
static int xwdt_probe(struct platform_device *pdev)
{
int rc;
- u32 *tmptr;
- u32 *pfreq;
+ u32 pfreq, enable_once;
struct resource *res;
struct xwdt_device *xdev;
bool no_timeout = false;
@@ -168,28 +167,24 @@ static int xwdt_probe(struct platform_device *pdev)
if (IS_ERR(xdev->base))
return PTR_ERR(xdev->base);
- pfreq = (u32 *)of_get_property(pdev->dev.of_node,
- "clock-frequency", NULL);
-
- if (pfreq == NULL) {
+ rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &pfreq);
+ if (rc) {
dev_warn(&pdev->dev,
"The watchdog clock frequency cannot be obtained\n");
no_timeout = true;
}
- tmptr = (u32 *)of_get_property(pdev->dev.of_node,
- "xlnx,wdt-interval", NULL);
- if (tmptr == NULL) {
+ rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval",
+ &xdev->wdt_interval);
+ if (rc) {
dev_warn(&pdev->dev,
"Parameter \"xlnx,wdt-interval\" not found\n");
no_timeout = true;
- } else {
- xdev->wdt_interval = *tmptr;
}
- tmptr = (u32 *)of_get_property(pdev->dev.of_node,
- "xlnx,wdt-enable-once", NULL);
- if (tmptr == NULL) {
+ rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-enable-once",
+ &enable_once);
+ if (!rc && enable_once) {
dev_warn(&pdev->dev,
"Parameter \"xlnx,wdt-enable-once\" not found\n");
watchdog_set_nowayout(xilinx_wdt_wdd, true);
@@ -201,7 +196,7 @@ static int xwdt_probe(struct platform_device *pdev)
*/
if (!no_timeout)
xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
- *pfreq);
+ pfreq);
spin_lock_init(&xdev->spinlock);
watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
--
1.8.2.3
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* [PATCH 06/10] watchdog: xilinx: Fix all printk messages
From: Michal Simek @ 2014-01-31 14:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ed4cb31c9a549343e6b492cf62fc962d39034bd0.1391177880.git.michal.simek@xilinx.com>
Use dev_ functions for printk messages.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/watchdog/of_xilinx_wdt.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index d28bd3f..c229cc4 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -10,8 +10,6 @@
* 2 of the License, or (at your option) any later version.
*/
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
#include <linux/err.h>
#include <linux/module.h>
#include <linux/types.h>
@@ -42,7 +40,6 @@
#define XWT_TIMER_FAILED 0xFFFFFFFF
#define WATCHDOG_NAME "Xilinx Watchdog"
-#define PFX WATCHDOG_NAME ": "
struct xwdt_device {
void __iomem *base;
@@ -175,14 +172,16 @@ static int xwdt_probe(struct platform_device *pdev)
"clock-frequency", NULL);
if (pfreq == NULL) {
- pr_warn("The watchdog clock frequency cannot be obtained!\n");
+ dev_warn(&pdev->dev,
+ "The watchdog clock frequency cannot be obtained\n");
no_timeout = true;
}
tmptr = (u32 *)of_get_property(pdev->dev.of_node,
"xlnx,wdt-interval", NULL);
if (tmptr == NULL) {
- pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n");
+ dev_warn(&pdev->dev,
+ "Parameter \"xlnx,wdt-interval\" not found\n");
no_timeout = true;
} else {
xdev->wdt_interval = *tmptr;
@@ -191,7 +190,8 @@ static int xwdt_probe(struct platform_device *pdev)
tmptr = (u32 *)of_get_property(pdev->dev.of_node,
"xlnx,wdt-enable-once", NULL);
if (tmptr == NULL) {
- pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n");
+ dev_warn(&pdev->dev,
+ "Parameter \"xlnx,wdt-enable-once\" not found\n");
watchdog_set_nowayout(xilinx_wdt_wdd, true);
}
@@ -208,13 +208,13 @@ static int xwdt_probe(struct platform_device *pdev)
rc = xwdt_selftest(xdev);
if (rc == XWT_TIMER_FAILED) {
- pr_err("SelfTest routine error!\n");
+ dev_err(&pdev->dev, "SelfTest routine error\n");
return rc;
}
rc = watchdog_register_device(xilinx_wdt_wdd);
if (rc) {
- pr_err("cannot register watchdog (err=%d)\n", rc);
+ dev_err(&pdev->dev, "Cannot register watchdog (err=%d)\n", rc);
return rc;
}
--
1.8.2.3
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* [PATCH 05/10] watchdog: xilinx: Allocate private structure per device
From: Michal Simek @ 2014-01-31 14:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ed4cb31c9a549343e6b492cf62fc962d39034bd0.1391177880.git.michal.simek@xilinx.com>
Only one watchdog could be used by this driver.
Create driver private data structure and move there
all variables for one instance.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/watchdog/of_xilinx_wdt.c | 97 +++++++++++++++++++++++-----------------
1 file changed, 55 insertions(+), 42 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index 1f7ad91..d28bd3f 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -47,30 +47,27 @@
struct xwdt_device {
void __iomem *base;
u32 wdt_interval;
+ spinlock_t spinlock;
+ struct watchdog_device xilinx_wdt_wdd;
};
-static struct xwdt_device xdev;
-
-static u32 timeout;
-
-static DEFINE_SPINLOCK(spinlock);
-
static int xilinx_wdt_start(struct watchdog_device *wdd)
{
u32 control_status_reg;
+ struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
- spin_lock(&spinlock);
+ spin_lock(&xdev->spinlock);
/* Clean previous status and enable the watchdog timer */
- control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
+ control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
- xdev.base + XWT_TWCSR0_OFFSET);
+ xdev->base + XWT_TWCSR0_OFFSET);
- iowrite32(XWT_CSRX_EWDT2_MASK, xdev.base + XWT_TWCSR1_OFFSET);
+ iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
- spin_unlock(&spinlock);
+ spin_unlock(&xdev->spinlock);
return 0;
}
@@ -78,17 +75,18 @@ static int xilinx_wdt_start(struct watchdog_device *wdd)
static int xilinx_wdt_stop(struct watchdog_device *wdd)
{
u32 control_status_reg;
+ struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
- spin_lock(&spinlock);
+ spin_lock(&xdev->spinlock);
- control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
+ control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
- xdev.base + XWT_TWCSR0_OFFSET);
+ xdev->base + XWT_TWCSR0_OFFSET);
- iowrite32(0, xdev.base + XWT_TWCSR1_OFFSET);
+ iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
- spin_unlock(&spinlock);
+ spin_unlock(&xdev->spinlock);
pr_info("Stopped!\n");
return 0;
@@ -97,14 +95,15 @@ static int xilinx_wdt_stop(struct watchdog_device *wdd)
static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
{
u32 control_status_reg;
+ struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
- spin_lock(&spinlock);
+ spin_lock(&xdev->spinlock);
- control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
+ control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
- iowrite32(control_status_reg, xdev.base + XWT_TWCSR0_OFFSET);
+ iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
- spin_unlock(&spinlock);
+ spin_unlock(&xdev->spinlock);
return 0;
}
@@ -123,29 +122,24 @@ static const struct watchdog_ops xilinx_wdt_ops = {
.ping = xilinx_wdt_keepalive,
};
-static struct watchdog_device xilinx_wdt_wdd = {
- .info = &xilinx_wdt_ident,
- .ops = &xilinx_wdt_ops,
-};
-
-static u32 xwdt_selftest(void)
+static u32 xwdt_selftest(struct xwdt_device *xdev)
{
int i;
u32 timer_value1;
u32 timer_value2;
- spin_lock(&spinlock);
+ spin_lock(&xdev->spinlock);
- timer_value1 = ioread32(xdev.base + XWT_TBR_OFFSET);
- timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET);
+ timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
+ timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
for (i = 0;
((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
(timer_value2 == timer_value1)); i++) {
- timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET);
+ timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
}
- spin_unlock(&spinlock);
+ spin_unlock(&xdev->spinlock);
if (timer_value2 != timer_value1)
return ~XWT_TIMER_FAILED;
@@ -159,12 +153,23 @@ static int xwdt_probe(struct platform_device *pdev)
u32 *tmptr;
u32 *pfreq;
struct resource *res;
+ struct xwdt_device *xdev;
bool no_timeout = false;
+ struct watchdog_device *xilinx_wdt_wdd;
+
+ xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
+ if (!xdev)
+ return -ENOMEM;
+
+ xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
+ xilinx_wdt_wdd->info = &xilinx_wdt_ident;
+ xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
+ xilinx_wdt_wdd->parent = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- xdev.base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(xdev.base))
- return PTR_ERR(xdev.base);
+ xdev->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(xdev->base))
+ return PTR_ERR(xdev->base);
pfreq = (u32 *)of_get_property(pdev->dev.of_node,
"clock-frequency", NULL);
@@ -180,14 +185,14 @@ static int xwdt_probe(struct platform_device *pdev)
pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n");
no_timeout = true;
} else {
- xdev.wdt_interval = *tmptr;
+ xdev->wdt_interval = *tmptr;
}
tmptr = (u32 *)of_get_property(pdev->dev.of_node,
"xlnx,wdt-enable-once", NULL);
if (tmptr == NULL) {
pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n");
- watchdog_set_nowayout(&xilinx_wdt_wdd, true);
+ watchdog_set_nowayout(xilinx_wdt_wdd, true);
}
/*
@@ -195,29 +200,37 @@ static int xwdt_probe(struct platform_device *pdev)
* ignored (interrupt), reset is only generated at second wdt overflow
*/
if (!no_timeout)
- timeout = 2 * ((1<<xdev.wdt_interval) / *pfreq);
+ xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
+ *pfreq);
+
+ spin_lock_init(&xdev->spinlock);
+ watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
- rc = xwdt_selftest();
+ rc = xwdt_selftest(xdev);
if (rc == XWT_TIMER_FAILED) {
pr_err("SelfTest routine error!\n");
return rc;
}
- rc = watchdog_register_device(&xilinx_wdt_wdd);
+ rc = watchdog_register_device(xilinx_wdt_wdd);
if (rc) {
pr_err("cannot register watchdog (err=%d)\n", rc);
return rc;
}
dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
- xdev.base, timeout);
+ xdev->base, xilinx_wdt_wdd->timeout);
+
+ platform_set_drvdata(pdev, xdev);
return 0;
}
-static int xwdt_remove(struct platform_device *dev)
+static int xwdt_remove(struct platform_device *pdev)
{
- watchdog_unregister_device(&xilinx_wdt_wdd);
+ struct xwdt_device *xdev = platform_get_drvdata(pdev);
+
+ watchdog_unregister_device(&xdev->xilinx_wdt_wdd);
return 0;
}
--
1.8.2.3
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* [PATCH 04/10] watchdog: xilinx: Move no_timeout to probe function
From: Michal Simek @ 2014-01-31 14:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ed4cb31c9a549343e6b492cf62fc962d39034bd0.1391177880.git.michal.simek@xilinx.com>
no_timeout should be local variable because it is used
only in probe function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/watchdog/of_xilinx_wdt.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index 7f371ed..1f7ad91 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -52,7 +52,6 @@ struct xwdt_device {
static struct xwdt_device xdev;
static u32 timeout;
-static u8 no_timeout;
static DEFINE_SPINLOCK(spinlock);
@@ -160,8 +159,7 @@ static int xwdt_probe(struct platform_device *pdev)
u32 *tmptr;
u32 *pfreq;
struct resource *res;
-
- no_timeout = 0;
+ bool no_timeout = false;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
xdev.base = devm_ioremap_resource(&pdev->dev, res);
@@ -173,14 +171,14 @@ static int xwdt_probe(struct platform_device *pdev)
if (pfreq == NULL) {
pr_warn("The watchdog clock frequency cannot be obtained!\n");
- no_timeout = 1;
+ no_timeout = true;
}
tmptr = (u32 *)of_get_property(pdev->dev.of_node,
"xlnx,wdt-interval", NULL);
if (tmptr == NULL) {
pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n");
- no_timeout = 1;
+ no_timeout = true;
} else {
xdev.wdt_interval = *tmptr;
}
--
1.8.2.3
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* [PATCH 03/10] watchdog: xilinx: Simplify probe and remove functions
From: Michal Simek @ 2014-01-31 14:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ed4cb31c9a549343e6b492cf62fc962d39034bd0.1391177880.git.michal.simek@xilinx.com>
Use devm_ helper function to simplify probe and error path.
Move ioremap to the beginning of probe function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/watchdog/of_xilinx_wdt.c | 41 +++++++++-------------------------------
1 file changed, 9 insertions(+), 32 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index aca9bab..7f371ed 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -12,6 +12,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include <linux/err.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
@@ -44,7 +45,6 @@
#define PFX WATCHDOG_NAME ": "
struct xwdt_device {
- struct resource res;
void __iomem *base;
u32 wdt_interval;
};
@@ -159,9 +159,15 @@ static int xwdt_probe(struct platform_device *pdev)
int rc;
u32 *tmptr;
u32 *pfreq;
+ struct resource *res;
no_timeout = 0;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ xdev.base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(xdev.base))
+ return PTR_ERR(xdev.base);
+
pfreq = (u32 *)of_get_property(pdev->dev.of_node,
"clock-frequency", NULL);
@@ -170,12 +176,6 @@ static int xwdt_probe(struct platform_device *pdev)
no_timeout = 1;
}
- rc = of_address_to_resource(pdev->dev.of_node, 0, &xdev.res);
- if (rc) {
- pr_warn("invalid address!\n");
- return rc;
- }
-
tmptr = (u32 *)of_get_property(pdev->dev.of_node,
"xlnx,wdt-interval", NULL);
if (tmptr == NULL) {
@@ -199,50 +199,27 @@ static int xwdt_probe(struct platform_device *pdev)
if (!no_timeout)
timeout = 2 * ((1<<xdev.wdt_interval) / *pfreq);
- if (!request_mem_region(xdev.res.start,
- xdev.res.end - xdev.res.start + 1, WATCHDOG_NAME)) {
- rc = -ENXIO;
- pr_err("memory request failure!\n");
- goto err_out;
- }
-
- xdev.base = ioremap(xdev.res.start, xdev.res.end - xdev.res.start + 1);
- if (xdev.base == NULL) {
- rc = -ENOMEM;
- pr_err("ioremap failure!\n");
- goto release_mem;
- }
-
rc = xwdt_selftest();
if (rc == XWT_TIMER_FAILED) {
pr_err("SelfTest routine error!\n");
- goto unmap_io;
+ return rc;
}
rc = watchdog_register_device(&xilinx_wdt_wdd);
if (rc) {
pr_err("cannot register watchdog (err=%d)\n", rc);
- goto unmap_io;
+ return rc;
}
dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
xdev.base, timeout);
return 0;
-
-unmap_io:
- iounmap(xdev.base);
-release_mem:
- release_mem_region(xdev.res.start, resource_size(&xdev.res));
-err_out:
- return rc;
}
static int xwdt_remove(struct platform_device *dev)
{
watchdog_unregister_device(&xilinx_wdt_wdd);
- iounmap(xdev.base);
- release_mem_region(xdev.res.start, resource_size(&xdev.res));
return 0;
}
--
1.8.2.3
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* [PATCH 02/10] watchdog: xilinx: Move control_status_reg to functions
From: Michal Simek @ 2014-01-31 14:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ed4cb31c9a549343e6b492cf62fc962d39034bd0.1391177880.git.michal.simek@xilinx.com>
control_status_reg is temp variables and should be
used locally by specific function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/watchdog/of_xilinx_wdt.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index 8c2814e..aca9bab 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -52,13 +52,14 @@ struct xwdt_device {
static struct xwdt_device xdev;
static u32 timeout;
-static u32 control_status_reg;
static u8 no_timeout;
static DEFINE_SPINLOCK(spinlock);
static int xilinx_wdt_start(struct watchdog_device *wdd)
{
+ u32 control_status_reg;
+
spin_lock(&spinlock);
/* Clean previous status and enable the watchdog timer */
@@ -77,6 +78,8 @@ static int xilinx_wdt_start(struct watchdog_device *wdd)
static int xilinx_wdt_stop(struct watchdog_device *wdd)
{
+ u32 control_status_reg;
+
spin_lock(&spinlock);
control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
@@ -94,6 +97,8 @@ static int xilinx_wdt_stop(struct watchdog_device *wdd)
static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
{
+ u32 control_status_reg;
+
spin_lock(&spinlock);
control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
--
1.8.2.3
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* [PATCH 01/10] watchdog: xilinx: Convert driver to the watchdog framework
From: Michal Simek @ 2014-01-31 14:18 UTC (permalink / raw)
To: linux-arm-kernel
- Remove uneeded headers, fops functions
- Use xilinx_wdt prefix in start/stop/keepalive functions
and in new structures
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/watchdog/Kconfig | 1 +
drivers/watchdog/of_xilinx_wdt.c | 204 ++++++---------------------------------
2 files changed, 33 insertions(+), 172 deletions(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 4c4c566..9db5d3c 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1025,6 +1025,7 @@ config M54xx_WATCHDOG
config XILINX_WATCHDOG
tristate "Xilinx Watchdog timer"
depends on MICROBLAZE
+ select WATCHDOG_CORE
---help---
Watchdog driver for the xps_timebase_wdt ip core.
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index fb57103..8c2814e 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -1,6 +1,7 @@
/*
* Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc.
* (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
*
* This program is free software; you can redistribute it and/or
@@ -14,13 +15,10 @@
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/watchdog.h>
#include <linux/io.h>
-#include <linux/uaccess.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
@@ -48,22 +46,18 @@
struct xwdt_device {
struct resource res;
void __iomem *base;
- u32 nowayout;
u32 wdt_interval;
- u32 boot_status;
};
static struct xwdt_device xdev;
static u32 timeout;
static u32 control_status_reg;
-static u8 expect_close;
static u8 no_timeout;
-static unsigned long driver_open;
static DEFINE_SPINLOCK(spinlock);
-static void xwdt_start(void)
+static int xilinx_wdt_start(struct watchdog_device *wdd)
{
spin_lock(&spinlock);
@@ -77,9 +71,11 @@ static void xwdt_start(void)
iowrite32(XWT_CSRX_EWDT2_MASK, xdev.base + XWT_TWCSR1_OFFSET);
spin_unlock(&spinlock);
+
+ return 0;
}
-static void xwdt_stop(void)
+static int xilinx_wdt_stop(struct watchdog_device *wdd)
{
spin_lock(&spinlock);
@@ -92,9 +88,11 @@ static void xwdt_stop(void)
spin_unlock(&spinlock);
pr_info("Stopped!\n");
+
+ return 0;
}
-static void xwdt_keepalive(void)
+static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
{
spin_lock(&spinlock);
@@ -103,23 +101,28 @@ static void xwdt_keepalive(void)
iowrite32(control_status_reg, xdev.base + XWT_TWCSR0_OFFSET);
spin_unlock(&spinlock);
-}
-static void xwdt_get_status(int *status)
-{
- int new_status;
+ return 0;
+}
- spin_lock(&spinlock);
+static const struct watchdog_info xilinx_wdt_ident = {
+ .options = WDIOF_MAGICCLOSE |
+ WDIOF_KEEPALIVEPING,
+ .firmware_version = 1,
+ .identity = WATCHDOG_NAME,
+};
- control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
- new_status = ((control_status_reg &
- (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK)) != 0);
- spin_unlock(&spinlock);
+static const struct watchdog_ops xilinx_wdt_ops = {
+ .owner = THIS_MODULE,
+ .start = xilinx_wdt_start,
+ .stop = xilinx_wdt_stop,
+ .ping = xilinx_wdt_keepalive,
+};
- *status = 0;
- if (new_status & 1)
- *status |= WDIOF_CARDRESET;
-}
+static struct watchdog_device xilinx_wdt_wdd = {
+ .info = &xilinx_wdt_ident,
+ .ops = &xilinx_wdt_ops,
+};
static u32 xwdt_selftest(void)
{
@@ -146,139 +149,6 @@ static u32 xwdt_selftest(void)
return XWT_TIMER_FAILED;
}
-static int xwdt_open(struct inode *inode, struct file *file)
-{
- /* Only one process can handle the wdt at a time */
- if (test_and_set_bit(0, &driver_open))
- return -EBUSY;
-
- /* Make sure that the module are always loaded...*/
- if (xdev.nowayout)
- __module_get(THIS_MODULE);
-
- xwdt_start();
- pr_info("Started...\n");
-
- return nonseekable_open(inode, file);
-}
-
-static int xwdt_release(struct inode *inode, struct file *file)
-{
- if (expect_close == 42) {
- xwdt_stop();
- } else {
- pr_crit("Unexpected close, not stopping watchdog!\n");
- xwdt_keepalive();
- }
-
- clear_bit(0, &driver_open);
- expect_close = 0;
- return 0;
-}
-
-/*
- * xwdt_write:
- * @file: file handle to the watchdog
- * @buf: buffer to write (unused as data does not matter here
- * @count: count of bytes
- * @ppos: pointer to the position to write. No seeks allowed
- *
- * A write to a watchdog device is defined as a keepalive signal. Any
- * write of data will do, as we don't define content meaning.
- */
-static ssize_t xwdt_write(struct file *file, const char __user *buf,
- size_t len, loff_t *ppos)
-{
- if (len) {
- if (!xdev.nowayout) {
- size_t i;
-
- /* In case it was set long ago */
- expect_close = 0;
-
- for (i = 0; i != len; i++) {
- char c;
-
- if (get_user(c, buf + i))
- return -EFAULT;
- if (c == 'V')
- expect_close = 42;
- }
- }
- xwdt_keepalive();
- }
- return len;
-}
-
-static const struct watchdog_info ident = {
- .options = WDIOF_MAGICCLOSE |
- WDIOF_KEEPALIVEPING,
- .firmware_version = 1,
- .identity = WATCHDOG_NAME,
-};
-
-/*
- * xwdt_ioctl:
- * @file: file handle to the device
- * @cmd: watchdog command
- * @arg: argument pointer
- *
- * The watchdog API defines a common set of functions for all watchdogs
- * according to their available features.
- */
-static long xwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- int status;
-
- union {
- struct watchdog_info __user *ident;
- int __user *i;
- } uarg;
-
- uarg.i = (int __user *)arg;
-
- switch (cmd) {
- case WDIOC_GETSUPPORT:
- return copy_to_user(uarg.ident, &ident,
- sizeof(ident)) ? -EFAULT : 0;
-
- case WDIOC_GETBOOTSTATUS:
- return put_user(xdev.boot_status, uarg.i);
-
- case WDIOC_GETSTATUS:
- xwdt_get_status(&status);
- return put_user(status, uarg.i);
-
- case WDIOC_KEEPALIVE:
- xwdt_keepalive();
- return 0;
-
- case WDIOC_GETTIMEOUT:
- if (no_timeout)
- return -ENOTTY;
- else
- return put_user(timeout, uarg.i);
-
- default:
- return -ENOTTY;
- }
-}
-
-static const struct file_operations xwdt_fops = {
- .owner = THIS_MODULE,
- .llseek = no_llseek,
- .write = xwdt_write,
- .open = xwdt_open,
- .release = xwdt_release,
- .unlocked_ioctl = xwdt_ioctl,
-};
-
-static struct miscdevice xwdt_miscdev = {
- .minor = WATCHDOG_MINOR,
- .name = "watchdog",
- .fops = &xwdt_fops,
-};
-
static int xwdt_probe(struct platform_device *pdev)
{
int rc;
@@ -314,7 +184,7 @@ static int xwdt_probe(struct platform_device *pdev)
"xlnx,wdt-enable-once", NULL);
if (tmptr == NULL) {
pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n");
- xdev.nowayout = WATCHDOG_NOWAYOUT;
+ watchdog_set_nowayout(&xilinx_wdt_wdd, true);
}
/*
@@ -344,24 +214,14 @@ static int xwdt_probe(struct platform_device *pdev)
goto unmap_io;
}
- xwdt_get_status(&xdev.boot_status);
-
- rc = misc_register(&xwdt_miscdev);
+ rc = watchdog_register_device(&xilinx_wdt_wdd);
if (rc) {
- pr_err("cannot register miscdev on minor=%d (err=%d)\n",
- xwdt_miscdev.minor, rc);
+ pr_err("cannot register watchdog (err=%d)\n", rc);
goto unmap_io;
}
- if (no_timeout)
- pr_info("driver loaded (timeout=? sec, nowayout=%d)\n",
- xdev.nowayout);
- else
- pr_info("driver loaded (timeout=%d sec, nowayout=%d)\n",
- timeout, xdev.nowayout);
-
- expect_close = 0;
- clear_bit(0, &driver_open);
+ dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
+ xdev.base, timeout);
return 0;
@@ -375,7 +235,7 @@ err_out:
static int xwdt_remove(struct platform_device *dev)
{
- misc_deregister(&xwdt_miscdev);
+ watchdog_unregister_device(&xilinx_wdt_wdd);
iounmap(xdev.base);
release_mem_region(xdev.res.start, resource_size(&xdev.res));
--
1.8.2.3
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^ permalink raw reply related
* [PATCH] ARM: dts: k2hk-evm: rename clock node to clocks
From: Sergei Shtylyov @ 2014-01-31 14:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391175066-13862-1-git-send-email-grygorii.strashko@ti.com>
Hello.
On 31-01-2014 17:31, Grygorii Strashko wrote:
> Fix type in clock(s) node name: "clock"-->"clocks".
Maybe "typo"? :-)
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
WBR, Sergei
^ permalink raw reply
* [PATCH v5 14/14] ARM: sun7i: dts: Add ahci / sata support
From: Maxime Ripard @ 2014-01-31 13:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390417489-5354-15-git-send-email-hdegoede@redhat.com>
On Wed, Jan 22, 2014 at 08:04:49PM +0100, Hans de Goede wrote:
> This patch adds sunxi sata support to A20 boards that have such a connector.
> Some boards also feature a regulator via a GPIO and support for this is also
> added.
>
> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 6 ++++++
> arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 20 ++++++++++++++++++++
> arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 6 ++++++
> arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
> 4 files changed, 40 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> index 48777cd..1cab521 100644
> --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> @@ -13,6 +13,7 @@
>
> /dts-v1/;
> /include/ "sun7i-a20.dtsi"
> +/include/ "sunxi-ahci-reg.dtsi"
>
> / {
> model = "Cubietech Cubieboard2";
> @@ -28,6 +29,11 @@
> status = "okay";
> };
>
> + ahci: sata at 01c18000 {
> + target-supply = <®_ahci_5v>;
> + status = "okay";
> + };
> +
> pinctrl at 01c20800 {
> mmc0_cd_pin_cubieboard2: mmc0_cd_pin at 0 {
> allwinner,pins = "PH1";
> diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> index 2684f27..1247ea1 100644
> --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> @@ -13,6 +13,7 @@
>
> /dts-v1/;
> /include/ "sun7i-a20.dtsi"
> +/include/ "sunxi-ahci-reg.dtsi"
>
> / {
> model = "Cubietech Cubietruck";
> @@ -28,6 +29,11 @@
> status = "okay";
> };
>
> + ahci: sata at 01c18000 {
> + target-supply = <®_ahci_5v>;
> + status = "okay";
> + };
> +
> pinctrl at 01c20800 {
> mmc0_cd_pin_cubietruck: mmc0_cd_pin at 0 {
> allwinner,pins = "PH1";
> @@ -36,6 +42,13 @@
> allwinner,pull = <0>;
> };
>
> + ahci_pwr_pin_cubietruck: ahci_pwr_pin at 1 {
> + allwinner,pins = "PH12";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> led_pins_cubietruck: led_pins at 0 {
> allwinner,pins = "PH7", "PH11", "PH20", "PH21";
> allwinner,function = "gpio_out";
> @@ -84,4 +97,11 @@
> gpios = <&pio 7 7 0>;
> };
> };
> +
> + regulators {
> + reg_ahci_5v: ahci-5v {
> + pinctrl-0 = <&ahci_pwr_pin_cubietruck>;
> + gpio = <&pio 7 12 0>;
> + };
> + };
> };
> diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
> index bf6f6c8..f135886 100644
> --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
> @@ -13,6 +13,7 @@
>
> /dts-v1/;
> /include/ "sun7i-a20.dtsi"
> +/include/ "sunxi-ahci-reg.dtsi"
>
> / {
> model = "Olimex A20-Olinuxino Micro";
> @@ -37,6 +38,11 @@
> status = "okay";
> };
>
> + ahci: sata at 01c18000 {
> + target-supply = <®_ahci_5v>;
> + status = "okay";
> + };
> +
> pinctrl at 01c20800 {
> mmc0_cd_pin_olinuxinom: mmc0_cd_pin at 0 {
> allwinner,pins = "PH1";
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index c9c123a..0657bad 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -347,6 +347,14 @@
> status = "disabled";
> };
>
> + ahci: sata at 01c18000 {
> + compatible = "allwinner,sun4i-a10-ahci";
> + reg = <0x01c18000 0x1000>;
> + interrupts = <0 56 1>;
This is supposed to be a level triggered interrupt, not an edge
triggered one.
Thanks for your work!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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* [PATCH v5 13/14] ARM: sun4i: dts: Add ahci / sata support
From: Maxime Ripard @ 2014-01-31 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390417489-5354-14-git-send-email-hdegoede@redhat.com>
Hi Hans,
On Wed, Jan 22, 2014 at 08:04:48PM +0100, Hans de Goede wrote:
> From: Oliver Schinagl <oliver@schinagl.nl>
>
> This patch adds sunxi sata support to A10 boards that have such a connector.
> Some boards also feature a regulator via a GPIO and support for this is also
> added.
>
> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> arch/arm/boot/dts/sun4i-a10-a1000.dts | 4 ++++
> arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 6 +++++
> arch/arm/boot/dts/sun4i-a10.dtsi | 8 +++++++
> arch/arm/boot/dts/sunxi-ahci-reg.dtsi | 38 ++++++++++++++++++++++++++++++
I'm still half convinced about this at the moment, given the number of
platforms we support, we can always change it back if things become too messy.
> 4 files changed, 56 insertions(+)
> create mode 100644 arch/arm/boot/dts/sunxi-ahci-reg.dtsi
>
> diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
> index aef8207..3fb7305 100644
> --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
> @@ -48,6 +48,10 @@
> status = "okay";
> };
>
> + ahci: sata at 01c18000 {
> + status = "okay";
> + };
> +
> pinctrl at 01c20800 {
> mmc0_cd_pin_a1000: mmc0_cd_pin at 0 {
> allwinner,pins = "PH1";
> diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> index f50fb2b..6ae1110 100644
> --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> @@ -12,6 +12,7 @@
>
> /dts-v1/;
> /include/ "sun4i-a10.dtsi"
> +/include/ "sunxi-ahci-reg.dtsi"
>
> / {
> model = "Cubietech Cubieboard";
> @@ -51,6 +52,11 @@
> status = "okay";
> };
>
> + ahci: sata at 01c18000 {
> + target-supply = <®_ahci_5v>;
> + status = "okay";
> + };
> +
> pinctrl at 01c20800 {
> mmc0_cd_pin_cubieboard: mmc0_cd_pin at 0 {
> allwinner,pins = "PH1";
> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
> index 4736dd2..198dcda 100644
> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> @@ -331,6 +331,14 @@
> status = "disabled";
> };
>
> + ahci: sata at 01c18000 {
> + compatible = "allwinner,sun4i-a10-ahci";
To be consistent with the rest of the sun4i devices compatible, It
should be sun4i-ahci.
However, since these devices don't use the same compatible pattern as
their own machine compatible, and are consisent with the rest of the
compatibles for the other SoCs, we can probably make this a go to
transition progressively to this pattern.
I'll cook up some patches for the other devices.
> + reg = <0x01c18000 0x1000>;
> + interrupts = <56>;
> + clocks = <&pll6 0>, <&ahb_gates 25>;
> + status = "disabled";
> + };
> +
> intc: interrupt-controller at 01c20400 {
> compatible = "allwinner,sun4i-ic";
> reg = <0x01c20400 0x400>;
> diff --git a/arch/arm/boot/dts/sunxi-ahci-reg.dtsi b/arch/arm/boot/dts/sunxi-ahci-reg.dtsi
> new file mode 100644
> index 0000000..955b197
> --- /dev/null
> +++ b/arch/arm/boot/dts/sunxi-ahci-reg.dtsi
> @@ -0,0 +1,38 @@
> +/*
> + * sunxi boards sata target power supply common code
> + *
> + * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/ {
> + soc at 01c00000 {
> + ahci_pwr_pin_a: ahci_pwr_pin at 0 {
> + allwinner,pins = "PB8";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
This should be under the pinctrl node.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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* [PATCH 0/3] spi: core: Introduce devm_spi_alloc_master
From: Maxime Ripard @ 2014-01-31 13:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140131121215.GB22609@sirena.org.uk>
On Fri, Jan 31, 2014 at 12:12:15PM +0000, Mark Brown wrote:
> On Fri, Jan 31, 2014 at 11:23:09AM +0100, Maxime Ripard wrote:
>
> > This patchset introduces a devm_spi_alloc_master to the spi core. While most of
> > the drivers have a spi_master_put call in the probe, a lot of them using the
> > devm_spi_register_master function are missing it in the remove function,
> > leading to leaked resources.
>
> This seems confusing - the idea here is that if we've handed the device
> off to the managed function then the managed function deals with
> destroying it. Note that spi_alloc_master() says that the put is only
> required after errors adding the device (which would be the expected
> behaviour if you look at other APIs). Looking at the code I think there
> is an issue here but I'm not at all clear that this is the best fix.
Ah, right, spi_master_put doesn't free the memory either...
I guess we have a few choices here, either:
- Add a devm_kzalloc to spi_alloc_master, since most of the drivers
I've been looking at fail to free the memory, this would be the
least intrusive solution. We'd still have to remove all the kfree
calls in the driver that rightfully free the memory.
- Make devm_unregister_master also call kfree on the master
- Add a kfree to my devm_put_master so that the memory is reclaimed,
which isn't the case for now.
I don't have a strong preference here, maybe for the third one, since
it makes obvious that it's managed and you don't have to do anything
about it, while the other do not.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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* [PATCH] ARM: dts: k2hk-evm: rename clock node to clocks
From: Grygorii Strashko @ 2014-01-31 13:31 UTC (permalink / raw)
To: linux-arm-kernel
Fix type in clock(s) node name: "clock"-->"clocks".
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
---
arch/arm/boot/dts/k2hk-evm.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
index eaefdfe..c02c3a8 100644
--- a/arch/arm/boot/dts/k2hk-evm.dts
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -15,7 +15,7 @@
compatible = "ti,keystone-evm";
soc {
- clock {
+ clocks {
refclksys: refclksys {
#clock-cells = <0>;
compatible = "fixed-clock";
--
1.7.9.5
^ permalink raw reply related
* [PATCH] usb: dwc3: keystone: switch to use runtime pm
From: Grygorii Strashko @ 2014-01-31 13:20 UTC (permalink / raw)
To: linux-arm-kernel
The Keystone PM management layer has been implemented using PM bus for
power management clocks. As result, most of Keystone drivers don't need
to manage clocks directly. They just need to enable runtime PM and use it
to handle their PM state and clocks.
Hence, remove clock management code and switch to use runtime PM.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
---
drivers/usb/dwc3/dwc3-keystone.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-keystone.c b/drivers/usb/dwc3/dwc3-keystone.c
index 1fad161..a810b41 100644
--- a/drivers/usb/dwc3/dwc3-keystone.c
+++ b/drivers/usb/dwc3/dwc3-keystone.c
@@ -23,6 +23,7 @@
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
/* USBSS register offsets */
#define USBSS_REVISION 0x0000
@@ -116,12 +117,10 @@ static int kdwc3_probe(struct platform_device *pdev)
kdwc3_dma_mask = dma_get_mask(dev);
dev->dma_mask = &kdwc3_dma_mask;
- kdwc->clk = devm_clk_get(kdwc->dev, "usb");
-
- error = clk_prepare_enable(kdwc->clk);
+ pm_runtime_enable(dev);
+ error = pm_runtime_get_sync(dev);
if (error < 0) {
- dev_dbg(kdwc->dev, "unable to enable usb clock, err %d\n",
- error);
+ dev_dbg(dev, "unable to enable usb dev, err %d\n", error);
return error;
}
@@ -152,7 +151,8 @@ static int kdwc3_probe(struct platform_device *pdev)
err_core:
kdwc3_disable_irqs(kdwc);
err_irq:
- clk_disable_unprepare(kdwc->clk);
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
return error;
}
@@ -172,7 +172,8 @@ static int kdwc3_remove(struct platform_device *pdev)
kdwc3_disable_irqs(kdwc);
device_for_each_child(&pdev->dev, NULL, kdwc3_remove_core);
- clk_disable_unprepare(kdwc->clk);
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
platform_set_drvdata(pdev, NULL);
return 0;
--
1.7.9.5
^ permalink raw reply related
* [PATCH 4/4] ARM: dts: add B2112 board support
From: srinivas kandagatla @ 2014-01-31 12:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391093744-19905-5-git-send-email-patrice.chotard@st.com>
On 30/01/14 14:55, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <alexandre.torgue@st.com>
>
> Add support for B2112 board based on STiD127 SoC.
>
> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
> ---
> arch/arm/boot/dts/Makefile | 3 ++-
> arch/arm/boot/dts/stid127-b2112.dts | 35 +++++++++++++++++++++++++++++++++++
> 2 files changed, 37 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/stid127-b2112.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index d57c1a6..7173dca 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -247,7 +247,8 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
> dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
> stih416-b2000.dtb \
> stih415-b2020.dtb \
> - stih416-b2020.dtb
> + stih416-b2020.dtb \
> + stid127-b2112.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += \
> sun4i-a10-a1000.dtb \
> sun4i-a10-cubieboard.dtb \
> diff --git a/arch/arm/boot/dts/stid127-b2112.dts b/arch/arm/boot/dts/stid127-b2112.dts
> new file mode 100644
> index 0000000..b4507e3
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127-b2112.dts
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright (C) 2013 STMicroelectronics Limited.
2014
> + * Author: Alexandre Torgue <alexandre.torgue@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
s/publishhed/published/
> + */
> +/dts-v1/;
> +#include "stid127.dtsi"
> +
> +/ {
> + model = "STiD127 B2112 Board";
> + compatible = "st,stid127", "st,stid127-b2112";
> +
> + memory{
> + device_type = "memory";
> + reg = <0x40000000 0x10000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyAS0,115200";
> + linux,stdout-path = &uart2;
> + };
> +
> + aliases {
> + ttyAS0 = &uart2;
> + };
> +
> + soc {
> + uart2: serial at fe532000{
> + status = "okay";
> + };
> + };
> +};
>
^ permalink raw reply
* [PATCH 3/4] ARM: dts: Add support of STid127 Soc.
From: srinivas kandagatla @ 2014-01-31 12:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391093744-19905-4-git-send-email-patrice.chotard@st.com>
Hi Patrice,
On 30/01/14 14:55, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <alexandre.torgue@st.com>
>
> The STid127 integrates all harware components to function as a cable modem
s/harware/hardware/
s/STid127/STiD127
Please fix other instances too.
> or, in combination with a back end device, as a Gateway set top boxe.
s/boxe/box/
>
> Supported devices:
> -UART0
> -UART2
>
> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> ---
> arch/arm/boot/dts/stid127-clock.dtsi | 31 ++++
> arch/arm/boot/dts/stid127-pinctrl.dtsi | 245 ++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/stid127.dtsi | 130 +++++++++++++++++
> 3 files changed, 406 insertions(+)
> create mode 100644 arch/arm/boot/dts/stid127-clock.dtsi
> create mode 100644 arch/arm/boot/dts/stid127-pinctrl.dtsi
> create mode 100644 arch/arm/boot/dts/stid127.dtsi
>
> diff --git a/arch/arm/boot/dts/stid127-clock.dtsi b/arch/arm/boot/dts/stid127-clock.dtsi
> new file mode 100644
> index 0000000..c6cafa9
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127-clock.dtsi
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited
2014
> + * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
> + * Alexandre Torgue <alexandre.torgue@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +/ {Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
> + clocks {
> + /*
> + * ARM Peripheral clock for timers
> + */
> + arm_periph_clk: arm_periph_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <100000000>;
> + };
> + /*
> + * Bootloader initialized system infrastructure clock for
> + * serial devices.
> + */
> + CLK_IC_LP_HD: clockgenA0 at 29 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <100000000>;
> + clock-output-names = "CLK_IC_LP_HD";
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/stid127-pinctrl.dtsi b/arch/arm/boot/dts/stid127-pinctrl.dtsi
> new file mode 100644
> index 0000000..3fa66f3
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127-pinctrl.dtsi
> @@ -0,0 +1,245 @@
> +/*
> + * Copyright (C) 2012 STMicroelectronics Limited.
2014
> + * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
> + * Alexandre Torgue <alexandre.torgue@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
s/publishhed/published/
> + */
> +#include "st-pincfg.h"
> +/ {
> + aliases {
> + gpio0 = &PIO0;
> + gpio1 = &PIO1;
> + gpio2 = &PIO2;
> + gpio3 = &PIO3;
> + gpio4 = &PIO4;
> + gpio5 = &PIO5;
> + gpio6 = &PIO6;
> + gpio7 = &PIO7;
> + gpio8 = &PIO8;
> + gpio9 = &PIO9;
> + gpio10 = &PIO10;
> + gpio11 = &PIO11;
> + gpio12 = &PIO12;
> + gpio13 = &PIO13;
> + gpio14 = &PIO14;
> + gpio15 = &PIO15;
> + gpio16 = &PIO16;
> + gpio17 = &PIO17;
> + gpio18 = &PIO18;
> + gpio19 = &PIO19;
> + gpio20 = &PIO20;
> + gpio21 = &PIO21;
> + gpio22 = &PIO22;
> +
> + };
> +
> + soc {
> + pin-controller-pwest {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "st,stid127-pwest-pinctrl";
> + st,syscfg = <&syscfg_pwest>;
> + ranges = <0 0xfebe0000 0x8000>;
Can you add interrupt controller support to the pin controller.
Patches are in : https://lkml.org/lkml/2014/1/16/342
All these patches are due to be in v3.15.
> +
> + PIO0: gpio at febe0000 {
> + gpio-controller;
> + #gpio-cells = <1>;
> + reg = <0 0x100>;
> + interrupts = <0 149 0>;
> + st,bank-name = "PIO0";
> + };
> + rx = <&PIO3 0 ALT2 IN>;
> + };
> + };
> + };
> +
> + };
unnecessary empty line here.
> diff --git a/arch/arm/boot/dts/stid127.dtsi b/arch/arm/boot/dts/stid127.dtsi
> new file mode 100644
> index 0000000..a6f0b8fe
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127.dtsi
> @@ -0,0 +1,130 @@
> +/*
> + * Copyright (C) 2013 STMicroelectronics Limited.
2014
> + * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
> + * Alexandre Torgue <alexandre.torgue@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
s/publishhed/published/
> + */
> +#include "stid127-pinctrl.dtsi"
> +#include "stid127-clock.dtsi"
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <0>;
> + };
> + cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <1>;
> + };
> + };
> +
> + intc: interrupt-controller at fffe1000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0xfffe1000 0x1000>,
> + <0xfffe0100 0x100>;
> + };
> +
> + scu at fffe0000 {
> + compatible = "arm,cortex-a9-scu";
> + reg = <0xfffe0000 0x1000>;
> + };
> +
> + timer at fffe0200 {
> + interrupt-parent = <&intc>;
> + compatible = "arm,cortex-a9-global-timer";
> + reg = <0xfffe0200 0x100>;
> + interrupts = <1 11 0x04>;
> + clocks = <&arm_periph_clk>;
Fix the tab spacing here.
Thanks,
srini
>
^ permalink raw reply
* [PATCH v3 3/5] spi: sunxi: Add Allwinner A31 SPI controller driver
From: Mark Brown @ 2014-01-31 12:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391165752-1819-4-git-send-email-maxime.ripard@free-electrons.com>
On Fri, Jan 31, 2014 at 11:55:50AM +0100, Maxime Ripard wrote:
> + master = devm_spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
> + if (!master) {
> + dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
> + return -ENOMEM;
> + }
This now depends on your other series which as I said doesn't look like
the best approach.
> + pm_runtime_enable(&pdev->dev);
> + if (!pm_runtime_enabled(&pdev->dev)) {
> + ret = sun6i_spi_runtime_resume(&pdev->dev);
> + if (ret) {
> + dev_err(&pdev->dev, "Couldn't resume the device\n");
> + return ret;
> + }
> + }
No, as discussed don't do this - notice how other drivers aren't written
this way either. Like I said leave the device powered on startup and
then let it be idled by runtime PM.
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^ permalink raw reply
* Extending OPP bindings
From: Lorenzo Pieralisi @ 2014-01-31 12:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52EAF1CA.3040702@ti.com>
Hi Nishanth,
On Fri, Jan 31, 2014 at 12:43:54AM +0000, Nishanth Menon wrote:
> Hi Sudeep,
>
> On 01/30/2014 07:43 AM, Sudeep Holla wrote:
>
> >
> > I am looking into a couple shortcomings in the current OPP bindings and
> > how to address them. Feel free to add to the list if you think of any more
> > issues that needs to be addressed or if and how any problem mentioned below
> > can be handled with the existing bindings.
> >
> > 1. indexing: currently there are no indices in the operating-points.
> indexing is based on frequency which is why the accessors use
> frequency to pull out the OPP data.
>
> indexing is a horrible idea - on platforms where OPP may be disabled
> or enabled for various reasons(see arch/arm/mach-imx/mach-imx6q.c,
> arch/arm/mach-omap2/board-omap3beagle.c etc) - the indexing you see in
> dts is just a myth that may not exist once the nodes are loaded and
> operated upon depending on SoC variations (example efuse describing
> which OPPs can be used and which not).
I do not understand why. As long as a mapping from DT to data structures
in the kernel is done at boot, I can see how by indexing device nodes
can refer to specific OPPs. If they are disabled, amen, as long as we
can point at specific operating points that should be ok.
Indexing does not mean that the index in the DT is the same as the one
allocated by the OS. Indexing is there to point at specific OPPs from
different DT nodes, a good example are clock bindings and that's exactly
how they work.
Can you provide me with an example where the indexing would go wrong
please ?
Certainly relying on implicit ordering is not great either, actually I
would say that it is broken.
> That said, the original OPP[1][2] series discussion started by trying
> to kill indexing precisely for the same reason.. once you have it - it
> becomes just crazy to deal with.
I could not find any "index killing" :) discussion in there, but I will
keep reading.
> > It's assumed that the list is either in ascending or descending
> > order of frequency but not explicit in the binding document.
> > There are arch/arm/boot/dts/* files with opps in both styles.
> it should not matter -> opp library should do an insertion sort and
> organize it in ascending order once all the data is inserted. (line
> 449ish in opp.c)
That's OS details and they must not be mandated by the bindings.
We cannot rely on word of mouth for things to work, I do not like
implicit rules, so the bindings should speficy the ordering or better
a way to reference OPPs.
> if you see issues with the insertion sort not functioning, it is a bug
> and should be easy to track down and fix.
Problem is not the insertion sort, problem is that DT bindings do not
define a way to refer to a specific OPP, unless we do that implicitly
and again, I rest my case, that is broken.
> > Few other bindings like thermal defines bindings like
> > cooling-{min,max}-state assuming some order which is broken IMO.
> Now that you bring it up, I missed it :(.. yeah, I might have
> preferred it to be min frequency and max_frequency - I agree it is
> probably broken. I'd let Eduardo comment more about it.
>
> >
> > One such use-case that came up recently[0] is the c-state latencies
> > which could be different for each OPP. It would be good if the
> > latencies are specified with the indices to OPP table to avoid
> > inconsistency between the bindings.
>
> You can define C states based on frequencies as well - which really
> makes sense - since that sounds really like our constraint (say
> valid-at-frequency "xyz"
I do not think that's generic enough, I do not like the idea of looking
up frequencies (eg a C-state target_residency does not depend on the
frequency only - ie voltage and other factors play a role, it really
depends on an operating point- looking it up by frequency is misleading IMO).
> > It's mainly to avoid issues due to inconsistency and duplication
> > on data(frequency) in multiple bindings requiring it.
> >
> > Once we have indices to each on the OPP entries, then other binding
> > using it can refer to OPP with phandle and OPP index/specifier pairs
> > very similar to clock provider and consumer.
>
> Having used indexing in OMAP platforms, indexing is a problem waiting
> to happen unfortunately :(
Please be specific, I do not see why it is a problem.
[...]
> > 3. latencies(*): currently the latency that the CPU/memory access is unavailable
> > during an OPP transition is generic i.e. same from any OPP to any
> > other OPP. Does it make sense to have this per-OPP entry ?
>
> Why modify OPP when you are describing something else? you are
> describing "latency at a frequency" - just because an OPP definition
> as it stands right now is {frequency, voltage} tuple, makes it a very
> attractive target to keep extending it -> believe me, we have done
> that in the past ->arch/arm/mach-omap2/opp4xxx_data.c efuse register
> describing AVS per frequency is tempting..
>
> why not have memory-latency-per-opp = <frequency latency>?
>
> that allows OPP definitions to change in the future, but the
> definition remain constant.
>
> That said -> consider the following usecase: AM335x, OMAP3,4... (i
> will use omap4 as an example)
> MPU at 300MHz and bus (on which LPDDR2 memory is) at 100MHz
> AND
> MPU at 300MHz and bus (on which LPDDR2 memory is) at 200MHz
>
> are both valid with different memory access latencies. tying it down
> to OPP for MPU is just plain wrong - as it ignores other factors.
I think it is time we were defining OPPs for the system as a whole, the
issue has been brought up for C-state dependencies as well.
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-January/228042.html
We can easily define a global node that encompasses OPPs for various
devices, and then map the OPPs for devices to a global OPP table.
(totally made-up DT bindings, just to get the message across)
opps {
operating-points = <......>;
operating-point-cells = <2>;
cpu-opps {
/* where index maps to a global OPP above where the CPU OPP is valid */
operating-points = <...... index>;
};
memory-opp {
/*
where index maps to a global OPP above where the memory OPP is
valid
*/
operating-points = <...... index>;
};
};
> > 4. power(*): A measure of maximum power dissipation in an OPP state.
> > This might be useful measure for power aware scheduling ?
> Umm.. this is a hard nut to crack -> I had considered that previously
> as well -> In reality the leakage characteristics of the SoC
> distribution varies dramatically depending on which end of the
> distribution you look for a specific process node. in my company, we
> typically use cold, hot,nominal devices, this is some form or other
> (example - Samsung calls it "SoC's ASV group" [4]) - and every SoC
> company comes up with some strategy or other to control it optimally
> -> TI uses ABB[5], AVS[6] - etc... - not an unique problem -> so what
> will "power" mean? we cannot create dts per SoC part.
Yes, that's a hard nut to crack. Probably we can define a reference value,
to be debated.
> > (*) these are already part of P-state in ACPI(refer struct acpi_processor_px
> > in include/acpi/processor.h)
>
> Hmm.. what do we do with legacy processors that dont support ACPI or
> what ever our latest ARM term is for the equivalent?
>
> >
> > Apart from these I have seen on-going discussion for Samsung Exynos CPUFreq[2]
> > which might have some feedback for OPP bindings.
> >
> > It would be good to consolidate the shortcomings found so far, that could
> > help in extending the current OPP bindings.
>
> I hope this discussion helps. open to more views as well.
It helps a lot, thank you, please keep it going.
Thanks,
Lorenzo
^ permalink raw reply
* [PATCH 2/4] pinctrl: st: add stid127 support
From: srinivas kandagatla @ 2014-01-31 12:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391093744-19905-3-git-send-email-patrice.chotard@st.com>
Looks good for me.
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
On 30/01/14 14:55, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <alexandre.torgue@st.com>
>
> Add STid127 PIOs (psouth, pwest, peast) in pinctrl.
>
> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> ---
> drivers/pinctrl/pinctrl-st.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
> index 9cadc68..01227de 100644
> --- a/drivers/pinctrl/pinctrl-st.c
> +++ b/drivers/pinctrl/pinctrl-st.c
> @@ -336,6 +336,27 @@ static const struct st_pctl_data stih416_data = {
> .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
> };
>
> +/* STid127 data */
> +static const struct st_pctl_data stid127_data = {
> + .rt_style = st_retime_style_dedicated,
> + /* reuse stih416 delays as they are identical */
> + .input_delays = stih416_delays,
> + .ninput_delays = 14,
> + /* reuse stih416 delays as they are identical */
> + .output_delays = stih416_delays,
> + .noutput_delays = 14,
> + .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 14,
> +};
> +
> +static const struct st_pctl_data stid127_psouth_data = {
> + .rt_style = st_retime_style_dedicated,
> + .input_delays = stid127_delays,
> + .ninput_delays = 14,
> + .output_delays = stid127_delays,
> + .noutput_delays = 14,
> + .alt = 0, .oe = 7, .pu = 9, .od = 11, .rt = 13,
> +};
> +
> /* Low level functions.. */
> static inline int st_gpio_bank(int gpio)
> {
> @@ -1264,6 +1285,10 @@ static struct of_device_id st_pctl_of_match[] = {
> { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data},
> { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data},
> { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data},
> + { .compatible = "st,stid127-pwest-pinctrl", .data = &stid127_data },
> + { .compatible = "st,stid127-psouth-pinctrl",
> + .data = &stid127_psouth_data },
> + { .compatible = "st,stid127-peast-pinctrl", .data = &stid127_data },
> { /* sentinel */ }
> };
>
>
^ permalink raw reply
* [PATCH 1/4] ARM: STi: add stid127 soc support
From: srinivas kandagatla @ 2014-01-31 12:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201401301939.08302.arnd@arndb.de>
Hi Arnd,
On 30/01/14 18:39, Arnd Bergmann wrote:
> Actually reading the code in this file shows that the L2 cache
> initialization is the only nonstandard thing in there. We should
> really find a way to get rid of the entire function.
I think this will get rid of lot of code left in board-dt.
>
> Sorry if I missed the initial review, but can you explain
> why this is needed to start with?
On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
the way-size explicit here.
Thanks,
srini
^ permalink raw reply
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