* [PATCH v2 1/7] cpufreq: cpufreq-cpu0: allow optional safe voltage during frequency transitions
From: Thomas Abraham @ 2014-02-03 16:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2009408.gnUEcoqA3p@phil>
On Thu, Jan 30, 2014 at 8:39 PM, Heiko St?bner <heiko@sntech.de> wrote:
> On Thursday, 30. January 2014 18:23:44 Thomas Abraham wrote:
>> Hi Mike,
>>
>> On Wed, Jan 29, 2014 at 12:17 AM, Mike Turquette <mturquette@linaro.org>
> wrote:
>> > On Mon, Jan 27, 2014 at 9:30 PM, Thomas Abraham <ta.omasab@gmail.com>
> wrote:
>> >> Hi Mike,
>> >>
>> >> On Tue, Jan 28, 2014 at 1:55 AM, Mike Turquette <mturquette@linaro.org>
> wrote:
>> >>> Quoting Thomas Abraham (2014-01-18 04:10:51)
>> >>>
>> > As far as I can tell
>> > the remux does not happen because it is necessary to generate the
>> > required clock rate, but because we don't want to run the ARM core out
>> > of spec for a short time while the PLL relocks. Assuming I have that
>> > part of it right, I prefer for the parent mux operation to be a part
>> > of the CPUfreq driver's .target callback instead of hidden away in the
>> > clock driver.
>>
>> The re-parenting is mostly done to keep the ARM CPU clocked while the
>> PLL is stopped, reprogrammed and restarted. One of the side effects of
>> that is, the clock speed of the temporary parent could be higher then
>> what is allowed due to the ARM voltage at the time of re-parenting.
>> That is the reason to use the safe voltage.
>
> The Rockchip-SoCs use something similar, so I'm following quite closely what
> Thomas is trying to do here, as similar solution would also solve this issue
> for me.
>
> On some Rockchip-SoCs even stuff like pclk and hclk seems to be sourced from
> the divided armclk, creating additional constraints.
>
> But on the RKs (at least in the upstream sources) the armclk is simply equal
> to the pll output. A divider exists, but is only used to make sure that the
> armclk stays below the original rate when sourced from the temp-parent, like
>
> if (clk_get_rate(temp_parent) > clk_get_rate(main_parent)
> set_divider(something so that rate(temp) <= rate(main)
> clk_set_parent(...)
>
> Isn't there a similar possiblity on your platform, as it would remove the need
> for the safe-voltage?
Hi Heiko,
Yes, this works too! I have tested this method on Exynos4210,
Exynos4412 and Exynos5250 and it works fine without any need for safe
voltage. This is much better than using safe voltage. Thank you for
suggesting this.
Regards,
Thomas.
>
>
> In general I also like the approach of hiding the rate-change logic inside
> this composite clock, as the depending clocks can be easily kept in sync. As
> with the Rockchips the depending clocks are different for each of the three
> Cortex-A9 SoCs I looked at, it would be "interesting" if all of this would
> need to be done in a cpufreq driver.
>
>
> Heiko
>
^ permalink raw reply
* [PATCH v4 2/5] arm: add new asm macro update_sctlr
From: Will Deacon @ 2014-02-03 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140203155542.GI11329@bivouac.eciton.net>
On Mon, Feb 03, 2014 at 03:55:42PM +0000, Leif Lindholm wrote:
> On Mon, Feb 03, 2014 at 10:34:15AM +0000, Will Deacon wrote:
> > On Thu, Jan 30, 2014 at 01:12:47PM +0000, Leif Lindholm wrote:
> > > Oh, that's neat - thanks!
> > >
> > > Well, given that, I can think of two less horrible options:
> > > 1)
> > > .macro update_sctlr, tmp:req, set=, clear=
> > > mrc p15, 0, \tmp, c1, c0, 0
> > > .ifnc \set,
> > > orr \tmp, \set
> > > .endif
> > > .ifnc \clear,
> > > mvn \clear, \clear
> > > and \tmp, \tmp, \clear
> >
> > Can't you use bic here?
>
> Yeah.
>
> > > .endif
> > > mcr p15, 0, \tmp, c1, c0, 0
> > > .endm
> > >
> > > With the two call sites in uefi_phys.S as:
> > >
> > > ldr r5, =(CR_M)
> > > update_sctlr r12, , r5
> > > and
> > > ldr r4, =(CR_I | CR_C | CR_M)
> > > update_sctlr r12, r4
> >
> > These ldr= could be movs, right?
>
> The first one could.
> The second one could be movw on armv7+.
>
> > If so, I definitely prefer this to putting an ldr = into the macro itself
> > (option 2).
>
> And your preference between 1) and 2) is?
(1), using bic and mov[tw] where possible.
Will
^ permalink raw reply
* about last level cache on big little cpu
From: Sudeep Holla @ 2014-02-03 15:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52EFACDC.7090103@linaro.org>
On 03/02/14 14:51, Alex Shi wrote:
> Does all the big.LITTLE cpu share the same llc? or it depends on
> different vendor's products?
>
It depends on implementation. e.g. on Cortex-A7 L2 is optional.
So there can be big.LITTLE system with CA15(with L2) and CA7(without L2).
In general depends are the choice of the processors in bL and if L2
is mandatory or optional on those processors.
Regards,
Sudeep
^ permalink raw reply
* [PATCH v4 2/5] arm: add new asm macro update_sctlr
From: Leif Lindholm @ 2014-02-03 15:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140203103415.GA12187@mudshark.cambridge.arm.com>
On Mon, Feb 03, 2014 at 10:34:15AM +0000, Will Deacon wrote:
> On Thu, Jan 30, 2014 at 01:12:47PM +0000, Leif Lindholm wrote:
> > Oh, that's neat - thanks!
> >
> > Well, given that, I can think of two less horrible options:
> > 1)
> > .macro update_sctlr, tmp:req, set=, clear=
> > mrc p15, 0, \tmp, c1, c0, 0
> > .ifnc \set,
> > orr \tmp, \set
> > .endif
> > .ifnc \clear,
> > mvn \clear, \clear
> > and \tmp, \tmp, \clear
>
> Can't you use bic here?
Yeah.
> > .endif
> > mcr p15, 0, \tmp, c1, c0, 0
> > .endm
> >
> > With the two call sites in uefi_phys.S as:
> >
> > ldr r5, =(CR_M)
> > update_sctlr r12, , r5
> > and
> > ldr r4, =(CR_I | CR_C | CR_M)
> > update_sctlr r12, r4
>
> These ldr= could be movs, right?
The first one could.
The second one could be movw on armv7+.
> If so, I definitely prefer this to putting an ldr = into the macro itself
> (option 2).
And your preference between 1) and 2) is?
/
Leif
^ permalink raw reply
* [PATCH 09/10] watchdog: xilinx: Add missing binding
From: Michal Simek @ 2014-02-03 15:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3121595.GbLMuGPlvA@wuerfel>
On 02/03/2014 04:32 PM, Arnd Bergmann wrote:
> On Monday 03 February 2014 16:13:47 Michal Simek wrote:
>> Intention wasn't to fix binding but document current one
>> which is in mainline for a long time.
>
> Ok, I see.
>
>> Apart of this - yes, wdt-enable-once is nowayout and wdt-interval should be timeout
>> is seconds, and clock-frequency should go out and use CCF for getting clock.
>
> Could we make a common binding then, and document that the xilinx
> watchdog can optionally provide either one?
Do you mean to have 2 DT bindings?
This binding is used from 2011-07.
It means it was generated for all hw designs at least from this time.
I would say from DT usage on Microblaze because it is not special case
in our dt generator.
xlnx,XXX are XXX parameters which you have to setup in tools
and get synthesized. This is valid for all xilinx IPs. We have full
IP description by generating xlnx,XXX parameters directly from tools
because we know all variants which can happen.
Just back to your previous post:
"I'm not sure about the enable-once flag, which seems to just map to the
"nowayout" watchdog option that is not a hardware feature at all"
this is hw feature which you can select in tools because this is fpga. :-)
Thanks,
Michal
^ permalink raw reply
* [PATCH v5 16/16] ARM: Remove uprobes dependency on kprobes
From: Jon Medhurst (Tixy) @ 2014-02-03 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390507559-4697-17-git-send-email-dave.long@linaro.org>
On Thu, 2014-01-23 at 15:05 -0500, David Long wrote:
> From: "David A. Long" <dave.long@linaro.org>
>
> Now that arm uprobes support has been made separate from the arm kprobes code
> the Kconfig can be changed to reflect that.
>
> Signed-off-by: David A. Long <dave.long@linaro.org>
> ---
> arch/arm/Kconfig | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index fec5a6b..9ddc4ae 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -204,7 +204,6 @@ config NEED_DMA_MAP_STATE
> def_bool y
>
> config ARCH_SUPPORTS_UPROBES
> - depends on KPROBES
> def_bool y
>
> config ARCH_HAS_DMA_SET_COHERENT_MASK
Was this patch meant to have other contents? If not, it seems a bit
pointless as all it does is remove a line added in the previous patch,
so should just be folded into that one.
--
Tixy
^ permalink raw reply
* NFS client broken in Linus' tip
From: Trond Myklebust @ 2014-02-03 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140203145759.GA30263@infradead.org>
On Feb 3, 2014, at 9:57, Christoph Hellwig <hch@infradead.org> wrote:
> On Mon, Feb 03, 2014 at 09:17:30AM -0500, Trond Myklebust wrote:
>> As I said above, that causes posix_acl_xattr_get() to return the wrong answer (ENODATA instead of EOPNOTSUPP).
>
> Is it really the wrong answer? How does userspace care wether this
> server doesn't support ACLs at all or none is set? The resulting
> behavior is the same.
It will certainly cause acl_get_file() to behave differently than previously. I?ve no idea how that will affect applications, though.
> If there's a good reason to care we might have to go with your patch,
> but if we can avoid it I'd prefer to keep things simple.
One alternative is to simply wrap posix_acl_xattr_get() in fs/nfs/nfs3acl.c, and have it check the value of nfs_server_capable(inode, NFS_CAP_ACLS) before returning ENODATA. That?s rather ugly too...
--
Trond Myklebust
Linux NFS client maintainer
^ permalink raw reply
* [PATCH] asm-generic: add sched_setattr/sched_getattr syscalls
From: James Hogan @ 2014-02-03 15:33 UTC (permalink / raw)
To: linux-arm-kernel
Add the sched_setattr and sched_getattr syscalls to the generic syscall
list, which is used by the following architectures: arc, arm64, c6x,
hexagon, metag, openrisc, score, tile, unicore32.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-arch at vger.kernel.org
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: Mark Salter <msalter@redhat.com>
Cc: Aurelien Jacquiot <a-jacquiot@ti.com>
Cc: linux-c6x-dev at linux-c6x.org
Cc: Richard Kuo <rkuo@codeaurora.org>
Cc: linux-hexagon at vger.kernel.org
Cc: linux-metag at vger.kernel.org
Cc: Jonas Bonn <jonas@southpole.se>
Cc: linux at lists.openrisc.net
Cc: Chen Liqin <liqin.linux@gmail.com>
Cc: Lennox Wu <lennox.wu@gmail.com>
Cc: Chris Metcalf <cmetcalf@tilera.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
include/uapi/asm-generic/unistd.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/uapi/asm-generic/unistd.h b/include/uapi/asm-generic/unistd.h
index a20a9b4d3871..dde8041f40d2 100644
--- a/include/uapi/asm-generic/unistd.h
+++ b/include/uapi/asm-generic/unistd.h
@@ -692,9 +692,13 @@ __SC_COMP(__NR_process_vm_writev, sys_process_vm_writev, \
__SYSCALL(__NR_kcmp, sys_kcmp)
#define __NR_finit_module 273
__SYSCALL(__NR_finit_module, sys_finit_module)
+#define __NR_sched_setattr 274
+__SYSCALL(__NR_sched_setattr, sys_sched_setattr)
+#define __NR_sched_getattr 275
+__SYSCALL(__NR_sched_getattr, sys_sched_getattr)
#undef __NR_syscalls
-#define __NR_syscalls 274
+#define __NR_syscalls 276
/*
* All syscalls below here should go away really,
--
1.8.1.2
^ permalink raw reply related
* [PATCH 09/10] watchdog: xilinx: Add missing binding
From: Arnd Bergmann @ 2014-02-03 15:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <24ecacca-2714-4834-921c-b827c0e592a3@VA3EHSMHS003.ehs.local>
On Monday 03 February 2014 16:13:47 Michal Simek wrote:
> Intention wasn't to fix binding but document current one
> which is in mainline for a long time.
Ok, I see.
> Apart of this - yes, wdt-enable-once is nowayout and wdt-interval should be timeout
> is seconds, and clock-frequency should go out and use CCF for getting clock.
Could we make a common binding then, and document that the xilinx
watchdog can optionally provide either one?
Arnd
^ permalink raw reply
* [PATCH 09/10] watchdog: xilinx: Add missing binding
From: Michal Simek @ 2014-02-03 15:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201402031606.11753.arnd@arndb.de>
On 02/03/2014 04:06 PM, Arnd Bergmann wrote:
> On Friday 31 January 2014, Michal Simek wrote:
>> +Optional properties:
>> +- clock-frequency : Frequency of clock in Hz
>> +- xlnx,wdt-enable-once : 0 - Watchdog can be restarted
>> + 1 - Watchdog can be enabled just once
>> +- xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,
>> + <val> is integer from 8 to 31.
>> +
>
> The latter two don't really seem to be xilinx specific, it would be
> reasonable to have a standard watchdog binding that mandates a common
> format for them.
>
> I'm not sure about the enable-once flag, which seems to just map to the
> "nowayout" watchdog option that is not a hardware feature at all
> and should probably be kept as a software setting only, rather than
> settable through DT. If it is kept, it should have a standard name and
> get turned into a boolean (present/absent) property rather than a
> 0/1 integer property.
>
> The interval should really be specified in terms of seconds or miliseconds,
> not in clock cycles.
Intention wasn't to fix binding but document current one
which is in mainline for a long time.
Apart of this - yes, wdt-enable-once is nowayout and wdt-interval should be timeout
is seconds, and clock-frequency should go out and use CCF for getting clock.
Thanks,
Michal
^ permalink raw reply
* [PATCH 09/10] watchdog: xilinx: Add missing binding
From: Arnd Bergmann @ 2014-02-03 15:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9c721b89ed2ceb6997809bb3363f852277e67dc2.1391177880.git.michal.simek@xilinx.com>
On Friday 31 January 2014, Michal Simek wrote:
> +Optional properties:
> +- clock-frequency : Frequency of clock in Hz
> +- xlnx,wdt-enable-once : 0 - Watchdog can be restarted
> + 1 - Watchdog can be enabled just once
> +- xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,
> + <val> is integer from 8 to 31.
> +
The latter two don't really seem to be xilinx specific, it would be
reasonable to have a standard watchdog binding that mandates a common
format for them.
I'm not sure about the enable-once flag, which seems to just map to the
"nowayout" watchdog option that is not a hardware feature at all
and should probably be kept as a software setting only, rather than
settable through DT. If it is kept, it should have a standard name and
get turned into a boolean (present/absent) property rather than a
0/1 integer property.
The interval should really be specified in terms of seconds or miliseconds,
not in clock cycles.
Arnd
^ permalink raw reply
* about last level cache on big little cpu
From: Morten Rasmussen @ 2014-02-03 15:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52EFACDC.7090103@linaro.org>
On Mon, Feb 03, 2014 at 02:51:08PM +0000, Alex Shi wrote:
> Does all the big.LITTLE cpu share the same llc? or it depends on
> different vendor's products?
No. I don't know of any big.LITTLE implementation that does have a
shared last level cache. TC2 has per cluster L2 caches as last level
caches, so no cache is shared between the big and little clusters.
Morten
^ permalink raw reply
* NFS client broken in Linus' tip
From: Christoph Hellwig @ 2014-02-03 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <85AAFCF5-60EE-42E5-B103-37A4613C5947@primarydata.com>
On Mon, Feb 03, 2014 at 09:17:30AM -0500, Trond Myklebust wrote:
> As I said above, that causes posix_acl_xattr_get() to return the wrong answer (ENODATA instead of EOPNOTSUPP).
Is it really the wrong answer? How does userspace care wether this
server doesn't support ACLs at all or none is set? The resulting
behavior is the same.
If there's a good reason to care we might have to go with your patch,
but if we can avoid it I'd prefer to keep things simple.
^ permalink raw reply
* [PATCH v5 07/16] ARM: Remove use of struct kprobe from generic probes code
From: Jon Medhurst (Tixy) @ 2014-02-03 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390507559-4697-8-git-send-email-dave.long@linaro.org>
On Thu, 2014-01-23 at 15:05 -0500, David Long wrote:
> From: "David A. Long" <dave.long@linaro.org>
>
> Change the generic ARM probes code to pass in the opcode and architecture-specific
> structure separately instead of using struct kprobe, so we do not pollute
> code being used only for uprobes or other non-kprobes instruction
> interpretation.
>
> Signed-off-by: David A. Long <dave.long@linaro.org>
> ---
One minor nit-pick...
[...]
> diff --git a/arch/arm/kernel/kprobes-thumb.c b/arch/arm/kernel/kprobes-thumb.c
> index c7ee290..cea707a 100644
> --- a/arch/arm/kernel/kprobes-thumb.c
> +++ b/arch/arm/kernel/kprobes-thumb.c
[...]
> @@ -593,7 +590,7 @@ t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs)
> bx_write_pc(pc, regs);
> }
>
> -static enum kprobe_insn __kprobes
> +enum kprobe_insn __kprobes
> t16_decode_pop(kprobe_opcode_t insn, struct arch_specific_insn *asi,
> struct decode_header *d)
> {
The above removal of 'static' appears to be an unneeded accidental
change?
--
Tixy
^ permalink raw reply
* [PATCH v5 08/14] ahci-platform: "Library-ise" suspend / resume functionality
From: Arnd Bergmann @ 2014-02-03 14:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390417489-5354-9-git-send-email-hdegoede@redhat.com>
On Wednesday 22 January 2014, Hans de Goede wrote:
> --- a/include/linux/ahci_platform.h
> +++ b/include/linux/ahci_platform.h
> @@ -50,4 +50,11 @@ int ahci_platform_init_host(struct platform_device *pdev,
> unsigned int force_port_map,
> unsigned int mask_port_map);
>
> +#ifdef CONFIG_PM_SLEEP
> +int ahci_platform_suspend_host(struct device *dev);
> +int ahci_platform_resume_host(struct device *dev);
> +int ahci_platform_suspend(struct device *dev);
> +int ahci_platform_resume(struct device *dev);
> +#endif
> +
Not sure if the #ifdef does any good here. Normally, we don't hide declarations
so we can do stuff like
if (IS_ENABLED(CONFIG_PM_SLEEP))
ret = ahci_platform_suspend_host(dev);
and expect the code to compile and link just fine.
Arnd
^ permalink raw reply
* about last level cache on big little cpu
From: Alex Shi @ 2014-02-03 14:51 UTC (permalink / raw)
To: linux-arm-kernel
Does all the big.LITTLE cpu share the same llc? or it depends on
different vendor's products?
--
Thanks
Alex
^ permalink raw reply
* [PATCH v2 6/6] ARM: STi: Add reset controller support to mach-sti Kconfig
From: srinivas.kandagatla at st.com @ 2014-02-03 14:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391437665-11913-1-git-send-email-srinivas.kandagatla@st.com>
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch selects reset controller support for ARCH_STI and
selects the reset controllers for STiH415 and STiH416 SoCs.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/mach-sti/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index d71654b..2550620 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -7,6 +7,7 @@ menuconfig ARCH_STI
select PINCTRL
select PINCTRL_ST
select MFD_SYSCON
+ select ARCH_HAS_RESET_CONTROLLER
select MIGHT_HAVE_CACHE_L2X0
select HAVE_SMP
select HAVE_ARM_SCU if SMP
@@ -28,6 +29,7 @@ if ARCH_STI
config SOC_STIH415
bool "STiH415 STMicroelectronics Consumer Electronics family"
default y
+ select STIH415_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH415 parts, primarily targeted at set-top-box
@@ -37,6 +39,7 @@ config SOC_STIH415
config SOC_STIH416
bool "STiH416 STMicroelectronics Consumer Electronics family"
default y
+ select STIH416_RESET
help
This enables support for STMicroelectronics Digital Consumer
Electronics family StiH416 parts, primarily targeted at set-top-box
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 5/6] drivers: reset: stih416: add softreset controller
From: srinivas.kandagatla at st.com @ 2014-02-03 14:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391437665-11913-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds softreset controller for STiH416 SOC, soft reset
controller is based on system configuration registers which are mapped
via regmap. This reset controller does not have any feedback or
acknowledgement. With this patch a new device "st,stih416-softreset" is
registered with system configuration registers based reset controller
that controls the softreset state of the hardware such as Ethernet, IRB.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
arch/arm/boot/dts/stih416.dtsi | 5 ++
drivers/reset/sti/reset-stih416.c | 64 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih416-resets.h | 29 +++++++++
3 files changed, 98 insertions(+)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index e5bec66..788ba5b 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -33,6 +33,11 @@
compatible = "st,stih416-powerdown";
};
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih416-softreset";
+ };
+
syscfg_sbc:sbc-syscfg at fe600000{
compatible = "st,stih416-sbc-syscfg", "syscon";
reg = <0xfe600000 0x1000>;
diff --git a/drivers/reset/sti/reset-stih416.c b/drivers/reset/sti/reset-stih416.c
index 0becfc5..fe3bf02 100644
--- a/drivers/reset/sti/reset-stih416.c
+++ b/drivers/reset/sti/reset-stih416.c
@@ -24,6 +24,7 @@ static const char stih416_front[] = "st,stih416-front-syscfg";
static const char stih416_rear[] = "st,stih416-rear-syscfg";
static const char stih416_sbc[] = "st,stih416-sbc-syscfg";
static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
+static const char stih416_cpu[] = "st,stih416-cpu-syscfg";
#define STIH416_PDN_FRONT(_bit) \
_SYSCFG_RST_CH(stih416_front, SYSCFG_1500, _bit, SYSSTAT_1578, _bit)
@@ -37,6 +38,29 @@ static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
#define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */
#define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */
+#define SYSCFG_2552 0x8A0 /* Reset Generator control 0 */
+#define SYSCFG_1539 0x86c /* Softreset Ethernet 0 */
+#define SYSCFG_510 0x7f8 /* Softreset Ethernet 1 */
+#define LPM_SYSCFG_1 0x4 /* Softreset IRB */
+#define SYSCFG_2553 0x8a4 /* Softreset SATA0/1, PCIE0/1 */
+#define SYSCFG_7563 0x8cc /* MPE softresets 0 */
+#define SYSCFG_7564 0x8d0 /* MPE softresets 1 */
+
+#define STIH416_SRST_CPU(_reg, _bit) \
+ _SYSCFG_RST_CH_NO_ACK(stih416_cpu, _reg, _bit)
+
+#define STIH416_SRST_FRONT(_reg, _bit) \
+ _SYSCFG_RST_CH_NO_ACK(stih416_front, _reg, _bit)
+
+#define STIH416_SRST_REAR(_reg, _bit) \
+ _SYSCFG_RST_CH_NO_ACK(stih416_rear, _reg, _bit)
+
+#define STIH416_SRST_LPM(_reg, _bit) \
+ _SYSCFG_RST_CH_NO_ACK(stih416_lpm, _reg, _bit)
+
+#define STIH416_SRST_SBC(_reg, _bit) \
+ _SYSCFG_RST_CH_NO_ACK(stih416_sbc, _reg, _bit)
+
static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
[STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0),
[STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1),
@@ -51,15 +75,55 @@ static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
[STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8),
};
+static const struct syscfg_reset_channel_data stih416_softresets[] = {
+ [STIH416_ETH0_SOFTRESET] = STIH416_SRST_FRONT(SYSCFG_1539, 0),
+ [STIH416_ETH1_SOFTRESET] = STIH416_SRST_SBC(SYSCFG_510, 0),
+ [STIH416_IRB_SOFTRESET] = STIH416_SRST_LPM(LPM_SYSCFG_1, 6),
+ [STIH416_USB0_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 9),
+ [STIH416_USB1_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 10),
+ [STIH416_USB2_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 11),
+ [STIH416_USB3_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 28),
+ [STIH416_SATA0_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 7),
+ [STIH416_SATA1_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 3),
+ [STIH416_PCIE0_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 15),
+ [STIH416_PCIE1_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 2),
+ [STIH416_AUD_DAC_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 14),
+ [STIH416_HDTVOUT_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 5),
+ [STIH416_VTAC_M_RX_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 25),
+ [STIH416_VTAC_A_RX_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 26),
+ [STIH416_SYNC_HD_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 5),
+ [STIH416_SYNC_SD_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 6),
+ [STIH416_BLITTER_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 10),
+ [STIH416_GPU_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 11),
+ [STIH416_VTAC_M_TX_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 18),
+ [STIH416_VTAC_A_TX_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 19),
+ [STIH416_VTG_AUX_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 21),
+ [STIH416_JPEG_DEC_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 23),
+ [STIH416_HVA_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 2),
+ [STIH416_COMPO_M_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 3),
+ [STIH416_COMPO_A_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 4),
+ [STIH416_VP8_DEC_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 10),
+ [STIH416_VTG_MAIN_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 16),
+};
+
static struct syscfg_reset_controller_data stih416_powerdown_controller = {
.wait_for_ack = true,
.nr_channels = ARRAY_SIZE(stih416_powerdowns),
.channels = stih416_powerdowns,
};
+static struct syscfg_reset_controller_data stih416_softreset_controller = {
+ .wait_for_ack = false,
+ .active_low = true,
+ .nr_channels = ARRAY_SIZE(stih416_softresets),
+ .channels = stih416_softresets,
+};
+
static struct of_device_id stih416_reset_match[] = {
{ .compatible = "st,stih416-powerdown",
.data = &stih416_powerdown_controller, },
+ { .compatible = "st,stih416-softreset",
+ .data = &stih416_softreset_controller, },
{},
};
diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h
index d7da55f..2127743 100644
--- a/include/dt-bindings/reset-controller/stih416-resets.h
+++ b/include/dt-bindings/reset-controller/stih416-resets.h
@@ -18,4 +18,33 @@
#define STIH416_PCIE0_POWERDOWN 9
#define STIH416_PCIE1_POWERDOWN 10
+#define STIH416_ETH0_SOFTRESET 0
+#define STIH416_ETH1_SOFTRESET 1
+#define STIH416_IRB_SOFTRESET 2
+#define STIH416_USB0_SOFTRESET 3
+#define STIH416_USB1_SOFTRESET 4
+#define STIH416_USB2_SOFTRESET 5
+#define STIH416_USB3_SOFTRESET 6
+#define STIH416_SATA0_SOFTRESET 7
+#define STIH416_SATA1_SOFTRESET 8
+#define STIH416_PCIE0_SOFTRESET 9
+#define STIH416_PCIE1_SOFTRESET 10
+#define STIH416_AUD_DAC_SOFTRESET 11
+#define STIH416_HDTVOUT_SOFTRESET 12
+#define STIH416_VTAC_M_RX_SOFTRESET 13
+#define STIH416_VTAC_A_RX_SOFTRESET 14
+#define STIH416_SYNC_HD_SOFTRESET 15
+#define STIH416_SYNC_SD_SOFTRESET 16
+#define STIH416_BLITTER_SOFTRESET 17
+#define STIH416_GPU_SOFTRESET 18
+#define STIH416_VTAC_M_TX_SOFTRESET 19
+#define STIH416_VTAC_A_TX_SOFTRESET 20
+#define STIH416_VTG_AUX_SOFTRESET 21
+#define STIH416_JPEG_DEC_SOFTRESET 22
+#define STIH416_HVA_SOFTRESET 23
+#define STIH416_COMPO_M_SOFTRESET 24
+#define STIH416_COMPO_A_SOFTRESET 25
+#define STIH416_VP8_DEC_SOFTRESET 26
+#define STIH416_VTG_MAIN_SOFTRESET 27
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 4/6] drivers: reset: stih415: add softreset controller
From: srinivas.kandagatla at st.com @ 2014-02-03 14:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391437665-11913-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds softreset controller for STiH415 SOC, soft reset
controller is based on system configuration registers which are mapped
via regmap. This reset controller does not have any feedback or
acknowledgement. With this patch a new device "st,stih415-softreset" is
registered with system configuration registers based reset controller
that controls the softreset state of the hardware such as Ethernet, IRB.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
---
.../devicetree/bindings/reset/st,sti-softreset.txt | 46 ++++++++++++++++++++
arch/arm/boot/dts/stih415.dtsi | 5 +++
drivers/reset/sti/reset-stih415.c | 35 +++++++++++++++
.../dt-bindings/reset-controller/stih415-resets.h | 7 +++
4 files changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-softreset.txt
diff --git a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
new file mode 100644
index 0000000..a8d3d3c
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
@@ -0,0 +1,46 @@
+STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller
+=============================================================================
+
+This binding describes a reset controller device that is used to enable and
+disable on-chip peripheral controllers such as USB and SATA, using
+"softreset" control bits found in the STi family SoC system configuration
+registers.
+
+The actual action taken when softreset is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers and after an assert/deassert sequence the hardware's previous state
+may no longer be valid.
+
+Please refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "st,<chip>-softreset" example:
+ "st,stih415-softreset" or "st,stih416-softreset";
+- #reset-cells: 1, see below
+
+example:
+
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-softreset";
+ };
+
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the softreset device node and an
+index specifying which channel to use, as described in reset.txt
+
+example:
+
+ ethernet0{
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ };
+
+Macro definitions for the supported reset channels can be found in:
+
+include/dt-bindings/reset-controller/stih415-resets.h
+include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 19e29f4..d52207c 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -34,6 +34,11 @@
compatible = "st,stih415-powerdown";
};
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-softreset";
+ };
+
syscfg_sbc: sbc-syscfg at fe600000{
compatible = "st,stih415-sbc-syscfg", "syscon";
reg = <0xfe600000 0xb4>;
diff --git a/drivers/reset/sti/reset-stih415.c b/drivers/reset/sti/reset-stih415.c
index 56c2146..e6f6c41 100644
--- a/drivers/reset/sti/reset-stih415.c
+++ b/drivers/reset/sti/reset-stih415.c
@@ -31,12 +31,29 @@ static const char stih415_lpm[] = "st,stih415-lpm-syscfg";
#define STIH415_PDN_REAR(_cntl, _stat) \
_SYSCFG_RST_CH(stih415_rear, SYSCFG_336, _cntl, SYSSTAT_384, _stat)
+#define STIH415_SRST_REAR(_reg, _bit) \
+ _SYSCFG_RST_CH_NO_ACK(stih415_rear, _reg, _bit)
+
+#define STIH415_SRST_SBC(_reg, _bit) \
+ _SYSCFG_RST_CH_NO_ACK(stih415_sbc, _reg, _bit)
+
+#define STIH415_SRST_FRONT(_reg, _bit) \
+ _SYSCFG_RST_CH_NO_ACK(stih415_front, _reg, _bit)
+
+#define STIH415_SRST_LPM(_reg, _bit) \
+ _SYSCFG_RST_CH_NO_ACK(stih415_lpm, _reg, _bit)
+
#define SYSCFG_114 0x38 /* Powerdown request EMI/NAND/Keyscan */
#define SYSSTAT_187 0x15c /* Powerdown status EMI/NAND/Keyscan */
#define SYSCFG_336 0x90 /* Powerdown request USB/SATA/PCIe */
#define SYSSTAT_384 0x150 /* Powerdown status USB/SATA/PCIe */
+#define SYSCFG_376 0x130 /* Reset generator 0 control 0 */
+#define SYSCFG_166 0x108 /* Softreset Ethernet 0 */
+#define SYSCFG_31 0x7c /* Softreset Ethernet 1 */
+#define LPM_SYSCFG_1 0x4 /* Softreset IRB */
+
static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
[STIH415_EMISS_POWERDOWN] = STIH415_PDN_FRONT(0),
[STIH415_NAND_POWERDOWN] = STIH415_PDN_FRONT(1),
@@ -49,15 +66,33 @@ static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
[STIH415_PCIE_POWERDOWN] = STIH415_PDN_REAR(5, 8),
};
+static const struct syscfg_reset_channel_data stih415_softresets[] = {
+ [STIH415_ETH0_SOFTRESET] = STIH415_SRST_FRONT(SYSCFG_166, 0),
+ [STIH415_ETH1_SOFTRESET] = STIH415_SRST_SBC(SYSCFG_31, 0),
+ [STIH415_IRB_SOFTRESET] = STIH415_SRST_LPM(LPM_SYSCFG_1, 6),
+ [STIH415_USB0_SOFTRESET] = STIH415_SRST_REAR(SYSCFG_376, 9),
+ [STIH415_USB1_SOFTRESET] = STIH415_SRST_REAR(SYSCFG_376, 10),
+ [STIH415_USB2_SOFTRESET] = STIH415_SRST_REAR(SYSCFG_376, 11),
+};
+
static struct syscfg_reset_controller_data stih415_powerdown_controller = {
.wait_for_ack = true,
.nr_channels = ARRAY_SIZE(stih415_powerdowns),
.channels = stih415_powerdowns,
};
+static struct syscfg_reset_controller_data stih415_softreset_controller = {
+ .wait_for_ack = false,
+ .active_low = true,
+ .nr_channels = ARRAY_SIZE(stih415_softresets),
+ .channels = stih415_softresets,
+};
+
static struct of_device_id stih415_reset_match[] = {
{ .compatible = "st,stih415-powerdown",
.data = &stih415_powerdown_controller, },
+ { .compatible = "st,stih415-softreset",
+ .data = &stih415_softreset_controller, },
{},
};
diff --git a/include/dt-bindings/reset-controller/stih415-resets.h b/include/dt-bindings/reset-controller/stih415-resets.h
index 2d54e68..c2f8a66 100644
--- a/include/dt-bindings/reset-controller/stih415-resets.h
+++ b/include/dt-bindings/reset-controller/stih415-resets.h
@@ -16,4 +16,11 @@
#define STIH415_SATA1_POWERDOWN 7
#define STIH415_PCIE_POWERDOWN 8
+#define STIH415_ETH0_SOFTRESET 0
+#define STIH415_ETH1_SOFTRESET 1
+#define STIH415_IRB_SOFTRESET 2
+#define STIH415_USB0_SOFTRESET 3
+#define STIH415_USB1_SOFTRESET 4
+#define STIH415_USB2_SOFTRESET 5
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 3/6] drivers: reset: Reset controller driver for STiH416
From: srinivas.kandagatla at st.com @ 2014-02-03 14:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391437665-11913-1-git-send-email-srinivas.kandagatla@st.com>
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller platform driver for the STiH416
SoC. This initial version provides a compatible driver for the
"st,stih416-powerdown" device, which registers a system configuration
register based reset controller that controls the powerdown state of
hardware such as the on-chip USB host controllers.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
arch/arm/boot/dts/stih416.dtsi | 6 ++
drivers/reset/sti/Kconfig | 4 +
drivers/reset/sti/Makefile | 2 +-
drivers/reset/sti/reset-stih416.c | 79 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih416-resets.h | 21 ++++++
5 files changed, 111 insertions(+), 1 deletion(-)
create mode 100644 drivers/reset/sti/reset-stih416.c
create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index b7ab47b..e5bec66 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -10,6 +10,7 @@
#include "stih416-clock.dtsi"
#include "stih416-pinctrl.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset-controller/stih416-resets.h>
/ {
L2: cache-controller {
compatible = "arm,pl310-cache";
@@ -27,6 +28,11 @@
ranges;
compatible = "simple-bus";
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih416-powerdown";
+ };
+
syscfg_sbc:sbc-syscfg at fe600000{
compatible = "st,stih416-sbc-syscfg", "syscon";
reg = <0xfe600000 0x1000>;
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
index ef6654a..88d2d03 100644
--- a/drivers/reset/sti/Kconfig
+++ b/drivers/reset/sti/Kconfig
@@ -8,4 +8,8 @@ config STIH415_RESET
bool
select STI_RESET_SYSCFG
+config STIH416_RESET
+ bool
+ select STI_RESET_SYSCFG
+
endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
index fce4433..be1c976 100644
--- a/drivers/reset/sti/Makefile
+++ b/drivers/reset/sti/Makefile
@@ -1,4 +1,4 @@
obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
-# SoC specific reset devices
obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
+obj-$(CONFIG_STIH416_RESET) += reset-stih416.o
diff --git a/drivers/reset/sti/reset-stih416.c b/drivers/reset/sti/reset-stih416.c
new file mode 100644
index 0000000..0becfc5
--- /dev/null
+++ b/drivers/reset/sti/reset-stih416.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/reset-controller/stih416-resets.h>
+
+#include "reset-syscfg.h"
+
+/*
+ * STiH416 Peripheral powerdown definitions.
+ */
+static const char stih416_front[] = "st,stih416-front-syscfg";
+static const char stih416_rear[] = "st,stih416-rear-syscfg";
+static const char stih416_sbc[] = "st,stih416-sbc-syscfg";
+static const char stih416_lpm[] = "st,stih416-lpm-syscfg";
+
+#define STIH416_PDN_FRONT(_bit) \
+ _SYSCFG_RST_CH(stih416_front, SYSCFG_1500, _bit, SYSSTAT_1578, _bit)
+
+#define STIH416_PDN_REAR(_cntl, _stat) \
+ _SYSCFG_RST_CH(stih416_rear, SYSCFG_2525, _cntl, SYSSTAT_2583, _stat)
+
+#define SYSCFG_1500 0x7d0 /* Powerdown request EMI/NAND/Keyscan */
+#define SYSSTAT_1578 0x908 /* Powerdown status EMI/NAND/Keyscan */
+
+#define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */
+#define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */
+
+static const struct syscfg_reset_channel_data stih416_powerdowns[] = {
+ [STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0),
+ [STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1),
+ [STIH416_KEYSCAN_POWERDOWN] = STIH416_PDN_FRONT(2),
+ [STIH416_USB0_POWERDOWN] = STIH416_PDN_REAR(0, 0),
+ [STIH416_USB1_POWERDOWN] = STIH416_PDN_REAR(1, 1),
+ [STIH416_USB2_POWERDOWN] = STIH416_PDN_REAR(2, 2),
+ [STIH416_USB3_POWERDOWN] = STIH416_PDN_REAR(6, 5),
+ [STIH416_SATA0_POWERDOWN] = STIH416_PDN_REAR(3, 3),
+ [STIH416_SATA1_POWERDOWN] = STIH416_PDN_REAR(4, 4),
+ [STIH416_PCIE0_POWERDOWN] = STIH416_PDN_REAR(7, 9),
+ [STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8),
+};
+
+static struct syscfg_reset_controller_data stih416_powerdown_controller = {
+ .wait_for_ack = true,
+ .nr_channels = ARRAY_SIZE(stih416_powerdowns),
+ .channels = stih416_powerdowns,
+};
+
+static struct of_device_id stih416_reset_match[] = {
+ { .compatible = "st,stih416-powerdown",
+ .data = &stih416_powerdown_controller, },
+ {},
+};
+
+static struct platform_driver stih416_reset_driver = {
+ .probe = syscfg_reset_probe,
+ .driver = {
+ .name = "reset-stih416",
+ .owner = THIS_MODULE,
+ .of_match_table = stih416_reset_match,
+ },
+};
+
+static int __init stih416_reset_init(void)
+{
+ return platform_driver_register(&stih416_reset_driver);
+}
+arch_initcall(stih416_reset_init);
diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h
new file mode 100644
index 0000000..d7da55f
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih416-resets.h
@@ -0,0 +1,21 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH416 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH416
+
+#define STIH416_EMISS_POWERDOWN 0
+#define STIH416_NAND_POWERDOWN 1
+#define STIH416_KEYSCAN_POWERDOWN 2
+#define STIH416_USB0_POWERDOWN 3
+#define STIH416_USB1_POWERDOWN 4
+#define STIH416_USB2_POWERDOWN 5
+#define STIH416_USB3_POWERDOWN 6
+#define STIH416_SATA0_POWERDOWN 7
+#define STIH416_SATA1_POWERDOWN 8
+#define STIH416_PCIE0_POWERDOWN 9
+#define STIH416_PCIE1_POWERDOWN 10
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 2/6] drivers: reset: Reset controller driver for STiH415
From: srinivas.kandagatla at st.com @ 2014-02-03 14:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391437665-11913-1-git-send-email-srinivas.kandagatla@st.com>
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller platform driver for the STiH415
SoC. This initial version provides a compatible driver for the
"st,stih415-powerdown" device, which registers a system configuration
register based reset controller that controls the powerdown state of
hardware such as the on-chip USB host controllers.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
.../devicetree/bindings/reset/st,sti-powerdown.txt | 47 ++++++++++++
arch/arm/boot/dts/stih415.dtsi | 6 ++
drivers/reset/sti/Kconfig | 4 +
drivers/reset/sti/Makefile | 3 +
drivers/reset/sti/reset-stih415.c | 77 ++++++++++++++++++++
.../dt-bindings/reset-controller/stih415-resets.h | 19 +++++
6 files changed, 156 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
create mode 100644 drivers/reset/sti/reset-stih415.c
create mode 100644 include/dt-bindings/reset-controller/stih415-resets.h
diff --git a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
new file mode 100644
index 0000000..5ab26b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
@@ -0,0 +1,47 @@
+STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
+=============================================================================
+
+This binding describes a reset controller device that is used to enable and
+disable on-chip peripheral controllers such as USB and SATA, using
+"powerdown" control bits found in the STi family SoC system configuration
+registers. These have been grouped together into a single reset controller
+device for convenience.
+
+The actual action taken when powerdown is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers and after an assert/deassert sequence the hardware's previous state
+may no longer be valid.
+
+Please refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "st,<chip>-powerdown"
+ ex: "st,stih415-powerdown", "st,stih416-powerdown"
+- #reset-cells: 1, see below
+
+example:
+
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-powerdown";
+ };
+
+
+Specifying powerdown control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the powerdown device node and an
+index specifying which channel to use, as described in reset.txt
+
+example:
+
+ usb1: usb at fe200000 {
+ resets = <&powerdown STIH41X_USB1_POWERDOWN>;
+ };
+
+Macro definitions for the supported reset channels can be found in:
+
+include/dt-bindings/reset-controller/stih415-resets.h
+include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index d9c7dd1..19e29f4 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -10,6 +10,7 @@
#include "stih415-clock.dtsi"
#include "stih415-pinctrl.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset-controller/stih415-resets.h>
/ {
L2: cache-controller {
@@ -28,6 +29,11 @@
ranges;
compatible = "simple-bus";
+ powerdown: powerdown-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih415-powerdown";
+ };
+
syscfg_sbc: sbc-syscfg at fe600000{
compatible = "st,stih415-sbc-syscfg", "syscon";
reg = <0xfe600000 0xb4>;
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
index ba13796..ef6654a 100644
--- a/drivers/reset/sti/Kconfig
+++ b/drivers/reset/sti/Kconfig
@@ -4,4 +4,8 @@ config STI_RESET_SYSCFG
bool
select RESET_CONTROLLER
+config STIH415_RESET
+ bool
+ select STI_RESET_SYSCFG
+
endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
index c4a51d9..fce4433 100644
--- a/drivers/reset/sti/Makefile
+++ b/drivers/reset/sti/Makefile
@@ -1 +1,4 @@
obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
+
+# SoC specific reset devices
+obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
diff --git a/drivers/reset/sti/reset-stih415.c b/drivers/reset/sti/reset-stih415.c
new file mode 100644
index 0000000..56c2146
--- /dev/null
+++ b/drivers/reset/sti/reset-stih415.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/reset-controller/stih415-resets.h>
+
+#include "reset-syscfg.h"
+
+/*
+ * STiH415 Peripheral powerdown definitions.
+ */
+static const char stih415_front[] = "st,stih415-front-syscfg";
+static const char stih415_rear[] = "st,stih415-rear-syscfg";
+static const char stih415_sbc[] = "st,stih415-sbc-syscfg";
+static const char stih415_lpm[] = "st,stih415-lpm-syscfg";
+
+#define STIH415_PDN_FRONT(_bit) \
+ _SYSCFG_RST_CH(stih415_front, SYSCFG_114, _bit, SYSSTAT_187, _bit)
+
+#define STIH415_PDN_REAR(_cntl, _stat) \
+ _SYSCFG_RST_CH(stih415_rear, SYSCFG_336, _cntl, SYSSTAT_384, _stat)
+
+#define SYSCFG_114 0x38 /* Powerdown request EMI/NAND/Keyscan */
+#define SYSSTAT_187 0x15c /* Powerdown status EMI/NAND/Keyscan */
+
+#define SYSCFG_336 0x90 /* Powerdown request USB/SATA/PCIe */
+#define SYSSTAT_384 0x150 /* Powerdown status USB/SATA/PCIe */
+
+static const struct syscfg_reset_channel_data stih415_powerdowns[] = {
+ [STIH415_EMISS_POWERDOWN] = STIH415_PDN_FRONT(0),
+ [STIH415_NAND_POWERDOWN] = STIH415_PDN_FRONT(1),
+ [STIH415_KEYSCAN_POWERDOWN] = STIH415_PDN_FRONT(2),
+ [STIH415_USB0_POWERDOWN] = STIH415_PDN_REAR(0, 0),
+ [STIH415_USB1_POWERDOWN] = STIH415_PDN_REAR(1, 1),
+ [STIH415_USB2_POWERDOWN] = STIH415_PDN_REAR(2, 2),
+ [STIH415_SATA0_POWERDOWN] = STIH415_PDN_REAR(3, 3),
+ [STIH415_SATA1_POWERDOWN] = STIH415_PDN_REAR(4, 4),
+ [STIH415_PCIE_POWERDOWN] = STIH415_PDN_REAR(5, 8),
+};
+
+static struct syscfg_reset_controller_data stih415_powerdown_controller = {
+ .wait_for_ack = true,
+ .nr_channels = ARRAY_SIZE(stih415_powerdowns),
+ .channels = stih415_powerdowns,
+};
+
+static struct of_device_id stih415_reset_match[] = {
+ { .compatible = "st,stih415-powerdown",
+ .data = &stih415_powerdown_controller, },
+ {},
+};
+
+static struct platform_driver stih415_reset_driver = {
+ .probe = syscfg_reset_probe,
+ .driver = {
+ .name = "reset-stih415",
+ .owner = THIS_MODULE,
+ .of_match_table = stih415_reset_match,
+ },
+};
+
+static int __init stih415_reset_init(void)
+{
+ return platform_driver_register(&stih415_reset_driver);
+}
+arch_initcall(stih415_reset_init);
diff --git a/include/dt-bindings/reset-controller/stih415-resets.h b/include/dt-bindings/reset-controller/stih415-resets.h
new file mode 100644
index 0000000..2d54e68
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih415-resets.h
@@ -0,0 +1,19 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH415 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH415
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH415
+
+#define STIH415_EMISS_POWERDOWN 0
+#define STIH415_NAND_POWERDOWN 1
+#define STIH415_KEYSCAN_POWERDOWN 2
+#define STIH415_USB0_POWERDOWN 3
+#define STIH415_USB1_POWERDOWN 4
+#define STIH415_USB2_POWERDOWN 5
+#define STIH415_SATA0_POWERDOWN 6
+#define STIH415_SATA1_POWERDOWN 7
+#define STIH415_PCIE_POWERDOWN 8
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH415 */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 1/6] drivers: reset: STi SoC system configuration reset controller support
From: srinivas.kandagatla at st.com @ 2014-02-03 14:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391437665-11913-1-git-send-email-srinivas.kandagatla@st.com>
From: Stephen Gallimore <stephen.gallimore@st.com>
This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device. System configuration registers are accessed through
the regmap framework and the mfd/syscon driver.
The implementation optionally supports waiting for the reset action to
be acknowledged in a separate status register and supports both
active high and active low reset lines. These properties are common across
all the reset channels in a specific reset controller instance, hence
all channels in a paritcular controller are expected to behave in the
same way.
Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com>
---
drivers/reset/Kconfig | 2 +
drivers/reset/Makefile | 1 +
drivers/reset/sti/Kconfig | 7 ++
drivers/reset/sti/Makefile | 1 +
drivers/reset/sti/reset-syscfg.c | 186 ++++++++++++++++++++++++++++++++++++++
drivers/reset/sti/reset-syscfg.h | 69 ++++++++++++++
6 files changed, 266 insertions(+)
create mode 100644 drivers/reset/sti/Kconfig
create mode 100644 drivers/reset/sti/Makefile
create mode 100644 drivers/reset/sti/reset-syscfg.c
create mode 100644 drivers/reset/sti/reset-syscfg.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c9d04f7..0615f50 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -11,3 +11,5 @@ menuconfig RESET_CONTROLLER
via GPIOs or SoC-internal reset controller modules.
If unsure, say no.
+
+source "drivers/reset/sti/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index cc29832..4f60caf 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_RESET_CONTROLLER) += core.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
+obj-$(CONFIG_ARCH_STI) += sti/
diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig
new file mode 100644
index 0000000..ba13796
--- /dev/null
+++ b/drivers/reset/sti/Kconfig
@@ -0,0 +1,7 @@
+if ARCH_STI
+
+config STI_RESET_SYSCFG
+ bool
+ select RESET_CONTROLLER
+
+endif
diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile
new file mode 100644
index 0000000..c4a51d9
--- /dev/null
+++ b/drivers/reset/sti/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
diff --git a/drivers/reset/sti/reset-syscfg.c b/drivers/reset/sti/reset-syscfg.c
new file mode 100644
index 0000000..a145cc0
--- /dev/null
+++ b/drivers/reset/sti/reset-syscfg.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ *
+ * Inspired by mach-imx/src.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+#include "reset-syscfg.h"
+
+/**
+ * Reset channel regmap configuration
+ *
+ * @reset: regmap field for the channel's reset bit.
+ * @ack: regmap field for the channel's ack bit (optional).
+ */
+struct syscfg_reset_channel {
+ struct regmap_field *reset;
+ struct regmap_field *ack;
+};
+
+/**
+ * A reset controller which groups together a set of related reset bits, which
+ * may be located in different system configuration registers.
+ *
+ * @rst: base reset controller structure.
+ * @active_low: are the resets in this controller active low, i.e. clearing
+ * the reset bit puts the hardware into reset.
+ * @channels: An array of reset channels for this controller.
+ */
+struct syscfg_reset_controller {
+ struct reset_controller_dev rst;
+ bool active_low;
+ struct syscfg_reset_channel *channels;
+};
+
+#define to_syscfg_reset_controller(_rst) \
+ container_of(_rst, struct syscfg_reset_controller, rst)
+
+static int syscfg_reset_program_hw(struct reset_controller_dev *rcdev,
+ unsigned long idx, int assert)
+{
+ struct syscfg_reset_controller *rst = to_syscfg_reset_controller(rcdev);
+ const struct syscfg_reset_channel *ch;
+ u32 ctrl_val = rst->active_low ? !assert : !!assert;
+ int err;
+
+ if (idx >= rcdev->nr_resets)
+ return -EINVAL;
+
+ ch = &rst->channels[idx];
+
+ err = regmap_field_write(ch->reset, ctrl_val);
+ if (err)
+ return err;
+
+ if (ch->ack) {
+ unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+ u32 ack_val;
+
+ while (true) {
+ err = regmap_field_read(ch->ack, &ack_val);
+ if (err)
+ return err;
+
+ if (ack_val == ctrl_val)
+ break;
+
+ if (time_after(jiffies, timeout))
+ return -ETIME;
+
+ cpu_relax();
+ }
+ }
+
+ return 0;
+}
+
+static int syscfg_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return syscfg_reset_program_hw(rcdev, idx, true);
+}
+
+static int syscfg_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return syscfg_reset_program_hw(rcdev, idx, false);
+}
+
+static int syscfg_reset_dev(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ int err = syscfg_reset_assert(rcdev, idx);
+ if (err)
+ return err;
+
+ return syscfg_reset_deassert(rcdev, idx);
+}
+
+static struct reset_control_ops syscfg_reset_ops = {
+ .reset = syscfg_reset_dev,
+ .assert = syscfg_reset_assert,
+ .deassert = syscfg_reset_deassert,
+};
+
+static int syscfg_reset_controller_register(struct device *dev,
+ const struct syscfg_reset_controller_data *data)
+{
+ struct syscfg_reset_controller *rc;
+ size_t size;
+ int i, err;
+
+ rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
+ if (!rc)
+ return -ENOMEM;
+
+ size = sizeof(struct syscfg_reset_channel) * data->nr_channels;
+
+ rc->channels = devm_kzalloc(dev, size, GFP_KERNEL);
+ if (!rc->channels)
+ return -ENOMEM;
+
+ rc->rst.ops = &syscfg_reset_ops,
+ rc->rst.of_node = dev->of_node;
+ rc->rst.nr_resets = data->nr_channels;
+ rc->active_low = data->active_low;
+
+ for (i = 0; i < data->nr_channels; i++) {
+ struct regmap *map;
+ struct regmap_field *f;
+ const char *compatible = data->channels[i].compatible;
+
+ map = syscon_regmap_lookup_by_compatible(compatible);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ f = devm_regmap_field_alloc(dev, map, data->channels[i].reset);
+ if (IS_ERR(f))
+ return PTR_ERR(f);
+
+ rc->channels[i].reset = f;
+
+ if (!data->wait_for_ack)
+ continue;
+
+ f = devm_regmap_field_alloc(dev, map, data->channels[i].ack);
+ if (IS_ERR(f))
+ return PTR_ERR(f);
+
+ rc->channels[i].ack = f;
+ }
+
+ err = reset_controller_register(&rc->rst);
+ if (!err)
+ dev_info(dev, "registered\n");
+
+ return err;
+}
+
+int syscfg_reset_probe(struct platform_device *pdev)
+{
+ struct device *dev = pdev ? &pdev->dev : NULL;
+ const struct of_device_id *match;
+
+ if (!dev || !dev->driver)
+ return -ENODEV;
+
+ match = of_match_device(dev->driver->of_match_table, dev);
+ if (!match || !match->data)
+ return -EINVAL;
+
+ return syscfg_reset_controller_register(dev, match->data);
+}
diff --git a/drivers/reset/sti/reset-syscfg.h b/drivers/reset/sti/reset-syscfg.h
new file mode 100644
index 0000000..2cc2283
--- /dev/null
+++ b/drivers/reset/sti/reset-syscfg.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author: Stephen Gallimore <stephen.gallimore@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __STI_RESET_SYSCFG_H
+#define __STI_RESET_SYSCFG_H
+
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+/**
+ * Reset channel description for a system configuration register based
+ * reset controller.
+ *
+ * @compatible: Compatible string of the syscon regmap containing this
+ * channel's control and ack (status) bits.
+ * @reset: Regmap field description of the channel's reset bit.
+ * @ack: Regmap field description of the channel's acknowledge bit.
+ */
+struct syscfg_reset_channel_data {
+ const char *compatible;
+ struct reg_field reset;
+ struct reg_field ack;
+};
+
+#define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \
+ { .compatible = _c, \
+ .reset = REG_FIELD(_rr, _rb, _rb), \
+ .ack = REG_FIELD(_ar, _ab, _ab), }
+
+#define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \
+ { .compatible = _c, \
+ .reset = REG_FIELD(_rr, _rb, _rb), }
+
+/**
+ * Description of a system configuration register based reset controller.
+ *
+ * @wait_for_ack: The controller will wait for reset assert and de-assert to
+ * be "ack'd" in a channel's ack field.
+ * @active_low: Are the resets in this controller active low, i.e. clearing
+ * the reset bit puts the hardware into reset.
+ * @nr_channels: The number of reset channels in this controller.
+ * @channels: An array of reset channel descriptions.
+ */
+struct syscfg_reset_controller_data {
+ bool wait_for_ack;
+ bool active_low;
+ int nr_channels;
+ const struct syscfg_reset_channel_data *channels;
+};
+
+/**
+ * syscfg_reset_probe(): platform device probe function used by syscfg
+ * reset controller drivers. This registers a reset
+ * controller configured by the OF match data for
+ * the compatible device which should be of type
+ * "struct syscfg_reset_controller_data".
+ *
+ * @pdev: platform device
+ */
+int syscfg_reset_probe(struct platform_device *pdev);
+
+#endif /* __STI_RESET_SYSCFG_H */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 0/6] ARM: STi reset controller support
From: srinivas.kandagatla at st.com @ 2014-02-03 14:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389696613-19683-1-git-send-email-srinivas.kandagatla@st.com>
From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Hi All,
This patch series adds reset controller support for STi SOC series STiH415 and
STiH416. It adds support for both power down reset and soft reset controllers.
On STi series SOCs reset lines are wired up to system configuration registers.
Most of the IPs on STi SOCs are left in reset state, so this driver is very
important for other drivers to use the IPs.
Patch 01: Adds reset controller based on system configuration registers via
regmap.
Patch 02, 03: adds STiH415 and STiH416 reset controller drivers.
Patch 04, 05: adds STiH415 and STiH416 soft reset controllers.
The final patch 06 selects reset controller in mach-sti Kconfig.
I would like get this driver in to 3.15, so that its possible to add dt
support for other IPs with reset lines. Without this patchset its impossible
to add DT support to IPs with reset lines as reset line definition is in
common header file in include/dt-bindings/.
This reset controller will be used by gmac, i2c and st-ir drivers.
Comments?
Changes since v1:
- Added all the softreset lines.
- rebased to v3.14-rc1.
Thanks,
srini
Srinivas Kandagatla (2):
drivers: reset: stih415: add softreset controller
drivers: reset: stih416: add softreset controller
Stephen Gallimore (4):
drivers: reset: STi SoC system configuration reset controller support
drivers: reset: Reset controller driver for STiH415
drivers: reset: Reset controller driver for STiH416
ARM: STi: Add reset controller support to mach-sti Kconfig
.../devicetree/bindings/reset/st,sti-powerdown.txt | 47 +++++
.../devicetree/bindings/reset/st,sti-softreset.txt | 46 +++++
arch/arm/boot/dts/stih415.dtsi | 11 ++
arch/arm/boot/dts/stih416.dtsi | 11 ++
arch/arm/mach-sti/Kconfig | 3 +
drivers/reset/Kconfig | 2 +
drivers/reset/Makefile | 1 +
drivers/reset/sti/Kconfig | 15 ++
drivers/reset/sti/Makefile | 4 +
drivers/reset/sti/reset-stih415.c | 112 ++++++++++++
drivers/reset/sti/reset-stih416.c | 143 +++++++++++++++
drivers/reset/sti/reset-syscfg.c | 186 ++++++++++++++++++++
drivers/reset/sti/reset-syscfg.h | 69 ++++++++
.../dt-bindings/reset-controller/stih415-resets.h | 26 +++
.../dt-bindings/reset-controller/stih416-resets.h | 50 ++++++
15 files changed, 726 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
create mode 100644 Documentation/devicetree/bindings/reset/st,sti-softreset.txt
create mode 100644 drivers/reset/sti/Kconfig
create mode 100644 drivers/reset/sti/Makefile
create mode 100644 drivers/reset/sti/reset-stih415.c
create mode 100644 drivers/reset/sti/reset-stih416.c
create mode 100644 drivers/reset/sti/reset-syscfg.c
create mode 100644 drivers/reset/sti/reset-syscfg.h
create mode 100644 include/dt-bindings/reset-controller/stih415-resets.h
create mode 100644 include/dt-bindings/reset-controller/stih416-resets.h
--
1.7.9.5
^ permalink raw reply
* [PATCH v5 05/16] ARM: use a function table for determining instruction interpreter action
From: Jon Medhurst (Tixy) @ 2014-02-03 14:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390507559-4697-6-git-send-email-dave.long@linaro.org>
On Thu, 2014-01-23 at 15:05 -0500, David Long wrote:
> From: "David A. Long" <dave.long@linaro.org>
>
> Make the instruction interpreter call back to semantic action functions
> through a function pointer array provided by the invoker. The interpreter
> decodes the instructions into groups and uses the group number to index
> into the supplied array. kprobes and uprobes code will each supply their
> own array of functions.
>
> Signed-off-by: David A. Long <dave.long@linaro.org>
> ---
[...]
> --- a/arch/arm/kernel/probes.c
> +++ b/arch/arm/kernel/probes.c
> @@ -378,10 +378,11 @@ static const int decode_struct_sizes[NUM_DECODE_TYPES] = {
> */
> int __kprobes
> kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
> - const union decode_item *table, bool thumb)
> + const union decode_item *table, bool thumb,
> + const union decode_action *actions)
> {
> - const struct decode_header *h = (struct decode_header *)table;
> - const struct decode_header *next;
> + struct decode_header *h = (struct decode_header *)table;
> + struct decode_header *next;
The decode tables are fixed structures which nothing should want to
modify, so I think the const's above should be kept. I believe that
you've had to resort to changing them because the following typedef
lacks a 'const' on the final argument....
[...]
> diff --git a/arch/arm/kernel/probes.h b/arch/arm/kernel/probes.h
> index c610fa9..81b6e61 100644
[...]
>
> +typedef enum kprobe_insn (probes_custom_decode_t)(kprobe_opcode_t,
> + struct arch_specific_insn *,
> + struct decode_header *);
> +
Adding 'const' above will also have the knock on effect of requiring
const on all the 'custom decode' functions as well.
--
Tixy
^ permalink raw reply
* NFS client broken in Linus' tip
From: Takashi Iwai @ 2014-02-03 14:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5ACE0C45-BEFA-47A8-9195-F3AB36C27752@primarydata.com>
At Mon, 3 Feb 2014 09:21:16 -0500,
Trond Myklebust wrote:
>
>
> On Feb 3, 2014, at 4:43, Takashi Iwai <tiwai@suse.de> wrote:
>
> > At Sun, 02 Feb 2014 17:04:38 -0500,
> > Trond Myklebust wrote:
> >>
> >> On Sun, 2014-02-02 at 12:27 +0000, Russell King - ARM Linux wrote:
> >>> On Sat, Feb 01, 2014 at 01:03:28AM +0000, Russell King - ARM Linux wrote:
> >>>> On Fri, Jan 31, 2014 at 03:59:30PM -0500, Trond Myklebust wrote:
> >>>>> On Thu, 2014-01-30 at 15:38 +0000, Russell King - ARM Linux wrote:
> >>>>>> On Thu, Jan 30, 2014 at 06:32:08AM -0800, Christoph Hellwig wrote:
> >>>>>>> On Thu, Jan 30, 2014 at 02:27:52PM +0000, Russell King - ARM Linux wrote:
> >>>>>>>> Yes and no. I still end up with an empty /etc/mtab, but the file now
> >>>>>>>> exists. However, I can create and echo data into /etc/mtab, but it seems
> >>>>>>>> that can't happen at boot time.
> >>>>>>>
> >>>>>>> Odd. Can you disable CONFIG_NFSD_V3_ACL for now to isolate the issue?
> >>>>>>
> >>>>>> Unfortunately, that results in some problem at boot time, which
> >>>>>> ultimately ends up with the other three CPUs being stopped, and
> >>>>>> hence the original reason scrolls off the screen before it can be
> >>>>>> read... even at 1920p.
> >>>>>>
> >>>>> Hi Russell,
> >>>>>
> >>>>> The following patch fixes the issue for me.
> >>>>
> >>>> It doesn't entirely fix the issue for me, instead we've got even weirder
> >>>> behaviour:
> >>>>
> >>>> root at cubox-i4:~# ls -al test
> >>>> ls: cannot access test: No such file or directory
> >>>> root at cubox-i4:~# touch test
> >>>> root at cubox-i4:~# ls -al test
> >>>> -rw-r--r-- 1 root root 0 Feb 1 01:01 test
> >>>> root at cubox-i4:~# echo foo > test
> >>>> root at cubox-i4:~# ls -al test
> >>>> -rw-r--r-- 1 root root 4 Feb 1 01:01 test
> >>>> root at cubox-i4:~# cat test
> >>>> foo
> >>>> root at cubox-i4:~# rm test
> >>>> root at cubox-i4:~# echo foo > test
> >>>> -bash: test: Operation not supported
> >>>> root at cubox-i4:~# ls -al test
> >>>> -rw-r--r-- 1 root root 0 Feb 1 01:01 test
> >>>
> >>> FYI, I just tested Linus' tip, and NFS is still broken.
> >>>
> >> Hi Russell,
> >>
> >> The following patch should fix the above problem. It needs to be applied
> >> on top of the one I sent you previously.
> >
> > I've hit the same problem, and your two patches seem fixing it.
> > I tested them on top of 3.14-rc1. Feel free to take my tested-by tag
> >
> > Tested-by: Takashi Iwai <tiwai@suse.de>
> >
> >
> >> In addition, you will want to
> >> apply Noah Massey's patch from
> >> http://lkml.kernel.org/r/1391135472-9639-1-git-send-email-Noah.Massey at gmail.com
> >
> > Do I still need to test this one, too?
> >
>
> Hi Takashi,
>
> Noah?s patch is not a replacement for the above 2 patches; it fixes a different problem. All three patches are therefore required for a complete solution.
OK, I'll test with Noah's patch.
thanks,
Takashi
^ permalink raw reply
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