* [PATCH v4] of: add functions to count number of elements in a property
From: Heiko Stübner @ 2014-02-04 18:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204173034.2D899C4050F@trevor.secretlab.ca>
Hi Grant,
On Tuesday, 4. February 2014 17:30:34 Grant Likely wrote:
> On Sat, 18 Jan 2014 09:07:30 -0600, Rob Herring <robherring2@gmail.com>
wrote:
> > On Sat, Jan 18, 2014 at 6:02 AM, Heiko St??bner <heiko@sntech.de> wrote:
> > > The need to know the number of array elements in a property is
> > > a common pattern. To prevent duplication of open-coded implementations
> > > add a helper static function that also centralises strict sanity
> > > checking and DTB format details, as well as a set of wrapper functions
> > > for u8, u16, u32 and u64.
> > >
> > > Suggested-by: Mark Rutland <mark.rutland@arm.com>
> > > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > > ---
> >
> > Looks good. Do you plan to convert some users to use this?
>
> I'll take that as an acked-by. Merged, thanks.
before you taking this patch, I was planning on simply sending this as part of
my rockchip-smp series - as I'm currently the only user of it :-) .
This going through your tree is most likely the better way, but now I need it
to somehow make its way into arm-soc too ... I guess some sort of stable
branch arm-soc could pull?
Thanks
Heiko
^ permalink raw reply
* [PATCH resend 1/2] arm64: defer reloading a task's FPSIMD state to userland resume
From: Ard Biesheuvel @ 2014-02-04 18:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204172737.GD664@mudshark.cambridge.arm.com>
On 4 February 2014 18:27, Will Deacon <will.deacon@arm.com> wrote:
> Hello,
>
> On Tue, Feb 04, 2014 at 02:49:14PM +0000, Ard Biesheuvel wrote:
>> On 3 February 2014 17:36, Will Deacon <will.deacon@arm.com> wrote:
>> > On Fri, Jan 31, 2014 at 10:13:15AM +0000, Ard Biesheuvel wrote:
>> >> If a task gets scheduled out and back in again and nothing has touched
>> >> its FPSIMD state in the mean time, there is really no reason to reload
>> >> it from memory. Similarly, repeated calls to kernel_neon_begin() and
>> >> kernel_neon_end() will preserve and restore the FPSIMD state every time.
>> >>
>> >> This patch defers the FPSIMD state restore to the last possible moment,
>> >> i.e., right before the task re-enters userland. If a task does not enter
>> >> userland at all (for any reason), the existing FPSIMD state is preserved
>> >> and may be reused by the owning task if it gets scheduled in again on the
>> >> same CPU.
>> >
>> > The one situation I'm unsure of here is how you deal with the saved fpsimd
>> > state potentially being updated by a signal handler or a debugger. In this
>> > case, we probably need to set _TIF_FOREIGN_FPSTATE to force a reload, or are
>> > you handling this some other way?
>> >
>>
>> If I am reading the code correctly, the signal handler is entered
>> using the normal userland resume path, so I don't think it requires
>> special treatment.
>
> It was the exiting of the signal handler that I was worried about, where it
> may have modified the interrupted programs fpsimd state on the stack.
>
Ah, ok, I see what you mean.
I will update the patch so
(a) it only saves the state if _TIF_FOREIGN_FPSTATE is cleared (so we
don't overwrite the task's saved state inadvertently), and
(b) it sets _TIF_FOREIGN_FPSTATE instead of performing the restore
upon return from the signal handler.
>> For the ptrace() case, it should suffice to set the 'last_cpu' field
>> to (u32)-1 to indicate that the FPSIMD context should be reloaded from
>> memory regardless of which CPU the debuggee is restarted on.
>
> Something like that sounds right, but it needs adding/testing.
>
OK, I will add the above and do some more testing.
Cheers,
Ard.
^ permalink raw reply
* [PATCH 00/17] amba: PM fixups for amba bus and some amba drivers
From: Mark Brown @ 2014-02-04 18:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391529538-21685-1-git-send-email-ulf.hansson@linaro.org>
On Tue, Feb 04, 2014 at 04:58:41PM +0100, Ulf Hansson wrote:
> The fixes for the amba bus needs to be merged prior to the other, thus I think
> it could make sense to merge this complete patchset through Russell's tree,
> if he and the other maintainers think this is okay.
What are the actual dependencies for the SPI bit? AFAICT it's probably
the first patch needs the bus updating?
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^ permalink raw reply
* [PATCH 00/11] ARM: shmobile: RSPI RZ and QSPI SoC and board integration
From: Geert Uytterhoeven @ 2014-02-04 18:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204173733.GI22609@sirena.org.uk>
Hi Mark,
On Tue, Feb 4, 2014 at 6:37 PM, Mark Brown <broonie@kernel.org> wrote:
> On Tue, Feb 04, 2014 at 04:23:54PM +0100, Geert Uytterhoeven wrote:
>> Hi Simon, Magnus,
>>
>> This patch series contains SoC and board integration for
>> 1. RSPI in the r7s72100 aka RZ/A1H SoC on the Genmai reference board,
>> 2. QSPI in the r8a7791 aka R-Car M2 SoC on the Koelsch reference board.
>> It was rebased on top of renesas-devel-v3.14-rc1-20140204.
>
> Can you please stop CCing arch/arm only patch serieses like this to the
> SPI list - they just mean I have to go through patchwork and mark them
> as not applicable.
Sorry, you're right. Only a few of them contained SPI-specific code.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* arm64: kernel panic in paging_init()
From: Mark Salter @ 2014-02-04 18:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204121452.GI30676@arm.com>
On Tue, 2014-02-04 at 12:14 +0000, Catalin Marinas wrote:
> On Mon, Feb 03, 2014 at 08:50:49PM +0000, Mark Salter wrote:
> > I'm seeing the following panic in paging init. This is on the foundation
> > model with a modified dtb memory node which has a non section-aligned
> > bank:
> > memory at 80000000 {
> > device_type = "memory";
> > reg = <0x00000000 0x80000000 0 0x20000000>,
> > <0x00000000 0xa0300000 0 0x1fd00000>;
> > };
> >
> > I only see this with 64k pagesize configured. What happens is the
> > non section-aligned bank causes alloc_init_pte() to allocate a page
> > for the new pte from the end of the first bank (the failing address
> > 0xfffffe001fff0000 [0x9fff0000 phys]). This should be a valid page
> > since it was mapped during the create_mapping() call for the first
> > memory bank. A flush_tlb_all() added to the end of create_mapping()
> > makes the panic go away so I think the problem is something stale
> > cached before the page with the failing address was mapped.
>
> I think it goes like this:
>
> head.S maps enough memory to get started but using 64K pages rather than
> 512M sections with a single pgd entry and several ptes. This never gets
> to the end of the first block (just up to KERNEL_END).
>
> create_mapping() realises it can do a 512M section mapping, overriding
> the original table pgd entry with a block one. The memblock limit is set
> correctly PGDIR_SIZE but create_mapping, when it replaces the table pgd
> with a block one doesn't do any TLB invalidation.
>
> So I wouldn't do a TLB invalidation all the time but only when the old
> pmd was set. Please give the patch below a try, I only compiled it (I'll
> add some text afterwards):
Yes, that works. Thanks.
>
> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> index f557ebbe7013..f8dc7e8fce6f 100644
> --- a/arch/arm64/mm/mmu.c
> +++ b/arch/arm64/mm/mmu.c
> @@ -203,10 +203,18 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
> do {
> next = pmd_addr_end(addr, end);
> /* try section mapping first */
> - if (((addr | next | phys) & ~SECTION_MASK) == 0)
> + if (((addr | next | phys) & ~SECTION_MASK) == 0) {
> + pmd_t old_pmd =*pmd;
> set_pmd(pmd, __pmd(phys | prot_sect_kernel));
> - else
> + /*
> + * Check for previous table entries created during
> + * boot (__create_page_tables) and flush them.
> + */
> + if (!pmd_none(old_pmd))
> + flush_tlb_all();
> + } else {
> alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys));
> + }
> phys += next - addr;
> } while (pmd++, addr = next, addr != end);
> }
>
>
> Thanks.
>
^ permalink raw reply
* [PATCH] dma: mv_xor: Silence a bunch of LPAE-related warnings
From: Dan Williams @ 2014-02-04 18:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOesGMg0mrikAp7cDkm9+5=TfR7bj7_f4=JPMxBbabEPwkQs9Q@mail.gmail.com>
On Tue, Feb 4, 2014 at 10:30 AM, Olof Johansson <olof@lixom.net> wrote:
> On Tue, Feb 4, 2014 at 9:00 AM, Jason Cooper <jason@lakedaemon.net> wrote:
>> On Tue, Feb 04, 2014 at 10:53:29AM +0530, Vinod Koul wrote:
>>> On Mon, Feb 03, 2014 at 05:13:23PM -0800, Olof Johansson wrote:
>>> > Enabling some of the mvebu platforms in the multiplatform config for ARM
>>> > enabled these drivers, which also triggered a bunch of warnings when LPAE
>>> > is enabled (thus making phys_addr_t 64-bit).
>>> >
>>> > Most changes are switching printk formats, but also a bit of changes to what
>>> > used to be array-based pointer arithmetic that could just be done with the
>>> > address types instead.
>>> >
>>> > The warnings were:
>>> >
>>> > drivers/dma/mv_xor.c: In function 'mv_xor_tx_submit':
>>> > drivers/dma/mv_xor.c:500:3: warning: format '%x' expects argument of type
>>> > 'unsigned int', but argument 4 has type 'dma_addr_t' [-Wformat]
>>> > drivers/dma/mv_xor.c: In function 'mv_xor_alloc_chan_resources':
>>> > drivers/dma/mv_xor.c:553:13: warning: cast to pointer from integer of
>>> > different size [-Wint-to-pointer-cast]
>>> > drivers/dma/mv_xor.c:555:4: warning: cast from pointer to integer of
>>> > different size [-Wpointer-to-int-cast]
>>> > drivers/dma/mv_xor.c: In function 'mv_xor_prep_dma_memcpy':
>>> > drivers/dma/mv_xor.c:584:2: warning: format '%x' expects argument of type
>>> > 'unsigned int', but argument 5 has type 'dma_addr_t' [-Wformat]
>>> > drivers/dma/mv_xor.c:584:2: warning: format '%x' expects argument of type
>>> > 'unsigned int', but argument 6 has type 'dma_addr_t' [-Wformat]
>>> > drivers/dma/mv_xor.c: In function 'mv_xor_prep_dma_xor':
>>> > drivers/dma/mv_xor.c:628:2: warning: format '%u' expects argument of type
>>> > 'unsigned int', but argument 7 has type 'dma_addr_t' [-Wformat]
>>> >
>>> > Signed-off-by: Olof Johansson <olof@lixom.net>
>>> Acked-by: Vinod Koul <vinod.koul@intel.com>
>>
>> Olof, would you like me to queue it up? Or do you want to take it
>> directly?
>>
>> Acked-by: Jason Cooper <jason@lakedaemon.net>
>
> I'm confused. I sent the patch to the drivers/dma maintainers and they
> just acked it without asking me to pick it up myself.
>
> Vinod, did you ack it for me to pick it up, or for some other reason?
> If you don't want to take it through your tree I'll be happy to take
> it through arm-soc, just looking to clarify.
>
> (Jason, I can apply it directly)
Vinod will correct me if I am wrong, but I take his acks to mean "yup,
take it through your tree". For this specific problem I thought we
had a comprehensive fix pending from Joe Perches to add a new %pX
format specifier for dma addresses?
^ permalink raw reply
* [PATCH] dma: mv_xor: Silence a bunch of LPAE-related warnings
From: Dan Williams @ 2014-02-04 18:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAPcyv4jwwRT_+c-yDycgY0d79nByvAVWH6waFWeodE9yi=7CDg@mail.gmail.com>
On Tue, Feb 4, 2014 at 10:57 AM, Dan Williams <dan.j.williams@intel.com> wrote:
> On Tue, Feb 4, 2014 at 10:30 AM, Olof Johansson <olof@lixom.net> wrote:
>> On Tue, Feb 4, 2014 at 9:00 AM, Jason Cooper <jason@lakedaemon.net> wrote:
>>> On Tue, Feb 04, 2014 at 10:53:29AM +0530, Vinod Koul wrote:
>>>> On Mon, Feb 03, 2014 at 05:13:23PM -0800, Olof Johansson wrote:
>>>> > Enabling some of the mvebu platforms in the multiplatform config for ARM
>>>> > enabled these drivers, which also triggered a bunch of warnings when LPAE
>>>> > is enabled (thus making phys_addr_t 64-bit).
>>>> >
>>>> > Most changes are switching printk formats, but also a bit of changes to what
>>>> > used to be array-based pointer arithmetic that could just be done with the
>>>> > address types instead.
>>>> >
>>>> > The warnings were:
>>>> >
>>>> > drivers/dma/mv_xor.c: In function 'mv_xor_tx_submit':
>>>> > drivers/dma/mv_xor.c:500:3: warning: format '%x' expects argument of type
>>>> > 'unsigned int', but argument 4 has type 'dma_addr_t' [-Wformat]
>>>> > drivers/dma/mv_xor.c: In function 'mv_xor_alloc_chan_resources':
>>>> > drivers/dma/mv_xor.c:553:13: warning: cast to pointer from integer of
>>>> > different size [-Wint-to-pointer-cast]
>>>> > drivers/dma/mv_xor.c:555:4: warning: cast from pointer to integer of
>>>> > different size [-Wpointer-to-int-cast]
>>>> > drivers/dma/mv_xor.c: In function 'mv_xor_prep_dma_memcpy':
>>>> > drivers/dma/mv_xor.c:584:2: warning: format '%x' expects argument of type
>>>> > 'unsigned int', but argument 5 has type 'dma_addr_t' [-Wformat]
>>>> > drivers/dma/mv_xor.c:584:2: warning: format '%x' expects argument of type
>>>> > 'unsigned int', but argument 6 has type 'dma_addr_t' [-Wformat]
>>>> > drivers/dma/mv_xor.c: In function 'mv_xor_prep_dma_xor':
>>>> > drivers/dma/mv_xor.c:628:2: warning: format '%u' expects argument of type
>>>> > 'unsigned int', but argument 7 has type 'dma_addr_t' [-Wformat]
>>>> >
>>>> > Signed-off-by: Olof Johansson <olof@lixom.net>
>>>> Acked-by: Vinod Koul <vinod.koul@intel.com>
>>>
>>> Olof, would you like me to queue it up? Or do you want to take it
>>> directly?
>>>
>>> Acked-by: Jason Cooper <jason@lakedaemon.net>
>>
>> I'm confused. I sent the patch to the drivers/dma maintainers and they
>> just acked it without asking me to pick it up myself.
>>
>> Vinod, did you ack it for me to pick it up, or for some other reason?
>> If you don't want to take it through your tree I'll be happy to take
>> it through arm-soc, just looking to clarify.
>>
>> (Jason, I can apply it directly)
>
> Vinod will correct me if I am wrong, but I take his acks to mean "yup,
> take it through your tree". For this specific problem I thought we
> had a comprehensive fix pending from Joe Perches to add a new %pX
> format specifier for dma addresses?
Never mind... that's what you are using. Sorry for the noise.
^ permalink raw reply
* [PATCH v3 2/5] ASoC: tda998x: add a codec driver for the TDA998x
From: Jean-Francois Moine @ 2014-02-04 18:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204175410.GL22609@sirena.org.uk>
On Tue, 4 Feb 2014 17:54:10 +0000
Mark Brown <broonie@kernel.org> wrote:
> On Tue, Feb 04, 2014 at 06:16:05PM +0100, Jean-Francois Moine wrote:
> > Mark Brown <broonie@kernel.org> wrote:
>
> > > > + /* load the optional CODEC */
> > > > + of_platform_populate(np, NULL, NULL, &client->dev);
>
> > > Why is this using of_platform_populate()? That's a very odd way of
> > > doing things.
>
> > The i2c does not populate the subnodes in the DT. I did not find why,
> > but, what is sure is that if of_platform_populate() is not called, the
> > tda CODEC module is not loaded.
>
> You shouldn't be representing this as a separate node in the DT unless
> there really is a distinct and reusable IP, otherwise you're putting
> Linux implementation details in there. Describe the hardware, not the
> implemementation.
If there is no 'compatible' node for the tda998x CODEC in the DT, the
simple-card is not usable, simply because you want the CODEC DAIs to be
defined by 'phandle + index' instead of by DAI name.
> > You may find an other example in drivers/mfd/twl-core.c.
>
> The TWL drivers aren't always a shining example of how to do things -
> they were one of the earliest MFDs so there's warts in there.
>
> > > > +config SND_SOC_TDA998X
> > > > + tristate
> > > > + depends on OF
> > > > + default y if DRM_I2C_NXP_TDA998X=y
> > > > + default m if DRM_I2C_NXP_TDA998X=m
>
> > > Make this visible if it can be selected from DT so it can be used with
> > > generic cards.
>
> > I don't understand. The tda CODEC can only be used with the TDA998x I2C
> > driver. It might have been included in the tda998x source as well.
>
> You shouldn't have the default settings there at all, that's not the
> normal idiom for MFDs. I'd also not expect to have to build the CODEC
> driver just because I built the DRM component.
As the tda998x handles audio in HDMI, it would be a pity if you should
connect an other cable to your screen.
> > Now, the CODEC is declared inside the tda998x as a node child. But, in
> > a bad DT, the tda CODEC could be declared anywhere, even inside a other
> > DRM I2C slave encoder, in which case, bad things would happen...
>
> So, part of the problem here is that this is being explicitly declared
> in the DT leading to more sources for error.
Simple-card constraint.
> > > What does this actually do? No information is being passed in to the
> > > core function here, not even any information on if it's starting or
> > > stopping. Looking at the rest of the code I can't help thinking it
> > > might be clearer to inline this possibly with a lookup helper, the code
> > > is very small and the lack of parameters makes it hard to follow.
>
> > I thought it was simple enough. The function tda_start_stop() is called
> > from 2 places:
>
> It's not at all obvious - _audio_update() isn't a terribly descriptive
> name, just looking at that function by itself I had no idea what it was
> supposed to be doing.
The first purpose of the function is to set the audio input port in the
tda998x. Streaming stop could have been omitted, but I thought it could
be interesting to stop HDMI audio when there is a super HiFi device
connected to the S/PDIF connector.
> > - on audio start in tda_startup with the audio type (DAI id)
> > priv->dai_id = dai->id;
>
> > - on audio stop with a null audio type
> > priv->dai_id = 0; /* streaming stop */
>
> > On stream start, the DAI id is never null, as explained in the patch 1:
>
> > The audio format values in the encoder configuration interface are
> > changed to non null values so that the value 0 is used in the audio
> > function to indicate that audio streaming is stopped.
>
> > and on streaming stop the port is not meaningful.
>
> > I will add a null item in the enum (AFMT_NO_AUDIO).
>
> So we can't use both streams simultaneously then? That's a bit sad.
That's how the NXP tda998x family works (and surely many other HDMI
transmitters).
So, as I understand from your remarks, the CODEC should be included in
the tda998x driver, and, then, as the simple-card cannot be used, there
should be a Cubox specific audio card driver for the (kirkwood audio +
tda998x HDMI + S/PDIF) set. Am I right?
--
Ken ar c'henta? | ** Breizh ha Linux atav! **
Jef | http://moinejf.free.fr/
^ permalink raw reply
* [GIT PULL] irqchip: dove: drivers for v3.14
From: Thomas Gleixner @ 2014-02-04 18:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140128173531.GT29184@titan.lakedaemon.net>
On Tue, 28 Jan 2014, Jason Cooper wrote:
> I see you pulled in mvebu/irqchip-fixes. Thanks for that. It's getting
> near to the end of the merge window and there's been no activity on this
> pull request.
>
> Please let us know if there's anything we can do to assist.
Nah. I simply forgot about it. About to send a pull request to Linus.
^ permalink raw reply
* [PATCH v3 3/5] ASoC: tda998x: add DT documentation of the tda998x CODEC
From: Jean-Francois Moine @ 2014-02-04 19:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204181213.GO22609@sirena.org.uk>
On Tue, 4 Feb 2014 18:12:13 +0000
Mark Brown <broonie@kernel.org> wrote:
> On Sat, Feb 01, 2014 at 05:48:49PM +0100, Jean-Francois Moine wrote:
>
> > + - compatible: must be "nxp,tda998x-codec".
>
> It's not clear to me why there's a separate compatible here - as far as
> I can see this can only appear as part of one of these devices and
> there's no addressing or other information that'd account for chip
> variation so I'd not expect to need to bind this independently of the
> parent.
If there is no 'compatible', the CODEC module is not loaded, and, when
the module is in the core, no CODEC device can be created from the DT.
--
Ken ar c'henta? | ** Breizh ha Linux atav! **
Jef | http://moinejf.free.fr/
^ permalink raw reply
* [GIT PULL] irqchip: dove: drivers for v3.14
From: Jason Cooper @ 2014-02-04 19:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.02.1402041959110.24986@ionos.tec.linutronix.de>
On Tue, Feb 04, 2014 at 07:59:58PM +0100, Thomas Gleixner wrote:
> On Tue, 28 Jan 2014, Jason Cooper wrote:
> > I see you pulled in mvebu/irqchip-fixes. Thanks for that. It's getting
> > near to the end of the merge window and there's been no activity on this
> > pull request.
> >
> > Please let us know if there's anything we can do to assist.
>
> Nah. I simply forgot about it. About to send a pull request to Linus.
Great, thanks!
Jason.
^ permalink raw reply
* [PATCH] regulator: core: Make regulator object reflect configured voltage
From: Bjorn Andersson @ 2014-02-04 19:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204181831.GP22609@sirena.org.uk>
On Tue, Feb 4, 2014 at 10:18 AM, Mark Brown <broonie@kernel.org> wrote:
> On Tue, Feb 04, 2014 at 10:02:14AM -0800, Bjorn Andersson wrote:
>> On Tue, Feb 4, 2014 at 3:05 AM, Mark Brown <broonie@kernel.org> wrote:
>
>> > Why not do this at the time we apply the voltage? That would seem to be
>> > more robust, doing it in a separate place means that we might update one
>> > bit of code and not the other or might change the execution path so that
>> > one gets run and the other doesn't.
>
>> I do share your concerns about having this logic mirrored here is
>> risky, unfortunately the regulator object is created upon request from
>> a consumer; so it is not available when regulator_register() calls
>> set_machine_constraints().
>
> Oh, hang on - that's what you mean by a regulator object... I don't
> think this fixes the problem you think it does. What is the actual
> problem you're trying to fix here? The min_uV and max_uV on a consumer
> struct are supposed to be the request from that consumer, they should
> only be set if the consumer actually made a request for a voltage range.
I have a regulator that's being configured from DT as:
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
In the consumer I do regulator_set_voltage(2.95V).
As min == max the voltage is applied by the regulator framework on registration
of the regulator; and the regulator_set_voltage() fails as
REGULATOR_CHANGE_VOLTAGE is not set for this regulator.
This makes sense, until I change regulator-min-microvolt to say 2000000 then
the regulator_set_voltage() succeeds; and the call is required for the device to
function properly.
So in the consumer I get different behavior depending on how the regulator is
configured in DT.
The proposed fix solves this by making the consumer object aware of
the initialized
voltage (as it's fixed in this case), making it okay for calls to
regulator_set_voltage()
given that it's the same value as the configured value; failing for others.
>
>> An alternative is to drop the conditional setting of
>> REGULATOR_CHANGE_VOLTAGE from of_regulator.c and force the regulator
>> drivers to set this flag explicitly; to avoid the difference in
>> behavior depending on configuration.
>
> Why would having each individual driver open code things help?
Without this fix I explicitly need to add REGULATOR_CHANGE_VOLTAGE to the
valid_ops_mask of my regulators, ignoring the fact that
of_get_regulation_constraints()
does apply some logic in this area.
Regards,
Bjorn
^ permalink raw reply
* [PATCH] arm64: Add architecture support for PCI
From: Jason Gunthorpe @ 2014-02-04 19:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8676627.b6SYsazoah@wuerfel>
On Tue, Feb 04, 2014 at 07:34:50PM +0100, Arnd Bergmann wrote:
> Well, the way I see it, we already have support for arbitrary
> PCI domains in the kernel, and that works fine, so we can just
> as well use it. That way we don't have to partition the available
> 256 buses among the host bridges, and anything that needs a separate
> PCI config space can live in its own world. Quite often when you
> have multiple PCI hosts, they actually have different ways to
> get at the config space and don't even share the same driver.
> On x86, any kind of HT/PCI/PCIe/PCI-x bridge is stuffed into a
> single domain so they can support OSs that only know the
> traditional config space access methods, but I don't see
> any real advantage to that for other architectures.
Supporting a standard configration interface is a solid reason, but
there is alot more going on.
For instance to support peer-to-peer IO you need to have a consisent,
non-overlapping set of bus/device/function/tag to uniquely route TLPs
within the chip. Cross domain TLP routing in HW is non-trivial.
IOMMUs (and SR-IOv) rely on the BDF to identify the originating device
for each TLP. Multiple domains means a much more complex IOMMU
environment.
Failure to integrate on-chip devices into the PCI world also means
thing like SR-IOv won't work sanely with on-chip devices.
The only reason we should see multi-domain on a SOC is because the HW
design was lazy. Being lazy misses the Big Picture where PCI is the
cornerstone of many important Server/Enterprise technologies.
> > SOC internal peripherals should all show up in the bus 0 config space
> > of the only domain and SOC PCI-E physical ports should show up on bus
> > 0 as PCI-PCI bridges. This is all covered in the PCI-E specs regarding
> > the root complex.
> >
> > Generally I would expect the internal peripherals to still be
> > internally connected with AXI, but also connected through the ECAM
> > space for configuration, control, power management and address
> > assignment.
>
> That would of course be very nice from a software perspective,
> but I think that is much less likely for any practical
> implementation.
Well, all x86 implementations do this already.. It actually isn't that
big a deal from a HW perspective, you just have to think about it
fully, understand PCI, and position your registers accordingly.
Jason
^ permalink raw reply
* [PATCH 2/3] PCI: ARM: add support for virtual PCI host controller
From: Arnd Bergmann @ 2014-02-04 19:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391532784-1953-3-git-send-email-will.deacon@arm.com>
On Tuesday 04 February 2014 16:53:03 Will Deacon wrote:
> +
> +- ranges : As described in IEEE Std 1275-1994, but must provide
> + at least a definition of the Configuration Space plus
> + one or both of IO and Memory Space.
> +
I might need to reread the spec, but I think the config space is not
actually supposed to be in the 'ranges' of the host bridge at all,
and it should just be listed in the 'reg'.
IIRC the reason why the config space is part of the three-cell address
is so that you can have funky ways to say "memory space of the device
with bus/dev/fn is actually translated to address X rather then Y".
It's too late to change that for the other drivers now, after the
binding is established.
> +Configuration Space is assumed to be memory-mapped (as opposed to being
> +accessed via an ioport) and laid out with a direct correspondence to the
> +geography of a PCI bus address, by concatenating the various components
> +to form a 24-bit offset:
> +
> + cfg_offset(bus, device, function, register) =
> + bus << 16 | device << 11 | function << 8 | register
This won't allow extended config space. Why not just do the
regular mmconfig layout and make this:
cfg_offset(bus, device, function, register) =
bus << 20 | device << 15 | function << 12 | register;
> +static int virt_pci_setup(int nr, struct pci_sys_data *sys)
> +{
> + struct virt_pci *pci = sys->private_data;
> +
> + if (resource_type(&pci->io)) {
> + pci_add_resource(&sys->resources, &pci->io);
> + pci_ioremap_io(nr * resource_size(&pci->io), pci->io.start);
> + }
This should really compute an io_offset.
> + if (resource_type(&pci->mem))
> + pci_add_resource(&sys->resources, &pci->mem);
and also a mem_offset, which is something different.
> + pci->cfg_base = devm_ioremap_resource(pci->dev, &pci->cfg);
> + return !IS_ERR(pci->cfg_base);
> +}
> +
> +static const struct of_device_id virt_pci_of_match[] = {
> + { .compatible = "linux,pci-virt" },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, virt_pci_of_match);
I don't think we even want "virt" in the compatible string. The
binding should be generic enough that it can actually work with
real hardware.
> + for_each_of_pci_range(&parser, &range) {
> + u32 restype = range.flags & IORESOURCE_TYPE_BITS;
> +
> + switch (restype) {
> + case IORESOURCE_IO:
> + if (resource_type(&pci->io))
> + dev_warn(dev,
> + "ignoring additional io resource\n");
> + else
> + of_pci_range_to_resource(&range, np, &pci->io);
> + break;
> + case IORESOURCE_MEM:
> + if (resource_type(&pci->mem))
> + dev_warn(dev,
> + "ignoring additional mem resource\n");
> + else
> + of_pci_range_to_resource(&range, np, &pci->mem);
> + break;
This shows once more that the range parser code is suboptimal. So far
every single driver got the I/O space wrong here, because the obvious
way to write this function is also completely wrong.
What you get out of "of_pci_range_to_resource(&range, np, &pci->io)"
is not the resource you want to pass into pci_add_resource()
later.
> + memset(&hw, 0, sizeof(hw));
> + hw.nr_controllers = 1;
> + hw.private_data = (void **)&pci;
> + hw.setup = virt_pci_setup;
> + hw.map_irq = of_irq_parse_and_map_pci;
> + hw.ops = &virt_pci_ops;
> + pci_common_init_dev(dev, &hw);
Since most fields here are constant, I'd just write this as
struct hw_pci hw = {
.nr_controllers = 1,
.setup = virt_pci_setup,
...
};
Arnd
^ permalink raw reply
* [PATCH] ARM: footbridge: Switch to sched_clock_register()
From: Stephen Boyd @ 2014-02-04 19:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389922207-5154-1-git-send-email-sboyd@codeaurora.org>
On 01/16, Stephen Boyd wrote:
> The 32 bit sched_clock interface supports 64 bits since 3.13-rc1.
> Upgrade to the 64 bit function to allow us to remove the 32 bit
> registration interface.
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Russell,
Can you please apply this for 3.14? This is the last user of the
deprecated interface in linus' tree. Once this is merged I will
remove setup_sched_clock(). It's 7945/1 in the patch tracker.
>
> Based on rmk/for-next
>
> arch/arm/mach-footbridge/dc21285-timer.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
> index 3971104d32d4..5d2725fd878c 100644
> --- a/arch/arm/mach-footbridge/dc21285-timer.c > +++ b/arch/arm/mach-footbridge/dc21285-timer.c
> @@ -125,7 +125,7 @@ void __init footbridge_timer_init(void)
> clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
> }
>
> -static u32 notrace footbridge_read_sched_clock(void)
> +static u64 notrace footbridge_read_sched_clock(void)
> {
> return ~*CSR_TIMER3_VALUE;
> }
> @@ -138,5 +138,5 @@ void __init footbridge_sched_clock(void)
> *CSR_TIMER3_CLR = 0;
> *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
>
> - setup_sched_clock(footbridge_read_sched_clock, 24, rate);
> + sched_clock_register(footbridge_read_sched_clock, 24, rate);
> }
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* [PATCH 07/17] spi: pl022: Don't ignore power domain and amba bus at system suspend
From: Mark Brown @ 2014-02-04 19:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391529538-21685-8-git-send-email-ulf.hansson@linaro.org>
On Tue, Feb 04, 2014 at 04:58:48PM +0100, Ulf Hansson wrote:
> @@ -2328,8 +2300,23 @@ static int pl022_suspend(struct device *dev)
> return ret;
> }
>
> - pm_runtime_get_sync(dev);
> - pl022_suspend_resources(pl022, false);
> + pm_runtime_disable(dev);
> +
> + if (!pm_runtime_status_suspended(dev)) {
> + if (dev->pm_domain && dev->pm_domain->ops.runtime_suspend)
> + ret = dev->pm_domain->ops.runtime_suspend(dev);
> + else
> + ret = dev->bus->pm->runtime_suspend(dev);
> +
> + if (ret) {
> + pm_runtime_enable(dev);
> + return ret;
> + }
> +
> + pm_runtime_set_suspended(dev);
> + }
This seems like a fairly hideous thing to be having to open code in an
individual driver, it all looks generic and like something that most if
not all devices ought to be doing and it looks very vulnerable to being
broken by changes in the core. At the very least I would expect this to
be done in a helper function, though it would be even nicer if the
driver core were figuring this stuff out for us based on the device
level callback so that drivers didn't need to worry about being in power
domains or manually calling bus level callbacks.
Putting it in a helper would at least mean that it's easier for the
mechanics to be transferred to the core proper later on.
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^ permalink raw reply
* [PATCH 09/17] spi: pl022: Simplify clock handling
From: Mark Brown @ 2014-02-04 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391529538-21685-10-git-send-email-ulf.hansson@linaro.org>
On Tue, Feb 04, 2014 at 04:58:50PM +0100, Ulf Hansson wrote:
> Make use of clk_prepare_enable and clk_disable_unprepare to simplify
> code. No functional change.
I went ahead and applied this since it looks good and seems like an
unrelated cleanup to the runtime PM stuff which seems to be where the
interdependencies are - thanks! It's on a separate branch with the
already applied change so if it does need to be cross merged we can do
that easily or even drop the branch.
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* [PATCH 10/17] spi: pl022: Remove redundant pinctrl to default state in probe
From: Mark Brown @ 2014-02-04 19:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391529538-21685-11-git-send-email-ulf.hansson@linaro.org>
On Tue, Feb 04, 2014 at 04:58:51PM +0100, Ulf Hansson wrote:
> The driver core is now taking care of putting our pins into default
> state at probe. Thus we can remove the redundant call for it in probe.
I applied this one too, as with the last patch it looks independant of
the runtime PM stuff.
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^ permalink raw reply
* [PATCH] arm64: Add architecture support for PCI
From: Arnd Bergmann @ 2014-02-04 19:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204191055.GC25695@obsidianresearch.com>
On Tuesday 04 February 2014 12:10:55 Jason Gunthorpe wrote:
>
> For instance to support peer-to-peer IO you need to have a consisent,
> non-overlapping set of bus/device/function/tag to uniquely route TLPs
> within the chip. Cross domain TLP routing in HW is non-trivial.
Yes, that is a good reason.
> IOMMUs (and SR-IOv) rely on the BDF to identify the originating device
> for each TLP. Multiple domains means a much more complex IOMMU
> environment.
I fear we already have to support complex IOMMU setups on ARM,
whether there are multiple PCI domains or not. But it would be
nice in theory not to require it.
> Failure to integrate on-chip devices into the PCI world also means
> thing like SR-IOv won't work sanely with on-chip devices.
I'd consider this a feature ;)
But you are probably right: people will do SR-IOV whether we like
it or not, and they will try to do it on non-PCI devices too,
and great suffering will be involved.
Arnd
^ permalink raw reply
* [PATCH 05/17] mmc: mmci: Put the device into low power state at system suspend
From: Kevin Hilman @ 2014-02-04 19:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391529538-21685-6-git-send-email-ulf.hansson@linaro.org>
Ulf Hansson <ulf.hansson@linaro.org> writes:
> Due to the available runtime PM callbacks, we are now able to put our
> device into low power state at system suspend.
>
> Earlier we could not accomplish this without trusting a power domain
> for the device to take care of it. Now we are able to cope with
> scenarios both with and without a power domain.
>
> Cc: Russell King <linux@arm.linux.org.uk>
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
> ---
> drivers/mmc/host/mmci.c | 45 +++++++++++++++++++++++++--------------------
> 1 file changed, 25 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> index c88da1c..074e0cb 100644
> --- a/drivers/mmc/host/mmci.c
> +++ b/drivers/mmc/host/mmci.c
> @@ -1723,33 +1723,38 @@ static int mmci_remove(struct amba_device *dev)
> return 0;
> }
>
> -#ifdef CONFIG_SUSPEND
> -static int mmci_suspend(struct device *dev)
> +#ifdef CONFIG_PM_SLEEP
> +static int mmci_suspend_late(struct device *dev)
> {
> - struct amba_device *adev = to_amba_device(dev);
> - struct mmc_host *mmc = amba_get_drvdata(adev);
> + int ret = 0;
>
> - if (mmc) {
> - struct mmci_host *host = mmc_priv(mmc);
> - pm_runtime_get_sync(dev);
> - writel(0, host->base + MMCIMASK0);
> - }
> + if (pm_runtime_status_suspended(dev))
> + return 0;
>
> - return 0;
> + if (dev->pm_domain && dev->pm_domain->ops.runtime_suspend)
> + ret = dev->pm_domain->ops.runtime_suspend(dev);
> + else
> + ret = dev->bus->pm->runtime_suspend(dev);
> +
> + if (!ret)
> + pm_runtime_set_suspended(dev);
Isn't this basically open-coding pm_runtime_suspend()...
> + return ret;
> }
>
> -static int mmci_resume(struct device *dev)
> +static int mmci_resume_early(struct device *dev)
> {
> - struct amba_device *adev = to_amba_device(dev);
> - struct mmc_host *mmc = amba_get_drvdata(adev);
> + int ret = 0;
>
> - if (mmc) {
> - struct mmci_host *host = mmc_priv(mmc);
> - writel(MCI_IRQENABLE, host->base + MMCIMASK0);
> - pm_runtime_put(dev);
> - }
> + if (pm_runtime_status_suspended(dev))
> + return 0;
>
> - return 0;
> + if (dev->pm_domain && dev->pm_domain->ops.runtime_resume)
> + ret = dev->pm_domain->ops.runtime_resume(dev);
> + else
> + ret = dev->bus->pm->runtime_resume(dev);
> +
> + return ret;
...and this is pm_runtime_resume()? (though both terribly simplified.)
This is starting to show that building with PM_SLEEP but not PM_RUNTIME
is going to force open-coding a lot of stuff that the runtime PM
framework already provides. So either we need some helper functions so
we're not sprinkling manual calls to bus/pm_domain callbacks all over
the place, or maybe where we need to go is have a way for platforms that
really are "runtime PM centric" to declare that even PM_SLEEP depends on
PM_RUNTIME.
I'm trying to thing of a good reason to not make PM_SLEEP depend on
PM_RUNTIME for platforms like this.
Kevin
^ permalink raw reply
* [RFC PATCH V3 1/4] pci: APM X-Gene PCIe controller driver
From: Arnd Bergmann @ 2014-02-04 19:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140203221559.GG2519@obsidianresearch.com>
On Monday 03 February 2014, Jason Gunthorpe wrote:
> On Mon, Feb 03, 2014 at 09:12:32PM +0100, Arnd Bergmann wrote:
>
> > Are you sure that is true for the root bridge as well? I don't
> > remember the details, but I though that for the host bridge,
> > we don't actually look at the BARs at all.
>
> That is right, but this isn't a host bridge device, it is a PCI-PCI
> bridge with root complex registers. The root complex bridge is not the
> same as the host bridge.
>
> Unfortunately the implementation is non-conforming. :(
Ok, I see. I was probably asking the wrong question then earlier
when I tried to find out what this is.
Arnd
^ permalink raw reply
* [PATCH v2 0/6] ARM: sunxi: Add driver for SD/MMC hosts found on allwinner sunxi SOCs
From: David Lanzendörfer @ 2014-02-04 19:24 UTC (permalink / raw)
To: linux-arm-kernel
Hello
The following patchset adds support for the SD/MMC host found in the Allwinner SoCs.
It contains all the necessary modifications for clock environment and also the device
tree script modification which add it to all the boards using it.
The clock environment function needed for phase offset configuration has
been proposed and implemented by Emilio.
This patchset is the second attempt to send this driver upstream.
I'm looking forward to the acceptance of this patchset into mainline.
best regards
David
---
David Lanzend?rfer (4):
ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
ARM: dts: sun7i: Add support for mmc
ARM: dts: sun4i: Add support for mmc
ARM: dts: sun5i: Add support for mmc
Emilio L?pez (1):
clk: sunxi: Implement MMC phase control
Hans de Goede (1):
ARM: sunxi: clk: export clk_sunxi_mmc_phase_control
arch/arm/boot/dts/sun4i-a10-a1000.dts | 8
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 8
arch/arm/boot/dts/sun4i-a10.dtsi | 54 +
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 30 +
arch/arm/boot/dts/sun5i-a10s.dtsi | 44 +
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 15
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 15
arch/arm/boot/dts/sun5i-a13.dtsi | 37 +
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 8
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 8
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +
arch/arm/boot/dts/sun7i-a20.dtsi | 61 ++
drivers/clk/sunxi/clk-sunxi.c | 35 +
drivers/mmc/host/Kconfig | 8
drivers/mmc/host/Makefile | 2
drivers/mmc/host/sunxi-mci.c | 848 ++++++++++++++++++++++
drivers/mmc/host/sunxi-mci.h | 239 ++++++
include/linux/clk/sunxi.h | 22 +
18 files changed, 1465 insertions(+)
create mode 100644 drivers/mmc/host/sunxi-mci.c
create mode 100644 drivers/mmc/host/sunxi-mci.h
create mode 100644 include/linux/clk/sunxi.h
--
Signature
^ permalink raw reply
* [Patch v4 1/2] dmaengine: add Qualcomm BAM dma driver
From: Andy Gross @ 2014-02-04 19:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F0D5E1.3040409@metafoo.de>
On Tue, Feb 04, 2014 at 12:58:25PM +0100, Lars-Peter Clausen wrote:
> On 02/04/2014 12:04 AM, Andy Gross wrote:
> [...]
> >+static int bam_dma_remove(struct platform_device *pdev)
> >+{
> >+ struct bam_device *bdev = platform_get_drvdata(pdev);
> >+ u32 i;
> >+
> >+ dma_async_device_unregister(&bdev->common);
> >+ of_dma_controller_free(pdev->dev.of_node);
>
> The controller should first be removed from the of lookup table,
> then free the device.
>
Ah right, had this reversed.
> >+
> >+ /* mask all interrupts for this execution environment */
> >+ writel_relaxed(0, bdev->regs + BAM_IRQ_SRCS_MSK_EE(bdev->ee));
>
> You still need to free the interrupt to make this race free,
> especially on a multi-processor system. free_irq() acts as a
> synchronization point that makes sure that interrupt handler has
> finished running and that no new interrupt handlers are being run
> after this point. Just masking the interrupt in the control register
> does not provide these guarantees.
ok i'll just add in a devm_free_irq(). The only good thing then about using the
devm_request_irq is the cleanup on error paths in the probe.
> >+
> >+ for (i = 0; i < bdev->num_channels; i++) {
> >+ bam_dma_terminate_all(&bdev->channels[i]);
> >+ tasklet_kill(&bdev->channels[i].vc.task);
> >+ }
> >+
> >+ tasklet_kill(&bdev->task);
> >+
> >+ clk_disable_unprepare(bdev->bamclk);
> >+
> >+ return 0;
> >+}
> [...]
>
--
sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* [PATCH v2 1/6] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
From: David Lanzendörfer @ 2014-02-04 19:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204191648.29809.14611.stgit@dizzy-6.o2s.ch>
This is based on the driver Allwinner ships in the Android kernel sources.
Initial porting to upstream kernels done by David Lanzend??rfer, additional
fixes and cleanups by Hans de Goede.
It uses dma in bus-master mode using a built-in designware idmac controller,
which is identical to the one found in the mmc-dw hosts.
The rest of the host is not identical to mmc-dw.
---
drivers/mmc/host/Kconfig | 8
drivers/mmc/host/Makefile | 2
drivers/mmc/host/sunxi-mci.c | 848 ++++++++++++++++++++++++++++++++++++++++++
drivers/mmc/host/sunxi-mci.h | 239 ++++++++++++
4 files changed, 1097 insertions(+)
create mode 100644 drivers/mmc/host/sunxi-mci.c
create mode 100644 drivers/mmc/host/sunxi-mci.h
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 1384f67..e56aabd 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -689,3 +689,11 @@ config MMC_REALTEK_PCI
help
Say Y here to include driver code to support SD/MMC card interface
of Realtek PCI-E card reader
+
+config MMC_SUNXI
+ tristate "Allwinner sunxi SD/MMC Host Controller support"
+ depends on ARCH_SUNXI
+ default y
+ help
+ This selects support for the SD/MMC Host Controller on
+ Allwinner sunxi SoCs.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 3483b6b..6c9cbd3 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -54,6 +54,8 @@ obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
+obj-$(CONFIG_MMC_SUNXI) += sunxi-mci.o
+
obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o
obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
diff --git a/drivers/mmc/host/sunxi-mci.c b/drivers/mmc/host/sunxi-mci.c
new file mode 100644
index 0000000..9d87da7
--- /dev/null
+++ b/drivers/mmc/host/sunxi-mci.c
@@ -0,0 +1,848 @@
+/*
+ * Driver for sunxi SD/MMC host controllers
+ * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
+ * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
+ * (C) Copyright 2013-2013 O2S GmbH <www.o2s.ch>
+ * (C) Copyright 2013-2013 David Lanzend?rfer <david.lanzendoerfer@o2s.ch>
+ * (C) Copyright 2013-2013 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/clk/sunxi.h>
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/regulator/consumer.h>
+
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+
+#include <linux/mmc/host.h>
+#include <linux/mmc/sd.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/core.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/slot-gpio.h>
+
+#include "sunxi-mci.h"
+
+static void sunxi_mmc_init_host(struct mmc_host *mmc)
+{
+ u32 rval;
+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
+
+ /* reset controller */
+ rval = mci_readl(smc_host, REG_GCTRL) | SDXC_HWReset;
+ mci_writel(smc_host, REG_GCTRL, rval);
+
+ mci_writel(smc_host, REG_FTRGL, 0x20070008);
+ mci_writel(smc_host, REG_TMOUT, 0xffffffff);
+ mci_writel(smc_host, REG_IMASK, smc_host->sdio_imask);
+ mci_writel(smc_host, REG_RINTR, 0xffffffff);
+ mci_writel(smc_host, REG_DBGC, 0xdeb);
+ mci_writel(smc_host, REG_FUNS, 0xceaa0000);
+ mci_writel(smc_host, REG_DLBA, smc_host->sg_dma);
+ rval = mci_readl(smc_host, REG_GCTRL)|SDXC_INTEnb;
+ rval &= ~SDXC_AccessDoneDirect;
+ mci_writel(smc_host, REG_GCTRL, rval);
+}
+
+static void sunxi_mmc_exit_host(struct sunxi_mmc_host *smc_host)
+{
+ mci_writel(smc_host, REG_GCTRL, SDXC_HWReset);
+}
+
+/* /\* UHS-I Operation Modes */
+/* * DS 25MHz 12.5MB/s 3.3V */
+/* * HS 50MHz 25MB/s 3.3V */
+/* * SDR12 25MHz 12.5MB/s 1.8V */
+/* * SDR25 50MHz 25MB/s 1.8V */
+/* * SDR50 100MHz 50MB/s 1.8V */
+/* * SDR104 208MHz 104MB/s 1.8V */
+/* * DDR50 50MHz 50MB/s 1.8V */
+/* * MMC Operation Modes */
+/* * DS 26MHz 26MB/s 3/1.8/1.2V */
+/* * HS 52MHz 52MB/s 3/1.8/1.2V */
+/* * HSDDR 52MHz 104MB/s 3/1.8/1.2V */
+/* * HS200 200MHz 200MB/s 1.8/1.2V */
+/* * */
+/* * Spec. Timing */
+/* * SD3.0 */
+/* * Fcclk Tcclk Fsclk Tsclk Tis Tih odly RTis RTih */
+/* * 400K 2.5us 24M 41ns 5ns 5ns 1 2209ns 41ns */
+/* * 25M 40ns 600M 1.67ns 5ns 5ns 3 14.99ns 5.01ns */
+/* * 50M 20ns 600M 1.67ns 6ns 2ns 3 14.99ns 5.01ns */
+/* * 50MDDR 20ns 600M 1.67ns 6ns 0.8ns 2 6.67ns 3.33ns */
+/* * 104M 9.6ns 600M 1.67ns 3ns 0.8ns 1 7.93ns 1.67ns */
+/* * 208M 4.8ns 600M 1.67ns 1.4ns 0.8ns 1 3.33ns 1.67ns */
+
+/* * 25M 40ns 300M 3.33ns 5ns 5ns 2 13.34ns 6.66ns */
+/* * 50M 20ns 300M 3.33ns 6ns 2ns 2 13.34ns 6.66ns */
+/* * 50MDDR 20ns 300M 3.33ns 6ns 0.8ns 1 6.67ns 3.33ns */
+/* * 104M 9.6ns 300M 3.33ns 3ns 0.8ns 0 7.93ns 1.67ns */
+/* * 208M 4.8ns 300M 3.33ns 1.4ns 0.8ns 0 3.13ns 1.67ns */
+
+/* * eMMC4.5 */
+/* * 400K 2.5us 24M 41ns 3ns 3ns 1 2209ns 41ns */
+/* * 25M 40ns 600M 1.67ns 3ns 3ns 3 14.99ns 5.01ns */
+/* * 50M 20ns 600M 1.67ns 3ns 3ns 3 14.99ns 5.01ns */
+/* * 50MDDR 20ns 600M 1.67ns 2.5ns 2.5ns 2 6.67ns 3.33ns */
+/* * 200M 5ns 600M 1.67ns 1.4ns 0.8ns 1 3.33ns 1.67ns */
+/* *\/ */
+
+static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
+ struct mmc_data *data)
+{
+ struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
+ struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma;
+ int i, max_len = (1 << host->idma_des_size_bits);
+
+ for (i = 0; i < data->sg_len; i++) {
+ pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
+ SDXC_IDMAC_DES0_DIC;
+
+ if (data->sg[i].length == max_len)
+ pdes[i].buf_size = 0; /* 0 == max_len */
+ else
+ pdes[i].buf_size = data->sg[i].length;
+
+ pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
+ pdes[i].buf_addr_ptr2 = (u32)&pdes_pa[i + 1];
+ }
+ pdes[0].config |= SDXC_IDMAC_DES0_FD;
+ pdes[i - 1].config = SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_LD;
+
+ wmb(); /* Ensure idma_des hit main mem before we start the idmac */
+}
+
+static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
+{
+ if (data->flags & MMC_DATA_WRITE)
+ return DMA_TO_DEVICE;
+ else
+ return DMA_FROM_DEVICE;
+}
+
+static int sunxi_mmc_prepare_dma(struct sunxi_mmc_host *smc_host,
+ struct mmc_data *data)
+{
+ u32 dma_len;
+ u32 i;
+ u32 temp;
+ struct scatterlist *sg;
+
+ dma_len = dma_map_sg(mmc_dev(smc_host->mmc), data->sg, data->sg_len,
+ sunxi_mmc_get_dma_dir(data));
+ if (dma_len == 0) {
+ dev_err(mmc_dev(smc_host->mmc), "dma_map_sg failed\n");
+ return -ENOMEM;
+ }
+
+ for_each_sg(data->sg, sg, data->sg_len, i) {
+ if (sg->offset & 3 || sg->length & 3) {
+ dev_err(mmc_dev(smc_host->mmc),
+ "unaligned scatterlist: os %x length %d\n",
+ sg->offset, sg->length);
+ return -EINVAL;
+ }
+ }
+
+ sunxi_mmc_init_idma_des(smc_host, data);
+
+ temp = mci_readl(smc_host, REG_GCTRL);
+ temp |= SDXC_DMAEnb;
+ mci_writel(smc_host, REG_GCTRL, temp);
+ temp |= SDXC_DMAReset;
+ mci_writel(smc_host, REG_GCTRL, temp);
+
+ mci_writel(smc_host, REG_DMAC, SDXC_IDMACSoftRST);
+
+ if (!(data->flags & MMC_DATA_WRITE))
+ mci_writel(smc_host, REG_IDIE, SDXC_IDMACReceiveInt);
+
+ mci_writel(smc_host, REG_DMAC, SDXC_IDMACFixBurst | SDXC_IDMACIDMAOn);
+
+ return 0;
+}
+
+static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
+ struct mmc_request *req)
+{
+ u32 cmd_val = SDXC_Start | SDXC_RspExp | SDXC_StopAbortCMD
+ | SDXC_CheckRspCRC | MMC_STOP_TRANSMISSION;
+ u32 ri = 0;
+ unsigned long expire = jiffies + msecs_to_jiffies(1000);
+
+ mci_writel(host, REG_CARG, 0);
+ mci_writel(host, REG_CMDR, cmd_val);
+ do {
+ ri = mci_readl(host, REG_RINTR);
+ } while (!(ri & (SDXC_CmdDone | SDXC_IntErrBit)) &&
+ time_before(jiffies, expire));
+
+ if (ri & SDXC_IntErrBit) {
+ dev_err(mmc_dev(host->mmc), "send stop command failed\n");
+ if (req->stop)
+ req->stop->resp[0] = -ETIMEDOUT;
+ } else {
+ if (req->stop)
+ req->stop->resp[0] = mci_readl(host, REG_RESP0);
+ }
+
+ mci_writel(host, REG_RINTR, 0xffff);
+}
+
+static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *smc_host)
+{
+ struct mmc_command *cmd = smc_host->mrq->cmd;
+ struct mmc_data *data = smc_host->mrq->data;
+
+ /* For some cmds timeout is normal with sd/mmc cards */
+ if ((smc_host->int_sum & SDXC_IntErrBit) == SDXC_RespTimeout &&
+ (cmd->opcode == 5 || cmd->opcode == 52))
+ return;
+
+ dev_err(mmc_dev(smc_host->mmc),
+ "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
+ smc_host->mmc->index, cmd->opcode,
+ data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
+ smc_host->int_sum & SDXC_RespErr ? " RE" : "",
+ smc_host->int_sum & SDXC_RespCRCErr ? " RCE" : "",
+ smc_host->int_sum & SDXC_DataCRCErr ? " DCE" : "",
+ smc_host->int_sum & SDXC_RespTimeout ? " RTO" : "",
+ smc_host->int_sum & SDXC_DataTimeout ? " DTO" : "",
+ smc_host->int_sum & SDXC_FIFORunErr ? " FE" : "",
+ smc_host->int_sum & SDXC_HardWLocked ? " HL" : "",
+ smc_host->int_sum & SDXC_StartBitErr ? " SBE" : "",
+ smc_host->int_sum & SDXC_EndBitErr ? " EBE" : ""
+ );
+}
+
+static void sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
+{
+ struct mmc_request *mrq;
+ unsigned long iflags;
+
+ spin_lock_irqsave(&host->lock, iflags);
+
+ mrq = host->mrq;
+ if (!mrq) {
+ spin_unlock_irqrestore(&host->lock, iflags);
+ dev_err(mmc_dev(host->mmc), "no request to finalize\n");
+ return;
+ }
+
+ if (host->int_sum & SDXC_IntErrBit) {
+ sunxi_mmc_dump_errinfo(host);
+ mrq->cmd->error = -ETIMEDOUT;
+ if (mrq->data)
+ mrq->data->error = -ETIMEDOUT;
+ if (mrq->stop)
+ mrq->stop->error = -ETIMEDOUT;
+ } else {
+ if (mrq->cmd->flags & MMC_RSP_136) {
+ mrq->cmd->resp[0] = mci_readl(host, REG_RESP3);
+ mrq->cmd->resp[1] = mci_readl(host, REG_RESP2);
+ mrq->cmd->resp[2] = mci_readl(host, REG_RESP1);
+ mrq->cmd->resp[3] = mci_readl(host, REG_RESP0);
+ } else {
+ mrq->cmd->resp[0] = mci_readl(host, REG_RESP0);
+ }
+ if (mrq->data)
+ mrq->data->bytes_xfered =
+ mrq->data->blocks * mrq->data->blksz;
+ }
+
+ if (mrq->data) {
+ struct mmc_data *data = mrq->data;
+ u32 temp;
+
+ mci_writel(host, REG_IDST, 0x337);
+ mci_writel(host, REG_DMAC, 0);
+ temp = mci_readl(host, REG_GCTRL);
+ mci_writel(host, REG_GCTRL, temp|SDXC_DMAReset);
+ temp &= ~SDXC_DMAEnb;
+ mci_writel(host, REG_GCTRL, temp);
+ temp |= SDXC_FIFOReset;
+ mci_writel(host, REG_GCTRL, temp);
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+ sunxi_mmc_get_dma_dir(data));
+ }
+
+ mci_writel(host, REG_RINTR, 0xffff);
+
+ dev_dbg(mmc_dev(host->mmc), "req done, resp %08x %08x %08x %08x\n",
+ mrq->cmd->resp[0], mrq->cmd->resp[1],
+ mrq->cmd->resp[2], mrq->cmd->resp[3]);
+
+ host->mrq = NULL;
+ host->int_sum = 0;
+ host->wait_dma = 0;
+
+ spin_unlock_irqrestore(&host->lock, iflags);
+
+ if (mrq->data && mrq->data->error) {
+ dev_err(mmc_dev(host->mmc),
+ "data error, sending stop command\n");
+ sunxi_mmc_send_manual_stop(host, mrq);
+ }
+
+ mmc_request_done(host->mmc, mrq);
+}
+
+static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
+{
+ struct sunxi_mmc_host *host = dev_id;
+ u32 finalize = 0;
+ u32 sdio_int = 0;
+ u32 msk_int;
+ u32 idma_int;
+
+ spin_lock(&host->lock);
+
+ idma_int = mci_readl(host, REG_IDST);
+ msk_int = mci_readl(host, REG_MISTA);
+
+ dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
+ host->mrq, msk_int, idma_int);
+
+ if (host->mrq) {
+ if (idma_int & SDXC_IDMACReceiveInt)
+ host->wait_dma = 0;
+
+ host->int_sum |= msk_int;
+
+ /* Wait for CmdDone on RespTimeout before finishing the req */
+ if ((host->int_sum & SDXC_RespTimeout) &&
+ !(host->int_sum & SDXC_CmdDone))
+ mci_writel(host, REG_IMASK,
+ host->sdio_imask | SDXC_CmdDone);
+ else if (host->int_sum & SDXC_IntErrBit)
+ finalize = 1; /* Don't wait for dma on error */
+ else if (host->int_sum & SDXC_IntDoneBit && !host->wait_dma)
+ finalize = 1; /* Done */
+
+ if (finalize) {
+ mci_writel(host, REG_IMASK, host->sdio_imask);
+ mci_writel(host, REG_IDIE, 0);
+ }
+ }
+
+ if (msk_int & SDXC_SDIOInt)
+ sdio_int = 1;
+
+ mci_writel(host, REG_RINTR, msk_int);
+ mci_writel(host, REG_IDST, idma_int);
+
+ spin_unlock(&host->lock);
+
+ if (finalize)
+ tasklet_schedule(&host->tasklet);
+
+ if (sdio_int)
+ mmc_signal_sdio_irq(host->mmc);
+
+ return IRQ_HANDLED;
+}
+
+static void sunxi_mmc_tasklet(unsigned long data)
+{
+ struct sunxi_mmc_host *smc_host = (struct sunxi_mmc_host *) data;
+ sunxi_mmc_finalize_request(smc_host);
+}
+
+static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
+{
+ unsigned long expire = jiffies + msecs_to_jiffies(2000);
+ u32 rval;
+
+ rval = mci_readl(host, REG_CLKCR);
+ rval &= ~(SDXC_CardClkOn | SDXC_LowPowerOn);
+ if (oclk_en)
+ rval |= SDXC_CardClkOn;
+ if (!host->io_flag)
+ rval |= SDXC_LowPowerOn;
+ mci_writel(host, REG_CLKCR, rval);
+
+ rval = SDXC_Start | SDXC_UPCLKOnly | SDXC_WaitPreOver;
+ if (host->voltage_switching)
+ rval |= SDXC_VolSwitch;
+ mci_writel(host, REG_CMDR, rval);
+ do {
+ rval = mci_readl(host, REG_CMDR);
+ } while (time_before(jiffies, expire) && (rval & SDXC_Start));
+
+ if (rval & SDXC_Start) {
+ dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
+ host->ferror = 1;
+ }
+}
+
+static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *smc_host,
+ u32 oclk_dly, u32 sclk_dly)
+{
+ unsigned long iflags;
+ struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
+
+ spin_lock_irqsave(&smc_host->lock, iflags);
+ clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
+ spin_unlock_irqrestore(&smc_host->lock, iflags);
+}
+
+struct sunxi_mmc_clk_dly mmc_clk_dly[MMC_CLK_MOD_NUM] = {
+ { MMC_CLK_400K, 0, 7 },
+ { MMC_CLK_25M, 0, 5 },
+ { MMC_CLK_50M, 3, 5 },
+ { MMC_CLK_50MDDR, 2, 4 },
+ { MMC_CLK_50MDDR_8BIT, 2, 4 },
+ { MMC_CLK_100M, 1, 4 },
+ { MMC_CLK_200M, 1, 4 },
+};
+
+static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
+ unsigned int rate)
+{
+ u32 newrate;
+ u32 src_clk;
+ u32 oclk_dly;
+ u32 sclk_dly;
+ u32 temp;
+ struct sunxi_mmc_clk_dly *dly = NULL;
+
+ newrate = clk_round_rate(smc_host->clk_mod, rate);
+ if (smc_host->clk_mod_rate == newrate) {
+ dev_dbg(mmc_dev(smc_host->mmc), "clk already %d, rounded %d\n",
+ rate, newrate);
+ return;
+ }
+
+ dev_dbg(mmc_dev(smc_host->mmc), "setting clk to %d, rounded %d\n",
+ rate, newrate);
+
+ /* setting clock rate */
+ clk_disable(smc_host->clk_mod);
+ clk_set_rate(smc_host->clk_mod, newrate);
+ clk_enable(smc_host->clk_mod);
+ smc_host->clk_mod_rate = newrate = clk_get_rate(smc_host->clk_mod);
+ dev_dbg(mmc_dev(smc_host->mmc), "clk is now %d\n", newrate);
+
+ sunxi_mmc_oclk_onoff(smc_host, 0);
+ /* clear internal divider */
+ temp = mci_readl(smc_host, REG_CLKCR);
+ temp &= ~0xff;
+ mci_writel(smc_host, REG_CLKCR, temp);
+
+ /* determine delays */
+ if (rate <= 400000) {
+ dly = &mmc_clk_dly[MMC_CLK_400K];
+ } else if (rate <= 25000000) {
+ dly = &mmc_clk_dly[MMC_CLK_25M];
+ } else if (rate <= 50000000) {
+ if (smc_host->ddr) {
+ if (smc_host->bus_width == 8)
+ dly = &mmc_clk_dly[MMC_CLK_50MDDR_8BIT];
+ else
+ dly = &mmc_clk_dly[MMC_CLK_50MDDR];
+ } else {
+ dly = &mmc_clk_dly[MMC_CLK_50M];
+ }
+ } else if (rate <= 104000000) {
+ dly = &mmc_clk_dly[MMC_CLK_100M];
+ } else if (rate <= 208000000) {
+ dly = &mmc_clk_dly[MMC_CLK_200M];
+ } else
+ dly = &mmc_clk_dly[MMC_CLK_50M];
+
+ oclk_dly = dly->oclk_dly;
+ sclk_dly = dly->sclk_dly;
+
+ src_clk = clk_get_rate(clk_get_parent(smc_host->clk_mod));
+ if (src_clk >= 300000000 && src_clk <= 400000000) {
+ if (oclk_dly)
+ oclk_dly--;
+ if (sclk_dly)
+ sclk_dly--;
+ }
+
+ sunxi_mmc_set_clk_dly(smc_host, oclk_dly, sclk_dly);
+ sunxi_mmc_oclk_onoff(smc_host, 1);
+
+ /* oclk_onoff sets various irq status bits, clear these */
+ mci_writel(smc_host, REG_RINTR,
+ mci_readl(smc_host, REG_RINTR) & ~SDXC_SDIOInt);
+}
+
+static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct sunxi_mmc_host *host = mmc_priv(mmc);
+ u32 temp;
+ s32 err;
+
+ /* Set the power state */
+ switch (ios->power_mode) {
+ case MMC_POWER_ON:
+ break;
+
+ case MMC_POWER_UP:
+ if (!IS_ERR(host->vmmc)) {
+ mmc_regulator_set_ocr(host->mmc, host->vmmc, ios->vdd);
+ udelay(200);
+ }
+
+ err = clk_prepare_enable(host->clk_ahb);
+ if (err) {
+ dev_err(mmc_dev(host->mmc), "AHB clk err %d\n", err);
+ host->ferror = 1;
+ return;
+ }
+ err = clk_prepare_enable(host->clk_mod);
+ if (err) {
+ dev_err(mmc_dev(host->mmc), "MOD clk err %d\n", err);
+ host->ferror = 1;
+ return;
+ }
+
+ sunxi_mmc_init_host(mmc);
+ enable_irq(host->irq);
+
+ dev_dbg(mmc_dev(host->mmc), "power on!\n");
+ host->ferror = 0;
+ break;
+
+ case MMC_POWER_OFF:
+ dev_dbg(mmc_dev(host->mmc), "power off!\n");
+ disable_irq(host->irq);
+ sunxi_mmc_exit_host(host);
+ clk_disable_unprepare(host->clk_ahb);
+ clk_disable_unprepare(host->clk_mod);
+ if (!IS_ERR(host->vmmc))
+ mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
+ host->ferror = 0;
+ break;
+ }
+
+ /* set bus width */
+ switch (ios->bus_width) {
+ case MMC_BUS_WIDTH_1:
+ mci_writel(host, REG_WIDTH, SDXC_WIDTH1);
+ host->bus_width = 1;
+ break;
+ case MMC_BUS_WIDTH_4:
+ mci_writel(host, REG_WIDTH, SDXC_WIDTH4);
+ host->bus_width = 4;
+ break;
+ case MMC_BUS_WIDTH_8:
+ mci_writel(host, REG_WIDTH, SDXC_WIDTH8);
+ host->bus_width = 8;
+ break;
+ }
+
+ /* set ddr mode */
+ temp = mci_readl(host, REG_GCTRL);
+ if (ios->timing == MMC_TIMING_UHS_DDR50) {
+ temp |= SDXC_DDR_MODE;
+ host->ddr = 1;
+ } else {
+ temp &= ~SDXC_DDR_MODE;
+ host->ddr = 0;
+ }
+ mci_writel(host, REG_GCTRL, temp);
+
+ /* set up clock */
+ if (ios->clock && ios->power_mode) {
+ dev_dbg(mmc_dev(host->mmc), "ios->clock: %d\n", ios->clock);
+ sunxi_mmc_clk_set_rate(host, ios->clock);
+ usleep_range(50000, 55000);
+ }
+}
+
+static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
+ unsigned long flags;
+ u32 imask;
+
+ spin_lock_irqsave(&smc_host->lock, flags);
+ imask = mci_readl(smc_host, REG_IMASK);
+ if (enable) {
+ smc_host->sdio_imask = SDXC_SDIOInt;
+ imask |= SDXC_SDIOInt;
+ } else {
+ smc_host->sdio_imask = 0;
+ imask &= ~SDXC_SDIOInt;
+ }
+ mci_writel(smc_host, REG_IMASK, imask);
+ spin_unlock_irqrestore(&smc_host->lock, flags);
+}
+
+static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
+{
+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
+ mci_writel(smc_host, REG_HWRST, 0);
+ udelay(10);
+ mci_writel(smc_host, REG_HWRST, 1);
+ udelay(300);
+}
+
+static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct sunxi_mmc_host *host = mmc_priv(mmc);
+ struct mmc_command *cmd = mrq->cmd;
+ struct mmc_data *data = mrq->data;
+ unsigned long iflags;
+ u32 imask = SDXC_IntErrBit;
+ u32 cmd_val = SDXC_Start | (cmd->opcode & 0x3f);
+ u32 byte_cnt = 0;
+ int ret;
+
+ if (!mmc_gpio_get_cd(mmc) || host->ferror) {
+ dev_dbg(mmc_dev(host->mmc), "no medium present\n");
+ mrq->cmd->error = -ENOMEDIUM;
+ mmc_request_done(mmc, mrq);
+ return;
+ }
+
+ if (data) {
+ byte_cnt = data->blksz * data->blocks;
+ mci_writel(host, REG_BLKSZ, data->blksz);
+ mci_writel(host, REG_BCNTR, byte_cnt);
+ ret = sunxi_mmc_prepare_dma(host, data);
+ if (ret < 0) {
+ dev_err(mmc_dev(host->mmc), "prepare DMA failed\n");
+ cmd->error = ret;
+ cmd->data->error = ret;
+ mmc_request_done(host->mmc, mrq);
+ return;
+ }
+ }
+
+ if (cmd->opcode == MMC_GO_IDLE_STATE) {
+ cmd_val |= SDXC_SendInitSeq;
+ imask |= SDXC_CmdDone;
+ }
+
+ if (cmd->opcode == SD_SWITCH_VOLTAGE) {
+ cmd_val |= SDXC_VolSwitch;
+ imask |= SDXC_VolChgDone;
+ host->voltage_switching = 1;
+ sunxi_mmc_oclk_onoff(host, 1);
+ }
+
+ if (cmd->flags & MMC_RSP_PRESENT) {
+ cmd_val |= SDXC_RspExp;
+ if (cmd->flags & MMC_RSP_136)
+ cmd_val |= SDXC_LongRsp;
+ if (cmd->flags & MMC_RSP_CRC)
+ cmd_val |= SDXC_CheckRspCRC;
+
+ if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
+ cmd_val |= SDXC_DataExp | SDXC_WaitPreOver;
+ if (cmd->data->flags & MMC_DATA_STREAM) {
+ imask |= SDXC_AutoCMDDone;
+ cmd_val |= SDXC_Seqmod | SDXC_SendAutoStop;
+ }
+ if (cmd->data->stop) {
+ imask |= SDXC_AutoCMDDone;
+ cmd_val |= SDXC_SendAutoStop;
+ } else
+ imask |= SDXC_DataOver;
+
+ if (cmd->data->flags & MMC_DATA_WRITE)
+ cmd_val |= SDXC_Write;
+ else
+ host->wait_dma = 1;
+ } else
+ imask |= SDXC_CmdDone;
+ } else
+ imask |= SDXC_CmdDone;
+
+ dev_dbg(mmc_dev(host->mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
+ cmd_val & 0x3f, cmd_val, cmd->arg, imask,
+ mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
+
+ spin_lock_irqsave(&host->lock, iflags);
+ host->mrq = mrq;
+ mci_writel(host, REG_IMASK, host->sdio_imask | imask);
+ spin_unlock_irqrestore(&host->lock, iflags);
+
+ mci_writel(host, REG_CARG, cmd->arg);
+ mci_writel(host, REG_CMDR, cmd_val);
+}
+
+static const struct of_device_id sunxi_mmc_of_match[] = {
+ { .compatible = "allwinner,sun4i-a10-mmc", },
+ { .compatible = "allwinner,sun5i-a13-mmc", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
+
+static struct mmc_host_ops sunxi_mmc_ops = {
+ .request = sunxi_mmc_request,
+ .set_ios = sunxi_mmc_set_ios,
+ .get_ro = mmc_gpio_get_ro,
+ .get_cd = mmc_gpio_get_cd,
+ .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
+ .hw_reset = sunxi_mmc_hw_reset,
+};
+
+static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
+ struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ int ret;
+
+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc"))
+ host->idma_des_size_bits = 13;
+ else
+ host->idma_des_size_bits = 16;
+
+ host->vmmc = devm_regulator_get_optional(&pdev->dev, "vmmc");
+ if (IS_ERR(host->vmmc) && PTR_ERR(host->vmmc) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ host->reg_base = devm_ioremap_resource(&pdev->dev,
+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
+ if (IS_ERR(host->reg_base))
+ return PTR_ERR(host->reg_base);
+
+ host->irq = platform_get_irq(pdev, 0);
+ ret = devm_request_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 0,
+ "sunxi-mci", host);
+ if (ret)
+ return ret;
+ disable_irq(host->irq);
+
+ host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
+ if (IS_ERR(host->clk_ahb)) {
+ dev_err(&pdev->dev, "Could not get ahb clock\n");
+ return PTR_ERR(host->clk_ahb);
+ }
+
+ host->clk_mod = devm_clk_get(&pdev->dev, "mod");
+ if (IS_ERR(host->clk_mod)) {
+ dev_err(&pdev->dev, "Could not get mod clock\n");
+ return PTR_ERR(host->clk_mod);
+ }
+
+ return 0;
+}
+
+static int sunxi_mmc_probe(struct platform_device *pdev)
+{
+ struct sunxi_mmc_host *host;
+ struct mmc_host *mmc;
+ int ret;
+
+ mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
+ if (!mmc) {
+ dev_err(&pdev->dev, "mmc alloc host failed\n");
+ return -ENOMEM;
+ }
+
+ ret = mmc_of_parse(mmc);
+ if (ret)
+ goto error_free_host;
+
+ host = mmc_priv(mmc);
+ host->mmc = mmc;
+ spin_lock_init(&host->lock);
+ tasklet_init(&host->tasklet, sunxi_mmc_tasklet, (unsigned long)host);
+
+ ret = sunxi_mmc_resource_request(host, pdev);
+ if (ret)
+ goto error_free_host;
+
+ host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
+ &host->sg_dma, GFP_KERNEL);
+ if (!host->sg_cpu) {
+ dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
+ ret = -ENOMEM;
+ goto error_free_host;
+ }
+
+ mmc->ops = &sunxi_mmc_ops;
+ mmc->max_blk_count = 8192;
+ mmc->max_blk_size = 4096;
+ mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
+ mmc->max_seg_size = (1 << host->idma_des_size_bits);
+ mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
+ /* 400kHz ~ 50MHz */
+ mmc->f_min = 400000;
+ mmc->f_max = 50000000;
+ /* available voltages */
+ if (!IS_ERR(host->vmmc))
+ mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vmmc);
+ else
+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+ MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
+ MMC_CAP_UHS_DDR50 | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL |
+ MMC_CAP_DRIVER_TYPE_A;
+ if (host->bus_width == 4)
+ mmc->caps |= MMC_CAP_4_BIT_DATA;
+ mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP;
+
+ ret = mmc_add_host(mmc);
+ if (ret)
+ goto error_free_dma;
+
+ dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
+ platform_set_drvdata(pdev, mmc);
+ return 0;
+
+error_free_dma:
+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+error_free_host:
+ mmc_free_host(mmc);
+ return ret;
+}
+
+static int sunxi_mmc_remove(struct platform_device *pdev)
+{
+ struct mmc_host *mmc = platform_get_drvdata(pdev);
+ struct sunxi_mmc_host *host = mmc_priv(mmc);
+
+ mmc_remove_host(mmc);
+ sunxi_mmc_exit_host(host);
+ tasklet_disable(&host->tasklet);
+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+ mmc_free_host(mmc);
+
+ return 0;
+}
+
+static struct platform_driver sunxi_mmc_driver = {
+ .driver = {
+ .name = "sunxi-mci",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(sunxi_mmc_of_match),
+ },
+ .probe = sunxi_mmc_probe,
+ .remove = sunxi_mmc_remove,
+};
+module_platform_driver(sunxi_mmc_driver);
+
+MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("David Lanzend?rfer <david.lanzendoerfer@o2s.ch>");
+MODULE_ALIAS("platform:sunxi-mmc");
diff --git a/drivers/mmc/host/sunxi-mci.h b/drivers/mmc/host/sunxi-mci.h
new file mode 100644
index 0000000..f75b2fc
--- /dev/null
+++ b/drivers/mmc/host/sunxi-mci.h
@@ -0,0 +1,239 @@
+/*
+ * Driver for sunxi SD/MMC host controllers
+ * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
+ * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
+ * (C) Copyright 2013-2013 O2S GmbH <www.o2s.ch>
+ * (C) Copyright 2013-2013 David Lanzend?rfer <david.lanzendoerfer@o2s.ch>
+ * (C) Copyright 2013-2013 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __SUNXI_MCI_H__
+#define __SUNXI_MCI_H__
+
+/* register offset define */
+#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
+#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
+#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
+#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
+#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
+#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
+#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
+#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
+#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
+#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
+#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
+#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
+#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
+#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
+#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
+#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
+#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
+#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
+#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
+#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
+#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
+#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
+#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
+#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
+#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
+#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
+#define SDXC_REG_CHDA (0x90)
+#define SDXC_REG_CBDA (0x94)
+
+#define mci_readl(host, reg) \
+ __raw_readl((host)->reg_base + SDXC_##reg)
+#define mci_writel(host, reg, value) \
+ __raw_writel((value), (host)->reg_base + SDXC_##reg)
+
+/* global control register bits */
+#define SDXC_SoftReset BIT(0)
+#define SDXC_FIFOReset BIT(1)
+#define SDXC_DMAReset BIT(2)
+#define SDXC_HWReset (SDXC_SoftReset|SDXC_FIFOReset|SDXC_DMAReset)
+#define SDXC_INTEnb BIT(4)
+#define SDXC_DMAEnb BIT(5)
+#define SDXC_DebounceEnb BIT(8)
+#define SDXC_PosedgeLatchData BIT(9)
+#define SDXC_DDR_MODE BIT(10)
+#define SDXC_MemAccessDone BIT(29)
+#define SDXC_AccessDoneDirect BIT(30)
+#define SDXC_ACCESS_BY_AHB BIT(31)
+#define SDXC_ACCESS_BY_DMA (0U << 31)
+/* clock control bits */
+#define SDXC_CardClkOn BIT(16)
+#define SDXC_LowPowerOn BIT(17)
+/* bus width */
+#define SDXC_WIDTH1 (0)
+#define SDXC_WIDTH4 (1)
+#define SDXC_WIDTH8 (2)
+/* smc command bits */
+#define SDXC_RspExp BIT(6)
+#define SDXC_LongRsp BIT(7)
+#define SDXC_CheckRspCRC BIT(8)
+#define SDXC_DataExp BIT(9)
+#define SDXC_Write BIT(10)
+#define SDXC_Seqmod BIT(11)
+#define SDXC_SendAutoStop BIT(12)
+#define SDXC_WaitPreOver BIT(13)
+#define SDXC_StopAbortCMD BIT(14)
+#define SDXC_SendInitSeq BIT(15)
+#define SDXC_UPCLKOnly BIT(21)
+#define SDXC_RdCEATADev BIT(22)
+#define SDXC_CCSExp BIT(23)
+#define SDXC_EnbBoot BIT(24)
+#define SDXC_AltBootOpt BIT(25)
+#define SDXC_BootACKExp BIT(26)
+#define SDXC_BootAbort BIT(27)
+#define SDXC_VolSwitch BIT(28)
+#define SDXC_UseHoldReg BIT(29)
+#define SDXC_Start BIT(31)
+/* interrupt bits */
+#define SDXC_RespErr BIT(1)
+#define SDXC_CmdDone BIT(2)
+#define SDXC_DataOver BIT(3)
+#define SDXC_TxDataReq BIT(4)
+#define SDXC_RxDataReq BIT(5)
+#define SDXC_RespCRCErr BIT(6)
+#define SDXC_DataCRCErr BIT(7)
+#define SDXC_RespTimeout BIT(8)
+#define SDXC_DataTimeout BIT(9)
+#define SDXC_VolChgDone BIT(10)
+#define SDXC_FIFORunErr BIT(11)
+#define SDXC_HardWLocked BIT(12)
+#define SDXC_StartBitErr BIT(13)
+#define SDXC_AutoCMDDone BIT(14)
+#define SDXC_EndBitErr BIT(15)
+#define SDXC_SDIOInt BIT(16)
+#define SDXC_CardInsert BIT(30)
+#define SDXC_CardRemove BIT(31)
+#define SDXC_IntErrBit (SDXC_RespErr | SDXC_RespCRCErr | \
+ SDXC_DataCRCErr | SDXC_RespTimeout | \
+ SDXC_DataTimeout | SDXC_FIFORunErr | \
+ SDXC_HardWLocked | SDXC_StartBitErr | \
+ SDXC_EndBitErr) /* 0xbbc2 */
+#define SDXC_IntDoneBit (SDXC_AutoCMDDone | SDXC_DataOver | \
+ SDXC_CmdDone | SDXC_VolChgDone)
+/* status */
+#define SDXC_RXWLFlag BIT(0)
+#define SDXC_TXWLFlag BIT(1)
+#define SDXC_FIFOEmpty BIT(2)
+#define SDXC_FIFOFull BIT(3)
+#define SDXC_CardPresent BIT(8)
+#define SDXC_CardDataBusy BIT(9)
+#define SDXC_DataFSMBusy BIT(10)
+#define SDXC_DMAReq BIT(31)
+#define SDXC_FIFO_SIZE (16)
+/* Function select */
+#define SDXC_CEATAOn (0xceaaU << 16)
+#define SDXC_SendIrqRsp BIT(0)
+#define SDXC_SDIORdWait BIT(1)
+#define SDXC_AbtRdData BIT(2)
+#define SDXC_SendCCSD BIT(8)
+#define SDXC_SendAutoStopCCSD BIT(9)
+#define SDXC_CEATADevIntEnb BIT(10)
+/* IDMA controller bus mod bit field */
+#define SDXC_IDMACSoftRST BIT(0)
+#define SDXC_IDMACFixBurst BIT(1)
+#define SDXC_IDMACIDMAOn BIT(7)
+#define SDXC_IDMACRefetchDES BIT(31)
+/* IDMA status bit field */
+#define SDXC_IDMACTransmitInt BIT(0)
+#define SDXC_IDMACReceiveInt BIT(1)
+#define SDXC_IDMACFatalBusErr BIT(2)
+#define SDXC_IDMACDesInvalid BIT(4)
+#define SDXC_IDMACCardErrSum BIT(5)
+#define SDXC_IDMACNormalIntSum BIT(8)
+#define SDXC_IDMACAbnormalIntSum BIT(9)
+#define SDXC_IDMACHostAbtInTx BIT(10)
+#define SDXC_IDMACHostAbtInRx BIT(10)
+#define SDXC_IDMACIdle (0U << 13)
+#define SDXC_IDMACSuspend (1U << 13)
+#define SDXC_IDMACDESCRd (2U << 13)
+#define SDXC_IDMACDESCCheck (3U << 13)
+#define SDXC_IDMACRdReqWait (4U << 13)
+#define SDXC_IDMACWrReqWait (5U << 13)
+#define SDXC_IDMACRd (6U << 13)
+#define SDXC_IDMACWr (7U << 13)
+#define SDXC_IDMACDESCClose (8U << 13)
+
+struct sunxi_idma_des {
+ u32 config;
+#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
+#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
+#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
+#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
+#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
+#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
+#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
+
+ /*
+ * If the idma-des-size-bits of property is ie 13, bufsize bits are:
+ * Bits 0-12: buf1 size
+ * Bits 13-25: buf2 size
+ * Bits 26-31: not used
+ * Since we only ever set buf1 size, we can simply store it directly.
+ */
+ u32 buf_size;
+ u32 buf_addr_ptr1;
+ u32 buf_addr_ptr2;
+};
+
+struct sunxi_mmc_host {
+ struct mmc_host *mmc;
+ struct regulator *vmmc;
+
+ /* IO mapping base */
+ void __iomem *reg_base;
+
+ spinlock_t lock;
+ struct tasklet_struct tasklet;
+
+ /* clock management */
+ struct clk *clk_ahb;
+ struct clk *clk_mod;
+
+ /* ios information */
+ u32 clk_mod_rate;
+ u32 bus_width;
+ u32 idma_des_size_bits;
+ u32 ddr;
+ u32 voltage_switching;
+
+ /* irq */
+ int irq;
+ u32 int_sum;
+ u32 sdio_imask;
+
+ /* flags */
+ u32 power_on:1;
+ u32 io_flag:1;
+ u32 wait_dma:1;
+
+ dma_addr_t sg_dma;
+ void *sg_cpu;
+
+ struct mmc_request *mrq;
+ u32 ferror;
+};
+
+#define MMC_CLK_400K 0
+#define MMC_CLK_25M 1
+#define MMC_CLK_50M 2
+#define MMC_CLK_50MDDR 3
+#define MMC_CLK_50MDDR_8BIT 4
+#define MMC_CLK_100M 5
+#define MMC_CLK_200M 6
+#define MMC_CLK_MOD_NUM 7
+
+struct sunxi_mmc_clk_dly {
+ u32 mode;
+ u32 oclk_dly;
+ u32 sclk_dly;
+};
+
+#endif
^ permalink raw reply related
* [PATCH v2 2/6] clk: sunxi: Implement MMC phase control
From: David Lanzendörfer @ 2014-02-04 19:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204191648.29809.14611.stgit@dizzy-6.o2s.ch>
From: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abb6c5a..33b9977 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -377,6 +377,41 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
/**
+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
+ */
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
+{
+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
+
+ struct clk_composite *composite = to_clk_composite(hw);
+ struct clk_hw *rate_hw = composite->rate_hw;
+ struct clk_factors *factors = to_clk_factors(rate_hw);
+ unsigned long flags = 0;
+ u32 reg;
+
+ if (factors->lock)
+ spin_lock_irqsave(factors->lock, flags);
+
+ reg = readl(factors->reg);
+
+ /* set sample clock phase control */
+ reg &= ~(0x7 << 20);
+ reg |= ((sample & 0x7) << 20);
+
+ /* set output clock phase control */
+ reg &= ~(0x7 << 8);
+ reg |= ((output & 0x7) << 8);
+
+ writel(reg, factors->reg);
+
+ if (factors->lock)
+ spin_unlock_irqrestore(factors->lock, flags);
+}
+
+
+/**
* sunxi_factors_clk_setup() - Setup function for factor clocks
*/
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