* [PATCH v4 1/3] clocksource: timer-keystone: introduce clocksource driver for Keystone
From: Thomas Gleixner @ 2014-02-04 20:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F11B5C.40407@ti.com>
On Tue, 4 Feb 2014, Ivan Khoronzhuk wrote:
Please do not top post.
> It was so in v1. But it was decided to use explicit memory barriers,
> because we're always sure the memory barriers are there and that
> they're properly documented. Also in this case I don't need to add
> keystone readl/writel relaxed function variants and to use mixed calls of
> writel/writel_relaxed functions.
>
> See:
> http://www.spinics.net/lists/arm-kernel/msg294941.html
Fair enough, but we want a proper explanation for explicit barriers in
the code and not in some random discussion of patch version X on some
random mailing list.
Aside of that it should be iowmb(), but I might miss something ...
Thanks,
tglx
^ permalink raw reply
* Extending OPP bindings
From: Mark Brown @ 2014-02-04 20:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F13F54.5060000@ti.com>
On Tue, Feb 04, 2014 at 01:28:20PM -0600, Nishanth Menon wrote:
> On 02/04/2014 12:22 PM, Mark Brown wrote:
> > You're assuming that the frequency is a unique key here. That may not
> > be the case, for example two OPPs might have the same CPU clock
> > (assuming that's the frequency you're referring to) but different bus
> > clocking and of course the CPUs or CPU clusters might be individually
> > scalable (this is common in big.LITTLE designs I think).
> Which is why OPPs are maintained per device, bus OPPs belong to bus
> device (in TI terminology, we'd be talking of cross domain dependency
> here for maintaining asynchronous bridge timing closure constraints -
> but ofcourse, other SoCs may or maynot have such constraints). For
> scaling bus frequency, we already have infrastructure in place - clock
> notifiers - discussion of using that is much deeper topic of it's own.
> for each processor that is uniquely transitioning, we'd have it's own
> sets of OPPs - the correct representation of the device node is the
> key there.
I've seen some SoCs characterised over the whole device rather than with
individual parts of the SoC done separately.
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* [PATCH v5 4/6] spmi: pmic_arb: add support for interrupt handling
From: Thomas Gleixner @ 2014-02-04 20:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391468739-20987-5-git-send-email-joshc@codeaurora.org>
On Mon, 3 Feb 2014, Josh Cartwright wrote:
> +static void qpnpint_irq_ack(struct irq_data *d)
> +{
> + struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
> + u8 irq = d->hwirq >> 8;
> + u8 apid = d->hwirq;
> + unsigned long flags;
> + u8 data;
> +
> + spin_lock_irqsave(&pa->lock, flags);
This wants to be a raw_spinlock - think about RT!
Looks sane otherwise.
Thanks,
tglx
^ permalink raw reply
* [PATCH 0/4] clk: mvebu: fix clk init order
From: Thomas Petazzoni @ 2014-02-04 20:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F10024.4030201@free-electrons.com>
Hello,
On Tue, 04 Feb 2014 15:58:44 +0100, Gregory CLEMENT wrote:
> > @Jason, Andrew, Gregory, Thomas:
> > Now that v3.14 is out, anything against taking this in as fixes for rc1?
>
> I am not found of this solution I still think it should be done
> at framework level. However we still have this very annoying issue,
> and this fix is better than nothing. So I am not against taking this
> for rc1 with the hope that it will be later revert with a better
> solution.
Same opinion here. I'm fine with this solution as a temporary measure,
but it would be good to solve this problem in a nicer way. Also, making
this change doesn't impact the DT in any way, there is no problem in
having a temporary not perfect solution, and improve it later on.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply
* UBI leb_write_unlock NULL pointer Oops (continuation) on ARM926
From: Richard Weinberger @ 2014-02-04 20:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87ha8e3b34.fsf@nbsps.com>
Am 04.02.2014 20:57, schrieb Bill Pringlemeir:
> On 4 Feb 2014, bpringlemeir at nbsps.com wrote:
>
>> http://lists.infradead.org/pipermail/linux-mtd/2013-May/046907.html
>>
>> at91sam9g20 - arm926, different MTD driver. Linux 3.6.9
>>
>> Code: e5903004 e58d2004 e1560003 0a00002a (e593200c)
>>
>> 0: e5903004 ldr r3, [r0, #4]
>> 4: e58d2004 str r2, [sp, #4]
>> 8: e1560003 cmp r6, r3
>> c: 0a00002a beq 0xbc
>> 10: e593200c ldr r2, [r3, #12]
>>
>> The code sequence looks identical and the Oops trace, etc is the same.
>> People from Pengutronix also indicated seeing the same type of Opps; I
>> think they deal with the IMX, but maybe this was on another board.
>
>>>>> schrieb Wiedemer, Thorsten (Lawo AG):
>
>> Ehmm, OK, OK, even with the changes in kernel, ubi_assert() in
>> leb_write_unlock() wouldn't have triggered ...
>
> Another up_read() crash,
>
> http://lists.infradead.org/pipermail/linux-mtd/2013-July/047512.html
>
> Code: e1530001 0a000016 e3e01000 e5801000 (e8930003)
>
> 00000000 <.data>:
> 0: e1530001 cmp r3, r1
> 4: 0a000016 beq 0x64
> 8: e3e01000 mvn r1, #0
> c: e5801000 str r1, [r0]
> 10: e8930003 ldm r3, {r0, r1}
>
> Thorsten's Oops,
>
> Code: e3e02000 e5842000 e59fc084 e59f0084 (e8930006)
>
> 00000000 <.data>:
> 0: e3e02000 mvn r2, #0
> 4: e5842000 str r2, [r4]
> 8: e59fc084 ldr ip, [pc, #132] ; 0x94
> c: e59f0084 ldr r0, [pc, #132] ; 0x98
> 10: e8930006 ldm r3, {r1, r2}
>
> The registers are different, but the instruction sequence is similar.
> In my ARM926 build, the __up_read() is,
>
> static inline int list_empty(const struct list_head *head)
> {
> return head->next == head;
> 250: e1a01000 mov r1, r0
> 254: e5b12004 ldr r2, [r1, #4]!
> 258: e1520001 cmp r2, r1
> 25c: 0a000017 beq 2c0 <__up_read+0xb0>
> __rwsem_wake_one_writer(struct rw_semaphore *sem)
> {
> struct rwsem_waiter *waiter;
> struct task_struct *tsk;
>
> sem->activity = -1;
> 260: e3e01000 mvn r1, #0
> 264: e5801000 str r1, [r0]
> * in an undefined state.
> */
> #ifndef CONFIG_DEBUG_LIST
> static inline void list_del(struct list_head *entry)
> {
> __list_del(entry->prev, entry->next);
> 268: e8920003 ldm r2, {r0, r1}
> * This is only for internal list manipulation where we know
> * the prev/next entries already!
> */
> static inline void __list_del(struct list_head * prev, struct list_head * next)
> {
> next->prev = prev;
> 26c: e5801004 str r1, [r0, #4]
> prev->next = next;
> 270: e5810000 str r0, [r1]
>
>
> This is the same symptom,
>
> __rwsem_wake_one_writer(struct rw_semaphore *sem)
> {
> ...
> waiter = list_entry(sem->wait_list.next, struct rwsem_waiter, list);
> list_del(&waiter->list);
>
> The sem->wait_list is non-NULL, but the 'sem->wait_list.next' is NULL. I
> would suggest you try with 'DEBUG_LOCK_ALLOC' or something like this.
> The crash points are not the failure, it is when we insert a
> rw_semaphore of 'NULL' or use some memory that is already freed.
CONFIG_DEBUG_LIST please.
Thanks,
//richard
^ permalink raw reply
* [PATCH] ARM: ux500: disable msp2 device tree node
From: Linus Walleij @ 2014-02-04 20:06 UTC (permalink / raw)
To: linux-arm-kernel
Commit 70b41abc151f9
"ARM: ux500: move MSP pin control to the device tree"
accidentally activated MSP2, giving rise to a boot scroll
scream as the kernel attempts to probe a driver for it and
fails to obtain DMA channel 14.
Fix this up by marking the node disabled again.
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 0c1e8d871ed1..6cb9b68e2188 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -188,7 +188,6 @@
msp2: msp at 80117000 {
pinctrl-names = "default";
pinctrl-0 = <&msp2_default_mode>;
- status = "okay";
};
msp3: msp at 80125000 {
--
1.8.5.3
^ permalink raw reply related
* [PATCH] regulator: core: Make regulator object reflect configured voltage
From: Mark Brown @ 2014-02-04 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJAp7Ohn3ch2nK_S8j9ieRBzNeyt6OJmumEhRXXykB9RgMJsQg@mail.gmail.com>
On Tue, Feb 04, 2014 at 11:09:03AM -0800, Bjorn Andersson wrote:
> I have a regulator that's being configured from DT as:
> regulator-min-microvolt = <2950000>;
> regulator-max-microvolt = <2950000>;
> In the consumer I do regulator_set_voltage(2.95V).
> As min == max the voltage is applied by the regulator framework on registration
> of the regulator; and the regulator_set_voltage() fails as
> REGULATOR_CHANGE_VOLTAGE is not set for this regulator.
So we should be changing the code to allow a set_voltage() that sets the
voltage to the existing voltage regardless of constraints allowing a
change then - that's what the underlying issue is. Your change wouldn't
cover the case where the hardware defualt is being used for example.
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* UBI leb_write_unlock NULL pointer Oops (continuation) on ARM926
From: Bill Pringlemeir @ 2014-02-04 19:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <874n4e4xml.fsf@nbsps.com>
On 4 Feb 2014, bpringlemeir at nbsps.com wrote:
> http://lists.infradead.org/pipermail/linux-mtd/2013-May/046907.html
>
> at91sam9g20 - arm926, different MTD driver. Linux 3.6.9
>
> Code: e5903004 e58d2004 e1560003 0a00002a (e593200c)
>
> 0: e5903004 ldr r3, [r0, #4]
> 4: e58d2004 str r2, [sp, #4]
> 8: e1560003 cmp r6, r3
> c: 0a00002a beq 0xbc
> 10: e593200c ldr r2, [r3, #12]
>
> The code sequence looks identical and the Oops trace, etc is the same.
> People from Pengutronix also indicated seeing the same type of Opps; I
> think they deal with the IMX, but maybe this was on another board.
>>>> schrieb Wiedemer, Thorsten (Lawo AG):
> Ehmm, OK, OK, even with the changes in kernel, ubi_assert() in
> leb_write_unlock() wouldn't have triggered ...
Another up_read() crash,
http://lists.infradead.org/pipermail/linux-mtd/2013-July/047512.html
Code: e1530001 0a000016 e3e01000 e5801000 (e8930003)
00000000 <.data>:
0: e1530001 cmp r3, r1
4: 0a000016 beq 0x64
8: e3e01000 mvn r1, #0
c: e5801000 str r1, [r0]
10: e8930003 ldm r3, {r0, r1}
Thorsten's Oops,
Code: e3e02000 e5842000 e59fc084 e59f0084 (e8930006)
00000000 <.data>:
0: e3e02000 mvn r2, #0
4: e5842000 str r2, [r4]
8: e59fc084 ldr ip, [pc, #132] ; 0x94
c: e59f0084 ldr r0, [pc, #132] ; 0x98
10: e8930006 ldm r3, {r1, r2}
The registers are different, but the instruction sequence is similar.
In my ARM926 build, the __up_read() is,
static inline int list_empty(const struct list_head *head)
{
return head->next == head;
250: e1a01000 mov r1, r0
254: e5b12004 ldr r2, [r1, #4]!
258: e1520001 cmp r2, r1
25c: 0a000017 beq 2c0 <__up_read+0xb0>
__rwsem_wake_one_writer(struct rw_semaphore *sem)
{
struct rwsem_waiter *waiter;
struct task_struct *tsk;
sem->activity = -1;
260: e3e01000 mvn r1, #0
264: e5801000 str r1, [r0]
* in an undefined state.
*/
#ifndef CONFIG_DEBUG_LIST
static inline void list_del(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
268: e8920003 ldm r2, {r0, r1}
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static inline void __list_del(struct list_head * prev, struct list_head * next)
{
next->prev = prev;
26c: e5801004 str r1, [r0, #4]
prev->next = next;
270: e5810000 str r0, [r1]
This is the same symptom,
__rwsem_wake_one_writer(struct rw_semaphore *sem)
{
...
waiter = list_entry(sem->wait_list.next, struct rwsem_waiter, list);
list_del(&waiter->list);
The sem->wait_list is non-NULL, but the 'sem->wait_list.next' is NULL. I
would suggest you try with 'DEBUG_LOCK_ALLOC' or something like this.
The crash points are not the failure, it is when we insert a
rw_semaphore of 'NULL' or use some memory that is already freed.
Fwiw,
Bill Pringlemeir.
^ permalink raw reply
* [PATCH v3 3/5] ASoC: tda998x: add DT documentation of the tda998x CODEC
From: Mark Brown @ 2014-02-04 19:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204200239.1baf309b@armhf>
On Tue, Feb 04, 2014 at 08:02:39PM +0100, Jean-Francois Moine wrote:
> Mark Brown <broonie@kernel.org> wrote:
> > On Sat, Feb 01, 2014 at 05:48:49PM +0100, Jean-Francois Moine wrote:
> > > + - compatible: must be "nxp,tda998x-codec".
> > It's not clear to me why there's a separate compatible here - as far as
> > I can see this can only appear as part of one of these devices and
> > there's no addressing or other information that'd account for chip
> > variation so I'd not expect to need to bind this independently of the
> > parent.
> If there is no 'compatible', the CODEC module is not loaded, and, when
> the module is in the core, no CODEC device can be created from the DT.
You're confusing implementation details with device tree specification
here. We can easily handle loading a subdriver without having to put
anything in the device tree, just create a platform device like we do
with MFDs.
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* [PATCH 10/10] ARM: ux500: move last AB8505 set-up to DT
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the set-up of the HREF500 with its AB8505 ASIC to
a device tree include. Since there is not yet any device tree
for this board the DTSI is currently unused. After this delete
the board file for pins for good and migration of pins to the
device tree is complete.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8505.dtsi | 240 ++++++++++++++++++++++++++++++++
arch/arm/mach-ux500/Makefile | 1 -
arch/arm/mach-ux500/board-mop500-pins.c | 93 -------------
arch/arm/mach-ux500/board-mop500.h | 2 -
arch/arm/mach-ux500/cpu-db8500.c | 3 -
5 files changed, 240 insertions(+), 99 deletions(-)
create mode 100644 arch/arm/boot/dts/ste-href-ab8505.dtsi
delete mode 100644 arch/arm/mach-ux500/board-mop500-pins.c
diff --git a/arch/arm/boot/dts/ste-href-ab8505.dtsi b/arch/arm/boot/dts/ste-href-ab8505.dtsi
new file mode 100644
index 000000000000..6006d62086a2
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-ab8505.dtsi
@@ -0,0 +1,240 @@
+/*
+ * Copyright 2014 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+ soc {
+ prcmu at 80157000 {
+ ab8505 {
+ ab8505-gpio {
+ /* Hog a few default settings */
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio2_default_mode>,
+ <&gpio10_default_mode>,
+ <&gpio11_default_mode>,
+ <&gpio13_default_mode>,
+ <&gpio34_default_mode>,
+ <&gpio50_default_mode>,
+ <&pwm_default_mode>,
+ <&adi2_default_mode>,
+ <&modsclsda_default_mode>,
+ <&resethw_default_mode>,
+ <&service_default_mode>;
+
+ /*
+ * Pins 2, 10, 11, 13, 34 and 50
+ * are muxed in as GPIO, and configured as INPUT PULL DOWN
+ */
+ gpio2 {
+ gpio2_default_mode: gpio2_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio2_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO2_R5";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio10 {
+ gpio10_default_mode: gpio10_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio10_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO10_B16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio11 {
+ gpio11_default_mode: gpio11_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio11_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO11_B17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio13 {
+ gpio13_default_mode: gpio13_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio13_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO13_D17";
+ input-enable;
+ bias-disable;
+ };
+ };
+ };
+ gpio34 {
+ gpio34_default_mode: gpio34_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio34_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO34_H14";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio50 {
+ gpio50_default_mode: gpio50_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio50_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO50_L4";
+ input-enable;
+ bias-disable;
+ };
+ };
+ };
+ /* This sets up the PWM pin 14 */
+ pwm {
+ pwm_default_mode: pwm_default {
+ default_mux {
+ ste,function = "pwmout";
+ ste,pins = "pwmout1_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO14_C16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ /* This sets up audio interface 2 */
+ adi2 {
+ adi2_default_mode: adi2_default {
+ default_mux {
+ ste,function = "adi2";
+ ste,pins = "adi2_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO17_P2",
+ "GPIO18_N3",
+ "GPIO19_T1",
+ "GPIO20_P3";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ /* Modem I2C setup (SCL and SDA pins) */
+ modsclsda {
+ modsclsda_default_mode: modsclsda_default {
+ default_mux {
+ ste,function = "modsclsda";
+ ste,pins = "modsclsda_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO40_J15",
+ "GPIO41_J14";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ resethw {
+ resethw_default_mode: resethw_default {
+ default_mux {
+ ste,function = "resethw";
+ ste,pins = "resethw_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO52_D16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ service {
+ service_default_mode: service_default {
+ default_mux {
+ ste,function = "service";
+ ste,pins = "service_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO53_D15";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ /*
+ * Clock output pins associated with regulators.
+ */
+ sysclkreq2 {
+ sysclkreq2_default_mode: sysclkreq2_default {
+ default_mux {
+ ste,function = "sysclkreq";
+ ste,pins = "sysclkreq2_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO1_N4";
+ input-enable;
+ bias-disable;
+ };
+ };
+ sysclkreq2_sleep_mode: sysclkreq2_sleep {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio1_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO1_N4";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ sysclkreq4 {
+ sysclkreq4_default_mode: sysclkreq4_default {
+ default_mux {
+ ste,function = "sysclkreq";
+ ste,pins = "sysclkreq4_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO3_P5";
+ input-enable;
+ bias-disable;
+ };
+ };
+ sysclkreq4_sleep_mode: sysclkreq4_sleep {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio3_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO3_P5";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index d05ba759da30..de544aabf292 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o
obj-$(CONFIG_MACH_MOP500) += board-mop500-sdi.o \
board-mop500-regulators.o \
- board-mop500-pins.o \
board-mop500-audio.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
deleted file mode 100644
index 1597ff7538e3..000000000000
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License (GPL) version 2
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/bug.h>
-#include <linux/string.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-
-#include <asm/mach-types.h>
-
-#include "board-mop500.h"
-
-/* These simply sets bias for pins */
-#define BIAS(a,b) static unsigned long a[] = { b }
-
-BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
-BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
-
-#define AB8505_MUX_HOG(group, func) \
- PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
-#define AB8505_PIN_HOG(pin, conf) \
- PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
-
-#define AB8505_MUX_STATE(group, func, dev, state) \
- PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
-#define AB8505_PIN_STATE(pin, conf, dev, state) \
- PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
-
-static struct pinctrl_map __initdata ab8505_pinmap[] = {
- /* Sysclkreq2 */
- AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
- AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
- /* sysclkreq2 disable, mux in gpio configured in input pulldown */
- AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
- AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
-
- /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
- AB8505_MUX_HOG("gpio2_a_1", "gpio"),
- AB8505_PIN_HOG("GPIO2_R5", in_pd),
-
- /* Sysclkreq4 */
- AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
- AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
- /* sysclkreq4 disable, mux in gpio configured in input pulldown */
- AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
- AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
-
- AB8505_MUX_HOG("gpio10_d_1", "gpio"),
- AB8505_PIN_HOG("GPIO10_B16", in_pd),
-
- AB8505_MUX_HOG("gpio11_d_1", "gpio"),
- AB8505_PIN_HOG("GPIO11_B17", in_pd),
-
- AB8505_MUX_HOG("gpio13_d_1", "gpio"),
- AB8505_PIN_HOG("GPIO13_D17", in_nopull),
-
- AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
- AB8505_PIN_HOG("GPIO14_C16", in_pd),
-
- AB8505_MUX_HOG("adi2_d_1", "adi2"),
- AB8505_PIN_HOG("GPIO17_P2", in_pd),
- AB8505_PIN_HOG("GPIO18_N3", in_pd),
- AB8505_PIN_HOG("GPIO19_T1", in_pd),
- AB8505_PIN_HOG("GPIO20_P3", in_pd),
-
- AB8505_MUX_HOG("gpio34_a_1", "gpio"),
- AB8505_PIN_HOG("GPIO34_H14", in_pd),
-
- AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
- AB8505_PIN_HOG("GPIO40_J15", in_pd),
- AB8505_PIN_HOG("GPIO41_J14", in_pd),
-
- AB8505_MUX_HOG("gpio50_d_1", "gpio"),
- AB8505_PIN_HOG("GPIO50_L4", in_nopull),
-
- AB8505_MUX_HOG("resethw_d_1", "resethw"),
- AB8505_PIN_HOG("GPIO52_D16", in_pd),
-
- AB8505_MUX_HOG("service_d_1", "service"),
- AB8505_PIN_HOG("GPIO53_D15", in_pd),
-};
-
-void __init mop500_pinmaps_init(void)
-{
- if (machine_is_u8520())
- pinctrl_register_mappings(ab8505_pinmap,
- ARRAY_SIZE(ab8505_pinmap));
-}
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 320517e17ac9..bb408b8f48de 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -88,6 +88,4 @@ extern struct msp_i2s_platform_data msp1_platform_data;
extern struct msp_i2s_platform_data msp2_platform_data;
extern struct msp_i2s_platform_data msp3_platform_data;
-void __init mop500_pinmaps_init(void);
-
#endif
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 2e52fcba57bd..180b3c59be36 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -191,9 +191,6 @@ static void __init u8500_init_machine(void)
{
struct device *parent = db8500_soc_device_init();
- /* Pinmaps must be in place before devices register */
- if (of_machine_is_compatible("st-ericsson,mop500"))
- mop500_pinmaps_init();
/* automatically probe child nodes of dbx5x0 devices */
if (of_machine_is_compatible("st-ericsson,u8540"))
of_platform_populate(NULL, u8500_local_bus_nodes,
--
1.8.5.3
^ permalink raw reply related
* [PATCH 09/10] ARM: ux500: move AB8500 clock out pins to DT
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the AB8500 pin settings for the clock out pins over
to the device tree. We can delete the special setup calls for the
platforms only using the AB8500 and not AB8505.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 51 +++++++++++++++++++++++++++++++++
arch/arm/mach-ux500/board-mop500-pins.c | 41 --------------------------
arch/arm/mach-ux500/board-mop500.h | 2 --
arch/arm/mach-ux500/cpu-db8500.c | 7 -----
4 files changed, 51 insertions(+), 50 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 333b554c0bf7..30f8601da323 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -370,6 +370,57 @@
};
};
};
+ /*
+ * Clock output pins associated with regulators.
+ */
+ sysclkreq2 {
+ sysclkreq2_default_mode: sysclkreq2_default {
+ default_mux {
+ ste,function = "sysclkreq";
+ ste,pins = "sysclkreq2_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO1_T10";
+ input-enable;
+ bias-disable;
+ };
+ };
+ sysclkreq2_sleep_mode: sysclkreq2_sleep {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio1_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO1_T10";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ sysclkreq4 {
+ sysclkreq4_default_mode: sysclkreq4_default {
+ default_mux {
+ ste,function = "sysclkreq";
+ ste,pins = "sysclkreq4_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO3_U9";
+ input-enable;
+ bias-disable;
+ };
+ };
+ sysclkreq4_sleep_mode: sysclkreq4_sleep {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio3_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO3_U9";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index cbe91714f57f..1597ff7538e3 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -21,16 +21,6 @@
BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
-#define AB8500_MUX_HOG(group, func) \
- PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
-#define AB8500_PIN_HOG(pin, conf) \
- PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
-
-#define AB8500_MUX_STATE(group, func, dev, state) \
- PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
-#define AB8500_PIN_STATE(pin, conf, dev, state) \
- PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
-
#define AB8505_MUX_HOG(group, func) \
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
#define AB8505_PIN_HOG(pin, conf) \
@@ -41,22 +31,6 @@ BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
#define AB8505_PIN_STATE(pin, conf, dev, state) \
PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
-static struct pinctrl_map __initdata ab8500_pinmap[] = {
- /* Sysclkreq2 */
- AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
- AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
- /* sysclkreq2 disable, mux in gpio configured in input pulldown */
- AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
- AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
-
- /* Sysclkreq4 */
- AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
- AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
- /* sysclkreq4 disable, mux in gpio configured in input pulldown */
- AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
- AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
-};
-
static struct pinctrl_map __initdata ab8505_pinmap[] = {
/* Sysclkreq2 */
AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
@@ -116,19 +90,4 @@ void __init mop500_pinmaps_init(void)
if (machine_is_u8520())
pinctrl_register_mappings(ab8505_pinmap,
ARRAY_SIZE(ab8505_pinmap));
- else
- pinctrl_register_mappings(ab8500_pinmap,
- ARRAY_SIZE(ab8500_pinmap));
-}
-
-void __init snowball_pinmaps_init(void)
-{
- pinctrl_register_mappings(ab8500_pinmap,
- ARRAY_SIZE(ab8500_pinmap));
-}
-
-void __init hrefv60_pinmaps_init(void)
-{
- pinctrl_register_mappings(ab8500_pinmap,
- ARRAY_SIZE(ab8500_pinmap));
}
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index d48e8662c676..320517e17ac9 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -89,7 +89,5 @@ extern struct msp_i2s_platform_data msp2_platform_data;
extern struct msp_i2s_platform_data msp3_platform_data;
void __init mop500_pinmaps_init(void);
-void __init snowball_pinmaps_init(void);
-void __init hrefv60_pinmaps_init(void);
#endif
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index bc8a6183560d..2e52fcba57bd 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -194,13 +194,6 @@ static void __init u8500_init_machine(void)
/* Pinmaps must be in place before devices register */
if (of_machine_is_compatible("st-ericsson,mop500"))
mop500_pinmaps_init();
- else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
- snowball_pinmaps_init();
- } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
- hrefv60_pinmaps_init();
- else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
- /* TODO: Add pinmaps for ccu9540 board. */
-
/* automatically probe child nodes of dbx5x0 devices */
if (of_machine_is_compatible("st-ericsson,u8540"))
of_platform_populate(NULL, u8500_local_bus_nodes,
--
1.8.5.3
^ permalink raw reply related
* [PATCH 08/10] ARM: ux500: move AB8500 modem I2C settings to DT
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the pin setup of the AB8500 modem I2C pins
(SCL/SDA) from the board file to the device tree.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 18 +++++++++++++++++-
arch/arm/mach-ux500/board-mop500-pins.c | 8 --------
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index beb59f99eff8..333b554c0bf7 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -37,7 +37,8 @@
<&adi1_default_mode>,
<&usbuicc_default_mode>,
<&dmic_default_mode>,
- <&extcpena_default_mode>;
+ <&extcpena_default_mode>,
+ <&modsclsda_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -354,6 +355,21 @@
};
};
};
+ /* Modem I2C setup (SCL and SDA pins) */
+ modsclsda {
+ modsclsda_default_mode: modsclsda_default {
+ default_mux {
+ ste,function = "modsclsda";
+ ste,pins = "modsclsda_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO40_T19",
+ "GPIO41_U19";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index bbd5bc56f7f0..cbe91714f57f 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -55,14 +55,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
/* sysclkreq4 disable, mux in gpio configured in input pulldown */
AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
-
- /*
- * pins 40 and 41 are muxed in MODCSLSDA
- * configured INPUT PULL DOWN
- */
- AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
- AB8500_PIN_HOG("GPIO40_T19", in_pd),
- AB8500_PIN_HOG("GPIO41_U19", in_pd),
};
static struct pinctrl_map __initdata ab8505_pinmap[] = {
--
1.8.5.3
^ permalink raw reply related
* [PATCH 07/10] ARM: ux500: move AB8500 EXTCPENA from board file to DT
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the configuration of the AB8500 EXTCPENA pin
from the board file to the device tree.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 17 +++++++++++++++--
arch/arm/mach-ux500/board-mop500-pins.c | 7 -------
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 6222b8e951c2..beb59f99eff8 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -36,7 +36,8 @@
<&pwm_default_mode>,
<&adi1_default_mode>,
<&usbuicc_default_mode>,
- <&dmic_default_mode>;
+ <&dmic_default_mode>,
+ <&extcpena_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -340,7 +341,19 @@
};
};
};
-
+ extcpena {
+ extcpena_default_mode: extcpena_default {
+ default_mux {
+ ste,function = "extcpena";
+ ste,pins = "extcpena_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO34_R17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 851f530e6e16..bbd5bc56f7f0 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -57,13 +57,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/*
- * pins 34 is muxed in EXTCPENA
- * configured INPUT PULL DOWN
- */
- AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
- AB8500_PIN_HOG("GPIO34_R17", in_pd),
-
- /*
* pins 40 and 41 are muxed in MODCSLSDA
* configured INPUT PULL DOWN
*/
--
1.8.5.3
^ permalink raw reply related
* [PATCH 06/10] ARM: ux500: move AB8500 DMIC settings to DT
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This move the AB8500 DMIC (microphone) pin setup from the board
file to the device tree.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 25 ++++++++++++++++++++++++-
arch/arm/mach-ux500/board-mop500-pins.c | 24 ------------------------
2 files changed, 24 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 9cf12d5d0923..6222b8e951c2 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -35,7 +35,8 @@
<&ycbcr_default_mode>,
<&pwm_default_mode>,
<&adi1_default_mode>,
- <&usbuicc_default_mode>;
+ <&usbuicc_default_mode>,
+ <&dmic_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -318,6 +319,28 @@
};
};
};
+ /* This sets up the microphone pins */
+ dmic {
+ dmic_default_mode: dmic_default {
+ default_mux {
+ ste,function = "dmic";
+ ste,pins = "dmic12_d_1",
+ "dmic34_d_1",
+ "dmic56_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO27_J6",
+ "GPIO28_K6",
+ "GPIO29_G6",
+ "GPIO30_H6",
+ "GPIO31_F5",
+ "GPIO32_G5";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 443b1f4b828a..851f530e6e16 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -57,30 +57,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/*
- * pins 27,28 are muxed in DMIC12
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("dmic12_d_1", "dmic"),
- AB8500_PIN_HOG("GPIO27_J6", in_pd),
- AB8500_PIN_HOG("GPIO28_K6", in_pd),
-
- /*
- * pins 29,30 are muxed in DMIC34
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("dmic34_d_1", "dmic"),
- AB8500_PIN_HOG("GPIO29_G6", in_pd),
- AB8500_PIN_HOG("GPIO30_H6", in_pd),
-
- /*
- * pins 31,32 are muxed in DMIC56
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("dmic56_d_1", "dmic"),
- AB8500_PIN_HOG("GPIO31_F5", in_pd),
- AB8500_PIN_HOG("GPIO32_G5", in_pd),
-
- /*
* pins 34 is muxed in EXTCPENA
* configured INPUT PULL DOWN
*/
--
1.8.5.3
^ permalink raw reply related
* [PATCH 05/10] ARM: ux500: move AB8500 USB UICC settings to DT
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the set-up of the USB UICC (InteChip USB) from the
board file to the device tree.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 19 ++++++++++++++++++-
arch/arm/mach-ux500/board-mop500-pins.c | 9 ---------
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 3aae4ec5bcc9..9cf12d5d0923 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -34,7 +34,8 @@
<&gpio35_default_mode>,
<&ycbcr_default_mode>,
<&pwm_default_mode>,
- <&adi1_default_mode>;
+ <&adi1_default_mode>,
+ <&usbuicc_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -301,6 +302,22 @@
};
};
};
+ /* This sets up the USB UICC pins */
+ usbuicc {
+ usbuicc_default_mode: usbuicc_default {
+ default_mux {
+ ste,function = "usbuicc";
+ ste,pins = "usbuicc_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO21_H19",
+ "GPIO22_G20",
+ "GPIO23_G19";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index d0b262242ab7..443b1f4b828a 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -57,15 +57,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/*
- * pins 21,22 and 23 are muxed in USB UICC
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
- AB8500_PIN_HOG("GPIO21_H19", in_pd),
- AB8500_PIN_HOG("GPIO22_G20", in_pd),
- AB8500_PIN_HOG("GPIO23_G19", in_pd),
-
- /*
* pins 27,28 are muxed in DMIC12
* configured in INPUT PULL DOWN
*/
--
1.8.5.3
^ permalink raw reply related
* [PATCH 04/10] ARM: ux500: move AB8500 audio interface 1 settings to DT
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the pin muxing and configuration for audio interface
one over to the device tree as a hog configuration.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 20 +++++++++++++++++++-
arch/arm/mach-ux500/board-mop500-pins.c | 10 ----------
2 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index cdf2b3fd22dc..3aae4ec5bcc9 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -33,7 +33,8 @@
<&gpio26_default_mode>,
<&gpio35_default_mode>,
<&ycbcr_default_mode>,
- <&pwm_default_mode>;
+ <&pwm_default_mode>,
+ <&adi1_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -283,6 +284,23 @@
};
};
};
+ /* This sets up audio interface 1 */
+ adi1 {
+ adi1_default_mode: adi1_default {
+ default_mux {
+ ste,function = "adi1";
+ ste,pins = "adi1_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO17_P5",
+ "GPIO18_R5",
+ "GPIO19_U5",
+ "GPIO20_T5";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index b75089faf956..d0b262242ab7 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -57,16 +57,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/*
- * pins 17,18,19 and 20 are muxed in AUDIO interface 1
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("adi1_d_1", "adi1"),
- AB8500_PIN_HOG("GPIO17_P5", in_pd),
- AB8500_PIN_HOG("GPIO18_R5", in_pd),
- AB8500_PIN_HOG("GPIO19_U5", in_pd),
- AB8500_PIN_HOG("GPIO20_T5", in_pd),
-
- /*
* pins 21,22 and 23 are muxed in USB UICC
* configured in INPUT PULL DOWN
*/
--
1.8.5.3
^ permalink raw reply related
* [PATCH 03/10] ARM: ux500: move AB8500 PWM out settings to device tree
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the muxing and biasing of the AB8500 PWM output pins
over to the device tree for affected platforms.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 18 +++++++++++++++++-
arch/arm/mach-ux500/board-mop500-pins.c | 10 ----------
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 2b548e90878e..cdf2b3fd22dc 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -32,7 +32,8 @@
<&gpio42_default_mode>,
<&gpio26_default_mode>,
<&gpio35_default_mode>,
- <&ycbcr_default_mode>;
+ <&ycbcr_default_mode>,
+ <&pwm_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -267,6 +268,21 @@
};
};
};
+ /* This sets up the PWM pins 14 and 15 */
+ pwm {
+ pwm_default_mode: pwm_default {
+ default_mux {
+ ste,function = "pwmout";
+ ste,pins = "pwmout1_d_1", "pwmout2_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO14_F14",
+ "GPIO15_B17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index d58513b08a6d..b75089faf956 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -57,16 +57,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/*
- * pins 14,15 are muxed in PWM1 and PWM2
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
- AB8500_PIN_HOG("GPIO14_F14", in_pd),
-
- AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
- AB8500_PIN_HOG("GPIO15_B17", in_pd),
-
- /*
* pins 17,18,19 and 20 are muxed in AUDIO interface 1
* configured in INPUT PULL DOWN
*/
--
1.8.5.3
^ permalink raw reply related
* [PATCH 02/10] ARM: ux500: move AB8500 YCBCR settings to device tree
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543546-11158-1-git-send-email-linus.walleij@linaro.org>
This moves the pin control settings for the YCBCR connector
on the AB8500 over to the device tree as a hog.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 23 ++++++++++++++++++++++-
arch/arm/mach-ux500/board-mop500-pins.c | 10 ----------
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 58b00d0f023e..2b548e90878e 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -31,7 +31,8 @@
<&gpio39_default_mode>,
<&gpio42_default_mode>,
<&gpio26_default_mode>,
- <&gpio35_default_mode>;
+ <&gpio35_default_mode>,
+ <&ycbcr_default_mode>;
/*
* Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
@@ -246,6 +247,26 @@
};
};
};
+ /*
+ * This sets up the YCBCR connector pins, i.e. analog video out.
+ * Set as input with no bias.
+ */
+ ycbcr {
+ ycbcr_default_mode: ycbcr_default {
+ default_mux {
+ ste,function = "ycbcr";
+ ste,pins = "ycbcr0123_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO6_Y18",
+ "GPIO7_AA20",
+ "GPIO8_W18",
+ "GPIO9_AA19";
+ input-enable;
+ bias-disable;
+ };
+ };
+ };
};
};
};
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 139298043685..d58513b08a6d 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -57,16 +57,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/*
- * pins 6,7,8 and 9 are muxed in YCBCR0123
- * configured in INPUT PULL UP
- */
- AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
- AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
- AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
- AB8500_PIN_HOG("GPIO8_W18", in_nopull),
- AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
-
- /*
* pins 14,15 are muxed in PWM1 and PWM2
* configured in INPUT PULL DOWN
*/
--
1.8.5.3
^ permalink raw reply related
* [PATCH 01/10] ARM: ux500: move AB8500 GPIOs to device tree
From: Linus Walleij @ 2014-02-04 19:52 UTC (permalink / raw)
To: linux-arm-kernel
Move the AB8500 muxing and biasing settings over from the board
file to the device tree, include it in the reference designs using
the AB8500: HREF prior to v60, v60plus and Snowball. Set up these
GPIO lines using hogs, just like in the board file.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-href-ab8500.dtsi | 253 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/ste-hrefprev60.dtsi | 1 +
arch/arm/boot/dts/ste-hrefv60plus.dtsi | 1 +
arch/arm/boot/dts/ste-snowball.dts | 1 +
arch/arm/mach-ux500/board-mop500-pins.c | 79 ----------
5 files changed, 256 insertions(+), 79 deletions(-)
create mode 100644 arch/arm/boot/dts/ste-href-ab8500.dtsi
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
new file mode 100644
index 000000000000..58b00d0f023e
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -0,0 +1,253 @@
+/*
+ * Copyright 2014 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+ soc {
+ prcmu at 80157000 {
+ ab8500 {
+ ab8500-gpio {
+ /* Hog a few default settings */
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio2_default_mode>,
+ <&gpio4_default_mode>,
+ <&gpio10_default_mode>,
+ <&gpio11_default_mode>,
+ <&gpio12_default_mode>,
+ <&gpio13_default_mode>,
+ <&gpio16_default_mode>,
+ <&gpio24_default_mode>,
+ <&gpio25_default_mode>,
+ <&gpio36_default_mode>,
+ <&gpio37_default_mode>,
+ <&gpio38_default_mode>,
+ <&gpio39_default_mode>,
+ <&gpio42_default_mode>,
+ <&gpio26_default_mode>,
+ <&gpio35_default_mode>;
+
+ /*
+ * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
+ * are muxed in as GPIO, and configured as INPUT PULL DOWN
+ */
+ gpio2 {
+ gpio2_default_mode: gpio2_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio2_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO2_T9";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio4 {
+ gpio4_default_mode: gpio4_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio4_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO4_W2";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio10 {
+ gpio10_default_mode: gpio10_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio10_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO10_U17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio11 {
+ gpio11_default_mode: gpio11_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio11_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO11_AA18";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio12 {
+ gpio12_default_mode: gpio12_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio12_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO12_U16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio13 {
+ gpio13_default_mode: gpio13_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio13_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO13_W17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio16 {
+ gpio16_default_mode: gpio16_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio16_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO16_F15";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio24 {
+ gpio24_default_mode: gpio24_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio24_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO24_T14";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio25 {
+ gpio25_default_mode: gpio25_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio25_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO25_R16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio36 {
+ gpio36_default_mode: gpio36_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio36_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO36_A17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio37 {
+ gpio37_default_mode: gpio37_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio37_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO37_E15";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio38 {
+ gpio38_default_mode: gpio38_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio38_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO38_C17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio39 {
+ gpio39_default_mode: gpio39_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio39_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO39_E16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio42 {
+ gpio42_default_mode: gpio42_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio42_a_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO42_U2";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ /*
+ * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW
+ */
+ gpio26 {
+ gpio26_default_mode: gpio26_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio26_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO26_M16";
+ output-low;
+ };
+ };
+ };
+ gpio35 {
+ gpio35_default_mode: gpio35_default {
+ default_mux {
+ ste,function = "gpio";
+ ste,pins = "gpio35_d_1";
+ };
+ default_cfg {
+ ste,pins = "GPIO35_W15";
+ output-low;
+ };
+ };
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index 40f0ecdf9303..abc762e24fcb 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -12,6 +12,7 @@
*/
#include "ste-dbx5x0.dtsi"
+#include "ste-href-ab8500.dtsi"
#include "ste-href.dtsi"
/ {
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index 3b6d1181939b..c2341061b943 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -10,6 +10,7 @@
*/
#include "ste-dbx5x0.dtsi"
+#include "ste-href-ab8500.dtsi"
#include "ste-href.dtsi"
/ {
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 97d5d21b7db7..a2f632d0be2a 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -11,6 +11,7 @@
/dts-v1/;
#include "ste-dbx5x0.dtsi"
+#include "ste-href-ab8500.dtsi"
#include "ste-href-family-pinctrl.dtsi"
/ {
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index f63619b69113..139298043685 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -18,7 +18,6 @@
/* These simply sets bias for pins */
#define BIAS(a,b) static unsigned long a[] = { b }
-BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
@@ -50,10 +49,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
- /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
- AB8500_MUX_HOG("gpio2_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO2_T9", in_pd),
-
/* Sysclkreq4 */
AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
@@ -61,10 +56,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
- /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
- AB8500_MUX_HOG("gpio4_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO4_W2", in_pd),
-
/*
* pins 6,7,8 and 9 are muxed in YCBCR0123
* configured in INPUT PULL UP
@@ -76,22 +67,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
/*
- * pins 10,11,12 and 13 are muxed in GPIO
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("gpio10_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO10_U17", in_pd),
-
- AB8500_MUX_HOG("gpio11_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO11_AA18", in_pd),
-
- AB8500_MUX_HOG("gpio12_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO12_U16", in_pd),
-
- AB8500_MUX_HOG("gpio13_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO13_W17", in_pd),
-
- /*
* pins 14,15 are muxed in PWM1 and PWM2
* configured in INPUT PULL DOWN
*/
@@ -102,13 +77,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_HOG("GPIO15_B17", in_pd),
/*
- * pins 16 is muxed in GPIO
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("gpio16_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO14_F14", in_pd),
-
- /*
* pins 17,18,19 and 20 are muxed in AUDIO interface 1
* configured in INPUT PULL DOWN
*/
@@ -128,23 +96,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_HOG("GPIO23_G19", in_pd),
/*
- * pins 24,25 are muxed in GPIO
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("gpio24_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO24_T14", in_pd),
-
- AB8500_MUX_HOG("gpio25_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO25_R16", in_pd),
-
- /*
- * pins 26 is muxed in GPIO
- * configured in OUTPUT LOW
- */
- AB8500_MUX_HOG("gpio26_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO26_M16", out_lo),
-
- /*
* pins 27,28 are muxed in DMIC12
* configured in INPUT PULL DOWN
*/
@@ -176,42 +127,12 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = {
AB8500_PIN_HOG("GPIO34_R17", in_pd),
/*
- * pins 35 is muxed in GPIO
- * configured in OUTPUT LOW
- */
- AB8500_MUX_HOG("gpio35_d_1", "gpio"),
- AB8500_PIN_HOG("GPIO35_W15", in_pd),
-
- /*
- * pins 36,37,38 and 39 are muxed in GPIO
- * configured in INPUT PULL DOWN
- */
- AB8500_MUX_HOG("gpio36_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO36_A17", in_pd),
-
- AB8500_MUX_HOG("gpio37_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO37_E15", in_pd),
-
- AB8500_MUX_HOG("gpio38_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO38_C17", in_pd),
-
- AB8500_MUX_HOG("gpio39_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO39_E16", in_pd),
-
- /*
* pins 40 and 41 are muxed in MODCSLSDA
* configured INPUT PULL DOWN
*/
AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
AB8500_PIN_HOG("GPIO40_T19", in_pd),
AB8500_PIN_HOG("GPIO41_U19", in_pd),
-
- /*
- * pins 42 is muxed in GPIO
- * configured INPUT PULL DOWN
- */
- AB8500_MUX_HOG("gpio42_a_1", "gpio"),
- AB8500_PIN_HOG("GPIO42_U2", in_pd),
};
static struct pinctrl_map __initdata ab8505_pinmap[] = {
--
1.8.5.3
^ permalink raw reply related
* [PATCH v2 5/5] ARM: bcm_defconfig: Enable PWM and Backlight
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543503-14773-1-git-send-email-tim.kryger@linaro.org>
Enable PWM drivers and the PWM-based backlight driver.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
---
arch/arm/configs/bcm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index 2519d6d..b1898c3 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -84,6 +84,7 @@ CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
@@ -97,6 +98,7 @@ CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_PWM=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
--
1.8.0.1
^ permalink raw reply related
* [PATCH v2 4/5] ARM: dts: Enable the PWM for bcm28155 AP board
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543503-14773-1-git-send-email-tim.kryger@linaro.org>
Mark the PWM as enabled on the bcm28155 AP board.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
---
arch/arm/boot/dts/bcm28155-ap.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts
index 5ff2382..37c72eb 100644
--- a/arch/arm/boot/dts/bcm28155-ap.dts
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -66,6 +66,10 @@
status = "okay";
};
+ pwm: pwm at 3e01a000 {
+ status = "okay";
+ };
+
usbotg: usb at 3f120000 {
status = "okay";
};
--
1.8.0.1
^ permalink raw reply related
* [PATCH v2 3/5] ARM: dts: Declare the PWM for bcm11351 (bcm281xx)
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543503-14773-1-git-send-email-tim.kryger@linaro.org>
Add the device tree node for the PWM on bcm11351 SoCs.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
---
arch/arm/boot/dts/bcm11351.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index e491b82..5296c3d 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -191,6 +191,14 @@
status = "disabled";
};
+ pwm: pwm at 3e01a000 {
+ compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
+ reg = <0x3e01a000 0xcc>;
+ clocks = <&pwm_clk>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
clocks {
bsc1_clk: bsc1 {
compatible = "fixed-clock";
--
1.8.0.1
^ permalink raw reply related
* [PATCH v2 2/5] pwm: kona: Introduce Kona PWM controller support
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543503-14773-1-git-send-email-tim.kryger@linaro.org>
Add support for the six-channel Kona PWM controller found on Broadcom
mobile SoCs like bcm281xx.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
---
drivers/pwm/Kconfig | 10 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-bcm-kona.c | 291 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 302 insertions(+)
create mode 100644 drivers/pwm/pwm-bcm-kona.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 22f2f28..1fd42af 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -62,6 +62,16 @@ config PWM_ATMEL_TCB
To compile this driver as a module, choose M here: the module
will be called pwm-atmel-tcb.
+config PWM_BCM_KONA
+ tristate "Kona PWM support"
+ depends on ARCH_BCM_MOBILE
+ default y
+ help
+ Generic PWM framework driver for Broadcom Kona PWM block.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-bcm-kona.
+
config PWM_BFIN
tristate "Blackfin PWM support"
depends on BFIN_GPTIMERS
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index d8906ec..7413090 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_PWM_SYSFS) += sysfs.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
+obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o
obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o
diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
new file mode 100644
index 0000000..631ec14
--- /dev/null
+++ b/drivers/pwm/pwm-bcm-kona.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#define PWM_CONTROL_OFFSET (0x00000000)
+#define PWM_CONTROL_SMOOTH_SHIFT(chan) (24 + (chan))
+#define PWM_CONTROL_TYPE_SHIFT(chan) (16 + (chan))
+#define PWM_CONTROL_POLARITY_SHIFT(chan) (8 + (chan))
+#define PWM_CONTROL_ENABLE_SHIFT(chan) (chan)
+
+#define PRESCALE_OFFSET (0x00000004)
+#define PRESCALE_SHIFT(chan) ((chan) << 2)
+#define PRESCALE_MASK(chan) (0x7 << PRESCALE_SHIFT(chan))
+#define PRESCALE_MIN (0x00000000)
+#define PRESCALE_MAX (0x00000007)
+
+#define PERIOD_COUNT_OFFSET(chan) (0x00000008 + ((chan) << 3))
+#define PERIOD_COUNT_MIN (0x00000002)
+#define PERIOD_COUNT_MAX (0x00ffffff)
+
+#define DUTY_CYCLE_HIGH_OFFSET(chan) (0x0000000c + ((chan) << 3))
+#define DUTY_CYCLE_HIGH_MIN (0x00000000)
+#define DUTY_CYCLE_HIGH_MAX (0x00ffffff)
+
+struct kona_pwmc {
+ struct pwm_chip chip;
+ void __iomem *base;
+ struct clk *clk;
+};
+
+static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
+{
+ /* New settings take effect on rising edge of enable bit */
+ unsigned long value = readl(kp->base + PWM_CONTROL_OFFSET);
+
+ value &= ~(1 << PWM_CONTROL_ENABLE_SHIFT(chan));
+ writel(value, kp->base + PWM_CONTROL_OFFSET);
+
+ value |= (1 << PWM_CONTROL_ENABLE_SHIFT(chan));
+ writel(value, kp->base + PWM_CONTROL_OFFSET);
+}
+
+static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
+ int duty_ns, int period_ns)
+{
+ struct kona_pwmc *kp = dev_get_drvdata(chip->dev);
+ u64 val, div, clk_rate;
+ unsigned long prescale = PRESCALE_MIN, pc, dc;
+ unsigned int value, chan = pwm->hwpwm;
+
+ /*
+ * Find period count, duty count and prescale to suit duty_ns and
+ * period_ns. This is done according to formulas described below:
+ *
+ * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
+ * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
+ *
+ * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
+ * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
+ */
+
+ clk_rate = clk_get_rate(kp->clk);
+
+ /* There is polarity support in HW but it is easier to manage in SW */
+ if (pwm->polarity == PWM_POLARITY_INVERSED)
+ duty_ns = period_ns - duty_ns;
+
+ while (1) {
+ div = 1000000000;
+ div *= 1 + prescale;
+ val = clk_rate * period_ns;
+ pc = div64_u64(val, div);
+ val = clk_rate * duty_ns;
+ dc = div64_u64(val, div);
+
+ /* If duty_ns or period_ns are not achievable then return */
+ if (pc < PERIOD_COUNT_MIN || dc < DUTY_CYCLE_HIGH_MIN)
+ return -EINVAL;
+
+ /* If pc and dc are in bounds, the calculation is done */
+ if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)
+ break;
+
+ /* Otherwise, increase prescale and recalculate pc and dc */
+ if (++prescale > PRESCALE_MAX)
+ return -EINVAL;
+ }
+
+ /* If the PWM channel is enabled, write the settings to the HW */
+ if (test_bit(PWMF_ENABLED, &pwm->flags)) {
+ value = readl(kp->base + PRESCALE_OFFSET);
+ value &= ~PRESCALE_MASK(chan);
+ value |= prescale << PRESCALE_SHIFT(chan);
+ writel(value, kp->base + PRESCALE_OFFSET);
+
+ writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
+
+ writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
+
+ kona_pwmc_apply_settings(kp, chan);
+ }
+
+ return 0;
+}
+
+static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
+ enum pwm_polarity polarity)
+{
+ /*
+ * The framework only allows the polarity to be changed when a PWM is
+ * disabled so no immediate action is required here. When a channel is
+ * enabled, the polarity gets handled as part of the re-config step.
+ */
+
+ return 0;
+}
+
+static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct kona_pwmc *kp = dev_get_drvdata(chip->dev);
+ int ret;
+
+ /*
+ * The PWM framework does not clear the enable bit in the flags if an
+ * error is returned from a PWM driver's enable function so it must be
+ * cleared here if any trouble is encountered.
+ */
+
+ ret = clk_prepare_enable(kp->clk);
+ if (ret < 0) {
+ dev_err(chip->dev, "failed to enable clock: %d\n", ret);
+ clear_bit(PWMF_ENABLED, &pwm->flags);
+ return ret;
+ }
+
+ ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period);
+ if (ret < 0) {
+ clk_disable_unprepare(kp->clk);
+ clear_bit(PWMF_ENABLED, &pwm->flags);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct kona_pwmc *kp = dev_get_drvdata(chip->dev);
+ unsigned int chan = pwm->hwpwm;
+
+ /*
+ * The "enable" bits in the control register only affect when settings
+ * start to take effect so the only real way to disable the PWM output
+ * is to program a zero duty cycle.
+ */
+
+ writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
+ kona_pwmc_apply_settings(kp, chan);
+
+ /*
+ * When the PWM clock is disabled, the output is pegged high or low
+ * depending on its state at that instant. To guarantee that the new
+ * settings have taken effect and the output is low a delay of 400ns is
+ * required.
+ */
+
+ ndelay(400);
+
+ clk_disable_unprepare(kp->clk);
+}
+
+static const struct pwm_ops kona_pwm_ops = {
+ .config = kona_pwmc_config,
+ .set_polarity = kona_pwmc_set_polarity,
+ .enable = kona_pwmc_enable,
+ .disable = kona_pwmc_disable,
+ .owner = THIS_MODULE,
+};
+
+static int kona_pwmc_probe(struct platform_device *pdev)
+{
+ struct kona_pwmc *kp;
+ struct resource *res;
+ unsigned int chan, value;
+ int ret = 0;
+
+ kp = devm_kzalloc(&pdev->dev, sizeof(*kp), GFP_KERNEL);
+ if (kp == NULL)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, kp);
+
+ kp->chip.dev = &pdev->dev;
+ kp->chip.ops = &kona_pwm_ops;
+ kp->chip.base = -1;
+ kp->chip.npwm = 6;
+ kp->chip.of_xlate = of_pwm_xlate_with_flags;
+ kp->chip.of_pwm_n_cells = 3;
+ kp->chip.can_sleep = true;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ kp->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(kp->base))
+ return PTR_ERR(kp->base);
+
+ kp->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(kp->clk)) {
+ dev_err(&pdev->dev, "failed to get clock: %ld\n",
+ PTR_ERR(kp->clk));
+ return PTR_ERR(kp->clk);
+ }
+
+ ret = clk_prepare_enable(kp->clk);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
+ return ret;
+ }
+
+ /* Set smooth mode, push/pull, and normal polarity for all channels */
+ for (value = 0, chan = 0; chan < kp->chip.npwm; chan++) {
+ value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
+ value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
+ value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan));
+ }
+ writel(value, kp->base + PWM_CONTROL_OFFSET);
+
+ clk_disable_unprepare(kp->clk);
+
+ ret = pwmchip_add(&kp->chip);
+ if (ret < 0)
+ dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
+
+ return ret;
+}
+
+static int kona_pwmc_remove(struct platform_device *pdev)
+{
+ struct kona_pwmc *kp = platform_get_drvdata(pdev);
+ unsigned int chan;
+
+ for (chan = 0; chan < kp->chip.npwm; chan++)
+ if (test_bit(PWMF_ENABLED, &kp->chip.pwms[chan].flags))
+ clk_disable_unprepare(kp->clk);
+
+ return pwmchip_remove(&kp->chip);
+}
+
+static const struct of_device_id bcm_kona_pwmc_dt[] = {
+ { .compatible = "brcm,kona-pwm" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt);
+
+static struct platform_driver kona_pwmc_driver = {
+
+ .driver = {
+ .name = "bcm-kona-pwm",
+ .of_match_table = bcm_kona_pwmc_dt,
+ },
+ .probe = kona_pwmc_probe,
+ .remove = kona_pwmc_remove,
+};
+
+module_platform_driver(kona_pwmc_driver);
+
+MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
+MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
+MODULE_DESCRIPTION("Driver for Kona PWM controller");
+MODULE_LICENSE("GPL v2");
--
1.8.0.1
^ permalink raw reply related
* [PATCH v2 1/5] Documentation: dt: Add Kona PWM binding
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391543503-14773-1-git-send-email-tim.kryger@linaro.org>
Add the binding description for the Kona PWM controller found on Broadcom's
mobile SoCs.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
---
.../devicetree/bindings/pwm/bcm-kona-pwm.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt
diff --git a/Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt b/Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt
new file mode 100644
index 0000000..c8e2d13
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt
@@ -0,0 +1,24 @@
+Broadcom Kona PWM controller device tree bindings
+
+This controller has 6 channels.
+
+Required Properties :
+- compatible: should be "brcm,kona-pwm"
+- reg: physical base address and length of the controller's registers
+- clocks: phandle + clock specifier pair for the external clock
+- #pwm-cells: should be 3. The first cell specifies the per-chip index
+ of the PWM to use, the second cell is the period in nanoseconds, and
+ the third cell is the flags.
+
+Refer to pwm/pwm.txt for generic pwm controller node properties.
+
+Refer to clocks/clock-bindings.txt for generic clock consumer properties.
+
+Example:
+
+pwm: pwm at 3e01a000 {
+ compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
+ reg = <0x3e01a000 0xc4>;
+ clocks = <&pwm_clk>;
+ #pwm-cells = <3>;
+};
--
1.8.0.1
^ permalink raw reply related
* [PATCH v2 0/5] Add Broadcom Kona PWM Support
From: Tim Kryger @ 2014-02-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
This series introduces the driver for the Kona PWM controller found in
Broadcom mobile SoCs like bcm281xx and updates the device tree and the
defconfig to enable use of this hardware on the bcm28155 AP board.
Changes since v1:
- Fixed up macros to be clearer and more complete
- Corrected spelling and punctuation mistakes
- Added support for polarity
- Made peripheral clock use more efficient
- Made prescale and duty computation clearer
- Moved Makefile addition to keep alphabetical
- Split complex lines into multiple steps
Tim Kryger (5):
Documentation: dt: Add Kona PWM binding
pwm: kona: Introduce Kona PWM controller support
ARM: dts: Declare the PWM for bcm11351 (bcm281xx)
ARM: dts: Enable the PWM for bcm28155 AP board
ARM: bcm_defconfig: Enable PWM and Backlight
.../devicetree/bindings/pwm/bcm-kona-pwm.txt | 24 ++
arch/arm/boot/dts/bcm11351.dtsi | 8 +
arch/arm/boot/dts/bcm28155-ap.dts | 4 +
arch/arm/configs/bcm_defconfig | 2 +
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-bcm-kona.c | 291 +++++++++++++++++++++
7 files changed, 340 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/bcm-kona-pwm.txt
create mode 100644 drivers/pwm/pwm-bcm-kona.c
--
1.8.0.1
^ permalink raw reply
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