* [PATCH] ARM: OMAP4: hwmod: Fix SOFTRESET logic for OMAP4
From: Grygorii Strashko @ 2014-02-05 17:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391612769-27890-1-git-send-email-illia.smyrnov@globallogic.com>
Hi All,
On 02/05/2014 05:06 PM, Illia Smyrnov wrote:
> Commit 313a76e (ARM: OMAP2+: hwmod: Fix SOFTRESET logic) introduced
> softreset bit cleaning right after set one. It is caused L3 error for
> OMAP4 ISS because ISS register write occurs when ISS reset process is in
> progress. Avoid this situation by cleaning softreset bit later, when reset
> process is successfully finished.
I'd like to mention that this issue has been caught while upgrading
custom Linux Kernel 3.4 to the last Stable Kernel linux-3.4.y.
So, the same OMAP4+ functionality can be broken in all Stable trees
where commit "ARM: OMAP2+: hwmod: Fix SOFTRESET logic" was merged to.
On OMAP4+ we should always try to wait until IP reset is finished before proceed.
Reviewed-by: "Grygorii Strashko <grygorii.strashko@ti.com>"
Error log example (k3.4):
[ 5766.575347] ------------[ cut here ]------------
[ 5766.580749] WARNING: at arch/arm/mach-omap2/omap_l3_noc.c:97 l3_interrupt_handler+0xc0/0x170()
[ 5766.590209] L3 standard error: TARGET:ISS at address 0x10
[ 5766.596435] Modules linked in: wlcore_sdio(O) wl18xx(O) wl12xx(O) wlcore(O) mac80211(O) pvrsrvkm_sgx544_112(O) cfg80211(O) compat(O)
[ 5766.611022] Backtrace:
[ 5766.614013] [<c00180ec>] (dump_backtrace+0x0/0x10c) from [<c065d448>] (dump_stack+0x18/0x1c)
[ 5766.623413] r6:c003a19c r5:00000009 r4:c0921d80 r3:c0982f10
[ 5766.630340] [<c065d430>] (dump_stack+0x0/0x1c) from [<c0046cf4>] (warn_slowpath_common+0x54/0x6c)
[ 5766.640258] [<c0046ca0>] (warn_slowpath_common+0x0/0x6c) from [<c0046db0>] (warn_slowpath_fmt+0x38/0x40)
[ 5766.650787] r8:00000000 r7:00000018 r6:c06712c4 r5:80080001 r4:e08f4400
[ 5766.658630] r3:00000009
[ 5766.661926] [<c0046d78>] (warn_slowpath_fmt+0x0/0x40) from [<c003a19c>] (l3_interrupt_handler+0xc0/0x170)
[ 5766.672546] r3:c080790c r2:c0807858
[ 5766.676910] [<c003a0dc>] (l3_interrupt_handler+0x0/0x170) from [<c00a8bc0>] (handle_irq_event_percpu+0x64/0x2b0)
[ 5766.688201] r8:00000000 r7:0000002a r6:0000002a r5:c0924190 r4:d6cbeac0
[ 5766.696533] [<c00a8b5c>] (handle_irq_event_percpu+0x0/0x2b0) from [<c00a8e50>] (handle_irq_event+0x44/0x64)
[ 5766.707244] [<c00a8e0c>] (handle_irq_event+0x0/0x64) from [<c00abb80>] (handle_fasteoi_irq+0xa0/0x160)
[ 5766.717620] r6:c0920000 r5:c0924190 r4:c0924140 r3:00000000
[ 5766.724639] [<c00abae0>] (handle_fasteoi_irq+0x0/0x160) from [<c00a83ac>] (generic_handle_irq+0x30/0x44)
[ 5766.735198] r5:c091e538 r4:c0946d40
[ 5766.739562] [<c00a837c>] (generic_handle_irq+0x0/0x44) from [<c0014b88>] (handle_IRQ+0x54/0xb8)
[ 5766.749267] [<c0014b34>] (handle_IRQ+0x0/0xb8) from [<c00084d0>] (gic_handle_irq+0x2c/0x60)
[ 5766.758453] r8:00000000 r7:c0921ed4 r6:c0921ea0 r5:c0945a00 r4:e0802100
[ 5766.766448] r3:c008aeb8
[ 5766.769744] [<c00084a4>] (gic_handle_irq+0x0/0x60) from [<c06678c0>] (__irq_svc+0x40/0x70)
[ 5766.778991] Exception stack(0xc0921ea0 to 0xc0921ee8)
[ 5766.784637] 1ea0: c0921ee8 000be65e a237f8b7 0000053e a2378182 0000053e c1858498 00000000
[ 5766.793762] 1ec0: 00000000 c095645c c0a3350c c0921f14 00001686 c0921ee8 c008aeb8 c042e5b4
[ 5766.802886] 1ee0: 60070013 ffffffff
[ 5766.806823] r6:ffffffff r5:60070013 r4:c042e5b4 r3:c008aeb8
[ 5766.813903] [<c042e564>] (cpuidle_wrap_enter+0x0/0x9c) from [<c042db94>] (cpuidle_enter_tk+0x18/0x1c)
[ 5766.824035] r7:c09c35b4 r6:c1858498 r5:00000000 r4:c1858498
[ 5766.830963] [<c042db7c>] (cpuidle_enter_tk+0x0/0x1c) from [<c042e0b0>] (cpuidle_enter_state+0x1c/0x78)
[ 5766.841339] [<c042e094>] (cpuidle_enter_state+0x0/0x78) from [<c042e1ec>] (cpuidle_idle_call+0xe0/0x31c)
[ 5766.851898] r6:c0920000 r5:00000000 r4:c1858498 r3:0000004c
[ 5766.858825] [<c042e10c>] (cpuidle_idle_call+0x0/0x31c) from [<c00152b4>] (cpu_idle+0xa4/0x10c)
[ 5766.868438] [<c0015210>] (cpu_idle+0x0/0x10c) from [<c063ce50>] (rest_init+0x74/0x8c)
[ 5766.877227] [<c063cddc>] (rest_init+0x0/0x8c) from [<c08c7864>] (start_kernel+0x2b4/0x304)
[ 5766.886352] r4:c0946b20 r3:c0982f10
[ 5766.890808] [<c08c75b0>] (start_kernel+0x0/0x304) from [<80008044>] (0x80008044)
[ 5766.898986] Board Information:
[ 5766.898986] Revision : 20edb4
[ 5766.899017] Serial : 0000000000000000
[ 5766.899017] SoC Information:
[ 5766.899017] CPU : OMAP4470
[ 5766.899017] Rev : ES1.0
[ 5766.899047] Type : HS
[ 5766.899047] Production ID: 0002B975-000000CC
[ 5766.899047] Die ID : 76080000-30002FFF-01518C70-0D00F007
[ 5766.899047]
[ 5766.935028] ---[ end trace 5f7d6da5db258915 ]---
[ 5766.948150] virtio_rpmsg_bus virtio1: destroying channel rpmsg-resmgr addr 0x66
[ 5767.098541] virtio_rpmsg_bus virtio1: creating channel rpmsg-resmgr addr 0x66
[ 5769.519683] ------------[ cut here ]------------
[ 5769.524749] WARNING: at arch/arm/mach-omap2/omap_l3_noc.c:97 l3_interrupt_handler+0xc0/0x170()
[ 5769.534149] L3 standard error: TARGET:ISS at address 0x10
[ 5769.540100] Modules linked in: wlcore_sdio(O) wl18xx(O) wl12xx(O) wlcore(O) mac80211(O) pvrsrvkm_sgx544_112(O) cfg80211(O) compat(O)
[ 5769.553802] Backtrace:
[ 5769.556610] [<c00180ec>] (dump_backtrace+0x0/0x10c) from [<c065d448>] (dump_stack+0x18/0x1c)
[ 5769.565734] r6:c003a19c r5:00000009 r4:ca453a68 r3:c0982f10
[ 5769.572296] [<c065d430>] (dump_stack+0x0/0x1c) from [<c0046cf4>] (warn_slowpath_common+0x54/0x6c)
[ 5769.581970] [<c0046ca0>] (warn_slowpath_common+0x0/0x6c) from [<c0046db0>] (warn_slowpath_fmt+0x38/0x40)
[ 5769.592285] r8:00000000 r7:00000018 r6:c06712c4 r5:80080001 r4:e08f4400
[ 5769.599700] r3:00000009
[ 5769.602783] [<c0046d78>] (warn_slowpath_fmt+0x0/0x40) from [<c003a19c>] (l3_interrupt_handler+0xc0/0x170)
[ 5769.613189] r3:c080790c r2:c0807858
[ 5769.617340] [<c003a0dc>] (l3_interrupt_handler+0x0/0x170) from [<c00a8bc0>] (handle_irq_event_percpu+0x64/0x2b0)
[ 5769.628356] r8:00000000 r7:0000002a r6:0000002a r5:c0924190 r4:d6cbeac0
[ 5769.636108] [<c00a8b5c>] (handle_irq_event_percpu+0x0/0x2b0) from [<c00a8e50>] (handle_irq_event+0x44/0x64)
[ 5769.646728] [<c00a8e0c>] (handle_irq_event+0x0/0x64) from [<c00abb80>] (handle_fasteoi_irq+0xa0/0x160)
[ 5769.656860] r6:ca452000 r5:c0924190 r4:c0924140 r3:00000000
[ 5769.663360] [<c00abae0>] (handle_fasteoi_irq+0x0/0x160) from [<c00a83ac>] (generic_handle_irq+0x30/0x44)
[ 5769.673675] r5:c091e538 r4:c0946d40
[ 5769.677764] [<c00a837c>] (generic_handle_irq+0x0/0x44) from [<c0014b88>] (handle_IRQ+0x54/0xb8)
[ 5769.687255] [<c0014b34>] (handle_IRQ+0x0/0xb8) from [<c00084d0>] (gic_handle_irq+0x2c/0x60)
[ 5769.696380] r8:d6cf3f40 r7:ca453bbc r6:ca453b88 r5:c0945a00 r4:e0802100
[ 5769.703857] r3:c0029070
[ 5769.706909] [<c00084a4>] (gic_handle_irq+0x0/0x60) from [<c06678c0>] (__irq_svc+0x40/0x70)
[ 5769.715881] Exception stack(0xca453b88 to 0xca453bd0)
[ 5769.721435] 3b80: c0964d98 a0000013 00000010 00000000 00000000 c0964d98
[ 5769.730377] 3ba0: a0000013 d6cf3f40 d6cf3f40 3b9aca00 00000000 ca453bdc ca453be0 ca453bd0
[ 5769.739227] 3bc0: c0029070 c0666d68 60000013 ffffffff
[ 5769.744781] r6:ffffffff r5:60000013 r4:c0666d68 r3:c0029070
[ 5769.751281] [<c0666d44>] (_raw_spin_unlock_irqrestore+0x0/0x50) from [<c0029070>] (omap_hwmod_reset+0x3c/0x4c)
[ 5769.762176] [<c0029034>] (omap_hwmod_reset+0x0/0x4c) from [<c0024d30>] (omap_cam_deactivate+0x30/0x48)
[ 5769.772308] r6:d6cf3fc0 r5:d6cf3fc0 r4:00000001 r3:d6cf3f80
[ 5769.778869] [<c0024d00>] (omap_cam_deactivate+0x0/0x48) from [<c0040bc4>] (_omap_device_deactivate+0xb4/0x14c)
[ 5769.789703] r5:d6cf1608 r4:d6cf3fc0
[ 5769.793853] [<c0040b10>] (_omap_device_deactivate+0x0/0x14c) from [<c0041434>] (omap_device_idle+0x30/0x5c)
[ 5769.804473] [<c0041404>] (omap_device_idle+0x0/0x5c) from [<c0041520>] (omap_device_runtime_suspend+0x24/0x2c)
[ 5769.815277] r4:00000000 r3:00000000
[ 5769.819396] [<c00414fc>] (omap_device_runtime_suspend+0x0/0x2c) from [<c02f1d5c>] (__rpm_callback+0x3c/0x78)
[ 5769.830078] r5:d6cf1668 r4:d6cf1608
[ 5769.834167] [<c02f1d20>] (__rpm_callback+0x0/0x78) from [<c02f2270>] (rpm_suspend+0x254/0x728)
[ 5769.843566] r6:00000000 r5:00000000 r4:d6cf1608 r3:c09827ec
[ 5769.850067] [<c02f201c>] (rpm_suspend+0x0/0x728) from [<c02f385c>] (__pm_runtime_suspend+0x60/0x84)
[ 5769.859924] [<c02f37fc>] (__pm_runtime_suspend+0x0/0x84) from [<c02eea28>] (pm_generic_runtime_idle+0x4c/0x58)
[ 5769.870819] r7:60000013 r6:c0040978 r5:d6cf1668 r4:d6cf1608
[ 5769.877319] [<c02ee9dc>] (pm_generic_runtime_idle+0x0/0x58) from [<c0040988>] (_od_runtime_idle+0x10/0x14)
[ 5769.887817] r4:d6cf1608 r3:00000000
[ 5769.891967] [<c0040978>] (_od_runtime_idle+0x0/0x14) from [<c02f1d5c>] (__rpm_callback+0x3c/0x78)
[ 5769.901580] [<c02f1d20>] (__rpm_callback+0x0/0x78) from [<c02f28c0>] (rpm_idle+0x100/0x290)
[ 5769.910675] r6:00000000 r5:00000004 r4:d6cf1608 r3:00000088
[ 5769.917236] [<c02f27c0>] (rpm_idle+0x0/0x290) from [<c02f2b2c>] (__pm_runtime_idle+0x60/0x84)
[ 5769.926452] r8:ce7b2c00 r7:60000013 r6:d6cf1668 r5:00000004 r4:d6cf1608
[ 5769.933959] r3:d6cf16ec
[ 5769.937042] [<c02f2acc>] (__pm_runtime_idle+0x0/0x84) from [<c0473100>] (_device_release+0x34/0x38)
[ 5769.946899] r7:cf2a3288 r6:ce7b2c08 r5:d6cf1608 r4:d5f9b440
[ 5769.953460] [<c04730cc>] (_device_release+0x0/0x38) from [<c0473b74>] (rprm_iss_release+0x10/0x38)
[ 5769.963165] r5:ce7b2c08 r4:cf2a32c0
[ 5769.967315] [<c0473b64>] (rprm_iss_release+0x0/0x38) from [<c0471f90>] (_resource_release+0x40/0xdc)
[ 5769.977172] r4:cf2a32c0 r3:c0473b64
[ 5769.981323] [<c0471f50>] (_resource_release+0x0/0xdc) from [<c04722f8>] (rprm_cb+0x270/0x680)
[ 5769.990631] r6:00000000 r5:ce7b2c08 r4:cf2a32a0 r3:00000000
[ 5769.997131] [<c0472088>] (rprm_cb+0x0/0x680) from [<c0470e50>] (rpmsg_recv_done+0x108/0x220)
[ 5770.006347] [<c0470d48>] (rpmsg_recv_done+0x0/0x220) from [<c02ab2f8>] (vring_interrupt+0x40/0x58)
[ 5770.016113] [<c02ab2b8>] (vring_interrupt+0x0/0x58) from [<c046f728>] (rproc_vq_interrupt+0x3c/0x50)
[ 5770.026000] [<c046f6ec>] (rproc_vq_interrupt+0x0/0x50) from [<c04707c4>] (_vq_interrupt_thread+0x1c/0x44)
[ 5770.036437] [<c04707a8>] (_vq_interrupt_thread+0x0/0x44) from [<c0066764>] (kthread+0x90/0x9c)
[ 5770.045806] r5:cf2e9cc0 r4:cf937e44
[ 5770.049896] [<c00666d4>] (kthread+0x0/0x9c) from [<c004ac04>] (do_exit+0x0/0x7b4)
[ 5770.058074] r6:c004ac04 r5:c00666d4 r4:cf937e44
[ 5770.063385] Board Information:
[ 5770.063385] Revision : 20edb4
[ 5770.063385] Serial : 0000000000000000
[ 5770.063385] SoC Information:
[ 5770.063385] CPU : OMAP4470
[ 5770.063385] Rev : ES1.0
[ 5770.063415] Type : HS
[ 5770.063415] Production ID: 0002B975-000000CC
[ 5770.063415] Die ID : 76080000-30002FFF-01518C70-0D00F007
[ 5770.063415]
[ 5770.098297] ---[ end trace 5f7d6da5db258916 ]---
[ 5770.110778] virtio_rpmsg_bus virtio1: destroying channel rpmsg-resmgr addr 0x66
[ 5770.266723] virtio_rpmsg_bus virtio1: creating channel rpmsg-resmgr addr 0x66
^ permalink raw reply
* How to support SDIO wifi/bt in DT
From: Mark Brown @ 2014-02-05 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140117104423.GR17530@lunn.ch>
On Fri, Jan 17, 2014 at 11:44:23AM +0100, Andrew Lunn wrote:
> I've not looked at regulators, but i would hope it also does reference
> counting of a regulators users.
Yes, it does.
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^ permalink raw reply
* [GIT PULL] clk: socfpga: Clock updates for v3.15
From: dinguyen at altera.com @ 2014-02-05 17:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mike,
Please consider pull these patch for v3.15.
Thanks,
Dinh
The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:
Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)
are available in the git repository at:
git://git.rocketboards.org/linux-socfpga-next.git tags/socfpga-clk-for-3.15
for you to fetch changes up to 5d81b6fc5ee1d904f9e3faab3a80cee36d267136:
clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk" (2014-02-05 11:05:09 -0600)
----------------------------------------------------------------
SOCFPGA clk updates for v3.15
----------------------------------------------------------------
Dinh Nguyen (4):
clk: socfpga: Map the clk manager base address in the clock driver
clk: socfpga: Look for the GPIO_DB_CLK by its offset
clk: socfpga: Remove socfpga_init_clocks
clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"
Steffen Trumtrar (3):
clk: socfpga: remove unused field
clk: socfpga: fix define typo
clk: socfpga: split clk code
.../devicetree/bindings/clock/altr_socfpga.txt | 5 +
arch/arm/boot/dts/socfpga.dtsi | 1 +
arch/arm/mach-socfpga/socfpga.c | 5 -
drivers/clk/socfpga/Makefile | 3 +
drivers/clk/socfpga/clk-gate.c | 263 ++++++++++++++++
drivers/clk/socfpga/clk-periph.c | 94 ++++++
drivers/clk/socfpga/clk-pll.c | 111 +++++++
drivers/clk/socfpga/clk.c | 326 +-------------------
drivers/clk/socfpga/clk.h | 57 ++++
9 files changed, 546 insertions(+), 319 deletions(-)
create mode 100644 drivers/clk/socfpga/clk-gate.c
create mode 100644 drivers/clk/socfpga/clk-periph.c
create mode 100644 drivers/clk/socfpga/clk-pll.c
create mode 100644 drivers/clk/socfpga/clk.h
^ permalink raw reply
* [PATCH v2 0/4] kernel mode NEON optimizations
From: Ard Biesheuvel @ 2014-02-05 17:13 UTC (permalink / raw)
To: linux-arm-kernel
The main purpose of this series is to allow Crypto Extensions instructions to be
used in interrupt context. For instance, the WPA2 CCMP handling (i.e., AES-128
in CCM mode) in the mac80211 layer runs entirely in softirq context.
Patch #1 does some preparatory work so all code external to kernel/fpsimd.c uses
accessor functions to manipulate both the on-CPU and preserved FPSIMD states
rather than poking them directly.
Patch #2 implements an optimization that reduces the number of times the
userland FPSIMD state is needlessly preserved and restored.
Patch #3 modifies kernel_neon_begin() and kernel_neon_end() so they may be
called from interrupt context.
Patch #4 contains the actual AES implementation, updated to reflect some recent
feedback I received when I posted it separately from this series.
Changes since previous version:
- added preparatory patch #1
- based on feedback from Will Deacon, make sure ptrace() and return from signal
handler cases are covered.
Mildly but not yet thoroughly tested.
All feedback highly appreciated.
Ard Biesheuvel (4):
arm64: add abstractions for FPSIMD state manipulation
arm64: defer reloading a task's FPSIMD state to userland resume
arm64: add support for kernel mode NEON in interrupt context
arm64: add Crypto Extensions based synchronous core AES cipher
arch/arm64/Makefile | 1 +
arch/arm64/crypto/Makefile | 13 +++
arch/arm64/crypto/aes-ce-cipher.c | 134 +++++++++++++++++++++++++++++
arch/arm64/include/asm/fpsimd.h | 30 ++++++-
arch/arm64/include/asm/fpsimdmacros.h | 37 ++++++++
arch/arm64/include/asm/neon.h | 6 +-
arch/arm64/include/asm/thread_info.h | 4 +-
arch/arm64/kernel/entry-fpsimd.S | 24 ++++++
arch/arm64/kernel/entry.S | 2 +-
arch/arm64/kernel/fpsimd.c | 156 +++++++++++++++++++++++++++++-----
arch/arm64/kernel/process.c | 2 +-
arch/arm64/kernel/ptrace.c | 22 +++--
arch/arm64/kernel/signal.c | 10 ++-
arch/arm64/kernel/signal32.c | 6 +-
crypto/Kconfig | 6 ++
15 files changed, 411 insertions(+), 42 deletions(-)
create mode 100644 arch/arm64/crypto/Makefile
create mode 100644 arch/arm64/crypto/aes-ce-cipher.c
--
1.8.3.2
^ permalink raw reply
* [PATCH v2 1/4] arm64: add abstractions for FPSIMD state manipulation
From: Ard Biesheuvel @ 2014-02-05 17:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391620418-3999-1-git-send-email-ard.biesheuvel@linaro.org>
This is a preparatory patch that replaces code that saves or restores the
on-CPU or preserved FPSIMD state directly with wrapper functions, resulting
in all direct manipulation of the FPSIMD state to be concentrated in fpsimd.c
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/include/asm/fpsimd.h | 9 ++++++---
arch/arm64/kernel/fpsimd.c | 31 +++++++++++++++++++++++++++++++
arch/arm64/kernel/process.c | 2 +-
arch/arm64/kernel/ptrace.c | 22 +++++++++++++---------
arch/arm64/kernel/signal.c | 6 +++---
arch/arm64/kernel/signal32.c | 6 +++---
6 files changed, 57 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
index c43b4ac13008..7807974b49ee 100644
--- a/arch/arm64/include/asm/fpsimd.h
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -52,12 +52,15 @@ struct fpsimd_state {
struct task_struct;
-extern void fpsimd_save_state(struct fpsimd_state *state);
-extern void fpsimd_load_state(struct fpsimd_state *state);
-
extern void fpsimd_thread_switch(struct task_struct *next);
extern void fpsimd_flush_thread(void);
+struct fpsimd_state *fpsimd_get_task_state(void);
+void fpsimd_set_task_state(struct fpsimd_state *state);
+
+struct user_fpsimd_state *fpsimd_get_user_state(struct task_struct *t);
+void fpsimd_set_user_state(struct task_struct *t, struct user_fpsimd_state *st);
+
#endif
#endif
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 4aef42a04bdc..eeb003f54ad0 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -34,6 +34,10 @@
#define FPEXC_IXF (1 << 4)
#define FPEXC_IDF (1 << 7)
+/* defined in entry-fpsimd.S but only used in this unit */
+void fpsimd_save_state(struct fpsimd_state *state);
+void fpsimd_load_state(struct fpsimd_state *state);
+
/*
* Trapped FP/ASIMD access.
*/
@@ -87,6 +91,33 @@ void fpsimd_flush_thread(void)
preempt_enable();
}
+/*
+ * Sync the saved FPSIMD context with the FPSIMD register file
+ */
+struct fpsimd_state *fpsimd_get_task_state(void)
+{
+ fpsimd_save_state(¤t->thread.fpsimd_state);
+ return ¤t->thread.fpsimd_state;
+}
+
+/*
+ * Load a new FPSIMD state into the FPSIMD register file.
+ */
+void fpsimd_set_task_state(struct fpsimd_state *state)
+{
+ fpsimd_load_state(state);
+}
+
+struct user_fpsimd_state *fpsimd_get_user_state(struct task_struct *t)
+{
+ return &t->thread.fpsimd_state.user_fpsimd;
+}
+
+void fpsimd_set_user_state(struct task_struct *t, struct user_fpsimd_state *st)
+{
+ t->thread.fpsimd_state.user_fpsimd = *st;
+}
+
#ifdef CONFIG_KERNEL_MODE_NEON
/*
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 1c0a9be2ffa8..bfa8214f92d1 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -199,7 +199,7 @@ void release_thread(struct task_struct *dead_task)
int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
- fpsimd_save_state(¤t->thread.fpsimd_state);
+ fpsimd_get_task_state();
*dst = *src;
return 0;
}
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 6a8928bba03c..d0b35af14539 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -500,8 +500,7 @@ static int fpr_get(struct task_struct *target, const struct user_regset *regset,
unsigned int pos, unsigned int count,
void *kbuf, void __user *ubuf)
{
- struct user_fpsimd_state *uregs;
- uregs = &target->thread.fpsimd_state.user_fpsimd;
+ struct user_fpsimd_state *uregs = fpsimd_get_user_state(target);
return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0, -1);
}
@@ -516,7 +515,7 @@ static int fpr_set(struct task_struct *target, const struct user_regset *regset,
if (ret)
return ret;
- target->thread.fpsimd_state.user_fpsimd = newstate;
+ fpsimd_set_user_state(target, &newstate);
return ret;
}
@@ -723,7 +722,7 @@ static int compat_vfp_get(struct task_struct *target,
compat_ulong_t fpscr;
int ret;
- uregs = &target->thread.fpsimd_state.user_fpsimd;
+ uregs = fpsimd_get_user_state(target);
/*
* The VFP registers are packed into the fpsimd_state, so they all sit
@@ -746,24 +745,29 @@ static int compat_vfp_set(struct task_struct *target,
unsigned int pos, unsigned int count,
const void *kbuf, const void __user *ubuf)
{
- struct user_fpsimd_state *uregs;
+ struct user_fpsimd_state newstate;
compat_ulong_t fpscr;
int ret;
if (pos + count > VFP_STATE_SIZE)
return -EIO;
- uregs = &target->thread.fpsimd_state.user_fpsimd;
+ /*
+ * We will not overwrite the entire FPSIMD state, so we need to
+ * initialize 'newstate' with sane values.
+ */
+ newstate = *fpsimd_get_user_state(target);
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
+ ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0,
VFP_STATE_SIZE - sizeof(compat_ulong_t));
if (count && !ret) {
ret = get_user(fpscr, (compat_ulong_t *)ubuf);
- uregs->fpsr = fpscr & VFP_FPSCR_STAT_MASK;
- uregs->fpcr = fpscr & VFP_FPSCR_CTRL_MASK;
+ newstate.fpsr = fpscr & VFP_FPSCR_STAT_MASK;
+ newstate.fpcr = fpscr & VFP_FPSCR_CTRL_MASK;
}
+ fpsimd_set_user_state(target, &newstate);
return ret;
}
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index 890a591f75dd..54e1092c5b4c 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -47,11 +47,11 @@ struct rt_sigframe {
static int preserve_fpsimd_context(struct fpsimd_context __user *ctx)
{
- struct fpsimd_state *fpsimd = ¤t->thread.fpsimd_state;
+ struct fpsimd_state *fpsimd;
int err;
/* dump the hardware registers to the fpsimd_state structure */
- fpsimd_save_state(fpsimd);
+ fpsimd = fpsimd_get_task_state();
/* copy the FP and status/control registers */
err = __copy_to_user(ctx->vregs, fpsimd->vregs, sizeof(fpsimd->vregs));
@@ -88,7 +88,7 @@ static int restore_fpsimd_context(struct fpsimd_context __user *ctx)
/* load the hardware registers from the fpsimd_state structure */
if (!err) {
preempt_disable();
- fpsimd_load_state(&fpsimd);
+ fpsimd_set_task_state(&fpsimd);
preempt_enable();
}
diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c
index b3fc9f5ec6d3..88e4535c3a45 100644
--- a/arch/arm64/kernel/signal32.c
+++ b/arch/arm64/kernel/signal32.c
@@ -208,7 +208,7 @@ int copy_siginfo_from_user32(siginfo_t *to, compat_siginfo_t __user *from)
*/
static int compat_preserve_vfp_context(struct compat_vfp_sigframe __user *frame)
{
- struct fpsimd_state *fpsimd = ¤t->thread.fpsimd_state;
+ struct fpsimd_state *fpsimd;
compat_ulong_t magic = VFP_MAGIC;
compat_ulong_t size = VFP_STORAGE_SIZE;
compat_ulong_t fpscr, fpexc;
@@ -219,7 +219,7 @@ static int compat_preserve_vfp_context(struct compat_vfp_sigframe __user *frame)
* Note that this also saves V16-31, which aren't visible
* in AArch32.
*/
- fpsimd_save_state(fpsimd);
+ fpsimd = fpsimd_get_task_state();
/* Place structure header on the stack */
__put_user_error(magic, &frame->magic, err);
@@ -284,7 +284,7 @@ static int compat_restore_vfp_context(struct compat_vfp_sigframe __user *frame)
*/
if (!err) {
preempt_disable();
- fpsimd_load_state(&fpsimd);
+ fpsimd_set_task_state(&fpsimd);
preempt_enable();
}
--
1.8.3.2
^ permalink raw reply related
* [PATCH v2 2/4] arm64: defer reloading a task's FPSIMD state to userland resume
From: Ard Biesheuvel @ 2014-02-05 17:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391620418-3999-1-git-send-email-ard.biesheuvel@linaro.org>
If a task gets scheduled out and back in again and nothing has touched
its FPSIMD state in the mean time, there is really no reason to reload
it from memory. Similarly, repeated calls to kernel_neon_begin() and
kernel_neon_end() will preserve and restore the FPSIMD state every time.
This patch defers the FPSIMD state restore to the last possible moment,
i.e., right before the task re-enters userland. If a task does not enter
userland at all (for any reason), the existing FPSIMD state is preserved
and may be reused by the owning task if it gets scheduled in again on the
same CPU.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/include/asm/fpsimd.h | 4 ++
arch/arm64/include/asm/thread_info.h | 4 +-
arch/arm64/kernel/entry.S | 2 +-
arch/arm64/kernel/fpsimd.c | 102 +++++++++++++++++++++++++++++------
arch/arm64/kernel/signal.c | 4 ++
5 files changed, 98 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
index 7807974b49ee..f7e70f3f1eb7 100644
--- a/arch/arm64/include/asm/fpsimd.h
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -37,6 +37,8 @@ struct fpsimd_state {
u32 fpcr;
};
};
+ /* the id of the last cpu to have restored this state */
+ unsigned int last_cpu;
};
#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
@@ -61,6 +63,8 @@ void fpsimd_set_task_state(struct fpsimd_state *state);
struct user_fpsimd_state *fpsimd_get_user_state(struct task_struct *t);
void fpsimd_set_user_state(struct task_struct *t, struct user_fpsimd_state *st);
+void fpsimd_reload_fpstate(void);
+
#endif
#endif
diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h
index 720e70b66ffd..4a1ca1cfb2f8 100644
--- a/arch/arm64/include/asm/thread_info.h
+++ b/arch/arm64/include/asm/thread_info.h
@@ -100,6 +100,7 @@ static inline struct thread_info *current_thread_info(void)
#define TIF_SIGPENDING 0
#define TIF_NEED_RESCHED 1
#define TIF_NOTIFY_RESUME 2 /* callback before returning to user */
+#define TIF_FOREIGN_FPSTATE 3 /* CPU's FP state is not current's */
#define TIF_SYSCALL_TRACE 8
#define TIF_POLLING_NRFLAG 16
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
@@ -112,10 +113,11 @@ static inline struct thread_info *current_thread_info(void)
#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
+#define _TIF_FOREIGN_FPSTATE (1 << TIF_FOREIGN_FPSTATE)
#define _TIF_32BIT (1 << TIF_32BIT)
#define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
- _TIF_NOTIFY_RESUME)
+ _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE)
#endif /* __KERNEL__ */
#endif /* __ASM_THREAD_INFO_H */
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 39ac630d83de..80464e2fb1a5 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -576,7 +576,7 @@ fast_work_pending:
str x0, [sp, #S_X0] // returned x0
work_pending:
tbnz x1, #TIF_NEED_RESCHED, work_resched
- /* TIF_SIGPENDING or TIF_NOTIFY_RESUME case */
+ /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */
ldr x2, [sp, #S_PSTATE]
mov x0, sp // 'regs'
tst x2, #PSR_MODE_MASK // user mode regs?
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index eeb003f54ad0..239c8162473f 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -39,6 +39,23 @@ void fpsimd_save_state(struct fpsimd_state *state);
void fpsimd_load_state(struct fpsimd_state *state);
/*
+ * In order to reduce the number of times the fpsimd state is needlessly saved
+ * and restored, keep track here of which task's userland owns the current state
+ * of the FPSIMD register file.
+ *
+ * This percpu variable points to the fpsimd_state.last_cpu field of the task
+ * whose FPSIMD state was most recently loaded onto this cpu. The last_cpu field
+ * itself contains the id of the cpu onto which the task's FPSIMD state was
+ * loaded most recently. So, to decide whether we can skip reloading the FPSIMD
+ * state, we need to check
+ * (a) whether this task was the last one to have its FPSIMD state loaded onto
+ * this cpu
+ * (b) whether this task may have manipulated its FPSIMD state on another cpu in
+ * the meantime
+ */
+static DEFINE_PER_CPU(unsigned int *, fpsimd_last_task);
+
+/*
* Trapped FP/ASIMD access.
*/
void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs)
@@ -76,36 +93,84 @@ void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs)
void fpsimd_thread_switch(struct task_struct *next)
{
- /* check if not kernel threads */
- if (current->mm)
+ /*
+ * The thread flag TIF_FOREIGN_FPSTATE conveys that the userland FPSIMD
+ * state belonging to the current task is not present in the registers
+ * but has (already) been saved to memory in order for the kernel to be
+ * able to go off and use the registers for something else. Therefore,
+ * we must not (re)save the register contents if this flag is set.
+ */
+ if (current->mm && !test_thread_flag(TIF_FOREIGN_FPSTATE))
fpsimd_save_state(¤t->thread.fpsimd_state);
- if (next->mm)
- fpsimd_load_state(&next->thread.fpsimd_state);
+
+ if (next->mm) {
+ /*
+ * If we are switching to a task whose most recent userland
+ * FPSIMD contents are already in the registers of *this* cpu,
+ * we can skip loading the state from memory. Otherwise, set
+ * the TIF_FOREIGN_FPSTATE flag so the state will be loaded
+ * upon the next entry of userland.
+ */
+ struct fpsimd_state *st = &next->thread.fpsimd_state;
+
+ if (__get_cpu_var(fpsimd_last_task) == &st->last_cpu
+ && st->last_cpu == smp_processor_id())
+ clear_ti_thread_flag(task_thread_info(next),
+ TIF_FOREIGN_FPSTATE);
+ else
+ set_ti_thread_flag(task_thread_info(next),
+ TIF_FOREIGN_FPSTATE);
+ }
}
void fpsimd_flush_thread(void)
{
- preempt_disable();
memset(¤t->thread.fpsimd_state, 0, sizeof(struct fpsimd_state));
- fpsimd_load_state(¤t->thread.fpsimd_state);
+ set_thread_flag(TIF_FOREIGN_FPSTATE);
+}
+
+/*
+ * Sync the FPSIMD register file with the saved FPSIMD context (if necessary)
+ */
+void fpsimd_reload_fpstate(void)
+{
+ preempt_disable();
+ if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
+ struct fpsimd_state *st = ¤t->thread.fpsimd_state;
+
+ fpsimd_load_state(st);
+ __get_cpu_var(fpsimd_last_task) = &st->last_cpu;
+ st->last_cpu = smp_processor_id();
+ }
preempt_enable();
}
/*
- * Sync the saved FPSIMD context with the FPSIMD register file
+ * Sync the saved FPSIMD context with the FPSIMD register file (if necessary)
*/
struct fpsimd_state *fpsimd_get_task_state(void)
{
- fpsimd_save_state(¤t->thread.fpsimd_state);
+ preempt_disable();
+ if (!test_thread_flag(TIF_FOREIGN_FPSTATE))
+ fpsimd_save_state(¤t->thread.fpsimd_state);
+ preempt_enable();
return ¤t->thread.fpsimd_state;
}
/*
- * Load a new FPSIMD state into the FPSIMD register file.
+ * Load a new FPSIMD state into the FPSIMD register file, and clear the
+ * TIF_FOREIGN_FPSTATE flag to convey that the register content is now
+ * owned by 'current'. To be called with preemption disabled.
*/
void fpsimd_set_task_state(struct fpsimd_state *state)
{
fpsimd_load_state(state);
+ if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
+ struct fpsimd_state *st = ¤t->thread.fpsimd_state;
+
+ __get_cpu_var(fpsimd_last_task) = &st->last_cpu;
+ st->last_cpu = smp_processor_id();
+ }
}
struct user_fpsimd_state *fpsimd_get_user_state(struct task_struct *t)
@@ -116,6 +181,9 @@ struct user_fpsimd_state *fpsimd_get_user_state(struct task_struct *t)
void fpsimd_set_user_state(struct task_struct *t, struct user_fpsimd_state *st)
{
t->thread.fpsimd_state.user_fpsimd = *st;
+
+ /* invalidate potential live copies of this FPSIMD state */
+ t->thread.fpsimd_state.last_cpu = NR_CPUS;
}
#ifdef CONFIG_KERNEL_MODE_NEON
@@ -129,16 +197,19 @@ void kernel_neon_begin(void)
BUG_ON(in_interrupt());
preempt_disable();
- if (current->mm)
+ /*
+ * Save the userland FPSIMD state if we have one and if we haven't done
+ * so already. Clear fpsimd_last_task to indicate that there is no
+ * longer userland context in the registers.
+ */
+ if (current->mm && !test_and_set_thread_flag(TIF_FOREIGN_FPSTATE))
fpsimd_save_state(¤t->thread.fpsimd_state);
+ __get_cpu_var(fpsimd_last_task) = NULL;
}
EXPORT_SYMBOL(kernel_neon_begin);
void kernel_neon_end(void)
{
- if (current->mm)
- fpsimd_load_state(¤t->thread.fpsimd_state);
-
preempt_enable();
}
EXPORT_SYMBOL(kernel_neon_end);
@@ -151,12 +222,11 @@ static int fpsimd_cpu_pm_notifier(struct notifier_block *self,
{
switch (cmd) {
case CPU_PM_ENTER:
- if (current->mm)
+ if (current->mm && !test_thread_flag(TIF_FOREIGN_FPSTATE))
fpsimd_save_state(¤t->thread.fpsimd_state);
break;
case CPU_PM_EXIT:
- if (current->mm)
- fpsimd_load_state(¤t->thread.fpsimd_state);
+ set_thread_flag(TIF_FOREIGN_FPSTATE);
break;
case CPU_PM_ENTER_FAILED:
default:
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index 54e1092c5b4c..68d2957e5ebe 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -416,4 +416,8 @@ asmlinkage void do_notify_resume(struct pt_regs *regs,
clear_thread_flag(TIF_NOTIFY_RESUME);
tracehook_notify_resume(regs);
}
+
+ if (thread_flags & _TIF_FOREIGN_FPSTATE)
+ fpsimd_reload_fpstate();
+
}
--
1.8.3.2
^ permalink raw reply related
* [PATCH v2 3/4] arm64: add support for kernel mode NEON in interrupt context
From: Ard Biesheuvel @ 2014-02-05 17:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391620418-3999-1-git-send-email-ard.biesheuvel@linaro.org>
This patch modifies kernel_neon_begin() and kernel_neon_end(), so
they may be called from any context. To address the case where only
a couple of registers are needed, kernel_neon_begin_partial(u32) is
introduced which takes as a parameter the number of bottom 'n' NEON
q-registers required. To mark the end of such a partial section, the
regular kernel_neon_end() should be used.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/include/asm/fpsimd.h | 17 ++++++++++++++
arch/arm64/include/asm/fpsimdmacros.h | 37 ++++++++++++++++++++++++++++++
arch/arm64/include/asm/neon.h | 6 ++++-
arch/arm64/kernel/entry-fpsimd.S | 24 +++++++++++++++++++
arch/arm64/kernel/fpsimd.c | 43 +++++++++++++++++++++++------------
5 files changed, 112 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
index f7e70f3f1eb7..8c0f8d332528 100644
--- a/arch/arm64/include/asm/fpsimd.h
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -41,6 +41,19 @@ struct fpsimd_state {
unsigned int last_cpu;
};
+/*
+ * Struct for stacking the bottom 'n' FP/SIMD registers.
+ * Mainly intended for kernel use of v8 Crypto Extensions which only
+ * needs a few registers and may need to execute in atomic context.
+ */
+struct fpsimd_partial_state {
+ u32 num_regs;
+ u32 fpsr;
+ u32 fpcr;
+ __uint128_t vregs[32] __aligned(16);
+} __aligned(16);
+
+
#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
/* Masks for extracting the FPSR and FPCR from the FPSCR */
#define VFP_FPSCR_STAT_MASK 0xf800009f
@@ -65,6 +78,10 @@ void fpsimd_set_user_state(struct task_struct *t, struct user_fpsimd_state *st);
void fpsimd_reload_fpstate(void);
+extern void fpsimd_save_partial_state(struct fpsimd_partial_state *state,
+ u32 num_regs);
+extern void fpsimd_load_partial_state(struct fpsimd_partial_state *state);
+
#endif
#endif
diff --git a/arch/arm64/include/asm/fpsimdmacros.h b/arch/arm64/include/asm/fpsimdmacros.h
index bbec599c96bd..42990a82c671 100644
--- a/arch/arm64/include/asm/fpsimdmacros.h
+++ b/arch/arm64/include/asm/fpsimdmacros.h
@@ -62,3 +62,40 @@
ldr w\tmpnr, [\state, #16 * 2 + 4]
msr fpcr, x\tmpnr
.endm
+
+.altmacro
+.macro q2op, op, q1, q2, state
+ \op q\q1, q\q2, [\state, # -16 * \q1 - 16]
+.endm
+
+.macro fpsimd_save_partial state, numnr, tmpnr1, tmpnr2
+ mrs x\tmpnr1, fpsr
+ str w\numnr, [\state]
+ mrs x\tmpnr2, fpcr
+ stp w\tmpnr1, w\tmpnr2, [\state, #4]
+ adr x\tmpnr1, 0f
+ add \state, \state, x\numnr, lsl #4
+ sub x\tmpnr1, x\tmpnr1, x\numnr, lsl #1
+ br x\tmpnr1
+ .irp qa, 30, 28, 26, 24, 22, 20, 18, 16, 14, 12, 10, 8, 6, 4, 2, 0
+ qb = \qa + 1
+ q2op stp, \qa, %qb, \state
+ .endr
+0:
+.endm
+
+.macro fpsimd_restore_partial state, tmpnr1, tmpnr2
+ ldp w\tmpnr1, w\tmpnr2, [\state, #4]
+ msr fpsr, x\tmpnr1
+ msr fpcr, x\tmpnr2
+ adr x\tmpnr1, 0f
+ ldr w\tmpnr2, [\state]
+ add \state, \state, x\tmpnr2, lsl #4
+ sub x\tmpnr1, x\tmpnr1, x\tmpnr2, lsl #1
+ br x\tmpnr1
+ .irp qa, 30, 28, 26, 24, 22, 20, 18, 16, 14, 12, 10, 8, 6, 4, 2, 0
+ qb = \qa + 1
+ q2op ldp, \qa, %qb, \state
+ .endr
+0:
+.endm
diff --git a/arch/arm64/include/asm/neon.h b/arch/arm64/include/asm/neon.h
index b0cc58a97780..13ce4cc18e26 100644
--- a/arch/arm64/include/asm/neon.h
+++ b/arch/arm64/include/asm/neon.h
@@ -8,7 +8,11 @@
* published by the Free Software Foundation.
*/
+#include <linux/types.h>
+
#define cpu_has_neon() (1)
-void kernel_neon_begin(void);
+#define kernel_neon_begin() kernel_neon_begin_partial(32)
+
+void kernel_neon_begin_partial(u32 num_regs);
void kernel_neon_end(void);
diff --git a/arch/arm64/kernel/entry-fpsimd.S b/arch/arm64/kernel/entry-fpsimd.S
index 6a27cd6dbfa6..d358ccacfc00 100644
--- a/arch/arm64/kernel/entry-fpsimd.S
+++ b/arch/arm64/kernel/entry-fpsimd.S
@@ -41,3 +41,27 @@ ENTRY(fpsimd_load_state)
fpsimd_restore x0, 8
ret
ENDPROC(fpsimd_load_state)
+
+#ifdef CONFIG_KERNEL_MODE_NEON
+
+/*
+ * Save the bottom n FP registers.
+ *
+ * x0 - pointer to struct fpsimd_partial_state
+ */
+ENTRY(fpsimd_save_partial_state)
+ fpsimd_save_partial x0, 1, 8, 9
+ ret
+ENDPROC(fpsimd_load_partial_state)
+
+/*
+ * Load the bottom n FP registers.
+ *
+ * x0 - pointer to struct fpsimd_partial_state
+ */
+ENTRY(fpsimd_load_partial_state)
+ fpsimd_restore_partial x0, 8, 9
+ ret
+ENDPROC(fpsimd_load_partial_state)
+
+#endif
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 239c8162473f..2ed92976ac16 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -188,29 +188,44 @@ void fpsimd_set_user_state(struct task_struct *t, struct user_fpsimd_state *st)
#ifdef CONFIG_KERNEL_MODE_NEON
+static DEFINE_PER_CPU(struct fpsimd_partial_state, hardirq_fpsimdstate);
+static DEFINE_PER_CPU(struct fpsimd_partial_state, softirq_fpsimdstate);
+
/*
* Kernel-side NEON support functions
*/
-void kernel_neon_begin(void)
+void kernel_neon_begin_partial(u32 num_regs)
{
- /* Avoid using the NEON in interrupt context */
- BUG_ON(in_interrupt());
- preempt_disable();
+ if (in_interrupt()) {
+ struct fpsimd_partial_state *s = this_cpu_ptr(
+ in_irq() ? &hardirq_fpsimdstate : &softirq_fpsimdstate);
- /*
- * Save the userland FPSIMD state if we have one and if we haven't done
- * so already. Clear fpsimd_last_task to indicate that there is no
- * longer userland context in the registers.
- */
- if (current->mm && !test_and_set_thread_flag(TIF_FOREIGN_FPSTATE))
- fpsimd_save_state(¤t->thread.fpsimd_state);
- __get_cpu_var(fpsimd_last_task) = NULL;
+ BUG_ON(num_regs > 32);
+ fpsimd_save_partial_state(s, roundup(num_regs, 2));
+ } else {
+ /*
+ * Save the userland FPSIMD state if we have one and if we
+ * haven't done so already. Clear fpsimd_last_task to indicate
+ * that there is no longer userland context in the registers.
+ */
+ preempt_disable();
+ if (current->mm &&
+ !test_and_set_thread_flag(TIF_FOREIGN_FPSTATE))
+ fpsimd_save_state(¤t->thread.fpsimd_state);
+ __get_cpu_var(fpsimd_last_task) = NULL;
+ }
}
-EXPORT_SYMBOL(kernel_neon_begin);
+EXPORT_SYMBOL(kernel_neon_begin_partial);
void kernel_neon_end(void)
{
- preempt_enable();
+ if (in_interrupt()) {
+ struct fpsimd_partial_state *s = this_cpu_ptr(
+ in_irq() ? &hardirq_fpsimdstate : &softirq_fpsimdstate);
+ fpsimd_load_partial_state(s);
+ } else {
+ preempt_enable();
+ }
}
EXPORT_SYMBOL(kernel_neon_end);
--
1.8.3.2
^ permalink raw reply related
* [PATCH v2 4/4] arm64: add Crypto Extensions based synchronous core AES cipher
From: Ard Biesheuvel @ 2014-02-05 17:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391620418-3999-1-git-send-email-ard.biesheuvel@linaro.org>
This implements the core AES cipher using the Crypto Extensions,
using only NEON registers q0 - q3.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/Makefile | 1 +
arch/arm64/crypto/Makefile | 13 ++++
arch/arm64/crypto/aes-ce-cipher.c | 134 ++++++++++++++++++++++++++++++++++++++
crypto/Kconfig | 6 ++
4 files changed, 154 insertions(+)
create mode 100644 arch/arm64/crypto/Makefile
create mode 100644 arch/arm64/crypto/aes-ce-cipher.c
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 2fceb71ac3b7..8185a913c5ed 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -45,6 +45,7 @@ export TEXT_OFFSET GZFLAGS
core-y += arch/arm64/kernel/ arch/arm64/mm/
core-$(CONFIG_KVM) += arch/arm64/kvm/
core-$(CONFIG_XEN) += arch/arm64/xen/
+core-$(CONFIG_CRYPTO) += arch/arm64/crypto/
libs-y := arch/arm64/lib/ $(libs-y)
libs-y += $(LIBGCC)
diff --git a/arch/arm64/crypto/Makefile b/arch/arm64/crypto/Makefile
new file mode 100644
index 000000000000..ac58945c50b3
--- /dev/null
+++ b/arch/arm64/crypto/Makefile
@@ -0,0 +1,13 @@
+#
+# linux/arch/arm64/crypto/Makefile
+#
+# Copyright (C) 2013 Linaro Ltd <ard.biesheuvel@linaro.org>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation.
+#
+
+obj-$(CONFIG_CRYPTO_AES_ARM64_CE) += aes-ce-cipher.o
+
+CFLAGS_aes-ce-cipher.o += -march=armv8-a+crypto
diff --git a/arch/arm64/crypto/aes-ce-cipher.c b/arch/arm64/crypto/aes-ce-cipher.c
new file mode 100644
index 000000000000..6dd64106923f
--- /dev/null
+++ b/arch/arm64/crypto/aes-ce-cipher.c
@@ -0,0 +1,134 @@
+/*
+ * linux/arch/arm64/crypto/aes-ce-cipher.c
+ *
+ * Copyright (C) 2013 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/hwcap.h>
+#include <asm/neon.h>
+#include <crypto/aes.h>
+#include <linux/crypto.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+
+MODULE_DESCRIPTION("Synchronous AES cipher using ARMv8 Crypto Extensions");
+MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
+MODULE_LICENSE("GPL");
+
+static int num_rounds(struct crypto_aes_ctx *ctx)
+{
+ /*
+ * # of rounds specified by AES:
+ * 128 bit key 10 rounds
+ * 192 bit key 12 rounds
+ * 256 bit key 14 rounds
+ * => n byte key => 6 + (n/4) rounds
+ */
+ return 6 + ctx->key_length / 4;
+}
+
+static void aes_cipher_encrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[])
+{
+ struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+
+ kernel_neon_begin_partial(4);
+
+ __asm__(" ld1 {v0.16b}, [%[in]] ;"
+ " cmp %[rounds], #10 ;"
+ " bmi 0f ;"
+ " bne 3f ;"
+ " ld1 {v3.2d}, [%[key]], #16 ;"
+ " b 2f ;"
+ "0: ld1 {v2.2d-v3.2d}, [%[key]], #32 ;"
+ "1: aese v0.16b, v2.16b ;"
+ " aesmc v0.16b, v0.16b ;"
+ "2: aese v0.16b, v3.16b ;"
+ " aesmc v0.16b, v0.16b ;"
+ "3: ld1 {v1.2d-v3.2d}, [%[key]], #48 ;"
+ " subs %[rounds], %[rounds], #3 ;"
+ " aese v0.16b, v1.16b ;"
+ " aesmc v0.16b, v0.16b ;"
+ " bpl 1b ;"
+ " aese v0.16b, v2.16b ;"
+ " eor v0.16b, v0.16b, v3.16b ;"
+ " st1 {v0.16b}, [%[out]] ;"
+ : :
+ [out] "r"(dst),
+ [in] "r"(src),
+ [rounds] "r"(num_rounds(ctx) - 2),
+ [key] "r"(ctx->key_enc)
+ : "cc", "memory");
+
+ kernel_neon_end();
+}
+
+static void aes_cipher_decrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[])
+{
+ struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+
+ kernel_neon_begin_partial(4);
+
+ __asm__(" ld1 {v0.16b}, [%[in]] ;"
+ " cmp %[rounds], #10 ;"
+ " bmi 0f ;"
+ " bne 3f ;"
+ " ld1 {v3.2d}, [%[key]], #16 ;"
+ " b 2f ;"
+ "0: ld1 {v2.2d-v3.2d}, [%[key]], #32 ;"
+ "1: aesd v0.16b, v2.16b ;"
+ " aesimc v0.16b, v0.16b ;"
+ "2: aesd v0.16b, v3.16b ;"
+ " aesimc v0.16b, v0.16b ;"
+ "3: ld1 {v1.2d-v3.2d}, [%[key]], #48 ;"
+ " subs %[rounds], %[rounds], #3 ;"
+ " aesd v0.16b, v1.16b ;"
+ " aesimc v0.16b, v0.16b ;"
+ " bpl 1b ;"
+ " aesd v0.16b, v2.16b ;"
+ " eor v0.16b, v0.16b, v3.16b ;"
+ " st1 {v0.16b}, [%[out]] ;"
+ : :
+ [out] "r"(dst),
+ [in] "r"(src),
+ [rounds] "r"(num_rounds(ctx) - 2),
+ [key] "r"(ctx->key_dec)
+ : "cc", "memory");
+
+ kernel_neon_end();
+}
+
+static struct crypto_alg aes_alg = {
+ .cra_name = "aes",
+ .cra_driver_name = "aes-ce",
+ .cra_priority = 300,
+ .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct crypto_aes_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_cipher = {
+ .cia_min_keysize = AES_MIN_KEY_SIZE,
+ .cia_max_keysize = AES_MAX_KEY_SIZE,
+ .cia_setkey = crypto_aes_set_key,
+ .cia_encrypt = aes_cipher_encrypt,
+ .cia_decrypt = aes_cipher_decrypt
+ }
+};
+
+static int __init aes_mod_init(void)
+{
+ if (!(elf_hwcap & HWCAP_AES))
+ return -ENODEV;
+ return crypto_register_alg(&aes_alg);
+}
+
+static void __exit aes_mod_exit(void)
+{
+ crypto_unregister_alg(&aes_alg);
+}
+
+module_init(aes_mod_init);
+module_exit(aes_mod_exit);
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 7bcb70d216e1..f1d98bc346b6 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -791,6 +791,12 @@ config CRYPTO_AES_ARM_BS
This implementation does not rely on any lookup tables so it is
believed to be invulnerable to cache timing attacks.
+config CRYPTO_AES_ARM64_CE
+ tristate "Synchronous AES cipher using ARMv8 Crypto Extensions"
+ depends on ARM64 && KERNEL_MODE_NEON
+ select CRYPTO_ALGAPI
+ select CRYPTO_AES
+
config CRYPTO_ANUBIS
tristate "Anubis cipher algorithm"
select CRYPTO_ALGAPI
--
1.8.3.2
^ permalink raw reply related
* [PATCH 2/2] ARM: tegra: paz00: Add LVDS support to device tree
From: Stephen Warren @ 2014-02-05 17:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <bcf12ecec69ef4e38e74a9be9c45e8bd2bd9ffcc.1387656959.git.marvin24@gmx.de>
On 12/21/2013 01:38 PM, Marc Dietrich wrote:
> Add backlight and panel nodes for the PAZ00 TFT LCD panel.
Applied to Tegra's for-3.15/dt branch.
^ permalink raw reply
* [PATCH] ARM: tegra: Properly sort clocks property
From: Stephen Warren @ 2014-02-05 17:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389021642-5516-1-git-send-email-treding@nvidia.com>
On 01/06/2014 08:20 AM, Thierry Reding wrote:
> Other files and nodes list the resets property after the clocks property
> so do the same here for consistency.
Applied to Tegra's for-3.15/dt branch.
^ permalink raw reply
* [PATCH] ARM: tegra: document which Dalmore revisions are supported
From: Stephen Warren @ 2014-02-05 17:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389035749-15261-1-git-send-email-swarren@wwwdotorg.org>
On 01/06/2014 12:15 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> There are a number of revisions of the Dalmore board, each with a variety
> of incompatible SW-visible HW changes. The Dalmore DT file in the kernel
> only supports HW revision A04. Document this in the DT file.
Applied to Tegra's for-3.15/dt branch.
^ permalink raw reply
* [PATCH v3 0/7] ARM: sunxi: Add driver for SD/MMC hosts found on allwinner sunxi SOCs
From: David Lanzendörfer @ 2014-02-05 17:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205134741.3027.50207.stgit@dizzy-6.o2s.ch>
As Maxime has pointed out, I've forgotten to add a changelog
in my coverletter.
Here is, what has changed in this revision:
Changes since v1:
-Using mmc_of_parse instead of diy dt parsing
-Adding nodes for all mmc controller to the dtsi files, including sofar unused
controllers
-Using generic GPIO slot library
-Adding additional MMC device nodes into DTSI files
Changes since v2:
-Add missing Signed-off-by tags
-Stop using __raw_readl / __raw_writel so that barriers are properly used
-Adding missing new lines
-Adding missing patch for automatic reparenting of clocks
cheers
david
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^ permalink raw reply
* [PATCH] ARM: tegra: add system-power-controller property for PMIC node
From: Stephen Warren @ 2014-02-05 17:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389265308-26405-1-git-send-email-ldewangan@nvidia.com>
On 01/09/2014 04:01 AM, Laxman Dewangan wrote:
> Add system-power-controller property to system PMIC, ams AS3722,
> node to enable power off functionality through PMIC.
Applied to Tegra's for-3.15/dt branch.
^ permalink raw reply
* [PATCH] ARM: config: enable ams AS3722 power reset driver
From: Stephen Warren @ 2014-02-05 17:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389084000-17033-1-git-send-email-ldewangan@nvidia.com>
On 01/07/2014 01:39 AM, Laxman Dewangan wrote:
> ams AS3722 is used as system PMIC for Tegra124 based Venice2.
> Enable ams AS3722 power reset driver for enabling power off
> system using PMIC.
Applied to Tegra's for-3.15/defconfig branch.
^ permalink raw reply
* [PATCH] mvebu : pcie: dt: potential issue in range parsing
From: Jason Cooper @ 2014-02-05 17:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205164710.082f689e@skate>
+ Bjorn, linux-pci
Bjorn,
It looks like this didn't get Cc'd to linux-pci. Here's a link:
http://www.spinics.net/lists/arm-kernel/msg299721.html
On Wed, Feb 05, 2014 at 04:47:10PM +0100, Thomas Petazzoni wrote:
> Dear Jean-Jacques Hiblot,
>
> On Fri, 10 Jan 2014 11:23:51 +0100, Jean-Jacques Hiblot wrote:
> > The second parameter of of_read_number is not the index, but a size.
> > As it happens, in this case it may work just fine because of the the conversion
> > to u32 and the favorable endianness on this architecture.
> >
> > Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
> > ---
> > drivers/pci/host/pci-mvebu.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
> > index c269e43..877e8ce 100644
> > --- a/drivers/pci/host/pci-mvebu.c
> > +++ b/drivers/pci/host/pci-mvebu.c
> > @@ -768,7 +768,7 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
> >
> > for (i = 0; i < nranges; i++) {
> > u32 flags = of_read_number(range, 1);
> > - u32 slot = of_read_number(range, 2);
> > + u32 slot = of_read_number(range + 1, 1);
> > u64 cpuaddr = of_read_number(range + na, pna);
> > unsigned long rtype;
> >
>
> Sorry for the long delay, and thanks for the fix!
>
> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>
> (on Armada 370, with PCIe cards plugged in)
Fixes: 11be65472a427 ("PCI: mvebu: Adapt to the new device tree layout")
Cc: <stable@vger.kernel.org> # v3.12+
Acked-by: Jason Cooper <jason@lakedaemon.net>
thx,
Jason.
^ permalink raw reply
* [GIT PULL] SOCFPGA DT updates for 3.15
From: dinguyen at altera.com @ 2014-02-05 17:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Kevin, and Olof,
Please consider pulling in these 2 patches for the enabling SD/MMC on the SOCFPGA
platform.
Thanks,
Dinh
The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:
Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)
are available in the git repository at:
git://git.rocketboards.org/linux-socfpga-next.git tags/socfpga-dts-for-3.15
for you to fetch changes up to e422c12bc07192289c3fec4edd457e6ffaa03b2b:
ARM: socfpga_defconfig: enable SD/MMC support (2014-02-05 11:19:34 -0600)
----------------------------------------------------------------
SOCFPGA dts updates for v3.15
----------------------------------------------------------------
Dinh Nguyen (2):
dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
ARM: socfpga_defconfig: enable SD/MMC support
arch/arm/boot/dts/socfpga.dtsi | 13 ++++++++++++-
arch/arm/boot/dts/socfpga_arria5.dtsi | 11 +++++++++++
arch/arm/boot/dts/socfpga_cyclone5.dtsi | 11 +++++++++++
arch/arm/boot/dts/socfpga_vt.dts | 11 +++++++++++
arch/arm/configs/socfpga_defconfig | 2 ++
5 files changed, 47 insertions(+), 1 deletion(-)
^ permalink raw reply
* [PATCH 05/22] Add shared printk wrapper for consistent prefixing
From: Joe Perches @ 2014-02-05 17:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391619853-10601-6-git-send-email-leif.lindholm@linaro.org>
On Wed, 2014-02-05 at 17:03 +0000, Leif Lindholm wrote:
> From: Roy Franz <roy.franz@linaro.org>
>
> Add a wrapper for printk to standardize the prefix for informational and
> error messages from the EFI stub.
trivia:
> diff --git a/drivers/firmware/efi/efi-stub-helper.c b/drivers/firmware/efi/efi-stub-helper.c
[]
> @@ -45,6 +45,9 @@ static void efi_printk(efi_system_table_t *sys_table_arg, char *str)
> }
> }
>
> +#define pr_efi(sys_table, msg) efi_printk(sys_table, "EFI stub: "msg)
> +#define pr_efi_err(sys_table, msg) efi_printk(sys_table, "EFI stub: ERROR: "msg)
Perhaps it'd be better to use a space after the second "
Also, maybe pr_efi should be pr_efi_info.
That would quiet any checkpatch noise around long msg uses.
^ permalink raw reply
* [PATCH] ARM: OMAP4: hwmod: Fix SOFTRESET logic for OMAP4
From: Nishanth Menon @ 2014-02-05 17:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F26F53.20408@ti.com>
2014-02-05 Grygorii Strashko <grygorii.strashko@ti.com>:
> Hi All,
> On 02/05/2014 05:06 PM, Illia Smyrnov wrote:
>> Commit 313a76e (ARM: OMAP2+: hwmod: Fix SOFTRESET logic) introduced
>> softreset bit cleaning right after set one. It is caused L3 error for
>> OMAP4 ISS because ISS register write occurs when ISS reset process is in
>> progress. Avoid this situation by cleaning softreset bit later, when reset
>> process is successfully finished.
>
> I'd like to mention that this issue has been caught while upgrading
> custom Linux Kernel 3.4 to the last Stable Kernel linux-3.4.y.
> So, the same OMAP4+ functionality can be broken in all Stable trees
> where commit "ARM: OMAP2+: hwmod: Fix SOFTRESET logic" was merged to.
>
> On OMAP4+ we should always try to wait until IP reset is finished before proceed.
>
> Reviewed-by: "Grygorii Strashko <grygorii.strashko@ti.com>"
>
> Error log example (k3.4):
>
Thanks - I for a moment thought it was on newer kernels :).
Looping in Dan who is currently looking at reset driver replacement
for existing hwmod based reset solution.
Regards,
Nishanth Menon
^ permalink raw reply
* [PATCH v5 2/3] clocksource: keystone: add bindings for keystone timer
From: Rob Herring @ 2014-02-05 17:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F26444.5090707@ti.com>
On Wed, Feb 5, 2014 at 10:18 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> wrote:
>
> On 02/05/2014 04:39 PM, Rob Herring wrote:
>>
>> On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
>> wrote:
>>>
>>> This patch provides bindings for the 64-bit timer in the KeyStone
>>> architecture devices. The timer can be configured as a general-purpose
>>> 64-bit
>>> timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
>>> timers, each half can operate in conjunction (chain mode) or
>>> independently
>>> (unchained mode) of each other.
>>
>> This is software configurable or h/w design time configurations?
>>
>> Rob
>>
>
> This is h/w design time configurations
Then it seems like the binding should provide for describing those
differences either with a property or different compatible strings.
Rob
^ permalink raw reply
* [PATCH 0/4] clk: mvebu: fix clk init order
From: Jason Cooper @ 2014-02-05 17:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205140802.9977.19747@quantum>
On Wed, Feb 05, 2014 at 06:08:02AM -0800, Mike Turquette wrote:
> Quoting Sebastian Hesselbarth (2014-01-25 10:19:06)
> > This patch set fixes clk init order that went upside-down with
> > v3.14. I haven't really investigated what caused this, but I assume
> > it is related with DT node reordering by addresses.
> >
> > Anyway, with v3.14 for MVEBU SoCs, the clock gating driver gets
> > registered before core clocks driver. Unfortunately, we cannot
> > return -EPROBE_DEFER in drivers initialized by clk_of_init. As the
> > init order for our drivers is always core clocks before clock gating,
> > we maintain init order ourselves by hooking CLK_OF_DECLARE to one
> > init function that will register core clocks before clock gating
> > driver.
> >
> > This patch is based on pre-v3.14-rc1 mainline and should go in as
> > fixes for it. As we now send MVEBU clk pull-requests to Mike directly,
> > I suggest Jason picks it up as a topic branch.
>
> Sebastian,
>
> These patches look OK to me. I'd rather take Gregory Clement's "respect
> the clock dependencies in of_clk_init" patch towards 3.15, so this fix
> will still be necessary for the current -rc's.
>
> Jason, will you be sending a PR?
Ahh, just saw this now. ignore my previous comments about using
Gregory's series as the fix.
Sure, I'll put this together for a pr to the clk tree.
thx,
Jason.
> > The patches have been boot tested on Dove and compile-tested only
> > for Kirkwood, Armada 370 and XP.
> >
> > Sebastian Hesselbarth (4):
> > clk: mvebu: armada-370: maintain clock init order
> > clk: mvebu: armada-xp: maintain clock init order
> > clk: mvebu: dove: maintain clock init order
> > clk: mvebu: kirkwood: maintain clock init order
> >
> > drivers/clk/mvebu/armada-370.c | 21 ++++++++++-----------
> > drivers/clk/mvebu/armada-xp.c | 20 +++++++++-----------
> > drivers/clk/mvebu/dove.c | 19 +++++++++----------
> > drivers/clk/mvebu/kirkwood.c | 34 ++++++++++++++++------------------
> > 4 files changed, 44 insertions(+), 50 deletions(-)
> >
> > ---
> > Cc: Mike Turquette <mturquette@linaro.org>
> > Cc: Jason Cooper <jason@lakedaemon.net>
> > Cc: Andrew Lunn <andrew@lunn.ch>
> > Cc: Gregory Clement <gregory.clement@free-electrons.com>
> > Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> > Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: linux-kernel at vger.kernel.org
> > --
> > 1.8.5.2
> >
^ permalink raw reply
* [PATCH] regulator: core: Make regulator object reflect configured voltage
From: Bjorn Andersson @ 2014-02-05 18:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140204200018.GZ22609@sirena.org.uk>
On Tue, Feb 4, 2014 at 12:00 PM, Mark Brown <broonie@kernel.org> wrote:
> On Tue, Feb 04, 2014 at 11:09:03AM -0800, Bjorn Andersson wrote:
>
>> I have a regulator that's being configured from DT as:
>> regulator-min-microvolt = <2950000>;
>> regulator-max-microvolt = <2950000>;
>
>> In the consumer I do regulator_set_voltage(2.95V).
>
>> As min == max the voltage is applied by the regulator framework on registration
>> of the regulator; and the regulator_set_voltage() fails as
>> REGULATOR_CHANGE_VOLTAGE is not set for this regulator.
>
> So we should be changing the code to allow a set_voltage() that sets the
> voltage to the existing voltage regardless of constraints allowing a
> change then - that's what the underlying issue is. Your change wouldn't
> cover the case where the hardware defualt is being used for example.
Makes sense, but the only thing we could check for would be if min_uV
== max_uV == current-voltage. That would work out fine for this use
case, but do you think it would be good enough?
The best thing I've come up with then is to add the following check in
regulator_set_voltage().
if (min_uV == max_uV && _regulator_get_voltage(rdev) == min_uV)
goto out;
Would this be acceptable? It's achieving the same thing as my patch,
is more robust and covers the case of setting the voltage to the hw
default value.
Regards,
Bjorn
^ permalink raw reply
* [PATCH 02/22] arm: add new asm macro update_sctlr
From: Will Deacon @ 2014-02-05 18:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391619853-10601-3-git-send-email-leif.lindholm@linaro.org>
On Wed, Feb 05, 2014 at 05:03:53PM +0000, Leif Lindholm wrote:
> A new macro for setting/clearing bits in the SCTLR.
>
> Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
> Suggested-by: Will Deacon <will.deacon@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> ---
> arch/arm/include/asm/assembler.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
Acked-by: Will Deacon <will.deacon@arm.com>
(although really minor comment below)
> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
> index 5c22851..e8ca24b 100644
> --- a/arch/arm/include/asm/assembler.h
> +++ b/arch/arm/include/asm/assembler.h
> @@ -383,4 +383,18 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
> #endif
> .endm
>
> +#ifdef CONFIG_CPU_CP15
> +/* Macro for setting/clearing bits in sctlr */
> + .macro update_sctlr, tmp:req, set=, clear=
> + mrc p15, 0, \tmp, c1, c0, 0
> + .ifnc \set,
> + orr \tmp, \set
I'd prefer the 3-arg form here for consistency (with this macro and the
rest of the file).
Will
^ permalink raw reply
* [alsa-devel] [PATCH v3 4/5] ASoC: tda998x: adjust the audio hw parameters from EDID
From: Jean-Francois Moine @ 2014-02-05 18:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F2021A.9020804@metafoo.de>
On Wed, 05 Feb 2014 10:19:22 +0100
Lars-Peter Clausen <lars@metafoo.de> wrote:
> > So, in the CODEC, I don't see how I could update the parameters
> > dictated by the EDID otherwise in changing the DAI driver parameters.
> >
>
> The startup function is the right place. But instead of modifying the DAI
> use snd_pcm_hw_constraint_mask64(), snd_pcm_hw_constraint_list(), etc. to
> setup the additional constraints that come from the EDID.
It is more complicated, but it works. Nevertheless, I have 2 problems:
- snd_pcm_hw_constraint_list() keeps a pointer to the list, so, it
cannot be in the stack. It fix this with static struct and rate array.
- snd_pcm_hw_constraint_mask64() is not exported.
Is there an other way to set constraints on the formats/sample widths?
--
Ken ar c'henta? | ** Breizh ha Linux atav! **
Jef | http://moinejf.free.fr/
^ permalink raw reply
* [PATCH 21/22] arm: efistub: ignore dtb= when UEFI SecureBoot is enabled
From: Ard Biesheuvel @ 2014-02-05 18:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391619853-10601-22-git-send-email-leif.lindholm@linaro.org>
On 5 February 2014 18:04, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> Loading unauthenticated FDT blobs directly from storage is a security hazard,
> so this should only be allowed when running with UEFI Secure Boot disabled.
>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> drivers/firmware/efi/arm-stub.c | 4 +++-
> drivers/firmware/efi/efi-stub-helper.c | 24 ++++++++++++++++++++++++
> 2 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/firmware/efi/arm-stub.c b/drivers/firmware/efi/arm-stub.c
> index b505fde..c651082 100644
> --- a/drivers/firmware/efi/arm-stub.c
> +++ b/drivers/firmware/efi/arm-stub.c
> @@ -95,7 +95,9 @@ unsigned long efi_entry(void *handle, efi_system_table_t *sys_table,
>
> /* Load a device tree from the configuration table, if present. */
> fdt_addr = (uintptr_t)get_fdt(sys_table);
> - if (!fdt_addr) {
> + if (efi_secureboot_enabled(sys_table))
> + pr_efi(sys_table, "UEFI Secure Boot is enabled, ignoring dtb= commandline option.\n");
I am pretty sure my original patch had braces on both branches of the if () :-)
Also, I think the precedence is backward here: dtb= should trump
config table, not the other way around.
--
Ard.
> + else if (!fdt_addr) {
> status = handle_cmdline_files(sys_table, image, cmdline_ptr,
> "dtb=",
> ~0UL, (unsigned long *)&fdt_addr,
> diff --git a/drivers/firmware/efi/efi-stub-helper.c b/drivers/firmware/efi/efi-stub-helper.c
> index 2ee69ea..6221be7 100644
> --- a/drivers/firmware/efi/efi-stub-helper.c
> +++ b/drivers/firmware/efi/efi-stub-helper.c
> @@ -721,3 +721,27 @@ static char *efi_convert_cmdline(efi_system_table_t *sys_table_arg,
> *cmd_line_len = options_bytes;
> return (char *)cmdline_addr;
> }
> +
> +static int __init efi_secureboot_enabled(efi_system_table_t *sys_table_arg)
> +{
> + static efi_guid_t const var_guid __initconst = EFI_GLOBAL_VARIABLE_GUID;
> + static efi_char16_t const var_name[] __initconst = {
> + 'S', 'e', 'c', 'u', 'r', 'e', 'B', 'o', 'o', 't', 0 };
> +
> + efi_get_variable_t *f_getvar = sys_table_arg->runtime->get_variable;
> + unsigned long size = sizeof(u8);
> + efi_status_t status;
> + u8 val;
> +
> + status = efi_call_phys5(f_getvar, (efi_char16_t *)var_name,
> + (efi_guid_t *)&var_guid, NULL, &size, &val);
> +
> + switch (status) {
> + case EFI_SUCCESS:
> + return val;
> + case EFI_NOT_FOUND:
> + return 0;
> + default:
> + return 1;
> + }
> +}
> --
> 1.7.10.4
>
^ permalink raw reply
* [PATCH] regulator: core: Make regulator object reflect configured voltage
From: Mark Brown @ 2014-02-05 18:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJAp7OjB-cJbLpdWo0RFJZefCKcCiKc8KgrjkBobJnddv4MSWA@mail.gmail.com>
On Wed, Feb 05, 2014 at 10:00:15AM -0800, Bjorn Andersson wrote:
> On Tue, Feb 4, 2014 at 12:00 PM, Mark Brown <broonie@kernel.org> wrote:
> > So we should be changing the code to allow a set_voltage() that sets the
> > voltage to the existing voltage regardless of constraints allowing a
> > change then - that's what the underlying issue is. Your change wouldn't
> > cover the case where the hardware defualt is being used for example.
> Makes sense, but the only thing we could check for would be if min_uV
> == max_uV == current-voltage. That would work out fine for this use
> case, but do you think it would be good enough?
It should be fine to check for min_uV <= current-voltage <= max_uV
instead if CHANGE_VOLTAGE isn't available, so long as the existing
setting is in the range it's fine.
> The best thing I've come up with then is to add the following check in
> regulator_set_voltage().
> if (min_uV == max_uV && _regulator_get_voltage(rdev) == min_uV)
> goto out;
> Would this be acceptable? It's achieving the same thing as my patch,
> is more robust and covers the case of setting the voltage to the hw
> default value.
That sort of thing yes, just short circuit out the main logic in this
case.
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