* [PATCH] ARM: mm: Fix the memblock allocation for LPAE machines
From: Santosh Shilimkar @ 2014-02-06 0:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205234815.GU26684@n2100.arm.linux.org.uk>
On Wednesday 05 February 2014 06:48 PM, Russell King - ARM Linux wrote:
> On Wed, Feb 05, 2014 at 06:39:44PM -0500, Santosh Shilimkar wrote:
>> Russell,
>>
>> On Saturday 01 February 2014 03:14 PM, Santosh Shilimkar wrote:
>>> Commit ad6492b8 added much needed memblock_virt_alloc_low() and further
>>> commit 07bacb3 {memblock, bootmem: restore goal for alloc_low} fixed the
>>> issue with low memory limit thansk to Yinghai. But even after all these fixes,
>>> there is still one case where the limit check done with ARCH_LOW_ADDRESS_LIMIT
>>> for low memory fails. Russell pointed out the issue with 32 bit LPAE machines
>>> in below thread.
>>> https://lkml.org/lkml/2014/1/28/364
>>>
>>> Since on some LPAE machines where memory start address is beyond 4GB,
>>> the low memory marker in memblock will be set to default
>>> ARCH_LOW_ADDRESS_LIMIT which is wrong. We can fix this by letting
>>> architectures set the ARCH_LOW_ADDRESS_LIMIT using another export
>>> similar to memblock_set_current_limit() but am not sure whether
>>> its worth the trouble. Tell me if you think otherwise.
>>>
>>> Rather am just trying to fix that one broken case using memblock_virt_alloc()
>>> in setup code since the memblock.current_limit is updated appropriately
>>> makes it work on all ARM 32 bit machines.
>>>
>>> Cc: Yinghai Lu <yinghai@kernel.org>
>>> Cc: Russell King <linux@arm.linux.org.uk>
>>> Cc: Strashko, Grygorii <grygorii.strashko@ti.com>
>>> Cc: Andrew Morton <akpm@linux-foundation.org>
>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> ---
>> Whats you say here ? We should get the fix for the
>> issue. If you are ok, I can drop the patch in patch system.
>
> Is this still an issue, or has Tejun fixed it by some other means? I've not
> noticed anything being broken at the moment.
>
> Can you confirm whether we still have an issue without this patch please?
>
Fixes for all cases exist except 'LPAE + memory start beyond 4 GB'.
This case is still broken and hence I posted the $subject patch.
Regards,
Santosh
^ permalink raw reply
* [PATCH 07/18] mfd: max14577: Rename and add MAX14577 symbols to prepare for max77836
From: Chanwoo Choi @ 2014-02-06 1:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390911522-28209-8-git-send-email-k.kozlowski@samsung.com>
On 01/28/2014 09:18 PM, Krzysztof Kozlowski wrote:
> This patch prepares for adding support for max77836 device to existing
> max14577 driver:
> 1. Renames most of symbols and defines prefixed with MAX14577 to MAXIM.
> 2. Adds prefixes (MAXIM or MAX14577) to defines without any MAX* prefix.
>
> This is only a rename-like patch, new code is not added.
>
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Cc: Kyungmin Park <kyungmin.park@samsung.com>
> Cc: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/extcon/extcon-max14577.c | 105 ++++-----
> drivers/mfd/max14577.c | 51 ++---
> drivers/power/max14577_charger.c | 81 +++----
> drivers/regulator/max14577.c | 44 ++--
> include/linux/mfd/max14577-private.h | 399 ++++++++++++++++------------------
> include/linux/mfd/max14577.h | 2 +-
> 6 files changed, 333 insertions(+), 349 deletions(-)
>
For extcon:
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Thanks,
Chanwoo Choi
^ permalink raw reply
* [PATCH 08/18] mfd: max14577: Rename state container to maxim_core
From: Chanwoo Choi @ 2014-02-06 1:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390911522-28209-9-git-send-email-k.kozlowski@samsung.com>
On 01/28/2014 09:18 PM, Krzysztof Kozlowski wrote:
> This patch continues the preparation for adding support for max77836
> device to existing max14577 driver.
>
> The patch renames the struct "max14577" state container to "maxim_core".
> This is only a rename-like patch, new code is not added.
>
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Cc: Kyungmin Park <kyungmin.park@samsung.com>
> Cc: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/extcon/extcon-max14577.c | 22 +++++------
> drivers/mfd/max14577.c | 68 +++++++++++++++++-----------------
> drivers/power/max14577_charger.c | 16 ++++----
> drivers/regulator/max14577.c | 6 +--
> include/linux/mfd/max14577-private.h | 5 ++-
> 5 files changed, 60 insertions(+), 57 deletions(-)
>
For extcon:
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
For mfd/regulator/charger/extcon of max14577
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Thanks,
Chanwoo Choi
^ permalink raw reply
* [PATCH 09/18] mfd: max14577: Add "muic" suffix to regmap and irq_chip
From: Chanwoo Choi @ 2014-02-06 1:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1390911522-28209-10-git-send-email-k.kozlowski@samsung.com>
On 01/28/2014 09:18 PM, Krzysztof Kozlowski wrote:
> This patch continues the preparation for adding support for max77836
> device to existing max14577 driver.
>
> Add "muic" suffix to regmap and irq_data fields in maxim_core state
> container to prepare for max77836 support.
> This is only a rename-like patch, new code is not added.
>
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Cc: Kyungmin Park <kyungmin.park@samsung.com>
> Cc: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/extcon/extcon-max14577.c | 17 +++++++++--------
> drivers/mfd/max14577.c | 22 +++++++++++-----------
> drivers/power/max14577_charger.c | 8 ++++----
> drivers/regulator/max14577.c | 2 +-
> include/linux/mfd/max14577-private.h | 4 ++--
> 5 files changed, 27 insertions(+), 26 deletions(-)
>
For extcon:
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
For mfd/regulator/charger/extcon of max14577
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Thanks,
Chanwoo Choi
^ permalink raw reply
* [PATCH 11/18] extcon: max14577: Add max14577 prefix to muic_irqs
From: Chanwoo Choi @ 2014-02-06 2:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140205140450.GE5196@lee--X1>
On 02/05/2014 11:04 PM, Lee Jones wrote:
>>> Following patch has conflict on extcon-next branch(Linus 3.14-rc1)
>>> when apply patchset by using git am.
>>>
>>> [PATCH 11/18] extcon: max14577: Add max14577 prefix to muic_irqs
>>> [PATCH 12/18] extcon: max14577: Choose muic_irqs according to device type
>>> [PATCH 14/18] extcon: max14577: Add support for max77836
>>>
>>> The base commit of this patchset isn't mainline. You need to rebase this patchset
>>> on extcon-next branch and please resend this patchset.
>
> <snip>
>
>> This patch patch (along with other) depends on previous rename patches
>> from this patchset:
>> [PATCH 07/18] mfd: max14577: Rename and add MAX14577 symbols to prepare
>> for max77836
>> http://article.gmane.org/gmane.linux.kernel/1636674
>>
>> I can resolve the conflict but then they will return on applying patch
>> 7/18.
>>
>> I think this patch may wait for a little until the rename-like patches
>> will be accepted.
>>
>> Can you ACK other patches touch extcon?
>> - [PATCH 07/18] mfd: max14577: Rename and add MAX14577 symbols...
>> - [PATCH 08/18] mfd: max14577: Rename state container to maxim_core
>> - [PATCH 09/18] mfd: max14577: Add "muic" suffix to regmap and irq_chip
>
> If you can obtain Acks for all of the patches, I can apply the entire
> patch-set to an immutable branch and issue a pull-request for the
> other maintainers to pull from.
>
Hi Lee,
OK, I agree your opionion.
I'd like you to apply this patchset dependent on extcon subsytem
on your tree. I acked on following patchset and tested all of this patchset series.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
[PATCH 06/18] extcon: max14577: Change extcon name instead of static name according to device type
- I will delete this patch([PATCH 06/18]) on extcon-next branch.
[PATCH 07/18] mfd: max14577: Rename and add MAX14577 symbols...
[PATCH 08/18] mfd: max14577: Rename state container to maxim_core
[PATCH 09/18] mfd: max14577: Add "muic" suffix to regmap and irq_chip
[PATCH 11/18] extcon: max14577: Add max14577 prefix to muic_irqs
[PATCH 12/18] extcon: max14577: Choose muic_irqs according to device type
[PATCH 14/18] extcon: max14577: Add support for max77836
Thanks,
Chanwoo Choi
^ permalink raw reply
* [PATCH 5/5] ARM: tegra: cpuidle: use firmware call for power down
From: Alexandre Courbot @ 2014-02-06 2:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F266A2.1030503@wwwdotorg.org>
On 02/06/2014 01:28 AM, Stephen Warren wrote:
> On 01/23/2014 12:39 AM, Alexandre Courbot wrote:
>> On Thu, Jan 23, 2014 at 5:45 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> On 01/21/2014 03:10 AM, Alexandre Courbot wrote:
>>>> Invoke the do_idle() firmware call before suspending a CPU so that the
>>>> underlying firmware (if any) can take necessary action.
>>>
>>>> diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
>>>
>>>> @@ -45,6 +46,8 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
>>>>
>>>> clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
>>>>
>>>> + call_firmware_op(do_idle);
>>>> +
>>>> cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
>>>>
>>>> clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
>>>
>>> Don't you need to have the kernel also *not* do something when entering
>>> idle; doesn't the FW op replace some of the register writes that the
>>> kernel would otherwise be doing?
>>
>> It seems like the operation is actually to inform the firmware that we
>> are going to suspend the CPU. Downstream kernel also uses it that way.
>> But you are right in that we should expect do_idle() to actually
>> perform the suspend operation. Maybe a prepare_idle() operation should
>> be added to the firmware interface for this purpose?
>
> That sounds like a reasonable change. Is it easy to plumb in?
I think so. Will post a v2 of this soon.
Thanks,
Alex.
^ permalink raw reply
* [PATCH v2 3/5] char: ti-usim: Add driver for USIM module on AM43xx
From: Satish Patel @ 2014-02-06 3:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F0E8EC.8030900@ti.com>
On 2/4/2014 6:49 PM, Roger Quadros wrote:
> Hi Satish,
>
> On 01/20/2014 06:33 AM, Satish Patel wrote:
>> TI-USIM driver is a platform driver that provides a character
>> driver interface to user applications.
>>
>> It allows user applications to call IOCTL's to
>> perform smart card operations.
>>
>> Driver currently supports
>> - ATR
>> - T=0 & T=1 protocol
>> - clock stop mode
>> - smart card clock configuration
>> - Tx/Rx application data units (APDU) to smart card
>> - Interface to PHY using DT & phy interface
>>
>> Validation is done with ACOS3 smart cards
>>
>> Signed-off-by: Satish Patel <satish.patel@ti.com>
>> ---
>> .../devicetree/bindings/ti-usim/ti-usim.txt | 31 +
>> drivers/char/Kconfig | 7 +
>> drivers/char/Makefile | 1 +
>> drivers/char/ti-usim-hw.h | 863 +++++++++
>> drivers/char/ti-usim.c | 1859 ++++++++++++++++++++
>
> ti-usim.c is a very large driver that does everything but looks like limited to TI hardware.
> How about splitting it into generic stuff and hw specific glue logic so that most of the generic stuff
> could be used by different hardware types.
>
Two things over here
- First interface between user application and smartcard controller
driver. There is already an open source f/w in user space called "pcsc"
exists for this.
- Second communication between smartcard controller and smartcard phy. I
have introduce lite interface called sc_phy which covers generic stuff
between controller and phy.
>> include/linux/ti-usim.h | 98 +
>> 6 files changed, 2859 insertions(+), 0 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/ti-usim/ti-usim.txt
>> create mode 100644 drivers/char/ti-usim-hw.h
>> create mode 100644 drivers/char/ti-usim.c
>> create mode 100644 include/linux/ti-usim.h
>>
>
> cheers,
> -roger
>
^ permalink raw reply
* [PATCH] ARM: imx6q: remove unneeded clk lookups
From: Shawn Guo @ 2014-02-06 4:14 UTC (permalink / raw)
To: linux-arm-kernel
Since commit (a94f8ec ARM: imx6q: remove board specific CLKO setup),
a number of clk lookups in imx6q clock driver is no longer needed.
Let's remove them.
The cpu0 lookup is also removed since we are now running imx6 cpufreq
driver and looking up clocks from device tree.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/clk-imx6q.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index af2e582..dd4f1e3 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -437,12 +437,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
- clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
- clk_register_clkdev(clk[ahb], "ahb", NULL);
- clk_register_clkdev(clk[cko1], "cko1", NULL);
- clk_register_clkdev(clk[arm], NULL, "cpu0");
- clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
- clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
cpu_is_imx6dl()) {
--
1.7.9.5
^ permalink raw reply related
* [PATCH V4 0/8]PCI:Add SPEAr13xx PCie support
From: Pratyush Anand @ 2014-02-06 4:44 UTC (permalink / raw)
To: linux-arm-kernel
First three patches are improvement and fixes for SPEAr13xx support.
Patches 4-6 add miphy40lp skelten driver and support for spear1310/40 miphy
wrapper. Patch 7 add support for SPEAr13xx PCIe.
These pathes are tested with linux-3.14-rc1 with following patch on the top of
it:
Author: Balaji T K <balajitk@ti.com>
Date: Mon Jan 20 16:41:27 2014 +0200
ata: ahci_platform: Manage SATA PHY
Tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Modifications for SATA are tested with SPEAr1340-evb board
Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3
Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall()
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g.
pcie designware driver improvements,fixes for IO translation bug, PCIe dw
driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA
platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.
PCIe driver support for SPEAr1310/40 platform board is added.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
Cc: linux-ide at vger.kernel.org
Cc: linux-pci at vger.kernel.org
Cc: spear-devel at list.st.com
Cc: linux-kernel at vger.kernel.org
Mohit Kumar (2):
SPEAr13xx: defconfig: Update
MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
Pratyush Anand (6):
clk: SPEAr13xx: Fix pcie clock name
SPEAr13xx: Fix static mapping table
phy: st-miphy-40lp: Add skeleton driver
SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
pcie: SPEAr13xx: Add designware pcie support
.../devicetree/bindings/arm/spear-misc.txt | 4 +
.../devicetree/bindings/pci/spear13xx-pcie.txt | 7 +
.../devicetree/bindings/phy/st-miphy40lp.txt | 12 +
MAINTAINERS | 6 +
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 96 +++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 32 +-
arch/arm/boot/dts/spear13xx.dtsi | 10 +-
arch/arm/configs/spear13xx_defconfig | 15 +
arch/arm/mach-spear/Kconfig | 3 +
arch/arm/mach-spear/include/mach/spear.h | 4 +-
arch/arm/mach-spear/spear1340.c | 127 +----
arch/arm/mach-spear/spear13xx.c | 2 +-
drivers/clk/spear/spear1310_clock.c | 6 +-
drivers/clk/spear/spear1340_clock.c | 2 +-
drivers/pci/host/Kconfig | 5 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-spear13xx.c | 414 ++++++++++++++++
drivers/phy/Kconfig | 6 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-miphy40lp.c | 544 +++++++++++++++++++++
22 files changed, 1166 insertions(+), 139 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
create mode 100644 drivers/pci/host/pcie-spear13xx.c
create mode 100644 drivers/phy/phy-miphy40lp.c
--
1.8.1.2
^ permalink raw reply
* [PATCH V4 1/8] clk: SPEAr13xx: Fix pcie clock name
From: Pratyush Anand @ 2014-02-06 4:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391661589.git.pratyush.anand@st.com>
Follow dt clock naming convention for PCIe clocks.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
drivers/clk/spear/spear1310_clock.c | 6 +++---
drivers/clk/spear/spear1340_clock.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 65894f7..4daa597 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.0");
+ clk_register_clkdev(clk, NULL, "b1000000.pcie");
clk_register_clkdev(clk, NULL, "b1000000.ahci");
clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.1");
+ clk_register_clkdev(clk, NULL, "b1800000.pcie");
clk_register_clkdev(clk, NULL, "b1800000.ahci");
clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.2");
+ clk_register_clkdev(clk, NULL, "b4000000.pcie");
clk_register_clkdev(clk, NULL, "b4000000.ahci");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index fe835c1..5a5c664 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base)
clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie");
+ clk_register_clkdev(clk, NULL, "b1000000.pcie");
clk_register_clkdev(clk, NULL, "b1000000.ahci");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
--
1.8.1.2
^ permalink raw reply related
* [PATCH V4 2/8] SPEAr13xx: Fix static mapping table
From: Pratyush Anand @ 2014-02-06 4:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391661589.git.pratyush.anand@st.com>
SPEAr13xx was using virtual address space 0xFE000000 to map physical address
space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So
change 0xFE000000 to 0xF9000000.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: stable at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
arch/arm/mach-spear/include/mach/spear.h | 4 ++--
arch/arm/mach-spear/spear13xx.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 5cdc53d..f2d6a01 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -52,10 +52,10 @@
#ifdef CONFIG_ARCH_SPEAR13XX
#define PERIP_GRP2_BASE UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000)
+#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)
#define MCIF_SDHCI_BASE UL(0xB3000000)
#define SYSRAM0_BASE UL(0xB3800000)
-#define VA_SYSRAM0_BASE IOMEM(0xFE800000)
+#define VA_SYSRAM0_BASE IOMEM(0xF9800000)
#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
#define PERIP_GRP1_BASE UL(0xE0000000)
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 7aa6e8c..89212ff 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -52,7 +52,7 @@ void __init spear13xx_l2x0_init(void)
/*
* Following will create 16MB static virtual/physical mappings
* PHYSICAL VIRTUAL
- * 0xB3000000 0xFE000000
+ * 0xB3000000 0xF9000000
* 0xE0000000 0xFD000000
* 0xEC000000 0xFC000000
* 0xED000000 0xFB000000
--
1.8.1.2
^ permalink raw reply related
* [PATCH V4 3/8] SPEAr13xx: defconfig: Update
From: Pratyush Anand @ 2014-02-06 4:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391661589.git.pratyush.anand@st.com>
From: Mohit Kumar <mohit.kumar@st.com>
Enable EABI, VFP and NFS configs in default configuration file for
SPEAr13xx.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
arch/arm/configs/spear13xx_defconfig | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 82eaa55..1e0bb6f 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -14,10 +14,18 @@ CONFIG_MACH_SPEAR1340=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_AEABI=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
@@ -27,6 +35,7 @@ CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
# CONFIG_SATA_PMP is not set
CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +75,7 @@ CONFIG_USB=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +89,14 @@ CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
--
1.8.1.2
^ permalink raw reply related
* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
From: Pratyush Anand @ 2014-02-06 4:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391661589.git.pratyush.anand@st.com>
ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
skeleton support for the same.
Currently phy ops are returning -EINVAL. They can be elaborated
depending on the SOC being supported in future.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
---
.../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++
drivers/phy/Kconfig | 6 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-miphy40lp.c | 174 +++++++++++++++++++++
4 files changed, 193 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
create mode 100644 drivers/phy/phy-miphy40lp.c
diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
new file mode 100644
index 0000000..d0c7096
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
@@ -0,0 +1,12 @@
+Required properties:
+- compatible : should be "st,miphy40lp-phy"
+ Other supported soc specific compatible:
+ "st,spear1310-miphy"
+ "st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+ - 1st cell: phandle to the phy node.
+ - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
+ and 2 for Super Speed USB.
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afa2354..2f58993 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
help
Enable this to support the Broadcom Kona USB 2.0 PHY.
+config PHY_ST_MIPHY40LP
+ tristate "ST MIPHY 40LP driver"
+ help
+ Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c253..c061091 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
+obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
new file mode 100644
index 0000000..d478c14
--- /dev/null
+++ b/drivers/phy/phy-miphy40lp.c
@@ -0,0 +1,174 @@
+/*
+ * ST MiPHY-40LP PHY driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+enum phy_mode {
+ SATA,
+ PCIE,
+ SS_USB,
+};
+
+struct st_miphy40lp_priv {
+ /* regmap for any soc specific misc registers */
+ struct regmap *misc;
+ /* phy struct pointer */
+ struct phy *phy;
+ /* device node pointer */
+ struct device_node *np;
+ /* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
+ enum phy_mode mode;
+ /* instance id of this phy */
+ u32 id;
+};
+
+static int miphy40lp_init(struct phy *phy)
+{
+ return -EINVAL;
+}
+
+static int miphy40lp_exit(struct phy *phy)
+{
+ return -EINVAL;
+}
+
+static int miphy40lp_power_off(struct phy *phy)
+{
+ return -EINVAL;
+}
+
+static int miphy40lp_power_on(struct phy *phy)
+{
+ return -EINVAL;
+}
+
+static const struct of_device_id st_miphy40lp_of_match[] = {
+ { .compatible = "st,miphy40lp-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
+
+static struct phy_ops st_miphy40lp_ops = {
+ .init = miphy40lp_init,
+ .exit = miphy40lp_exit,
+ .power_off = miphy40lp_power_off,
+ .power_on = miphy40lp_power_on,
+ .owner = THIS_MODULE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int miphy40lp_suspend(struct device *dev)
+{
+ return -EINVAL;
+}
+
+static int miphy40lp_resume(struct device *dev)
+{
+ return -EINVAL;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
+ miphy40lp_resume);
+
+static struct phy *st_miphy40lp_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+ if (args->args_count < 1) {
+ dev_err(dev, "DT did not pass correct no of args\n");
+ return NULL;
+ }
+
+ phypriv->mode = args->args[0];
+
+ return phypriv->phy;
+}
+
+static int __init st_miphy40lp_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct st_miphy40lp_priv *phypriv;
+ struct phy_provider *phy_provider;
+
+ phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
+ if (!phypriv) {
+ dev_err(dev, "can't alloc miphy40lp private date memory\n");
+ return -ENOMEM;
+ }
+
+ phypriv->np = dev->of_node;
+
+ phypriv->misc =
+ syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
+ if (IS_ERR(phypriv->misc)) {
+ dev_err(dev, "failed to find misc regmap\n");
+ return PTR_ERR(phypriv->misc);
+ }
+
+ if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
+ dev_err(dev, "failed to find phy id\n");
+ return -EINVAL;
+ }
+
+ phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(dev, "failed to register phy provider\n");
+ return PTR_ERR(phy_provider);
+ }
+
+ phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
+ if (IS_ERR(phypriv->phy)) {
+ dev_err(dev, "failed to create SATA PCIe PHY\n");
+ return PTR_ERR(phypriv->phy);
+ }
+
+ dev_set_drvdata(dev, phypriv);
+ phy_set_drvdata(phypriv->phy, phypriv);
+
+ return 0;
+}
+
+static int __exit st_miphy40lp_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static struct platform_driver st_miphy40lp_driver = {
+ .remove = __exit_p(st_miphy40lp_remove),
+ .driver = {
+ .name = "miphy40lp-phy",
+ .owner = THIS_MODULE,
+ .pm = &miphy40lp_pm_ops,
+ .of_match_table = of_match_ptr(st_miphy40lp_of_match),
+ },
+};
+
+static int __init st_miphy40lp_init(void)
+{
+
+ return platform_driver_probe(&st_miphy40lp_driver,
+ st_miphy40lp_probe);
+}
+module_init(st_miphy40lp_init);
+
+MODULE_DESCRIPTION("ST MIPHY-40LP driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
--
1.8.1.2
^ permalink raw reply related
* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
From: Pratyush Anand @ 2014-02-06 4:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391661589.git.pratyush.anand@st.com>
ahci driver needs some platform specific functions which are called at
init, exit, suspend and resume conditions. Till now these functions were
present in a platform driver with a fixme notes.
Similar functions modifying same set of registers will also be needed in
case of PCIe phy init/exit.
So move all these SATA platform code to phy-miphy40lp driver.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
Cc: linux-ide at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
---
.../devicetree/bindings/arm/spear-misc.txt | 4 +
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 39 +++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 13 +-
arch/arm/boot/dts/spear13xx.dtsi | 5 +
arch/arm/mach-spear/Kconfig | 2 +
arch/arm/mach-spear/spear1340.c | 127 +------------
drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
9 files changed, 266 insertions(+), 136 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt
new file mode 100644
index 0000000..aacd36a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
@@ -0,0 +1,4 @@
+* SPEAr Misc configuration
+** misc node required properties:
+- compatible Should be "st,spear1340-misc", "syscon".
+- reg: Address range of misc space
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index b56a801..d42c84b 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -106,6 +106,10 @@
status = "okay";
};
+ miphy at eb800000 {
+ status = "okay";
+ };
+
cf at b2800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 122ae94..64e7dd5 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -29,24 +29,57 @@
#gpio-cells = <2>;
};
- ahci at b1000000 {
+ miphy0: miphy at eb800000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ phy-id = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ miphy1: miphy at eb804000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb804000 0x4000>;
+ misc = <&misc>;
+ phy-id = <1>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ miphy2: miphy at eb808000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb808000 0x4000>;
+ misc = <&misc>;
+ phy-id = <2>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ ahci0: ahci at b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 68 0x4>;
+ phys = <&miphy0 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
- ahci at b1800000 {
+ ahci1: ahci at b1800000 {
compatible = "snps,spear-ahci";
reg = <0xb1800000 0x10000>;
interrupts = <0 69 0x4>;
+ phys = <&miphy1 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
- ahci at b4000000 {
+ ahci2: ahci at b4000000 {
compatible = "snps,spear-ahci";
reg = <0xb4000000 0x10000>;
interrupts = <0 70 0x4>;
+ phys = <&miphy2 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index d6c30ae..b23e05e 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -122,6 +122,10 @@
status = "okay";
};
+ miphy at eb800000 {
+ status = "okay";
+ };
+
dma at ea800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 54d128d..7e3a04b 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -31,10 +31,21 @@
status = "disabled";
};
- ahci at b1000000 {
+ miphy0: miphy at eb800000 {
+ compatible = "st,miphy", "st,spear1340-miphy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ phy-id = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ ahci0: ahci at b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 72 0x4>;
+ phys = <&miphy0 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3a72508 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -220,6 +220,11 @@
0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
+ misc: syscon at e0700000 {
+ compatible = "st,spear1340-misc", "syscon";
+ reg = <0xe0700000 0x1000>;
+ };
+
gpio0: gpio at e0600000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0600000 0x1000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e6..7e7f1b0 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -26,6 +26,8 @@ config ARCH_SPEAR13XX
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select USE_OF
+ select MFD_SYSCON
+ select PHY_ST_MIPHY40LP
help
Supports for ARM's SPEAR13XX family
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..8e27093 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -11,138 +11,13 @@
* warranty of any kind, whether express or implied.
*/
-#define pr_fmt(fmt) "SPEAr1340: " fmt
-
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
- /* PCIE CFG MASks */
- #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
- #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
- #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
- #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
- #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
- #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
- #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
- #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
- #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
- #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
- #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
- #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
- SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
- SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
- SPEAR1340_PCIE_CFG_POWERUP_RESET | \
- SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
- #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
- SPEAR1340_SATA_CFG_PM_CLK_EN | \
- SPEAR1340_SATA_CFG_POWERUP_RESET | \
- SPEAR1340_SATA_CFG_RX_CLK_EN | \
- SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
- #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
- #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
- #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_CLK_REF_DIV2 | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
- (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr)
-{
- writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
- writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
- SPEAR1340_PCIE_MIPHY_CFG);
- /* Switch on sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
- /* Disable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
-
- return 0;
-}
-
-void sata_miphy_exit(struct device *dev)
-{
- writel(0, SPEAR1340_PCIE_SATA_CFG);
- writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
- /* Enable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
- /* Switch off sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_FREEZE)
- return 0;
-
- sata_miphy_exit(dev);
-
- return 0;
-}
-
-int sata_resume(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_THAW)
- return 0;
-
- return sata_miphy_init(dev, NULL);
-}
-
-static struct ahci_platform_data sata_pdata = {
- .init = sata_miphy_init,
- .exit = sata_miphy_exit,
- .suspend = sata_suspend,
- .resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */
-static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
- &sata_pdata),
- {}
-};
static void __init spear1340_dt_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- spear1340_auxdata_lookup, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const spear1340_dt_board_compat[] = {
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index d478c14..cc7f45d 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -8,6 +8,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
+ * 04/02/2014: Adding support of SATA mode for SPEAr1340.
*/
#include <linux/delay.h>
@@ -19,6 +20,60 @@
#include <linux/phy/phy.h>
#include <linux/regmap.h>
+/* SPEAr1340 Registers */
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG 0x100
+ #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
+#define SPEAR1340_PCM_WKUP_CFG 0x104
+#define SPEAR1340_SWITCH_CTR 0x108
+
+#define SPEAR1340_PERIP1_SW_RST 0x318
+ #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
+#define SPEAR1340_PERIP2_SW_RST 0x31C
+#define SPEAR1340_PERIP3_SW_RST 0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG 0x424
+ /* PCIE CFG MASks */
+ #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
+ #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
+ #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
+ #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
+ #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
+ #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
+ #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
+ #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
+ #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
+ #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
+ #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
+ #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
+ SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+ SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+ SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+ SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+ #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
+ SPEAR1340_SATA_CFG_PM_CLK_EN | \
+ SPEAR1340_SATA_CFG_POWERUP_RESET | \
+ SPEAR1340_SATA_CFG_RX_CLK_EN | \
+ SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG 0x428
+ #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
+ #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
enum phy_mode {
SATA,
PCIE,
@@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
u32 id;
};
+static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+ /* Switch on sata power domain */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN);
+ msleep(20);
+ /* Disable PCIE SATA Controller reset */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RST_SATA, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+ /* Enable PCIE SATA Controller reset */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RST_SATA,
+ SPEAR1340_PERIP1_SW_RST_SATA);
+ msleep(20);
+ /* Switch off sata power domain */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_sata_miphy_init(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_sata_miphy_exit(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return 0;
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return 0;
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_sata_miphy_exit(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_sata_miphy_init(phypriv);
+ else
+ return -EINVAL;
+}
+
static int miphy40lp_init(struct phy *phy)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_init(phypriv);
+ default:
+ return -EINVAL;
+ }
}
static int miphy40lp_exit(struct phy *phy)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_exit(phypriv);
+ default:
+ return -EINVAL;
+ }
}
static int miphy40lp_power_off(struct phy *phy)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_power_off(phypriv);
+ default:
+ return -EINVAL;
+ }
}
static int miphy40lp_power_on(struct phy *phy)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_power_on(phypriv);
+ default:
+ return -EINVAL;
+ }
}
static const struct of_device_id st_miphy40lp_of_match[] = {
{ .compatible = "st,miphy40lp-phy" },
+ { .compatible = "st,spear1340-miphy" },
{ },
};
MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
@@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
#ifdef CONFIG_PM_SLEEP
static int miphy40lp_suspend(struct device *dev)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+ if (dev->power.power_state.event == PM_EVENT_FREEZE)
+ return 0;
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_suspend(phypriv);
+ default:
+ return -EINVAL;
+ }
}
static int miphy40lp_resume(struct device *dev)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+ if (dev->power.power_state.event == PM_EVENT_THAW)
+ return 0;
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_resume(phypriv);
+ default:
+ return -EINVAL;
+ }
}
#endif
--
1.8.1.2
^ permalink raw reply related
* [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
From: Pratyush Anand @ 2014-02-06 4:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391661589.git.pratyush.anand@st.com>
SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds
support for the same.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/phy/phy-miphy40lp.c | 178 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 178 insertions(+)
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index cc7f45d..61e94be 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -9,6 +9,7 @@
* published by the Free Software Foundation.
*
* 04/02/2014: Adding support of SATA mode for SPEAr1340.
+ * 04/02/2014: Adding support of PCIe mode for SPEAr1340 and SPEAr1310
*/
#include <linux/delay.h>
@@ -73,6 +74,80 @@
#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+/* SPEAr1310 Registers */
+#define SPEAR1310_PCIE_SATA_CFG 0x3A4
+ #define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
+ #define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30)
+ #define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29)
+ #define SPEAR1310_PCIE_SATA2_SEL_SATA (1 << 31)
+ #define SPEAR1310_PCIE_SATA1_SEL_SATA (1 << 30)
+ #define SPEAR1310_PCIE_SATA0_SEL_SATA (1 << 29)
+ #define SPEAR1310_SATA2_CFG_TX_CLK_EN (1 << 27)
+ #define SPEAR1310_SATA2_CFG_RX_CLK_EN (1 << 26)
+ #define SPEAR1310_SATA2_CFG_POWERUP_RESET (1 << 25)
+ #define SPEAR1310_SATA2_CFG_PM_CLK_EN (1 << 24)
+ #define SPEAR1310_SATA1_CFG_TX_CLK_EN (1 << 23)
+ #define SPEAR1310_SATA1_CFG_RX_CLK_EN (1 << 22)
+ #define SPEAR1310_SATA1_CFG_POWERUP_RESET (1 << 21)
+ #define SPEAR1310_SATA1_CFG_PM_CLK_EN (1 << 20)
+ #define SPEAR1310_SATA0_CFG_TX_CLK_EN (1 << 19)
+ #define SPEAR1310_SATA0_CFG_RX_CLK_EN (1 << 18)
+ #define SPEAR1310_SATA0_CFG_POWERUP_RESET (1 << 17)
+ #define SPEAR1310_SATA0_CFG_PM_CLK_EN (1 << 16)
+ #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT (1 << 11)
+ #define SPEAR1310_PCIE2_CFG_POWERUP_RESET (1 << 10)
+ #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN (1 << 9)
+ #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN (1 << 8)
+ #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT (1 << 7)
+ #define SPEAR1310_PCIE1_CFG_POWERUP_RESET (1 << 6)
+ #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN (1 << 5)
+ #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN (1 << 4)
+ #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT (1 << 3)
+ #define SPEAR1310_PCIE0_CFG_POWERUP_RESET (1 << 2)
+ #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN (1 << 1)
+ #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN (1 << 0)
+
+ #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | (1 << (x + 29)))
+ #define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+ (1 << (x + 29)))
+ #define SPEAR1310_PCIE_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+ SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+ #define SPEAR1310_SATA_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+ SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8
+ #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT (1 << 31)
+ #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 (1 << 28)
+ #define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16)
+ #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT (1 << 15)
+ #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 (1 << 12)
+ #define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC
enum phy_mode {
SATA,
@@ -181,6 +256,104 @@ static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
return -EINVAL;
}
+static int spear1340_pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_PCIE_CFG_VAL);
+
+ return 0;
+}
+
+static int spear1340_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+
+ return 0;
+}
+
+static int spear1310_pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ u32 mask, val;
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
+
+ switch (phypriv->id) {
+ case 0:
+ mask = SPEAR1310_PCIE_CFG_MASK(0);
+ val = SPEAR1310_PCIE_CFG_VAL(0);
+ break;
+ case 1:
+ mask = SPEAR1310_PCIE_CFG_MASK(1);
+ val = SPEAR1310_PCIE_CFG_VAL(1);
+ break;
+ case 2:
+ mask = SPEAR1310_PCIE_CFG_MASK(2);
+ val = SPEAR1310_PCIE_CFG_VAL(2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG, mask, val);
+
+ return 0;
+}
+
+static int spear1310_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ u32 mask;
+
+ switch (phypriv->id) {
+ case 0:
+ mask = SPEAR1310_PCIE_CFG_MASK(0);
+ break;
+ case 1:
+ mask = SPEAR1310_PCIE_CFG_MASK(1);
+ break;
+ case 2:
+ mask = SPEAR1310_PCIE_CFG_MASK(2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
+ SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
+
+ return 0;
+}
+
+static int pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_pcie_miphy_init(phypriv);
+ else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
+ return spear1310_pcie_miphy_init(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_pcie_miphy_exit(phypriv);
+ else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
+ return spear1310_pcie_miphy_exit(phypriv);
+ else
+ return -EINVAL;
+}
+
static int miphy40lp_init(struct phy *phy)
{
struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
@@ -188,6 +361,8 @@ static int miphy40lp_init(struct phy *phy)
switch (phypriv->mode) {
case SATA:
return sata_miphy_init(phypriv);
+ case PCIE:
+ return pcie_miphy_init(phypriv);
default:
return -EINVAL;
}
@@ -200,6 +375,8 @@ static int miphy40lp_exit(struct phy *phy)
switch (phypriv->mode) {
case SATA:
return sata_miphy_exit(phypriv);
+ case PCIE:
+ return pcie_miphy_exit(phypriv);
default:
return -EINVAL;
}
@@ -232,6 +409,7 @@ static int miphy40lp_power_on(struct phy *phy)
static const struct of_device_id st_miphy40lp_of_match[] = {
{ .compatible = "st,miphy40lp-phy" },
{ .compatible = "st,spear1340-miphy" },
+ { .compatible = "st,spear1310-miphy" },
{ },
};
MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
--
1.8.1.2
^ permalink raw reply related
* imx6dl/imx6q fec rmii mode with external ref_clk
From: Shawn Guo @ 2014-02-06 5:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140129095429.GA30854@frolo.macqel>
On Wed, Jan 29, 2014 at 10:54:29AM +0100, Philippe De Muyter wrote:
> > diff --git a/arch/arm/mach-imx/mach-imx6q.c
> > b/arch/arm/mach-imx/mach-imx6q.c
> > index e51e3da..be8d074 100644
> > --- a/arch/arm/mach-imx/mach-imx6q.c
> > +++ b/arch/arm/mach-imx/mach-imx6q.c
> > @@ -188,7 +188,7 @@ static void __init imx6q_1588_init(void)
> > if (!IS_ERR(gpr))
> > regmap_update_bits(gpr, IOMUXC_GPR1,
> > IMX6Q_GPR1_ENET_CLK_SEL_MASK,
> > - IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
> > + 0);
> > else
> > pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
> >
>
> Yes, it works now. Thanks. Is that configurable from the device tree ?
Yes, with some code change, I think that's configurable from device
tree. But, it's not that simple. As I explained in thread [1], the
RMII reference clock ENET_REF_CLK from pad GPIO_16 will also be used
by PTP (IEEE 1588) as sampling clock in your configuration. Right now,
the ptp clock in fec node is defaulted to be enet_ref from IMX6 CCM
(id 190) in imx6qdl.dtsi. You will need to correct it in your board dts
file, something like the following.
clocks {
#address-cells = <1>;
#size-cells = <0>;
rmii_clk: clock at 0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <25000000>; /* 25MHz for example */
};
};
&fec {
clocks = <&clks 117>, <&clks 117>, <&rmii_clk>;
};
I think we can even save a device tree property and ask kernel to figure
it out that bit GPR1[21] should be set or cleared. Yes, kernel should
be able to do that by checking whether the ptp_clk in fec node points to
the enet_ref clock coming from IMX6 clock driver (ANATOP/CCM). I will
send a patch for this soon.
Shawn
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/269265/focus=269646
^ permalink raw reply
* [PATCH] ARM: davinci: fix typo
From: Prabhakar Lad @ 2014-02-06 5:25 UTC (permalink / raw)
To: linux-arm-kernel
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
this patch fixes a typo in mach/hardware.h, by
replacing "ths" to "this".
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
---
arch/arm/mach-davinci/include/mach/hardware.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 16bb422..8a5d843 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -12,7 +12,7 @@
#define __ASM_ARCH_HARDWARE_H
/*
- * Before you add anything to ths file:
+ * Before you add anything to this file:
*
* This header is for defines common to ALL DaVinci family chips.
* Anything that is chip specific should go in <chipname>.h,
--
1.7.9.5
^ permalink raw reply related
* Freescale FEC packet loss
From: Christian Ege @ 2014-02-06 5:30 UTC (permalink / raw)
To: linux-arm-kernel
> On Sunday, January 26, 2014 at 10:33:33 PM, Ben Hutchings wrote:
> > On Sun, 2014-01-26 at 20:12 +0100, Marek Vasut wrote:
> > > On Sunday, January 26, 2014 at 07:56:30 PM, Ben Hutchings wrote:
> > > > On Wed, 2014-01-22 at 22:55 +0100, Marek Vasut wrote:
> > > > > Hi guys,
> > > > >
> > > > > I am running stock Linux 3.13 on i.MX6Q SabreLite board. The CPU is
> > > > > i.MX6Q TO 1.0 .
> > > > >
> > > > > I am hitting a WARNING when I use the FEC ethernet to transfer data,
> > > > > thus I started investigating this problem. TL;DR I am not able to
> > > > > figure this problem out, so I am not attaching a patch :-(
> > > > >
> > > > > Steps to reproduce:
> > > > > -------------------
> > > > > 1) Boot stock Linux 3.13 on i.MX6Q SabreLite board
> > > > > 2) Plug in an SD card into one of the SD slots (I use the full-size
> > > > > one) 3) Plug in an USB stick into one of the USB ports (I use the
> > > > > upper one) 4) Plug in an ethernet cable into the board
> > > > >
> > > > > -> Connect the other side into a gigabit-capable PC
> > > >
> > > > [...]
> > > >
> > > > I think there are known problems with 1000BASE-T on the Sabre Lite
> > > > board.
> > >
> > > This is MX6-wide thing, not sabrelite specific actually.
> > >
> > > > Two possible workarounds are to limit the PHY to 100BASE-TX
> > > > (should be doable with ethtool) or force it to be clock master for
> > > > 1000BASE-T (requires a driver patch).
> > >
> > > Can you please elaborate on the later ? I don't quite understand that.
> >
> > 1000BASE-T uses all 4 pairs in both directions at the same time, which
> > requires that both ends transmit symbols synchronously. As part of the
> > autonegotiation protocol, they decide which is the clock master (using a
> > local clock generator) and which is the clock slave (generating a clock
> > from the received signal). A PHY can be configured to support only one
> > of these roles.
>
> I checked the patch you pointed me to. The patch basically messes with the
> CTL1000 (0x9) register of the PHY, right ? I did the adjustments to the PHY
> register manually , but the result is still the same (backtrace).
>
> I did two different kinds of adjustment:
> 1) reg 0x9 |= 0x1800;
> 2) reg 0x9 |= 0x1000;
> In both cases, the crash did happen. I verified the PHY register was configured
> as necessary. The KSZ9021 PHY bit 12 configures the master/slave override, same
> as the patch does. The bit 11 forces either master or slave mode for the PHY. In
> both cases the crash was there.
>
> I think this patch won't help in this case, sorry.
>
Are there any news on this topic?
We also ran into these problems, we've tested the following scenarios
like Marek did with iperf:
We've tested on this equipment
----------------------------------------------
- Boundary Devices Nitrogen 6x Quad with Boundary Kernel based on FSL
3.10.17 (https://github.com/boundarydevices/linux-imx6/tree/boundary-imx_3.10.17_1.0.0_beta)
-> With this Kernel we do not have seen any issues. We see a stable
transfer and a acceptable bandwidth (~325 Mbit/s) on TCP/IP.
- Boundary Devices Nitrogen 6x Quad with vanilla Kernel 3.12.0
https://github.com/boundarydevices/linux-imx6/commits/boundary-imx_3.12.0
-> Here we had massive stability issues and a low TCP/IP throughput
( < 200 Mbit/s )
- Our custom board i.mx6 Dual KSZ9031 Phy with Kernel 3.11 we have
backported a bunch of Ethernet related Patches from mainline and FSL
-> We have a acceptable TCP/IP throughput (~310 Mbit/s) but we also
see periodicaly dips in transmission speed and the NETDEV WATCHDOG
OOps
- Another 3rd party i.mx6 quad board with Kernel 3.10
-> Here we had massive stability issues and a low TCP/IP
throughput ( < 180 Mbit/s )
Best regards,
Christian Ege
^ permalink raw reply
* [PATCH] ARM: imx6q: support ptp and rmii clock from pad
From: Shawn Guo @ 2014-02-06 5:53 UTC (permalink / raw)
To: linux-arm-kernel
On imx6qdl, the ENET RMII and PTP clock can come from either internal
ANATOP/CCM or external clock source through pad GPIO_16. But in case
of the external clock source, bit IOMUXC_GPR1[21] needs to be cleared.
The patch adds the support for systems that use an external clock source
and distinguishes above two cases by checking if the PTP clock specified
in device tree is the one coming from the internal ANATOP/CCM.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/clk-imx6q.c | 1 +
arch/arm/mach-imx/mach-imx6q.c | 36 +++++++++++++++++++++++++++++++++++-
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index dd4f1e3..45de2e5 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -437,6 +437,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
+ clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
cpu_is_imx6dl()) {
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index f9cbbf9..d131499b 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -182,16 +182,50 @@ static void __init imx6q_enet_phy_init(void)
static void __init imx6q_1588_init(void)
{
+ struct device_node *np;
+ struct clk *ptp_clk;
+ struct clk *enet_ref;
struct regmap *gpr;
+ u32 clksel;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
+ if (!np) {
+ pr_warn("%s: failed to find fec node\n", __func__);
+ return;
+ }
+
+ ptp_clk = of_clk_get(np, 2);
+ if (IS_ERR(ptp_clk)) {
+ pr_warn("%s: failed to get ptp clock\n", __func__);
+ goto put_node;
+ }
+
+ enet_ref = clk_get_sys(NULL, "enet_ref");
+ if (IS_ERR(enet_ref)) {
+ pr_warn("%s: failed to get enet clock\n", __func__);
+ goto put_ptp_clk;
+ }
+ /*
+ * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
+ * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad
+ * (external OSC), and we need to clear the bit.
+ */
+ clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
+ IMX6Q_GPR1_ENET_CLK_SEL_PAD;
gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
if (!IS_ERR(gpr))
regmap_update_bits(gpr, IOMUXC_GPR1,
IMX6Q_GPR1_ENET_CLK_SEL_MASK,
- IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
+ clksel);
else
pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
+ clk_put(enet_ref);
+put_ptp_clk:
+ clk_put(ptp_clk);
+put_node:
+ of_node_put(np);
}
static void __init imx6q_init_machine(void)
--
1.7.9.5
^ permalink raw reply related
* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
From: Kishon Vijay Abraham I @ 2014-02-06 6:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8596e7596e0dfa9a487c4c2deb325bbdf785e55e.1391661589.git.pratyush.anand@st.com>
Hi,
On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> skeleton support for the same.
>
> Currently phy ops are returning -EINVAL. They can be elaborated
> depending on the SOC being supported in future.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel at list.st.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: devicetree at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org
> ---
> .../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++
> drivers/phy/Kconfig | 6 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-miphy40lp.c | 174 +++++++++++++++++++++
> 4 files changed, 193 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> create mode 100644 drivers/phy/phy-miphy40lp.c
>
> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> new file mode 100644
> index 0000000..d0c7096
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> @@ -0,0 +1,12 @@
> +Required properties:
> +- compatible : should be "st,miphy40lp-phy"
> + Other supported soc specific compatible:
> + "st,spear1310-miphy"
> + "st,spear1340-miphy"
> +- reg : offset and length of the PHY register set.
> +- misc: phandle for the syscon node to access misc registers
> +- phy-id: Instance id of the phy.
> +- #phy-cells : from the generic PHY bindings, must be 1.
> + - 1st cell: phandle to the phy node.
> + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> + and 2 for Super Speed USB.
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index afa2354..2f58993 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
> help
> Enable this to support the Broadcom Kona USB 2.0 PHY.
>
> +config PHY_ST_MIPHY40LP
> + tristate "ST MIPHY 40LP driver"
> + help
> + Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> + select GENERIC_PHY
> +
> endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index b57c253..c061091 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
> obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
> obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
> obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
> +obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> new file mode 100644
> index 0000000..d478c14
> --- /dev/null
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -0,0 +1,174 @@
> +/*
> + * ST MiPHY-40LP PHY driver
> + *
> + * Copyright (C) 2014 ST Microelectronics
> + * Pratyush Anand <pratyush.anand@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +enum phy_mode {
> + SATA,
> + PCIE,
> + SS_USB,
> +};
> +
> +struct st_miphy40lp_priv {
> + /* regmap for any soc specific misc registers */
> + struct regmap *misc;
> + /* phy struct pointer */
> + struct phy *phy;
> + /* device node pointer */
> + struct device_node *np;
> + /* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> + enum phy_mode mode;
> + /* instance id of this phy */
> + u32 id;
> +};
> +
> +static int miphy40lp_init(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_exit(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_power_off(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_power_on(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static const struct of_device_id st_miphy40lp_of_match[] = {
> + { .compatible = "st,miphy40lp-phy" },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> +
> +static struct phy_ops st_miphy40lp_ops = {
> + .init = miphy40lp_init,
> + .exit = miphy40lp_exit,
> + .power_off = miphy40lp_power_off,
> + .power_on = miphy40lp_power_on,
> + .owner = THIS_MODULE,
Would prefer to either align all the fields or align none. Here only owner is
aligned.
> +};
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int miphy40lp_suspend(struct device *dev)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_resume(struct device *dev)
> +{
> + return -EINVAL;
> +}
> +#endif
> +
> +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> + miphy40lp_resume);
> +
> +static struct phy *st_miphy40lp_xlate(struct device *dev,
> + struct of_phandle_args *args)
> +{
> + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> + if (args->args_count < 1) {
> + dev_err(dev, "DT did not pass correct no of args\n");
> + return NULL;
> + }
> +
> + phypriv->mode = args->args[0];
> +
> + return phypriv->phy;
> +}
> +
> +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct st_miphy40lp_priv *phypriv;
> + struct phy_provider *phy_provider;
> +
> + phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> + if (!phypriv) {
> + dev_err(dev, "can't alloc miphy40lp private date memory\n");
> + return -ENOMEM;
> + }
> +
> + phypriv->np = dev->of_node;
> +
> + phypriv->misc =
> + syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> + if (IS_ERR(phypriv->misc)) {
> + dev_err(dev, "failed to find misc regmap\n");
> + return PTR_ERR(phypriv->misc);
> + }
> +
> + if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> + dev_err(dev, "failed to find phy id\n");
> + return -EINVAL;
> + }
Do we really need this phy id? How is it being used?
> +
> + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> + if (IS_ERR(phy_provider)) {
> + dev_err(dev, "failed to register phy provider\n");
> + return PTR_ERR(phy_provider);
> + }
phy_provider_register should be the last step in registering the PHY. Or your
PHY call backs can be called before you create the PHY. Btw in your case you
should call dev_set_drvdata before doing phy_provider_register.
> +
> + phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> + if (IS_ERR(phypriv->phy)) {
> + dev_err(dev, "failed to create SATA PCIe PHY\n");
> + return PTR_ERR(phypriv->phy);
> + }
> +
> + dev_set_drvdata(dev, phypriv);
> + phy_set_drvdata(phypriv->phy, phypriv);
> +
> + return 0;
> +}
> +
> +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
I think you can remove this empty 'remove' callback.
Thanks
Kishon
^ permalink raw reply
* [GIT PULL] Renesas CPG update for v3.15
From: Simon Horman @ 2014-02-06 6:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
please consider this Renesas CPG update for v3.15.
The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:
Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-cpg-for-v3.15
for you to fetch changes up to a028c6da34d434e35ba8322568c756ea97ff3c18:
ARM: shmobile: wait for MSTP clock status to toggle, when enabling it (2014-02-04 10:22:39 +0900)
----------------------------------------------------------------
Renesas CPG update for v3.15
* Wait for MSTP clock status to toggle when enabling it
----------------------------------------------------------------
Guennadi Liakhovetski (1):
ARM: shmobile: wait for MSTP clock status to toggle, when enabling it
drivers/sh/clk/cpg.c | 38 ++++++++++++++++++++++++++++++++++++++
include/linux/sh_clk.h | 19 ++++++++++++-------
2 files changed, 50 insertions(+), 7 deletions(-)
^ permalink raw reply
* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
From: Pratyush Anand @ 2014-02-06 6:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F32549.5010303@ti.com>
Hi Kishon,
On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> > skeleton support for the same.
> >
> > Currently phy ops are returning -EINVAL. They can be elaborated
> > depending on the SOC being supported in future.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Tested-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: spear-devel at list.st.com
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: devicetree at vger.kernel.org
> > Cc: linux-kernel at vger.kernel.org
> > ---
> > .../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++
> > drivers/phy/Kconfig | 6 +
> > drivers/phy/Makefile | 1 +
> > drivers/phy/phy-miphy40lp.c | 174 +++++++++++++++++++++
> > 4 files changed, 193 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > create mode 100644 drivers/phy/phy-miphy40lp.c
> >
> > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > new file mode 100644
> > index 0000000..d0c7096
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > @@ -0,0 +1,12 @@
> > +Required properties:
> > +- compatible : should be "st,miphy40lp-phy"
> > + Other supported soc specific compatible:
> > + "st,spear1310-miphy"
> > + "st,spear1340-miphy"
> > +- reg : offset and length of the PHY register set.
> > +- misc: phandle for the syscon node to access misc registers
> > +- phy-id: Instance id of the phy.
> > +- #phy-cells : from the generic PHY bindings, must be 1.
> > + - 1st cell: phandle to the phy node.
> > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > + and 2 for Super Speed USB.
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index afa2354..2f58993 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
> > help
> > Enable this to support the Broadcom Kona USB 2.0 PHY.
> >
> > +config PHY_ST_MIPHY40LP
> > + tristate "ST MIPHY 40LP driver"
> > + help
> > + Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> > + select GENERIC_PHY
> > +
> > endmenu
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index b57c253..c061091 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
> > obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
> > obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
> > obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
> > +obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > new file mode 100644
> > index 0000000..d478c14
> > --- /dev/null
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -0,0 +1,174 @@
> > +/*
> > + * ST MiPHY-40LP PHY driver
> > + *
> > + * Copyright (C) 2014 ST Microelectronics
> > + * Pratyush Anand <pratyush.anand@st.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/regmap.h>
> > +
> > +enum phy_mode {
> > + SATA,
> > + PCIE,
> > + SS_USB,
> > +};
> > +
> > +struct st_miphy40lp_priv {
> > + /* regmap for any soc specific misc registers */
> > + struct regmap *misc;
> > + /* phy struct pointer */
> > + struct phy *phy;
> > + /* device node pointer */
> > + struct device_node *np;
> > + /* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> > + enum phy_mode mode;
> > + /* instance id of this phy */
> > + u32 id;
> > +};
> > +
> > +static int miphy40lp_init(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_exit(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_off(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_on(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id st_miphy40lp_of_match[] = {
> > + { .compatible = "st,miphy40lp-phy" },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > +
> > +static struct phy_ops st_miphy40lp_ops = {
> > + .init = miphy40lp_init,
> > + .exit = miphy40lp_exit,
> > + .power_off = miphy40lp_power_off,
> > + .power_on = miphy40lp_power_on,
> > + .owner = THIS_MODULE,
>
> Would prefer to either align all the fields or align none. Here only owner is
> aligned.
ok.
> > +};
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int miphy40lp_suspend(struct device *dev)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_resume(struct device *dev)
> > +{
> > + return -EINVAL;
> > +}
> > +#endif
> > +
> > +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> > + miphy40lp_resume);
> > +
> > +static struct phy *st_miphy40lp_xlate(struct device *dev,
> > + struct of_phandle_args *args)
> > +{
> > + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > + if (args->args_count < 1) {
> > + dev_err(dev, "DT did not pass correct no of args\n");
> > + return NULL;
> > + }
> > +
> > + phypriv->mode = args->args[0];
> > +
> > + return phypriv->phy;
> > +}
> > +
> > +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct st_miphy40lp_priv *phypriv;
> > + struct phy_provider *phy_provider;
> > +
> > + phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> > + if (!phypriv) {
> > + dev_err(dev, "can't alloc miphy40lp private date memory\n");
> > + return -ENOMEM;
> > + }
> > +
> > + phypriv->np = dev->of_node;
> > +
> > + phypriv->misc =
> > + syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> > + if (IS_ERR(phypriv->misc)) {
> > + dev_err(dev, "failed to find misc regmap\n");
> > + return PTR_ERR(phypriv->misc);
> > + }
> > +
> > + if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> > + dev_err(dev, "failed to find phy id\n");
> > + return -EINVAL;
> > + }
> Do we really need this phy id? How is it being used?
Yes , it is being used by patch 6/8.
>
> > +
> > + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> > + if (IS_ERR(phy_provider)) {
> > + dev_err(dev, "failed to register phy provider\n");
> > + return PTR_ERR(phy_provider);
> > + }
>
> phy_provider_register should be the last step in registering the PHY. Or your
> PHY call backs can be called before you create the PHY. Btw in your case you
But every one else like phy-exynos-mipi-video or phy-omap-usb2 or any
other did it same way. First phy_provider_register and then
phy_create.
> should call dev_set_drvdata before doing phy_provider_register.
yes, I need to correct it.
> > +
> > + phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> > + if (IS_ERR(phypriv->phy)) {
> > + dev_err(dev, "failed to create SATA PCIe PHY\n");
> > + return PTR_ERR(phypriv->phy);
> > + }
> > +
> > + dev_set_drvdata(dev, phypriv);
> > + phy_set_drvdata(phypriv->phy, phypriv);
> > +
> > + return 0;
> > +}
> > +
> > +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> > +{
> > + return 0;
> > +}
>
> I think you can remove this empty 'remove' callback.
Yaa.. Can be removed.
Rgds
Pratyush
>
> Thanks
> Kishon
^ permalink raw reply
* [PATCH] ARM: shmobile: wait for MSTP clock status to toggle, when enabling it
From: Simon Horman @ 2014-02-06 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391651474.git.horms+renesas@verge.net.au>
From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
On r-/sh-mobile SoCs MSTP clocks are used by the runtime PM to dynamically
enable and disable peripheral clocks. To make sure the clock has really
started we have to read back its status register until it confirms success.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/sh/clk/cpg.c | 38 ++++++++++++++++++++++++++++++++++++++
include/linux/sh_clk.h | 19 ++++++++++++-------
2 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 1ebe67c..7442bc1 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -36,9 +36,47 @@ static void sh_clk_write(int value, struct clk *clk)
iowrite32(value, clk->mapped_reg);
}
+static unsigned int r8(const void __iomem *addr)
+{
+ return ioread8(addr);
+}
+
+static unsigned int r16(const void __iomem *addr)
+{
+ return ioread16(addr);
+}
+
+static unsigned int r32(const void __iomem *addr)
+{
+ return ioread32(addr);
+}
+
static int sh_clk_mstp_enable(struct clk *clk)
{
sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);
+ if (clk->status_reg) {
+ unsigned int (*read)(const void __iomem *addr);
+ int i;
+ void __iomem *mapped_status = (phys_addr_t)clk->status_reg -
+ (phys_addr_t)clk->enable_reg + clk->mapped_reg;
+
+ if (clk->flags & CLK_ENABLE_REG_8BIT)
+ read = r8;
+ else if (clk->flags & CLK_ENABLE_REG_16BIT)
+ read = r16;
+ else
+ read = r32;
+
+ for (i = 1000;
+ (read(mapped_status) & (1 << clk->enable_bit)) && i;
+ i--)
+ cpu_relax();
+ if (!i) {
+ pr_err("cpg: failed to enable %p[%d]\n",
+ clk->enable_reg, clk->enable_bit);
+ return -ETIMEDOUT;
+ }
+ }
return 0;
}
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
index 60c7239..1f208b2 100644
--- a/include/linux/sh_clk.h
+++ b/include/linux/sh_clk.h
@@ -52,6 +52,7 @@ struct clk {
unsigned long flags;
void __iomem *enable_reg;
+ void __iomem *status_reg;
unsigned int enable_bit;
void __iomem *mapped_reg;
@@ -116,22 +117,26 @@ long clk_round_parent(struct clk *clk, unsigned long target,
unsigned long *best_freq, unsigned long *parent_freq,
unsigned int div_min, unsigned int div_max);
-#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \
+#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \
{ \
.parent = _parent, \
.enable_reg = (void __iomem *)_enable_reg, \
.enable_bit = _enable_bit, \
+ .status_reg = _status_reg, \
.flags = _flags, \
}
-#define SH_CLK_MSTP32(_p, _r, _b, _f) \
- SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT)
+#define SH_CLK_MSTP32(_p, _r, _b, _f) \
+ SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT)
-#define SH_CLK_MSTP16(_p, _r, _b, _f) \
- SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT)
+#define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \
+ SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT)
-#define SH_CLK_MSTP8(_p, _r, _b, _f) \
- SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT)
+#define SH_CLK_MSTP16(_p, _r, _b, _f) \
+ SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
+
+#define SH_CLK_MSTP8(_p, _r, _b, _f) \
+ SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT)
int sh_clk_mstp_register(struct clk *clks, int nr);
--
1.8.5.2
^ permalink raw reply related
* [GIT PULL 00/21] Renesas ARM based SoC Board Updates for v3.15
From: Simon Horman @ 2014-02-06 6:17 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
please consider these Renesas ARM based SoC board updates for v3.15.
The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:
Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-boards-for-v3.15
for you to fetch changes up to 235cda29e4d5047622ff9b82b1f0b4cb6cf95f6c:
ARM: shmobile: Remove Lager USBHS UDC ifdefs (2014-02-04 14:28:33 +0900)
----------------------------------------------------------------
Renesas ARM based SoC Board Updates for v3.15
* r8a7791 (R-Car M2) based Koelsch board
- Fix error return code check from clk_get()
- Add SATA0 support
- Conditionally select MICREL_PHY for Multiplatform
* r8a7790 (R-Car H2) based Lager board
- Add USBHS support
- Fix error return code check from clk_get()
- Add SATA support
- Make spi_flash_data const
- Add VIN1 SoC camera support
- Conditionally select CONFIG_MICREL_PHY
* r8a7778 (R-Car M1) based Bock-W board
- Add USB Func DMAEngine support
- Use HPBIF DMAEngine for sound
- Use SSI DMAEngine for sound
* emev2 (Emma Mobile EV2) based kzm9d board
- Use common clock framework
* r8a773a0 (SH-Mobile AG5) based kzm9g board
- Add zboot support
* Many boards
- Conditionally select SMSC_PHY
----------------------------------------------------------------
Ben Dooks (2):
ARM: shmobile: lager: fix error return code check from clk_get()
ARM: shmobile: koelsch: fix error return code check from clk_get()
Geert Uytterhoeven (1):
ARM: shmobile: lager: Make spi_flash_data const
Kuninori Morimoto (3):
ARM: shmobile: bockw: use SSI DMAEngine for sound
ARM: shmobile: bockw: use HPBIF DMAEngine for sound
ARM: shmobile: bockw: add USB Func DMAEngine support
Magnus Damm (1):
ARM: shmobile: Remove Lager USBHS UDC ifdefs
Sergei Shtylyov (1):
ARM: shmobile: Lager: conditionally select CONFIG_MICREL_PHY
Simon Horman (7):
ARM: shmobile: koelsch: Conditionally select MICREL_PHY for Multiplatform
ARM: shmobile: ape6evm: Conditionally select SMSC_PHY
ARM: shmobile: armadillo800eva: Conditionally select SMSC_PHY
ARM: shmobile: bockw: Sort Kconfig node's selections
ARM: shmobile: kzm9d: Conditionally select SMSC_PHY
ARM: shmobile: mackerel: Conditionally select SMSC_PHY
ARM: shmobile: marzen: Conditionally select SMSC_PHY
Takashi Yoshii (1):
ARM: shmobile: kzm9d: Use common clock framework
Ulrich Hecht (1):
ARM: mach-shmobile: kzm9g: add zboot support
Valentine Barshak (4):
ARM: shmobile: lager: Add VIN1 SoC camera support
ARM: shmobile: lager: Add SATA support
ARM: shmobile: koelsch: Add SATA0 support
ARM: shmobile: lager: Add USBHS support
arch/arm/mach-shmobile/Kconfig | 15 +-
arch/arm/mach-shmobile/board-bockw.c | 24 +-
arch/arm/mach-shmobile/board-koelsch-reference.c | 4 +-
arch/arm/mach-shmobile/board-koelsch.c | 17 +
arch/arm/mach-shmobile/board-kzm9d-reference.c | 5 +-
arch/arm/mach-shmobile/board-lager-reference.c | 4 +-
arch/arm/mach-shmobile/board-lager.c | 229 +++++++++++-
arch/arm/mach-shmobile/include/mach/head-kzm9g.txt | 410 +++++++++++++++++++++
arch/arm/mach-shmobile/include/mach/zboot.h | 3 +
arch/arm/mach-shmobile/include/mach/zboot_macros.h | 43 +++
10 files changed, 737 insertions(+), 17 deletions(-)
create mode 100644 arch/arm/mach-shmobile/include/mach/head-kzm9g.txt
^ permalink raw reply
* [PATCH 01/21] ARM: shmobile: Lager: conditionally select CONFIG_MICREL_PHY
From: Simon Horman @ 2014-02-06 6:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Now that support for KSZ8041RNLI is added to the Micrel PHY driver and we intend
to support PHY IRQs on the Lager board, we have to enable the Micrel driver.
Do this by selecting CONFIG_MICREL_PHY for Lager if CONFIG_SH_ETH is enabled.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 3386406..a127252 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -54,6 +54,7 @@ config MACH_KZM9D
config MACH_LAGER
bool "Lager board"
depends on ARCH_R8A7790
+ select MICREL_PHY if SH_ETH
comment "Renesas ARM SoCs System Configuration"
endif
@@ -261,6 +262,7 @@ config MACH_LAGER
bool "Lager board"
depends on ARCH_R8A7790
select USE_OF
+ select MICREL_PHY if SH_ETH
config MACH_KOELSCH
bool "Koelsch board"
--
1.8.5.2
^ permalink raw reply related
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