* [PATCH 15/21] ARM: shmobile: kzm9d: Conditionally select SMSC_PHY
From: Simon Horman @ 2014-02-06 6:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
The kzm9d board uses has an SMSC911X ethernet controller which uses an
SMSC phy. Select SMSC_PHY for kzm9d if SMSC911X is enabled to make use of the
SMSC-specific phy driver rather than relying on the generic phy driver.
This only covers the case of multiplatform kzm9d
as there is currently no Kconfig node for non-multiplatform kzm9d.
One could be added if desired.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 6f16983..b735ea8 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -51,6 +51,7 @@ config MACH_KZM9D
bool "KZM9D board"
depends on ARCH_EMEV2
select REGULATOR_FIXED_VOLTAGE if REGULATOR
+ select SMSC_PHY if SMSC911X
config MACH_LAGER
bool "Lager board"
--
1.8.5.2
^ permalink raw reply related
* [PATCH 14/21] ARM: shmobile: bockw: Sort Kconfig node's selections
From: Simon Horman @ 2014-02-06 6:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index b624b5a..6f16983 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -207,11 +207,11 @@ config MACH_BOCKW
bool "BOCK-W platform"
depends on ARCH_R8A7778
select ARCH_REQUIRE_GPIOLIB
- select RENESAS_INTC_IRQPIN
select REGULATOR_FIXED_VOLTAGE if REGULATOR
- select USE_OF
+ select RENESAS_INTC_IRQPIN
select SND_SOC_AK4554 if SND_SIMPLE_CARD
select SND_SOC_AK4642 if SND_SIMPLE_CARD
+ select USE_OF
config MACH_BOCKW_REFERENCE
bool "BOCK-W - Reference Device Tree Implementation"
--
1.8.5.2
^ permalink raw reply related
* [PATCH 13/21] ARM: shmobile: armadillo800eva: Conditionally select SMSC_PHY
From: Simon Horman @ 2014-02-06 6:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
The armadillo800eva board uses has an SH ethernet controller which uses an
SMSC phy. Select SMSC_PHY for koelsch if SH_ETH is enabled to make use of the
SMSC-specific phy driver rather than relying on the generic phy driver.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 2673f68..b624b5a 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -184,6 +184,7 @@ config MACH_ARMADILLO800EVA
depends on ARCH_R8A7740
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
+ select SMSC_PHY if SH_ETH
select SND_SOC_WM8978 if SND_SIMPLE_CARD
select USE_OF
@@ -192,6 +193,7 @@ config MACH_ARMADILLO800EVA_REFERENCE
depends on ARCH_R8A7740
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
+ select SMSC_PHY if SH_ETH
select SND_SOC_WM8978 if SND_SIMPLE_CARD
select USE_OF
---help---
--
1.8.5.2
^ permalink raw reply related
* [PATCH 12/21] ARM: shmobile: ape6evm: Conditionally select SMSC_PHY
From: Simon Horman @ 2014-02-06 6:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
The ape6evm board uses has an SMSC911X ethernet controller which uses an
SMSC phy. Select SMSC_PHY for ape6evm if SMSC911X is enabled to make use of the
SMSC-specific phy driver rather than relying on the generic phy driver.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 958ccf3d..2673f68 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -156,11 +156,13 @@ comment "Renesas ARM SoCs Board Type"
config MACH_APE6EVM
bool "APE6EVM board"
depends on ARCH_R8A73A4
+ select SMSC_PHY if SMSC911X
select USE_OF
config MACH_APE6EVM_REFERENCE
bool "APE6EVM board - Reference Device Tree Implementation"
depends on ARCH_R8A73A4
+ select SMSC_PHY if SMSC911X
select USE_OF
---help---
Use reference implementation of APE6EVM board support
--
1.8.5.2
^ permalink raw reply related
* [PATCH 11/21] ARM: shmobile: koelsch: Add SATA0 support
From: Simon Horman @ 2014-02-06 6:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
This adds SATA0 support to Koelsch board.
SATA1 is not available since its pinmux
configuration is fixed to PCIe.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/board-koelsch.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index de7cc64..2ab5c75 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -148,6 +148,21 @@ static const struct gpio_keys_platform_data koelsch_keys_pdata __initconst = {
.nbuttons = ARRAY_SIZE(gpio_buttons),
};
+/* SATA0 */
+static const struct resource sata0_resources[] __initconst = {
+ DEFINE_RES_MEM(0xee300000, 0x2000),
+ DEFINE_RES_IRQ(gic_spi(105)),
+};
+
+static const struct platform_device_info sata0_info __initconst = {
+ .parent = &platform_bus,
+ .name = "sata-r8a7791",
+ .id = 0,
+ .res = sata0_resources,
+ .num_res = ARRAY_SIZE(sata0_resources),
+ .dma_mask = DMA_BIT_MASK(32),
+};
+
static const struct pinctrl_map koelsch_pinctrl_map[] = {
/* DU */
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
@@ -192,6 +207,8 @@ static void __init koelsch_add_standard_devices(void)
sizeof(koelsch_keys_pdata));
koelsch_add_du_device();
+
+ platform_device_register_full(&sata0_info);
}
/*
--
1.8.5.2
^ permalink raw reply related
* [PATCH 10/21] ARM: shmobile: lager: Add SATA support
From: Simon Horman @ 2014-02-06 6:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
This adds SATA support to Lager board. Only SATA1 port is available.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Acked-by: Magnus Damm <damm@opensource.se>
[horms+renesas at verge.net.au: resolved trivial conflicts]
[horms+renesas at verge.net.au: capitalised "ARM" in subject]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/board-lager.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index aa8f1d9..8dde446 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -349,6 +349,21 @@ static void __init lager_add_camera1_device(void)
lager_add_vin_device(1, &vin1_pdata);
}
+/* SATA1 */
+static const struct resource sata1_resources[] __initconst = {
+ DEFINE_RES_MEM(0xee500000, 0x2000),
+ DEFINE_RES_IRQ(gic_spi(106)),
+};
+
+static const struct platform_device_info sata1_info __initconst = {
+ .parent = &platform_bus,
+ .name = "sata-r8a7790",
+ .id = 1,
+ .res = sata1_resources,
+ .num_res = ARRAY_SIZE(sata1_resources),
+ .dma_mask = DMA_BIT_MASK(32),
+};
+
static const struct pinctrl_map lager_pinctrl_map[] = {
/* DU (CN10: ARGB0, CN13: LVDS) */
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
@@ -444,6 +459,8 @@ static void __init lager_add_standard_devices(void)
&vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
lager_add_camera1_device();
+
+ platform_device_register_full(&sata1_info);
}
/*
--
1.8.5.2
^ permalink raw reply related
* [PATCH 09/21] ARM: shmobile: lager: Make spi_flash_data const
From: Simon Horman @ 2014-02-06 6:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/board-lager.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index c5643e1..aa8f1d9 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -265,7 +265,7 @@ static struct mtd_partition spi_flash_part[] = {
},
};
-static struct flash_platform_data spi_flash_data = {
+static const struct flash_platform_data spi_flash_data = {
.name = "m25p80",
.parts = spi_flash_part,
.nr_parts = ARRAY_SIZE(spi_flash_part),
--
1.8.5.2
^ permalink raw reply related
* [PATCH 08/21] ARM: shmobile: kzm9d: Use common clock framework
From: Simon Horman @ 2014-02-06 6:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
From: Takashi Yoshii <takasi-y@ops.dti.ne.jp>
Use common clock framework version of clock
drivers/clk/shmobile/clk-emev2.c
instead of sh-clkfwk version
arch/arm/mach-shmobile/clock-emev2.c
when it is configured as a part of multi-platform.
Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/board-kzm9d-reference.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-kzm9d-reference.c b/arch/arm/mach-shmobile/board-kzm9d-reference.c
index 054d8d5..853003c 100644
--- a/arch/arm/mach-shmobile/board-kzm9d-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9d-reference.c
@@ -20,15 +20,14 @@
#include <linux/init.h>
#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
#include <mach/emev2.h>
#include <mach/common.h>
#include <asm/mach/arch.h>
static void __init kzm9d_add_standard_devices(void)
{
- if (!IS_ENABLED(CONFIG_COMMON_CLK))
- emev2_clock_init();
-
+ of_clk_init(NULL);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
--
1.8.5.2
^ permalink raw reply related
* [PATCH 07/21] ARM: shmobile: lager: Add VIN1 SoC camera support
From: Simon Horman @ 2014-02-06 6:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
This adds VIN1 SoC camera along with ADV7180 subdevice support to Lager.
VIN0 camera is not registered because it has ADV7612 I2C subdevice
which is not supported yet.
Changes in V2:
* made lager_add_vin_device function static.
Changes in V3:
* capitalized ARM in the subject.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/board-lager.c | 76 ++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index f20c10a..c5643e1 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -27,6 +27,7 @@
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mmcif.h>
#include <linux/pinctrl/machine.h>
+#include <linux/platform_data/camera-rcar.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/rcar-du.h>
#include <linux/platform_device.h>
@@ -39,6 +40,7 @@
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a7790.h>
+#include <media/soc_camera.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <linux/mtd/partitions.h>
@@ -291,6 +293,62 @@ static const struct resource qspi_resources[] __initconst = {
DEFINE_RES_IRQ(gic_spi(184)),
};
+/* VIN */
+static const struct resource vin_resources[] __initconst = {
+ /* VIN0 */
+ DEFINE_RES_MEM(0xe6ef0000, 0x1000),
+ DEFINE_RES_IRQ(gic_spi(188)),
+ /* VIN1 */
+ DEFINE_RES_MEM(0xe6ef1000, 0x1000),
+ DEFINE_RES_IRQ(gic_spi(189)),
+};
+
+static void __init lager_add_vin_device(unsigned idx,
+ struct rcar_vin_platform_data *pdata)
+{
+ struct platform_device_info vin_info = {
+ .parent = &platform_bus,
+ .name = "r8a7790-vin",
+ .id = idx,
+ .res = &vin_resources[idx * 2],
+ .num_res = 2,
+ .dma_mask = DMA_BIT_MASK(32),
+ .data = pdata,
+ .size_data = sizeof(*pdata),
+ };
+
+ BUG_ON(idx > 1);
+
+ platform_device_register_full(&vin_info);
+}
+
+#define LAGER_CAMERA(idx, name, addr, pdata, flag) \
+static struct i2c_board_info i2c_cam##idx##_device = { \
+ I2C_BOARD_INFO(name, addr), \
+}; \
+ \
+static struct rcar_vin_platform_data vin##idx##_pdata = { \
+ .flags = flag, \
+}; \
+ \
+static struct soc_camera_link cam##idx##_link = { \
+ .bus_id = idx, \
+ .board_info = &i2c_cam##idx##_device, \
+ .i2c_adapter_id = 2, \
+ .module_name = name, \
+ .priv = pdata, \
+}
+
+/* Camera 0 is not currently supported due to adv7612 support missing */
+LAGER_CAMERA(1, "adv7180", 0x20, NULL, RCAR_VIN_BT656);
+
+static void __init lager_add_camera1_device(void)
+{
+ platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1,
+ &cam1_link, sizeof(cam1_link));
+ lager_add_vin_device(1, &vin1_pdata);
+}
+
static const struct pinctrl_map lager_pinctrl_map[] = {
/* DU (CN10: ARGB0, CN13: LVDS) */
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
@@ -319,6 +377,22 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
"eth_rmii", "eth"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
"intc_irq0", "intc"),
+ /* VIN0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
+ "vin0_data24", "vin0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
+ "vin0_sync", "vin0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
+ "vin0_field", "vin0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
+ "vin0_clkenb", "vin0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
+ "vin0_clk", "vin0"),
+ /* VIN1 */
+ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
+ "vin1_data8", "vin1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
+ "vin1_clk", "vin1"),
};
static void __init lager_add_standard_devices(void)
@@ -368,6 +442,8 @@ static void __init lager_add_standard_devices(void)
&vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++,
&vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
+
+ lager_add_camera1_device();
}
/*
--
1.8.5.2
^ permalink raw reply related
* [PATCH 06/21] ARM: mach-shmobile: kzm9g: add zboot support
From: Simon Horman @ 2014-02-06 6:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
From: Ulrich Hecht <ulrich.hecht@gmail.com>
Adds support to run the kernel on the uninitialized KZM9G board, using for
instance the mask ROM boot loader or JTAG. This patch tries to emulate the
style of the corresponding "mackerel" implementation. The DRAM controller
setup code has been adapted from u-boot.
Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/include/mach/head-kzm9g.txt | 410 +++++++++++++++++++++
arch/arm/mach-shmobile/include/mach/zboot.h | 3 +
arch/arm/mach-shmobile/include/mach/zboot_macros.h | 43 +++
3 files changed, 456 insertions(+)
create mode 100644 arch/arm/mach-shmobile/include/mach/head-kzm9g.txt
diff --git a/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt b/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt
new file mode 100644
index 0000000..9531f46
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt
@@ -0,0 +1,410 @@
+LIST "KZM9G low-level initialization routine."
+LIST "Adapted from u-boot KZM9G support code."
+
+LIST "Copyright (C) 2013 Ulrich Hecht"
+
+LIST "This program is free software; you can redistribute it and/or modify"
+LIST "it under the terms of the GNU General Public License version 2 as"
+LIST "published by the Free Software Foundation."
+
+LIST "This program is distributed in the hope that it will be useful,"
+LIST "but WITHOUT ANY WARRANTY; without even the implied warranty of"
+LIST "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the"
+LIST "GNU General Public License for more details."
+
+
+LIST "Register definitions:"
+
+LIST "Secure control register"
+#define LIFEC_SEC_SRC (0xE6110008)
+
+LIST "RWDT"
+#define RWDT_BASE (0xE6020000)
+#define RWTCSRA0 (RWDT_BASE + 0x04)
+
+LIST "HPB Semaphore Control Registers"
+#define HPBSCR_BASE (0xE6000000)
+#define HPBCTRL6 (HPBSCR_BASE + 0x1030)
+
+#define SBSC1_BASE (0xFE400000)
+#define SDCR0A (SBSC1_BASE + 0x0008)
+#define SDCR1A (SBSC1_BASE + 0x000C)
+#define SDPCRA (SBSC1_BASE + 0x0010)
+#define SDCR0SA (SBSC1_BASE + 0x0018)
+#define SDCR1SA (SBSC1_BASE + 0x001C)
+#define RTCSRA (SBSC1_BASE + 0x0020)
+#define RTCORA (SBSC1_BASE + 0x0028)
+#define RTCORHA (SBSC1_BASE + 0x002C)
+#define SDWCRC0A (SBSC1_BASE + 0x0040)
+#define SDWCRC1A (SBSC1_BASE + 0x0044)
+#define SDWCR00A (SBSC1_BASE + 0x0048)
+#define SDWCR01A (SBSC1_BASE + 0x004C)
+#define SDWCR10A (SBSC1_BASE + 0x0050)
+#define SDWCR11A (SBSC1_BASE + 0x0054)
+#define SDWCR2A (SBSC1_BASE + 0x0060)
+#define SDWCRC2A (SBSC1_BASE + 0x0064)
+#define ZQCCRA (SBSC1_BASE + 0x0068)
+#define SDMRACR0A (SBSC1_BASE + 0x0084)
+#define SDMRTMPCRA (SBSC1_BASE + 0x008C)
+#define SDMRTMPMSKA (SBSC1_BASE + 0x0094)
+#define SDGENCNTA (SBSC1_BASE + 0x009C)
+#define SDDRVCR0A (SBSC1_BASE + 0x00B4)
+#define DLLCNT0A (SBSC1_BASE + 0x0354)
+
+#define SDMRA1 (0xFE500000)
+#define SDMRA2 (0xFE5C0000)
+#define SDMRA3 (0xFE504000)
+
+#define SBSC2_BASE (0xFB400000)
+#define SDCR0B (SBSC2_BASE + 0x0008)
+#define SDCR1B (SBSC2_BASE + 0x000C)
+#define SDPCRB (SBSC2_BASE + 0x0010)
+#define SDCR0SB (SBSC2_BASE + 0x0018)
+#define SDCR1SB (SBSC2_BASE + 0x001C)
+#define RTCSRB (SBSC2_BASE + 0x0020)
+#define RTCORB (SBSC2_BASE + 0x0028)
+#define RTCORHB (SBSC2_BASE + 0x002C)
+#define SDWCRC0B (SBSC2_BASE + 0x0040)
+#define SDWCRC1B (SBSC2_BASE + 0x0044)
+#define SDWCR00B (SBSC2_BASE + 0x0048)
+#define SDWCR01B (SBSC2_BASE + 0x004C)
+#define SDWCR10B (SBSC2_BASE + 0x0050)
+#define SDWCR11B (SBSC2_BASE + 0x0054)
+#define SDPDCR0B (SBSC2_BASE + 0x0058)
+#define SDWCR2B (SBSC2_BASE + 0x0060)
+#define SDWCRC2B (SBSC2_BASE + 0x0064)
+#define ZQCCRB (SBSC2_BASE + 0x0068)
+#define SDMRACR0B (SBSC2_BASE + 0x0084)
+#define SDMRTMPCRB (SBSC2_BASE + 0x008C)
+#define SDMRTMPMSKB (SBSC2_BASE + 0x0094)
+#define SDGENCNTB (SBSC2_BASE + 0x009C)
+#define DPHYCNT0B (SBSC2_BASE + 0x00A0)
+#define DPHYCNT1B (SBSC2_BASE + 0x00A4)
+#define DPHYCNT2B (SBSC2_BASE + 0x00A8)
+#define SDDRVCR0B (SBSC2_BASE + 0x00B4)
+#define DLLCNT0B (SBSC2_BASE + 0x0354)
+
+#define SDMRB1 (0xFB500000)
+#define SDMRB2 (0xFB5C0000)
+#define SDMRB3 (0xFB504000)
+
+#define CPG_BASE (0xE6150000)
+#define FRQCRA (CPG_BASE + 0x0000)
+#define FRQCRB (CPG_BASE + 0x0004)
+#define FRQCRD (CPG_BASE + 0x00E4)
+#define VCLKCR1 (CPG_BASE + 0x0008)
+#define VCLKCR2 (CPG_BASE + 0x000C)
+#define VCLKCR3 (CPG_BASE + 0x001C)
+#define ZBCKCR (CPG_BASE + 0x0010)
+#define FLCKCR (CPG_BASE + 0x0014)
+#define SD0CKCR (CPG_BASE + 0x0074)
+#define SD1CKCR (CPG_BASE + 0x0078)
+#define SD2CKCR (CPG_BASE + 0x007C)
+#define FSIACKCR (CPG_BASE + 0x0018)
+#define SUBCKCR (CPG_BASE + 0x0080)
+#define SPUACKCR (CPG_BASE + 0x0084)
+#define SPUVCKCR (CPG_BASE + 0x0094)
+#define MSUCKCR (CPG_BASE + 0x0088)
+#define HSICKCR (CPG_BASE + 0x008C)
+#define FSIBCKCR (CPG_BASE + 0x0090)
+#define MFCK1CR (CPG_BASE + 0x0098)
+#define MFCK2CR (CPG_BASE + 0x009C)
+#define DSITCKCR (CPG_BASE + 0x0060)
+#define DSI0PCKCR (CPG_BASE + 0x0064)
+#define DSI1PCKCR (CPG_BASE + 0x0068)
+#define DSI0PHYCR (CPG_BASE + 0x006C)
+#define DVFSCR3 (CPG_BASE + 0x0174)
+#define DVFSCR4 (CPG_BASE + 0x0178)
+#define DVFSCR5 (CPG_BASE + 0x017C)
+#define MPMODE (CPG_BASE + 0x00CC)
+
+#define PLLECR (CPG_BASE + 0x00D0)
+#define PLL0CR (CPG_BASE + 0x00D8)
+#define PLL1CR (CPG_BASE + 0x0028)
+#define PLL2CR (CPG_BASE + 0x002C)
+#define PLL3CR (CPG_BASE + 0x00DC)
+#define PLL0STPCR (CPG_BASE + 0x00F0)
+#define PLL1STPCR (CPG_BASE + 0x00C8)
+#define PLL2STPCR (CPG_BASE + 0x00F8)
+#define PLL3STPCR (CPG_BASE + 0x00FC)
+#define RMSTPCR0 (CPG_BASE + 0x0110)
+#define RMSTPCR1 (CPG_BASE + 0x0114)
+#define RMSTPCR2 (CPG_BASE + 0x0118)
+#define RMSTPCR3 (CPG_BASE + 0x011C)
+#define RMSTPCR4 (CPG_BASE + 0x0120)
+#define RMSTPCR5 (CPG_BASE + 0x0124)
+#define SMSTPCR0 (CPG_BASE + 0x0130)
+#define SMSTPCR2 (CPG_BASE + 0x0138)
+#define SMSTPCR3 (CPG_BASE + 0x013C)
+#define CPGXXCR4 (CPG_BASE + 0x0150)
+#define SRCR0 (CPG_BASE + 0x80A0)
+#define SRCR2 (CPG_BASE + 0x80B0)
+#define SRCR3 (CPG_BASE + 0x80A8)
+#define VREFCR (CPG_BASE + 0x00EC)
+#define PCLKCR (CPG_BASE + 0x1020)
+
+#define PORT32CR (0xE6051020)
+#define PORT33CR (0xE6051021)
+#define PORT34CR (0xE6051022)
+#define PORT35CR (0xE6051023)
+
+LIST "DRAM initialization code:"
+
+EW RWTCSRA0, 0xA507
+
+ED_AND LIFEC_SEC_SRC, 0xFFFF7FFF
+
+ED_AND SMSTPCR3,0xFFFF7FFF
+ED_AND SRCR3, 0xFFFF7FFF
+ED_AND SMSTPCR2,0xFFFBFFFF
+ED_AND SRCR2, 0xFFFBFFFF
+ED PLLECR, 0x00000000
+
+WAIT_MASK PLLECR, 0x00000F00, 0x00000000
+WAIT_MASK FRQCRB, 0x80000000, 0x00000000
+
+ED PLL0CR, 0x2D000000
+ED PLL1CR, 0x17100000
+ED FRQCRB, 0x96235880
+WAIT_MASK FRQCRB, 0x80000000, 0x00000000
+
+ED FLCKCR, 0x0000000B
+ED_AND SMSTPCR0, 0xFFFFFFFD
+
+ED_AND SRCR0, 0xFFFFFFFD
+ED 0xE6001628, 0x514
+ED 0xE6001648, 0x514
+ED 0xE6001658, 0x514
+ED 0xE6001678, 0x514
+
+ED DVFSCR4, 0x00092000
+ED DVFSCR5, 0x000000DC
+ED PLLECR, 0x00000000
+WAIT_MASK PLLECR, 0x00000F00, 0x00000000
+
+ED FRQCRA, 0x0012453C
+ED FRQCRB, 0x80431350
+WAIT_MASK FRQCRB, 0x80000000, 0x00000000
+ED FRQCRD, 0x00000B0B
+WAIT_MASK FRQCRD, 0x80000000, 0x00000000
+
+ED PCLKCR, 0x00000003
+ED VCLKCR1, 0x0000012F
+ED VCLKCR2, 0x00000119
+ED VCLKCR3, 0x00000119
+ED ZBCKCR, 0x00000002
+ED FLCKCR, 0x00000005
+ED SD0CKCR, 0x00000080
+ED SD1CKCR, 0x00000080
+ED SD2CKCR, 0x00000080
+ED FSIACKCR, 0x0000003F
+ED FSIBCKCR, 0x0000003F
+ED SUBCKCR, 0x00000080
+ED SPUACKCR, 0x0000000B
+ED SPUVCKCR, 0x0000000B
+ED MSUCKCR, 0x0000013F
+ED HSICKCR, 0x00000080
+ED MFCK1CR, 0x0000003F
+ED MFCK2CR, 0x0000003F
+ED DSITCKCR, 0x00000107
+ED DSI0PCKCR, 0x00000313
+ED DSI1PCKCR, 0x0000130D
+ED DSI0PHYCR, 0x2A800E0E
+ED PLL0CR, 0x1E000000
+ED PLL0CR, 0x2D000000
+ED PLL1CR, 0x17100000
+ED PLL2CR, 0x27000080
+ED PLL3CR, 0x1D000000
+ED PLL0STPCR, 0x00080000
+ED PLL1STPCR, 0x000120C0
+ED PLL2STPCR, 0x00012000
+ED PLL3STPCR, 0x00000030
+ED PLLECR, 0x0000000B
+WAIT_MASK PLLECR, 0x00000B00, 0x00000B00
+
+ED DVFSCR3, 0x000120F0
+ED MPMODE, 0x00000020
+ED VREFCR, 0x0000028A
+ED RMSTPCR0, 0xE4628087
+ED RMSTPCR1, 0xFFFFFFFF
+ED RMSTPCR2, 0x53FFFFFF
+ED RMSTPCR3, 0xFFFFFFFF
+ED RMSTPCR4, 0x00800D3D
+ED RMSTPCR5, 0xFFFFF3FF
+ED SMSTPCR2, 0x00000000
+ED SRCR2, 0x00040000
+ED_AND PLLECR, 0xFFFFFFF7
+WAIT_MASK PLLECR, 0x00000800, 0x00000000
+
+LIST "set SBSC operational"
+ED HPBCTRL6, 0x00000001
+WAIT_MASK HPBCTRL6, 0x00000001, 0x00000001
+
+LIST "set SBSC operating frequency"
+ED FRQCRD, 0x00001414
+WAIT_MASK FRQCRD, 0x80000000, 0x00000000
+ED PLL3CR, 0x1D000000
+ED_OR PLLECR, 0x00000008
+WAIT_MASK PLLECR, 0x00000800, 0x00000800
+
+LIST "enable DLL oscillation in DDRPHY"
+ED_OR DLLCNT0A, 0x00000002
+
+LIST "wait >= 100 ns"
+ED SDGENCNTA, 0x00000005
+WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
+
+LIST "target LPDDR2 device settings"
+ED SDCR0A, 0xACC90159
+ED SDCR1A, 0x00010059
+ED SDWCRC0A, 0x50874114
+ED SDWCRC1A, 0x33199B37
+ED SDWCRC2A, 0x008F2313
+ED SDWCR00A, 0x31020707
+ED SDWCR01A, 0x0017040A
+ED SDWCR10A, 0x31020707
+ED SDWCR11A, 0x0017040A
+
+ED SDDRVCR0A, 0x055557ff
+
+ED SDWCR2A, 0x30000000
+
+LIST "drive CKE high"
+ED_OR SDPCRA, 0x00000080
+WAIT_MASK SDPCRA, 0x00000080, 0x00000080
+
+LIST "wait >= 200 us"
+ED SDGENCNTA, 0x00002710
+WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
+
+LIST "issue reset command to LPDDR2 device"
+ED SDMRACR0A, 0x0000003F
+ED SDMRA1, 0x00000000
+
+LIST "wait >= 10 (or 1) us (docs inconsistent)"
+ED SDGENCNTA, 0x000001F4
+WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
+
+LIST "MRW ZS initialization calibration command"
+ED SDMRACR0A, 0x0000FF0A
+ED SDMRA3, 0x00000000
+
+LIST "wait >= 1 us"
+ED SDGENCNTA, 0x00000032
+WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
+
+LIST "specify operating mode in LPDDR2"
+ED SDMRACR0A, 0x00002201
+ED SDMRA1, 0x00000000
+ED SDMRACR0A, 0x00000402
+ED SDMRA1, 0x00000000
+ED SDMRACR0A, 0x00000203
+ED SDMRA1, 0x00000000
+
+LIST "initialize DDR interface"
+ED SDMRA2, 0x00000000
+
+LIST "temperature sensor control"
+ED SDMRTMPCRA, 0x88800004
+ED SDMRTMPMSKA,0x00000004
+
+LIST "auto-refreshing control"
+ED RTCORA, 0xA55A0032
+ED RTCORHA, 0xA55A000C
+ED RTCSRA, 0xA55A2048
+
+ED_OR SDCR0A, 0x00000800
+ED_OR SDCR1A, 0x00000400
+
+LIST "auto ZQ calibration control"
+ED ZQCCRA, 0xFFF20000
+
+ED_OR DLLCNT0B, 0x00000002
+ED SDGENCNTB, 0x00000005
+WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
+
+ED SDCR0B, 0xACC90159
+ED SDCR1B, 0x00010059
+ED SDWCRC0B, 0x50874114
+ED SDWCRC1B, 0x33199B37
+ED SDWCRC2B, 0x008F2313
+ED SDWCR00B, 0x31020707
+ED SDWCR01B, 0x0017040A
+ED SDWCR10B, 0x31020707
+ED SDWCR11B, 0x0017040A
+ED SDDRVCR0B, 0x055557ff
+ED SDWCR2B, 0x30000000
+ED_OR SDPCRB, 0x00000080
+WAIT_MASK SDPCRB, 0x00000080, 0x00000080
+
+ED SDGENCNTB, 0x00002710
+WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
+ED SDMRACR0B, 0x0000003F
+
+LIST "upstream u-boot writes to SDMRA1A for both SBSC 1 and 2, which does"
+LIST "not seem to make a lot of sense..."
+ED SDMRB1, 0x00000000
+
+ED SDGENCNTB, 0x000001F4
+WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
+
+ED SDMRACR0B, 0x0000FF0A
+ED SDMRB3, 0x00000000
+ED SDGENCNTB, 0x00000032
+WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
+
+ED SDMRACR0B, 0x00002201
+ED SDMRB1, 0x00000000
+ED SDMRACR0B, 0x00000402
+ED SDMRB1, 0x00000000
+ED SDMRACR0B, 0x00000203
+ED SDMRB1, 0x00000000
+ED SDMRB2, 0x00000000
+ED SDMRTMPCRB, 0x88800004
+ED SDMRTMPMSKB, 0x00000004
+ED RTCORB, 0xA55A0032
+ED RTCORHB, 0xA55A000C
+ED RTCSRB, 0xA55A2048
+ED_OR SDCR0B, 0x00000800
+ED_OR SDCR1B, 0x00000400
+ED ZQCCRB, 0xFFF20000
+ED_OR SDPDCR0B, 0x00030000
+ED DPHYCNT1B, 0xA5390000
+ED DPHYCNT0B, 0x00001200
+ED DPHYCNT1B, 0x07CE0000
+ED DPHYCNT0B, 0x00001247
+WAIT_MASK DPHYCNT2B, 0xFFFFFFFF, 0x07CE0000
+
+ED_AND SDPDCR0B, 0xFFFCFFFF
+
+ED FRQCRD, 0x00000B0B
+WAIT_MASK FRQCRD, 0x80000000, 0x00000000
+
+ED CPGXXCR4, 0xfffffffc
+
+LIST "Setup SCIF4 / workaround"
+EB PORT32CR, 0x12
+EB PORT33CR, 0x22
+EB PORT34CR, 0x12
+EB PORT35CR, 0x22
+
+EW 0xE6C80000, 0
+EB 0xE6C80004, 0x19
+EW 0xE6C80008, 0x0030
+EW 0xE6C80018, 0
+EW 0xE6C80030, 0x0014
+
+LIST "Magic to avoid hangs and corruption on DRAM writes."
+
+LIST "It has been observed that the system would most often hang while"
+LIST "decompressing the kernel, and if it didn't it would always write"
+LIST "a corrupt image to DRAM."
+LIST "This problem does not occur in u-boot, and the reason is that"
+LIST "u-boot performs an additional cache invalidation after setting up"
+LIST "the DRAM controller. Such an invalidation should not be necessary at"
+LIST "this point, and attempts at removing parts of the routine to arrive"
+LIST "at the minimal snippet of code necessary to avoid the DRAM stability"
+LIST "problem yielded the following:"
+
+MRC p15, 0, r0, c1, c0, 0
+MCR p15, 0, r0, c1, c0, 0
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index c3c4669..727cc78 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -12,6 +12,9 @@
#ifdef CONFIG_MACH_MACKEREL
#define MEMORY_START 0x40000000
#include "mach/head-mackerel.txt"
+#elif defined(CONFIG_MACH_KZM9G) || defined(CONFIG_MACH_KZM9G_REFERENCE)
+#define MEMORY_START 0x43000000
+#include "mach/head-kzm9g.txt"
#else
#error "unsupported board."
#endif
diff --git a/arch/arm/mach-shmobile/include/mach/zboot_macros.h b/arch/arm/mach-shmobile/include/mach/zboot_macros.h
index aa6111f..14fd3d5 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot_macros.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot_macros.h
@@ -62,4 +62,47 @@
2 :
.endm
+/* loop until a given value has been read (with mask) */
+.macro WAIT_MASK, addr, data, cmp
+ LDR r0, 2f
+ LDR r1, 3f
+ LDR r2, 4f
+1:
+ LDR r3, [r0, #0]
+ AND r3, r1, r3
+ CMP r2, r3
+ BNE 1b
+ B 5f
+2: .long \addr
+3: .long \data
+4: .long \cmp
+5:
+.endm
+
+/* read 32-bit value from addr, "or" an immediate and write back */
+.macro ED_OR, addr, data
+ LDR r4, 1f
+ LDR r5, 2f
+ LDR r6, [r4]
+ ORR r5, r6, r5
+ STR r5, [r4]
+ B 3f
+1: .long \addr
+2: .long \data
+3:
+.endm
+
+/* read 32-bit value from addr, "and" an immediate and write back */
+.macro ED_AND, addr, data
+ LDR r4, 1f
+ LDR r5, 2f
+ LDR r6, [r4]
+ AND r5, r6, r5
+ STR r5, [r4]
+ B 3f
+1: .long \addr
+2: .long \data
+3:
+.endm
+
#endif /* __ZBOOT_MACRO_H */
--
1.8.5.2
^ permalink raw reply related
* [PATCH 05/21] ARM: shmobile: koelsch: Conditionally select MICREL_PHY for Multiplatform
From: Simon Horman @ 2014-02-06 6:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
The koelsch board uses has an SH ethernet controller which uses a Micrel
phy. Select MICREL_PHY for koelsch if SH_ETH is enabled to make use of the
Micrel-specific phy driver rather than relying on the generic phy driver.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index a127252..958ccf3d 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -45,6 +45,7 @@ config MACH_GENMAI
config MACH_KOELSCH
bool "Koelsch board"
depends on ARCH_R8A7791
+ select MICREL_PHY if SH_ETH
config MACH_KZM9D
bool "KZM9D board"
--
1.8.5.2
^ permalink raw reply related
* [PATCH 04/21] ARM: shmobile: bockw: add USB Func DMAEngine support
From: Simon Horman @ 2014-02-06 6:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/board-bockw.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 24b4161..684a529 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -168,6 +168,8 @@ static struct renesas_usbhs_platform_info usbhs_info __initdata = {
},
.driver_param = {
.buswait_bwait = 4,
+ .d0_tx_id = HPBDMA_SLAVE_USBFUNC_TX,
+ .d1_rx_id = HPBDMA_SLAVE_USBFUNC_RX,
},
};
--
1.8.5.2
^ permalink raw reply related
* [PATCH 03/21] ARM: shmobile: bockw: use HPBIF DMAEngine for sound
From: Simon Horman @ 2014-02-06 6:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
R-Car sound driver is supporting Mem <-> SRU <-> SSI
transfer via DMAEngine.
The sound will be less noise if it uses SRU path
since it has FIFO.
This patch supports it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/board-bockw.c | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index bdb78a7..24b4161 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -332,16 +332,24 @@ static struct rsnd_ssi_platform_info rsnd_ssi[] = {
RSND_SSI_UNUSED, /* SSI 0 */
RSND_SSI_UNUSED, /* SSI 1 */
RSND_SSI_UNUSED, /* SSI 2 */
- RSND_SSI_SET(1, HPBDMA_SLAVE_SSI3_TX, gic_iid(0x85), RSND_SSI_PLAY),
- RSND_SSI_SET(2, HPBDMA_SLAVE_SSI4_RX, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE),
- RSND_SSI_SET(0, HPBDMA_SLAVE_SSI5_TX, gic_iid(0x86), RSND_SSI_PLAY),
- RSND_SSI_SET(0, HPBDMA_SLAVE_SSI6_RX, gic_iid(0x86), 0),
- RSND_SSI_SET(3, HPBDMA_SLAVE_SSI7_TX, gic_iid(0x86), RSND_SSI_PLAY),
- RSND_SSI_SET(4, HPBDMA_SLAVE_SSI8_RX, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE),
+ RSND_SSI_SET(1, HPBDMA_SLAVE_HPBIF3_TX, gic_iid(0x85), RSND_SSI_PLAY),
+ RSND_SSI_SET(2, HPBDMA_SLAVE_HPBIF4_RX, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE),
+ RSND_SSI_SET(0, HPBDMA_SLAVE_HPBIF5_TX, gic_iid(0x86), RSND_SSI_PLAY),
+ RSND_SSI_SET(0, HPBDMA_SLAVE_HPBIF6_RX, gic_iid(0x86), 0),
+ RSND_SSI_SET(3, HPBDMA_SLAVE_HPBIF7_TX, gic_iid(0x86), RSND_SSI_PLAY),
+ RSND_SSI_SET(4, HPBDMA_SLAVE_HPBIF8_RX, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE),
};
static struct rsnd_scu_platform_info rsnd_scu[9] = {
- /* no member at this point */
+ { .flags = 0, }, /* SRU 0 */
+ { .flags = 0, }, /* SRU 1 */
+ { .flags = 0, }, /* SRU 2 */
+ { .flags = RSND_SCU_USE_HPBIF, },
+ { .flags = RSND_SCU_USE_HPBIF, },
+ { .flags = RSND_SCU_USE_HPBIF, },
+ { .flags = RSND_SCU_USE_HPBIF, },
+ { .flags = RSND_SCU_USE_HPBIF, },
+ { .flags = RSND_SCU_USE_HPBIF, },
};
enum {
--
1.8.5.2
^ permalink raw reply related
* [PATCH 02/21] ARM: shmobile: bockw: use SSI DMAEngine for sound
From: Simon Horman @ 2014-02-06 6:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
R-Car sound driver is supporting Mem <-> SSI
direct transfer via DMAEngine.
Current HPB-DMA is using double plane transfer,
but the sound may have noise since SSI doesn't have FIFO.
This patch supports it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/board-bockw.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index c475220..bdb78a7 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -332,12 +332,12 @@ static struct rsnd_ssi_platform_info rsnd_ssi[] = {
RSND_SSI_UNUSED, /* SSI 0 */
RSND_SSI_UNUSED, /* SSI 1 */
RSND_SSI_UNUSED, /* SSI 2 */
- RSND_SSI_SET(1, 0, gic_iid(0x85), RSND_SSI_PLAY),
- RSND_SSI_SET(2, 0, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE),
- RSND_SSI_SET(0, 0, gic_iid(0x86), RSND_SSI_PLAY),
- RSND_SSI_SET(0, 0, gic_iid(0x86), 0),
- RSND_SSI_SET(3, 0, gic_iid(0x86), RSND_SSI_PLAY),
- RSND_SSI_SET(4, 0, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE),
+ RSND_SSI_SET(1, HPBDMA_SLAVE_SSI3_TX, gic_iid(0x85), RSND_SSI_PLAY),
+ RSND_SSI_SET(2, HPBDMA_SLAVE_SSI4_RX, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE),
+ RSND_SSI_SET(0, HPBDMA_SLAVE_SSI5_TX, gic_iid(0x86), RSND_SSI_PLAY),
+ RSND_SSI_SET(0, HPBDMA_SLAVE_SSI6_RX, gic_iid(0x86), 0),
+ RSND_SSI_SET(3, HPBDMA_SLAVE_SSI7_TX, gic_iid(0x86), RSND_SSI_PLAY),
+ RSND_SSI_SET(4, HPBDMA_SLAVE_SSI8_RX, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE),
};
static struct rsnd_scu_platform_info rsnd_scu[9] = {
--
1.8.5.2
^ permalink raw reply related
* [PATCH 01/21] ARM: shmobile: Lager: conditionally select CONFIG_MICREL_PHY
From: Simon Horman @ 2014-02-06 6:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391665225.git.horms+renesas@verge.net.au>
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Now that support for KSZ8041RNLI is added to the Micrel PHY driver and we intend
to support PHY IRQs on the Lager board, we have to enable the Micrel driver.
Do this by selecting CONFIG_MICREL_PHY for Lager if CONFIG_SH_ETH is enabled.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 3386406..a127252 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -54,6 +54,7 @@ config MACH_KZM9D
config MACH_LAGER
bool "Lager board"
depends on ARCH_R8A7790
+ select MICREL_PHY if SH_ETH
comment "Renesas ARM SoCs System Configuration"
endif
@@ -261,6 +262,7 @@ config MACH_LAGER
bool "Lager board"
depends on ARCH_R8A7790
select USE_OF
+ select MICREL_PHY if SH_ETH
config MACH_KOELSCH
bool "Koelsch board"
--
1.8.5.2
^ permalink raw reply related
* [GIT PULL 00/21] Renesas ARM based SoC Board Updates for v3.15
From: Simon Horman @ 2014-02-06 6:17 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
please consider these Renesas ARM based SoC board updates for v3.15.
The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:
Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-boards-for-v3.15
for you to fetch changes up to 235cda29e4d5047622ff9b82b1f0b4cb6cf95f6c:
ARM: shmobile: Remove Lager USBHS UDC ifdefs (2014-02-04 14:28:33 +0900)
----------------------------------------------------------------
Renesas ARM based SoC Board Updates for v3.15
* r8a7791 (R-Car M2) based Koelsch board
- Fix error return code check from clk_get()
- Add SATA0 support
- Conditionally select MICREL_PHY for Multiplatform
* r8a7790 (R-Car H2) based Lager board
- Add USBHS support
- Fix error return code check from clk_get()
- Add SATA support
- Make spi_flash_data const
- Add VIN1 SoC camera support
- Conditionally select CONFIG_MICREL_PHY
* r8a7778 (R-Car M1) based Bock-W board
- Add USB Func DMAEngine support
- Use HPBIF DMAEngine for sound
- Use SSI DMAEngine for sound
* emev2 (Emma Mobile EV2) based kzm9d board
- Use common clock framework
* r8a773a0 (SH-Mobile AG5) based kzm9g board
- Add zboot support
* Many boards
- Conditionally select SMSC_PHY
----------------------------------------------------------------
Ben Dooks (2):
ARM: shmobile: lager: fix error return code check from clk_get()
ARM: shmobile: koelsch: fix error return code check from clk_get()
Geert Uytterhoeven (1):
ARM: shmobile: lager: Make spi_flash_data const
Kuninori Morimoto (3):
ARM: shmobile: bockw: use SSI DMAEngine for sound
ARM: shmobile: bockw: use HPBIF DMAEngine for sound
ARM: shmobile: bockw: add USB Func DMAEngine support
Magnus Damm (1):
ARM: shmobile: Remove Lager USBHS UDC ifdefs
Sergei Shtylyov (1):
ARM: shmobile: Lager: conditionally select CONFIG_MICREL_PHY
Simon Horman (7):
ARM: shmobile: koelsch: Conditionally select MICREL_PHY for Multiplatform
ARM: shmobile: ape6evm: Conditionally select SMSC_PHY
ARM: shmobile: armadillo800eva: Conditionally select SMSC_PHY
ARM: shmobile: bockw: Sort Kconfig node's selections
ARM: shmobile: kzm9d: Conditionally select SMSC_PHY
ARM: shmobile: mackerel: Conditionally select SMSC_PHY
ARM: shmobile: marzen: Conditionally select SMSC_PHY
Takashi Yoshii (1):
ARM: shmobile: kzm9d: Use common clock framework
Ulrich Hecht (1):
ARM: mach-shmobile: kzm9g: add zboot support
Valentine Barshak (4):
ARM: shmobile: lager: Add VIN1 SoC camera support
ARM: shmobile: lager: Add SATA support
ARM: shmobile: koelsch: Add SATA0 support
ARM: shmobile: lager: Add USBHS support
arch/arm/mach-shmobile/Kconfig | 15 +-
arch/arm/mach-shmobile/board-bockw.c | 24 +-
arch/arm/mach-shmobile/board-koelsch-reference.c | 4 +-
arch/arm/mach-shmobile/board-koelsch.c | 17 +
arch/arm/mach-shmobile/board-kzm9d-reference.c | 5 +-
arch/arm/mach-shmobile/board-lager-reference.c | 4 +-
arch/arm/mach-shmobile/board-lager.c | 229 +++++++++++-
arch/arm/mach-shmobile/include/mach/head-kzm9g.txt | 410 +++++++++++++++++++++
arch/arm/mach-shmobile/include/mach/zboot.h | 3 +
arch/arm/mach-shmobile/include/mach/zboot_macros.h | 43 +++
10 files changed, 737 insertions(+), 17 deletions(-)
create mode 100644 arch/arm/mach-shmobile/include/mach/head-kzm9g.txt
^ permalink raw reply
* [PATCH] ARM: shmobile: wait for MSTP clock status to toggle, when enabling it
From: Simon Horman @ 2014-02-06 6:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391651474.git.horms+renesas@verge.net.au>
From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
On r-/sh-mobile SoCs MSTP clocks are used by the runtime PM to dynamically
enable and disable peripheral clocks. To make sure the clock has really
started we have to read back its status register until it confirms success.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/sh/clk/cpg.c | 38 ++++++++++++++++++++++++++++++++++++++
include/linux/sh_clk.h | 19 ++++++++++++-------
2 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 1ebe67c..7442bc1 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -36,9 +36,47 @@ static void sh_clk_write(int value, struct clk *clk)
iowrite32(value, clk->mapped_reg);
}
+static unsigned int r8(const void __iomem *addr)
+{
+ return ioread8(addr);
+}
+
+static unsigned int r16(const void __iomem *addr)
+{
+ return ioread16(addr);
+}
+
+static unsigned int r32(const void __iomem *addr)
+{
+ return ioread32(addr);
+}
+
static int sh_clk_mstp_enable(struct clk *clk)
{
sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);
+ if (clk->status_reg) {
+ unsigned int (*read)(const void __iomem *addr);
+ int i;
+ void __iomem *mapped_status = (phys_addr_t)clk->status_reg -
+ (phys_addr_t)clk->enable_reg + clk->mapped_reg;
+
+ if (clk->flags & CLK_ENABLE_REG_8BIT)
+ read = r8;
+ else if (clk->flags & CLK_ENABLE_REG_16BIT)
+ read = r16;
+ else
+ read = r32;
+
+ for (i = 1000;
+ (read(mapped_status) & (1 << clk->enable_bit)) && i;
+ i--)
+ cpu_relax();
+ if (!i) {
+ pr_err("cpg: failed to enable %p[%d]\n",
+ clk->enable_reg, clk->enable_bit);
+ return -ETIMEDOUT;
+ }
+ }
return 0;
}
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
index 60c7239..1f208b2 100644
--- a/include/linux/sh_clk.h
+++ b/include/linux/sh_clk.h
@@ -52,6 +52,7 @@ struct clk {
unsigned long flags;
void __iomem *enable_reg;
+ void __iomem *status_reg;
unsigned int enable_bit;
void __iomem *mapped_reg;
@@ -116,22 +117,26 @@ long clk_round_parent(struct clk *clk, unsigned long target,
unsigned long *best_freq, unsigned long *parent_freq,
unsigned int div_min, unsigned int div_max);
-#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \
+#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \
{ \
.parent = _parent, \
.enable_reg = (void __iomem *)_enable_reg, \
.enable_bit = _enable_bit, \
+ .status_reg = _status_reg, \
.flags = _flags, \
}
-#define SH_CLK_MSTP32(_p, _r, _b, _f) \
- SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT)
+#define SH_CLK_MSTP32(_p, _r, _b, _f) \
+ SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT)
-#define SH_CLK_MSTP16(_p, _r, _b, _f) \
- SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT)
+#define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \
+ SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT)
-#define SH_CLK_MSTP8(_p, _r, _b, _f) \
- SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT)
+#define SH_CLK_MSTP16(_p, _r, _b, _f) \
+ SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
+
+#define SH_CLK_MSTP8(_p, _r, _b, _f) \
+ SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT)
int sh_clk_mstp_register(struct clk *clks, int nr);
--
1.8.5.2
^ permalink raw reply related
* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
From: Pratyush Anand @ 2014-02-06 6:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F32549.5010303@ti.com>
Hi Kishon,
On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> > skeleton support for the same.
> >
> > Currently phy ops are returning -EINVAL. They can be elaborated
> > depending on the SOC being supported in future.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Tested-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: spear-devel at list.st.com
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: devicetree at vger.kernel.org
> > Cc: linux-kernel at vger.kernel.org
> > ---
> > .../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++
> > drivers/phy/Kconfig | 6 +
> > drivers/phy/Makefile | 1 +
> > drivers/phy/phy-miphy40lp.c | 174 +++++++++++++++++++++
> > 4 files changed, 193 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > create mode 100644 drivers/phy/phy-miphy40lp.c
> >
> > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > new file mode 100644
> > index 0000000..d0c7096
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > @@ -0,0 +1,12 @@
> > +Required properties:
> > +- compatible : should be "st,miphy40lp-phy"
> > + Other supported soc specific compatible:
> > + "st,spear1310-miphy"
> > + "st,spear1340-miphy"
> > +- reg : offset and length of the PHY register set.
> > +- misc: phandle for the syscon node to access misc registers
> > +- phy-id: Instance id of the phy.
> > +- #phy-cells : from the generic PHY bindings, must be 1.
> > + - 1st cell: phandle to the phy node.
> > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > + and 2 for Super Speed USB.
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index afa2354..2f58993 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
> > help
> > Enable this to support the Broadcom Kona USB 2.0 PHY.
> >
> > +config PHY_ST_MIPHY40LP
> > + tristate "ST MIPHY 40LP driver"
> > + help
> > + Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> > + select GENERIC_PHY
> > +
> > endmenu
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index b57c253..c061091 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
> > obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
> > obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
> > obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
> > +obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > new file mode 100644
> > index 0000000..d478c14
> > --- /dev/null
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -0,0 +1,174 @@
> > +/*
> > + * ST MiPHY-40LP PHY driver
> > + *
> > + * Copyright (C) 2014 ST Microelectronics
> > + * Pratyush Anand <pratyush.anand@st.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/regmap.h>
> > +
> > +enum phy_mode {
> > + SATA,
> > + PCIE,
> > + SS_USB,
> > +};
> > +
> > +struct st_miphy40lp_priv {
> > + /* regmap for any soc specific misc registers */
> > + struct regmap *misc;
> > + /* phy struct pointer */
> > + struct phy *phy;
> > + /* device node pointer */
> > + struct device_node *np;
> > + /* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> > + enum phy_mode mode;
> > + /* instance id of this phy */
> > + u32 id;
> > +};
> > +
> > +static int miphy40lp_init(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_exit(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_off(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_on(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id st_miphy40lp_of_match[] = {
> > + { .compatible = "st,miphy40lp-phy" },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > +
> > +static struct phy_ops st_miphy40lp_ops = {
> > + .init = miphy40lp_init,
> > + .exit = miphy40lp_exit,
> > + .power_off = miphy40lp_power_off,
> > + .power_on = miphy40lp_power_on,
> > + .owner = THIS_MODULE,
>
> Would prefer to either align all the fields or align none. Here only owner is
> aligned.
ok.
> > +};
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int miphy40lp_suspend(struct device *dev)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_resume(struct device *dev)
> > +{
> > + return -EINVAL;
> > +}
> > +#endif
> > +
> > +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> > + miphy40lp_resume);
> > +
> > +static struct phy *st_miphy40lp_xlate(struct device *dev,
> > + struct of_phandle_args *args)
> > +{
> > + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > + if (args->args_count < 1) {
> > + dev_err(dev, "DT did not pass correct no of args\n");
> > + return NULL;
> > + }
> > +
> > + phypriv->mode = args->args[0];
> > +
> > + return phypriv->phy;
> > +}
> > +
> > +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct st_miphy40lp_priv *phypriv;
> > + struct phy_provider *phy_provider;
> > +
> > + phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> > + if (!phypriv) {
> > + dev_err(dev, "can't alloc miphy40lp private date memory\n");
> > + return -ENOMEM;
> > + }
> > +
> > + phypriv->np = dev->of_node;
> > +
> > + phypriv->misc =
> > + syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> > + if (IS_ERR(phypriv->misc)) {
> > + dev_err(dev, "failed to find misc regmap\n");
> > + return PTR_ERR(phypriv->misc);
> > + }
> > +
> > + if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> > + dev_err(dev, "failed to find phy id\n");
> > + return -EINVAL;
> > + }
> Do we really need this phy id? How is it being used?
Yes , it is being used by patch 6/8.
>
> > +
> > + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> > + if (IS_ERR(phy_provider)) {
> > + dev_err(dev, "failed to register phy provider\n");
> > + return PTR_ERR(phy_provider);
> > + }
>
> phy_provider_register should be the last step in registering the PHY. Or your
> PHY call backs can be called before you create the PHY. Btw in your case you
But every one else like phy-exynos-mipi-video or phy-omap-usb2 or any
other did it same way. First phy_provider_register and then
phy_create.
> should call dev_set_drvdata before doing phy_provider_register.
yes, I need to correct it.
> > +
> > + phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> > + if (IS_ERR(phypriv->phy)) {
> > + dev_err(dev, "failed to create SATA PCIe PHY\n");
> > + return PTR_ERR(phypriv->phy);
> > + }
> > +
> > + dev_set_drvdata(dev, phypriv);
> > + phy_set_drvdata(phypriv->phy, phypriv);
> > +
> > + return 0;
> > +}
> > +
> > +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> > +{
> > + return 0;
> > +}
>
> I think you can remove this empty 'remove' callback.
Yaa.. Can be removed.
Rgds
Pratyush
>
> Thanks
> Kishon
^ permalink raw reply
* [GIT PULL] Renesas CPG update for v3.15
From: Simon Horman @ 2014-02-06 6:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
please consider this Renesas CPG update for v3.15.
The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:
Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-cpg-for-v3.15
for you to fetch changes up to a028c6da34d434e35ba8322568c756ea97ff3c18:
ARM: shmobile: wait for MSTP clock status to toggle, when enabling it (2014-02-04 10:22:39 +0900)
----------------------------------------------------------------
Renesas CPG update for v3.15
* Wait for MSTP clock status to toggle when enabling it
----------------------------------------------------------------
Guennadi Liakhovetski (1):
ARM: shmobile: wait for MSTP clock status to toggle, when enabling it
drivers/sh/clk/cpg.c | 38 ++++++++++++++++++++++++++++++++++++++
include/linux/sh_clk.h | 19 ++++++++++++-------
2 files changed, 50 insertions(+), 7 deletions(-)
^ permalink raw reply
* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
From: Kishon Vijay Abraham I @ 2014-02-06 6:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8596e7596e0dfa9a487c4c2deb325bbdf785e55e.1391661589.git.pratyush.anand@st.com>
Hi,
On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> skeleton support for the same.
>
> Currently phy ops are returning -EINVAL. They can be elaborated
> depending on the SOC being supported in future.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel at list.st.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: devicetree at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org
> ---
> .../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++
> drivers/phy/Kconfig | 6 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-miphy40lp.c | 174 +++++++++++++++++++++
> 4 files changed, 193 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> create mode 100644 drivers/phy/phy-miphy40lp.c
>
> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> new file mode 100644
> index 0000000..d0c7096
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> @@ -0,0 +1,12 @@
> +Required properties:
> +- compatible : should be "st,miphy40lp-phy"
> + Other supported soc specific compatible:
> + "st,spear1310-miphy"
> + "st,spear1340-miphy"
> +- reg : offset and length of the PHY register set.
> +- misc: phandle for the syscon node to access misc registers
> +- phy-id: Instance id of the phy.
> +- #phy-cells : from the generic PHY bindings, must be 1.
> + - 1st cell: phandle to the phy node.
> + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> + and 2 for Super Speed USB.
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index afa2354..2f58993 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
> help
> Enable this to support the Broadcom Kona USB 2.0 PHY.
>
> +config PHY_ST_MIPHY40LP
> + tristate "ST MIPHY 40LP driver"
> + help
> + Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> + select GENERIC_PHY
> +
> endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index b57c253..c061091 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
> obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
> obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
> obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
> +obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> new file mode 100644
> index 0000000..d478c14
> --- /dev/null
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -0,0 +1,174 @@
> +/*
> + * ST MiPHY-40LP PHY driver
> + *
> + * Copyright (C) 2014 ST Microelectronics
> + * Pratyush Anand <pratyush.anand@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +enum phy_mode {
> + SATA,
> + PCIE,
> + SS_USB,
> +};
> +
> +struct st_miphy40lp_priv {
> + /* regmap for any soc specific misc registers */
> + struct regmap *misc;
> + /* phy struct pointer */
> + struct phy *phy;
> + /* device node pointer */
> + struct device_node *np;
> + /* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> + enum phy_mode mode;
> + /* instance id of this phy */
> + u32 id;
> +};
> +
> +static int miphy40lp_init(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_exit(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_power_off(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_power_on(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static const struct of_device_id st_miphy40lp_of_match[] = {
> + { .compatible = "st,miphy40lp-phy" },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> +
> +static struct phy_ops st_miphy40lp_ops = {
> + .init = miphy40lp_init,
> + .exit = miphy40lp_exit,
> + .power_off = miphy40lp_power_off,
> + .power_on = miphy40lp_power_on,
> + .owner = THIS_MODULE,
Would prefer to either align all the fields or align none. Here only owner is
aligned.
> +};
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int miphy40lp_suspend(struct device *dev)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_resume(struct device *dev)
> +{
> + return -EINVAL;
> +}
> +#endif
> +
> +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> + miphy40lp_resume);
> +
> +static struct phy *st_miphy40lp_xlate(struct device *dev,
> + struct of_phandle_args *args)
> +{
> + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> + if (args->args_count < 1) {
> + dev_err(dev, "DT did not pass correct no of args\n");
> + return NULL;
> + }
> +
> + phypriv->mode = args->args[0];
> +
> + return phypriv->phy;
> +}
> +
> +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct st_miphy40lp_priv *phypriv;
> + struct phy_provider *phy_provider;
> +
> + phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> + if (!phypriv) {
> + dev_err(dev, "can't alloc miphy40lp private date memory\n");
> + return -ENOMEM;
> + }
> +
> + phypriv->np = dev->of_node;
> +
> + phypriv->misc =
> + syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> + if (IS_ERR(phypriv->misc)) {
> + dev_err(dev, "failed to find misc regmap\n");
> + return PTR_ERR(phypriv->misc);
> + }
> +
> + if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> + dev_err(dev, "failed to find phy id\n");
> + return -EINVAL;
> + }
Do we really need this phy id? How is it being used?
> +
> + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> + if (IS_ERR(phy_provider)) {
> + dev_err(dev, "failed to register phy provider\n");
> + return PTR_ERR(phy_provider);
> + }
phy_provider_register should be the last step in registering the PHY. Or your
PHY call backs can be called before you create the PHY. Btw in your case you
should call dev_set_drvdata before doing phy_provider_register.
> +
> + phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> + if (IS_ERR(phypriv->phy)) {
> + dev_err(dev, "failed to create SATA PCIe PHY\n");
> + return PTR_ERR(phypriv->phy);
> + }
> +
> + dev_set_drvdata(dev, phypriv);
> + phy_set_drvdata(phypriv->phy, phypriv);
> +
> + return 0;
> +}
> +
> +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
I think you can remove this empty 'remove' callback.
Thanks
Kishon
^ permalink raw reply
* [PATCH] ARM: imx6q: support ptp and rmii clock from pad
From: Shawn Guo @ 2014-02-06 5:53 UTC (permalink / raw)
To: linux-arm-kernel
On imx6qdl, the ENET RMII and PTP clock can come from either internal
ANATOP/CCM or external clock source through pad GPIO_16. But in case
of the external clock source, bit IOMUXC_GPR1[21] needs to be cleared.
The patch adds the support for systems that use an external clock source
and distinguishes above two cases by checking if the PTP clock specified
in device tree is the one coming from the internal ANATOP/CCM.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/clk-imx6q.c | 1 +
arch/arm/mach-imx/mach-imx6q.c | 36 +++++++++++++++++++++++++++++++++++-
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index dd4f1e3..45de2e5 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -437,6 +437,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
+ clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
cpu_is_imx6dl()) {
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index f9cbbf9..d131499b 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -182,16 +182,50 @@ static void __init imx6q_enet_phy_init(void)
static void __init imx6q_1588_init(void)
{
+ struct device_node *np;
+ struct clk *ptp_clk;
+ struct clk *enet_ref;
struct regmap *gpr;
+ u32 clksel;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
+ if (!np) {
+ pr_warn("%s: failed to find fec node\n", __func__);
+ return;
+ }
+
+ ptp_clk = of_clk_get(np, 2);
+ if (IS_ERR(ptp_clk)) {
+ pr_warn("%s: failed to get ptp clock\n", __func__);
+ goto put_node;
+ }
+
+ enet_ref = clk_get_sys(NULL, "enet_ref");
+ if (IS_ERR(enet_ref)) {
+ pr_warn("%s: failed to get enet clock\n", __func__);
+ goto put_ptp_clk;
+ }
+ /*
+ * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
+ * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad
+ * (external OSC), and we need to clear the bit.
+ */
+ clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
+ IMX6Q_GPR1_ENET_CLK_SEL_PAD;
gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
if (!IS_ERR(gpr))
regmap_update_bits(gpr, IOMUXC_GPR1,
IMX6Q_GPR1_ENET_CLK_SEL_MASK,
- IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
+ clksel);
else
pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
+ clk_put(enet_ref);
+put_ptp_clk:
+ clk_put(ptp_clk);
+put_node:
+ of_node_put(np);
}
static void __init imx6q_init_machine(void)
--
1.7.9.5
^ permalink raw reply related
* Freescale FEC packet loss
From: Christian Ege @ 2014-02-06 5:30 UTC (permalink / raw)
To: linux-arm-kernel
> On Sunday, January 26, 2014 at 10:33:33 PM, Ben Hutchings wrote:
> > On Sun, 2014-01-26 at 20:12 +0100, Marek Vasut wrote:
> > > On Sunday, January 26, 2014 at 07:56:30 PM, Ben Hutchings wrote:
> > > > On Wed, 2014-01-22 at 22:55 +0100, Marek Vasut wrote:
> > > > > Hi guys,
> > > > >
> > > > > I am running stock Linux 3.13 on i.MX6Q SabreLite board. The CPU is
> > > > > i.MX6Q TO 1.0 .
> > > > >
> > > > > I am hitting a WARNING when I use the FEC ethernet to transfer data,
> > > > > thus I started investigating this problem. TL;DR I am not able to
> > > > > figure this problem out, so I am not attaching a patch :-(
> > > > >
> > > > > Steps to reproduce:
> > > > > -------------------
> > > > > 1) Boot stock Linux 3.13 on i.MX6Q SabreLite board
> > > > > 2) Plug in an SD card into one of the SD slots (I use the full-size
> > > > > one) 3) Plug in an USB stick into one of the USB ports (I use the
> > > > > upper one) 4) Plug in an ethernet cable into the board
> > > > >
> > > > > -> Connect the other side into a gigabit-capable PC
> > > >
> > > > [...]
> > > >
> > > > I think there are known problems with 1000BASE-T on the Sabre Lite
> > > > board.
> > >
> > > This is MX6-wide thing, not sabrelite specific actually.
> > >
> > > > Two possible workarounds are to limit the PHY to 100BASE-TX
> > > > (should be doable with ethtool) or force it to be clock master for
> > > > 1000BASE-T (requires a driver patch).
> > >
> > > Can you please elaborate on the later ? I don't quite understand that.
> >
> > 1000BASE-T uses all 4 pairs in both directions at the same time, which
> > requires that both ends transmit symbols synchronously. As part of the
> > autonegotiation protocol, they decide which is the clock master (using a
> > local clock generator) and which is the clock slave (generating a clock
> > from the received signal). A PHY can be configured to support only one
> > of these roles.
>
> I checked the patch you pointed me to. The patch basically messes with the
> CTL1000 (0x9) register of the PHY, right ? I did the adjustments to the PHY
> register manually , but the result is still the same (backtrace).
>
> I did two different kinds of adjustment:
> 1) reg 0x9 |= 0x1800;
> 2) reg 0x9 |= 0x1000;
> In both cases, the crash did happen. I verified the PHY register was configured
> as necessary. The KSZ9021 PHY bit 12 configures the master/slave override, same
> as the patch does. The bit 11 forces either master or slave mode for the PHY. In
> both cases the crash was there.
>
> I think this patch won't help in this case, sorry.
>
Are there any news on this topic?
We also ran into these problems, we've tested the following scenarios
like Marek did with iperf:
We've tested on this equipment
----------------------------------------------
- Boundary Devices Nitrogen 6x Quad with Boundary Kernel based on FSL
3.10.17 (https://github.com/boundarydevices/linux-imx6/tree/boundary-imx_3.10.17_1.0.0_beta)
-> With this Kernel we do not have seen any issues. We see a stable
transfer and a acceptable bandwidth (~325 Mbit/s) on TCP/IP.
- Boundary Devices Nitrogen 6x Quad with vanilla Kernel 3.12.0
https://github.com/boundarydevices/linux-imx6/commits/boundary-imx_3.12.0
-> Here we had massive stability issues and a low TCP/IP throughput
( < 200 Mbit/s )
- Our custom board i.mx6 Dual KSZ9031 Phy with Kernel 3.11 we have
backported a bunch of Ethernet related Patches from mainline and FSL
-> We have a acceptable TCP/IP throughput (~310 Mbit/s) but we also
see periodicaly dips in transmission speed and the NETDEV WATCHDOG
OOps
- Another 3rd party i.mx6 quad board with Kernel 3.10
-> Here we had massive stability issues and a low TCP/IP
throughput ( < 180 Mbit/s )
Best regards,
Christian Ege
^ permalink raw reply
* [PATCH] ARM: davinci: fix typo
From: Prabhakar Lad @ 2014-02-06 5:25 UTC (permalink / raw)
To: linux-arm-kernel
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
this patch fixes a typo in mach/hardware.h, by
replacing "ths" to "this".
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
---
arch/arm/mach-davinci/include/mach/hardware.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 16bb422..8a5d843 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -12,7 +12,7 @@
#define __ASM_ARCH_HARDWARE_H
/*
- * Before you add anything to ths file:
+ * Before you add anything to this file:
*
* This header is for defines common to ALL DaVinci family chips.
* Anything that is chip specific should go in <chipname>.h,
--
1.7.9.5
^ permalink raw reply related
* imx6dl/imx6q fec rmii mode with external ref_clk
From: Shawn Guo @ 2014-02-06 5:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140129095429.GA30854@frolo.macqel>
On Wed, Jan 29, 2014 at 10:54:29AM +0100, Philippe De Muyter wrote:
> > diff --git a/arch/arm/mach-imx/mach-imx6q.c
> > b/arch/arm/mach-imx/mach-imx6q.c
> > index e51e3da..be8d074 100644
> > --- a/arch/arm/mach-imx/mach-imx6q.c
> > +++ b/arch/arm/mach-imx/mach-imx6q.c
> > @@ -188,7 +188,7 @@ static void __init imx6q_1588_init(void)
> > if (!IS_ERR(gpr))
> > regmap_update_bits(gpr, IOMUXC_GPR1,
> > IMX6Q_GPR1_ENET_CLK_SEL_MASK,
> > - IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
> > + 0);
> > else
> > pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
> >
>
> Yes, it works now. Thanks. Is that configurable from the device tree ?
Yes, with some code change, I think that's configurable from device
tree. But, it's not that simple. As I explained in thread [1], the
RMII reference clock ENET_REF_CLK from pad GPIO_16 will also be used
by PTP (IEEE 1588) as sampling clock in your configuration. Right now,
the ptp clock in fec node is defaulted to be enet_ref from IMX6 CCM
(id 190) in imx6qdl.dtsi. You will need to correct it in your board dts
file, something like the following.
clocks {
#address-cells = <1>;
#size-cells = <0>;
rmii_clk: clock at 0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <25000000>; /* 25MHz for example */
};
};
&fec {
clocks = <&clks 117>, <&clks 117>, <&rmii_clk>;
};
I think we can even save a device tree property and ask kernel to figure
it out that bit GPR1[21] should be set or cleared. Yes, kernel should
be able to do that by checking whether the ptp_clk in fec node points to
the enet_ref clock coming from IMX6 clock driver (ANATOP/CCM). I will
send a patch for this soon.
Shawn
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/269265/focus=269646
^ permalink raw reply
* [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
From: Pratyush Anand @ 2014-02-06 4:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1391661589.git.pratyush.anand@st.com>
SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds
support for the same.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/phy/phy-miphy40lp.c | 178 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 178 insertions(+)
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index cc7f45d..61e94be 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -9,6 +9,7 @@
* published by the Free Software Foundation.
*
* 04/02/2014: Adding support of SATA mode for SPEAr1340.
+ * 04/02/2014: Adding support of PCIe mode for SPEAr1340 and SPEAr1310
*/
#include <linux/delay.h>
@@ -73,6 +74,80 @@
#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+/* SPEAr1310 Registers */
+#define SPEAR1310_PCIE_SATA_CFG 0x3A4
+ #define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
+ #define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30)
+ #define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29)
+ #define SPEAR1310_PCIE_SATA2_SEL_SATA (1 << 31)
+ #define SPEAR1310_PCIE_SATA1_SEL_SATA (1 << 30)
+ #define SPEAR1310_PCIE_SATA0_SEL_SATA (1 << 29)
+ #define SPEAR1310_SATA2_CFG_TX_CLK_EN (1 << 27)
+ #define SPEAR1310_SATA2_CFG_RX_CLK_EN (1 << 26)
+ #define SPEAR1310_SATA2_CFG_POWERUP_RESET (1 << 25)
+ #define SPEAR1310_SATA2_CFG_PM_CLK_EN (1 << 24)
+ #define SPEAR1310_SATA1_CFG_TX_CLK_EN (1 << 23)
+ #define SPEAR1310_SATA1_CFG_RX_CLK_EN (1 << 22)
+ #define SPEAR1310_SATA1_CFG_POWERUP_RESET (1 << 21)
+ #define SPEAR1310_SATA1_CFG_PM_CLK_EN (1 << 20)
+ #define SPEAR1310_SATA0_CFG_TX_CLK_EN (1 << 19)
+ #define SPEAR1310_SATA0_CFG_RX_CLK_EN (1 << 18)
+ #define SPEAR1310_SATA0_CFG_POWERUP_RESET (1 << 17)
+ #define SPEAR1310_SATA0_CFG_PM_CLK_EN (1 << 16)
+ #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT (1 << 11)
+ #define SPEAR1310_PCIE2_CFG_POWERUP_RESET (1 << 10)
+ #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN (1 << 9)
+ #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN (1 << 8)
+ #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT (1 << 7)
+ #define SPEAR1310_PCIE1_CFG_POWERUP_RESET (1 << 6)
+ #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN (1 << 5)
+ #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN (1 << 4)
+ #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT (1 << 3)
+ #define SPEAR1310_PCIE0_CFG_POWERUP_RESET (1 << 2)
+ #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN (1 << 1)
+ #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN (1 << 0)
+
+ #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | (1 << (x + 29)))
+ #define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+ (1 << (x + 29)))
+ #define SPEAR1310_PCIE_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+ SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+ #define SPEAR1310_SATA_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+ SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8
+ #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT (1 << 31)
+ #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 (1 << 28)
+ #define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16)
+ #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT (1 << 15)
+ #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 (1 << 12)
+ #define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC
enum phy_mode {
SATA,
@@ -181,6 +256,104 @@ static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
return -EINVAL;
}
+static int spear1340_pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_PCIE_CFG_VAL);
+
+ return 0;
+}
+
+static int spear1340_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+
+ return 0;
+}
+
+static int spear1310_pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ u32 mask, val;
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
+
+ switch (phypriv->id) {
+ case 0:
+ mask = SPEAR1310_PCIE_CFG_MASK(0);
+ val = SPEAR1310_PCIE_CFG_VAL(0);
+ break;
+ case 1:
+ mask = SPEAR1310_PCIE_CFG_MASK(1);
+ val = SPEAR1310_PCIE_CFG_VAL(1);
+ break;
+ case 2:
+ mask = SPEAR1310_PCIE_CFG_MASK(2);
+ val = SPEAR1310_PCIE_CFG_VAL(2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG, mask, val);
+
+ return 0;
+}
+
+static int spear1310_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ u32 mask;
+
+ switch (phypriv->id) {
+ case 0:
+ mask = SPEAR1310_PCIE_CFG_MASK(0);
+ break;
+ case 1:
+ mask = SPEAR1310_PCIE_CFG_MASK(1);
+ break;
+ case 2:
+ mask = SPEAR1310_PCIE_CFG_MASK(2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
+ SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
+
+ return 0;
+}
+
+static int pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_pcie_miphy_init(phypriv);
+ else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
+ return spear1310_pcie_miphy_init(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_pcie_miphy_exit(phypriv);
+ else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
+ return spear1310_pcie_miphy_exit(phypriv);
+ else
+ return -EINVAL;
+}
+
static int miphy40lp_init(struct phy *phy)
{
struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
@@ -188,6 +361,8 @@ static int miphy40lp_init(struct phy *phy)
switch (phypriv->mode) {
case SATA:
return sata_miphy_init(phypriv);
+ case PCIE:
+ return pcie_miphy_init(phypriv);
default:
return -EINVAL;
}
@@ -200,6 +375,8 @@ static int miphy40lp_exit(struct phy *phy)
switch (phypriv->mode) {
case SATA:
return sata_miphy_exit(phypriv);
+ case PCIE:
+ return pcie_miphy_exit(phypriv);
default:
return -EINVAL;
}
@@ -232,6 +409,7 @@ static int miphy40lp_power_on(struct phy *phy)
static const struct of_device_id st_miphy40lp_of_match[] = {
{ .compatible = "st,miphy40lp-phy" },
{ .compatible = "st,spear1340-miphy" },
+ { .compatible = "st,spear1310-miphy" },
{ },
};
MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
--
1.8.1.2
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