* [PATCH v1 1/3] net: stmmac:sti: Add STi SOC glue driver.
From: srinivas kandagatla @ 2014-02-07 7:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140206.195342.1998479313077409827.davem@davemloft.net>
Thankyou Dave,
On 07/02/14 03:53, David Miller wrote:
> From: <srinivas.kandagatla@st.com>
> Date: Mon, 3 Feb 2014 12:01:08 +0000
>
>> + res = platform_get_resource_byname(pdev,
>> + IORESOURCE_MEM, "sti-ethconf");
>
> This is not the correct way to format multi-line function calls,
> you'll need to fix this up in this entire series.
I will fix this in next version.
>
> The arguments on the second and subsequent lines must start at
> the first column after the openning parenthesis of the function
> call. You must use the appropriate number of both space and
> TAB characters necessary to do so.
>
> If you're only using TAB characters to indent, you're doing it
> wrong.
>
> Thank you.
>
>
Thanks,
srini
^ permalink raw reply
* [PATCH 4/4] ARM: Kirkwood: Add support for many Synology NAS devices
From: Ben Peddell @ 2014-02-07 7:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140206160126.GH29860@lunn.ch>
On 7/02/2014 2:01 AM, Andrew Lunn wrote:
> On Thu, Feb 06, 2014 at 10:39:39AM -0500, Jason Cooper wrote:
>>
>> + devicetree ML, DT maintainers
>>
>> On Wed, Feb 05, 2014 at 10:05:09PM +0100, Andrew Lunn wrote:
>>> Add device tree fragments and files to support many of the kirkwood
>>> based Synology NAS devices. This is a translation of the board setup
>>> file maintained by Ben Peddell <klightspeed@killerwolves.net>
>>>
>>> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
>>> Tested by Ben Peddell <klightspeed@killerwolves.net>
>>> cc: Ben Peddell <klightspeed@killerwolves.net>
>>> ---
>>>
>>> v2:
>>> Fix gpio's which should be gpo.
>>> Rebase onto v3-14-rc1
>>> Update RTC nodes with vendor name.
>>> Update SPI flash node with vendor name.
>>> ---
>>> arch/arm/boot/dts/Makefile | 15 ++++
>>> arch/arm/boot/dts/kirkwood-ds109.dts | 33 +++++++
>>> arch/arm/boot/dts/kirkwood-ds110jv10.dts | 33 +++++++
>>> arch/arm/boot/dts/kirkwood-ds111.dts | 33 +++++++
>>> arch/arm/boot/dts/kirkwood-ds112.dts | 34 +++++++
>>> arch/arm/boot/dts/kirkwood-ds209.dts | 33 +++++++
>>> arch/arm/boot/dts/kirkwood-ds210.dts | 35 ++++++++
>>> arch/arm/boot/dts/kirkwood-ds212.dts | 37 ++++++++
>>> arch/arm/boot/dts/kirkwood-ds212j.dts | 34 +++++++
>>> arch/arm/boot/dts/kirkwood-ds409.dts | 34 +++++++
>>> arch/arm/boot/dts/kirkwood-ds409slim.dts | 32 +++++++
>>> arch/arm/boot/dts/kirkwood-ds411.dts | 35 ++++++++
>>> arch/arm/boot/dts/kirkwood-ds411j.dts | 34 +++++++
>>> arch/arm/boot/dts/kirkwood-ds411slim.dts | 34 +++++++
>>> arch/arm/boot/dts/kirkwood-rs212.dts | 34 +++++++
>>> arch/arm/boot/dts/kirkwood-rs409.dts | 33 +++++++
>>> arch/arm/boot/dts/kirkwood-rs411.dts | 34 +++++++
>>> arch/arm/boot/dts/synology/alarm-led-12.dtsi | 28 ++++++
>>> arch/arm/boot/dts/synology/common.dtsi | 112 ++++++++++++++++++++++++
>>> arch/arm/boot/dts/synology/ethernet-1.dtsi | 15 ++++
>>> arch/arm/boot/dts/synology/fan-alarm-18.dtsi | 22 +++++
>>> arch/arm/boot/dts/synology/fan-alarm-35-1.dtsi | 22 +++++
>>> arch/arm/boot/dts/synology/fan-alarm-35-3.dtsi | 32 +++++++
>>> arch/arm/boot/dts/synology/fan-gpios-15.dtsi | 34 +++++++
>>> arch/arm/boot/dts/synology/fan-gpios-32.dtsi | 34 +++++++
>>> arch/arm/boot/dts/synology/fan-speed-100.dtsi | 20 +++++
>>> arch/arm/boot/dts/synology/fan-speed-120.dtsi | 20 +++++
>>> arch/arm/boot/dts/synology/fan-speed-150.dtsi | 20 +++++
>>> arch/arm/boot/dts/synology/hdd-leds-20.dtsi | 90 +++++++++++++++++++
>>> arch/arm/boot/dts/synology/hdd-leds-21-1.dtsi | 36 ++++++++
>>> arch/arm/boot/dts/synology/hdd-leds-21-2.dtsi | 52 +++++++++++
>>> arch/arm/boot/dts/synology/hdd-leds-36.dtsi | 103 ++++++++++++++++++++++
>>> arch/arm/boot/dts/synology/hdd-leds-38.dtsi | 52 +++++++++++
>>> arch/arm/boot/dts/synology/hdd-power-29.dtsi | 56 ++++++++++++
>>> arch/arm/boot/dts/synology/hdd-power-30-1.dtsi | 40 +++++++++
>>> arch/arm/boot/dts/synology/hdd-power-30-2.dtsi | 56 ++++++++++++
>>> arch/arm/boot/dts/synology/hdd-power-30-4.dtsi | 89 +++++++++++++++++++
>>> arch/arm/boot/dts/synology/hdd-power-31.dtsi | 40 +++++++++
>>> arch/arm/boot/dts/synology/hdd-power-34.dtsi | 73 +++++++++++++++
>>> arch/arm/boot/dts/synology/i2c-rtc-ricoh.dtsi | 18 ++++
>>> arch/arm/boot/dts/synology/i2c-rtc-seiko.dtsi | 18 ++++
>>> arch/arm/boot/dts/synology/pcie-2.dtsi | 19 ++++
>>> 42 files changed, 1658 insertions(+)
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds109.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds110jv10.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds111.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds112.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds209.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds210.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds212.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds212j.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds409.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds409slim.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds411.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds411j.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-ds411slim.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-rs212.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-rs409.dts
>>> create mode 100644 arch/arm/boot/dts/kirkwood-rs411.dts
>>> create mode 100644 arch/arm/boot/dts/synology/alarm-led-12.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/common.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/ethernet-1.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/fan-alarm-18.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/fan-alarm-35-1.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/fan-alarm-35-3.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/fan-gpios-15.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/fan-gpios-32.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/fan-speed-100.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/fan-speed-120.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/fan-speed-150.dtsi
If we're not worried about the non-linearity of the 150R+120R+100R and
182R+150R+100R fan controllers (vs the 150R/100R/33R ones), these fan
speed blocks could be collapsed into common.dtsi.
>>> create mode 100644 arch/arm/boot/dts/synology/hdd-leds-20.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/hdd-leds-21-1.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/hdd-leds-21-2.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/hdd-leds-36.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/hdd-leds-38.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/hdd-power-29.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/hdd-power-30-1.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/hdd-power-30-2.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/hdd-power-30-4.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/hdd-power-31.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/hdd-power-34.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/i2c-rtc-ricoh.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/i2c-rtc-seiko.dtsi
>>> create mode 100644 arch/arm/boot/dts/synology/pcie-2.dtsi
>>
>> Holy sh*t! I know we're adding 15 boards
>
> More than 15 actually. Most .dts files support multiple devices. So
> there should be about 30 devices supported by these .dts files.
>
>> , but this is, imho,
>> over-fragmenting. I'm sure there's a reason you chose this path, but
>> you haven't explained why in your commit log. So I'm left guessing...
>
> Synology seem to build there devices like lego. They have two
> different RTC blocks. They have three different fan alarm blocks, four
> different led blocks, etc. And to build a product, the just select a
> group of blocks and put them together.
The Ricoh RTC seems to be only used in the pre-2010 units. Everything
else uses the Seiko RTC.
Most of the 1-bay and 2-bay units use the GPIOs that are multiplexed
with the built-in SATA interface activity/presence pins on mpp 20-23,
while the 4-bay units use ge01 and a PCIe SATA controller, and put the
software controlled HDD leds on mpp 36-43.
Most of the 6281 units with HDD power controls use mpp 29 and 31, while
most of the 6282 units with HDD power controls use mpp 30, 34, 44 and 45
and provide a model ID on mpp 28, 29, 46 and 47. Pre-2012 units and
4-bay units didn't have a separate power control for HDD1. These power
controls are presumably to limit startup current from the 12V brick
power supply.
From
http://forum.synology.com/wiki/index.php/What_kind_of_CPU_does_my_NAS_have,
it doesn't look like there are any new 6281 or 6282 models for 2014.
>
> The board setup code which Ben Peddell wrote has a somewhat similar
> structure:
>
> http://klightspeed.killerwolves.net/synology/linux-3.4-synology-0.1.patch
A more up-to-date version is at:
http://klightspeed.killerwolves.net/synology/linux-3.7-synology-0.2.patch
>
> It has a set of functions which add platform devices. And a table
> driven piece of code which based on the product name calls these
> functions to add the needed platform devices. Take a look at the table
> to get a better idea of the re-use factor of the blocks.
>
> In this DT version, i have a dtsi file for each function, and a dti
> file for each table entry.
>
> I will add to the changelog in the next version.
--
Ben Peddell
IT Support Bowen, Collinsville and Proserpine Catholic schools
http://klightspeed.killerwolves.net/
^ permalink raw reply
* [PATCH 1/2] PPC: powernv: remove redundant cpuidle_idle_call()
From: Preeti U Murthy @ 2014-02-07 7:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.11.1402070105170.1906@knanqh.ubzr>
Hi Nicolas,
Find below the patch that will need to be squashed with this one.
This patch is based on the mainline.Adding Deepthi, the author of
the patch which introduced the powernv cpuidle driver. Deepthi,
do you think the below patch looks right? We do not need to do an
explicit local_irq_enable() since we are in the call path of
cpuidle driver and that explicitly enables irqs on exit from
idle states.
On 02/07/2014 06:47 AM, Nicolas Pitre wrote:
> On Thu, 6 Feb 2014, Preeti U Murthy wrote:
>
>> Hi Daniel,
>>
>> On 02/06/2014 09:55 PM, Daniel Lezcano wrote:
>>> Hi Nico,
>>>
>>>
>>> On 6 February 2014 14:16, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>>>
>>>> The core idle loop now takes care of it.
>>>>
>>>> Signed-off-by: Nicolas Pitre <nico@linaro.org>
>>>> ---
>>>> arch/powerpc/platforms/powernv/setup.c | 13 +------------
>>>> 1 file changed, 1 insertion(+), 12 deletions(-)
>>>>
>>>> diff --git a/arch/powerpc/platforms/powernv/setup.c
>>>> b/arch/powerpc/platforms/powernv/setup.c
>>>> index 21166f65c9..a932feb290 100644
>>>> --- a/arch/powerpc/platforms/powernv/setup.c
>>>> +++ b/arch/powerpc/platforms/powernv/setup.c
>>>> @@ -26,7 +26,6 @@
>>>> #include <linux/of_fdt.h>
>>>> #include <linux/interrupt.h>
>>>> #include <linux/bug.h>
>>>> -#include <linux/cpuidle.h>
>>>>
>>>> #include <asm/machdep.h>
>>>> #include <asm/firmware.h>
>>>> @@ -217,16 +216,6 @@ static int __init pnv_probe(void)
>>>> return 1;
>>>> }
>>>>
>>>> -void powernv_idle(void)
>>>> -{
>>>> - /* Hook to cpuidle framework if available, else
>>>> - * call on default platform idle code
>>>> - */
>>>> - if (cpuidle_idle_call()) {
>>>> - power7_idle();
>>>> - }
>>>>
drivers/cpuidle/cpuidle-powernv.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/cpuidle/cpuidle-powernv.c b/drivers/cpuidle/cpuidle-powernv.c
index 78fd174..130f081 100644
--- a/drivers/cpuidle/cpuidle-powernv.c
+++ b/drivers/cpuidle/cpuidle-powernv.c
@@ -31,11 +31,13 @@ static int snooze_loop(struct cpuidle_device *dev,
set_thread_flag(TIF_POLLING_NRFLAG);
while (!need_resched()) {
+ ppc64_runlatch_off();
HMT_low();
HMT_very_low();
}
HMT_medium();
+ ppc64_runlatch_on();
clear_thread_flag(TIF_POLLING_NRFLAG);
smp_mb();
return index;
@@ -45,7 +47,9 @@ static int nap_loop(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
+ ppc64_runlatch_off();
power7_idle();
+ ppc64_runlatch_on();
return index;
}
Thanks
Regards
Preeti U Murthy
^ permalink raw reply related
* [PATCH 1/3] clk: rcar-h2: fix sd0/sd1 divisor table
From: Kuninori Morimoto @ 2014-02-07 6:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87txcdul4b.wl%kuninori.morimoto.gx@gmail.com>
Hi William, Ben, Laurent
> > > >>> static const struct clk_div_table cpg_sd01_div_table[] = {
> > > >>> + { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
> > > >>> + { 4, 8 },
> > > >>>
> > > >>> { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
> > > >>> { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
According to HW team, datasheet is correct.
Some HW has above un-documented implementation indeed,
but these are not supported.
But, 0x0100 (x1/8) on SD0FC/SD1FC is now supported and documented in
latest datasheet.
> > > sdhi0 showed 156MHz output, and it seemed to work. So there is a
> > > distinct possibility that the sdh clock also supports setting 12
> > > for a /10
According to HW there,
SDHFC will be stopped if you set 0xC.
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
From: Pratyush Anand @ 2014-02-07 6:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140207035429.GB2414@pratyush-vbox>
Hi Arnd,
On Fri, Feb 07, 2014 at 11:54:30AM +0800, Pratyush ANAND wrote:
> Hi Arnd,
>
> On Thu, Feb 06, 2014 at 11:37:05PM +0800, Arnd Bergmann wrote:
> > On Thursday 06 February 2014, Pratyush Anand wrote:
> >
[...]
> > I think it's better to make this code table-driven. Rather than checking
> > 'of_device_is_compatible()', it's much easier to add a .data field to
> > the of_device_id array that describes the PHY. You can use .data to
> > point to a structure containing per-device function pointers or
> > (better) values and offsets to be used.
values and offset would be good as long as we do not need to write on
conditional read status. In our case its OK, as we do not need to
write conditionally. But, would it be a good idea to go that way?
Regards
Pratyush
>
> Sounds a better idea. will reduce code size a lot. Thanks.
>
> Regards
> Pratyush
>
> >
> > Arnd
^ permalink raw reply
* [PATCH v9 00/12] Add power management support for mxs phy
From: Peter Chen @ 2014-02-07 5:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e3a207a65094481e9a3e149ac89e6505@BL2PR03MB226.namprd03.prod.outlook.com>
On Mon, Jan 20, 2014 at 2:48 PM, Peter Chen <Peter.Chen@freescale.com> wrote:
>
>
>
>>
>> Hi Felipe & Shawn,
>>
>> The serial adds power management support for MXS PHY, it includes:
>>
>> - Add one PHY API .set_wakeup, and related API implementation at mxs phy
>> driver
>> - misc changes and bug fixes for mxs phy to support low power mode and
>> wakeup.
>>
>> It is based on the lastest Greg's usb-next, 3.13-rc5.
>>
>
> Hi Felipe,
>
> I would like to confirm if this patchset is ok, and will be in
> your 3.15 tree?
>
ping...
--
BR,
Peter Chen
^ permalink raw reply
* [PATCH 02/18] arm64: GICv3 device tree binding documentation
From: Arnab Basu @ 2014-02-07 5:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391607050-540-3-git-send-email-marc.zyngier@arm.com>
Hi Marc
Marc Zyngier <marc.zyngier <at> arm.com> writes:
> +
> +AArch64 SMP cores are often associated with a GICv3, providing private
> +peripheral interrupts (PPI), shared peripheral interrupts (SPI),
> +software generated interrupts (SGI), and locality-specific peripheral
> +Interrupts (LPI).
> +
> +Main node required properties:
> +
> +- compatible : should at least contain "arm,gic-v3".
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> + interrupt source. Must be a single cell with a value of at least 3.
> +
> + The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
> + interrupts. Other values are reserved for future use.
These values are defined in
"include/dt-bindings/interrupt-controller/arm-gic.h" maybe we should start
mentioning that here and encourage future device treese to use those defines
to improve readability.
> +
> + The 2nd cell contains the interrupt number for the interrupt type.
> + SPI interrupts are in the range [0-987]. PPI interrupts are in the
> + range [0-15].
> +
> + The 3rd cell is the flags, encoded as follows:
> + bits[3:0] trigger type and level flags.
> + 1 = edge triggered
> + 2 = edge triggered (deprecated, for compatibility with GICv2)
> + 4 = level triggered
> + 8 = level triggered (deprecated, for compatibility with GICv2)
Similar to the above comment
"include/dt-bindings/interrupt-controller/irq.h" defines the trigger type
and level flags. Although this file currently contains the GICv2 bindings,
we could update them.
Thanks
Arnab
> +
> + Cells 4 and beyond are reserved for future use. Where the 1st cell
> + has a value of 0 or 1, cells 4 and beyond act as padding, and may be
> + ignored. It is recommended that padding cells have a value of 0.
> +
> +- reg : Specifies base physical address(s) and size of the GIC
> + registers, in the following order:
> + - GIC Distributor interface (GICD)
> + - GIC Redistributors (GICR), one range per redistributor region
> + - GIC CPU interface (GICC)
> + - GIC Hypervisor interface (GICH)
> + - GIC Virtual CPU interface (GICV)
> +
> + GICC, GICH and GICV are optional.
> +
> +- interrupts : Interrupt source of the VGIC maintenance interrupt.
> +
^ permalink raw reply
* [PATCH 1/2] PPC: powernv: remove redundant cpuidle_idle_call()
From: Preeti U Murthy @ 2014-02-07 5:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.11.1402070105170.1906@knanqh.ubzr>
Hi Nicolas,
On 02/07/2014 06:47 AM, Nicolas Pitre wrote:
> On Thu, 6 Feb 2014, Preeti U Murthy wrote:
>
>> Hi Daniel,
>>
>> On 02/06/2014 09:55 PM, Daniel Lezcano wrote:
>>> Hi Nico,
>>>
>>>
>>> On 6 February 2014 14:16, Nicolas Pitre <nicolas.pitre@linaro.org> wrote:
>>>
>>>> The core idle loop now takes care of it.
>>>>
>>>> Signed-off-by: Nicolas Pitre <nico@linaro.org>
>>>> ---
>>>> arch/powerpc/platforms/powernv/setup.c | 13 +------------
>>>> 1 file changed, 1 insertion(+), 12 deletions(-)
>>>>
>>>> diff --git a/arch/powerpc/platforms/powernv/setup.c
>>>> b/arch/powerpc/platforms/powernv/setup.c
>>>> index 21166f65c9..a932feb290 100644
>>>> --- a/arch/powerpc/platforms/powernv/setup.c
>>>> +++ b/arch/powerpc/platforms/powernv/setup.c
>>>> @@ -26,7 +26,6 @@
>>>> #include <linux/of_fdt.h>
>>>> #include <linux/interrupt.h>
>>>> #include <linux/bug.h>
>>>> -#include <linux/cpuidle.h>
>>>>
>>>> #include <asm/machdep.h>
>>>> #include <asm/firmware.h>
>>>> @@ -217,16 +216,6 @@ static int __init pnv_probe(void)
>>>> return 1;
>>>> }
>>>>
>>>> -void powernv_idle(void)
>>>> -{
>>>> - /* Hook to cpuidle framework if available, else
>>>> - * call on default platform idle code
>>>> - */
>>>> - if (cpuidle_idle_call()) {
>>>> - power7_idle();
>>>> - }
>>>>
>>>
>>> The cpuidle_idle_call is called from arch_cpu_idle in
>>> arch/powerpc/kernel/idle.c between a ppc64_runlatch_off|on section.
>>> Shouldn't the cpuidle-powernv driver call these functions when entering
>>> idle ?
>>
>> Yes they should, I will send out a patch that does that ontop of this.
>> There have been cpuidle driver cleanups for powernv and pseries in this
>> merge window. While no change would be required in the pseries cpuidle
>> driver as a result of Nicolas's cleanup, we would need to add the
>> ppc64_runlatch_on and off functions before and after the entry into the
>> powernv idle states.
>
> What about creating arch_cpu_idle_enter() and arch_cpu_idle_exit() in
> arch/powerpc/kernel/idle.c and calling ppc64_runlatch_off() and
> ppc64_runlatch_on() respectively from there instead? Would that work?
> That would make the idle consolidation much easier afterwards.
I would not suggest doing this. The ppc64_runlatch_*() routines need to
be called when we are sure that the cpu is about to enter or has exit an
idle state. Moving the ppc64_runlatch_on() routine to
arch_cpu_idle_enter() for instance is not a good idea because there are
places where the cpu can decide not to enter any idle state before the
call to cpuidle_idle_call() itself. In that case communicating
prematurely that we are in an idle state would not be a good idea.
So its best to add the ppc64_runlatch_* calls in the powernv cpuidle
driver IMO. We could however create idle_loop_prologue/epilogue()
variants inside it so that in addition to the runlatch routines we could
potentially add more such similar routines that are powernv specific.
If there are cases where there is work to be done prior to and post an
entry into an idle state common to both pseries and powernv, we will
probably put them in arch_cpu_idle_enter/exit(). But the runlatch
routines are not suitable to be moved there as far as I can see.
Thank you
Regards
Preeti U Murthy
>
>
> Nicolas
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
* [PATCH v5 00/14] Add support for MSM's mmio clock/reset controller
From: Joe Perches @ 2014-02-07 5:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F45DEE.8020400@gmail.com>
On Thu, 2014-02-06 at 20:15 -0800, Frank Rowand wrote:
> On 1/15/2014 10:47 AM, Stephen Boyd wrote:
> > The first breaks a reset-controller include ordering requirement. It got
> > an ack so I think we're ok for it to go through the clock tree.
> >
>
> < snip >
>
> checkpatch is whining about patches
>
> 4
> 5
> 6
> 7
> 8
>
> (Just for completeness if someone thinks I did not check all the patches,
> it also whines about patch 11, but I think the whining should be ignored,
> and it whines about patch 1 but I think that might be a checkpatch bug.)
Hi Frank.
For patch 1, what checkpatch bug might that be?
I think all the checkpatch whinges in patch 11 are correct.
I didn't check any of 4-8.
^ permalink raw reply
* PCIe trouble on imx6q
From: Hong-Xing.Zhu at freescale.com @ 2014-02-07 4:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAM9uW_6ok-H1YpqUu3CgZ45aezi9rs+eDjCHBmd9-vO4jDjf4w@mail.gmail.com>
Hi:
> -----Original Message-----
> From: Kamel BOUHARA [mailto:k.bouhara at gmail.com]
> Sent: Tuesday, February 04, 2014 5:10 PM
> To: Bjorn Helgaas
> Cc: linux-pci at vger.kernel.org; linux-arm; Zhu Richard-R65037; Shawn Guo
> Subject: Re: PCIe trouble on imx6q
>
> 2014-01-29 Kamel BOUHARA <k.bouhara@gmail.com>:
> > 2014-01-29 Bjorn Helgaas <bhelgaas@google.com>:
> >> [+cc linux-arm, Richard, Shawn (please keep the cc list)]
> >>
> >> On Wed, Jan 29, 2014 at 2:28 AM, Kamel BOUHARA <k.bouhara@gmail.com> wrote:
> >>> ---------- Forwarded message ----------
> >>> From: Kamel BOUHARA <k.bouhara@gmail.com>
> >>> Date: 2014-01-29
> >>> Subject: Re: PCIe trouble on imx6q
> >>> To: Bjorn Helgaas <bhelgaas@google.com>
> >>>
> >>>
> >>> 2014-01-28 Bjorn Helgaas <bhelgaas@google.com>:
> >>>> [+cc Richard, Shawn, linux-arm-kernel (all from MAINTAINERS)]
> >>>>
> >>>> On Tue, Jan 28, 2014 at 1:02 AM, Kamel BOUHARA <k.bouhara@gmail.com>
> wrote:
> >>>>> Hello,
> >>>>>
> >>>>> Im getting trouble with kernel 3.13 at boot time, the pcie link
> >>>>> failed to get up with the following log:
> >>>>> ------------[ cut here ]------------
> >>>>> WARNING: CPU: 0 PID: 1 at drivers/gpio/gpiolib.c:159
> >>>>> gpio_to_desc+0x34/0x48() invalid GPIO -2 Modules linked in:
> >>>>> CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0+ #4
> >>>>> Backtrace:
> >>>>> [<8001217c>] (dump_backtrace) from [<80012460>]
> >>>>> (show_stack+0x18/0x1c)
> >>>>> r6:802b9548 r5:00000000 r4:808d3060 r3:00000000 [<80012448>]
> >>>>> (show_stack) from [<806414fc>] (dump_stack+0x84/0x9c) [<80641478>]
> >>>>> (dump_stack) from [<800289f8>] (warn_slowpath_common+0x70/0x94)
> >>>>> r5:00000009 r4:bf05bcb0
> >>>>> [<80028988>] (warn_slowpath_common) from [<80028a54>]
> >>>>> (warn_slowpath_fmt+0x38/0x40)
> >>>>> r8:01f00000 r7:00000000 r6:0011cc11 r5:808b68c0 r4:bf24fa30
> >>>>> [<80028a20>] (warn_slowpath_fmt) from [<802b9548>]
> >>>>> (gpio_to_desc+0x34/0x48) r3:fffffffe r2:807d23fc [<802b9514>]
> >>>>> (gpio_to_desc) from [<802d9de0>] (imx6_pcie_host_init+0x174/0x434)
> >>>>> [<802d9c6c>] (imx6_pcie_host_init) from [<80886dbc>]
> >>>>> (dw_pcie_host_init+0x348/0x41c)
> >>>>> r6:00000000 r5:808d52cc r4:00000020 r3:802d9c6c [<80886a74>]
> >>>>> (dw_pcie_host_init) from [<808871d4>]
> >>>>> (imx6_pcie_probe+0x320/0x3dc)
> >>>>> r10:00000000 r9:000000c4 r8:808d539c r7:bf7e3384 r6:bf24fa30
> >>>>> r5:bf135810
> >>>>> r4:bf24fa10
> >>>>> [<80886eb4>] (imx6_pcie_probe) from [<8034b670>]
> >>>>> (platform_drv_probe+0x20/0x50) r8:808d539c r7:00000000
> >>>>> r6:00000000 r5:808d539c r4:bf135810 [<8034b650>]
> >>>>> (platform_drv_probe) from [<80349c74>]
> >>>>> (driver_probe_device+0x118/0x234)
> >>>>> r5:bf135810 r4:80e526b8
> >>>>> [<80349b5c>] (driver_probe_device) from [<80349e78>]
> >>>>> (__driver_attach+0x9c/0xa0)
> >>>>> r8:80886e90 r7:00000000 r6:bf135844 r5:808d539c r4:bf135810
> >>>>> r3:00000000 [<80349ddc>] (__driver_attach) from [<8034806c>]
> >>>>> (bus_for_each_dev+0x68/0x9c) r6:80349ddc r5:808d539c r4:00000000
> >>>>> r3:00000000 [<80348004>] (bus_for_each_dev) from [<8034972c>]
> >>>>> (driver_attach+0x20/0x28)
> >>>>> r6:808df6a8 r5:bf1f5e00 r4:808d539c [<8034970c>] (driver_attach)
> >>>>> from [<803493b0>] (bus_add_driver+0x148/0x1f4) [<80349268>]
> >>>>> (bus_add_driver) from [<8034a4c8>] (driver_register+0x80/0x100)
> >>>>> r7:8090e640 r6:8090e640 r5:00000005 r4:808d539c [<8034a448>]
> >>>>> (driver_register) from [<8034b63c>]
> >>>>> (__platform_driver_register+0x50/0x64)
> >>>>> r5:00000005 r4:808d5388
> >>>>> [<8034b5ec>] (__platform_driver_register) from [<8034b6e0>]
> >>>>> (platform_driver_probe+0x28/0xac)
> >>>>> [<8034b6b8>] (platform_driver_probe) from [<80886ea8>]
> >>>>> (imx6_pcie_init+0x18/0x24)
> >>>>> r5:00000005 r4:808aa104
> >>>>> [<80886e90>] (imx6_pcie_init) from [<80008978>]
> >>>>> (do_one_initcall+0x100/0x164) [<80008878>] (do_one_initcall) from
> >>>>> [<8085ecc0>]
> >>>>> (kernel_init_freeable+0x10c/0x1d0)
> >>>>> r10:8089e060 r9:000000c4 r8:8089e050 r7:8090e640 r6:8090e640
> >>>>> r5:00000005
> >>>>> r4:808aa104
> >>>>> [<8085ebb4>] (kernel_init_freeable) from [<8063b67c>]
> >>>>> (kernel_init+0x10/0x120)
> >>>>> r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000
> >>>>> r5:8063b66c
> >>>>> r4:00000000
> >>>>> [<8063b66c>] (kernel_init) from [<8000e9c8>]
> >>>>> (ret_from_fork+0x14/0x2c)
> >>>>> r4:00000000 r3:ffffffff
> >>>>> ---[ end trace b5e746dfc2398cd6 ]--- ------------[ cut here
> >>>>> ]------------
> >>>>> WARNING: CPU: 0 PID: 1 at drivers/gpio/gpiolib.c:159
> >>>>> gpio_to_desc+0x34/0x48() invalid GPIO -2 Modules linked in:
> >>>>> CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.13.0+ #4
> >>>>> Backtrace:
> >>>>> [<8001217c>] (dump_backtrace) from [<80012460>]
> >>>>> (show_stack+0x18/0x1c)
> >>>>> r6:802b9548 r5:00000000 r4:808d3060 r3:00000000 [<80012448>]
> >>>>> (show_stack) from [<806414fc>] (dump_stack+0x84/0x9c) [<80641478>]
> >>>>> (dump_stack) from [<800289f8>] (warn_slowpath_common+0x70/0x94)
> >>>>> r5:00000009 r4:bf05bcb0
> >>>>> [<80028988>] (warn_slowpath_common) from [<80028a54>]
> >>>>> (warn_slowpath_fmt+0x38/0x40)
> >>>>> r8:01f00000 r7:00000000 r6:0011cc11 r5:808b68c0 r4:bf24fa30
> >>>>> [<80028a20>] (warn_slowpath_fmt) from [<802b9548>]
> >>>>> (gpio_to_desc+0x34/0x48) r3:fffffffe r2:807d23fc [<802b9514>]
> >>>>> (gpio_to_desc) from [<802d9df8>] (imx6_pcie_host_init+0x18c/0x434)
> >>>>> [<802d9c6c>] (imx6_pcie_host_init) from [<80886dbc>]
> >>>>> (dw_pcie_host_init+0x348/0x41c)
> >>>>> r6:00000000 r5:808d52cc r4:00000020 r3:802d9c6c [<80886a74>]
> >>>>> (dw_pcie_host_init) from [<808871d4>]
> >>>>> (imx6_pcie_probe+0x320/0x3dc)
> >>>>> r10:00000000 r9:000000c4 r8:808d539c r7:bf7e3384 r6:bf24fa30
> >>>>> r5:bf135810
> >>>>> r4:bf24fa10
> >>>>> [<80886eb4>] (imx6_pcie_probe) from [<8034b670>]
> >>>>> (platform_drv_probe+0x20/0x50) r8:808d539c r7:00000000
> >>>>> r6:00000000 r5:808d539c r4:bf135810 [<8034b650>]
> >>>>> (platform_drv_probe) from [<80349c74>]
> >>>>> (driver_probe_device+0x118/0x234)
> >>>>> r5:bf135810 r4:80e526b8
> >>>>> [<80349b5c>] (driver_probe_device) from [<80349e78>]
> >>>>> (__driver_attach+0x9c/0xa0)
> >>>>> r8:80886e90 r7:00000000 r6:bf135844 r5:808d539c r4:bf135810
> >>>>> r3:00000000 [<80349ddc>] (__driver_attach) from [<8034806c>]
> >>>>> (bus_for_each_dev+0x68/0x9c) r6:80349ddc r5:808d539c r4:00000000
> >>>>> r3:00000000 [<80348004>] (bus_for_each_dev) from [<8034972c>]
> >>>>> (driver_attach+0x20/0x28)
> >>>>> r6:808df6a8 r5:bf1f5e00 r4:808d539c [<8034970c>] (driver_attach)
> >>>>> from [<803493b0>] (bus_add_driver+0x148/0x1f4) [<80349268>]
> >>>>> (bus_add_driver) from [<8034a4c8>] (driver_register+0x80/0x100)
> >>>>> r7:8090e640 r6:8090e640 r5:00000005 r4:808d539c [<8034a448>]
> >>>>> (driver_register) from [<8034b63c>]
> >>>>> (__platform_driver_register+0x50/0x64)
> >>>>> r5:00000005 r4:808d5388
> >>>>> [<8034b5ec>] (__platform_driver_register) from [<8034b6e0>]
> >>>>> (platform_driver_probe+0x28/0xac)
> >>>>> [<8034b6b8>] (platform_driver_probe) from [<80886ea8>]
> >>>>> (imx6_pcie_init+0x18/0x24)
> >>>>> r5:00000005 r4:808aa104
> >>>>> [<80886e90>] (imx6_pcie_init) from [<80008978>]
> >>>>> (do_one_initcall+0x100/0x164) [<80008878>] (do_one_initcall) from
> >>>>> [<8085ecc0>]
> >>>>> (kernel_init_freeable+0x10c/0x1d0)
> >>>>> r10:8089e060 r9:000000c4 r8:8089e050 r7:8090e640 r6:8090e640
> >>>>> r5:00000005
> >>>>> r4:808aa104
> >>>>> [<8085ebb4>] (kernel_init_freeable) from [<8063b67c>]
> >>>>> (kernel_init+0x10/0x120)
> >>>>> r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000
> >>>>> r5:8063b66c
> >>>>> r4:00000000
> >>>>> [<8063b66c>] (kernel_init) from [<8000e9c8>]
> >>>>> (ret_from_fork+0x14/0x2c)
> >>>>> r4:00000000 r3:ffffffff
> >>>>> ---[ end trace b5e746dfc2398cd7 ]--- imx6q-pcie 1ffc000.pcie: phy
> >>>>> link never came up PCI host bridge to bus 0000:00 pci_bus 0000:00:
> >>>>> root bus resource [io 0x1000-0x10000] pci_bus 0000:00: root bus
> >>>>> resource [mem 0x01000000-0x01efffff] pci_bus 0000:00: No busn
> >>>>> resource found for root bus, will use [bus 00-ff]
> >>>>
> >>>> Not related to the GPIO/link problem, but something's wrong here --
> >>>> the host bridge driver should be telling us what bus numbers are
> >>>> behind the host bridge. Since it didn't, the PCI core had to guess.
> >>>>
> >>>>> PCI: bus0: Fast back to back transfers disabled
> >>>>> PCI: bus1: Fast back to back transfers enabled pci 0000:00:00.0:
> >>>>> BAR 0: assigned [mem 0x01000000-0x010fffff] pci 0000:00:00.0: BAR
> >>>>> 6: assigned [mem 0x01100000-0x0110ffff pref] pci 0000:00:00.0: PCI
> >>>>> bridge to [bus 01] pci 0000:00:00.0: PCI bridge to [bus 01]
> >>>>>
> >>>>> Please, any help is welcome.
> >>>>> Regards,
> >>>>> Kamel.B
> >>>>> --
> >>>>> To unsubscribe from this list: send the line "unsubscribe
> >>>>> linux-pci" in the body of a message to majordomo at vger.kernel.org
> >>>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
> >>>
> >>> So I suppose, this is not a hardware issue rather a bad configuration ?
> >>> Maybe the following log from lspci will be helpful ?
> >>
> >> It looks like a configuration issue or an imx6q host bridge issue.
> >> In either case, it looks like something *before* we get to PCIe, so
> >> something like your DT description of the host bridge is more likely
> >> to be useful.
> >>
> >>> root at phyFLEX-i:~ lspci -vvv
> >>> 00:00.0 PCI bridge: Device 16c3:abcd (rev 01) (prog-if 00 [Normal decode])
> >>> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> >>> ParErr+ Stepping- SERR+ FastB2B- DisINTx+
> >>> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast
> >>> >TAbort-
> >>> <TAbort- <MAbort- >SERR- <PERR- INTx-
> >>> Latency: 0, Cache Line Size: 64 bytes
> >>> Region 0: Memory at 01000000 (32-bit, non-prefetchable) [size=1M]
> >>> Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
> >>> I/O behind bridge: 0000f000-00000fff
> >>> Memory behind bridge: fff00000-000fffff
> >>> Prefetchable memory behind bridge: fff00000-000fffff
> >>> Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast
> >>> >TAbort-
> >>> <TAbort- <MAbort- <SERR- <PERR-
> >>> [virtual] Expansion ROM at 01100000 [disabled] [size=64K]
> >>> BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
> >>> PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
> >>> Capabilities: [40] Power Management version 3
> >>> Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA
> >>> PME(D0+,D1+,D2-,D3hot+,D3cold+)
> >>> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> >>> Capabilities: [50] MSI: Mask+ 64bit+ Count=1/1 Enable+
> >>> Address: 0000000090000000 Data: 0000
> >>> Masking: 00000000 Pending: 00000000
> >>> Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
> >>> DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency
> >>> L0s <64ns, L1 <1us
> >>> ExtTag- RBE+ FLReset-
> >>> DevCtl: Report errors: Correctable+ Non-Fatal+
> >>> Fatal+
> >>> Unsupported+
> >>> RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
> >>> MaxPayload 128 bytes, MaxReadReq 512 bytes
> >>> DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq-
> >>> AuxPwr+ TransPend-
> >>> LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s
> >>> L1, Latency L0 <1us, L1 <8us
> >>> ClockPM- Surprise- LLActRep+ BwNot-
> >>> LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain-
> CommClk-
> >>> ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
> >>> LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train-
> >>> SlotClk+ DLActive- BWMgmt- ABWMgmt-
> >>> RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal-
> >>> PMEIntEna+ CRSVisible-
> >>> RootCap: CRSVisible-
> >>> RootSta: PME ReqID 0000, PMEStatus- PMEPending-
> >>> DevCap2: Completion Timeout: Range ABCD, TimeoutDis+
> ARIFwd-
> >>> DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
> ARIFwd-
> >>> LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance-
> >>> SpeedDis-, Selectable De-emphasis: -6dB
> >>> Transmit Margin: Normal Operating Range,
> >>> EnterModifiedCompliance- ComplianceSOS-
> >>> Compliance De-emphasis: -6dB
> >>> LnkSta2: Current De-emphasis Level: -3.5dB
> >>> Capabilities: [100] Advanced Error Reporting
> >>> UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt-
> >>> UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
> >>> UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt-
> >>> UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
> >>> UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt-
> >>> UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
> >>> CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout-
> NonFatalErr-
> >>> CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout-
> NonFatalErr+
> >>> AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+
> ChkEn-
> >>> Capabilities: [140] Virtual Channel <?>
> >>> Kernel driver in use: pcieport
> >>> --
> >>> To unsubscribe from this list: send the line "unsubscribe linux-pci"
> >>> in the body of a message to majordomo at vger.kernel.org More majordomo
> >>> info at http://vger.kernel.org/majordomo-info.html
> >
> > Ok, actually I didn't get the host bridge set properly for my board,
> > here is my DT:
> >
> >
> > /dts-v1/;
> > #include "imx6q-phytec-pfla02.dtsi"
> >
> > / {
> > model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board";
> > compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02",
> > "fsl,imx6q"; };
> >
> > &fec {
> > status = "okay";
> > };
> >
> > &uart4 {
> > status = "okay";
> > };
> >
> > &usdhc2 {
> > status = "okay";
> > };
> >
> > &usdhc3 {
> > status = "okay";
> > };
> >
> > &pcie {
> > status = "okay";
> > };
> >
> >
> > Can you give me a example of host configuration ?
> >
> >
> > BR, Kamel.B
>
> I finally found that I missed the disable-gpio that has to be at high level:
>
> &pcie {
> /*module pfla02 rev1 */
> #if 0
> reset-gpio = <&gpio2 23 0>; /* active low */
> wake-up-gpio = <&gpio1 7 0>; /* active low */
> disable-gpio = <&gpio1 21 1>; /* active low, don't disable endpoint gpios
> */ #endif #if 1
> /*module pfla02 rev2*/
> reset-gpio = <&gpio2 23 0>;
> wake-up-gpio = <&gpio1 7 0>;
> disable-gpio = <&gpio4 17 1>;
> #endif
> };
>
> But Im still stuck on the bus ressource affectation, Bjorn Helgaas said that
> normally it is auto affected by the host bridge driver ?
> Is there a patch to fix this ?
>
> imx6q-pcie 1ffc000.pcie: reset-gpio number is 55 imx6q-pcie 1ffc000.pcie:
> power-on-gpio number is -2 imx6q-pcie 1ffc000.pcie: wake-up-gpio number is 7
> imx6q-pcie 1ffc000.pcie: disable-gpio number is 113 PCI host bridge to bus
> 0000:00 pci_bus 0000:00: root bus resource [io 0x1000-0x10000] pci_bus
> 0000:00: root bus resource [mem 0x01000000-0x01efffff] pci_bus 0000:00: No
> busn resource found for root bus, will use [bus 00-ff]
> PCI: bus0: Fast back to back transfers disabled
> PCI: bus1: Fast back to back transfers disabled pci 0000:00:00.0: BAR 0:
> assigned [mem 0x01000000-0x010fffff] pci 0000:00:00.0: BAR 9: assigned [mem
> 0x01100000-0x011fffff pref] pci 0000:00:00.0: BAR 6: assigned [mem 0x01200000-
> 0x0120ffff pref] pci 0000:01:00.0: BAR 0: assigned [mem 0x01100000-0x01100fff
> 64bit pref] pci 0000:00:00.0: PCI bridge to [bus 01]
> pci 0000:00:00.0: bridge window [mem 0x01100000-0x011fffff pref]
> pci 0000:00:00.0: PCI bridge to [bus 01]
> pci 0000:00:00.0: bridge window [mem 0x01100000-0x011fffff pref]
>
[Richard] Tested pci-v3.13-fixes-2 on imx6q sabresd board, the dts modifications of imx6qdl-sabresd.dtsi
are listed below:
&pcie {
power-on-gpio = <&gpio3 19 0>;
reset-gpio = <&gpio7 12 0>;
status = "okay";
};
Logs:
[ 0.327515] cfg80211: Calling CRDA to update world regulatory domain
[ 0.329373] Switched to clocksource mxc_timer1
[ 0.462992] PCI host bridge to bus 0000:00
[ 0.463012] pci_bus 0000:00: root bus resource [io 0x1000-0x10000]
[ 0.463026] pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]
[ 0.463050] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
[ 0.463190] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
[ 0.463255] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
[ 0.463309] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
[ 0.463481] pci 0000:00:00.0: supports D1
[ 0.463494] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
[ 0.464120] PCI: bus0: Fast back to back transfers disabled
[ 0.464684] pci 0000:01:00.0: [1033:0194] type 00 class 0x0c0330
[ 0.464933] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00001fff 64bit]
[ 0.465892] pci 0000:01:00.0: PME# supported from D0 D3hot
[ 0.466758] PCI: bus1: Fast back to back transfers disabled
[ 0.466778] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 0.466802] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
[ 0.466933] pci 0000:00:00.0: BAR 0: assigned [mem 0x01000000-0x010fffff]
[ 0.466960] pci 0000:00:00.0: BAR 8: assigned [mem 0x01100000-0x011fffff]
[ 0.466974] pci 0000:00:00.0: BAR 6: assigned [mem 0x01200000-0x0120ffff pref]
[ 0.466992] pci 0000:01:00.0: BAR 0: assigned [mem 0x01100000-0x01101fff 64bit]
[ 0.467141] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 0.467165] pci 0000:00:00.0: bridge window [mem 0x01100000-0x011fffff]
[ 0.467208] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 0.467231] pci 0000:00:00.0: bridge window [mem 0x01100000-0x011fffff]
[ 0.467265] pci_bus 0000:00: resource 4 [io 0x1000-0x10000]
[ 0.467277] pci_bus 0000:00: resource 5 [mem 0x01000000-0x01efffff]
[ 0.467288] pci_bus 0000:01: resource 1 [mem 0x01100000-0x011fffff]
[ 0.486674] NET: Registered protocol family 2
root at imx6qdlsolo:~# lspci -v
00:00.0 PCI bridge: Device 16c3:abcd (rev 01) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0
Memory at 01000000 (32-bit, non-prefetchable) [size=1M]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Memory behind bridge: 01100000-011fffff
[virtual] Expansion ROM at 01200000 [disabled] [size=64K]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Virtual Channel
Kernel driver in use: pcieport
lspci: Unable to load libkmod resources: error -12
01:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 03) (prog-if 30 [XHCI])
Flags: bus master, fast devsel, latency 0, IRQ 155
Memory at 01100000 (64-bit, non-prefetchable) [size=8K]
Capabilities: [50] Power Management version 3
Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+
Capabilities: [90] MSI-X: Enable- Count=8 Masked-
Capabilities: [a0] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Device Serial Number ff-ff-ff-ff-ff-ff-ff-ff
Capabilities: [150] Latency Tolerance Reporting
Kernel driver in use: xhci_hcd
root at imx6qdlsolo:~# uname -a
Linux imx6qdlsolo 3.13.0-rc1+ #409 SMP Fri Feb 7 11:43:01 CST 2014 armv7l GNU/Linux
root at imx6qdlsolo:~#
> BR, Kamel B.
>
Best Regards
Richard Zhu
^ permalink raw reply
* [PATCH 2/2 v4] i2c: exynos5: configure fifo_depth based on HSI2C module variant
From: Naveen Krishna Chatradhi @ 2014-02-07 4:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1385100851-32254-1-git-send-email-ch.naveen@samsung.com>
fifo_depth of the HSI2C is not constant
Exynos5420 and Exynos5250 supports fifo_depth of 64bytes
Exynos5260 supports fifo_depth of 16bytes.
This patch configures the fifo_depth based on HSI2C modules version.
Signed-off-by: Naveen Krishna Chatradhi <ich.naveen@samsung.com>
[For finding out the difference and initial contribution]
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
changes since v3:
use variant struct to handle the fifo depths
drivers/i2c/busses/i2c-exynos5.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 12730d1..5c875c0 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -76,12 +76,6 @@
#define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
#define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
-/* As per user manual FIFO max depth is 64bytes */
-#define HSI2C_FIFO_MAX 0x40
-/* default trigger levels for Tx and Rx FIFOs */
-#define HSI2C_DEF_TXFIFO_LVL (HSI2C_FIFO_MAX - 0x30)
-#define HSI2C_DEF_RXFIFO_LVL (HSI2C_FIFO_MAX - 0x10)
-
/* I2C_TRAILING_CTL Register bits */
#define HSI2C_TRAILING_COUNT (0xf)
@@ -455,7 +449,7 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
- len = HSI2C_FIFO_MAX - fifo_level;
+ len = i2c->variant->fifo_depth - fifo_level;
if (len > (i2c->msg->len - i2c->msg_ptr))
len = i2c->msg->len - i2c->msg_ptr;
@@ -523,6 +517,7 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
u32 i2c_auto_conf = 0;
u32 fifo_ctl;
unsigned long flags;
+ unsigned short trig_lvl;
i2c_ctl = readl(i2c->regs + HSI2C_CTL);
i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
@@ -533,13 +528,19 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
i2c_auto_conf = HSI2C_READ_WRITE;
- fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(HSI2C_DEF_TXFIFO_LVL);
+ trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
+ (i2c->variant->fifo_depth * 3/4) : i2c->msg->len;
+ fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
+
int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
HSI2C_INT_TRAILING_EN);
} else {
i2c_ctl |= HSI2C_TXCHON;
- fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(HSI2C_DEF_RXFIFO_LVL);
+ trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
+ (i2c->variant->fifo_depth * 1/4) : i2c->msg->len;
+ fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
+
int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
}
@@ -731,6 +732,8 @@ static int exynos5_i2c_probe(struct platform_device *pdev)
if (ret)
goto err_clk;
+ i2c->variant = exynos5_i2c_get_variant(pdev);
+
exynos5_i2c_reset(i2c);
ret = i2c_add_adapter(&i2c->adap);
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/2 v4] i2c: exynos5: add support for HSI2C on Exynos5260 SoC
From: Naveen Krishna Chatradhi @ 2014-02-07 4:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1385100726-32165-1-git-send-email-ch.naveen@samsung.com>
This patch adds a new compatible and uses variant struct to support
HSI2C module on Exynos5260. Updates the Documentation dt bindings.
Also resets the module as an init sequence (Needed by Exynos5260).
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v3:
1. split patches as (v1 version does)
add exynso5260 suppport and handle fifo depths
2. keep the old - compatible = "samsung,exynos5-hsi2c";
mark it as (DEPRECATED)
.../devicetree/bindings/i2c/i2c-exynos5.txt | 11 ++++-
drivers/i2c/busses/i2c-exynos5.c | 46 ++++++++++++++++++--
2 files changed, 52 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
index 056732c..d4745e3 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -5,7 +5,14 @@ at various speeds ranging from 100khz to 3.4Mhz.
Required properties:
- compatible: value should be.
- -> "samsung,exynos5-hsi2c", for i2c compatible with exynos5 hsi2c.
+ -> "samsung,exynos5-hsi2c", (DEPRECATED)
+ for i2c compatible with HSI2C available
+ on Exynos5250 and Exynos5420 SoCs.
+ -> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available
+ on Exynos5250 and Exynos5420 SoCs.
+ -> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available
+ on Exynos5260 SoCs.
+
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
@@ -26,7 +33,7 @@ Optional properties:
Example:
hsi2c at 12ca0000 {
- compatible = "samsung,exynos5-hsi2c";
+ compatible = "samsung,exynos5250-hsi2c";
reg = <0x12ca0000 0x100>;
interrupts = <56>;
clock-frequency = <100000>;
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 9fd711c..12730d1 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -183,14 +183,54 @@ struct exynos5_i2c {
* 2. Fast speed upto 1Mbps
*/
int speed_mode;
+
+ /* Version of HS-I2C Hardware */
+ struct exynos_hsi2c_variant *variant;
+};
+
+/**
+ * struct exynos_hsi2c_variant - platform specific HSI2C driver data
+ * @fifo_depth: the fifo depth supported by the HSI2C module
+ *
+ * Specifies platform specific configuration of HSI2C module.
+ * Note: A structure for driver specific platform data is used for future
+ * expansion of its usage.
+ */
+struct exynos_hsi2c_variant {
+ unsigned int fifo_depth;
+};
+
+static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
+ .fifo_depth = 64,
+};
+
+static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
+ .fifo_depth = 16,
};
static const struct of_device_id exynos5_i2c_match[] = {
- { .compatible = "samsung,exynos5-hsi2c" },
- {},
+ {
+ .compatible = "samsung,exynos5-hsi2c"
+ .data = &exynos5250_hsi2c_data
+ }, {
+ .compatible = "samsung,exynos5250-hsi2c",
+ .data = &exynos5250_hsi2c_data
+ }, {
+ .compatible = "samsung,exynos5260-hsi2c",
+ .data = &exynos5260_hsi2c_data
+ }, {},
};
MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
+static inline struct exynos_hsi2c_variant *exynos5_i2c_get_variant
+ (struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos5_i2c_match, pdev->dev.of_node);
+ return (struct exynos_hsi2c_variant *)match->data;
+}
+
static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
{
writel(readl(i2c->regs + HSI2C_INT_STATUS),
@@ -691,7 +731,7 @@ static int exynos5_i2c_probe(struct platform_device *pdev)
if (ret)
goto err_clk;
- exynos5_i2c_init(i2c);
+ exynos5_i2c_reset(i2c);
ret = i2c_add_adapter(&i2c->adap);
if (ret < 0) {
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 6/6] ARM: tegra: cpuidle: use firmware for power down
From: Alexandre Courbot @ 2014-02-07 4:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391747706-1847-1-git-send-email-acourbot@nvidia.com>
Attempt to invoke the prepare_idle() and do_idle() firmware calls
to power down a CPU so an underlying firmware gets informed of
the idle operation and performs it by itself if designed in such a way.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
arch/arm/mach-tegra/cpuidle-tegra114.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index e0b87300243d..558067ddc186 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -19,6 +19,7 @@
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/clockchips.h>
+#include <asm/firmware.h>
#include <asm/cpuidle.h>
#include <asm/suspend.h>
@@ -45,7 +46,15 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
- cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+ call_firmware_op(prepare_idle);
+
+ switch (call_firmware_op(do_idle)) {
+ case -ENOSYS:
+ cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+ break;
+ default:
+ break;
+ }
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
--
1.8.5.3
^ permalink raw reply related
* [PATCH v2 5/6] ARM: trusted_foundations: implement prepare_idle()
From: Alexandre Courbot @ 2014-02-07 4:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391747706-1847-1-git-send-email-acourbot@nvidia.com>
Support the prepare_idle() firmware call, which is necessary to properly
support CPU idling.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
arch/arm/firmware/trusted_foundations.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c
index ef1e3d8f4af0..3fb1b5a1dce9 100644
--- a/arch/arm/firmware/trusted_foundations.c
+++ b/arch/arm/firmware/trusted_foundations.c
@@ -22,6 +22,15 @@
#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
+#define TF_CPU_PM 0xfffffffc
+#define TF_CPU_PM_S3 0xffffffe3
+#define TF_CPU_PM_S2 0xffffffe6
+#define TF_CPU_PM_S2_NO_MC_CLK 0xffffffe5
+#define TF_CPU_PM_S1 0xffffffe4
+#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
+
+static unsigned long cpu_boot_addr;
+
static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2)
{
asm volatile(
@@ -41,13 +50,22 @@ static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2)
static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
{
- tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0);
+ cpu_boot_addr = boot_addr;
+ tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);
+
+ return 0;
+}
+
+static int tf_prepare_idle(void)
+{
+ tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2, cpu_boot_addr);
return 0;
}
static const struct firmware_ops trusted_foundations_ops = {
.set_cpu_boot_addr = tf_set_cpu_boot_addr,
+ .prepare_idle = tf_prepare_idle,
};
void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
--
1.8.5.3
^ permalink raw reply related
* [PATCH v2 4/6] ARM: firmware: add prepare_idle() operation
From: Alexandre Courbot @ 2014-02-07 4:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391747706-1847-1-git-send-email-acourbot@nvidia.com>
Some firmwares do not put the CPU into idle mode themselves, but still
need to be informed that the CPU is about to enter idle mode before this
happens. Add a prepare_idle() operation to the firmware_ops structure to
handle such cases.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
arch/arm/include/asm/firmware.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
index 15631300c238..2c9f10df7568 100644
--- a/arch/arm/include/asm/firmware.h
+++ b/arch/arm/include/asm/firmware.h
@@ -22,6 +22,10 @@
*/
struct firmware_ops {
/*
+ * Inform the firmware we intend to enter CPU idle mode
+ */
+ int (*prepare_idle)(void);
+ /*
* Enters CPU idle mode
*/
int (*do_idle)(void);
--
1.8.5.3
^ permalink raw reply related
* [PATCH v2 3/6] ARM: firmware: enable Trusted Foundations by default
From: Alexandre Courbot @ 2014-02-07 4:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391747706-1847-1-git-send-email-acourbot@nvidia.com>
As discussed previously (https://lkml.org/lkml/2013/11/26/289), enable
Trusted Foundation support by default since it already depends on a
supporting architecture being selected.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
arch/arm/firmware/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig
index bb126594995e..ad396af68e47 100644
--- a/arch/arm/firmware/Kconfig
+++ b/arch/arm/firmware/Kconfig
@@ -11,6 +11,7 @@ menu "Firmware options"
config TRUSTED_FOUNDATIONS
bool "Trusted Foundations secure monitor support"
depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
+ default y
help
Some devices (including most Tegra-based consumer devices on the
market) are booted with the Trusted Foundations secure monitor
--
1.8.5.3
^ permalink raw reply related
* [PATCH v2 2/6] ARM: trusted_foundations: fallback when TF support is missing
From: Alexandre Courbot @ 2014-02-07 4:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391747706-1847-1-git-send-email-acourbot@nvidia.com>
When Trusted Foundations is detected as present on the system, but
Trusted Foundations support is not built into the kernel, the kernel
used to issue a panic very early during boot, leaving little clue to the
user as to what is going wrong.
It turns out that even without TF support built-in, the kernel can boot
on a TF-enabled system provided that SMP and cpuidle are disabled. This
patch does this and continue booting on one CPU, leaving the user with a
usable (however degraded) system.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
arch/arm/include/asm/trusted_foundations.h | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h
index 997862fd5d77..b5f7705abcb0 100644
--- a/arch/arm/include/asm/trusted_foundations.h
+++ b/arch/arm/include/asm/trusted_foundations.h
@@ -30,6 +30,8 @@
#include <linux/printk.h>
#include <linux/bug.h>
#include <linux/of.h>
+#include <linux/cpu.h>
+#include <linux/smp.h>
struct trusted_foundations_platform_data {
unsigned int version_major;
@@ -47,10 +49,13 @@ static inline void register_trusted_foundations(
struct trusted_foundations_platform_data *pd)
{
/*
- * If we try to register TF, this means the system needs it to continue.
- * Its absence if thus a fatal error.
+ * If the system requires TF and we cannot provide it, continue booting
+ * but disable features that cannot be provided.
*/
- panic("No support for Trusted Foundations, stopping...\n");
+ pr_err("No support for Trusted Foundations, continuing in degraded mode.\n");
+ pr_err("Secondary processors as well as CPU PM will be disabled.\n");
+ setup_max_cpus = 0;
+ cpu_idle_poll_ctrl(true);
}
static inline void of_register_trusted_foundations(void)
--
1.8.5.3
^ permalink raw reply related
* [PATCH v2 1/6] ARM: trusted_foundations: fix vendor prefix typos
From: Alexandre Courbot @ 2014-02-07 4:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391747706-1847-1-git-send-email-acourbot@nvidia.com>
of_register_trusted_foundations() and the firmware Kconfig used
the wrong vendor prefix for Trusted Logic Mobility.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
arch/arm/firmware/Kconfig | 2 +-
arch/arm/include/asm/trusted_foundations.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig
index bb00ccf00d66..bb126594995e 100644
--- a/arch/arm/firmware/Kconfig
+++ b/arch/arm/firmware/Kconfig
@@ -20,7 +20,7 @@ config TRUSTED_FOUNDATIONS
This option allows the kernel to invoke the secure monitor whenever
required on devices using Trusted Foundations. See
arch/arm/include/asm/trusted_foundations.h or the
- tl,trusted-foundations device tree binding documentation for details
+ tlm,trusted-foundations device tree binding documentation for details
on how to use it.
Say n if you don't know what this is about.
diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h
index 3bd36e2c5f2e..997862fd5d77 100644
--- a/arch/arm/include/asm/trusted_foundations.h
+++ b/arch/arm/include/asm/trusted_foundations.h
@@ -59,7 +59,7 @@ static inline void of_register_trusted_foundations(void)
* If we find the target should enable TF but does not support it,
* fail as the system won't be able to do much anyway
*/
- if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations"))
+ if (of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations"))
register_trusted_foundations(NULL);
}
#endif /* CONFIG_TRUSTED_FOUNDATIONS */
--
1.8.5.3
^ permalink raw reply related
* [PATCH v2 0/6] ARM: firmware: improvements to Trusted Foundations support
From: Alexandre Courbot @ 2014-02-07 4:35 UTC (permalink / raw)
To: linux-arm-kernel
These (mostly minor) patches fix a few typos, improve points that
were agreed upon when the Trusted Foundation series was initially
submitted, and more importantly add support for a prepare_idle()
firmware operation that informs the firmware a CPU is doing idle.
Tegra's cpuidle driver is then also updated accordingly.
These patches should be the last step before device trees for NVIDIA
SHIELD and Tegra Note 7 can be submitted.
Changes since v1:
- Do not remove TF support from tegra_defconfig (will automatically be taken
care of during next configuration update)
- Add a new prepare_idle() operation to firmware_ops that informs the firmware
a CPU is going idle (vs. asking the firmware to do it itself as do_idle()
does)
- Fix idle states names in TF implementation of prepare_idle to sound less
Tegra-specific
Alexandre Courbot (6):
ARM: trusted_foundations: fix vendor prefix typos
ARM: trusted_foundations: fallback when TF support is missing
ARM: firmware: enable Trusted Foundations by default
ARM: firmware: add prepare_idle() operation
ARM: trusted_foundations: implement prepare_idle()
ARM: tegra: cpuidle: use firmware for power down
arch/arm/firmware/Kconfig | 3 ++-
arch/arm/firmware/trusted_foundations.c | 20 +++++++++++++++++++-
arch/arm/include/asm/firmware.h | 4 ++++
arch/arm/include/asm/trusted_foundations.h | 13 +++++++++----
arch/arm/mach-tegra/cpuidle-tegra114.c | 11 ++++++++++-
5 files changed, 44 insertions(+), 7 deletions(-)
--
1.8.5.3
^ permalink raw reply
* [PATCH v5 00/14] Add support for MSM's mmio clock/reset controller
From: Frank Rowand @ 2014-02-07 4:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F45DEE.8020400@gmail.com>
On 2/6/2014 8:15 PM, Frank Rowand wrote:
> On 1/15/2014 10:47 AM, Stephen Boyd wrote:
>> The first breaks a reset-controller include ordering requirement. It got
>> an ack so I think we're ok for it to go through the clock tree.
>>
>
> < snip >
>
> checkpatch is whining about patches
>
< snip >
Never mind.... I see that the patches are already in 3.14-rc1.
-Frank
^ permalink raw reply
* [PATCH] iommu/exynos: Remove driver
From: Inki Dae @ 2014-02-07 4:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391716317-20300-1-git-send-email-olof@lixom.net>
2014-02-07 Olof Johansson <olof@lixom.net>:
> The driver has been unbuildable due to unfulfilled dependencies since
> 3.11, and even if enabled it won't build due to build breakage. Emails
> about status on this have gone unanswered, and fixes seem to have been
> abandoned.
>
> It's obvious that nobody cares about it, so let's remove it.
Wait, we are going to fix up this module. It seems that KyoungHo,
original author, is busy with some works related to product.
we can care about it if KyoungHo cannot afford to care for the time being.
Thanks,
Inki Dae
>
> Signed-off-by: Olof Johansson <olof@lixom.net>
> ---
> drivers/iommu/Kconfig | 21 -
> drivers/iommu/Makefile | 1 -
> drivers/iommu/exynos-iommu.c | 1035 ------------------------------------------
> 3 files changed, 1057 deletions(-)
> delete mode 100644 drivers/iommu/exynos-iommu.c
>
> diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
> index 79bbc21..b893367 100644
> --- a/drivers/iommu/Kconfig
> +++ b/drivers/iommu/Kconfig
> @@ -176,27 +176,6 @@ config TEGRA_IOMMU_SMMU
> space through the SMMU (System Memory Management Unit)
> hardware included on Tegra SoCs.
>
> -config EXYNOS_IOMMU
> - bool "Exynos IOMMU Support"
> - depends on ARCH_EXYNOS && EXYNOS_DEV_SYSMMU
> - select IOMMU_API
> - help
> - Support for the IOMMU(System MMU) of Samsung Exynos application
> - processor family. This enables H/W multimedia accellerators to see
> - non-linear physical memory chunks as a linear memory in their
> - address spaces
> -
> - If unsure, say N here.
> -
> -config EXYNOS_IOMMU_DEBUG
> - bool "Debugging log for Exynos IOMMU"
> - depends on EXYNOS_IOMMU
> - help
> - Select this to see the detailed log message that shows what
> - happens in the IOMMU driver
> -
> - Say N unless you need kernel log message for IOMMU debugging
> -
> config SHMOBILE_IPMMU
> bool
>
> diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
> index 5d58bf1..de6c909 100644
> --- a/drivers/iommu/Makefile
> +++ b/drivers/iommu/Makefile
> @@ -14,7 +14,6 @@ obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o
> obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
> obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o
> obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o
> -obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
> obj-$(CONFIG_SHMOBILE_IOMMU) += shmobile-iommu.o
> obj-$(CONFIG_SHMOBILE_IPMMU) += shmobile-ipmmu.o
> obj-$(CONFIG_FSL_PAMU) += fsl_pamu.o fsl_pamu_domain.o
> diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
> deleted file mode 100644
> index 0740189..0000000
> --- a/drivers/iommu/exynos-iommu.c
> +++ /dev/null
> @@ -1,1035 +0,0 @@
> -/* linux/drivers/iommu/exynos_iommu.c
> - *
> - * Copyright (c) 2011 Samsung Electronics Co., Ltd.
> - * http://www.samsung.com
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#ifdef CONFIG_EXYNOS_IOMMU_DEBUG
> -#define DEBUG
> -#endif
> -
> -#include <linux/io.h>
> -#include <linux/interrupt.h>
> -#include <linux/platform_device.h>
> -#include <linux/slab.h>
> -#include <linux/pm_runtime.h>
> -#include <linux/clk.h>
> -#include <linux/err.h>
> -#include <linux/mm.h>
> -#include <linux/iommu.h>
> -#include <linux/errno.h>
> -#include <linux/list.h>
> -#include <linux/memblock.h>
> -#include <linux/export.h>
> -
> -#include <asm/cacheflush.h>
> -#include <asm/pgtable.h>
> -
> -#include <mach/sysmmu.h>
> -
> -/* We does not consider super section mapping (16MB) */
> -#define SECT_ORDER 20
> -#define LPAGE_ORDER 16
> -#define SPAGE_ORDER 12
> -
> -#define SECT_SIZE (1 << SECT_ORDER)
> -#define LPAGE_SIZE (1 << LPAGE_ORDER)
> -#define SPAGE_SIZE (1 << SPAGE_ORDER)
> -
> -#define SECT_MASK (~(SECT_SIZE - 1))
> -#define LPAGE_MASK (~(LPAGE_SIZE - 1))
> -#define SPAGE_MASK (~(SPAGE_SIZE - 1))
> -
> -#define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
> -#define lv1ent_page(sent) ((*(sent) & 3) == 1)
> -#define lv1ent_section(sent) ((*(sent) & 3) == 2)
> -
> -#define lv2ent_fault(pent) ((*(pent) & 3) == 0)
> -#define lv2ent_small(pent) ((*(pent) & 2) == 2)
> -#define lv2ent_large(pent) ((*(pent) & 3) == 1)
> -
> -#define section_phys(sent) (*(sent) & SECT_MASK)
> -#define section_offs(iova) ((iova) & 0xFFFFF)
> -#define lpage_phys(pent) (*(pent) & LPAGE_MASK)
> -#define lpage_offs(iova) ((iova) & 0xFFFF)
> -#define spage_phys(pent) (*(pent) & SPAGE_MASK)
> -#define spage_offs(iova) ((iova) & 0xFFF)
> -
> -#define lv1ent_offset(iova) ((iova) >> SECT_ORDER)
> -#define lv2ent_offset(iova) (((iova) & 0xFF000) >> SPAGE_ORDER)
> -
> -#define NUM_LV1ENTRIES 4096
> -#define NUM_LV2ENTRIES 256
> -
> -#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
> -
> -#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
> -
> -#define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
> -
> -#define mk_lv1ent_sect(pa) ((pa) | 2)
> -#define mk_lv1ent_page(pa) ((pa) | 1)
> -#define mk_lv2ent_lpage(pa) ((pa) | 1)
> -#define mk_lv2ent_spage(pa) ((pa) | 2)
> -
> -#define CTRL_ENABLE 0x5
> -#define CTRL_BLOCK 0x7
> -#define CTRL_DISABLE 0x0
> -
> -#define REG_MMU_CTRL 0x000
> -#define REG_MMU_CFG 0x004
> -#define REG_MMU_STATUS 0x008
> -#define REG_MMU_FLUSH 0x00C
> -#define REG_MMU_FLUSH_ENTRY 0x010
> -#define REG_PT_BASE_ADDR 0x014
> -#define REG_INT_STATUS 0x018
> -#define REG_INT_CLEAR 0x01C
> -
> -#define REG_PAGE_FAULT_ADDR 0x024
> -#define REG_AW_FAULT_ADDR 0x028
> -#define REG_AR_FAULT_ADDR 0x02C
> -#define REG_DEFAULT_SLAVE_ADDR 0x030
> -
> -#define REG_MMU_VERSION 0x034
> -
> -#define REG_PB0_SADDR 0x04C
> -#define REG_PB0_EADDR 0x050
> -#define REG_PB1_SADDR 0x054
> -#define REG_PB1_EADDR 0x058
> -
> -static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
> -{
> - return pgtable + lv1ent_offset(iova);
> -}
> -
> -static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
> -{
> - return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
> -}
> -
> -enum exynos_sysmmu_inttype {
> - SYSMMU_PAGEFAULT,
> - SYSMMU_AR_MULTIHIT,
> - SYSMMU_AW_MULTIHIT,
> - SYSMMU_BUSERROR,
> - SYSMMU_AR_SECURITY,
> - SYSMMU_AR_ACCESS,
> - SYSMMU_AW_SECURITY,
> - SYSMMU_AW_PROTECTION, /* 7 */
> - SYSMMU_FAULT_UNKNOWN,
> - SYSMMU_FAULTS_NUM
> -};
> -
> -/*
> - * @itype: type of fault.
> - * @pgtable_base: the physical address of page table base. This is 0 if @itype
> - * is SYSMMU_BUSERROR.
> - * @fault_addr: the device (virtual) address that the System MMU tried to
> - * translated. This is 0 if @itype is SYSMMU_BUSERROR.
> - */
> -typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype,
> - unsigned long pgtable_base, unsigned long fault_addr);
> -
> -static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
> - REG_PAGE_FAULT_ADDR,
> - REG_AR_FAULT_ADDR,
> - REG_AW_FAULT_ADDR,
> - REG_DEFAULT_SLAVE_ADDR,
> - REG_AR_FAULT_ADDR,
> - REG_AR_FAULT_ADDR,
> - REG_AW_FAULT_ADDR,
> - REG_AW_FAULT_ADDR
> -};
> -
> -static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
> - "PAGE FAULT",
> - "AR MULTI-HIT FAULT",
> - "AW MULTI-HIT FAULT",
> - "BUS ERROR",
> - "AR SECURITY PROTECTION FAULT",
> - "AR ACCESS PROTECTION FAULT",
> - "AW SECURITY PROTECTION FAULT",
> - "AW ACCESS PROTECTION FAULT",
> - "UNKNOWN FAULT"
> -};
> -
> -struct exynos_iommu_domain {
> - struct list_head clients; /* list of sysmmu_drvdata.node */
> - unsigned long *pgtable; /* lv1 page table, 16KB */
> - short *lv2entcnt; /* free lv2 entry counter for each section */
> - spinlock_t lock; /* lock for this structure */
> - spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
> -};
> -
> -struct sysmmu_drvdata {
> - struct list_head node; /* entry of exynos_iommu_domain.clients */
> - struct device *sysmmu; /* System MMU's device descriptor */
> - struct device *dev; /* Owner of system MMU */
> - char *dbgname;
> - int nsfrs;
> - void __iomem **sfrbases;
> - struct clk *clk[2];
> - int activations;
> - rwlock_t lock;
> - struct iommu_domain *domain;
> - sysmmu_fault_handler_t fault_handler;
> - unsigned long pgtable;
> -};
> -
> -static bool set_sysmmu_active(struct sysmmu_drvdata *data)
> -{
> - /* return true if the System MMU was not active previously
> - and it needs to be initialized */
> - return ++data->activations == 1;
> -}
> -
> -static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
> -{
> - /* return true if the System MMU is needed to be disabled */
> - BUG_ON(data->activations < 1);
> - return --data->activations == 0;
> -}
> -
> -static bool is_sysmmu_active(struct sysmmu_drvdata *data)
> -{
> - return data->activations > 0;
> -}
> -
> -static void sysmmu_unblock(void __iomem *sfrbase)
> -{
> - __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
> -}
> -
> -static bool sysmmu_block(void __iomem *sfrbase)
> -{
> - int i = 120;
> -
> - __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
> - while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1))
> - --i;
> -
> - if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) {
> - sysmmu_unblock(sfrbase);
> - return false;
> - }
> -
> - return true;
> -}
> -
> -static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
> -{
> - __raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
> -}
> -
> -static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
> - unsigned long iova)
> -{
> - __raw_writel((iova & SPAGE_MASK) | 1, sfrbase + REG_MMU_FLUSH_ENTRY);
> -}
> -
> -static void __sysmmu_set_ptbase(void __iomem *sfrbase,
> - unsigned long pgd)
> -{
> - __raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */
> - __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
> -
> - __sysmmu_tlb_invalidate(sfrbase);
> -}
> -
> -static void __sysmmu_set_prefbuf(void __iomem *sfrbase, unsigned long base,
> - unsigned long size, int idx)
> -{
> - __raw_writel(base, sfrbase + REG_PB0_SADDR + idx * 8);
> - __raw_writel(size - 1 + base, sfrbase + REG_PB0_EADDR + idx * 8);
> -}
> -
> -static void __set_fault_handler(struct sysmmu_drvdata *data,
> - sysmmu_fault_handler_t handler)
> -{
> - unsigned long flags;
> -
> - write_lock_irqsave(&data->lock, flags);
> - data->fault_handler = handler;
> - write_unlock_irqrestore(&data->lock, flags);
> -}
> -
> -void exynos_sysmmu_set_fault_handler(struct device *dev,
> - sysmmu_fault_handler_t handler)
> -{
> - struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> -
> - __set_fault_handler(data, handler);
> -}
> -
> -static int default_fault_handler(enum exynos_sysmmu_inttype itype,
> - unsigned long pgtable_base, unsigned long fault_addr)
> -{
> - unsigned long *ent;
> -
> - if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
> - itype = SYSMMU_FAULT_UNKNOWN;
> -
> - pr_err("%s occurred at 0x%lx(Page table base: 0x%lx)\n",
> - sysmmu_fault_name[itype], fault_addr, pgtable_base);
> -
> - ent = section_entry(__va(pgtable_base), fault_addr);
> - pr_err("\tLv1 entry: 0x%lx\n", *ent);
> -
> - if (lv1ent_page(ent)) {
> - ent = page_entry(ent, fault_addr);
> - pr_err("\t Lv2 entry: 0x%lx\n", *ent);
> - }
> -
> - pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
> -
> - BUG();
> -
> - return 0;
> -}
> -
> -static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
> -{
> - /* SYSMMU is in blocked when interrupt occurred. */
> - struct sysmmu_drvdata *data = dev_id;
> - struct resource *irqres;
> - struct platform_device *pdev;
> - enum exynos_sysmmu_inttype itype;
> - unsigned long addr = -1;
> -
> - int i, ret = -ENOSYS;
> -
> - read_lock(&data->lock);
> -
> - WARN_ON(!is_sysmmu_active(data));
> -
> - pdev = to_platform_device(data->sysmmu);
> - for (i = 0; i < (pdev->num_resources / 2); i++) {
> - irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
> - if (irqres && ((int)irqres->start == irq))
> - break;
> - }
> -
> - if (i == pdev->num_resources) {
> - itype = SYSMMU_FAULT_UNKNOWN;
> - } else {
> - itype = (enum exynos_sysmmu_inttype)
> - __ffs(__raw_readl(data->sfrbases[i] + REG_INT_STATUS));
> - if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
> - itype = SYSMMU_FAULT_UNKNOWN;
> - else
> - addr = __raw_readl(
> - data->sfrbases[i] + fault_reg_offset[itype]);
> - }
> -
> - if (data->domain)
> - ret = report_iommu_fault(data->domain, data->dev,
> - addr, itype);
> -
> - if ((ret == -ENOSYS) && data->fault_handler) {
> - unsigned long base = data->pgtable;
> - if (itype != SYSMMU_FAULT_UNKNOWN)
> - base = __raw_readl(
> - data->sfrbases[i] + REG_PT_BASE_ADDR);
> - ret = data->fault_handler(itype, base, addr);
> - }
> -
> - if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
> - __raw_writel(1 << itype, data->sfrbases[i] + REG_INT_CLEAR);
> - else
> - dev_dbg(data->sysmmu, "(%s) %s is not handled.\n",
> - data->dbgname, sysmmu_fault_name[itype]);
> -
> - if (itype != SYSMMU_FAULT_UNKNOWN)
> - sysmmu_unblock(data->sfrbases[i]);
> -
> - read_unlock(&data->lock);
> -
> - return IRQ_HANDLED;
> -}
> -
> -static bool __exynos_sysmmu_disable(struct sysmmu_drvdata *data)
> -{
> - unsigned long flags;
> - bool disabled = false;
> - int i;
> -
> - write_lock_irqsave(&data->lock, flags);
> -
> - if (!set_sysmmu_inactive(data))
> - goto finish;
> -
> - for (i = 0; i < data->nsfrs; i++)
> - __raw_writel(CTRL_DISABLE, data->sfrbases[i] + REG_MMU_CTRL);
> -
> - if (data->clk[1])
> - clk_disable(data->clk[1]);
> - if (data->clk[0])
> - clk_disable(data->clk[0]);
> -
> - disabled = true;
> - data->pgtable = 0;
> - data->domain = NULL;
> -finish:
> - write_unlock_irqrestore(&data->lock, flags);
> -
> - if (disabled)
> - dev_dbg(data->sysmmu, "(%s) Disabled\n", data->dbgname);
> - else
> - dev_dbg(data->sysmmu, "(%s) %d times left to be disabled\n",
> - data->dbgname, data->activations);
> -
> - return disabled;
> -}
> -
> -/* __exynos_sysmmu_enable: Enables System MMU
> - *
> - * returns -error if an error occurred and System MMU is not enabled,
> - * 0 if the System MMU has been just enabled and 1 if System MMU was already
> - * enabled before.
> - */
> -static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data,
> - unsigned long pgtable, struct iommu_domain *domain)
> -{
> - int i, ret = 0;
> - unsigned long flags;
> -
> - write_lock_irqsave(&data->lock, flags);
> -
> - if (!set_sysmmu_active(data)) {
> - if (WARN_ON(pgtable != data->pgtable)) {
> - ret = -EBUSY;
> - set_sysmmu_inactive(data);
> - } else {
> - ret = 1;
> - }
> -
> - dev_dbg(data->sysmmu, "(%s) Already enabled\n", data->dbgname);
> - goto finish;
> - }
> -
> - if (data->clk[0])
> - clk_enable(data->clk[0]);
> - if (data->clk[1])
> - clk_enable(data->clk[1]);
> -
> - data->pgtable = pgtable;
> -
> - for (i = 0; i < data->nsfrs; i++) {
> - __sysmmu_set_ptbase(data->sfrbases[i], pgtable);
> -
> - if ((readl(data->sfrbases[i] + REG_MMU_VERSION) >> 28) == 3) {
> - /* System MMU version is 3.x */
> - __raw_writel((1 << 12) | (2 << 28),
> - data->sfrbases[i] + REG_MMU_CFG);
> - __sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 0);
> - __sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 1);
> - }
> -
> - __raw_writel(CTRL_ENABLE, data->sfrbases[i] + REG_MMU_CTRL);
> - }
> -
> - data->domain = domain;
> -
> - dev_dbg(data->sysmmu, "(%s) Enabled\n", data->dbgname);
> -finish:
> - write_unlock_irqrestore(&data->lock, flags);
> -
> - return ret;
> -}
> -
> -int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable)
> -{
> - struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> - int ret;
> -
> - BUG_ON(!memblock_is_memory(pgtable));
> -
> - ret = pm_runtime_get_sync(data->sysmmu);
> - if (ret < 0) {
> - dev_dbg(data->sysmmu, "(%s) Failed to enable\n", data->dbgname);
> - return ret;
> - }
> -
> - ret = __exynos_sysmmu_enable(data, pgtable, NULL);
> - if (WARN_ON(ret < 0)) {
> - pm_runtime_put(data->sysmmu);
> - dev_err(data->sysmmu,
> - "(%s) Already enabled with page table %#lx\n",
> - data->dbgname, data->pgtable);
> - } else {
> - data->dev = dev;
> - }
> -
> - return ret;
> -}
> -
> -static bool exynos_sysmmu_disable(struct device *dev)
> -{
> - struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> - bool disabled;
> -
> - disabled = __exynos_sysmmu_disable(data);
> - pm_runtime_put(data->sysmmu);
> -
> - return disabled;
> -}
> -
> -static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova)
> -{
> - unsigned long flags;
> - struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> -
> - read_lock_irqsave(&data->lock, flags);
> -
> - if (is_sysmmu_active(data)) {
> - int i;
> - for (i = 0; i < data->nsfrs; i++) {
> - if (sysmmu_block(data->sfrbases[i])) {
> - __sysmmu_tlb_invalidate_entry(
> - data->sfrbases[i], iova);
> - sysmmu_unblock(data->sfrbases[i]);
> - }
> - }
> - } else {
> - dev_dbg(data->sysmmu,
> - "(%s) Disabled. Skipping invalidating TLB.\n",
> - data->dbgname);
> - }
> -
> - read_unlock_irqrestore(&data->lock, flags);
> -}
> -
> -void exynos_sysmmu_tlb_invalidate(struct device *dev)
> -{
> - unsigned long flags;
> - struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> -
> - read_lock_irqsave(&data->lock, flags);
> -
> - if (is_sysmmu_active(data)) {
> - int i;
> - for (i = 0; i < data->nsfrs; i++) {
> - if (sysmmu_block(data->sfrbases[i])) {
> - __sysmmu_tlb_invalidate(data->sfrbases[i]);
> - sysmmu_unblock(data->sfrbases[i]);
> - }
> - }
> - } else {
> - dev_dbg(data->sysmmu,
> - "(%s) Disabled. Skipping invalidating TLB.\n",
> - data->dbgname);
> - }
> -
> - read_unlock_irqrestore(&data->lock, flags);
> -}
> -
> -static int exynos_sysmmu_probe(struct platform_device *pdev)
> -{
> - int i, ret;
> - struct device *dev;
> - struct sysmmu_drvdata *data;
> -
> - dev = &pdev->dev;
> -
> - data = kzalloc(sizeof(*data), GFP_KERNEL);
> - if (!data) {
> - dev_dbg(dev, "Not enough memory\n");
> - ret = -ENOMEM;
> - goto err_alloc;
> - }
> -
> - ret = dev_set_drvdata(dev, data);
> - if (ret) {
> - dev_dbg(dev, "Unabled to initialize driver data\n");
> - goto err_init;
> - }
> -
> - data->nsfrs = pdev->num_resources / 2;
> - data->sfrbases = kmalloc(sizeof(*data->sfrbases) * data->nsfrs,
> - GFP_KERNEL);
> - if (data->sfrbases == NULL) {
> - dev_dbg(dev, "Not enough memory\n");
> - ret = -ENOMEM;
> - goto err_init;
> - }
> -
> - for (i = 0; i < data->nsfrs; i++) {
> - struct resource *res;
> - res = platform_get_resource(pdev, IORESOURCE_MEM, i);
> - if (!res) {
> - dev_dbg(dev, "Unable to find IOMEM region\n");
> - ret = -ENOENT;
> - goto err_res;
> - }
> -
> - data->sfrbases[i] = ioremap(res->start, resource_size(res));
> - if (!data->sfrbases[i]) {
> - dev_dbg(dev, "Unable to map IOMEM @ PA:%#x\n",
> - res->start);
> - ret = -ENOENT;
> - goto err_res;
> - }
> - }
> -
> - for (i = 0; i < data->nsfrs; i++) {
> - ret = platform_get_irq(pdev, i);
> - if (ret <= 0) {
> - dev_dbg(dev, "Unable to find IRQ resource\n");
> - goto err_irq;
> - }
> -
> - ret = request_irq(ret, exynos_sysmmu_irq, 0,
> - dev_name(dev), data);
> - if (ret) {
> - dev_dbg(dev, "Unabled to register interrupt handler\n");
> - goto err_irq;
> - }
> - }
> -
> - if (dev_get_platdata(dev)) {
> - char *deli, *beg;
> - struct sysmmu_platform_data *platdata = dev_get_platdata(dev);
> -
> - beg = platdata->clockname;
> -
> - for (deli = beg; (*deli != '\0') && (*deli != ','); deli++)
> - /* NOTHING */;
> -
> - if (*deli == '\0')
> - deli = NULL;
> - else
> - *deli = '\0';
> -
> - data->clk[0] = clk_get(dev, beg);
> - if (IS_ERR(data->clk[0])) {
> - data->clk[0] = NULL;
> - dev_dbg(dev, "No clock descriptor registered\n");
> - }
> -
> - if (data->clk[0] && deli) {
> - *deli = ',';
> - data->clk[1] = clk_get(dev, deli + 1);
> - if (IS_ERR(data->clk[1]))
> - data->clk[1] = NULL;
> - }
> -
> - data->dbgname = platdata->dbgname;
> - }
> -
> - data->sysmmu = dev;
> - rwlock_init(&data->lock);
> - INIT_LIST_HEAD(&data->node);
> -
> - __set_fault_handler(data, &default_fault_handler);
> -
> - if (dev->parent)
> - pm_runtime_enable(dev);
> -
> - dev_dbg(dev, "(%s) Initialized\n", data->dbgname);
> - return 0;
> -err_irq:
> - while (i-- > 0) {
> - int irq;
> -
> - irq = platform_get_irq(pdev, i);
> - free_irq(irq, data);
> - }
> -err_res:
> - while (data->nsfrs-- > 0)
> - iounmap(data->sfrbases[data->nsfrs]);
> - kfree(data->sfrbases);
> -err_init:
> - kfree(data);
> -err_alloc:
> - dev_err(dev, "Failed to initialize\n");
> - return ret;
> -}
> -
> -static struct platform_driver exynos_sysmmu_driver = {
> - .probe = exynos_sysmmu_probe,
> - .driver = {
> - .owner = THIS_MODULE,
> - .name = "exynos-sysmmu",
> - }
> -};
> -
> -static inline void pgtable_flush(void *vastart, void *vaend)
> -{
> - dmac_flush_range(vastart, vaend);
> - outer_flush_range(virt_to_phys(vastart),
> - virt_to_phys(vaend));
> -}
> -
> -static int exynos_iommu_domain_init(struct iommu_domain *domain)
> -{
> - struct exynos_iommu_domain *priv;
> -
> - priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> - if (!priv)
> - return -ENOMEM;
> -
> - priv->pgtable = (unsigned long *)__get_free_pages(
> - GFP_KERNEL | __GFP_ZERO, 2);
> - if (!priv->pgtable)
> - goto err_pgtable;
> -
> - priv->lv2entcnt = (short *)__get_free_pages(
> - GFP_KERNEL | __GFP_ZERO, 1);
> - if (!priv->lv2entcnt)
> - goto err_counter;
> -
> - pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
> -
> - spin_lock_init(&priv->lock);
> - spin_lock_init(&priv->pgtablelock);
> - INIT_LIST_HEAD(&priv->clients);
> -
> - domain->geometry.aperture_start = 0;
> - domain->geometry.aperture_end = ~0UL;
> - domain->geometry.force_aperture = true;
> -
> - domain->priv = priv;
> - return 0;
> -
> -err_counter:
> - free_pages((unsigned long)priv->pgtable, 2);
> -err_pgtable:
> - kfree(priv);
> - return -ENOMEM;
> -}
> -
> -static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
> -{
> - struct exynos_iommu_domain *priv = domain->priv;
> - struct sysmmu_drvdata *data;
> - unsigned long flags;
> - int i;
> -
> - WARN_ON(!list_empty(&priv->clients));
> -
> - spin_lock_irqsave(&priv->lock, flags);
> -
> - list_for_each_entry(data, &priv->clients, node) {
> - while (!exynos_sysmmu_disable(data->dev))
> - ; /* until System MMU is actually disabled */
> - }
> -
> - spin_unlock_irqrestore(&priv->lock, flags);
> -
> - for (i = 0; i < NUM_LV1ENTRIES; i++)
> - if (lv1ent_page(priv->pgtable + i))
> - kfree(__va(lv2table_base(priv->pgtable + i)));
> -
> - free_pages((unsigned long)priv->pgtable, 2);
> - free_pages((unsigned long)priv->lv2entcnt, 1);
> - kfree(domain->priv);
> - domain->priv = NULL;
> -}
> -
> -static int exynos_iommu_attach_device(struct iommu_domain *domain,
> - struct device *dev)
> -{
> - struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> - struct exynos_iommu_domain *priv = domain->priv;
> - unsigned long flags;
> - int ret;
> -
> - ret = pm_runtime_get_sync(data->sysmmu);
> - if (ret < 0)
> - return ret;
> -
> - ret = 0;
> -
> - spin_lock_irqsave(&priv->lock, flags);
> -
> - ret = __exynos_sysmmu_enable(data, __pa(priv->pgtable), domain);
> -
> - if (ret == 0) {
> - /* 'data->node' must not be appeared in priv->clients */
> - BUG_ON(!list_empty(&data->node));
> - data->dev = dev;
> - list_add_tail(&data->node, &priv->clients);
> - }
> -
> - spin_unlock_irqrestore(&priv->lock, flags);
> -
> - if (ret < 0) {
> - dev_err(dev, "%s: Failed to attach IOMMU with pgtable %#lx\n",
> - __func__, __pa(priv->pgtable));
> - pm_runtime_put(data->sysmmu);
> - } else if (ret > 0) {
> - dev_dbg(dev, "%s: IOMMU with pgtable 0x%lx already attached\n",
> - __func__, __pa(priv->pgtable));
> - } else {
> - dev_dbg(dev, "%s: Attached new IOMMU with pgtable 0x%lx\n",
> - __func__, __pa(priv->pgtable));
> - }
> -
> - return ret;
> -}
> -
> -static void exynos_iommu_detach_device(struct iommu_domain *domain,
> - struct device *dev)
> -{
> - struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> - struct exynos_iommu_domain *priv = domain->priv;
> - struct list_head *pos;
> - unsigned long flags;
> - bool found = false;
> -
> - spin_lock_irqsave(&priv->lock, flags);
> -
> - list_for_each(pos, &priv->clients) {
> - if (list_entry(pos, struct sysmmu_drvdata, node) == data) {
> - found = true;
> - break;
> - }
> - }
> -
> - if (!found)
> - goto finish;
> -
> - if (__exynos_sysmmu_disable(data)) {
> - dev_dbg(dev, "%s: Detached IOMMU with pgtable %#lx\n",
> - __func__, __pa(priv->pgtable));
> - list_del_init(&data->node);
> -
> - } else {
> - dev_dbg(dev, "%s: Detaching IOMMU with pgtable %#lx delayed",
> - __func__, __pa(priv->pgtable));
> - }
> -
> -finish:
> - spin_unlock_irqrestore(&priv->lock, flags);
> -
> - if (found)
> - pm_runtime_put(data->sysmmu);
> -}
> -
> -static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,
> - short *pgcounter)
> -{
> - if (lv1ent_fault(sent)) {
> - unsigned long *pent;
> -
> - pent = kzalloc(LV2TABLE_SIZE, GFP_ATOMIC);
> - BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
> - if (!pent)
> - return NULL;
> -
> - *sent = mk_lv1ent_page(__pa(pent));
> - *pgcounter = NUM_LV2ENTRIES;
> - pgtable_flush(pent, pent + NUM_LV2ENTRIES);
> - pgtable_flush(sent, sent + 1);
> - }
> -
> - return page_entry(sent, iova);
> -}
> -
> -static int lv1set_section(unsigned long *sent, phys_addr_t paddr, short *pgcnt)
> -{
> - if (lv1ent_section(sent))
> - return -EADDRINUSE;
> -
> - if (lv1ent_page(sent)) {
> - if (*pgcnt != NUM_LV2ENTRIES)
> - return -EADDRINUSE;
> -
> - kfree(page_entry(sent, 0));
> -
> - *pgcnt = 0;
> - }
> -
> - *sent = mk_lv1ent_sect(paddr);
> -
> - pgtable_flush(sent, sent + 1);
> -
> - return 0;
> -}
> -
> -static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
> - short *pgcnt)
> -{
> - if (size == SPAGE_SIZE) {
> - if (!lv2ent_fault(pent))
> - return -EADDRINUSE;
> -
> - *pent = mk_lv2ent_spage(paddr);
> - pgtable_flush(pent, pent + 1);
> - *pgcnt -= 1;
> - } else { /* size == LPAGE_SIZE */
> - int i;
> - for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
> - if (!lv2ent_fault(pent)) {
> - memset(pent, 0, sizeof(*pent) * i);
> - return -EADDRINUSE;
> - }
> -
> - *pent = mk_lv2ent_lpage(paddr);
> - }
> - pgtable_flush(pent - SPAGES_PER_LPAGE, pent);
> - *pgcnt -= SPAGES_PER_LPAGE;
> - }
> -
> - return 0;
> -}
> -
> -static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova,
> - phys_addr_t paddr, size_t size, int prot)
> -{
> - struct exynos_iommu_domain *priv = domain->priv;
> - unsigned long *entry;
> - unsigned long flags;
> - int ret = -ENOMEM;
> -
> - BUG_ON(priv->pgtable == NULL);
> -
> - spin_lock_irqsave(&priv->pgtablelock, flags);
> -
> - entry = section_entry(priv->pgtable, iova);
> -
> - if (size == SECT_SIZE) {
> - ret = lv1set_section(entry, paddr,
> - &priv->lv2entcnt[lv1ent_offset(iova)]);
> - } else {
> - unsigned long *pent;
> -
> - pent = alloc_lv2entry(entry, iova,
> - &priv->lv2entcnt[lv1ent_offset(iova)]);
> -
> - if (!pent)
> - ret = -ENOMEM;
> - else
> - ret = lv2set_page(pent, paddr, size,
> - &priv->lv2entcnt[lv1ent_offset(iova)]);
> - }
> -
> - if (ret) {
> - pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n",
> - __func__, iova, size);
> - }
> -
> - spin_unlock_irqrestore(&priv->pgtablelock, flags);
> -
> - return ret;
> -}
> -
> -static size_t exynos_iommu_unmap(struct iommu_domain *domain,
> - unsigned long iova, size_t size)
> -{
> - struct exynos_iommu_domain *priv = domain->priv;
> - struct sysmmu_drvdata *data;
> - unsigned long flags;
> - unsigned long *ent;
> -
> - BUG_ON(priv->pgtable == NULL);
> -
> - spin_lock_irqsave(&priv->pgtablelock, flags);
> -
> - ent = section_entry(priv->pgtable, iova);
> -
> - if (lv1ent_section(ent)) {
> - BUG_ON(size < SECT_SIZE);
> -
> - *ent = 0;
> - pgtable_flush(ent, ent + 1);
> - size = SECT_SIZE;
> - goto done;
> - }
> -
> - if (unlikely(lv1ent_fault(ent))) {
> - if (size > SECT_SIZE)
> - size = SECT_SIZE;
> - goto done;
> - }
> -
> - /* lv1ent_page(sent) == true here */
> -
> - ent = page_entry(ent, iova);
> -
> - if (unlikely(lv2ent_fault(ent))) {
> - size = SPAGE_SIZE;
> - goto done;
> - }
> -
> - if (lv2ent_small(ent)) {
> - *ent = 0;
> - size = SPAGE_SIZE;
> - priv->lv2entcnt[lv1ent_offset(iova)] += 1;
> - goto done;
> - }
> -
> - /* lv1ent_large(ent) == true here */
> - BUG_ON(size < LPAGE_SIZE);
> -
> - memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
> -
> - size = LPAGE_SIZE;
> - priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
> -done:
> - spin_unlock_irqrestore(&priv->pgtablelock, flags);
> -
> - spin_lock_irqsave(&priv->lock, flags);
> - list_for_each_entry(data, &priv->clients, node)
> - sysmmu_tlb_invalidate_entry(data->dev, iova);
> - spin_unlock_irqrestore(&priv->lock, flags);
> -
> -
> - return size;
> -}
> -
> -static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
> - dma_addr_t iova)
> -{
> - struct exynos_iommu_domain *priv = domain->priv;
> - unsigned long *entry;
> - unsigned long flags;
> - phys_addr_t phys = 0;
> -
> - spin_lock_irqsave(&priv->pgtablelock, flags);
> -
> - entry = section_entry(priv->pgtable, iova);
> -
> - if (lv1ent_section(entry)) {
> - phys = section_phys(entry) + section_offs(iova);
> - } else if (lv1ent_page(entry)) {
> - entry = page_entry(entry, iova);
> -
> - if (lv2ent_large(entry))
> - phys = lpage_phys(entry) + lpage_offs(iova);
> - else if (lv2ent_small(entry))
> - phys = spage_phys(entry) + spage_offs(iova);
> - }
> -
> - spin_unlock_irqrestore(&priv->pgtablelock, flags);
> -
> - return phys;
> -}
> -
> -static struct iommu_ops exynos_iommu_ops = {
> - .domain_init = &exynos_iommu_domain_init,
> - .domain_destroy = &exynos_iommu_domain_destroy,
> - .attach_dev = &exynos_iommu_attach_device,
> - .detach_dev = &exynos_iommu_detach_device,
> - .map = &exynos_iommu_map,
> - .unmap = &exynos_iommu_unmap,
> - .iova_to_phys = &exynos_iommu_iova_to_phys,
> - .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
> -};
> -
> -static int __init exynos_iommu_init(void)
> -{
> - int ret;
> -
> - ret = platform_driver_register(&exynos_sysmmu_driver);
> -
> - if (ret == 0)
> - bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
> -
> - return ret;
> -}
> -subsys_initcall(exynos_iommu_init);
> --
> 1.7.10.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v5 00/14] Add support for MSM's mmio clock/reset controller
From: Frank Rowand @ 2014-02-07 4:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389811654-21397-1-git-send-email-sboyd@codeaurora.org>
On 1/15/2014 10:47 AM, Stephen Boyd wrote:
> The first breaks a reset-controller include ordering requirement. It got
> an ack so I think we're ok for it to go through the clock tree.
>
< snip >
checkpatch is whining about patches
4
5
6
7
8
(Just for completeness if someone thinks I did not check all the patches,
it also whines about patch 11, but I think the whining should be ignored,
and it whines about patch 1 but I think that might be a checkpatch bug.)
-Frank
^ permalink raw reply
* [PATCH 2/3] ARM: OMAP2+: AM43x: Add ID for ES1.1
From: Lokesh Vutla @ 2014-02-07 4:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F39E74.3030404@ti.com>
Hi Nishanth,
On Thursday 06 February 2014 08:08 PM, Nishanth Menon wrote:
> On 02/06/2014 02:45 AM, Lokesh Vutla wrote:
>> Adding ID for AM437x ES1.1 silicon.
>>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> ---
>> arch/arm/mach-omap2/id.c | 14 ++++++++++++--
>> arch/arm/mach-omap2/soc.h | 3 ++-
>> 2 files changed, 14 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
>> index 9428c5f..8a05eaf 100644
>> --- a/arch/arm/mach-omap2/id.c
>> +++ b/arch/arm/mach-omap2/id.c
>> @@ -465,8 +465,18 @@ void __init omap3xxx_check_revision(void)
>> }
>> break;
>> case 0xb98c:
>> - omap_revision = AM437X_REV_ES1_0;
>> - cpu_rev = "1.0";
>> + switch (rev) {
>> + case 0:
>> + omap_revision = AM437X_REV_ES1_0;
>> + cpu_rev = "1.0";
>> + break;
>> + case 1:
>> + /* FALLTHROUGH */
>> + default:
>> + omap_revision = AM437X_REV_ES1_1;
>> + cpu_rev = "1.1";
>> + break;
>> + }
>> break;
>> case 0xb8f2:
>> switch (rev) {
>> diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
>> index 076bd90..30abcc8 100644
>> --- a/arch/arm/mach-omap2/soc.h
>> +++ b/arch/arm/mach-omap2/soc.h
>> @@ -438,7 +438,8 @@ IS_OMAP_TYPE(3430, 0x3430)
>> #define AM335X_REV_ES2_1 (AM335X_CLASS | (0x2 << 8))
>>
>> #define AM437X_CLASS 0x43700000
>> -#define AM437X_REV_ES1_0 AM437X_CLASS
>> +#define AM437X_REV_ES1_0 (AM437X_CLASS | (0x10 << 8))
>> +#define AM437X_REV_ES1_1 (AM437X_CLASS | (0x11 << 8))
>>
>> #define OMAP443X_CLASS 0x44300044
>> #define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
>>
>
> can you also check if socbus shows proper results?
> I had http://slexy.org/view/s20e3OsIVx with v3.14-rc1
Oops....missed out formating and sending "AM43x : determine features patch".
Thanks for pointing it out. ll update and send a v2 for this series.
Thanks and regards,
Lokesh
>
^ permalink raw reply
* [PATCH v3 11/11] ARM: KVM: trap VM system registers until MMU and caches are ON
From: Christoffer Dall @ 2014-02-07 4:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391630151-7875-12-git-send-email-marc.zyngier@arm.com>
On Wed, Feb 05, 2014 at 07:55:51PM +0000, Marc Zyngier wrote:
> In order to be able to detect the point where the guest enables
> its MMU and caches, trap all the VM related system registers.
>
> Once we see the guest enabling both the MMU and the caches, we
> can go back to a saner mode of operation, which is to leave these
> registers in complete control of the guest.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
^ permalink raw reply
* [PATCH v3 04/11] arm64: KVM: flush VM pages before letting the guest enable caches
From: Christoffer Dall @ 2014-02-07 4:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391630151-7875-5-git-send-email-marc.zyngier@arm.com>
On Wed, Feb 05, 2014 at 07:55:44PM +0000, Marc Zyngier wrote:
> When the guest runs with caches disabled (like in an early boot
> sequence, for example), all the writes are diectly going to RAM,
> bypassing the caches altogether.
>
> Once the MMU and caches are enabled, whatever sits in the cache
> becomes suddenly visible, which isn't what the guest expects.
>
> A way to avoid this potential disaster is to invalidate the cache
> when the MMU is being turned on. For this, we hook into the SCTLR_EL1
> trapping code, and scan the stage-2 page tables, invalidating the
> pages/sections that have already been mapped in.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
> arch/arm/include/asm/kvm_mmu.h | 8 ++++
> arch/arm/kvm/mmu.c | 93 ++++++++++++++++++++++++++++++++++++++++
> arch/arm64/include/asm/kvm_mmu.h | 4 ++
> arch/arm64/kvm/sys_regs.c | 5 ++-
> 4 files changed, 109 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
> index 6d0f3d3..0931cda 100644
> --- a/arch/arm/include/asm/kvm_mmu.h
> +++ b/arch/arm/include/asm/kvm_mmu.h
> @@ -114,6 +114,12 @@ static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
> pmd_val(*pmd) |= L_PMD_S2_RDWR;
> }
>
> +/* Open coded pgd_addr_end that can deal with 64bit addresses */
> +#define kvm_pgd_addr_end(addr, end) \
> +({ u64 __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
> + (__boundary - 1 < (end) - 1)? __boundary: (end); \
> +})
> +
> struct kvm;
>
> static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
> @@ -142,6 +148,8 @@ static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
> #define kvm_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
> #define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x))
>
> +void stage2_flush_vm(struct kvm *kvm);
> +
> #endif /* !__ASSEMBLY__ */
>
> #endif /* __ARM_KVM_MMU_H__ */
> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> index fc71a8d..ea21b6a 100644
> --- a/arch/arm/kvm/mmu.c
> +++ b/arch/arm/kvm/mmu.c
> @@ -187,6 +187,99 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
> }
> }
>
> +static void stage2_flush_ptes(struct kvm *kvm, pmd_t *pmd,
> + phys_addr_t addr, phys_addr_t end)
> +{
> + pte_t *pte;
> +
> + pte = pte_offset_kernel(pmd, addr);
> + do {
> + if (!pte_none(*pte)) {
> + hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);
> + kvm_flush_dcache_to_poc((void*)hva, PAGE_SIZE);
> + }
> + } while (pte++, addr += PAGE_SIZE, addr != end);
> +}
> +
> +static void stage2_flush_pmds(struct kvm *kvm, pud_t *pud,
> + phys_addr_t addr, phys_addr_t end)
> +{
> + pmd_t *pmd;
> + phys_addr_t next;
> +
> + pmd = pmd_offset(pud, addr);
> + do {
> + next = pmd_addr_end(addr, end);
> + if (!pmd_none(*pmd)) {
> + if (kvm_pmd_huge(*pmd)) {
> + hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);
> + kvm_flush_dcache_to_poc((void*)hva, PMD_SIZE);
> + } else {
> + stage2_flush_ptes(kvm, pmd, addr, next);
> + }
> + }
> + } while (pmd++, addr = next, addr != end);
> +}
> +
> +static void stage2_flush_puds(struct kvm *kvm, pgd_t *pgd,
> + phys_addr_t addr, phys_addr_t end)
> +{
> + pud_t *pud;
> + phys_addr_t next;
> +
> + pud = pud_offset(pgd, addr);
> + do {
> + next = pud_addr_end(addr, end);
> + if (!pud_none(*pud)) {
> + if (pud_huge(*pud)) {
> + hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);
> + kvm_flush_dcache_to_poc((void*)hva, PUD_SIZE);
> + } else {
> + stage2_flush_pmds(kvm, pud, addr, next);
> + }
> + }
> + } while(pud++, addr = next, addr != end);
you missed one space after this while, but no need to respin just
because of that.
> +}
> +
> +static void stage2_flush_memslot(struct kvm *kvm,
> + struct kvm_memory_slot *memslot)
> +{
> + phys_addr_t addr = memslot->base_gfn << PAGE_SHIFT;
> + phys_addr_t end = addr + PAGE_SIZE * memslot->npages;
> + phys_addr_t next;
> + pgd_t *pgd;
> +
> + pgd = kvm->arch.pgd + pgd_index(addr);
> + do {
> + next = kvm_pgd_addr_end(addr, end);
> + stage2_flush_puds(kvm, pgd, addr, next);
> + } while (pgd++, addr = next, addr != end);
> +}
> +
> +/**
> + * stage2_flush_vm - Invalidate cache for pages mapped in stage 2
> + * @kvm: The struct kvm pointer
> + *
> + * Go through the stage 2 page tables and invalidate any cache lines
> + * backing memory already mapped to the VM.
> + */
> +void stage2_flush_vm(struct kvm *kvm)
> +{
> + struct kvm_memslots *slots;
> + struct kvm_memory_slot *memslot;
> + int idx;
> +
> + idx = srcu_read_lock(&kvm->srcu);
> + spin_lock(&kvm->mmu_lock);
> +
> + slots = kvm_memslots(kvm);
> + kvm_for_each_memslot(memslot, slots)
> + stage2_flush_memslot(kvm, memslot);
> +
> + spin_unlock(&kvm->mmu_lock);
> + srcu_read_unlock(&kvm->srcu, idx);
> +}
> +
> /**
> * free_boot_hyp_pgd - free HYP boot page tables
> *
> diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
> index 6eaf69b..e78d050 100644
> --- a/arch/arm64/include/asm/kvm_mmu.h
> +++ b/arch/arm64/include/asm/kvm_mmu.h
> @@ -121,6 +121,8 @@ static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
> pmd_val(*pmd) |= PMD_S2_RDWR;
> }
>
> +#define kvm_pgd_addr_end(addr, end) pgd_addr_end(addr, end)
> +
> struct kvm;
>
> #define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
> @@ -146,5 +148,7 @@ static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
>
> #define kvm_virt_to_phys(x) __virt_to_phys((unsigned long)(x))
>
> +void stage2_flush_vm(struct kvm *kvm);
> +
> #endif /* __ASSEMBLY__ */
> #endif /* __ARM64_KVM_MMU_H__ */
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 2097e5e..0324458 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -27,6 +27,7 @@
> #include <asm/kvm_host.h>
> #include <asm/kvm_emulate.h>
> #include <asm/kvm_coproc.h>
> +#include <asm/kvm_mmu.h>
> #include <asm/cacheflush.h>
> #include <asm/cputype.h>
> #include <trace/events/kvm.h>
> @@ -154,8 +155,10 @@ static bool access_sctlr(struct kvm_vcpu *vcpu,
> {
> access_vm_reg(vcpu, p, r);
>
> - if (vcpu_has_cache_enabled(vcpu)) /* MMU+Caches enabled? */
> + if (vcpu_has_cache_enabled(vcpu)) { /* MMU+Caches enabled? */
> vcpu->arch.hcr_el2 &= ~HCR_TVM;
> + stage2_flush_vm(vcpu->kvm);
> + }
>
> return true;
> }
> --
> 1.8.3.4
>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
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