* Re: [PATCH v3 1/2] spi:fsl-dspi:convert to use regmap and big-endian supports
From: Alexander Shiyan @ 2014-02-11 6:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392097697-14919-1-git-send-email-b44548@freescale.com>
???????, 11 ??????? 2014, 13:48 +08:00 ?? Chao Fu <b44548@freescale.com>:
> From: Chao Fu <B44548@freescale.com>
>
> Freescale DSPI module will have two endianess in different platform,
> but ARM is little endian. So when DSPI in big endian, core in little endian,
> readl and writel can not adjust R/W register in this condition.
> This patch will remove general readl/writel, and import regmap mechanism.
> Data endian will be transfered in regmap APIs.
In this case You should additionally select REGMAP_MMIO option
for SPI_FSL_DSPI in the drivers/spi/Kconfig.
---
^ permalink raw reply
* [linux-sunxi] Re: [PATCH 1/3] mfd: axp20x: Add mfd driver for axp20x PMIC
From: Carlo Caione @ 2014-02-11 6:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOQ7t2axObbBpVcF0z826Q2b0DaCx+wr0fvJ1X9Ek33174pOwA@mail.gmail.com>
On Mon, Feb 10, 2014 at 11:34 PM, Carlo Caione <carlo@caione.org> wrote:
>>> +static struct axp20x_dev *axp20x_pm_power_off;
>>
>> This looks pretty unconventional. What's the point of it?
>
> On a single board we can have multiple AXPs so I track which one is in
> charge of powering off the board (and to get the correct device in the
> axp20x_power_off())
<snip>
>>> +
>>> + if (!pm_power_off) {
>>> + axp20x_pm_power_off = axp20x;
>>> + pm_power_off = axp20x_power_off;
>>> + }
>>
>> Can you describe to me what you're using the pm_power_off call-back
>> for please?
>
> It's meant to poweroff the board
Actually what is missing here is also a way to determine which device
is in charge of powering off when multiple AXPs are registered.
I'll fix it in v2.
Thanks,
--
Carlo Caione
^ permalink raw reply
* [PATCH v2 11/11] watchdog: xilinx: Remove no_timeout variable
From: Michal Simek @ 2014-02-11 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f298edd222c57b0ce1ebad3ae50c3f715406c631.1392101734.git.michal.simek@xilinx.com>
Remove no_timeout variable and check variables
directly.
Suggested-by: Rob Herring <robherring2@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2:
- New patch in this series
drivers/watchdog/of_xilinx_wdt.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index dad8fb5..fc91285 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -147,10 +147,9 @@ static u32 xwdt_selftest(struct xwdt_device *xdev)
static int xwdt_probe(struct platform_device *pdev)
{
int rc;
- u32 pfreq, enable_once = 0;
+ u32 pfreq = 0, enable_once = 0;
struct resource *res;
struct xwdt_device *xdev;
- bool no_timeout = false;
struct watchdog_device *xilinx_wdt_wdd;
xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
@@ -168,19 +167,15 @@ static int xwdt_probe(struct platform_device *pdev)
return PTR_ERR(xdev->base);
rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &pfreq);
- if (rc) {
+ if (rc)
dev_warn(&pdev->dev,
"The watchdog clock frequency cannot be obtained\n");
- no_timeout = true;
- }
rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval",
&xdev->wdt_interval);
- if (rc) {
+ if (rc)
dev_warn(&pdev->dev,
"Parameter \"xlnx,wdt-interval\" not found\n");
- no_timeout = true;
- }
rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-enable-once",
&enable_once);
@@ -195,7 +190,7 @@ static int xwdt_probe(struct platform_device *pdev)
* Twice of the 2^wdt_interval / freq because the first wdt overflow is
* ignored (interrupt), reset is only generated at second wdt overflow
*/
- if (!no_timeout)
+ if (pfreq && xdev->wdt_interval)
xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
pfreq);
--
1.8.2.3
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* [PATCH v2 09/11] watchdog: xilinx: Add missing binding
From: Michal Simek @ 2014-02-11 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f298edd222c57b0ce1ebad3ae50c3f715406c631.1392101734.git.michal.simek@xilinx.com>
Document current driver binding.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
Changes in v2: None
.../devicetree/bindings/watchdog/of-xilinx-wdt.txt | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt b/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
new file mode 100644
index 0000000..6d63782
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
@@ -0,0 +1,23 @@
+Xilinx AXI/PLB soft-core watchdog Device Tree Bindings
+---------------------------------------------------------
+
+Required properties:
+- compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or
+ "xlnx,xps-timebase-wdt-1.01.a".
+- reg : Physical base address and size
+
+Optional properties:
+- clock-frequency : Frequency of clock in Hz
+- xlnx,wdt-enable-once : 0 - Watchdog can be restarted
+ 1 - Watchdog can be enabled just once
+- xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,
+ <val> is integer from 8 to 31.
+
+Example:
+axi-timebase-wdt at 40100000 {
+ clock-frequency = <50000000>;
+ compatible = "xlnx,xps-timebase-wdt-1.00.a";
+ reg = <0x40100000 0x10000>;
+ xlnx,wdt-enable-once = <0x0>;
+ xlnx,wdt-interval = <0x1b>;
+} ;
--
1.8.2.3
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* [PATCH v2 08/11] watchdog: xilinx: Use correct comment indentation
From: Michal Simek @ 2014-02-11 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f298edd222c57b0ce1ebad3ae50c3f715406c631.1392101734.git.michal.simek@xilinx.com>
No functional changes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
Changes in v2: None
drivers/watchdog/of_xilinx_wdt.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index bb03e5b..dad8fb5 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -191,10 +191,10 @@ static int xwdt_probe(struct platform_device *pdev)
if (enable_once)
watchdog_set_nowayout(xilinx_wdt_wdd, true);
-/*
- * Twice of the 2^wdt_interval / freq because the first wdt overflow is
- * ignored (interrupt), reset is only generated at second wdt overflow
- */
+ /*
+ * Twice of the 2^wdt_interval / freq because the first wdt overflow is
+ * ignored (interrupt), reset is only generated at second wdt overflow
+ */
if (!no_timeout)
xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
pfreq);
--
1.8.2.3
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* [PATCH v2 07/11] watchdog: xilinx: Use of_property_read_u32
From: Michal Simek @ 2014-02-11 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f298edd222c57b0ce1ebad3ae50c3f715406c631.1392101734.git.michal.simek@xilinx.com>
Use of_property_read_u32 functions to clean probe function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2:
- Fix enable_once logic
- Change patch subject
drivers/watchdog/of_xilinx_wdt.c | 28 ++++++++++++----------------
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index c229cc4..bb03e5b 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -147,8 +147,7 @@ static u32 xwdt_selftest(struct xwdt_device *xdev)
static int xwdt_probe(struct platform_device *pdev)
{
int rc;
- u32 *tmptr;
- u32 *pfreq;
+ u32 pfreq, enable_once = 0;
struct resource *res;
struct xwdt_device *xdev;
bool no_timeout = false;
@@ -168,32 +167,29 @@ static int xwdt_probe(struct platform_device *pdev)
if (IS_ERR(xdev->base))
return PTR_ERR(xdev->base);
- pfreq = (u32 *)of_get_property(pdev->dev.of_node,
- "clock-frequency", NULL);
-
- if (pfreq == NULL) {
+ rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &pfreq);
+ if (rc) {
dev_warn(&pdev->dev,
"The watchdog clock frequency cannot be obtained\n");
no_timeout = true;
}
- tmptr = (u32 *)of_get_property(pdev->dev.of_node,
- "xlnx,wdt-interval", NULL);
- if (tmptr == NULL) {
+ rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval",
+ &xdev->wdt_interval);
+ if (rc) {
dev_warn(&pdev->dev,
"Parameter \"xlnx,wdt-interval\" not found\n");
no_timeout = true;
- } else {
- xdev->wdt_interval = *tmptr;
}
- tmptr = (u32 *)of_get_property(pdev->dev.of_node,
- "xlnx,wdt-enable-once", NULL);
- if (tmptr == NULL) {
+ rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-enable-once",
+ &enable_once);
+ if (rc)
dev_warn(&pdev->dev,
"Parameter \"xlnx,wdt-enable-once\" not found\n");
+
+ if (enable_once)
watchdog_set_nowayout(xilinx_wdt_wdd, true);
- }
/*
* Twice of the 2^wdt_interval / freq because the first wdt overflow is
@@ -201,7 +197,7 @@ static int xwdt_probe(struct platform_device *pdev)
*/
if (!no_timeout)
xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
- *pfreq);
+ pfreq);
spin_lock_init(&xdev->spinlock);
watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
--
1.8.2.3
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* [PATCH v2 06/11] watchdog: xilinx: Fix all printk messages
From: Michal Simek @ 2014-02-11 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f298edd222c57b0ce1ebad3ae50c3f715406c631.1392101734.git.michal.simek@xilinx.com>
Use dev_ functions for printk messages.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
Changes in v2: None
drivers/watchdog/of_xilinx_wdt.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index d28bd3f..c229cc4 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -10,8 +10,6 @@
* 2 of the License, or (at your option) any later version.
*/
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
#include <linux/err.h>
#include <linux/module.h>
#include <linux/types.h>
@@ -42,7 +40,6 @@
#define XWT_TIMER_FAILED 0xFFFFFFFF
#define WATCHDOG_NAME "Xilinx Watchdog"
-#define PFX WATCHDOG_NAME ": "
struct xwdt_device {
void __iomem *base;
@@ -175,14 +172,16 @@ static int xwdt_probe(struct platform_device *pdev)
"clock-frequency", NULL);
if (pfreq == NULL) {
- pr_warn("The watchdog clock frequency cannot be obtained!\n");
+ dev_warn(&pdev->dev,
+ "The watchdog clock frequency cannot be obtained\n");
no_timeout = true;
}
tmptr = (u32 *)of_get_property(pdev->dev.of_node,
"xlnx,wdt-interval", NULL);
if (tmptr == NULL) {
- pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n");
+ dev_warn(&pdev->dev,
+ "Parameter \"xlnx,wdt-interval\" not found\n");
no_timeout = true;
} else {
xdev->wdt_interval = *tmptr;
@@ -191,7 +190,8 @@ static int xwdt_probe(struct platform_device *pdev)
tmptr = (u32 *)of_get_property(pdev->dev.of_node,
"xlnx,wdt-enable-once", NULL);
if (tmptr == NULL) {
- pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n");
+ dev_warn(&pdev->dev,
+ "Parameter \"xlnx,wdt-enable-once\" not found\n");
watchdog_set_nowayout(xilinx_wdt_wdd, true);
}
@@ -208,13 +208,13 @@ static int xwdt_probe(struct platform_device *pdev)
rc = xwdt_selftest(xdev);
if (rc == XWT_TIMER_FAILED) {
- pr_err("SelfTest routine error!\n");
+ dev_err(&pdev->dev, "SelfTest routine error\n");
return rc;
}
rc = watchdog_register_device(xilinx_wdt_wdd);
if (rc) {
- pr_err("cannot register watchdog (err=%d)\n", rc);
+ dev_err(&pdev->dev, "Cannot register watchdog (err=%d)\n", rc);
return rc;
}
--
1.8.2.3
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* [PATCH v2 05/11] watchdog: xilinx: Allocate private structure per device
From: Michal Simek @ 2014-02-11 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f298edd222c57b0ce1ebad3ae50c3f715406c631.1392101734.git.michal.simek@xilinx.com>
Only one watchdog could be used by this driver.
Create driver private data structure and move there
all variables for one instance.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
Changes in v2: None
drivers/watchdog/of_xilinx_wdt.c | 97 +++++++++++++++++++++++-----------------
1 file changed, 55 insertions(+), 42 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index 1f7ad91..d28bd3f 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -47,30 +47,27 @@
struct xwdt_device {
void __iomem *base;
u32 wdt_interval;
+ spinlock_t spinlock;
+ struct watchdog_device xilinx_wdt_wdd;
};
-static struct xwdt_device xdev;
-
-static u32 timeout;
-
-static DEFINE_SPINLOCK(spinlock);
-
static int xilinx_wdt_start(struct watchdog_device *wdd)
{
u32 control_status_reg;
+ struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
- spin_lock(&spinlock);
+ spin_lock(&xdev->spinlock);
/* Clean previous status and enable the watchdog timer */
- control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
+ control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
- xdev.base + XWT_TWCSR0_OFFSET);
+ xdev->base + XWT_TWCSR0_OFFSET);
- iowrite32(XWT_CSRX_EWDT2_MASK, xdev.base + XWT_TWCSR1_OFFSET);
+ iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
- spin_unlock(&spinlock);
+ spin_unlock(&xdev->spinlock);
return 0;
}
@@ -78,17 +75,18 @@ static int xilinx_wdt_start(struct watchdog_device *wdd)
static int xilinx_wdt_stop(struct watchdog_device *wdd)
{
u32 control_status_reg;
+ struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
- spin_lock(&spinlock);
+ spin_lock(&xdev->spinlock);
- control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
+ control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
- xdev.base + XWT_TWCSR0_OFFSET);
+ xdev->base + XWT_TWCSR0_OFFSET);
- iowrite32(0, xdev.base + XWT_TWCSR1_OFFSET);
+ iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
- spin_unlock(&spinlock);
+ spin_unlock(&xdev->spinlock);
pr_info("Stopped!\n");
return 0;
@@ -97,14 +95,15 @@ static int xilinx_wdt_stop(struct watchdog_device *wdd)
static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
{
u32 control_status_reg;
+ struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
- spin_lock(&spinlock);
+ spin_lock(&xdev->spinlock);
- control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
+ control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
- iowrite32(control_status_reg, xdev.base + XWT_TWCSR0_OFFSET);
+ iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
- spin_unlock(&spinlock);
+ spin_unlock(&xdev->spinlock);
return 0;
}
@@ -123,29 +122,24 @@ static const struct watchdog_ops xilinx_wdt_ops = {
.ping = xilinx_wdt_keepalive,
};
-static struct watchdog_device xilinx_wdt_wdd = {
- .info = &xilinx_wdt_ident,
- .ops = &xilinx_wdt_ops,
-};
-
-static u32 xwdt_selftest(void)
+static u32 xwdt_selftest(struct xwdt_device *xdev)
{
int i;
u32 timer_value1;
u32 timer_value2;
- spin_lock(&spinlock);
+ spin_lock(&xdev->spinlock);
- timer_value1 = ioread32(xdev.base + XWT_TBR_OFFSET);
- timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET);
+ timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
+ timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
for (i = 0;
((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
(timer_value2 == timer_value1)); i++) {
- timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET);
+ timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
}
- spin_unlock(&spinlock);
+ spin_unlock(&xdev->spinlock);
if (timer_value2 != timer_value1)
return ~XWT_TIMER_FAILED;
@@ -159,12 +153,23 @@ static int xwdt_probe(struct platform_device *pdev)
u32 *tmptr;
u32 *pfreq;
struct resource *res;
+ struct xwdt_device *xdev;
bool no_timeout = false;
+ struct watchdog_device *xilinx_wdt_wdd;
+
+ xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
+ if (!xdev)
+ return -ENOMEM;
+
+ xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
+ xilinx_wdt_wdd->info = &xilinx_wdt_ident;
+ xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
+ xilinx_wdt_wdd->parent = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- xdev.base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(xdev.base))
- return PTR_ERR(xdev.base);
+ xdev->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(xdev->base))
+ return PTR_ERR(xdev->base);
pfreq = (u32 *)of_get_property(pdev->dev.of_node,
"clock-frequency", NULL);
@@ -180,14 +185,14 @@ static int xwdt_probe(struct platform_device *pdev)
pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n");
no_timeout = true;
} else {
- xdev.wdt_interval = *tmptr;
+ xdev->wdt_interval = *tmptr;
}
tmptr = (u32 *)of_get_property(pdev->dev.of_node,
"xlnx,wdt-enable-once", NULL);
if (tmptr == NULL) {
pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n");
- watchdog_set_nowayout(&xilinx_wdt_wdd, true);
+ watchdog_set_nowayout(xilinx_wdt_wdd, true);
}
/*
@@ -195,29 +200,37 @@ static int xwdt_probe(struct platform_device *pdev)
* ignored (interrupt), reset is only generated at second wdt overflow
*/
if (!no_timeout)
- timeout = 2 * ((1<<xdev.wdt_interval) / *pfreq);
+ xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
+ *pfreq);
+
+ spin_lock_init(&xdev->spinlock);
+ watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
- rc = xwdt_selftest();
+ rc = xwdt_selftest(xdev);
if (rc == XWT_TIMER_FAILED) {
pr_err("SelfTest routine error!\n");
return rc;
}
- rc = watchdog_register_device(&xilinx_wdt_wdd);
+ rc = watchdog_register_device(xilinx_wdt_wdd);
if (rc) {
pr_err("cannot register watchdog (err=%d)\n", rc);
return rc;
}
dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
- xdev.base, timeout);
+ xdev->base, xilinx_wdt_wdd->timeout);
+
+ platform_set_drvdata(pdev, xdev);
return 0;
}
-static int xwdt_remove(struct platform_device *dev)
+static int xwdt_remove(struct platform_device *pdev)
{
- watchdog_unregister_device(&xilinx_wdt_wdd);
+ struct xwdt_device *xdev = platform_get_drvdata(pdev);
+
+ watchdog_unregister_device(&xdev->xilinx_wdt_wdd);
return 0;
}
--
1.8.2.3
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* [PATCH v2 04/11] watchdog: xilinx: Move no_timeout to probe function
From: Michal Simek @ 2014-02-11 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f298edd222c57b0ce1ebad3ae50c3f715406c631.1392101734.git.michal.simek@xilinx.com>
no_timeout should be local variable because it is used
only in probe function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
Changes in v2: None
drivers/watchdog/of_xilinx_wdt.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index 7f371ed..1f7ad91 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -52,7 +52,6 @@ struct xwdt_device {
static struct xwdt_device xdev;
static u32 timeout;
-static u8 no_timeout;
static DEFINE_SPINLOCK(spinlock);
@@ -160,8 +159,7 @@ static int xwdt_probe(struct platform_device *pdev)
u32 *tmptr;
u32 *pfreq;
struct resource *res;
-
- no_timeout = 0;
+ bool no_timeout = false;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
xdev.base = devm_ioremap_resource(&pdev->dev, res);
@@ -173,14 +171,14 @@ static int xwdt_probe(struct platform_device *pdev)
if (pfreq == NULL) {
pr_warn("The watchdog clock frequency cannot be obtained!\n");
- no_timeout = 1;
+ no_timeout = true;
}
tmptr = (u32 *)of_get_property(pdev->dev.of_node,
"xlnx,wdt-interval", NULL);
if (tmptr == NULL) {
pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n");
- no_timeout = 1;
+ no_timeout = true;
} else {
xdev.wdt_interval = *tmptr;
}
--
1.8.2.3
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* [PATCH v2 03/11] watchdog: xilinx: Simplify probe and remove functions
From: Michal Simek @ 2014-02-11 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f298edd222c57b0ce1ebad3ae50c3f715406c631.1392101734.git.michal.simek@xilinx.com>
Use devm_ helper function to simplify probe and error path.
Move ioremap to the beginning of probe function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
Changes in v2: None
drivers/watchdog/of_xilinx_wdt.c | 41 +++++++++-------------------------------
1 file changed, 9 insertions(+), 32 deletions(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index aca9bab..7f371ed 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -12,6 +12,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include <linux/err.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
@@ -44,7 +45,6 @@
#define PFX WATCHDOG_NAME ": "
struct xwdt_device {
- struct resource res;
void __iomem *base;
u32 wdt_interval;
};
@@ -159,9 +159,15 @@ static int xwdt_probe(struct platform_device *pdev)
int rc;
u32 *tmptr;
u32 *pfreq;
+ struct resource *res;
no_timeout = 0;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ xdev.base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(xdev.base))
+ return PTR_ERR(xdev.base);
+
pfreq = (u32 *)of_get_property(pdev->dev.of_node,
"clock-frequency", NULL);
@@ -170,12 +176,6 @@ static int xwdt_probe(struct platform_device *pdev)
no_timeout = 1;
}
- rc = of_address_to_resource(pdev->dev.of_node, 0, &xdev.res);
- if (rc) {
- pr_warn("invalid address!\n");
- return rc;
- }
-
tmptr = (u32 *)of_get_property(pdev->dev.of_node,
"xlnx,wdt-interval", NULL);
if (tmptr == NULL) {
@@ -199,50 +199,27 @@ static int xwdt_probe(struct platform_device *pdev)
if (!no_timeout)
timeout = 2 * ((1<<xdev.wdt_interval) / *pfreq);
- if (!request_mem_region(xdev.res.start,
- xdev.res.end - xdev.res.start + 1, WATCHDOG_NAME)) {
- rc = -ENXIO;
- pr_err("memory request failure!\n");
- goto err_out;
- }
-
- xdev.base = ioremap(xdev.res.start, xdev.res.end - xdev.res.start + 1);
- if (xdev.base == NULL) {
- rc = -ENOMEM;
- pr_err("ioremap failure!\n");
- goto release_mem;
- }
-
rc = xwdt_selftest();
if (rc == XWT_TIMER_FAILED) {
pr_err("SelfTest routine error!\n");
- goto unmap_io;
+ return rc;
}
rc = watchdog_register_device(&xilinx_wdt_wdd);
if (rc) {
pr_err("cannot register watchdog (err=%d)\n", rc);
- goto unmap_io;
+ return rc;
}
dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
xdev.base, timeout);
return 0;
-
-unmap_io:
- iounmap(xdev.base);
-release_mem:
- release_mem_region(xdev.res.start, resource_size(&xdev.res));
-err_out:
- return rc;
}
static int xwdt_remove(struct platform_device *dev)
{
watchdog_unregister_device(&xilinx_wdt_wdd);
- iounmap(xdev.base);
- release_mem_region(xdev.res.start, resource_size(&xdev.res));
return 0;
}
--
1.8.2.3
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* [PATCH v2 02/11] watchdog: xilinx: Move control_status_reg to functions
From: Michal Simek @ 2014-02-11 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f298edd222c57b0ce1ebad3ae50c3f715406c631.1392101734.git.michal.simek@xilinx.com>
control_status_reg is temp variables and should be
used locally by specific function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
Changes in v2: None
drivers/watchdog/of_xilinx_wdt.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index 8c2814e..aca9bab 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -52,13 +52,14 @@ struct xwdt_device {
static struct xwdt_device xdev;
static u32 timeout;
-static u32 control_status_reg;
static u8 no_timeout;
static DEFINE_SPINLOCK(spinlock);
static int xilinx_wdt_start(struct watchdog_device *wdd)
{
+ u32 control_status_reg;
+
spin_lock(&spinlock);
/* Clean previous status and enable the watchdog timer */
@@ -77,6 +78,8 @@ static int xilinx_wdt_start(struct watchdog_device *wdd)
static int xilinx_wdt_stop(struct watchdog_device *wdd)
{
+ u32 control_status_reg;
+
spin_lock(&spinlock);
control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
@@ -94,6 +97,8 @@ static int xilinx_wdt_stop(struct watchdog_device *wdd)
static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
{
+ u32 control_status_reg;
+
spin_lock(&spinlock);
control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
--
1.8.2.3
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^ permalink raw reply related
* [PATCH v2 01/11] watchdog: xilinx: Convert driver to the watchdog framework
From: Michal Simek @ 2014-02-11 6:55 UTC (permalink / raw)
To: linux-arm-kernel
- Remove uneeded headers, fops functions
- Use xilinx_wdt prefix in start/stop/keepalive functions
and in new structures
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
Changes in v2: None
drivers/watchdog/Kconfig | 1 +
drivers/watchdog/of_xilinx_wdt.c | 204 ++++++---------------------------------
2 files changed, 33 insertions(+), 172 deletions(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 4c4c566..9db5d3c 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1025,6 +1025,7 @@ config M54xx_WATCHDOG
config XILINX_WATCHDOG
tristate "Xilinx Watchdog timer"
depends on MICROBLAZE
+ select WATCHDOG_CORE
---help---
Watchdog driver for the xps_timebase_wdt ip core.
diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index fb57103..8c2814e 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -1,6 +1,7 @@
/*
* Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc.
* (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
*
* This program is free software; you can redistribute it and/or
@@ -14,13 +15,10 @@
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/watchdog.h>
#include <linux/io.h>
-#include <linux/uaccess.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
@@ -48,22 +46,18 @@
struct xwdt_device {
struct resource res;
void __iomem *base;
- u32 nowayout;
u32 wdt_interval;
- u32 boot_status;
};
static struct xwdt_device xdev;
static u32 timeout;
static u32 control_status_reg;
-static u8 expect_close;
static u8 no_timeout;
-static unsigned long driver_open;
static DEFINE_SPINLOCK(spinlock);
-static void xwdt_start(void)
+static int xilinx_wdt_start(struct watchdog_device *wdd)
{
spin_lock(&spinlock);
@@ -77,9 +71,11 @@ static void xwdt_start(void)
iowrite32(XWT_CSRX_EWDT2_MASK, xdev.base + XWT_TWCSR1_OFFSET);
spin_unlock(&spinlock);
+
+ return 0;
}
-static void xwdt_stop(void)
+static int xilinx_wdt_stop(struct watchdog_device *wdd)
{
spin_lock(&spinlock);
@@ -92,9 +88,11 @@ static void xwdt_stop(void)
spin_unlock(&spinlock);
pr_info("Stopped!\n");
+
+ return 0;
}
-static void xwdt_keepalive(void)
+static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
{
spin_lock(&spinlock);
@@ -103,23 +101,28 @@ static void xwdt_keepalive(void)
iowrite32(control_status_reg, xdev.base + XWT_TWCSR0_OFFSET);
spin_unlock(&spinlock);
-}
-static void xwdt_get_status(int *status)
-{
- int new_status;
+ return 0;
+}
- spin_lock(&spinlock);
+static const struct watchdog_info xilinx_wdt_ident = {
+ .options = WDIOF_MAGICCLOSE |
+ WDIOF_KEEPALIVEPING,
+ .firmware_version = 1,
+ .identity = WATCHDOG_NAME,
+};
- control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
- new_status = ((control_status_reg &
- (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK)) != 0);
- spin_unlock(&spinlock);
+static const struct watchdog_ops xilinx_wdt_ops = {
+ .owner = THIS_MODULE,
+ .start = xilinx_wdt_start,
+ .stop = xilinx_wdt_stop,
+ .ping = xilinx_wdt_keepalive,
+};
- *status = 0;
- if (new_status & 1)
- *status |= WDIOF_CARDRESET;
-}
+static struct watchdog_device xilinx_wdt_wdd = {
+ .info = &xilinx_wdt_ident,
+ .ops = &xilinx_wdt_ops,
+};
static u32 xwdt_selftest(void)
{
@@ -146,139 +149,6 @@ static u32 xwdt_selftest(void)
return XWT_TIMER_FAILED;
}
-static int xwdt_open(struct inode *inode, struct file *file)
-{
- /* Only one process can handle the wdt at a time */
- if (test_and_set_bit(0, &driver_open))
- return -EBUSY;
-
- /* Make sure that the module are always loaded...*/
- if (xdev.nowayout)
- __module_get(THIS_MODULE);
-
- xwdt_start();
- pr_info("Started...\n");
-
- return nonseekable_open(inode, file);
-}
-
-static int xwdt_release(struct inode *inode, struct file *file)
-{
- if (expect_close == 42) {
- xwdt_stop();
- } else {
- pr_crit("Unexpected close, not stopping watchdog!\n");
- xwdt_keepalive();
- }
-
- clear_bit(0, &driver_open);
- expect_close = 0;
- return 0;
-}
-
-/*
- * xwdt_write:
- * @file: file handle to the watchdog
- * @buf: buffer to write (unused as data does not matter here
- * @count: count of bytes
- * @ppos: pointer to the position to write. No seeks allowed
- *
- * A write to a watchdog device is defined as a keepalive signal. Any
- * write of data will do, as we don't define content meaning.
- */
-static ssize_t xwdt_write(struct file *file, const char __user *buf,
- size_t len, loff_t *ppos)
-{
- if (len) {
- if (!xdev.nowayout) {
- size_t i;
-
- /* In case it was set long ago */
- expect_close = 0;
-
- for (i = 0; i != len; i++) {
- char c;
-
- if (get_user(c, buf + i))
- return -EFAULT;
- if (c == 'V')
- expect_close = 42;
- }
- }
- xwdt_keepalive();
- }
- return len;
-}
-
-static const struct watchdog_info ident = {
- .options = WDIOF_MAGICCLOSE |
- WDIOF_KEEPALIVEPING,
- .firmware_version = 1,
- .identity = WATCHDOG_NAME,
-};
-
-/*
- * xwdt_ioctl:
- * @file: file handle to the device
- * @cmd: watchdog command
- * @arg: argument pointer
- *
- * The watchdog API defines a common set of functions for all watchdogs
- * according to their available features.
- */
-static long xwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- int status;
-
- union {
- struct watchdog_info __user *ident;
- int __user *i;
- } uarg;
-
- uarg.i = (int __user *)arg;
-
- switch (cmd) {
- case WDIOC_GETSUPPORT:
- return copy_to_user(uarg.ident, &ident,
- sizeof(ident)) ? -EFAULT : 0;
-
- case WDIOC_GETBOOTSTATUS:
- return put_user(xdev.boot_status, uarg.i);
-
- case WDIOC_GETSTATUS:
- xwdt_get_status(&status);
- return put_user(status, uarg.i);
-
- case WDIOC_KEEPALIVE:
- xwdt_keepalive();
- return 0;
-
- case WDIOC_GETTIMEOUT:
- if (no_timeout)
- return -ENOTTY;
- else
- return put_user(timeout, uarg.i);
-
- default:
- return -ENOTTY;
- }
-}
-
-static const struct file_operations xwdt_fops = {
- .owner = THIS_MODULE,
- .llseek = no_llseek,
- .write = xwdt_write,
- .open = xwdt_open,
- .release = xwdt_release,
- .unlocked_ioctl = xwdt_ioctl,
-};
-
-static struct miscdevice xwdt_miscdev = {
- .minor = WATCHDOG_MINOR,
- .name = "watchdog",
- .fops = &xwdt_fops,
-};
-
static int xwdt_probe(struct platform_device *pdev)
{
int rc;
@@ -314,7 +184,7 @@ static int xwdt_probe(struct platform_device *pdev)
"xlnx,wdt-enable-once", NULL);
if (tmptr == NULL) {
pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n");
- xdev.nowayout = WATCHDOG_NOWAYOUT;
+ watchdog_set_nowayout(&xilinx_wdt_wdd, true);
}
/*
@@ -344,24 +214,14 @@ static int xwdt_probe(struct platform_device *pdev)
goto unmap_io;
}
- xwdt_get_status(&xdev.boot_status);
-
- rc = misc_register(&xwdt_miscdev);
+ rc = watchdog_register_device(&xilinx_wdt_wdd);
if (rc) {
- pr_err("cannot register miscdev on minor=%d (err=%d)\n",
- xwdt_miscdev.minor, rc);
+ pr_err("cannot register watchdog (err=%d)\n", rc);
goto unmap_io;
}
- if (no_timeout)
- pr_info("driver loaded (timeout=? sec, nowayout=%d)\n",
- xdev.nowayout);
- else
- pr_info("driver loaded (timeout=%d sec, nowayout=%d)\n",
- timeout, xdev.nowayout);
-
- expect_close = 0;
- clear_bit(0, &driver_open);
+ dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
+ xdev.base, timeout);
return 0;
@@ -375,7 +235,7 @@ err_out:
static int xwdt_remove(struct platform_device *dev)
{
- misc_deregister(&xwdt_miscdev);
+ watchdog_unregister_device(&xilinx_wdt_wdd);
iounmap(xdev.base);
release_mem_region(xdev.res.start, resource_size(&xdev.res));
--
1.8.2.3
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* [PATCH] sched_clock: Prevent callers from seeing half-updated data
From: Stephen Boyd @ 2014-02-11 6:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F55E14.9080609@linaro.org>
On 02/07, John Stultz wrote:
> On 02/07/2014 02:22 PM, Stephen Boyd wrote:
> > On 02/07, Stephen Boyd wrote:
> >> If two sched_clock sources are registered we may end up in a
> >> situation where a call to sched_clock() may be accessing the
> >> epoch cycle count for the old counter and the cycle count for the
> >> new counter. This can lead to confusing results where
> >> sched_clock() values jump and then are reset to 0 (due to the way
> >> the registration function forces the epoch_ns to be 0). Fix this
> >> by reorganizing the registration function to hold the seqlock for
> >> as short a time as possible while we update the clock_data
> >> structure for a new counter and stop resetting the epoch_ns count
> >> to 0.
> > Hmm.. This won't properly accumulate time. We need to put
> > whatever time has elapsed into epoch_ns when we register the new
> > counter for this to work. I don't have a board with this
> > configuration but I'll send a v2 that should fix this. Hopefully
> > Will can test it.
>
> Also maybe clarify in the commit message that this is a result of not
> having the necessary locking in place in the registration code (likely
> due to it not really being required in the single clock case), just so
> Ingo and others have some more context as to why this is needed now and
> wasn't hit before.
>
Hmph... I already sent v2 before you replied. Is the commit text
good enough? I do mention that this is about two sched_clock
sources being registered.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* [PATCH] video: xilinxfb: Move xilinxfb_platform_data directly to the driver
From: Michal Simek @ 2014-02-11 6:48 UTC (permalink / raw)
To: linux-arm-kernel
No reason to have separate file in header in include/linux folder
if this is purely driver specific structure.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
I have this patch in my devel tree for a while and would like
to hear your opinion. I can't see any reason to have
xilinxfb_platform_data in header if this is purely OF driver
used on OF archs.
---
drivers/video/xilinxfb.c | 15 ++++++++++++++-
include/linux/xilinxfb.h | 30 ------------------------------
2 files changed, 14 insertions(+), 31 deletions(-)
delete mode 100644 include/linux/xilinxfb.h
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index 6ff1a91..553cff2 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -33,7 +33,6 @@
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/io.h>
-#include <linux/xilinxfb.h>
#include <linux/slab.h>
#ifdef CONFIG_PPC_DCR
@@ -84,6 +83,20 @@
#define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */
+/* ML300/403 reference design framebuffer driver platform data struct */
+struct xilinxfb_platform_data {
+ u32 rotate_screen; /* Flag to rotate display 180 degrees */
+ u32 screen_height_mm; /* Physical dimensions of screen in mm */
+ u32 screen_width_mm;
+ u32 xres, yres; /* resolution of screen in pixels */
+ u32 xvirt, yvirt; /* resolution of memory buffer */
+
+ /* Physical address of framebuffer memory; If non-zero, driver
+ * will use provided memory address instead of allocating one from
+ * the consistent pool. */
+ u32 fb_phys;
+};
+
/*
* Default xilinxfb configuration
*/
diff --git a/include/linux/xilinxfb.h b/include/linux/xilinxfb.h
deleted file mode 100644
index 5a155a9..0000000
--- a/include/linux/xilinxfb.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Platform device data for Xilinx Framebuffer device
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef __XILINXFB_H__
-#define __XILINXFB_H__
-
-#include <linux/types.h>
-
-/* ML300/403 reference design framebuffer driver platform data struct */
-struct xilinxfb_platform_data {
- u32 rotate_screen; /* Flag to rotate display 180 degrees */
- u32 screen_height_mm; /* Physical dimensions of screen in mm */
- u32 screen_width_mm;
- u32 xres, yres; /* resolution of screen in pixels */
- u32 xvirt, yvirt; /* resolution of memory buffer */
-
- /* Physical address of framebuffer memory; If non-zero, driver
- * will use provided memory address instead of allocating one from
- * the consistent pool. */
- u32 fb_phys;
-};
-
-#endif /* __XILINXFB_H__ */
--
1.8.2.3
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^ permalink raw reply related
* [PATCH v3 0/7] Modernize pm8921 with irqdomains, regmap, DT
From: Stephen Boyd @ 2014-02-11 6:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1389206270-3728-1-git-send-email-sboyd@codeaurora.org>
On 01/08, Stephen Boyd wrote:
> These patches lay the groundwork for converting the pm8921 sub-devices
> to devicetree as well as simplify the API by migrating the core code
> to use the regmap API instead of the custom pm8xxx read/write wrapper.
Lee,
Can you pick up these patches now? I don't think we're going to
get an ack from the DT reviewers. Its been over a month and
according to the documentation[1] I think we've done our due
diligence.
[1] Documentation/devicetree/bindings/submitting-patches.txt
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* [PATCH 3/3] Documentation: DT: add new entry for Samsung GH7 SoC and SSDK board
From: Kukjin Kim @ 2014-02-11 6:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392100183-30930-1-git-send-email-kgene.kim@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
---
Documentation/devicetree/bindings/arm/samsung-boards.txt | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung-boards.txt
index 2168ed3..9284db3 100644
--- a/Documentation/devicetree/bindings/arm/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung-boards.txt
@@ -16,3 +16,13 @@ Optional:
compatible = "samsung,secure-firmware";
reg = <0x0203F000 0x1000>;
};
+
+* Samsung's GH7 based SSDK-GH7 evaluation board
+
+SSDK-GH7 evaluation board is based on Samsung's GH7 SoC which has ARMv8 cores.
+
+Required root node properties:
+ - compatible = should be one or more of the following.
+ (a) "samsung,ssdk-gh7" - for Samsung's SSDK-GH7 eval board.
+ (b) "samsung,gh7" - for boards based on GH7 SoC.
+
--
1.7.10.4
^ permalink raw reply related
* [PATCH 2/3] arm64: Add Kconfig option for Samsung GH7 SoC family
From: Kukjin Kim @ 2014-02-11 6:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392100183-30930-1-git-send-email-kgene.kim@samsung.com>
This patch adds support for Samsung GH7 SoC in arm64/Kconfig.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/Kconfig | 5 +++++
arch/arm64/boot/dts/Makefile | 1 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index dd4327f..7d71823 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -111,6 +111,11 @@ source "kernel/Kconfig.freezer"
menu "Platform selection"
+config ARCH_GH7
+ bool "Samsung ARMv8 GH7 SoC"
+ help
+ This enables support for Samsung GH7 SoC
+
config ARCH_VEXPRESS
bool "ARMv8 software model (Versatile Express)"
select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index c52bdb0..54fb0cf 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_GH7) += samsung-ssdk-gh7.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
--
1.7.10.4
^ permalink raw reply related
* [PATCH 1/3] arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
From: Kukjin Kim @ 2014-02-11 6:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392100183-30930-1-git-send-email-kgene.kim@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/boot/dts/samsung-gh7.dtsi | 108 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/samsung-ssdk-gh7.dts | 26 +++++++
2 files changed, 134 insertions(+)
create mode 100644 arch/arm64/boot/dts/samsung-gh7.dtsi
create mode 100644 arch/arm64/boot/dts/samsung-ssdk-gh7.dts
diff --git a/arch/arm64/boot/dts/samsung-gh7.dtsi b/arch/arm64/boot/dts/samsung-gh7.dtsi
new file mode 100644
index 0000000..5b8785c
--- /dev/null
+++ b/arch/arm64/boot/dts/samsung-gh7.dtsi
@@ -0,0 +1,108 @@
+/*
+ * SAMSUNG GH7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+
+/memreserve/ 0x80000000 0x0C400000;
+
+/ {
+ model = "SAMSUNG GH7";
+ compatible = "samsung,gh7";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu at 000 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x8000fff8>;
+ };
+ cpu at 001 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x8000fff8>;
+ };
+ cpu at 002 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x002>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x8000fff8>;
+ };
+ cpu at 003 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x003>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x8000fff8>;
+ };
+ };
+
+ gic: interrupt-controller at 1C000000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x1C001000 0 0x1000>, /* GIC Dist */
+ <0x0 0x1C002000 0 0x1000>, /* GIC CPU */
+ <0x0 0x1C004000 0 0x2000>, /* GIC VCPU Control */
+ <0x0 0x1C006000 0 0x2000>; /* GIC VCPU */
+ interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xff01>, /* Secure Phys IRQ */
+ <1 14 0xff01>, /* Non-secure Phys IRQ */
+ <1 11 0xff01>, /* Virt IRQ */
+ <1 10 0xff01>; /* Hyp IRQ */
+ clock-frequency = <100000000>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 294 8>,
+ <0 295 8>,
+ <0 296 8>,
+ <0 297 8>,
+ <0 298 8>,
+ <0 299 8>,
+ <0 300 8>,
+ <0 301 8>;
+ };
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ serial at 12c00000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12c00000 0x10000>;
+ interrupts = <418>;
+ };
+
+ serial at 12c20000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12c20000 0x10000>;
+ interrupts = <420>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/samsung-ssdk-gh7.dts b/arch/arm64/boot/dts/samsung-ssdk-gh7.dts
new file mode 100644
index 0000000..47afbc4
--- /dev/null
+++ b/arch/arm64/boot/dts/samsung-ssdk-gh7.dts
@@ -0,0 +1,26 @@
+/*
+ * SAMSUNG SSDK-GH7 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "samsung-gh7.dtsi"
+
+/ {
+ model = "SAMSUNG SSDK-GH7 board based on GH7 SoC";
+ compatible = "samsung,ssdk-gh7", "samsung,gh7";
+
+ chosen {
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x80000000>;
+ };
+};
--
1.7.10.4
^ permalink raw reply related
* [PATCH 0/3] arm64: add new support Samsung GH7 SoC and SSDK board
From: Kukjin Kim @ 2014-02-11 6:29 UTC (permalink / raw)
To: linux-arm-kernel
This adds support for Samsung ARMv8 core based GH7 SoC and its evaluation SSDK board.
[PATCH 1/3] arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
[PATCH 2/3] arm64: Add Kconfig option for Samsung GH7 SoC family
[PATCH 3/3] Documentation: DT: add new entry for Samsung GH7 SoC and SSDK board
^ permalink raw reply
* [PATCH] ARM: imx: avoid calling clk APIs in idle thread which may cause schedule
From: Shawn Guo @ 2014-02-11 6:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392014090-27984-1-git-send-email-b20788@freescale.com>
On Mon, Feb 10, 2014 at 02:34:50PM +0800, Anson Huang wrote:
> @@ -81,19 +99,67 @@ static const u32 clks_init_on[] __initconst = {
> * entering WAIT mode.
> *
> * This function will set the ARM clk to max value within the 12:5 limit.
> + * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
> + * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
> + * the clk APIs can NOT be called in idle thread(may cause kernel schedule
> + * as there is sleep function in PLL wait function), so here we just slow
> + * down ARM to below freq according to previous freq:
> + *
> + * run mode wait mode
> + * 396MHz -> 132MHz;
> + * 792MHz -> 158.4MHz;
> + * 996MHz -> 142.3MHz;
> */
> +static int imx6sl_get_arm_divider_for_wait(void)
> +{
> + if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) {
> + return ARM_WAIT_DIV_396M;
> + } else {
> + if ((readl_relaxed(anatop_base + PLL_ARM) &
> + BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M)
> + return ARM_WAIT_DIV_792M;
> + else
> + return ARM_WAIT_DIV_996M;
> + }
> +}
> +
> +static void imx6sl_enable_pll_arm(bool enable)
> +{
> + static u32 saved_pll_arm;
> + u32 val;
> +
> + if (enable) {
> + saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
> + val |= BM_PLL_ARM_ENABLE;
> + val &= ~BM_PLL_ARM_POWERDOWN;
> + writel_relaxed(val, anatop_base + PLL_ARM);
> + while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
> + ;
> + } else {
> + writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
> + }
> +}
> +
> void imx6sl_set_wait_clk(bool enter)
> {
> - static unsigned long saved_arm_rate;
> + static unsigned long saved_arm_div;
>
> + /*
> + * According to hardware design, arm podf change need
> + * PLL1 clock enabled.
> + */
> + imx6sl_enable_pll_arm(true);
This only applies to the ARM_WAIT_DIV_396M case, since for the other two
PLL1 must already be enabled, right?
> if (enter) {
> - unsigned long ipg_rate = clk_get_rate(clks[IMX6SL_CLK_IPG]);
> - unsigned long max_arm_wait_rate = (12 * ipg_rate) / 5;
> - saved_arm_rate = clk_get_rate(clks[IMX6SL_CLK_ARM]);
> - clk_set_rate(clks[IMX6SL_CLK_ARM], max_arm_wait_rate);
> + saved_arm_div = readl_relaxed(ccm_base + CACRR);
> + writel_relaxed(imx6sl_get_arm_divider_for_wait(),
> + ccm_base + CACRR);
> } else {
> - clk_set_rate(clks[IMX6SL_CLK_ARM], saved_arm_rate);
> + writel_relaxed(saved_arm_div, ccm_base + CACRR);
> }
> +
> + while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
> + ;
> + imx6sl_enable_pll_arm(false);
> }
>
> static void __init imx6sl_clocks_init(struct device_node *ccm_node)
> @@ -110,6 +176,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
>
> np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
> base = of_iomap(np, 0);
> + anatop_base = base;
More logical to put it after the WARN_ON() below?
> WARN_ON(!base);
>
> /* type name parent base div_mask */
> @@ -157,6 +224,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
>
> np = ccm_node;
> base = of_iomap(np, 0);
> + ccm_base = base;
Ditto.
Shawn
> WARN_ON(!base);
>
> /* Reuse imx6q pm code */
> --
> 1.7.9.5
>
>
^ permalink raw reply
* [PATCH v1 0/1] Boot all secondary cores on Exynos SoC's
From: Sachin Kamat @ 2014-02-11 6:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392084929-14116-1-git-send-email-t.dakhran@samsung.com>
Hi Tarek,
On 11 February 2014 07:45, Tarek Dakhran <t.dakhran@samsung.com> wrote:
> Due to implementation of exynos_boot_secondary function
> only one secondary core boots on Exynos SoC's.
Even without this patch I could boot the secondary CPUs on Exynos4210, 4412 and
5250 based boards with the latest Linux kernel (v3.14-rc2+). Is this
patch required for
a specific use case or am I missing something?
---
With warm regards,
Sachin
^ permalink raw reply
* [PATCH 00/12] ARM: S3C24XX: convert s3c2410, s3c2440 s3c2442 to common clock framework
From: Kukjin Kim @ 2014-02-11 6:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52F7DD6E.8070303@gmail.com>
2014-02-10 1:26 GMT+05:30 Tomasz Figa <tomasz.figa@gmail.com>:
> Hi Heiko,
>
>
> On 13.12.2013 13:56, Heiko St?bner wrote:
>>
>> This series converts the earliest s3c socs to use a clock driver based on
>> the
>> common clock framework instead of the old Samsung clock implementation.
>>
>> The only obstacle I found was the configuration of the clkout outputs in
>> the different machines. As I lack hardware test and knowledge on what is
>> expected there, somebody with interest in these machines will have to
>> step up to implement the clkout configuration
>> This can for example be done in the machine_init function after
>> the platform-devices (and thus the dclk-device) are populated.
>>
>> This leaves the s3c2412 soc to be converted, as it has yet another
>> different
>> clock tree.
>>
>> Tested on an Openmoko Neo Freerunner (S3C2442), but of course more tests
>> would be really helpful.
>>
>> Heiko Stuebner (12):
>> ARM: S3C24XX: cpufreq-utils: don't write raw values to MPLLCON when
>> using ccf
>> dt-bindings: document s3c24xx controller for external clock output
>> clk: samsung: add clock driver for external clock outputs
>> ARM: S3C24XX: enable usage of common dclk if common clock framework is
>> enabled
>> ARM: S3C24XX: only store clock registers when old clock code is active
>> clk: samsung: add plls used by the early s3c24xx cpus
>> dt-bindings: add documentation for s3c2410 clock controller
>> clk: samsung: add clock controller driver for s3c2410, s3c2440 and
>> s3c2442
>> ARM: S3C24XX: add platform code for conversion to the common clock
>> framework
>> ARM: S3C24XX: convert s3c2440 and s3c2442 to common clock framework
>> ARM: S3C24XX: convert s3c2410 to common clock framework
>> ARM: S3C24XX: remove legacy clock code
>>
>> .../bindings/clock/samsung,s3c2410-clock.txt | 50 ++
>> .../bindings/clock/samsung,s3c2410-dclk.txt | 53 ++
>> arch/arm/mach-s3c24xx/Kconfig | 50 +-
>> arch/arm/mach-s3c24xx/Makefile | 6 +-
>> arch/arm/mach-s3c24xx/clock-dclk.c | 195 --------
>> arch/arm/mach-s3c24xx/clock-s3c2410.c | 285 -----------
>> arch/arm/mach-s3c24xx/clock-s3c2440.c | 217 --------
>> arch/arm/mach-s3c24xx/clock-s3c244x.c | 141 ------
>> arch/arm/mach-s3c24xx/common.c | 45 +-
>> arch/arm/mach-s3c24xx/common.h | 11 +-
>> arch/arm/mach-s3c24xx/cpufreq-utils.c | 13 +
>> arch/arm/mach-s3c24xx/include/mach/regs-clock.h | 18 -
>> arch/arm/mach-s3c24xx/include/mach/regs-gpio.h | 3 -
>> arch/arm/mach-s3c24xx/mach-amlm5900.c | 9 +-
>> arch/arm/mach-s3c24xx/mach-anubis.c | 15 +-
>> arch/arm/mach-s3c24xx/mach-at2440evb.c | 10 +-
>> arch/arm/mach-s3c24xx/mach-bast.c | 15 +-
>> arch/arm/mach-s3c24xx/mach-gta02.c | 8 +-
>> arch/arm/mach-s3c24xx/mach-h1940.c | 10 +-
>> arch/arm/mach-s3c24xx/mach-mini2440.c | 10 +-
>> arch/arm/mach-s3c24xx/mach-n30.c | 12 +-
>> arch/arm/mach-s3c24xx/mach-nexcoder.c | 10 +-
>> arch/arm/mach-s3c24xx/mach-osiris.c | 15 +-
>> arch/arm/mach-s3c24xx/mach-otom.c | 10 +-
>> arch/arm/mach-s3c24xx/mach-qt2410.c | 9 +-
>> arch/arm/mach-s3c24xx/mach-rx1950.c | 15 +-
>> arch/arm/mach-s3c24xx/mach-rx3715.c | 10 +-
>> arch/arm/mach-s3c24xx/mach-smdk2410.c | 9 +-
>> arch/arm/mach-s3c24xx/mach-smdk2440.c | 10 +-
>> arch/arm/mach-s3c24xx/mach-tct_hammer.c | 9 +-
>> arch/arm/mach-s3c24xx/mach-vr1000.c | 15 +-
>> arch/arm/mach-s3c24xx/pm.c | 13 +-
>> arch/arm/mach-s3c24xx/s3c2410.c | 56 ---
>> arch/arm/mach-s3c24xx/s3c2442.c | 111 -----
>> arch/arm/mach-s3c24xx/s3c244x.c | 59 +--
>> drivers/clk/samsung/Makefile | 2 +
>> drivers/clk/samsung/clk-pll.c | 182 +++++++
>> drivers/clk/samsung/clk-pll.h | 3 +
>> drivers/clk/samsung/clk-s3c2410-dclk.c | 517
>> ++++++++++++++++++++
>> drivers/clk/samsung/clk-s3c2410.c | 428
>> ++++++++++++++++
>> include/dt-bindings/clock/samsung,s3c2410-clock.h | 64 +++
>> include/dt-bindings/clock/samsung,s3c2410-dclk.h | 28 ++
>> 42 files changed, 1575 insertions(+), 1176 deletions(-)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt
>> create mode 100644
>> Documentation/devicetree/bindings/clock/samsung,s3c2410-dclk.txt
>> delete mode 100644 arch/arm/mach-s3c24xx/clock-dclk.c
>> delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2410.c
>> delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2440.c
>> delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c244x.c
>> create mode 100644 drivers/clk/samsung/clk-s3c2410-dclk.c
>> create mode 100644 drivers/clk/samsung/clk-s3c2410.c
>> create mode 100644 include/dt-bindings/clock/samsung,s3c2410-clock.h
>> create mode 100644 include/dt-bindings/clock/samsung,s3c2410-dclk.h
>>
>
> For patches 4, 5, 9, 10, 11, 12:
>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
>
> For patches 6, 7:
>
> Acked-by: Tomasz Figa <t.figa@samsung.com>
>
Really nice series.
Heiko, thanks for your effort and Tomasz, thanks for your review and ack.
OK, I'll apply this whole series and this will be sent to arm-soc in this week.
Thanks,
Kukjin
^ permalink raw reply
* [PATCH v3 2/2] spi:dspi:Remove some coding sytle not in standard
From: Chao Fu @ 2014-02-11 5:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392097697-14919-1-git-send-email-b44548@freescale.com>
From: Chao Fu <B44548@freescale.com>
Remove some coding sytle not in standard in former code.
Signed-off-by: Chao Fu <b44548@freescale.com>
---
Change in v3:
None.
Change in v2:
New.
drivers/spi/spi-fsl-dspi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index fb16575..42ede0d 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -111,9 +111,9 @@ struct fsl_dspi {
struct regmap *regmap;
int irq;
- struct clk *clk;
+ struct clk *clk;
- struct spi_transfer *cur_transfer;
+ struct spi_transfer *cur_transfer;
struct chip_data *cur_chip;
size_t len;
void *tx;
@@ -124,8 +124,8 @@ struct fsl_dspi {
u8 cs;
u16 void_write_data;
- wait_queue_head_t waitq;
- u32 waitflags;
+ wait_queue_head_t waitq;
+ u32 waitflags;
};
static inline int is_double_byte_mode(struct fsl_dspi *dspi)
--
1.8.4
^ permalink raw reply related
* [PATCH v3 1/2] spi:fsl-dspi:convert to use regmap and big-endian supports
From: Chao Fu @ 2014-02-11 5:48 UTC (permalink / raw)
To: linux-arm-kernel
From: Chao Fu <B44548@freescale.com>
Freescale DSPI module will have two endianess in different platform,
but ARM is little endian. So when DSPI in big endian, core in little endian,
readl and writel can not adjust R/W register in this condition.
This patch will remove general readl/writel, and import regmap mechanism.
Data endian will be transfered in regmap APIs.
Documents: dspi add bool "big-endian" in dts node if DSPI module
work in big endian.
Signed-off-by: Chao Fu <b44548@freescale.com>
---
Change in v3:
Remove readl and wrirel, and import regmap mechanism to R/W module registers.
Change in v2:
Make dspi_readx dspi_writex as inline functions.
Modify the issue of indentation in function is_double_byte_mode.
Add description about big endian in bindings document.
.../devicetree/bindings/spi/spi-fsl-dspi.txt | 2 +
drivers/spi/spi-fsl-dspi.c | 80 ++++++++++++++--------
2 files changed, 55 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index a1fb303..5376de4 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -10,6 +10,7 @@ Required properties:
- pinctrl-names: must contain a "default" entry.
- spi-num-chipselects : the number of the chipselect signals.
- bus-num : the slave chip chipselect signal number.
+- big-endian : if DSPI modudle is big endian, the bool will be set in node.
Example:
dspi0 at 4002c000 {
@@ -24,6 +25,7 @@ dspi0 at 4002c000 {
bus-num = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi0_1>;
+ big-endian;
status = "okay";
sflash: at26df081a at 0 {
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index ec79f72..fb16575 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -18,6 +18,7 @@
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -108,7 +109,7 @@ struct fsl_dspi {
struct spi_bitbang bitbang;
struct platform_device *pdev;
- void __iomem *base;
+ struct regmap *regmap;
int irq;
struct clk *clk;
@@ -129,18 +130,11 @@ struct fsl_dspi {
static inline int is_double_byte_mode(struct fsl_dspi *dspi)
{
- return ((readl(dspi->base + SPI_CTAR(dspi->cs)) & SPI_FRAME_BITS_MASK)
- == SPI_FRAME_BITS(8)) ? 0 : 1;
-}
+ unsigned int val;
-static void set_bit_mode(struct fsl_dspi *dspi, unsigned char bits)
-{
- u32 temp;
+ regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
- temp = readl(dspi->base + SPI_CTAR(dspi->cs));
- temp &= ~SPI_FRAME_BITS_MASK;
- temp |= SPI_FRAME_BITS(bits);
- writel(temp, dspi->base + SPI_CTAR(dspi->cs));
+ return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
}
static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
@@ -188,7 +182,8 @@ static int dspi_transfer_write(struct fsl_dspi *dspi)
*/
if (tx_word && (dspi->len == 1)) {
dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
- set_bit_mode(dspi, 8);
+ regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
+ SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
tx_word = 0;
}
@@ -238,7 +233,8 @@ static int dspi_transfer_write(struct fsl_dspi *dspi)
dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
}
- writel(dspi_pushr, dspi->base + SPI_PUSHR);
+ regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
+
tx_count++;
}
@@ -253,17 +249,23 @@ static int dspi_transfer_read(struct fsl_dspi *dspi)
while ((dspi->rx < dspi->rx_end)
&& (rx_count < DSPI_FIFO_SIZE)) {
if (rx_word) {
+ unsigned int val;
+
if ((dspi->rx_end - dspi->rx) == 1)
break;
- d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR));
+ regmap_read(dspi->regmap, SPI_POPR, &val);
+ d = SPI_POPR_RXDATA(val);
if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
*(u16 *)dspi->rx = d;
dspi->rx += 2;
} else {
- d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR));
+ unsigned int val;
+
+ regmap_read(dspi->regmap, SPI_POPR, &val);
+ d = SPI_POPR_RXDATA(val);
if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
*(u8 *)dspi->rx = d;
dspi->rx++;
@@ -295,13 +297,13 @@ static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
if (!dspi->tx)
dspi->dataflags |= TRAN_STATE_TX_VOID;
- writel(dspi->cur_chip->mcr_val, dspi->base + SPI_MCR);
- writel(dspi->cur_chip->ctar_val, dspi->base + SPI_CTAR(dspi->cs));
- writel(SPI_RSER_EOQFE, dspi->base + SPI_RSER);
+ regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
+ regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi->cur_chip->ctar_val);
+ regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
if (t->speed_hz)
- writel(dspi->cur_chip->ctar_val,
- dspi->base + SPI_CTAR(dspi->cs));
+ regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
+ dspi->cur_chip->ctar_val);
dspi_transfer_write(dspi);
@@ -315,7 +317,9 @@ static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
static void dspi_chipselect(struct spi_device *spi, int value)
{
struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
- u32 pushr = readl(dspi->base + SPI_PUSHR);
+ unsigned int pushr;
+
+ regmap_read(dspi->regmap, SPI_PUSHR, &pushr);
switch (value) {
case BITBANG_CS_ACTIVE:
@@ -326,7 +330,7 @@ static void dspi_chipselect(struct spi_device *spi, int value)
break;
}
- writel(pushr, dspi->base + SPI_PUSHR);
+ regmap_write(dspi->regmap, SPI_PUSHR, pushr);
}
static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
@@ -382,13 +386,15 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
{
struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
- writel(SPI_SR_EOQF, dspi->base + SPI_SR);
+ regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
dspi_transfer_read(dspi);
if (!dspi->len) {
if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
- set_bit_mode(dspi, 16);
+ regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
+ SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
+
dspi->waitflags = 1;
wake_up_interruptible(&dspi->waitq);
} else {
@@ -435,12 +441,20 @@ static const struct dev_pm_ops dspi_pm = {
SET_SYSTEM_SLEEP_PM_OPS(dspi_suspend, dspi_resume)
};
+static struct regmap_config dspi_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x88,
+};
+
static int dspi_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct spi_master *master;
struct fsl_dspi *dspi;
struct resource *res;
+ void __iomem *base;
int ret = 0, cs_num, bus_num;
master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
@@ -475,12 +489,24 @@ static int dspi_probe(struct platform_device *pdev)
master->bus_num = bus_num;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- dspi->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(dspi->base)) {
- ret = PTR_ERR(dspi->base);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base)) {
+ ret = PTR_ERR(base);
goto out_master_put;
}
+ dspi_regmap_config.lock_arg = dspi;
+ dspi_regmap_config.val_format_endian =
+ of_property_read_bool(np, "big-endian")
+ ? REGMAP_ENDIAN_BIG : REGMAP_ENDIAN_DEFAULT;
+ dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
+ &dspi_regmap_config);
+ if (IS_ERR(dspi->regmap)) {
+ dev_err(&pdev->dev, "failed to init regmap: %ld\n",
+ PTR_ERR(dspi->regmap));
+ return PTR_ERR(dspi->regmap);
+ }
+
dspi->irq = platform_get_irq(pdev, 0);
if (dspi->irq < 0) {
dev_err(&pdev->dev, "can't get platform irq\n");
--
1.8.4
^ permalink raw reply related
* [PATCH v4 0/3] serial: fsl_lpuart: add DMA support
From: Shawn Guo @ 2014-02-11 5:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c2b2798647d44d3c950ce17f23551555@DM2PR03MB349.namprd03.prod.outlook.com>
On Tue, Feb 11, 2014 at 05:34:49AM +0000, Yao Yuan wrote:
> Here I also have a confusion.
> IRQ is must. But DMA isn't very necessary.
> How to deal with if one board is need DMA but another is not need?
> You mean if DMA is be support once all of them must use dma as first?
That's the point. Why whether using DMA or not is a board decision?
The DMA resource should be defined at SoC level from the beginning
just like IO and interrupt resource. And using DMA or PIO should be a
decision made by device driver not device tree.
Shawn
^ permalink raw reply
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