* [PATCH 1/3] ARM: mvebu: remove unneeded ->map_io field for Armada 370/XP
From: Jason Cooper @ 2014-02-11 19:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392138433-12573-2-git-send-email-thomas.petazzoni@free-electrons.com>
On Tue, Feb 11, 2014 at 06:07:11PM +0100, Thomas Petazzoni wrote:
> The ->map_io() implementation of Armada 370/XP simply calls
> debug_ll_io_init(), which is exactly what the kernel does when
> ->map_io is NULL. Therefore, there is no need to have a specific
> ->map_io() implementation in Armada 370/XP.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
> arch/arm/mach-mvebu/armada-370-xp.c | 6 ------
> 1 file changed, 6 deletions(-)
Applied to mvebu/soc with Gregory's Ack.
thx,
Jason.
^ permalink raw reply
* [PATCH v5 6/8] ARM: dts: sun4i: Add support for mmc
From: David Lanzendörfer @ 2014-02-11 19:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140211190543.4568.83517.stgit@dizzy-6.o2s.ch>
Signed-off-by: David Lanzend?rfer <david.lanzendoerfer@o2s.ch>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 8 ++++
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 8 ++++
arch/arm/boot/dts/sun4i-a10.dtsi | 54 ++++++++++++++++++++++++++++
3 files changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index d4b081d..a879ef3 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -35,6 +35,14 @@
};
};
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
emac_power_pin_a1000: emac_power_pin at 0 {
allwinner,pins = "PH15";
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b139ee6..20b976a 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -33,6 +33,14 @@
};
};
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
led_pins_cubieboard: led_pins at 0 {
allwinner,pins = "PH20", "PH21";
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 9044c53..d040d37 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -330,6 +330,46 @@
#size-cells = <0>;
};
+ mmc0: mmc at 01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <32>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc at 01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <33>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc at 01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <34>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc3: mmc at 01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <35>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
intc: interrupt-controller at 01c20400 {
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;
@@ -400,6 +440,20 @@
allwinner,drive = <0>;
allwinner,pull = <0>;
};
+
+ mmc0_pins_a: mmc0 at 0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
+ allwinner,pins = "PH1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
};
timer at 01c20c00 {
^ permalink raw reply related
* [PATCH v5 5/8] ARM: dts: sun7i: Add support for mmc
From: David Lanzendörfer @ 2014-02-11 19:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140211190543.4568.83517.stgit@dizzy-6.o2s.ch>
Signed-off-by: David Lanzend?rfer <david.lanzendoerfer@o2s.ch>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 8 +++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 8 +++
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +++++++++
arch/arm/boot/dts/sun7i-a20.dtsi | 61 +++++++++++++++++++++++
4 files changed, 100 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 5c51cb8..ae800b6 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -34,6 +34,14 @@
};
};
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
led_pins_cubieboard2: led_pins at 0 {
allwinner,pins = "PH20", "PH21";
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index f9dcb61..370cef84 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -19,6 +19,14 @@
compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
soc at 01c00000 {
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
led_pins_cubietruck: led_pins at 0 {
allwinner,pins = "PH7", "PH11", "PH20", "PH21";
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index ead3013..46dbe5b 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -34,7 +34,30 @@
};
};
+ mmc0: mmc at 01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
+ mmc3: mmc at 01c12000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ pinctrl-1 = <&mmc3_cd_pin_olinuxinom>;
+ cd-gpios = <&pio 7 11 0>; /* PH11 */
+ status = "okay";
+ };
+
pinctrl at 01c20800 {
+ mmc3_cd_pin_olinuxinom: mmc3_cd_pin at 0 {
+ allwinner,pins = "PH11";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
led_pins_olinuxino: led_pins at 0 {
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 9ff0948..1338d1e 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -355,6 +355,46 @@
#size-cells = <0>;
};
+ mmc0: mmc at 01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 32 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc at 01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 33 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc at 01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 34 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc3: mmc at 01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 35 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
pio: pinctrl at 01c20800 {
compatible = "allwinner,sun7i-a20-pinctrl";
reg = <0x01c20800 0x400>;
@@ -432,6 +472,27 @@
allwinner,drive = <0>;
allwinner,pull = <0>;
};
+
+ mmc0_pins_a: mmc0 at 0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
+ allwinner,pins = "PH1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ mmc3_pins_a: mmc3 at 0 {
+ allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
+ allwinner,function = "mmc3";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
};
timer at 01c20c00 {
^ permalink raw reply related
* [PATCH v5 4/8] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
From: David Lanzendörfer @ 2014-02-11 19:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140211190543.4568.83517.stgit@dizzy-6.o2s.ch>
This is based on the driver Allwinner ships in their Android kernel sources.
Initial porting to upstream kernels done by David Lanzend??rfer, additional
fixes and cleanups by Hans de Goede.
It uses dma in bus-master mode using a built-in designware idmac controller,
which is identical to the one found in the mmc-dw hosts.
The rest of the host is not identical to mmc-dw.
Signed-off-by: David Lanzend??rfer <david.lanzendoerfer@o2s.ch>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/mmc/host/Kconfig | 7
drivers/mmc/host/Makefile | 2
drivers/mmc/host/sunxi-mmc.c | 872 ++++++++++++++++++++++++++++++++++++++++++
drivers/mmc/host/sunxi-mmc.h | 239 ++++++++++++
4 files changed, 1120 insertions(+)
create mode 100644 drivers/mmc/host/sunxi-mmc.c
create mode 100644 drivers/mmc/host/sunxi-mmc.h
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 1384f67..7caf266 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -689,3 +689,10 @@ config MMC_REALTEK_PCI
help
Say Y here to include driver code to support SD/MMC card interface
of Realtek PCI-E card reader
+
+config MMC_SUNXI
+ tristate "Allwinner sunxi SD/MMC Host Controller support"
+ depends on ARCH_SUNXI
+ help
+ This selects support for the SD/MMC Host Controller on
+ Allwinner sunxi SoCs.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 3483b6b..f3c7c243 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -54,6 +54,8 @@ obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
+obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o
+
obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o
obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
new file mode 100644
index 0000000..5fc4634
--- /dev/null
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -0,0 +1,872 @@
+/*
+ * Driver for sunxi SD/MMC host controllers
+ * (C) Copyright 2014-2015 Reuuimlla Technology Co., Ltd.
+ * (C) Copyright 2014-2015 Aaron Maoye <leafy.myeh@reuuimllatech.com>
+ * (C) Copyright 2014-2015 O2S GmbH <www.o2s.ch>
+ * (C) Copyright 2014-2015 David Lanzend?rfer <david.lanzendoerfer@o2s.ch>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/clk/sunxi.h>
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/regulator/consumer.h>
+
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+
+#include <linux/mmc/host.h>
+#include <linux/mmc/sd.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/core.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/slot-gpio.h>
+
+#include "sunxi-mmc.h"
+
+static int sunxi_mmc_init_host(struct mmc_host *mmc)
+{
+ u32 rval;
+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
+ int ret;
+
+ ret = clk_prepare_enable(smc_host->clk_ahb);
+ if (ret) {
+ dev_err(mmc_dev(smc_host->mmc), "AHB clk err %d\n", ret);
+ return ret;
+ }
+ ret = clk_prepare_enable(smc_host->clk_mod);
+ if (ret) {
+ dev_err(mmc_dev(smc_host->mmc), "MOD clk err %d\n", ret);
+ clk_disable_unprepare(smc_host->clk_ahb);
+ return ret;
+ }
+
+ /* reset controller */
+ rval = mci_readl(smc_host, REG_GCTRL) | SDXC_HARDWARE_RESET;
+ mci_writel(smc_host, REG_GCTRL, rval);
+
+ mci_writel(smc_host, REG_FTRGL, 0x20070008);
+ mci_writel(smc_host, REG_TMOUT, 0xffffffff);
+ mci_writel(smc_host, REG_IMASK, smc_host->sdio_imask);
+ mci_writel(smc_host, REG_RINTR, 0xffffffff);
+ mci_writel(smc_host, REG_DBGC, 0xdeb);
+ mci_writel(smc_host, REG_FUNS, 0xceaa0000);
+ mci_writel(smc_host, REG_DLBA, smc_host->sg_dma);
+ rval = mci_readl(smc_host, REG_GCTRL)|SDXC_INTERRUPT_ENABLE_BIT;
+ rval &= ~SDXC_ACCESS_DONE_DIRECT;
+ mci_writel(smc_host, REG_GCTRL, rval);
+
+ return 0;
+}
+
+static void sunxi_mmc_exit_host(struct sunxi_mmc_host *smc_host)
+{
+ mci_writel(smc_host, REG_GCTRL, SDXC_HARDWARE_RESET);
+ clk_disable_unprepare(smc_host->clk_ahb);
+ clk_disable_unprepare(smc_host->clk_mod);
+}
+
+/* /\* UHS-I Operation Modes */
+/* * DS 25MHz 12.5MB/s 3.3V */
+/* * HS 50MHz 25MB/s 3.3V */
+/* * SDR12 25MHz 12.5MB/s 1.8V */
+/* * SDR25 50MHz 25MB/s 1.8V */
+/* * SDR50 100MHz 50MB/s 1.8V */
+/* * SDR104 208MHz 104MB/s 1.8V */
+/* * DDR50 50MHz 50MB/s 1.8V */
+/* * MMC Operation Modes */
+/* * DS 26MHz 26MB/s 3/1.8/1.2V */
+/* * HS 52MHz 52MB/s 3/1.8/1.2V */
+/* * HSDDR 52MHz 104MB/s 3/1.8/1.2V */
+/* * HS200 200MHz 200MB/s 1.8/1.2V */
+/* * */
+/* * Spec. Timing */
+/* * SD3.0 */
+/* * Fcclk Tcclk Fsclk Tsclk Tis Tih odly RTis RTih */
+/* * 400K 2.5us 24M 41ns 5ns 5ns 1 2209ns 41ns */
+/* * 25M 40ns 600M 1.67ns 5ns 5ns 3 14.99ns 5.01ns */
+/* * 50M 20ns 600M 1.67ns 6ns 2ns 3 14.99ns 5.01ns */
+/* * 50MDDR 20ns 600M 1.67ns 6ns 0.8ns 2 6.67ns 3.33ns */
+/* * 104M 9.6ns 600M 1.67ns 3ns 0.8ns 1 7.93ns 1.67ns */
+/* * 208M 4.8ns 600M 1.67ns 1.4ns 0.8ns 1 3.33ns 1.67ns */
+
+/* * 25M 40ns 300M 3.33ns 5ns 5ns 2 13.34ns 6.66ns */
+/* * 50M 20ns 300M 3.33ns 6ns 2ns 2 13.34ns 6.66ns */
+/* * 50MDDR 20ns 300M 3.33ns 6ns 0.8ns 1 6.67ns 3.33ns */
+/* * 104M 9.6ns 300M 3.33ns 3ns 0.8ns 0 7.93ns 1.67ns */
+/* * 208M 4.8ns 300M 3.33ns 1.4ns 0.8ns 0 3.13ns 1.67ns */
+
+/* * eMMC4.5 */
+/* * 400K 2.5us 24M 41ns 3ns 3ns 1 2209ns 41ns */
+/* * 25M 40ns 600M 1.67ns 3ns 3ns 3 14.99ns 5.01ns */
+/* * 50M 20ns 600M 1.67ns 3ns 3ns 3 14.99ns 5.01ns */
+/* * 50MDDR 20ns 600M 1.67ns 2.5ns 2.5ns 2 6.67ns 3.33ns */
+/* * 200M 5ns 600M 1.67ns 1.4ns 0.8ns 1 3.33ns 1.67ns */
+/* *\/ */
+
+static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
+ struct mmc_data *data)
+{
+ struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
+ struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma;
+ int i, max_len = (1 << host->idma_des_size_bits);
+
+ for (i = 0; i < data->sg_len; i++) {
+ pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
+ SDXC_IDMAC_DES0_DIC;
+
+ if (data->sg[i].length == max_len)
+ pdes[i].buf_size = 0; /* 0 == max_len */
+ else
+ pdes[i].buf_size = data->sg[i].length;
+
+ pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
+ pdes[i].buf_addr_ptr2 = (u32)&pdes_pa[i + 1];
+ }
+
+ pdes[0].config |= SDXC_IDMAC_DES0_FD;
+ pdes[i - 1].config = SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_LD;
+
+ wmb(); /* Ensure idma_des hit main mem before we start the idmac */
+}
+
+static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
+{
+ if (data->flags & MMC_DATA_WRITE)
+ return DMA_TO_DEVICE;
+ else
+ return DMA_FROM_DEVICE;
+}
+
+static int sunxi_mmc_prepare_dma(struct sunxi_mmc_host *smc_host,
+ struct mmc_data *data)
+{
+ u32 dma_len;
+ u32 i;
+ u32 temp;
+ struct scatterlist *sg;
+
+ dma_len = dma_map_sg(mmc_dev(smc_host->mmc), data->sg, data->sg_len,
+ sunxi_mmc_get_dma_dir(data));
+ if (dma_len == 0) {
+ dev_err(mmc_dev(smc_host->mmc), "dma_map_sg failed\n");
+ return -ENOMEM;
+ }
+
+ for_each_sg(data->sg, sg, data->sg_len, i) {
+ if (sg->offset & 3 || sg->length & 3) {
+ dev_err(mmc_dev(smc_host->mmc),
+ "unaligned scatterlist: os %x length %d\n",
+ sg->offset, sg->length);
+ return -EINVAL;
+ }
+ }
+
+ sunxi_mmc_init_idma_des(smc_host, data);
+
+ temp = mci_readl(smc_host, REG_GCTRL);
+ temp |= SDXC_DMA_ENABLE_BIT;
+ mci_writel(smc_host, REG_GCTRL, temp);
+ temp |= SDXC_DMA_RESET;
+ mci_writel(smc_host, REG_GCTRL, temp);
+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
+
+ if (!(data->flags & MMC_DATA_WRITE))
+ mci_writel(smc_host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
+
+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
+
+ return 0;
+}
+
+static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
+ struct mmc_request *req)
+{
+ u32 cmd_val = SDXC_START | SDXC_RESPONSE_EXPIRE | SDXC_STOP_ABORT_CMD
+ | SDXC_CHECK_RESPONSE_CRC | MMC_STOP_TRANSMISSION;
+ u32 ri = 0;
+ unsigned long expire = jiffies + msecs_to_jiffies(1000);
+
+ mci_writel(host, REG_CARG, 0);
+ mci_writel(host, REG_CMDR, cmd_val);
+
+ do {
+ ri = mci_readl(host, REG_RINTR);
+ } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
+ time_before(jiffies, expire));
+
+ if (ri & SDXC_INTERRUPT_ERROR_BIT) {
+ dev_err(mmc_dev(host->mmc), "send stop command failed\n");
+ if (req->stop)
+ req->stop->resp[0] = -ETIMEDOUT;
+ } else {
+ if (req->stop)
+ req->stop->resp[0] = mci_readl(host, REG_RESP0);
+ }
+
+ mci_writel(host, REG_RINTR, 0xffff);
+}
+
+static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *smc_host)
+{
+ struct mmc_command *cmd = smc_host->mrq->cmd;
+ struct mmc_data *data = smc_host->mrq->data;
+
+ /* For some cmds timeout is normal with sd/mmc cards */
+ if ((smc_host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == SDXC_RESPONSE_TIMEOUT &&
+ (cmd->opcode == SD_IO_SEND_OP_COND || cmd->opcode == SD_IO_RW_DIRECT))
+ return;
+
+ dev_err(mmc_dev(smc_host->mmc),
+ "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
+ smc_host->mmc->index, cmd->opcode,
+ data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
+ smc_host->int_sum & SDXC_RESPONSE_ERROR ? " RE" : "",
+ smc_host->int_sum & SDXC_RESPONSE_CRC_ERROR ? " RCE" : "",
+ smc_host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
+ smc_host->int_sum & SDXC_RESPONSE_TIMEOUT ? " RTO" : "",
+ smc_host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
+ smc_host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
+ smc_host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
+ smc_host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
+ smc_host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
+ );
+}
+
+static void sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
+{
+ struct mmc_request *mrq;
+ unsigned long iflags;
+
+ spin_lock_irqsave(&host->lock, iflags);
+
+ mrq = host->mrq;
+ if (!mrq) {
+ spin_unlock_irqrestore(&host->lock, iflags);
+ dev_err(mmc_dev(host->mmc), "no request to finalize\n");
+ return;
+ }
+
+ if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
+ sunxi_mmc_dump_errinfo(host);
+ mrq->cmd->error = -ETIMEDOUT;
+ if (mrq->data)
+ mrq->data->error = -ETIMEDOUT;
+ if (mrq->stop)
+ mrq->stop->error = -ETIMEDOUT;
+ } else {
+ if (mrq->cmd->flags & MMC_RSP_136) {
+ mrq->cmd->resp[0] = mci_readl(host, REG_RESP3);
+ mrq->cmd->resp[1] = mci_readl(host, REG_RESP2);
+ mrq->cmd->resp[2] = mci_readl(host, REG_RESP1);
+ mrq->cmd->resp[3] = mci_readl(host, REG_RESP0);
+ } else {
+ mrq->cmd->resp[0] = mci_readl(host, REG_RESP0);
+ }
+ if (mrq->data)
+ mrq->data->bytes_xfered =
+ mrq->data->blocks * mrq->data->blksz;
+ }
+
+ if (mrq->data) {
+ struct mmc_data *data = mrq->data;
+ u32 temp;
+
+ mci_writel(host, REG_IDST, 0x337);
+ mci_writel(host, REG_DMAC, 0);
+ temp = mci_readl(host, REG_GCTRL);
+ mci_writel(host, REG_GCTRL, temp|SDXC_DMA_RESET);
+ temp &= ~SDXC_DMA_ENABLE_BIT;
+ mci_writel(host, REG_GCTRL, temp);
+ temp |= SDXC_FIFO_RESET;
+ mci_writel(host, REG_GCTRL, temp);
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+ sunxi_mmc_get_dma_dir(data));
+ }
+
+ mci_writel(host, REG_RINTR, 0xffff);
+
+ dev_dbg(mmc_dev(host->mmc), "req done, resp %08x %08x %08x %08x\n",
+ mrq->cmd->resp[0], mrq->cmd->resp[1],
+ mrq->cmd->resp[2], mrq->cmd->resp[3]);
+
+ host->mrq = NULL;
+ host->int_sum = 0;
+ host->wait_dma = 0;
+
+ spin_unlock_irqrestore(&host->lock, iflags);
+
+ if (mrq->data && mrq->data->error) {
+ dev_err(mmc_dev(host->mmc),
+ "data error, sending stop command\n");
+ sunxi_mmc_send_manual_stop(host, mrq);
+ }
+
+ mmc_request_done(host->mmc, mrq);
+}
+
+static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
+{
+ struct sunxi_mmc_host *host = dev_id;
+ u32 finalize = 0;
+ u32 sdio_int = 0;
+ u32 msk_int;
+ u32 idma_int;
+
+ spin_lock(&host->lock);
+
+ idma_int = mci_readl(host, REG_IDST);
+ msk_int = mci_readl(host, REG_MISTA);
+
+ dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
+ host->mrq, msk_int, idma_int);
+
+ if (host->mrq) {
+ if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
+ host->wait_dma = 0;
+
+ host->int_sum |= msk_int;
+
+ /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finishing the req */
+ if ((host->int_sum & SDXC_RESPONSE_TIMEOUT) &&
+ !(host->int_sum & SDXC_COMMAND_DONE))
+ mci_writel(host, REG_IMASK,
+ host->sdio_imask | SDXC_COMMAND_DONE);
+ else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
+ finalize = 1; /* Don't wait for dma on error */
+ else if (host->int_sum & SDXC_INTERRUPT_DONE_BIT && !host->wait_dma)
+ finalize = 1; /* Done */
+
+ if (finalize) {
+ mci_writel(host, REG_IMASK, host->sdio_imask);
+ mci_writel(host, REG_IDIE, 0);
+ }
+ }
+
+ if (msk_int & SDXC_SDIO_INTERRUPT)
+ sdio_int = 1;
+
+ mci_writel(host, REG_RINTR, msk_int);
+ mci_writel(host, REG_IDST, idma_int);
+
+ spin_unlock(&host->lock);
+
+ if (finalize)
+ tasklet_schedule(&host->tasklet);
+
+ if (sdio_int)
+ mmc_signal_sdio_irq(host->mmc);
+
+ return IRQ_HANDLED;
+}
+
+static void sunxi_mmc_tasklet(unsigned long data)
+{
+ struct sunxi_mmc_host *smc_host = (struct sunxi_mmc_host *) data;
+ sunxi_mmc_finalize_request(smc_host);
+}
+
+static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
+{
+ unsigned long expire = jiffies + msecs_to_jiffies(2000);
+ u32 rval;
+
+ rval = mci_readl(host, REG_CLKCR);
+ rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
+
+ if (oclk_en)
+ rval |= SDXC_CARD_CLOCK_ON;
+
+ if (!host->io_flag)
+ rval |= SDXC_LOW_POWER_ON;
+
+ mci_writel(host, REG_CLKCR, rval);
+
+ rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
+ if (host->voltage_switching)
+ rval |= SDXC_VOLTAGE_SWITCH;
+ mci_writel(host, REG_CMDR, rval);
+
+ do {
+ rval = mci_readl(host, REG_CMDR);
+ } while (time_before(jiffies, expire) && (rval & SDXC_START));
+
+ if (rval & SDXC_START) {
+ dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
+ host->ferror = 1;
+ }
+}
+
+static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *smc_host,
+ u32 oclk_dly, u32 sclk_dly)
+{
+ unsigned long iflags;
+ struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
+
+ spin_lock_irqsave(&smc_host->lock, iflags);
+ clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
+ spin_unlock_irqrestore(&smc_host->lock, iflags);
+}
+
+struct sunxi_mmc_clk_dly mmc_clk_dly[MMC_CLK_MOD_NUM] = {
+ { MMC_CLK_400K, 0, 7 },
+ { MMC_CLK_25M, 0, 5 },
+ { MMC_CLK_50M, 3, 5 },
+ { MMC_CLK_50MDDR, 2, 4 },
+ { MMC_CLK_50MDDR_8BIT, 2, 4 },
+ { MMC_CLK_100M, 1, 4 },
+ { MMC_CLK_200M, 1, 4 },
+};
+
+static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
+ unsigned int rate)
+{
+ u32 newrate;
+ u32 src_clk;
+ u32 oclk_dly;
+ u32 sclk_dly;
+ u32 temp;
+ struct sunxi_mmc_clk_dly *dly = NULL;
+
+ newrate = clk_round_rate(smc_host->clk_mod, rate);
+ if (smc_host->clk_mod_rate == newrate) {
+ dev_dbg(mmc_dev(smc_host->mmc), "clk already %d, rounded %d\n",
+ rate, newrate);
+ return;
+ }
+
+ dev_dbg(mmc_dev(smc_host->mmc), "setting clk to %d, rounded %d\n",
+ rate, newrate);
+
+ /* setting clock rate */
+ clk_disable(smc_host->clk_mod);
+ clk_set_rate(smc_host->clk_mod, newrate);
+ clk_enable(smc_host->clk_mod);
+ smc_host->clk_mod_rate = newrate = clk_get_rate(smc_host->clk_mod);
+ dev_dbg(mmc_dev(smc_host->mmc), "clk is now %d\n", newrate);
+
+ sunxi_mmc_oclk_onoff(smc_host, 0);
+ /* clear internal divider */
+ temp = mci_readl(smc_host, REG_CLKCR);
+ temp &= ~0xff;
+ mci_writel(smc_host, REG_CLKCR, temp);
+
+ /* determine delays */
+ if (rate <= 400000) {
+ dly = &mmc_clk_dly[MMC_CLK_400K];
+ } else if (rate <= 25000000) {
+ dly = &mmc_clk_dly[MMC_CLK_25M];
+ } else if (rate <= 50000000) {
+ if (smc_host->ddr) {
+ if (smc_host->bus_width == 8)
+ dly = &mmc_clk_dly[MMC_CLK_50MDDR_8BIT];
+ else
+ dly = &mmc_clk_dly[MMC_CLK_50MDDR];
+ } else {
+ dly = &mmc_clk_dly[MMC_CLK_50M];
+ }
+ } else if (rate <= 104000000) {
+ dly = &mmc_clk_dly[MMC_CLK_100M];
+ } else if (rate <= 208000000) {
+ dly = &mmc_clk_dly[MMC_CLK_200M];
+ } else {
+ dly = &mmc_clk_dly[MMC_CLK_50M];
+ }
+
+ oclk_dly = dly->oclk_dly;
+ sclk_dly = dly->sclk_dly;
+
+ src_clk = clk_get_rate(clk_get_parent(smc_host->clk_mod));
+
+ if (src_clk >= 300000000 && src_clk <= 400000000) {
+ if (oclk_dly)
+ oclk_dly--;
+ if (sclk_dly)
+ sclk_dly--;
+ }
+
+ sunxi_mmc_set_clk_dly(smc_host, oclk_dly, sclk_dly);
+ sunxi_mmc_oclk_onoff(smc_host, 1);
+
+ /* oclk_onoff sets various irq status bits, clear these */
+ mci_writel(smc_host, REG_RINTR,
+ mci_readl(smc_host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
+}
+
+static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct sunxi_mmc_host *host = mmc_priv(mmc);
+ u32 temp;
+ s32 err;
+
+ /* Set the power state */
+ switch (ios->power_mode) {
+ case MMC_POWER_ON:
+ break;
+
+ case MMC_POWER_UP:
+ if (!IS_ERR(host->vmmc)) {
+ mmc_regulator_set_ocr(host->mmc, host->vmmc, ios->vdd);
+ udelay(200);
+ }
+
+ err = sunxi_mmc_init_host(mmc);
+ if (err) {
+ host->ferror = 1;
+ return;
+ }
+ enable_irq(host->irq);
+
+ dev_dbg(mmc_dev(host->mmc), "power on!\n");
+ host->ferror = 0;
+ break;
+
+ case MMC_POWER_OFF:
+ dev_dbg(mmc_dev(host->mmc), "power off!\n");
+ disable_irq(host->irq);
+ sunxi_mmc_exit_host(host);
+ if (!IS_ERR(host->vmmc))
+ mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
+ host->ferror = 0;
+ break;
+ }
+
+ /* set bus width */
+ switch (ios->bus_width) {
+ case MMC_BUS_WIDTH_1:
+ mci_writel(host, REG_WIDTH, SDXC_WIDTH1);
+ host->bus_width = 1;
+ break;
+ case MMC_BUS_WIDTH_4:
+ mci_writel(host, REG_WIDTH, SDXC_WIDTH4);
+ host->bus_width = 4;
+ break;
+ case MMC_BUS_WIDTH_8:
+ mci_writel(host, REG_WIDTH, SDXC_WIDTH8);
+ host->bus_width = 8;
+ break;
+ }
+
+ /* set ddr mode */
+ temp = mci_readl(host, REG_GCTRL);
+ if (ios->timing == MMC_TIMING_UHS_DDR50) {
+ temp |= SDXC_DDR_MODE;
+ host->ddr = 1;
+ } else {
+ temp &= ~SDXC_DDR_MODE;
+ host->ddr = 0;
+ }
+ mci_writel(host, REG_GCTRL, temp);
+
+ /* set up clock */
+ if (ios->clock && ios->power_mode) {
+ dev_dbg(mmc_dev(host->mmc), "ios->clock: %d\n", ios->clock);
+ sunxi_mmc_clk_set_rate(host, ios->clock);
+ usleep_range(50000, 55000);
+ }
+}
+
+static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
+ unsigned long flags;
+ u32 imask;
+
+ spin_lock_irqsave(&smc_host->lock, flags);
+ imask = mci_readl(smc_host, REG_IMASK);
+ if (enable) {
+ smc_host->sdio_imask = SDXC_SDIO_INTERRUPT;
+ imask |= SDXC_SDIO_INTERRUPT;
+ } else {
+ smc_host->sdio_imask = 0;
+ imask &= ~SDXC_SDIO_INTERRUPT;
+ }
+ mci_writel(smc_host, REG_IMASK, imask);
+ spin_unlock_irqrestore(&smc_host->lock, flags);
+}
+
+static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
+{
+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
+ mci_writel(smc_host, REG_HWRST, 0);
+ udelay(10);
+ mci_writel(smc_host, REG_HWRST, 1);
+ udelay(300);
+}
+
+static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct sunxi_mmc_host *host = mmc_priv(mmc);
+ struct mmc_command *cmd = mrq->cmd;
+ struct mmc_data *data = mrq->data;
+ unsigned long iflags;
+ u32 imask = SDXC_INTERRUPT_ERROR_BIT;
+ u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
+ u32 byte_cnt = 0;
+ int ret;
+
+ if (!mmc_gpio_get_cd(mmc) || host->ferror) {
+ dev_dbg(mmc_dev(host->mmc), "no medium present\n");
+ mrq->cmd->error = -ENOMEDIUM;
+ mmc_request_done(mmc, mrq);
+ return;
+ }
+
+ if (data) {
+ byte_cnt = data->blksz * data->blocks;
+ mci_writel(host, REG_BLKSZ, data->blksz);
+ mci_writel(host, REG_BCNTR, byte_cnt);
+ ret = sunxi_mmc_prepare_dma(host, data);
+ if (ret < 0) {
+ dev_err(mmc_dev(host->mmc), "prepare DMA failed\n");
+ cmd->error = ret;
+ cmd->data->error = ret;
+ mmc_request_done(host->mmc, mrq);
+ return;
+ }
+ }
+
+ if (cmd->opcode == MMC_GO_IDLE_STATE) {
+ cmd_val |= SDXC_SEND_INIT_SEQUENCE;
+ imask |= SDXC_COMMAND_DONE;
+ }
+
+ if (cmd->opcode == SD_SWITCH_VOLTAGE) {
+ cmd_val |= SDXC_VOLTAGE_SWITCH;
+ imask |= SDXC_VOLTAGE_CHANGE_DONE;
+ host->voltage_switching = 1;
+ sunxi_mmc_oclk_onoff(host, 1);
+ }
+
+ if (cmd->flags & MMC_RSP_PRESENT) {
+ cmd_val |= SDXC_RESPONSE_EXPIRE;
+ if (cmd->flags & MMC_RSP_136)
+ cmd_val |= SDXC_LONG_RESPONSE;
+ if (cmd->flags & MMC_RSP_CRC)
+ cmd_val |= SDXC_CHECK_RESPONSE_CRC;
+
+ if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
+ cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
+ if (cmd->data->flags & MMC_DATA_STREAM) {
+ imask |= SDXC_AUTO_COMMAND_DONE;
+ cmd_val |= SDXC_SEQUENCE_MODE | SDXC_SEND_AUTO_STOP;
+ }
+ if (cmd->data->stop) {
+ imask |= SDXC_AUTO_COMMAND_DONE;
+ cmd_val |= SDXC_SEND_AUTO_STOP;
+ } else
+ imask |= SDXC_DATA_OVER;
+
+ if (cmd->data->flags & MMC_DATA_WRITE)
+ cmd_val |= SDXC_WRITE;
+ else
+ host->wait_dma = 1;
+ } else
+ imask |= SDXC_COMMAND_DONE;
+ } else
+ imask |= SDXC_COMMAND_DONE;
+
+ dev_dbg(mmc_dev(host->mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
+ cmd_val & 0x3f, cmd_val, cmd->arg, imask,
+ mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
+
+ spin_lock_irqsave(&host->lock, iflags);
+ host->mrq = mrq;
+ mci_writel(host, REG_IMASK, host->sdio_imask | imask);
+ spin_unlock_irqrestore(&host->lock, iflags);
+
+ mci_writel(host, REG_CARG, cmd->arg);
+ mci_writel(host, REG_CMDR, cmd_val);
+}
+
+static const struct of_device_id sunxi_mmc_of_match[] = {
+ { .compatible = "allwinner,sun4i-a10-mmc", },
+ { .compatible = "allwinner,sun5i-a13-mmc", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
+
+static struct mmc_host_ops sunxi_mmc_ops = {
+ .request = sunxi_mmc_request,
+ .set_ios = sunxi_mmc_set_ios,
+ .get_ro = mmc_gpio_get_ro,
+ .get_cd = mmc_gpio_get_cd,
+ .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
+ .hw_reset = sunxi_mmc_hw_reset,
+};
+
+static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
+ struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ int ret;
+
+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc"))
+ host->idma_des_size_bits = 13;
+ else
+ host->idma_des_size_bits = 16;
+
+ host->vmmc = devm_regulator_get_optional(&pdev->dev, "vmmc");
+ if (IS_ERR(host->vmmc) && PTR_ERR(host->vmmc) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ host->reg_base = devm_ioremap_resource(&pdev->dev,
+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
+ if (IS_ERR(host->reg_base))
+ return PTR_ERR(host->reg_base);
+
+ host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
+ if (IS_ERR(host->clk_ahb)) {
+ dev_err(&pdev->dev, "Could not get ahb clock\n");
+ return PTR_ERR(host->clk_ahb);
+ }
+
+ host->clk_mod = devm_clk_get(&pdev->dev, "mod");
+ if (IS_ERR(host->clk_mod)) {
+ dev_err(&pdev->dev, "Could not get mod clock\n");
+ return PTR_ERR(host->clk_mod);
+ }
+
+ /* Make sure the controller is in a sane state before enabling irqs */
+ ret = sunxi_mmc_init_host(host->mmc);
+ if (ret)
+ return ret;
+
+ host->irq = platform_get_irq(pdev, 0);
+ ret = devm_request_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 0,
+ "sunxi-mci", host);
+ if (ret == 0)
+ disable_irq(host->irq);
+
+ /* And put it back in reset */
+ sunxi_mmc_exit_host(host);
+
+ return ret;
+}
+
+static int sunxi_mmc_probe(struct platform_device *pdev)
+{
+ struct sunxi_mmc_host *host;
+ struct mmc_host *mmc;
+ int ret;
+
+ mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
+ if (!mmc) {
+ dev_err(&pdev->dev, "mmc alloc host failed\n");
+ return -ENOMEM;
+ }
+
+ ret = mmc_of_parse(mmc);
+ if (ret)
+ goto error_free_host;
+
+ host = mmc_priv(mmc);
+ host->mmc = mmc;
+ spin_lock_init(&host->lock);
+ tasklet_init(&host->tasklet, sunxi_mmc_tasklet, (unsigned long)host);
+
+ ret = sunxi_mmc_resource_request(host, pdev);
+ if (ret)
+ goto error_free_host;
+
+ host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
+ &host->sg_dma, GFP_KERNEL);
+ if (!host->sg_cpu) {
+ dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
+ ret = -ENOMEM;
+ goto error_free_host;
+ }
+
+ mmc->ops = &sunxi_mmc_ops;
+ mmc->max_blk_count = 8192;
+ mmc->max_blk_size = 4096;
+ mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
+ mmc->max_seg_size = (1 << host->idma_des_size_bits);
+ mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
+ /* 400kHz ~ 50MHz */
+ mmc->f_min = 400000;
+ mmc->f_max = 50000000;
+ /* available voltages */
+ if (!IS_ERR(host->vmmc))
+ mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vmmc);
+ else
+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+ MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
+ MMC_CAP_UHS_DDR50 | MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL |
+ MMC_CAP_DRIVER_TYPE_A;
+
+ if (host->bus_width == 4)
+ mmc->caps |= MMC_CAP_4_BIT_DATA;
+
+ mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP;
+
+ ret = mmc_add_host(mmc);
+
+ if (ret)
+ goto error_free_dma;
+
+ dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
+ platform_set_drvdata(pdev, mmc);
+ return 0;
+
+error_free_dma:
+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+error_free_host:
+ mmc_free_host(mmc);
+ return ret;
+}
+
+static int sunxi_mmc_remove(struct platform_device *pdev)
+{
+ struct mmc_host *mmc = platform_get_drvdata(pdev);
+ struct sunxi_mmc_host *host = mmc_priv(mmc);
+
+ mmc_remove_host(mmc);
+ sunxi_mmc_exit_host(host);
+ tasklet_disable(&host->tasklet);
+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+ mmc_free_host(mmc);
+
+ return 0;
+}
+
+static struct platform_driver sunxi_mmc_driver = {
+ .driver = {
+ .name = "sunxi-mci",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(sunxi_mmc_of_match),
+ },
+ .probe = sunxi_mmc_probe,
+ .remove = sunxi_mmc_remove,
+};
+module_platform_driver(sunxi_mmc_driver);
+
+MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("David Lanzend?rfer <david.lanzendoerfer@o2s.ch>");
+MODULE_ALIAS("platform:sunxi-mmc");
diff --git a/drivers/mmc/host/sunxi-mmc.h b/drivers/mmc/host/sunxi-mmc.h
new file mode 100644
index 0000000..cbd6d49
--- /dev/null
+++ b/drivers/mmc/host/sunxi-mmc.h
@@ -0,0 +1,239 @@
+/*
+ * Driver for sunxi SD/MMC host controllers
+ * (C) Copyright 2014-2015 Reuuimlla Technology Co., Ltd.
+ * (C) Copyright 2014-2015 Aaron Maoye <leafy.myeh@reuuimllatech.com>
+ * (C) Copyright 2014-2015 O2S GmbH <www.o2s.ch>
+ * (C) Copyright 2014-2015 David Lanzend?rfer <david.lanzendoerfer@o2s.ch>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __SUNXI_MCI_H__
+#define __SUNXI_MCI_H__
+
+/* register offset define */
+#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
+#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
+#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
+#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
+#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
+#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
+#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
+#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
+#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
+#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
+#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
+#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
+#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
+#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
+#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
+#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
+#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
+#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
+#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
+#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
+#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
+#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
+#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
+#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
+#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
+#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
+#define SDXC_REG_CHDA (0x90)
+#define SDXC_REG_CBDA (0x94)
+
+#define mci_readl(host, reg) \
+ readl((host)->reg_base + SDXC_##reg)
+#define mci_writel(host, reg, value) \
+ writel((value), (host)->reg_base + SDXC_##reg)
+
+/* global control register bits */
+#define SDXC_SOFT_RESET BIT(0)
+#define SDXC_FIFO_RESET BIT(1)
+#define SDXC_DMA_RESET BIT(2)
+#define SDXC_HARDWARE_RESET (SDXC_SOFT_RESET|SDXC_FIFO_RESET|SDXC_DMA_RESET)
+#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
+#define SDXC_DMA_ENABLE_BIT BIT(5)
+#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
+#define SDXC_POSEDGE_LATCH_DATA BIT(9)
+#define SDXC_DDR_MODE BIT(10)
+#define SDXC_MEMORY_ACCESS_DONE BIT(29)
+#define SDXC_ACCESS_DONE_DIRECT BIT(30)
+#define SDXC_ACCESS_BY_AHB BIT(31)
+#define SDXC_ACCESS_BY_DMA (0U << 31)
+/* clock control bits */
+#define SDXC_CARD_CLOCK_ON BIT(16)
+#define SDXC_LOW_POWER_ON BIT(17)
+/* bus width */
+#define SDXC_WIDTH1 (0)
+#define SDXC_WIDTH4 (1)
+#define SDXC_WIDTH8 (2)
+/* smc command bits */
+#define SDXC_RESPONSE_EXPIRE BIT(6)
+#define SDXC_LONG_RESPONSE BIT(7)
+#define SDXC_CHECK_RESPONSE_CRC BIT(8)
+#define SDXC_DATA_EXPIRE BIT(9)
+#define SDXC_WRITE BIT(10)
+#define SDXC_SEQUENCE_MODE BIT(11)
+#define SDXC_SEND_AUTO_STOP BIT(12)
+#define SDXC_WAIT_PRE_OVER BIT(13)
+#define SDXC_STOP_ABORT_CMD BIT(14)
+#define SDXC_SEND_INIT_SEQUENCE BIT(15)
+#define SDXC_UPCLK_ONLY BIT(21)
+#define SDXC_READ_CEATA_DEV BIT(22)
+#define SDXC_CCS_EXPIRE BIT(23)
+#define SDXC_ENABLE_BIT_BOOT BIT(24)
+#define SDXC_ALT_BOOT_OPTIONS BIT(25)
+#define SDXC_BOOT_ACK_EXPIRE BIT(26)
+#define SDXC_BOOT_ABORT BIT(27)
+#define SDXC_VOLTAGE_SWITCH BIT(28)
+#define SDXC_USE_HOLD_REGISTER BIT(29)
+#define SDXC_START BIT(31)
+/* interrupt bits */
+#define SDXC_RESPONSE_ERROR BIT(1)
+#define SDXC_COMMAND_DONE BIT(2)
+#define SDXC_DATA_OVER BIT(3)
+#define SDXC_TX_DATA_REQUEST BIT(4)
+#define SDXC_RX_DATA_REQUEST BIT(5)
+#define SDXC_RESPONSE_CRC_ERROR BIT(6)
+#define SDXC_DATA_CRC_ERROR BIT(7)
+#define SDXC_RESPONSE_TIMEOUT BIT(8)
+#define SDXC_DATA_TIMEOUT BIT(9)
+#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
+#define SDXC_FIFO_RUN_ERROR BIT(11)
+#define SDXC_HARD_WARE_LOCKED BIT(12)
+#define SDXC_START_BIT_ERROR BIT(13)
+#define SDXC_AUTO_COMMAND_DONE BIT(14)
+#define SDXC_END_BIT_ERROR BIT(15)
+#define SDXC_SDIO_INTERRUPT BIT(16)
+#define SDXC_CARD_INSERT BIT(30)
+#define SDXC_CARD_REMOVE BIT(31)
+#define SDXC_INTERRUPT_ERROR_BIT (SDXC_RESPONSE_ERROR | SDXC_RESPONSE_CRC_ERROR | \
+ SDXC_DATA_CRC_ERROR | SDXC_RESPONSE_TIMEOUT | \
+ SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
+ SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | \
+ SDXC_END_BIT_ERROR) /* 0xbbc2 */
+#define SDXC_INTERRUPT_DONE_BIT (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
+ SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
+/* status */
+#define SDXC_RXWL_FLAG BIT(0)
+#define SDXC_TXWL_FLAG BIT(1)
+#define SDXC_FIFO_EMPTY BIT(2)
+#define SDXC_FIFO_FULL BIT(3)
+#define SDXC_CARD_PRESENT BIT(8)
+#define SDXC_CARD_DATA_BUSY BIT(9)
+#define SDXC_DATA_FSM_BUSY BIT(10)
+#define SDXC_DMA_REQUEST BIT(31)
+#define SDXC_FIFO_SIZE (16)
+/* Function select */
+#define SDXC_CEATA_ON (0xceaaU << 16)
+#define SDXC_SEND_IRQ_RESPONSE BIT(0)
+#define SDXC_SDIO_READ_WAIT BIT(1)
+#define SDXC_ABORT_READ_DATA BIT(2)
+#define SDXC_SEND_CCSD BIT(8)
+#define SDXC_SEND_AUTO_STOPCCSD BIT(9)
+#define SDXC_CEATA_DEV_INTERRUPT_ENABLE_BIT BIT(10)
+/* IDMA controller bus mod bit field */
+#define SDXC_IDMAC_SOFT_RESET BIT(0)
+#define SDXC_IDMAC_FIX_BURST BIT(1)
+#define SDXC_IDMAC_IDMA_ON BIT(7)
+#define SDXC_IDMAC_REFETCH_DES BIT(31)
+/* IDMA status bit field */
+#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
+#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
+#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
+#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
+#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
+#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
+#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
+#define SDXC_IDMAC_HOST_ABORT_INTERRUPT_TX BIT(10)
+#define SDXC_IDMAC_HOST_ABORT_INTERRUPT_RX BIT(10)
+#define SDXC_IDMAC_IDLE (0U << 13)
+#define SDXC_IDMAC_SUSPEND (1U << 13)
+#define SDXC_IDMAC_DESC_READ (2U << 13)
+#define SDXC_IDMAC_DESC_CHECK (3U << 13)
+#define SDXC_IDMAC_READ_REQUEST_WAIT (4U << 13)
+#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5U << 13)
+#define SDXC_IDMAC_READ (6U << 13)
+#define SDXC_IDMAC_WRITE (7U << 13)
+#define SDXC_IDMAC_DESC_CLOSE (8U << 13)
+
+/*
+* If the idma-des-size-bits of property is ie 13, bufsize bits are:
+* Bits 0-12: buf1 size
+* Bits 13-25: buf2 size
+* Bits 26-31: not used
+* Since we only ever set buf1 size, we can simply store it directly.
+*/
+#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
+#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
+#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
+#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
+#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
+#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
+#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
+
+struct sunxi_idma_des {
+ u32 config;
+ u32 buf_size;
+ u32 buf_addr_ptr1;
+ u32 buf_addr_ptr2;
+};
+
+struct sunxi_mmc_host {
+ struct mmc_host *mmc;
+ struct regulator *vmmc;
+
+ /* IO mapping base */
+ void __iomem *reg_base;
+
+ spinlock_t lock;
+ struct tasklet_struct tasklet;
+
+ /* clock management */
+ struct clk *clk_ahb;
+ struct clk *clk_mod;
+
+ /* ios information */
+ u32 clk_mod_rate;
+ u32 bus_width;
+ u32 idma_des_size_bits;
+ u32 ddr;
+ u32 voltage_switching;
+
+ /* irq */
+ int irq;
+ u32 int_sum;
+ u32 sdio_imask;
+
+ /* flags */
+ u32 power_on:1;
+ u32 io_flag:1;
+ u32 wait_dma:1;
+
+ dma_addr_t sg_dma;
+ void *sg_cpu;
+
+ struct mmc_request *mrq;
+ u32 ferror;
+};
+
+#define MMC_CLK_400K 0
+#define MMC_CLK_25M 1
+#define MMC_CLK_50M 2
+#define MMC_CLK_50MDDR 3
+#define MMC_CLK_50MDDR_8BIT 4
+#define MMC_CLK_100M 5
+#define MMC_CLK_200M 6
+#define MMC_CLK_MOD_NUM 7
+
+struct sunxi_mmc_clk_dly {
+ u32 mode;
+ u32 oclk_dly;
+ u32 sclk_dly;
+};
+
+#endif
^ permalink raw reply related
* [PATCH v5 3/8] ARM: sunxi: clk: export clk_sunxi_mmc_phase_control
From: David Lanzendörfer @ 2014-02-11 19:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140211190543.4568.83517.stgit@dizzy-6.o2s.ch>
From: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
include/linux/clk/sunxi.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 include/linux/clk/sunxi.h
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
new file mode 100644
index 0000000..1ef5c89
--- /dev/null
+++ b/include/linux/clk/sunxi.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_SUNXI_H_
+#define __LINUX_CLK_SUNXI_H_
+
+#include <linux/clk.h>
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output);
+
+#endif
^ permalink raw reply related
* [PATCH v5 2/8] clk: sunxi: Implement MMC phase control
From: David Lanzendörfer @ 2014-02-11 19:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140211190543.4568.83517.stgit@dizzy-6.o2s.ch>
From: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abb6c5a..33b9977 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -377,6 +377,41 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
/**
+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
+ */
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
+{
+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
+
+ struct clk_composite *composite = to_clk_composite(hw);
+ struct clk_hw *rate_hw = composite->rate_hw;
+ struct clk_factors *factors = to_clk_factors(rate_hw);
+ unsigned long flags = 0;
+ u32 reg;
+
+ if (factors->lock)
+ spin_lock_irqsave(factors->lock, flags);
+
+ reg = readl(factors->reg);
+
+ /* set sample clock phase control */
+ reg &= ~(0x7 << 20);
+ reg |= ((sample & 0x7) << 20);
+
+ /* set output clock phase control */
+ reg &= ~(0x7 << 8);
+ reg |= ((output & 0x7) << 8);
+
+ writel(reg, factors->reg);
+
+ if (factors->lock)
+ spin_unlock_irqrestore(factors->lock, flags);
+}
+
+
+/**
* sunxi_factors_clk_setup() - Setup function for factor clocks
*/
^ permalink raw reply related
* [PATCH v5 1/8] clk: sunxi: factors: automatic reparenting support
From: David Lanzendörfer @ 2014-02-11 19:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140211190543.4568.83517.stgit@dizzy-6.o2s.ch>
From: Emilio L?pez <emilio@elopez.com.ar>
This commit implements .determine_rate, so that our factor clocks can be
reparented when needed.
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
---
drivers/clk/sunxi/clk-factors.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 9e23264..3806d97 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -77,6 +77,41 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
return rate;
}
+static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate,
+ struct clk **best_parent_p)
+{
+ struct clk *clk = hw->clk, *parent, *best_parent = NULL;
+ int i, num_parents;
+ unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
+
+ /* find the parent that can help provide the fastest rate <= rate */
+ num_parents = __clk_get_num_parents(clk);
+ for (i = 0; i < num_parents; i++) {
+ parent = clk_get_parent_by_index(clk, i);
+ if (!parent)
+ continue;
+ if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
+ parent_rate = __clk_round_rate(parent, rate);
+ else
+ parent_rate = __clk_get_rate(parent);
+
+ child_rate = clk_factors_round_rate(hw, rate, &parent_rate);
+
+ if (child_rate <= rate && child_rate > best_child_rate) {
+ best_parent = parent;
+ best = parent_rate;
+ best_child_rate = child_rate;
+ }
+ }
+
+ if (best_parent)
+ *best_parent_p = best_parent;
+ *best_parent_rate = best;
+
+ return best_child_rate;
+}
+
static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -113,6 +148,7 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
}
const struct clk_ops clk_factors_ops = {
+ .determine_rate = clk_factors_determine_rate,
.recalc_rate = clk_factors_recalc_rate,
.round_rate = clk_factors_round_rate,
.set_rate = clk_factors_set_rate,
^ permalink raw reply related
* Toggling gpio pins while powering down
From: Jasbir Matharu @ 2014-02-11 19:33 UTC (permalink / raw)
To: linux-arm-kernel
I'm trying to determine the correct way of toggling gpio pins when the
soc is powering down to enter low power mode. My current crude
implementation is perform these within a pm_power_off function however
this is currently done within the board file by checking for a
compatible board type (ugly). The alternative would be create a driver
and implement the pm_power_off function within. However given there
could many drivers implementing a pm_power_off functions there's no
guarantee mine will be called? Another requirement is that the gpio
need to be set in the correct order.
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts
index 0ce92cd..e5e2af9 100644
--- a/arch/arm/boot/dts/imx6q-udoo.dts
+++ b/arch/arm/boot/dts/imx6q-udoo.dts
@@ -62,6 +62,13 @@
compatible = "fsl,mxc_v4l2_output";
status = "okay";
};
+
+ poweroff {
+ compatible = "udoo,poweroff";
+ sam3x_rst_gpio = <&gpio1 0 0>;
+ pwr_5v_gpio = <&gpio2 4 0>;
+ };
+
};
&hdmi_audio {
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index f24c231..3fea3fd 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -34,6 +34,7 @@
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of_net.h>
+#include <linux/delay.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
@@ -336,6 +337,55 @@ static const struct of_dev_auxdata
imx6q_auxdata_lookup[] __initconst = {
{ /* sentinel */ }
};
+#define SNVS_LPCR 0x04
+static void imx6q_poweroff(void)
+{
+ struct device_node *snvs_np, *pwr_off_np;
+ void __iomem *mx6_snvs_base;
+ u32 value;
+ int sam3x_rst_gpio,pwr_5v_gpio;
+
+ snvs_np = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0-mon-rtc-lp");
+ if (!snvs_np) {
+ pr_warn("failed to find sec-v4.0-mon-rtc-lp node\n");
+ return;
+ }
+
+ mx6_snvs_base = of_iomap(snvs_np, 0);
+ if (!mx6_snvs_base) {
+ pr_warn("failed to map sec-v4.0-mon-rtc-lp\n");
+ goto put_snvs_node;
+ }
+
+ value = readl(mx6_snvs_base + SNVS_LPCR);
+ /*set TOP and DP_EN bit*/
+ writel(value | 0x60, mx6_snvs_base + SNVS_LPCR);
+
+ if (of_machine_is_compatible("udoo,imx6q-udoo")) {
+ // Power down SAM3X and UDOO
+ pwr_off_np = of_find_compatible_node(NULL, NULL, "udoo,poweroff");
+ if (!pwr_off_np) {
+ pr_warn("failed to find udoo,poweroff node\n");
+ goto put_snvs_node;
+ }
+
+ sam3x_rst_gpio = of_get_named_gpio(pwr_off_np, "sam3x_rst_gpio", 0);
+ pwr_5v_gpio = of_get_named_gpio(pwr_off_np, "pwr_5v_gpio", 0);
+ if (gpio_is_valid(sam3x_rst_gpio) && gpio_is_valid(pwr_5v_gpio)) {
+ gpio_request_one(sam3x_rst_gpio, GPIOF_OUT_INIT_LOW,"sam3x_rst_gpio"),
+ msleep(5);
+ gpio_request_one(pwr_5v_gpio, GPIOF_OUT_INIT_HIGH,"pwr_5v_gpio");
+ } else {
+ pr_warn("failed to find sam3x_rst_gpio or pwr_5v_gpio property\n");
+ }
+
+ }
+
+ of_node_put(pwr_off_np);
+put_snvs_node:
+ of_node_put(snvs_np);
+}
+
static void __init imx6q_init_machine(void)
{
struct device *parent;
@@ -353,6 +403,8 @@ static void __init imx6q_init_machine(void)
imx6_pm_init();
imx6q_csi_mux_init();
imx6q_lvds_cabc_init();
+
+ pm_power_off = imx6q_poweroff;
}
^ permalink raw reply related
* [PATCH v5 0/8] ARM: sunxi: Add driver for SD/MMC hosts found on allwinner sunxi SOCs
From: David Lanzendörfer @ 2014-02-11 19:33 UTC (permalink / raw)
To: linux-arm-kernel
Hello
The following patchset adds support for the SD/MMC host found in the Allwinner SoCs.
It contains all the necessary modifications for clock environment and also the device
tree script modification which add it to all the boards using it.
The clock environment function needed for phase offset configuration has
been proposed and implemented by Emilio.
A lot of work and cleanup has been done by Hans de Goede. Special thanks to him!
This patchset is the 4th attempt to send this driver upstream.
Changes since v1:
-Using mmc_of_parse instead of diy dt parsing
-Adding nodes for all mmc controller to the dtsi files,
including sofar unused controllers
-Using generic GPIO slot library for WP/CD
-Adding additional MMC device nodes into DTSI files
Changes since v2:
-Add missing Signed-off-by tags
-Stop using __raw_readl / __raw_writel so that barriers are properly used
-Adding missing new lines
-Adding missing patch for automatic reparenting of clocks
Changes since v3:
-Move clk_enable / disable into host_init / exit (Hans)
-Fix hang on boot caused by irq storm (Hans)
Changes since v4:
-moving sunxi-mci.{c/h} to sunxi-mmc.{c/h}
-removing camel cases from the defines in sunxi-mmc.h
-moving defines out of the struct definition
since this is bad coding style
-adding documentation for the device tree binding
---
David Lanzend?rfer (5):
ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
ARM: dts: sun7i: Add support for mmc
ARM: dts: sun4i: Add support for mmc
ARM: dts: sun5i: Add support for mmc
ARM: sunxi: Add documentation for driver for SD/MMC hosts found on Allwinner sunxi SoCs
Emilio L?pez (2):
clk: sunxi: factors: automatic reparenting support
clk: sunxi: Implement MMC phase control
Hans de Goede (1):
ARM: sunxi: clk: export clk_sunxi_mmc_phase_control
.../devicetree/bindings/mmc/sunxi-mmc.txt | 32 +
arch/arm/boot/dts/sun4i-a10-a1000.dts | 8
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 8
arch/arm/boot/dts/sun4i-a10.dtsi | 54 +
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 30 +
arch/arm/boot/dts/sun5i-a10s.dtsi | 44 +
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 15
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 15
arch/arm/boot/dts/sun5i-a13.dtsi | 37 +
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 8
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 8
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +
arch/arm/boot/dts/sun7i-a20.dtsi | 61 +
drivers/clk/sunxi/clk-factors.c | 36 +
drivers/clk/sunxi/clk-sunxi.c | 35 +
drivers/mmc/host/Kconfig | 7
drivers/mmc/host/Makefile | 2
drivers/mmc/host/sunxi-mmc.c | 872 ++++++++++++++++++++
drivers/mmc/host/sunxi-mmc.h | 239 +++++
include/linux/clk/sunxi.h | 22 +
20 files changed, 1556 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
create mode 100644 drivers/mmc/host/sunxi-mmc.c
create mode 100644 drivers/mmc/host/sunxi-mmc.h
create mode 100644 include/linux/clk/sunxi.h
--
Signature
^ permalink raw reply
* [PATCH 4/8] ARM: mvebu: make use of of_find_matching_node_and_match
From: Jason Cooper @ 2014-02-11 19:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392135847-30791-5-git-send-email-joshc@codeaurora.org>
On Tue, Feb 11, 2014 at 10:24:02AM -0600, Josh Cartwright wrote:
> Instead of the of_find_matching_node()/of_match_node() pair, which requires two
> iterations through the match table, make use of of_find_matching_node_and_match(),
> which only iterates through the table once.
>
> While we're here, mark the of_system_controller table const.
>
> Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
> ---
> arch/arm/mach-mvebu/system-controller.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
Applied to mvebu/soc with Thomas' Reviewed-by, and Gregory's Ack.
thx,
Jason.
^ permalink raw reply
* [PATCH 00/12] Versatile Express updates
From: Arnd Bergmann @ 2014-02-11 19:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392138636-29240-1-git-send-email-pawel.moll@arm.com>
On Tuesday 11 February 2014 17:10:24 Pawel Moll wrote:
> This series is a set of updates following the infrastructure
> rework and depends on it. It will be finally posted once
> the main series is merged. For the time being I would really
> appreciate feedback and/or (n)acks...
>
I haven't read the patches yet, but on a general level, do
you think this code can be (or should) be shared with
mach-versatile and mach-realview?
One of the things on my (mid-term) to-do list is to completely
convert those two platforms over to being entirely DT based
and having no board specific code so we can actually delete
the directories along with mach-vexpress. The sysreg part
seems to be almost identical, and I wonder if you have an
overview of what the difference is, if any.
If we are going to share that code, we might want to give it
a different name, as vexpress is just the latest platform
in that line.
Arnd
^ permalink raw reply
* [PATCH 2/8] bus: mvebu-mbus: make use of of_find_matching_node_and_match
From: Jason Cooper @ 2014-02-11 19:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392135847-30791-3-git-send-email-joshc@codeaurora.org>
On Tue, Feb 11, 2014 at 10:24:00AM -0600, Josh Cartwright wrote:
> Instead of the of_find_matching_node()/of_match_node() pair, which requires two
> iterations through the match table, make use of of_find_matching_node_and_match(),
> which only iterates through the table once.
>
> Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
> ---
> drivers/bus/mvebu-mbus.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
Applied to mvebu/drivers
thx,
Jason.
^ permalink raw reply
* [PATCH 2/3] PCI: ARM: add support for virtual PCI host controller
From: Arnd Bergmann @ 2014-02-11 19:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140209203412.GN26684@n2100.arm.linux.org.uk>
On Sunday 09 February 2014, Russell King - ARM Linux wrote:
> On Sun, Feb 09, 2014 at 09:18:19PM +0100, Arnd Bergmann wrote:
> > On Thursday 06 February 2014, Russell King - ARM Linux wrote:
> >
> > > So, whenever you enumerate a PCI bus, and read the resource information
> > > out of the BARs, you must know how that address region specified in
> > > the BAR as a bus address maps to the host address space.
> > >
> >
> > None of that contradicts what I wrote. Please try to understand what
> > I suggested, which is to have a common way to communicate that
> > information from DT to the PCI core without involving the PCI host
> > bridge driver.
>
> Please explain it better then.
>
Let me try again: Looking at the dw_pcie driver (since that is one of
the few that gets it mostly right), we have quite a bit of generic
code in dw_pcie_host_init() and in dw_pcie_setup(). All the DT parsing
in there just implements the generic PCI DT binding, and what the
setup function does depends exclusively on what comes out of the
parser.
If we manage to move all the common parts into a generic helper
function that gets called by the setup() on arm32, we no longer
need to worry about host drivers implementing an incorrect DT
parser or getting the io_offset calculation wrong, because they
don't actually see any of that, plus we save a lot of duplicate
code.
How it fits together with the new arm64 pci support is a different
question, but if it's just a helper function, it should really work
on any architecture.
Arnd
^ permalink raw reply
* [PATCH] ARM: mvebu: rename mvebu_defconfig to mvebu_v7_defconfig
From: Jason Cooper @ 2014-02-11 19:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392056399-20908-1-git-send-email-thomas.petazzoni@free-electrons.com>
On Mon, Feb 10, 2014 at 07:19:59PM +0100, Thomas Petazzoni wrote:
> With the merge of the Kirkwood support into arch/arm/mach-mvebu/, the
> mvebu platform will no longer only contain ARMv7 compatible processors
> (Armada 370, Armada XP, and soon Armada 375, Armada 38x and Dove), but
> also ARMv5 compatible processors (Kirkwood, and hopefully Orion5x in
> the future).
>
> However, a single mvebu_defconfig cannot work, since it is not
> possible to build a kernel that supports both ARMv5 and ARMv7
> platforms in the same binary. As a consequence, this commit renames
> mvebu_defconfig to mvebu_v7_defconfig, which is the configuration that
> will build a kernel that supports all ARMv7 mvebu platforms. As
> Kirkwood support gets merged into mach-mvebu, an additional
> mvebu_v5_defconfig will be added.
>
> Even though we already have a multi_v7_defconfig, the mvebu developers
> found it more convenient for development to have a defconfig that
> builds only the mvebu platforms.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
> arch/arm/configs/{mvebu_defconfig => mvebu_v7_defconfig} | 0
> 1 file changed, 0 insertions(+), 0 deletions(-)
> rename arch/arm/configs/{mvebu_defconfig => mvebu_v7_defconfig} (100%)
>
> diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_v7_defconfig
> similarity index 100%
> rename from arch/arm/configs/mvebu_defconfig
> rename to arch/arm/configs/mvebu_v7_defconfig
Applied to mvebu/defconfig with Andrew's Ack.
thx,
Jason.
^ permalink raw reply
* [PATCH 6/6] dt: Update binding information for mvebu gating clocks with Armada 380/385
From: Jason Cooper @ 2014-02-11 19:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140210185908.3374eaf6@skate>
On Mon, Feb 10, 2014 at 06:59:08PM +0100, Thomas Petazzoni wrote:
> Dear Andrew Lunn,
>
> On Mon, 10 Feb 2014 18:53:50 +0100, Andrew Lunn wrote:
> > > +The following is a list of provided IDs for Armada 380/385:
> > > +ID Clock Peripheral
> > > +-----------------------------------
> > > +0 audio Audio
> > > +2 ge2 Gigabit Ethernet 2
> > > +3 ge1 Gigabit Ethernet 1
> > > +4 ge0 Gigabit Ethernet 0
> > > +5 pex1 PCIe 1
> > > +6 pex2 PCIe 2
> > > +7 pex3 PCIe 3
> > > +8 pex4 PCIe 0
> >
> > Is that last one a typo? It at least looks a bit odd.
>
> Right, this should be:
>
> 8 pex0 PCIe 0
>
> (just checked again in the datasheet)
I can fix this up when I pull it in for Mike. No need to redo the
series just for this.
I'll let it sit for a day or two more before I pull it to give everyone
a chance to look it over.
thx,
Jason.
>
> Thomas
> --
> Thomas Petazzoni, CTO, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 0/2] Marvell Armada 375 and 38x pinctrl drivers
From: Jason Cooper @ 2014-02-11 19:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392051896-19178-1-git-send-email-thomas.petazzoni@free-electrons.com>
On Mon, Feb 10, 2014 at 06:04:54PM +0100, Thomas Petazzoni wrote:
> Linus,
>
> Here are two patches that add the pinctrl drivers for two new Marvell
> ARM SOCs that belong to the mach-mvebu family: the Armada 375 and the
> Armada 380/385. They are based on Cortex-A9 CPU cores, and share a
> number of peripherals with their predecessors in the mach-mvebu
> family. pinctrl-wise, they have a completely similar register layout
> than Armada 370/XP, so only a list of pins and functions has to be
> introduced, and therefore the drivers are straightforward.
>
> The core support (arch/arm/mach-mvebu) for these SOCs will be posted
> shortly, and we're aiming at having this merged for 3.15 if possible.
>
> Thanks!
>
> Thomas
>
> Thomas Petazzoni (2):
> pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375
> pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385
>
> .../pinctrl/marvell,armada-375-pinctrl.txt | 81 ++++
> .../pinctrl/marvell,armada-38x-pinctrl.txt | 79 ++++
> drivers/pinctrl/mvebu/Kconfig | 8 +
> drivers/pinctrl/mvebu/Makefile | 2 +
> drivers/pinctrl/mvebu/pinctrl-armada-375.c | 441 ++++++++++++++++++++
> drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 445 +++++++++++++++++++++
> 6 files changed, 1056 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt
> create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-375.c
> create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-38x.c
For the whole series,
Acked-by: Jason Cooper <jason@lakedaemon.net>
thx,
Jason.
^ permalink raw reply
* [PATCH v2 1/5] drivers: of: add initialization code for reserved memory
From: Grant Likely @ 2014-02-11 19:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FA33E2.4050004@samsung.com>
On Tue, 11 Feb 2014 15:29:54 +0100, Tomasz Figa <t.figa@samsung.com> wrote:
> > Yes, if only because it is an define usage of the reg property. If a
> > devtree has multiple tuples in reg, then all of those tuples should be
> > treated as reserved, even if the kernel doesn't know how to use them.
> >
> > I would not do the same for size/align/alloc-ranges unless there is a
> > very specific use case that you can define. These ones are different
> > from the static regions because they aren't ever used to protect
> > something that already exists in the memory.
>
> Is there a reason why multiple regions could not be used for this
> purpose, instead of adding extra complexity of having multiple reg
> entries per region?
>
> I.e. I don't see a difference between
>
> reg1: region at 00000000 {
> reg = <0x00000000 0x1000>;
> };
>
> reg2: region at 10000000 {
> reg = <0x10000000 0x1000>;
> };
>
> user {
> regions = <®1>, <®2>;
> };
>
> and
>
> reg: region at 00000000 {
> reg = <0x00000000 0x1000>, <0x10000000 0x1000>;
> };
>
> user {
> regions = <®>;
> };
>
> except that the former IMHO better suits the definition of memory
> region, which I see as a single contiguous range of memory and can be
> simplified to have a single reg entry per region.
My point is rather if multiple reg tuples are found in a reserved memory
node, the kernel must respect them and reserve the memory. I'm not
arguing about whether or not that makes for a good binding.
g.
^ permalink raw reply
* [PATCH] ARM: dts: omap3-n9 family: mark proper OMAP version
From: Aaro Koskinen @ 2014-02-11 18:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392132541-25340-1-git-send-email-nm@ti.com>
Hi,
On Tue, Feb 11, 2014 at 09:29:01AM -0600, Nishanth Menon wrote:
> Nokia N900 uses OMAP3430 and N9/N950 uses OMAP3630. Mark SoC compatibilty
> as per Documentation/devicetree/bindings/arm/omap/omap.txt else
> N9/N950 will be probed as a OMAP3430 type device, since default ti,omap3
> maps to OMAP3430 compatibility.
I already sent & tested patches for this:
http://marc.info/?l=linux-omap&m=139194800711362&w=2
http://marc.info/?l=linux-omap&m=139194800011360&w=2
The N9/N950 is mandatory for 3.14, as the boot hangs without it.
A.
> Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>
> just build tested. but given examples such as
> http://thread.gmane.org/gmane.linux.ports.arm.omap/110006
>
> I guess, some form of failure is expected.
>
> based on v3.14-rc2
>
> arch/arm/boot/dts/omap3-n9.dts | 2 +-
> arch/arm/boot/dts/omap3-n900.dts | 2 +-
> arch/arm/boot/dts/omap3-n950.dts | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
> index 39828ce..9938b5d 100644
> --- a/arch/arm/boot/dts/omap3-n9.dts
> +++ b/arch/arm/boot/dts/omap3-n9.dts
> @@ -14,5 +14,5 @@
>
> / {
> model = "Nokia N9";
> - compatible = "nokia,omap3-n9", "ti,omap3";
> + compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3";
> };
> diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
> index 6fc85f9..97db027 100644
> --- a/arch/arm/boot/dts/omap3-n900.dts
> +++ b/arch/arm/boot/dts/omap3-n900.dts
> @@ -13,7 +13,7 @@
>
> / {
> model = "Nokia N900";
> - compatible = "nokia,omap3-n900", "ti,omap3";
> + compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
>
> cpus {
> cpu at 0 {
> diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts
> index b076a52..261c558 100644
> --- a/arch/arm/boot/dts/omap3-n950.dts
> +++ b/arch/arm/boot/dts/omap3-n950.dts
> @@ -14,5 +14,5 @@
>
> / {
> model = "Nokia N950";
> - compatible = "nokia,omap3-n950", "ti,omap3";
> + compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3";
> };
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] ARM: dts: imx27-phytec-phycard-s-som: Rename file to .dtsi
From: Alexander Shiyan @ 2014-02-11 18:44 UTC (permalink / raw)
To: linux-arm-kernel
PCA-100 module cannot be used standalone. This patch renames
module file to .dtsi and excludes it from compilation.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
arch/arm/boot/dts/Makefile | 1 -
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 2 +-
.../{imx27-phytec-phycard-s-som.dts => imx27-phytec-phycard-s-som.dtsi} | 0
3 files changed, 1 insertion(+), 2 deletions(-)
rename arch/arm/boot/dts/{imx27-phytec-phycard-s-som.dts => imx27-phytec-phycard-s-som.dtsi} (100%)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 222fe15..48ee3ab 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -144,7 +144,6 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx27-apf27dev.dtb \
imx27-pdk.dtb \
imx27-phytec-phycore-rdk.dtb \
- imx27-phytec-phycard-s-som.dtb \
imx27-phytec-phycard-s-rdk.dtb \
imx31-bug.dtb \
imx35-eukrea-mbimxsd35-baseboard.dtb \
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
index 1cd3a87..3c3964a 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -9,7 +9,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include "imx27-phytec-phycard-s-som.dts"
+#include "imx27-phytec-phycard-s-som.dtsi"
/ {
model = "Phytec pca100 rapid development kit";
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
similarity index 100%
rename from arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
rename to arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
--
1.8.3.2
^ permalink raw reply related
* [PATCH 3/8] ARM: at91: make use of of_find_matching_node_and_match
From: Josh Cartwright @ 2014-02-11 18:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FA61F4.90905@atmel.com>
On Tue, Feb 11, 2014 at 06:46:28PM +0100, Nicolas Ferre wrote:
> On 11/02/2014 17:24, Josh Cartwright :
> > Instead of the of_find_matching_node()/of_match_node() pair, which requires two
> > iterations through the match table, make use of of_find_matching_node_and_match(),
> > which only iterates through the table once.
> >
> > While we're here, mark the rtsc id table const.
>
> Well, I might remove this one, just because other id tables are not
> marked as "const" in the same file... So it can be good to change all of
> them in a raw.
Indeed, I was only looking for a specific pattern.
[..]
> => if you want, I can take the patch with me through arm-soc with at91
> material for 3.15 and complete your "const" modification. What do you
> think about that?
Yes, this sounds good.
Thanks,
Josh
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* [BUG] Circular locking dependency - DRM/CMA/MM/hotplug/...
From: Russell King - ARM Linux @ 2014-02-11 18:35 UTC (permalink / raw)
To: linux-arm-kernel
The cubox-i4 just hit a new lockdep problem - not quite sure what to
make of this - it looks like an interaction between quite a lot of
locks - I suspect more than the lockdep code is reporting in its
"Possible unsafe locking scenario" report.
I'm hoping I've sent this to appropriate people... if anyone thinks
this needs to go to someone else, please forward it. Thanks.
======================================================
[ INFO: possible circular locking dependency detected ]
3.14.0-rc2+ #517 Tainted: G W
-------------------------------------------------------
Xorg/805 is trying to acquire lock:
(cma_mutex){+.+.+.}, at: [<c03716f4>] dma_release_from_contiguous+0xb8/0xf8
but task is already holding lock:
(&dev->struct_mutex){+.+...}, at: [<c03512ec>] drm_gem_object_handle_unreference_unlocked+0xdc/0x148
which lock already depends on the new lock.
the existing dependency chain (in reverse order) is:
-> #5 (&dev->struct_mutex){+.+...}:
[<c0066f04>] __lock_acquire+0x151c/0x1ca0
[<c0067c28>] lock_acquire+0xa0/0x130
[<c0698180>] mutex_lock_nested+0x5c/0x3ac
[<c0350c30>] drm_gem_mmap+0x40/0xdc
[<c03671d8>] drm_gem_cma_mmap+0x14/0x2c
[<c00ef4f4>] mmap_region+0x3ac/0x59c
[<c00ef9ac>] do_mmap_pgoff+0x2c8/0x370
[<c00dd730>] vm_mmap_pgoff+0x6c/0x9c
[<c00ee1fc>] SyS_mmap_pgoff+0x54/0x98
[<c000e6e0>] ret_fast_syscall+0x0/0x48
-> #4 (&mm->mmap_sem){++++++}:
[<c0066f04>] __lock_acquire+0x151c/0x1ca0
[<c0067c28>] lock_acquire+0xa0/0x130
[<c00e6c5c>] might_fault+0x6c/0x94
[<c0335440>] con_set_unimap+0x158/0x27c
[<c032f800>] vt_ioctl+0x1298/0x1388
[<c0323f44>] tty_ioctl+0x168/0xbf4
[<c0115fac>] do_vfs_ioctl+0x84/0x664
[<c01165d0>] SyS_ioctl+0x44/0x64
[<c000e6e0>] ret_fast_syscall+0x0/0x48
-> #3 (console_lock){+.+.+.}:
[<c0066f04>] __lock_acquire+0x151c/0x1ca0
[<c0067c28>] lock_acquire+0xa0/0x130
[<c006edcc>] console_lock+0x60/0x74
[<c006f7b8>] console_cpu_notify+0x28/0x34
[<c004904c>] notifier_call_chain+0x4c/0x8c
[<c004916c>] __raw_notifier_call_chain+0x1c/0x24
[<c0024124>] __cpu_notify+0x34/0x50
[<c002424c>] cpu_notify_nofail+0x18/0x24
[<c068e168>] _cpu_down+0x100/0x244
[<c068e2dc>] cpu_down+0x30/0x44
[<c036ef8c>] cpu_subsys_offline+0x14/0x18
[<c036af28>] device_offline+0x94/0xbc
[<c036b030>] online_store+0x4c/0x74
[<c0368d3c>] dev_attr_store+0x20/0x2c
[<c016b2e0>] sysfs_kf_write+0x54/0x58
[<c016eaa4>] kernfs_fop_write+0xc4/0x160
[<c0105a54>] vfs_write+0xbc/0x184
[<c0105dfc>] SyS_write+0x48/0x70
[<c000e6e0>] ret_fast_syscall+0x0/0x48
-> #2 (cpu_hotplug.lock){+.+.+.}:
[<c0066f04>] __lock_acquire+0x151c/0x1ca0
[<c0067c28>] lock_acquire+0xa0/0x130
[<c0698180>] mutex_lock_nested+0x5c/0x3ac
[<c0024218>] get_online_cpus+0x3c/0x58
[<c00d0ab0>] lru_add_drain_all+0x24/0x190
[<c0101d3c>] migrate_prep+0x10/0x18
[<c00cba04>] alloc_contig_range+0xf4/0x30c
[<c0371588>] dma_alloc_from_contiguous+0x7c/0x130
[<c0018ef8>] __alloc_from_contiguous+0x38/0x12c
[<c0908694>] atomic_pool_init+0x74/0x128
[<c0008850>] do_one_initcall+0x3c/0x164
[<c0903c98>] kernel_init_freeable+0x104/0x1d0
[<c068de54>] kernel_init+0x10/0xec
[<c000e7a8>] ret_from_fork+0x14/0x2c
-> #1 (lock){+.+...}:
[<c0066f04>] __lock_acquire+0x151c/0x1ca0
[<c0067c28>] lock_acquire+0xa0/0x130
[<c0698180>] mutex_lock_nested+0x5c/0x3ac
[<c00d0aa8>] lru_add_drain_all+0x1c/0x190
[<c0101d3c>] migrate_prep+0x10/0x18
[<c00cba04>] alloc_contig_range+0xf4/0x30c
[<c0371588>] dma_alloc_from_contiguous+0x7c/0x130
[<c0018ef8>] __alloc_from_contiguous+0x38/0x12c
[<c0908694>] atomic_pool_init+0x74/0x128
[<c0008850>] do_one_initcall+0x3c/0x164
[<c0903c98>] kernel_init_freeable+0x104/0x1d0
[<c068de54>] kernel_init+0x10/0xec
[<c000e7a8>] ret_from_fork+0x14/0x2c
-> #0 (cma_mutex){+.+.+.}:
[<c0690850>] print_circular_bug+0x70/0x2f0
[<c0066f68>] __lock_acquire+0x1580/0x1ca0
[<c0067c28>] lock_acquire+0xa0/0x130
[<c0698180>] mutex_lock_nested+0x5c/0x3ac
[<c03716f4>] dma_release_from_contiguous+0xb8/0xf8
[<c00197a4>] __arm_dma_free.isra.11+0x194/0x218
[<c0019868>] arm_dma_free+0x1c/0x24
[<c0366e34>] drm_gem_cma_free_object+0x68/0xb8
[<c0351194>] drm_gem_object_free+0x30/0x38
[<c0351318>] drm_gem_object_handle_unreference_unlocked+0x108/0x148
[<c0351498>] drm_gem_handle_delete+0xb0/0x10c
[<c0351508>] drm_gem_dumb_destroy+0x14/0x18
[<c035e838>] drm_mode_destroy_dumb_ioctl+0x34/0x40
[<c034f918>] drm_ioctl+0x3f4/0x498
[<c0115fac>] do_vfs_ioctl+0x84/0x664
[<c01165d0>] SyS_ioctl+0x44/0x64
[<c000e6e0>] ret_fast_syscall+0x0/0x48
other info that might help us debug this:
Chain exists of: cma_mutex --> &mm->mmap_sem --> &dev->struct_mutex
Possible unsafe locking scenario:
CPU0 CPU1
---- ----
lock(&dev->struct_mutex);
lock(&mm->mmap_sem);
lock(&dev->struct_mutex);
lock(cma_mutex);
*** DEADLOCK ***
1 lock held by Xorg/805:
#0: (&dev->struct_mutex){+.+...}, at: [<c03512ec>] drm_gem_object_handle_unreference_unlocked+0xdc/0x148
stack backtrace:
CPU: 0 PID: 805 Comm: Xorg Tainted: G W 3.14.0-rc2+ #517
Backtrace:
[<c00124e0>] (dump_backtrace) from [<c0012680>] (show_stack+0x18/0x1c)
r6:c0a869f0 r5:c0a8d540 r4:00000000 r3:00000000
[<c0012668>] (show_stack) from [<c0693310>] (dump_stack+0x70/0x8c)
[<c06932a0>] (dump_stack) from [<c0690a7c>] (print_circular_bug+0x29c/0x2f0)
r4:c0a79570 r3:e9338980
[<c06907e0>] (print_circular_bug) from [<c0066f68>] (__lock_acquire+0x1580/0x1ca0)
r10:c0a6da70 r8:e9338dc8 r7:c10ed83c r6:00000001 r5:e9338db0 r4:e9338980
[<c00659e8>] (__lock_acquire) from [<c0067c28>] (lock_acquire+0xa0/0x130)
r10:00000000 r9:00000002 r8:00000000 r7:00000000 r6:c099e3b0 r5:e8ca2000
r4:00000000
[<c0067b88>] (lock_acquire) from [<c0698180>] (mutex_lock_nested+0x5c/0x3ac)
r10:e9338980 r9:ea16d010 r8:e8ca2000 r7:00000000 r6:c0ebe304 r5:c03716f4
r4:c099e378
[<c0698124>] (mutex_lock_nested) from [<c03716f4>] (dma_release_from_contiguous+0xb8/0xf8)
r10:ebb00000 r9:ea16d010 r8:c0979cc8 r7:0002bb00 r6:000003fc r5:0003bb00
r4:c10f4a78
[<c037163c>] (dma_release_from_contiguous) from [<c00197a4>] (__arm_dma_free.isra.11+0x194/0x218)
r6:003fc000 r5:ea7d8000 r4:ead4e000 r3:c001db4c
[<c0019610>] (__arm_dma_free.isra.11) from [<c0019868>] (arm_dma_free+0x1c/0x24)
r10:e9902e20 r9:e8ca3e38 r8:e989e000 r7:e9902e58 r6:e9902f10 r5:e989e030
r4:e9aad540
[<c001984c>] (arm_dma_free) from [<c0366e34>] (drm_gem_cma_free_object+0x68/0xb8)
[<c0366dcc>] (drm_gem_cma_free_object) from [<c0351194>] (drm_gem_object_free+0x30/0x38)
r4:e9aad540
[<c0351164>] (drm_gem_object_free) from [<c0351318>] (drm_gem_object_handle_unreference_unlocked+0x108/0x148)
[<c0351210>] (drm_gem_object_handle_unreference_unlocked) from [<c0351498>] (drm_gem_handle_delete+0xb0/0x10c)
r5:e9aad540 r4:e9902e00
[<c03513e8>] (drm_gem_handle_delete) from [<c0351508>] (drm_gem_dumb_destroy+0x14/0x18)
r10:c06e3448 r8:e8ca3e38 r7:e8ca2000 r6:e9902e00 r5:000000b4 r4:e8ca3e38
[<c03514f4>] (drm_gem_dumb_destroy) from [<c035e838>] (drm_mode_destroy_dumb_ioctl+0x34/0x40)
[<c035e804>] (drm_mode_destroy_dumb_ioctl) from [<c034f918>] (drm_ioctl+0x3f4/0x498)
r4:e989e000 r3:c035e804
[<c034f524>] (drm_ioctl) from [<c0115fac>] (do_vfs_ioctl+0x84/0x664)
r10:00000000 r9:e8ca2000 r8:beeb6bb4 r7:e9824560 r6:c01165d0 r5:00000006
r4:e9b97300
[<c0115f28>] (do_vfs_ioctl) from [<c01165d0>] (SyS_ioctl+0x44/0x64)
r10:00000000 r9:e8ca2000 r8:00000006 r7:c00464b4 r6:beeb6bb4 r5:e9b97300
r4:00000000
[<c011658c>] (SyS_ioctl) from [<c000e6e0>] (ret_fast_syscall+0x0/0x48)
r8:c000e8a4 r7:00000036 r6:00000006 r5:c00464b4 r4:beeb6bb4
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* Re: [PATCH v2 1/4] tty/serial: Add GPIOLIB helpers for controlling modem lines
From: Alexander Shiyan @ 2014-02-11 18:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392140715-15295-2-git-send-email-richard.genoud@gmail.com>
Hello.
???????, 11 ??????? 2014, 18:45 +01:00 ?? Richard Genoud <richard.genoud@gmail.com>:
> This patch add some helpers to control modem lines (CTS/RTS/DSR...) via
> GPIO.
> This will be useful for many boards which have a serial controller that
> only handle CTS/RTS pins (or even just RX/TX).
>
> Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
> ---
OK, a few comments below.
...
> +config SERIAL_MCTRL_GPIO
> + def_bool y
> + depends on GPIOLIB
I suggest to move GPIOLIB dependency to serial_mctrl_gpio.h header, so
unit can be used with or without GPIOLIB, so Kconfig will look something like this:
config SERIAL_MCTRL_GPIO
tristate
Then, you can select this option for particular UART:
config SERIAL_ATMEL
...
select SERIAL_MCTRL_GPIO
...
> +++ b/drivers/tty/serial/serial_mctrl_gpio.c
...
> +static const char *mctrl_gpio_of_names[UART_GPIO_MAX] = {
> + "cts", "dsr", "dcd", "ri", "rts", "dtr"
> +};
Make a combined array. This will use cycles for set/get operations.
static struct {
const char *name;
unsigned int mctrl;
} mctrl_gpios[] = {
{ "cts", TIOCM_CTS, },
...
};
...
> +int mctrl_gpio_init(struct device *dev, struct mctrl_gpios *gpios)
> +{
I'm not sure whether to make a non-DT support at all ...
> + enum mctrl_gpio_idx i;
> + int err = 0;
> + int ret = 0;
> +
> + for (i = UART_GPIO_MIN; i < UART_GPIO_MAX; i++) {
> + gpios->gpio[i] = gpiod_get(dev, mctrl_gpio_of_names[i]);
What a reason to using gpiod_xxx() ?
Why we cannot use standart devm_gpio_request/get/set etc. ?
In addition, I recommend create this patch as separate,
because it will most likely still be comments later.
Thanks.
---
^ permalink raw reply
* [PATCH] ARM: mm: report both sections from PMD
From: Kees Cook @ 2014-02-11 18:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140211111751.GD3748@arm.com>
On Tue, Feb 11, 2014 at 3:17 AM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
> On Mon, Feb 10, 2014 at 05:26:28PM +0000, Kees Cook wrote:
>> On Mon, Feb 10, 2014 at 2:41 AM, Catalin Marinas
>> <catalin.marinas@arm.com> wrote:
>> > On Mon, Feb 10, 2014 at 10:29:35AM +0000, Catalin Marinas wrote:
>> >> On Sun, Feb 09, 2014 at 10:18:26PM +0000, Kees Cook wrote:
>> >> > diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
>> >> > index 1f7b1e13d945..ff1559f9200c 100644
>> >> > --- a/arch/arm/mm/dump.c
>> >> > +++ b/arch/arm/mm/dump.c
>> >> > @@ -264,6 +264,9 @@ static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start)
>> >> > note_page(st, addr, 3, pmd_val(*pmd));
>> >> > else
>> >> > walk_pte(st, pmd, addr);
>> >> > +
>> >> > + if (SECTION_SIZE < PMD_SIZE && pmd_sect(*pmd))
>> >> > + note_page(st, addr + SECTION_SIZE, 3, pmd_val(pmd[1]));
>> >>
>> >> You can use pmd_large() here as well.
>> >>
>> >> But I think this function is broken (the "for" statement not shown
>> >> here). The pmd_t is 32-bit with classic MMU and it uses pmd++ while the
>> >> address grows by PMD_SIZE (two pmd_t entries).
>> >
>> > Actually it's ok since PTRS_PER_PMD is 1, so it only goes through this
>> > loop once.
>> >
>> > But in your patch shouldn't you check for pmd_large(*(pmd+1))? The first
>> > pmd is already caught by the 'if' statement.
>>
>> It wasn't clear to me what the logic should be here. If PTRS_PER_PMD
>> is 1, then why is there this second pmd after the first? Shouldn't
>> PTRS_PER_PMD be 2 if that's the case?
>
> The reason is that a hardware pte has only 256 entries (classic MMU),
> this is 1KB. We put two pte tables together and it gives us 2KB. The
> other 2KB in the page are used for Linux pte bits. Because we have two
> hw pte tables in a page, we need two corresponding pmd entries.
>
> A side effect is that even though we don't actually have a pmd (normally
> we should have included pgtable-nopmd.h), we still pretend we have one
> and __pmd_populate takes care of writing two consecutive entries. If we
> set PTRS_PER_PMD to 2, we should modify pte_alloc_one() to allocate a
> single hw pte (1KB + 1KB for software bits). I don't think this would be
> more efficient (there may have been other kernel restrictions in the
> past to require a full pte table page).
>
>> If that's not the case, then I figured the state of needing to report
>> the 2nd pmd depended on the type of the first one, so that's what I
>> wrote instead of trying to figure out why PTRS_PER_PMD wasn't 2.
>
> I don't remember whether we can have the first pmd being a table and the
> second one being a section. I don't think we restrict this but Russell
> should know more.
It sounds like my logic is still okay, then? Perhaps move it into the
first "if" for readability?
if (pmd_none(*pmd) || pmd_large(*pmd) || !pmd_present(*pmd)) {
note_page(st, addr, 3, pmd_val(*pmd));
if (SECTION_SIZE < PMD_SIZE && pmd_sect(*pmd))
note_page(st, addr + SECTION_SIZE, 3,
pmd_val(pmd[1]));
} else
walk_pte(st, pmd, addr);
Or should be be explicitly separated (to allow for the very unlikely
future case of pmd_large != pmd_sect)? In the LPAE case, SECTION_SIZE
== PMD_SIZE, so IIUC, we have to continue testing for that:
if (pmd_sect(*pmd)) {
note_page(st, addr, 3, pmd_val(*pmd));
if (SECTION_SIZE < PMD_SIZE)
note_page(st, addr + SECTION_SIZE, 3,
pmd_val(pmd[1]));
} else if (pmd_none(*pmd) || pmd_large(*pmd) ||
!pmd_present(*pmd))
note_page(st, addr, 3, pmd_val(*pmd));
else
walk_pte(st, pmd, addr);
>> There's clearly something I'm not understanding in here. :)
>
> I happen to understand it from time to time but it doesn't last ;).
Heh, understood. Thanks for looking at this. :)
-Kees
--
Kees Cook
Chrome OS Security
^ permalink raw reply
* [PATCH 1/3] arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
From: Mark Rutland @ 2014-02-11 18:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392100183-30930-2-git-send-email-kgene.kim@samsung.com>
On Tue, Feb 11, 2014 at 06:29:41AM +0000, Kukjin Kim wrote:
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> ---
> arch/arm64/boot/dts/samsung-gh7.dtsi | 108 ++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/samsung-ssdk-gh7.dts | 26 +++++++
> 2 files changed, 134 insertions(+)
> create mode 100644 arch/arm64/boot/dts/samsung-gh7.dtsi
> create mode 100644 arch/arm64/boot/dts/samsung-ssdk-gh7.dts
>
> diff --git a/arch/arm64/boot/dts/samsung-gh7.dtsi b/arch/arm64/boot/dts/samsung-gh7.dtsi
> new file mode 100644
> index 0000000..5b8785c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/samsung-gh7.dtsi
> @@ -0,0 +1,108 @@
> +/*
> + * SAMSUNG GH7 SoC device tree source
> + *
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +
> +/memreserve/ 0x80000000 0x0C400000;
That looks _very_ large. What is this for?
[...]
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <1 13 0xff01>, /* Secure Phys IRQ */
> + <1 14 0xff01>, /* Non-secure Phys IRQ */
> + <1 11 0xff01>, /* Virt IRQ */
> + <1 10 0xff01>; /* Hyp IRQ */
> + clock-frequency = <100000000>;
Please, get your bootloader to set CNTFREQ. The clock frequency property
for the timer node is a horrible hack for buggy firmware.
[...]
> + amba {
> + compatible = "arm,amba-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + serial at 12c00000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x12c00000 0x10000>;
> + interrupts = <418>;
> + };
> +
> + serial at 12c20000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x12c20000 0x10000>;
> + interrupts = <420>;
> + };
Don't these need clocks?
[...]
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x00000000 0x80000000 0 0x80000000>;
Minor nit, but it would be nice for the 0 values to be consistently padded.
Thanks,
Mark.
^ permalink raw reply
* [PATCH v3 3/5] ARM: qcom: Split Qualcomm support into legacy and multiplatform
From: Bryan Huntsman @ 2014-02-11 18:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <392A0D29-65A3-403D-B645-DB74A1897170@codeaurora.org>
On 02/11/2014 07:13 AM, Kumar Gala wrote:
>>> * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
>>> >> + * Copyright (c) 2014 The Linux Foundation. All rights reserved.
>> >
>> > We should replace the Code Aurora Forum copyright with Linux
>> > Foundation here.
> Is this something we?ve been doing? Its normally bad form to make such changes, but I don?t know what the details re when LF took over CAF w/regards to something like Copyright.
>
> - k
Yes, the line should read:
- * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010,2014 The Linux Foundation. All rights reserved.
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
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