* [RFC/PATCH 2/3] arm: Add ARCH_WANT_OF_RANDOMNESS
From: Laura Abbott @ 2014-02-12 1:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392168805-14200-1-git-send-email-lauraa@codeaurora.org>
The stack canary for ARM is currently the same across reboots
due to lack of randomness early enough. Add ARCH_WANT_OF_RANDOMNESS
to allow devices to add whatever randomness they need.
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
---
arch/arm/Kconfig | 3 +++
arch/arm/kernel/vmlinux.lds.S | 1 +
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e254198..7ab0db1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -222,6 +222,9 @@ config NEED_RET_TO_USER
config ARCH_MTD_XIP
bool
+config ARCH_WANT_OF_RANDOMNESS
+ def_bool n
+
config VECTORS_BASE
hex
default 0xffff0000 if MMU || CPU_HIGH_VECTOR
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 7bcee5c..2198258 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -202,6 +202,7 @@ SECTIONS
INIT_SETUP(16)
INIT_CALLS
CON_INITCALL
+ EARLY_RANDOM_FUNCS
SECURITY_INITCALL
INIT_RAM_FS
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related
* [RFC/PATCH 3/3] init: Move stack canary initialization after setup_arch
From: Laura Abbott @ 2014-02-12 1:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392168805-14200-1-git-send-email-lauraa@codeaurora.org>
Stack canary intialization involves getting a random number.
Getting this random number may involve accessing caches or other
architectural specific features which are not available until
after the architecture is setup. Move the stack canary initialization
later to accomodate this.
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
---
init/main.c | 9 ++++-----
1 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/init/main.c b/init/main.c
index eb03090..63d0596 100644
--- a/init/main.c
+++ b/init/main.c
@@ -489,11 +489,6 @@ asmlinkage void __init start_kernel(void)
smp_setup_processor_id();
debug_objects_early_init();
- /*
- * Set up the the initial canary ASAP:
- */
- boot_init_stack_canary();
-
cgroup_init_early();
local_irq_disable();
@@ -507,6 +502,10 @@ asmlinkage void __init start_kernel(void)
page_address_init();
pr_notice("%s", linux_banner);
setup_arch(&command_line);
+ /*
+ * Set up the the initial canary ASAP:
+ */
+ boot_init_stack_canary();
mm_init_owner(&init_mm, &init_task);
mm_init_cpumask(&init_mm);
setup_command_line(command_line);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH] ARM: shmobile: set proper DMA masks for Ether devices
From: Simon Horman @ 2014-02-12 1:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201402120255.25037.sergei.shtylyov@cogentembedded.com>
On Wed, Feb 12, 2014 at 02:55:24AM +0300, Sergei Shtylyov wrote:
> Ether MAC is a DMA-capable device and so should have 'dev.dma_mask' and
> 'dev.coherent_dma_mask' fields set properly, to reflect 32-bit DMA addressing
> ability. Currently, the code works without DMA masks but in the future, when
> support for NETIF_F_HIGHDMA & NETIF_F_SG would be added to the 'sh_eth' driver,
> the DMA masks should start to matter...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Hi Sergei,
please split this series up so there is a separate patch for each board.
Thanks
>
> ---
> The patch is against 'renesas-devel-v3.14-rc1-20140207' tag in Simon Horman's
> 'renesas.git' repo...
>
> arch/arm/mach-shmobile/board-armadillo800eva.c | 2 ++
> arch/arm/mach-shmobile/board-bockw.c | 21 ++++++++++++++-------
> arch/arm/mach-shmobile/board-genmai.c | 19 ++++++++++++++-----
> arch/arm/mach-shmobile/board-koelsch.c | 16 ++++++++++++----
> arch/arm/mach-shmobile/board-lager.c | 19 ++++++++++++++-----
> 5 files changed, 56 insertions(+), 21 deletions(-)
^ permalink raw reply
* [PATCH v2 6/6] ARM: tegra: cpuidle: use firmware for power down
From: Olof Johansson @ 2014-02-12 1:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391747706-1847-7-git-send-email-acourbot@nvidia.com>
On Fri, Feb 07, 2014 at 01:35:06PM +0900, Alexandre Courbot wrote:
> Attempt to invoke the prepare_idle() and do_idle() firmware calls
> to power down a CPU so an underlying firmware gets informed of
> the idle operation and performs it by itself if designed in such a way.
>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
> ---
> arch/arm/mach-tegra/cpuidle-tegra114.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
> index e0b87300243d..558067ddc186 100644
> --- a/arch/arm/mach-tegra/cpuidle-tegra114.c
> +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
> @@ -19,6 +19,7 @@
> #include <linux/cpuidle.h>
> #include <linux/cpu_pm.h>
> #include <linux/clockchips.h>
> +#include <asm/firmware.h>
>
> #include <asm/cpuidle.h>
> #include <asm/suspend.h>
> @@ -45,7 +46,15 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
>
> clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
>
> - cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
> + call_firmware_op(prepare_idle);
> +
> + switch (call_firmware_op(do_idle)) {
> + case -ENOSYS:
> + cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
> + break;
> + default:
> + break;
Do you expect other cases down the road? If not, this is a simple if instead:
/* Only call cpu_suspend if TF didn't handle the pre-suspend logic */
if (call_firmware_op(do_idle) == -ENOSYS)
cpu_suspend(....);
-Olof
^ permalink raw reply
* [PATCH v2 0/6] ARM: firmware: improvements to Trusted Foundations support
From: Olof Johansson @ 2014-02-12 1:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391747706-1847-1-git-send-email-acourbot@nvidia.com>
On Fri, Feb 07, 2014 at 01:35:00PM +0900, Alexandre Courbot wrote:
> These (mostly minor) patches fix a few typos, improve points that
> were agreed upon when the Trusted Foundation series was initially
> submitted, and more importantly add support for a prepare_idle()
> firmware operation that informs the firmware a CPU is doing idle.
> Tegra's cpuidle driver is then also updated accordingly.
>
> These patches should be the last step before device trees for NVIDIA
> SHIELD and Tegra Note 7 can be submitted.
>
> Changes since v1:
> - Do not remove TF support from tegra_defconfig (will automatically be taken
> care of during next configuration update)
> - Add a new prepare_idle() operation to firmware_ops that informs the firmware
> a CPU is going idle (vs. asking the firmware to do it itself as do_idle()
> does)
> - Fix idle states names in TF implementation of prepare_idle to sound less
> Tegra-specific
1-5:
Acked-by: Olof Johansson <olof@lixom.net>
Stephen asked if he should merge through Russell's tree or ours; since
tegra is the only user I don't have a problem merging this (via tegra
pull requests) but I'm giving Russell veto power. :)
-Olof
^ permalink raw reply
* [PATCH v2 6/6] ARM: tegra: cpuidle: use firmware for power down
From: Alexandre Courbot @ 2014-02-12 1:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140212013650.GA7584@quad.lixom.net>
On 02/12/2014 10:36 AM, Olof Johansson wrote:
> On Fri, Feb 07, 2014 at 01:35:06PM +0900, Alexandre Courbot wrote:
>> Attempt to invoke the prepare_idle() and do_idle() firmware calls
>> to power down a CPU so an underlying firmware gets informed of
>> the idle operation and performs it by itself if designed in such a way.
>>
>> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
>> ---
>> arch/arm/mach-tegra/cpuidle-tegra114.c | 11 ++++++++++-
>> 1 file changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
>> index e0b87300243d..558067ddc186 100644
>> --- a/arch/arm/mach-tegra/cpuidle-tegra114.c
>> +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
>> @@ -19,6 +19,7 @@
>> #include <linux/cpuidle.h>
>> #include <linux/cpu_pm.h>
>> #include <linux/clockchips.h>
>> +#include <asm/firmware.h>
>>
>> #include <asm/cpuidle.h>
>> #include <asm/suspend.h>
>> @@ -45,7 +46,15 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
>>
>> clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
>>
>> - cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
>> + call_firmware_op(prepare_idle);
>> +
>> + switch (call_firmware_op(do_idle)) {
>> + case -ENOSYS:
>> + cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
>> + break;
>> + default:
>> + break;
>
> Do you expect other cases down the road? If not, this is a simple if instead:
>
> /* Only call cpu_suspend if TF didn't handle the pre-suspend logic */
> if (call_firmware_op(do_idle) == -ENOSYS)
> cpu_suspend(....);
I might have been overdoing it indeed. Let me submit a v3 just for this
one patch.
Thanks!
Alex.
^ permalink raw reply
* [PATCH v3] ARM: tegra: cpuidle: use firmware for power down
From: Alexandre Courbot @ 2014-02-12 2:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FAD4C2.80803@nvidia.com>
Attempt to invoke the prepare_idle() and do_idle() firmware calls
to power down a CPU so an underlying firmware gets informed of
the idle operation and performs it by itself if designed in such a way.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
This is the only v3 patch in the series.
Changes since v2:
- Use an if statement instead of a switch to handle the single return
code we need to care about.
arch/arm/mach-tegra/cpuidle-tegra114.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index e0b87300243d..b5fb7c110c64 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -19,6 +19,7 @@
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/clockchips.h>
+#include <asm/firmware.h>
#include <asm/cpuidle.h>
#include <asm/suspend.h>
@@ -45,7 +46,11 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
- cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+ call_firmware_op(prepare_idle);
+
+ /* Do suspend by ourselves if the firmware does not implement it */
+ if (call_firmware_op(do_idle) == -ENOSYS)
+ cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
--
1.8.5.4
^ permalink raw reply related
* [PATCH V2] ARM: imx: avoid calling clk APIs in idle thread which may cause schedule
From: Shawn Guo @ 2014-02-12 3:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392107148-27395-1-git-send-email-b20788@freescale.com>
On Tue, Feb 11, 2014 at 04:25:48PM +0800, Anson Huang wrote:
> As clk_pllv3_wait_lock will call usleep_range, and the clk APIs
> mutex lock may be held when CPU entering idle, so calling clk
> APIs must be avoided in cpu idle thread, this is to avoid reschedule
> warning in cpu idle, just access register directly to achieve that.
...
> Signed-off-by: Anson Huang <b20788@freescale.com>
Applied, thanks.
^ permalink raw reply
* [PATCH V6 07/12] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
From: Mohit KUMAR DCG @ 2014-02-12 4:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FA122A.1010900@ti.com>
Hello Kishon,
> -----Original Message-----
> From: Kishon Vijay Abraham I [mailto:kishon at ti.com]
> Sent: Tuesday, February 11, 2014 5:36 PM
> To: Mohit KUMAR DCG; arnd at arndb.de
> Cc: Pratyush ANAND; Viresh Kumar; spear-devel; linux-arm-
> kernel at lists.infradead.org; linux-kernel at vger.kernel.org
> Subject: Re: [PATCH V6 07/12] phy: st-miphy-40lp: Add SPEAr1310 and
> SPEAr1340 PCIe phy support
>
> On Tuesday 11 February 2014 03:00 PM, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds
> > support for the same.
>
> What's up with SATA support for SPEAr1310? Do you have plans of adding it
> soon?
> >
- yes we will be doing it after this series is finalized.
[...]
> > +
> > + regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
> > + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
> > + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
> > +
> > + switch (priv->id) {
>
> 'id' should be made as optional dt property since it's not used for 1340 no?
>
- ok
Thanks
Mohit
^ permalink raw reply
* [PATCH 4/9] ARM: Select V6K instead of V6 by default for multi-platform
From: Shawn Guo @ 2014-02-12 4:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392153119-23248-5-git-send-email-robherring2@gmail.com>
On Tue, Feb 11, 2014 at 03:11:54PM -0600, Rob Herring wrote:
> From: Rob Herring <robh@kernel.org>
>
> MULTI_V6 should default to V6K as it is more optimal than V6. Any
> platform which is not V6K should select CPU_V6 which will enable the
> less optimal code paths.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
> Cc: Anton Vorontsov <anton@enomsg.org>
> Cc: Shawn Guo <shawn.guo@linaro.org>
...
> arch/arm/mach-imx/Kconfig | 1 -
Acked-by: Shawn Guo <shawn.guo@linaro.org>
^ permalink raw reply
* [PATCH] ARM: shmobile: Remove legacy r8a7790 DT clocks
From: Magnus Damm @ 2014-02-12 4:09 UTC (permalink / raw)
To: linux-arm-kernel
From: Magnus Damm <damm@opensource.se>
The DT device case is handled by CCF these days, so get
rid of DT devices from the legacy clocks for r8a7790.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-shmobile/clock-r8a7790.c | 11 -----------
1 file changed, 11 deletions(-)
--- 0001/arch/arm/mach-shmobile/clock-r8a7790.c
+++ work/arch/arm/mach-shmobile/clock-r8a7790.c 2014-02-10 16:04:29.000000000 +0900
@@ -328,34 +328,23 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
- CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
- CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
- CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
- CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
- CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
- CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
- CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
- CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
- CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
- CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]),
CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
- CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
^ permalink raw reply
* [PATCH] ARM: dts: exynos5250-arndale: Keep G3D regulator always on
From: Tushar Behera @ 2014-02-12 4:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392141043-27170-1-git-send-email-t.figa@samsung.com>
On 11 February 2014 23:20, Tomasz Figa <t.figa@samsung.com> wrote:
> Apparently, if G3D regulator is powered off, the SoC cannot enter low
> power modes and just hangs. This patch fixes this by keeping the
> regulator always on when the system is running, as suggested by Exynos 4
> User's Manual in case of Exynos4210/4x12 SoCs (Exynos5250 UM does not
> have such note, but observed behavior seems to confirm that it is true
> for this SoC as well).
>
> This fixes an issue preventing Arndale board from entering sleep mode
> observed since commit
>
> 346f372f7b72a0 clk: exynos5250: Add CLK_IGNORE_UNUSED flag for pmu clock
>
> that landed in kernel 3.11, which has fixed the clock driver to make the
> SoC actually try to enter the sleep mode.
>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
> Cc: stable at vger.kernel.org
Thanks for the patch.
Tested-by: Tushar Behera <tushar.behera@linaro.org>
--
Tushar Behera
^ permalink raw reply
* [PATCH V5 4/8] phy: st-miphy-40lp: Add skeleton driver
From: Mohit KUMAR DCG @ 2014-02-12 4:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <10315753.nkNxr0yDnp@wuerfel>
Hello Arnd,
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Tuesday, February 11, 2014 8:09 PM
> To: Mohit KUMAR DCG
> Cc: Pratyush ANAND; Kishon Vijay Abraham I; spear-devel; linux-arm-
> kernel at lists.infradead.org; devicetree at vger.kernel.org; linux-
> kernel at vger.kernel.org; Lee Jones
> Subject: Re: [PATCH V5 4/8] phy: st-miphy-40lp: Add skeleton driver
>
> On Tuesday 11 February 2014 11:57:46 Mohit KUMAR DCG wrote:
> >
> > > Maybe mention that this phy is used inside the spear13xx SoC here
> > > rather than a standalone phy.
> >
> > - Yes, for spear13xx its used internally. Do you think that it
> > requires to be mentioned here?
> > We have few prototype boards that uses this as external phy.
>
> [adding Lee since he mentioned working on a similar part]
>
> I'm a bit confused. Is it actually the same IP block that can be used internally
> as part of a SoC and as a standalone chip?
>
> Since some of the settings of the PHY are controlled through the misc
> register in case of spear13xx, I assume that part is different on the
> standalone version. How do you actually select the mode in that case?
>
> It would certainly be helpful to explain this somewhere, and the binding
> might not be the worst place for this.
>
> On a related note, the driver in its current shape looks a bit silly since it
> doesn't contain any of the miphy specific code but only the SoC specific parts
> (as I suggested you do, so I'm not blaming you :-)) and a multiplexer that
> switches between the two possible implementations.
- yes, thats what we were explaining earlier. If it is integrated into some SoC
Then there are some soc specific configurations. Actual phy reg settings could
also vary for the different SoCs for the best tuning.
However we agreed to your idea as miphy40lp register definitions would remain
same across the SoCs.
>
> What is your plan for the future, do you intend to add the actual miphy code
> soon, or is that something you just want to leave as an option for the future
> but have no specific plans to do right now? If not, the driver would probably
> look nicer if it were split into two separate implementations, one for each
> spear13xx SoC and with a separate set of phy_ops but no multiplexer.
Do you want it to split the code into two different files like phy-miphyspear1310.c
and phy-miphyspear1340.c ?
Regards
Mohit
^ permalink raw reply
* [PATCH 0/7] ARM: shmobile: r8a7790/Lager QSPI SoC/board integration
From: Magnus Damm @ 2014-02-12 5:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392029254-15400-1-git-send-email-geert@linux-m68k.org>
Hi Geert, Simon,
On Mon, Feb 10, 2014 at 7:47 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> Hi Simon, Magnus,
>
> The following patch series completes r8a7790 SoC and Lager board
> integration for the Renesas Quad Serial Peripheral Interface. It brings
> r8a7790/Lager to the same support level as r8a7791/Koelsch, allowing access
> to the Spansion s25fl512s SPI FLASH for both legacy and multi-platform
> kernels.
>
> [1/7] pinctrl: sh-pfc: r8a7790: Add QSPI pin groups
> [2/7] ARM: shmobile: lager legacy: Add QSPI pinmux
> [3/7] ARM: shmobile: r8a7790 dtsi: Add QSPI node
> [4/7] ARM: shmobile: lager dts: Add QSPI nodes
> [5/7] ARM: shmobile: lager defconfig: Enable RSPI and MTD_M25P80
Thanks a lot for this! All patches included in this series look great to me.
I noticed that 1/7 turned into a v2, so feel free to omit or include
the below ack.
Acked-by: Magnus Damm <damm@opensource.se>
> [6/7] ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI
> FLASH
> [7/7] ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI
> FLASH
>
> Please do _not_ apply patches [6/7] and [7/7] yet, as these have a runtime
> dependency on Quad SPI support in the RSPI/QSPI driver, which is queued up
> in the linux-spi tree for v3.15.
That makes sense, thanks for pointing that out. You still have my Ack
though, so please include that when you resend.
Simon, can you please pick up 2-5?
Cheers,
/ magnus
^ permalink raw reply
* [PATCH 1/2] ARM: bcm2835: fix DT node sort order
From: Stephen Warren @ 2014-02-12 5:03 UTC (permalink / raw)
To: linux-arm-kernel
Re-order all the DT nodes so that they're ordered by their reg address.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
---
arch/arm/boot/dts/bcm2835.dtsi | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 398eac3..5ceba45 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -60,14 +60,6 @@
reg = <0x7e104000 0x10>;
};
- uart at 20201000 {
- compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
- reg = <0x7e201000 0x1000>;
- interrupts = <2 25>;
- clock-frequency = <3000000>;
- arm,primecell-periphid = <0x00241011>;
- };
-
gpio: gpio {
compatible = "brcm,bcm2835-gpio";
reg = <0x7e200000 0xb4>;
@@ -91,6 +83,14 @@
#interrupt-cells = <2>;
};
+ uart at 20201000 {
+ compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
+ reg = <0x7e201000 0x1000>;
+ interrupts = <2 25>;
+ clock-frequency = <3000000>;
+ arm,primecell-periphid = <0x00241011>;
+ };
+
i2s: i2s at 7e203000 {
compatible = "brcm,bcm2835-i2s";
reg = <0x7e203000 0x20>,
@@ -121,6 +121,14 @@
status = "disabled";
};
+ sdhci: sdhci {
+ compatible = "brcm,bcm2835-sdhci";
+ reg = <0x7e300000 0x100>;
+ interrupts = <2 30>;
+ clocks = <&clk_mmc>;
+ status = "disabled";
+ };
+
i2c1: i2c at 20804000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e804000 0x1000>;
@@ -131,14 +139,6 @@
status = "disabled";
};
- sdhci: sdhci {
- compatible = "brcm,bcm2835-sdhci";
- reg = <0x7e300000 0x100>;
- interrupts = <2 30>;
- clocks = <&clk_mmc>;
- status = "disabled";
- };
-
usb {
compatible = "brcm,bcm2835-usb";
reg = <0x7e980000 0x10000>;
--
1.8.3.2
^ permalink raw reply related
* [PATCH 2/2] ARM: bcm2835: add unit address to all nodes w/ reg prop
From: Stephen Warren @ 2014-02-12 5:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392181392-29694-1-git-send-email-swarren@wwwdotorg.org>
DT nodes that contain a reg property should include a unit address in
their name. Add the missing unit addresses.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
---
arch/arm/boot/dts/bcm2835.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 5ceba45..9eadfb7 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -15,7 +15,7 @@
#size-cells = <1>;
ranges = <0x7e000000 0x20000000 0x02000000>;
- timer {
+ timer at 7e003000 {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7e003000 0x1000>;
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
@@ -43,24 +43,24 @@
brcm,dma-channel-mask = <0x7f35>;
};
- intc: interrupt-controller {
+ intc: interrupt-controller at 7e00b200 {
compatible = "brcm,bcm2835-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
- watchdog {
+ watchdog at 7e100000 {
compatible = "brcm,bcm2835-pm-wdt";
reg = <0x7e100000 0x28>;
};
- rng {
+ rng at 7e104000 {
compatible = "brcm,bcm2835-rng";
reg = <0x7e104000 0x10>;
};
- gpio: gpio {
+ gpio: gpio at 7e200000 {
compatible = "brcm,bcm2835-gpio";
reg = <0x7e200000 0xb4>;
/*
@@ -121,7 +121,7 @@
status = "disabled";
};
- sdhci: sdhci {
+ sdhci: sdhci at 7e300000 {
compatible = "brcm,bcm2835-sdhci";
reg = <0x7e300000 0x100>;
interrupts = <2 30>;
@@ -139,7 +139,7 @@
status = "disabled";
};
- usb {
+ usb at 7e980000 {
compatible = "brcm,bcm2835-usb";
reg = <0x7e980000 0x10000>;
interrupts = <1 9>;
@@ -155,21 +155,21 @@
#address-cells = <1>;
#size-cells = <0>;
- clk_mmc: mmc {
+ clk_mmc: clock at 0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <100000000>;
};
- clk_i2c: i2c {
+ clk_i2c: clock at 1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <250000000>;
};
- clk_spi: spi {
+ clk_spi: clock at 2 {
compatible = "fixed-clock";
reg = <2>;
#clock-cells = <0>;
--
1.8.3.2
^ permalink raw reply related
* [patch] initial perf_event support for Raspberry-Pi
From: Stephen Warren @ 2014-02-12 5:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.10.1312311649530.3173@vincent-weaver-1.um.maine.edu>
On 12/31/2013 02:54 PM, Vince Weaver wrote:
>
> The following patch enables performance counter support on Raspberry-Pi.
>
> We have this working on the 2708 based rasp-pi kernels by manually putting
> the device registration in the platform files.
>
> This change does things properly in a device tree. The boot messages look
> proper, but my rasp-pi hangs somewhere in USB enabling when running a
> stock 3.13-rc6 kernel so I have been unable to fully test this change.
>
> I also understand that the rasp-pi 1176 pmu support is missing the
> overflow interrupt. I'm not sure if that's true of all 2835
> implementations. If not, then this patch will need to be changed a bit.
I've applied this to bcm2835's for-3.15/dt branch, with minor fixes.
^ permalink raw reply
* [PATCH 1/2] BCM2835: Add dmaengine driver to device tree
From: Stephen Warren @ 2014-02-12 5:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52D3C9EF.1030901@koalo.de>
On 01/13/2014 04:11 AM, Florian Meier wrote:
> This adds the definitions for the BCM2835 dmaengine driver
> to the device tree. The dma-channel-mask is currently
> fixed. Later it should be set via the firmware.
I've applied patch 1, and the part of patch 2 which touches bcm2835.dtsi
to bcm2835's for-3.15/dt branch, with minor fixes.
^ permalink raw reply
* [PATCH 1/2] ARM: bcm2835: fix DT node sort order
From: Stephen Warren @ 2014-02-12 5:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392181392-29694-1-git-send-email-swarren@wwwdotorg.org>
On 02/11/2014 10:03 PM, Stephen Warren wrote:
> Re-order all the DT nodes so that they're ordered by their reg address.
I've applied this series to bcm2835's for-3.15/dt branch.
^ permalink raw reply
* [PATCHv3 2/2] arm: Get rid of meminfo
From: Kukjin Kim @ 2014-02-12 5:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392153265-14439-3-git-send-email-lauraa@codeaurora.org>
2014-02-12 2:44 GMT+05:30 Laura Abbott <lauraa@codeaurora.org>:
> memblock is now fully integrated into the kernel and is the prefered
> method for tracking memory. Rather than reinvent the wheel with
> meminfo, migrate to using memblock directly instead of meminfo as
> an intermediate.
>
> Acked-by: Jason Cooper <jason@lakedaemon.net>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
> Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
> ---
> arch/arm/include/asm/mach/arch.h | 4 +-
> arch/arm/include/asm/memblock.h | 3 +-
> arch/arm/include/asm/setup.h | 23 ------
> arch/arm/kernel/atags_parse.c | 5 +-
> arch/arm/kernel/devtree.c | 5 --
> arch/arm/kernel/setup.c | 30 ++------
> arch/arm/mach-clps711x/board-clep7312.c | 7 +-
> arch/arm/mach-clps711x/board-edb7211.c | 10 +--
> arch/arm/mach-clps711x/board-p720t.c | 2 +-
> arch/arm/mach-footbridge/cats-hw.c | 2 +-
> arch/arm/mach-footbridge/netwinder-hw.c | 2 +-
> arch/arm/mach-msm/board-halibut.c | 6 --
> arch/arm/mach-msm/board-mahimahi.c | 13 +---
> arch/arm/mach-msm/board-msm7x30.c | 3 +-
> arch/arm/mach-msm/board-sapphire.c | 13 ++--
> arch/arm/mach-msm/board-trout.c | 8 +--
> arch/arm/mach-orion5x/common.c | 3 +-
> arch/arm/mach-orion5x/common.h | 3 +-
> arch/arm/mach-pxa/cm-x300.c | 3 +-
> arch/arm/mach-pxa/corgi.c | 10 +--
> arch/arm/mach-pxa/eseries.c | 9 +--
> arch/arm/mach-pxa/poodle.c | 8 +--
> arch/arm/mach-pxa/spitz.c | 8 +--
> arch/arm/mach-pxa/tosa.c | 8 +--
> arch/arm/mach-realview/core.c | 11 +--
> arch/arm/mach-realview/core.h | 3 +-
> arch/arm/mach-realview/realview_pb1176.c | 8 +--
> arch/arm/mach-realview/realview_pbx.c | 17 ++---
> arch/arm/mach-s3c24xx/mach-smdk2413.c | 8 +--
> arch/arm/mach-s3c24xx/mach-vstms.c | 8 +--
For s3c24xx,
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
> arch/arm/mach-sa1100/assabet.c | 2 +-
> arch/arm/mm/init.c | 67 +++++++-----------
> arch/arm/mm/mmu.c | 115 +++++++++---------------------
> 33 files changed, 136 insertions(+), 291 deletions(-)
Thanks,
Kukjin
^ permalink raw reply
* [PATCH v2 0/7] armv7 BE kvm support
From: Victor Kamensky @ 2014-02-12 5:41 UTC (permalink / raw)
To: linux-arm-kernel
Hi Guys,
Here is second version of series that enables KVM support for V7 big endian
kernels. Mostly it deals with BE KVM host support. Marc Zyngier showed before
with his patches how BE guest could run on top LE host. With these patches
BE guest runs on top of BE host. If Marc's kvmtool is used with few
additional changes I tested that BE host could run LE guest. Also I verified
that there were no regressions in BE guest on top of LE host case.
Note that posted series covers only kernel side changes. The changes were
tested inside of bigger setup with additional changes in qemu and kvmtool.
I will post those changes separately in proper aliases but for completeness
sake Appendix A gives pointers to git repositories and branches with all
needed changes.
Changes since V1:
1) Patch that handles issue of including assembler.h into kvm .S file now
handled separately. It was posted before on mailing list [1]. This series
depend on it.
2) Incorporated most of Christoffer V1 review comments. The only thing
I did not do wrt Christoffer's suggestion is possible rework of 'one_reg
coproc set and get BE fixes' patch. I think I put better explanation on
what my code does, and if it is still not good we will go from there.
3) Moved rr_lo_hi macro into arch/arm/include/asm/kvm_asm.h along the
lines Christoffer suggested
4) Split 'fix KVM assembler files to work in BE case' patch into 4 smaller
one each handling one logic issue.
Thanks,
Victor
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-February/231432.html
Victor Kamensky (7):
ARM: KVM: switch hypervisor into BE mode in case of BE host
ARM: KVM: fix vgic V7 assembler code to work in BE image
ARM: KVM: handle 64bit values passed to mrcc or from mcrr instructions
in BE case
ARM: KVM: __kvm_vcpu_run function return result fix in BE case
ARM: KVM: one_reg coproc set and get BE fixes
ARM: KVM: vgic mmio should hold data as LE bytes array in BE case
ARM: KVM: MMIO support BE host running LE code
arch/arm/include/asm/kvm_asm.h | 23 +++++++++-
arch/arm/include/asm/kvm_emulate.h | 22 +++++++--
arch/arm/kvm/coproc.c | 94 ++++++++++++++++++++++++++++----------
arch/arm/kvm/init.S | 7 ++-
arch/arm/kvm/interrupts.S | 9 +++-
arch/arm/kvm/interrupts_head.S | 32 +++++++++----
virt/kvm/arm/vgic.c | 4 +-
7 files changed, 145 insertions(+), 46 deletions(-)
--
1.8.1.4
Appendix A: Testing and Full Setup Description
----------------------------------------------
I) No mixed mode setup - i.e BE guest on BE host; and LE guest
on LE host tested to make sure no regressions.
KVM host and guest kernels:
TC2 on top of Linus 3.13 (this patch series):
git: git://git.linaro.org/people/victor.kamensky/linux-linaro-tracking-be.git
branch: arm-be-kvm-3.13
range: 7098f45..78419d0
TC2 and Arndale on top of Linaro BE tree:
git: git://git.linaro.org/people/victor.kamensky/linux-linaro-tracking-be.git
branch: llct-be-20140211-kvm
range: 308a752..ae47fa8
- TC1 kernels used as guests
qemu:
git: git://git.linaro.org/people/victor.kamensky/qemu-be.git
branch: armv7be-v1
description: changes to run qemu on armeb target; and other
changes to work with be image on top of be host
kvmtool:
git: git://git.linaro.org/people/victor.kamensky/linux-linaro-tracking-be.git
branch: kvmtool-armv7be-v1
description: minimal changes to build kvmtool for armeb target; and
tiny change with virtio magic
II) Mixed mode setup all possible combinations within V7 (LE guest on BE host;
BE guest on LE host as Marc's setup tested to make sure no regressions) only
with kvmtool.
This work is based on Marc Zyngier's work that made BE guest to run on top
of LE host. For this setup special version of kvmtool should be used and
in addition I had to apply patch to guest kernel that would switch reading
virtio configs reads to be LE only, that is made on top of previous Rusty
Russell's changes. Effectively I just had to do very minor addition to make
LE guest to work on BE host, most of heavy lifting was done before by Marc.
KVM host kernels: as in previous setup
Guest TC1 kernels with LE virtio config patch:
git: git://git.linaro.org/people/victor.kamensky/linux-linaro-tracking-be.git
branch: virtio-leconfig-3.13-rc4
kvmtool:
git: git://git.linaro.org/people/victor.kamensky/linux-linaro-tracking-be.git
branch: kvmtool-mixed-v1
description: based on git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
branch kvm-arm64/kvmtool-be-on-le; adds missing include fix; above armeb target
build patches; and one fix related to BE mode
qemu:
git: git://git.linaro.org/people/victor.kamensky/qemu-be.git
branch: armv7be-leconfig-v1
description: change virtio-blk that so qemu could work with guest image
where virtio leconfig is made; note it does not work in mixed mode; to do
so qemu would need bunch of similar changes that Marc did in kvmtool
^ permalink raw reply
* [PATCH v2 1/7] ARM: KVM: switch hypervisor into BE mode in case of BE host
From: Victor Kamensky @ 2014-02-12 5:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392183693-21238-1-git-send-email-victor.kamensky@linaro.org>
Switch hypervisor to run in BE mode if image is compiled
with CONFIG_CPU_BIG_ENDIAN.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
---
arch/arm/kvm/init.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
index 1b9844d..74f0718 100644
--- a/arch/arm/kvm/init.S
+++ b/arch/arm/kvm/init.S
@@ -22,6 +22,7 @@
#include <asm/kvm_asm.h>
#include <asm/kvm_arm.h>
#include <asm/kvm_mmu.h>
+#include <asm/assembler.h>
/********************************************************************
* Hypervisor initialization
@@ -70,6 +71,8 @@ __do_hyp_init:
cmp r0, #0 @ We have a SP?
bne phase2 @ Yes, second stage init
+ARM_BE8(setend be) @ Switch to Big Endian mode if needed
+
@ Set the HTTBR to point to the hypervisor PGD pointer passed
mcrr p15, 4, r2, r3, c2
--
1.8.1.4
^ permalink raw reply related
* [PATCH v2 2/7] ARM: KVM: fix vgic V7 assembler code to work in BE image
From: Victor Kamensky @ 2014-02-12 5:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392183693-21238-1-git-send-email-victor.kamensky@linaro.org>
The vgic h/w registers are little endian; when asm code reads/writes
from/to them, it needs to do byteswap after/before. Byteswap code
uses ARM_BE8 wrapper to add swap only if CONFIG_CPU_BIG_ENDIAN is
configured.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
---
arch/arm/kvm/interrupts_head.S | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index 6f18695..1e9be2f 100644
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -1,4 +1,5 @@
#include <linux/irqchip/arm-gic.h>
+#include <asm/assembler.h>
#define VCPU_USR_REG(_reg_nr) (VCPU_USR_REGS + (_reg_nr * 4))
#define VCPU_USR_SP (VCPU_USR_REG(13))
@@ -412,6 +413,14 @@ vcpu .req r0 @ vcpu pointer always in r0
ldr r8, [r2, #GICH_ELRSR0]
ldr r9, [r2, #GICH_ELRSR1]
ldr r10, [r2, #GICH_APR]
+ARM_BE8(rev r3, r3 )
+ARM_BE8(rev r4, r4 )
+ARM_BE8(rev r5, r5 )
+ARM_BE8(rev r6, r6 )
+ARM_BE8(rev r7, r7 )
+ARM_BE8(rev r8, r8 )
+ARM_BE8(rev r9, r9 )
+ARM_BE8(rev r10, r10 )
str r3, [r11, #VGIC_CPU_HCR]
str r4, [r11, #VGIC_CPU_VMCR]
@@ -431,6 +440,7 @@ vcpu .req r0 @ vcpu pointer always in r0
add r3, r11, #VGIC_CPU_LR
ldr r4, [r11, #VGIC_CPU_NR_LR]
1: ldr r6, [r2], #4
+ARM_BE8(rev r6, r6 )
str r6, [r3], #4
subs r4, r4, #1
bne 1b
@@ -458,6 +468,9 @@ vcpu .req r0 @ vcpu pointer always in r0
ldr r3, [r11, #VGIC_CPU_HCR]
ldr r4, [r11, #VGIC_CPU_VMCR]
ldr r8, [r11, #VGIC_CPU_APR]
+ARM_BE8(rev r3, r3 )
+ARM_BE8(rev r4, r4 )
+ARM_BE8(rev r8, r8 )
str r3, [r2, #GICH_HCR]
str r4, [r2, #GICH_VMCR]
@@ -468,6 +481,7 @@ vcpu .req r0 @ vcpu pointer always in r0
add r3, r11, #VGIC_CPU_LR
ldr r4, [r11, #VGIC_CPU_NR_LR]
1: ldr r6, [r3], #4
+ARM_BE8(rev r6, r6 )
str r6, [r2], #4
subs r4, r4, #1
bne 1b
--
1.8.1.4
^ permalink raw reply related
* [PATCH v2 3/7] ARM: KVM: handle 64bit values passed to mrcc or from mcrr instructions in BE case
From: Victor Kamensky @ 2014-02-12 5:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392183693-21238-1-git-send-email-victor.kamensky@linaro.org>
In some cases the mcrr and mrrc instructions in combination with the ldrd
and strd instructions need to deal with 64bit value in memory. The ldrd
and strd instructions already handle endianness within word (register)
boundaries but to get effect of the whole 64bit value represented correctly,
rr_lo_hi macro is introduced and is used to swap registers positions when
the mcrr and mrrc instructions are used. That has the effect of swapping
two words.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
---
arch/arm/include/asm/kvm_asm.h | 23 +++++++++++++++++++++--
arch/arm/kvm/init.S | 4 ++--
arch/arm/kvm/interrupts.S | 4 ++--
arch/arm/kvm/interrupts_head.S | 18 +++++++++---------
4 files changed, 34 insertions(+), 15 deletions(-)
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index 661da11..c6ae937 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -26,9 +26,9 @@
#define c1_ACTLR 4 /* Auxilliary Control Register */
#define c1_CPACR 5 /* Coprocessor Access Control */
#define c2_TTBR0 6 /* Translation Table Base Register 0 */
-#define c2_TTBR0_high 7 /* TTBR0 top 32 bits */
+#define c2_TTBR0_hilo 7 /* TTBR0 top 32 bits in LE case, low 32 bits in BE case */
#define c2_TTBR1 8 /* Translation Table Base Register 1 */
-#define c2_TTBR1_high 9 /* TTBR1 top 32 bits */
+#define c2_TTBR1_hilo 9 /* TTBR1 top 32 bits in LE case, low 32 bits in BE case */
#define c2_TTBCR 10 /* Translation Table Base Control R. */
#define c3_DACR 11 /* Domain Access Control Register */
#define c5_DFSR 12 /* Data Fault Status Register */
@@ -59,6 +59,25 @@
#define ARM_EXCEPTION_FIQ 6
#define ARM_EXCEPTION_HVC 7
+/*
+ * The rr_lo_hi macro swap pair of registers positions depending on
+ * current endianness. It is used in conjunction with ldrd and strd
+ * instructions that loads/store 64 bit value from/to memory to/from
+ * pair of registers which are used with the mrrc and mcrr instructions.
+ * The a1 parameter is register that typically holds lower address
+ * word (least significant word in LE, most significant in BE). The
+ * a2 parameter is register that holds higher address word. Note
+ * within word (single register) the ldrd/strd instruction already
+ * swap data correctly, only additional manipulation required with order
+ * of register to have effect of 64 bit value beeing effectively
+ * swapped.
+ */
+#ifdef CONFIG_CPU_ENDIAN_BE8
+#define rr_lo_hi(a1, a2) a2, a1
+#else
+#define rr_lo_hi(a1, a2) a1, a2
+#endif
+
#ifndef __ASSEMBLY__
struct kvm;
struct kvm_vcpu;
diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
index 74f0718..2d10b2d 100644
--- a/arch/arm/kvm/init.S
+++ b/arch/arm/kvm/init.S
@@ -74,7 +74,7 @@ __do_hyp_init:
ARM_BE8(setend be) @ Switch to Big Endian mode if needed
@ Set the HTTBR to point to the hypervisor PGD pointer passed
- mcrr p15, 4, r2, r3, c2
+ mcrr p15, 4, rr_lo_hi(r2, r3), c2
@ Set the HTCR and VTCR to the same shareability and cacheability
@ settings as the non-secure TTBCR and with T0SZ == 0.
@@ -140,7 +140,7 @@ phase2:
mov pc, r0
target: @ We're now in the trampoline code, switch page tables
- mcrr p15, 4, r2, r3, c2
+ mcrr p15, 4, rr_lo_hi(r2, r3), c2
isb
@ Invalidate the old TLBs
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index ddc1553..f0696bd 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -52,7 +52,7 @@ ENTRY(__kvm_tlb_flush_vmid_ipa)
dsb ishst
add r0, r0, #KVM_VTTBR
ldrd r2, r3, [r0]
- mcrr p15, 6, r2, r3, c2 @ Write VTTBR
+ mcrr p15, 6, rr_lo_hi(r2, r3), c2 @ Write VTTBR
isb
mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS (rt ignored)
dsb ish
@@ -135,7 +135,7 @@ ENTRY(__kvm_vcpu_run)
ldr r1, [vcpu, #VCPU_KVM]
add r1, r1, #KVM_VTTBR
ldrd r2, r3, [r1]
- mcrr p15, 6, r2, r3, c2 @ Write VTTBR
+ mcrr p15, 6, rr_lo_hi(r2, r3), c2 @ Write VTTBR
@ We're all done, just restore the GPRs and go to the guest
restore_guest_regs
diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index 1e9be2f..3409ed6 100644
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -252,8 +252,8 @@ vcpu .req r0 @ vcpu pointer always in r0
mrc p15, 0, r3, c1, c0, 2 @ CPACR
mrc p15, 0, r4, c2, c0, 2 @ TTBCR
mrc p15, 0, r5, c3, c0, 0 @ DACR
- mrrc p15, 0, r6, r7, c2 @ TTBR 0
- mrrc p15, 1, r8, r9, c2 @ TTBR 1
+ mrrc p15, 0, rr_lo_hi(r6, r7), c2 @ TTBR 0
+ mrrc p15, 1, rr_lo_hi(r8, r9), c2 @ TTBR 1
mrc p15, 0, r10, c10, c2, 0 @ PRRR
mrc p15, 0, r11, c10, c2, 1 @ NMRR
mrc p15, 2, r12, c0, c0, 0 @ CSSELR
@@ -303,7 +303,7 @@ vcpu .req r0 @ vcpu pointer always in r0
.endif
mrc p15, 0, r2, c14, c1, 0 @ CNTKCTL
- mrrc p15, 0, r4, r5, c7 @ PAR
+ mrrc p15, 0, rr_lo_hi(r4, r5), c7 @ PAR
.if \store_to_vcpu == 0
push {r2,r4-r5}
@@ -331,7 +331,7 @@ vcpu .req r0 @ vcpu pointer always in r0
.endif
mcr p15, 0, r2, c14, c1, 0 @ CNTKCTL
- mcrr p15, 0, r4, r5, c7 @ PAR
+ mcrr p15, 0, rr_lo_hi(r4, r5), c7 @ PAR
.if \read_from_vcpu == 0
pop {r2-r12}
@@ -381,8 +381,8 @@ vcpu .req r0 @ vcpu pointer always in r0
mcr p15, 0, r3, c1, c0, 2 @ CPACR
mcr p15, 0, r4, c2, c0, 2 @ TTBCR
mcr p15, 0, r5, c3, c0, 0 @ DACR
- mcrr p15, 0, r6, r7, c2 @ TTBR 0
- mcrr p15, 1, r8, r9, c2 @ TTBR 1
+ mcrr p15, 0, rr_lo_hi(r6, r7), c2 @ TTBR 0
+ mcrr p15, 1, rr_lo_hi(r8, r9), c2 @ TTBR 1
mcr p15, 0, r10, c10, c2, 0 @ PRRR
mcr p15, 0, r11, c10, c2, 1 @ NMRR
mcr p15, 2, r12, c0, c0, 0 @ CSSELR
@@ -512,7 +512,7 @@ ARM_BE8(rev r6, r6 )
mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
isb
- mrrc p15, 3, r2, r3, c14 @ CNTV_CVAL
+ mrrc p15, 3, rr_lo_hi(r2, r3), c14 @ CNTV_CVAL
ldr r4, =VCPU_TIMER_CNTV_CVAL
add r5, vcpu, r4
strd r2, r3, [r5]
@@ -552,12 +552,12 @@ ARM_BE8(rev r6, r6 )
ldr r2, [r4, #KVM_TIMER_CNTVOFF]
ldr r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
- mcrr p15, 4, r2, r3, c14 @ CNTVOFF
+ mcrr p15, 4, rr_lo_hi(r2, r3), c14 @ CNTVOFF
ldr r4, =VCPU_TIMER_CNTV_CVAL
add r5, vcpu, r4
ldrd r2, r3, [r5]
- mcrr p15, 3, r2, r3, c14 @ CNTV_CVAL
+ mcrr p15, 3, rr_lo_hi(r2, r3), c14 @ CNTV_CVAL
isb
ldr r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
--
1.8.1.4
^ permalink raw reply related
* [PATCH v2 4/7] ARM: KVM: __kvm_vcpu_run function return result fix in BE case
From: Victor Kamensky @ 2014-02-12 5:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392183693-21238-1-git-send-email-victor.kamensky@linaro.org>
The __kvm_vcpu_run function returns a 64-bit result in two registers,
which has to be adjusted for BE case.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
---
arch/arm/kvm/interrupts.S | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index f0696bd..5d27f7f 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -199,8 +199,13 @@ after_vfp_restore:
restore_host_regs
clrex @ Clear exclusive monitor
+#ifndef __ARMEB__
mov r0, r1 @ Return the return code
mov r1, #0 @ Clear upper bits in return value
+#else
+ @ r1 already has return code
+ mov r0, #0 @ Clear upper bits in return value
+#endif /* __ARMEB__ */
bx lr @ return to IOCTL
/********************************************************************
--
1.8.1.4
^ permalink raw reply related
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