* [PATCH v2] ARM: mm: report both sections from PMD
From: Catalin Marinas @ 2014-02-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGXu5jKG=8Fwd=yJEFF0-8tO0v4H_3sr_x2JLW4jm1Y2ouDFHQ@mail.gmail.com>
On Thu, Feb 13, 2014 at 07:52:03PM +0000, Kees Cook wrote:
> On Thu, Feb 13, 2014 at 9:12 AM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
> > On Wed, Feb 12, 2014 at 10:46:38PM +0000, Kees Cook wrote:
> >> diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
> >> index 03243f7eeddf..fb3de59ee811 100644
> >> --- a/arch/arm/include/asm/pgtable-3level.h
> >> +++ b/arch/arm/include/asm/pgtable-3level.h
> >> @@ -138,10 +138,6 @@
> >> #define pud_none(pud) (!pud_val(pud))
> >> #define pud_bad(pud) (!(pud_val(pud) & 2))
> >> #define pud_present(pud) (pud_val(pud))
> >> -#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
> >> - PMD_TYPE_TABLE)
> >> -#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
> >> - PMD_TYPE_SECT)
> >> #define pmd_large(pmd) pmd_sect(pmd)
> >>
> >> #define pud_clear(pudp) \
> >> diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
> >> index 7d59b524f2af..934aa5b60c7c 100644
> >> --- a/arch/arm/include/asm/pgtable.h
> >> +++ b/arch/arm/include/asm/pgtable.h
> >> @@ -183,6 +183,10 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
> >>
> >> #define pmd_none(pmd) (!pmd_val(pmd))
> >> #define pmd_present(pmd) (pmd_val(pmd))
> >> +#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
> >> + PMD_TYPE_TABLE)
> >> +#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
> >> + PMD_TYPE_SECT)
> >
> > Do you still need to move these two if you only use pmd_large()? AFAICT,
> > it is equivalent to pmd_sect().
>
> Why does pmd_sect exist? I can reduce it to just using pmd_large.
pmd_sect/pmd_table were there first and used by kvm. The pmd_large() was
added by Russell because the dump.c code was derived from x86 which uses
such macro. And we have another close relative, pmd_huge(), though only
defined if CONFIG_HUGETLB_PAGE.
We could drop pmd_large() in favour of pmd_sect() but it's up to
Russell. OTOH, when someone will try to add arm64 support, I'll most
likely ask for part of the x86 code to be turned into a generic library
and we'll need some common naming for such macros (e.g. pmd_large()).
--
Catalin
^ permalink raw reply
* [PATCH v3] ARM: mm: report both sections from PMD
From: Catalin Marinas @ 2014-02-14 10:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140213195230.GA15275@www.outflux.net>
On Thu, Feb 13, 2014 at 07:52:30PM +0000, Kees Cook wrote:
> On 2-level page table systems, the PMD has 2 section entries. Report
> these, otherwise ARM_PTDUMP will miss reporting permission changes on
> odd section boundaries.
>
> Signed-off-by: Kees Cook <keescook@chromium.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
^ permalink raw reply
* [PATCH v5 2/3] serial: fsl_lpuart: add DMA support
From: Mark Rutland @ 2014-02-14 10:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392362839-8004-3-git-send-email-yao.yuan@freescale.com>
On Fri, Feb 14, 2014 at 07:27:18AM +0000, Yuan Yao wrote:
> Add dma support for lpuart. This function depend on DMA driver.
> You can turn on it by write both the dmas and dma-name properties in dts node.
>
> Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
> ---
> .../devicetree/bindings/serial/fsl-lpuart.txt | 19 +-
> drivers/tty/serial/fsl_lpuart.c | 430 ++++++++++++++++++++-
> 2 files changed, 433 insertions(+), 16 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
> index 6fd1dd1..6e1cbbf 100644
> --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
> +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
> @@ -5,10 +5,24 @@ Required properties:
> - reg : Address and length of the register set for the device
> - interrupts : Should contain uart interrupt
>
> +Optional properties:
> +- dmas: List of two DMA specifiers, using a three-cell specifier for each channel.
> + a phandle plus two integer cells. The three cells in order are:
> + 1.A phandle pointing to the DMA controller.
> + 2.specifies the channel group(DMAMUX) in which this request can be multiplexed,
> + 3.specifies the request source.
The precise format of a dma-specifier is up to the DMA binding. Why does
the client binding care?
> +- dma-names: Contains one identifier string for each DMA specifier in the dmas property.
> + "tx" for the transmit channel, "rx" for the receive channel.
> +
> +Note: Optional properties for DMA support. Write them both or both not.
> +
All you need is something like:
dmas: A list of two dma specifiers, one for each entry in dma-names
dma-names: should contain "tx" and "rx".
Thanks,
Mark.
^ permalink raw reply
* [PATCH v2 10/52] arm, kvm: Fix CPU hotplug callback registration
From: Paolo Bonzini @ 2014-02-14 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140214075122.22701.18462.stgit@srivatsabhat.in.ibm.com>
Il 14/02/2014 08:51, Srivatsa S. Bhat ha scritto:
> Subsystems that want to register CPU hotplug callbacks, as well as perform
> initialization for the CPUs that are already online, often do it as shown
> below:
>
> get_online_cpus();
>
> for_each_online_cpu(cpu)
> init_cpu(cpu);
>
> register_cpu_notifier(&foobar_cpu_notifier);
>
> put_online_cpus();
>
> This is wrong, since it is prone to ABBA deadlocks involving the
> cpu_add_remove_lock and the cpu_hotplug.lock (when running concurrently
> with CPU hotplug operations).
>
> Instead, the correct and race-free way of performing the callback
> registration is:
>
> cpu_notifier_register_begin();
>
> for_each_online_cpu(cpu)
> init_cpu(cpu);
>
> /* Note the use of the double underscored version of the API */
> __register_cpu_notifier(&foobar_cpu_notifier);
>
> cpu_notifier_register_done();
>
>
> Fix the kvm code in arm by using this latter form of callback registration.
>
> Cc: Christoffer Dall <christoffer.dall@linaro.org>
> Cc: Gleb Natapov <gleb@kernel.org>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Ingo Molnar <mingo@kernel.org>
> Cc: kvmarm at lists.cs.columbia.edu
> Cc: kvm at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
> ---
>
> arch/arm/kvm/arm.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> index 1d8248e..147b917 100644
> --- a/arch/arm/kvm/arm.c
> +++ b/arch/arm/kvm/arm.c
> @@ -1050,21 +1050,26 @@ int kvm_arch_init(void *opaque)
> }
> }
>
> + cpu_notifier_register_begin();
> +
> err = init_hyp_mode();
> if (err)
> goto out_err;
>
> - err = register_cpu_notifier(&hyp_init_cpu_nb);
> + err = __register_cpu_notifier(&hyp_init_cpu_nb);
> if (err) {
> kvm_err("Cannot register HYP init CPU notifier (%d)\n", err);
> goto out_err;
> }
>
> + cpu_notifier_register_done();
> +
> hyp_cpu_pm_init();
>
> kvm_coproc_table_init();
> return 0;
> out_err:
> + cpu_notifier_register_done();
> return err;
> }
>
>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply
* [PATCH 0/6] ARM: integrator: multiplatform advancements
From: Linus Walleij @ 2014-02-14 10:29 UTC (permalink / raw)
To: linux-arm-kernel
This takes some steps towards enabling multiplatform support for the
Integrator. This also removes some minor strings attached to the
Versatile and RealView platforms to help them advancing.
File movement is trivial, but I need some advice on the memory.h
removal patch which is more of a puzzle due to lack of history
with this header on my behalf.
What remains for multiplatform afte this is just one
thing: <plat/clcd.h>. That is the only dependency toward
plat-versatile and the <plat/*> inclusion hierarchy remaining
for the Integrator.
This is a display database and timing set-up callback driver
where the Versatile family looks up settings for VGA and similar
displays.
I'm tempted to attempt to just move this down into drivers/video
alongside the CLCD driver with some platform data header in
<linux/platform_data/video-clcd.h>.
The *real* solution, one might argue is to convert the CLCD
driver to DRM and add device tree bindings, but it appears that
this is an orthogonal goal that has been attempted by other with
mixed results.
I have tested all patches on the Integrator/AP and Integrator/CP,
but I'd appreciate help testing some PCI traffic as well if
you (Will!) have an Integrator/AP with working PCI set-up.
Since this is based on other patches from me, here is a
pullable branch based on v3.14-rc2:
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator.git multiplatform
Linus Walleij (6):
ARM: integrator: localize the lm.h header
ARM: integrator: localize the impd1.h header
ARM: integrator: merge platform.h to hardware.h
ARM: integrator: localize the hardware.h header
ARM: integrator: register sched_clock directly
RFC: ARM: integrator: get rid of <mach/memory.h>
arch/arm/Kconfig | 1 -
arch/arm/mach-integrator/core.c | 4 +-
arch/arm/mach-integrator/hardware.h | 354 +++++++++++++++++++++
arch/arm/mach-integrator/impd1.c | 4 +-
arch/arm/mach-integrator/impd1.h | 14 +
arch/arm/mach-integrator/include/mach/hardware.h | 45 ---
arch/arm/mach-integrator/include/mach/impd1.h | 18 --
arch/arm/mach-integrator/include/mach/lm.h | 23 --
arch/arm/mach-integrator/include/mach/memory.h | 34 --
arch/arm/mach-integrator/include/mach/platform.h | 382 -----------------------
arch/arm/mach-integrator/integrator_ap.c | 6 +-
arch/arm/mach-integrator/integrator_cp.c | 17 +-
arch/arm/mach-integrator/leds.c | 4 +-
arch/arm/mach-integrator/lm.c | 2 +-
arch/arm/mach-integrator/lm.h | 23 ++
arch/arm/mach-integrator/pci_v3.c | 4 +-
drivers/clk/versatile/clk-impd1.c | 6 +-
17 files changed, 411 insertions(+), 530 deletions(-)
create mode 100644 arch/arm/mach-integrator/hardware.h
create mode 100644 arch/arm/mach-integrator/impd1.h
delete mode 100644 arch/arm/mach-integrator/include/mach/hardware.h
delete mode 100644 arch/arm/mach-integrator/include/mach/impd1.h
delete mode 100644 arch/arm/mach-integrator/include/mach/lm.h
delete mode 100644 arch/arm/mach-integrator/include/mach/memory.h
delete mode 100644 arch/arm/mach-integrator/include/mach/platform.h
create mode 100644 arch/arm/mach-integrator/lm.h
--
1.8.5.3
^ permalink raw reply
* [PATCH 1/6] ARM: integrator: localize the lm.h header
From: Linus Walleij @ 2014-02-14 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392373771-17303-1-git-send-email-linus.walleij@linaro.org>
As we move toward multiplatform support for the Integrator family
we need to localize all <mach/*> headers. This moves the lm.h
header down to the machine folder as it is not used outside it
anyway.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Jonathan Austin <jonathan.austin@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-integrator/impd1.c | 2 +-
arch/arm/mach-integrator/include/mach/lm.h | 23 -----------------------
arch/arm/mach-integrator/integrator_ap.c | 3 +--
arch/arm/mach-integrator/integrator_cp.c | 3 ---
arch/arm/mach-integrator/lm.c | 2 +-
arch/arm/mach-integrator/lm.h | 23 +++++++++++++++++++++++
6 files changed, 26 insertions(+), 30 deletions(-)
delete mode 100644 arch/arm/mach-integrator/include/mach/lm.h
create mode 100644 arch/arm/mach-integrator/lm.h
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index d9b784824808..a90e83fe8776 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -25,9 +25,9 @@
#include <linux/slab.h>
#include <linux/irqchip/arm-vic.h>
-#include <mach/lm.h>
#include <mach/impd1.h>
#include <asm/sizes.h>
+#include "lm.h"
static int module_id;
diff --git a/arch/arm/mach-integrator/include/mach/lm.h b/arch/arm/mach-integrator/include/mach/lm.h
deleted file mode 100644
index 28186b6f2c09..000000000000
--- a/arch/arm/mach-integrator/include/mach/lm.h
+++ /dev/null
@@ -1,23 +0,0 @@
-
-struct lm_device {
- struct device dev;
- struct resource resource;
- unsigned int irq;
- unsigned int id;
-};
-
-struct lm_driver {
- struct device_driver drv;
- int (*probe)(struct lm_device *);
- void (*remove)(struct lm_device *);
- int (*suspend)(struct lm_device *, pm_message_t);
- int (*resume)(struct lm_device *);
-};
-
-int lm_driver_register(struct lm_driver *drv);
-void lm_driver_unregister(struct lm_driver *drv);
-
-int lm_device_register(struct lm_device *dev);
-
-#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
-#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index fedcd2fab094..f4ef41707046 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -51,8 +51,6 @@
#include <asm/param.h> /* HZ */
#include <asm/mach-types.h>
-#include <mach/lm.h>
-
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
@@ -61,6 +59,7 @@
#include "cm.h"
#include "common.h"
#include "pci_v3.h"
+#include "lm.h"
/* Base address to the AP system controller */
void __iomem *ap_syscon_base;
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 0ad5f60598c8..9af1ed995faa 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -32,9 +32,6 @@
#include <mach/platform.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
-
-#include <mach/lm.h>
-
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
diff --git a/arch/arm/mach-integrator/lm.c b/arch/arm/mach-integrator/lm.c
index f52c7af31eaa..3f9e9f043168 100644
--- a/arch/arm/mach-integrator/lm.c
+++ b/arch/arm/mach-integrator/lm.c
@@ -12,7 +12,7 @@
#include <linux/device.h>
#include <linux/slab.h>
-#include <mach/lm.h>
+#include "lm.h"
#define to_lm_device(d) container_of(d, struct lm_device, dev)
#define to_lm_driver(d) container_of(d, struct lm_driver, drv)
diff --git a/arch/arm/mach-integrator/lm.h b/arch/arm/mach-integrator/lm.h
new file mode 100644
index 000000000000..28186b6f2c09
--- /dev/null
+++ b/arch/arm/mach-integrator/lm.h
@@ -0,0 +1,23 @@
+
+struct lm_device {
+ struct device dev;
+ struct resource resource;
+ unsigned int irq;
+ unsigned int id;
+};
+
+struct lm_driver {
+ struct device_driver drv;
+ int (*probe)(struct lm_device *);
+ void (*remove)(struct lm_device *);
+ int (*suspend)(struct lm_device *, pm_message_t);
+ int (*resume)(struct lm_device *);
+};
+
+int lm_driver_register(struct lm_driver *drv);
+void lm_driver_unregister(struct lm_driver *drv);
+
+int lm_device_register(struct lm_device *dev);
+
+#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
+#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
--
1.8.5.3
^ permalink raw reply related
* [PATCH 2/6] ARM: integrator: localize the impd1.h header
From: Linus Walleij @ 2014-02-14 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392373771-17303-1-git-send-email-linus.walleij@linaro.org>
As we move toward multiplatform support for the Integrator family
we need to localize all <mach/*> headers. This moves the impd1.h
header down to the machine folder, copying the the three defines
only used by the clock driver down into the clock driver.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Jonathan Austin <jonathan.austin@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Hi Mike, looking for an ACK on this patch.
---
arch/arm/mach-integrator/impd1.c | 2 +-
arch/arm/mach-integrator/impd1.h | 14 ++++++++++++++
arch/arm/mach-integrator/include/mach/impd1.h | 18 ------------------
drivers/clk/versatile/clk-impd1.c | 6 ++++--
4 files changed, 19 insertions(+), 21 deletions(-)
create mode 100644 arch/arm/mach-integrator/impd1.h
delete mode 100644 arch/arm/mach-integrator/include/mach/impd1.h
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index a90e83fe8776..0e870ea818c4 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -25,9 +25,9 @@
#include <linux/slab.h>
#include <linux/irqchip/arm-vic.h>
-#include <mach/impd1.h>
#include <asm/sizes.h>
#include "lm.h"
+#include "impd1.h"
static int module_id;
diff --git a/arch/arm/mach-integrator/impd1.h b/arch/arm/mach-integrator/impd1.h
new file mode 100644
index 000000000000..76de4dc9bee4
--- /dev/null
+++ b/arch/arm/mach-integrator/impd1.h
@@ -0,0 +1,14 @@
+#define IMPD1_LEDS 0x0c
+#define IMPD1_INT 0x10
+#define IMPD1_SW 0x14
+#define IMPD1_CTRL 0x18
+
+#define IMPD1_CTRL_DISP_LCD (0 << 0)
+#define IMPD1_CTRL_DISP_VGA (1 << 0)
+#define IMPD1_CTRL_DISP_LCD1 (2 << 0)
+#define IMPD1_CTRL_DISP_ENABLE (1 << 2)
+#define IMPD1_CTRL_DISP_MASK (7 << 0)
+
+struct device;
+
+void impd1_tweak_control(struct device *dev, u32 mask, u32 val);
diff --git a/arch/arm/mach-integrator/include/mach/impd1.h b/arch/arm/mach-integrator/include/mach/impd1.h
deleted file mode 100644
index d75de4b14237..000000000000
--- a/arch/arm/mach-integrator/include/mach/impd1.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#define IMPD1_OSC1 0x00
-#define IMPD1_OSC2 0x04
-#define IMPD1_LOCK 0x08
-#define IMPD1_LEDS 0x0c
-#define IMPD1_INT 0x10
-#define IMPD1_SW 0x14
-#define IMPD1_CTRL 0x18
-
-#define IMPD1_CTRL_DISP_LCD (0 << 0)
-#define IMPD1_CTRL_DISP_VGA (1 << 0)
-#define IMPD1_CTRL_DISP_LCD1 (2 << 0)
-#define IMPD1_CTRL_DISP_ENABLE (1 << 2)
-#define IMPD1_CTRL_DISP_MASK (7 << 0)
-
-struct device;
-
-void impd1_tweak_control(struct device *dev, u32 mask, u32 val);
-
diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c
index 6d8b8e1a080a..31b44f025f9e 100644
--- a/drivers/clk/versatile/clk-impd1.c
+++ b/drivers/clk/versatile/clk-impd1.c
@@ -13,10 +13,12 @@
#include <linux/io.h>
#include <linux/platform_data/clk-integrator.h>
-#include <mach/impd1.h>
-
#include "clk-icst.h"
+#define IMPD1_OSC1 0x00
+#define IMPD1_OSC2 0x04
+#define IMPD1_LOCK 0x08
+
struct impd1_clk {
char *vco1name;
struct clk *vco1clk;
--
1.8.5.3
^ permalink raw reply related
* [PATCH 3/6] ARM: integrator: merge platform.h to hardware.h
From: Linus Walleij @ 2014-02-14 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392373771-17303-1-git-send-email-linus.walleij@linaro.org>
There is no need to have the two separate headers <mach/platform.h>
and <mach/hardware.h>, especially since we are now going to make them
local files. There is not one single driver outside the mach-integrator
folder referencing any of the files.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Jonathan Austin <jonathan.austin@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-integrator/core.c | 1 -
arch/arm/mach-integrator/include/mach/hardware.h | 327 ++++++++++++++++++-
arch/arm/mach-integrator/include/mach/platform.h | 382 -----------------------
arch/arm/mach-integrator/integrator_ap.c | 1 -
arch/arm/mach-integrator/integrator_cp.c | 1 -
arch/arm/mach-integrator/leds.c | 1 -
arch/arm/mach-integrator/pci_v3.c | 1 -
7 files changed, 318 insertions(+), 396 deletions(-)
delete mode 100644 arch/arm/mach-integrator/include/mach/platform.h
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 00ddf20ed91b..7a330f541a9d 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -26,7 +26,6 @@
#include <linux/of_address.h>
#include <mach/hardware.h>
-#include <mach/platform.h>
#include <asm/mach-types.h>
#include <asm/mach/time.h>
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h
index 65fed7c0eb84..857ca5f8b9a6 100644
--- a/arch/arm/mach-integrator/include/mach/hardware.h
+++ b/arch/arm/mach-integrator/include/mach/hardware.h
@@ -1,9 +1,7 @@
/*
- * arch/arm/mach-integrator/include/mach/hardware.h
- *
* This file contains the hardware definitions of the Integrator.
*
- * Copyright (C) 1999 ARM Limited.
+ * Copyright (C) 1998-1999 ARM Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,16 +17,14 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
+#ifndef INTEGRATOR_HARDWARE_H
+#define INTEGRATOR_HARDWARE_H
/*
* Where in virtual memory the IO devices (timers, system controllers
* and so on)
*/
-#define IO_BASE 0xF0000000 // VA of IO
+#define IO_BASE 0xF0000000 // VA of IO
#define IO_SIZE 0x0B000000 // How much?
#define IO_START INTEGRATOR_HDR_BASE // PA of IO
@@ -41,5 +37,318 @@
#define __io_address(n) ((void __iomem *)IO_ADDRESS(n))
-#endif
+/*
+ * Integrator memory map
+ */
+#define INTEGRATOR_BOOT_ROM_LO 0x00000000
+#define INTEGRATOR_BOOT_ROM_HI 0x20000000
+#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
+#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
+
+/*
+ * New Core Modules have different amounts of SSRAM, the amount of SSRAM
+ * fitted can be found in HDR_STAT.
+ *
+ * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
+ * the minimum amount of SSRAM fitted on any core module.
+ *
+ * New Core Modules also alias the SSRAM.
+ *
+ */
+#define INTEGRATOR_SSRAM_BASE 0x00000000
+#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
+#define INTEGRATOR_SSRAM_SIZE SZ_256K
+
+#define INTEGRATOR_FLASH_BASE 0x24000000
+#define INTEGRATOR_FLASH_SIZE SZ_32M
+
+#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
+#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
+
+/*
+ * SDRAM is a SIMM therefore the size is not known.
+ */
+#define INTEGRATOR_SDRAM_BASE 0x00040000
+
+#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
+#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
+#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
+#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
+#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
+
+/*
+ * Logic expansion modules
+ *
+ */
+#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
+#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
+#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
+#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
+#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
+
+/*
+ * Integrator header card registers
+ */
+#define INTEGRATOR_HDR_ID_OFFSET 0x00
+#define INTEGRATOR_HDR_PROC_OFFSET 0x04
+#define INTEGRATOR_HDR_OSC_OFFSET 0x08
+#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
+#define INTEGRATOR_HDR_STAT_OFFSET 0x10
+#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
+#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
+#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */
+#define INTEGRATOR_HDR_IC_OFFSET 0x40
+#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
+#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
+
+#define INTEGRATOR_HDR_BASE 0x10000000
+#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
+#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
+#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
+#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
+#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
+#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
+#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
+#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
+#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
+#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
+#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
+
+#define INTEGRATOR_HDR_CTRL_LED 0x01
+#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
+#define INTEGRATOR_HDR_CTRL_REMAP 0x04
+#define INTEGRATOR_HDR_CTRL_RESET 0x08
+#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
+#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
+#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
+#define INTEGRATOR_HDR_CTRL_SYNC 0x80
+
+#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
+#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
+#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
+#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
+#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
+#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
+#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
+#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
+#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
+#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
+#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
+#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
+#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
+#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
+#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
+#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
+#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
+#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
+#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
+#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
+#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
+#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
+#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
+#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
+#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
+#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
+#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
+#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
+#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
+#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
+#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
+#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
+
+#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
+#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
+#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
+#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
+#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
+#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
+#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
+#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
+#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
+#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
+#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
+
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
+#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
+
+#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5)
+
+/*
+ * Integrator system registers
+ */
+
+/*
+ * System Controller
+ */
+#define INTEGRATOR_SC_ID_OFFSET 0x00
+#define INTEGRATOR_SC_OSC_OFFSET 0x04
+#define INTEGRATOR_SC_CTRLS_OFFSET 0x08
+#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
+#define INTEGRATOR_SC_DEC_OFFSET 0x10
+#define INTEGRATOR_SC_ARB_OFFSET 0x14
+#define INTEGRATOR_SC_LOCK_OFFSET 0x1C
+
+#define INTEGRATOR_SC_BASE 0x11000000
+#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
+#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
+#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
+#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
+#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
+#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
+#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
+#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
+
+#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
+#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
+#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
+#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
+#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
+#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
+
+#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
+#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
+#define INTEGRATOR_SC_OSC_PCI_MASK 0x100
+
+#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
+#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1)
+#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2)
+#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4)
+#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5)
+#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
+#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
+
+/*
+ * External Bus Interface
+ */
+#define INTEGRATOR_EBI_BASE 0x12000000
+
+#define INTEGRATOR_EBI_CSR0_OFFSET 0x00
+#define INTEGRATOR_EBI_CSR1_OFFSET 0x04
+#define INTEGRATOR_EBI_CSR2_OFFSET 0x08
+#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
+#define INTEGRATOR_EBI_LOCK_OFFSET 0x20
+
+#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
+#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
+#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
+#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
+#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
+
+#define INTEGRATOR_EBI_8_BIT 0x00
+#define INTEGRATOR_EBI_16_BIT 0x01
+#define INTEGRATOR_EBI_32_BIT 0x02
+#define INTEGRATOR_EBI_WRITE_ENABLE 0x04
+#define INTEGRATOR_EBI_SYNC 0x08
+#define INTEGRATOR_EBI_WS_2 0x00
+#define INTEGRATOR_EBI_WS_3 0x10
+#define INTEGRATOR_EBI_WS_4 0x20
+#define INTEGRATOR_EBI_WS_5 0x30
+#define INTEGRATOR_EBI_WS_6 0x40
+#define INTEGRATOR_EBI_WS_7 0x50
+#define INTEGRATOR_EBI_WS_8 0x60
+#define INTEGRATOR_EBI_WS_9 0x70
+#define INTEGRATOR_EBI_WS_10 0x80
+#define INTEGRATOR_EBI_WS_11 0x90
+#define INTEGRATOR_EBI_WS_12 0xA0
+#define INTEGRATOR_EBI_WS_13 0xB0
+#define INTEGRATOR_EBI_WS_14 0xC0
+#define INTEGRATOR_EBI_WS_15 0xD0
+#define INTEGRATOR_EBI_WS_16 0xE0
+#define INTEGRATOR_EBI_WS_17 0xF0
+
+
+#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */
+#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */
+#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */
+#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */
+#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */
+#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
+#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
+
+/*
+ * LED's & Switches
+ */
+#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
+#define INTEGRATOR_DBG_LEDS_OFFSET 0x04
+#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
+
+#define INTEGRATOR_DBG_BASE 0x1A000000
+#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
+#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
+#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
+
+#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */
+
+#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */
+#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */
+#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */
+#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */
+#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */
+#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
+
+/* PS2 Keyboard interface */
+#define KMI0_BASE INTEGRATOR_KBD_BASE
+
+/* PS2 Mouse interface */
+#define KMI1_BASE INTEGRATOR_MOUSE_BASE
+
+/*
+ * Integrator Interrupt Controllers
+ *
+ *
+ * Offsets from interrupt controller base
+ *
+ * System Controller interrupt controller base is
+ *
+ * INTEGRATOR_IC_BASE + (header_number << 6)
+ *
+ * Core Module interrupt controller base is
+ *
+ * INTEGRATOR_HDR_IC
+ */
+#define IRQ_STATUS 0
+#define IRQ_RAW_STATUS 0x04
+#define IRQ_ENABLE 0x08
+#define IRQ_ENABLE_SET 0x08
+#define IRQ_ENABLE_CLEAR 0x0C
+
+#define INT_SOFT_SET 0x10
+#define INT_SOFT_CLEAR 0x14
+
+#define FIQ_STATUS 0x20
+#define FIQ_RAW_STATUS 0x24
+#define FIQ_ENABLE 0x28
+#define FIQ_ENABLE_SET 0x28
+#define FIQ_ENABLE_CLEAR 0x2C
+
+
+/*
+ * LED's
+ */
+#define GREEN_LED 0x01
+#define YELLOW_LED 0x02
+#define RED_LED 0x04
+#define GREEN_LED_2 0x08
+#define ALL_LEDS 0x0F
+
+#define LED_BANK INTEGRATOR_DBG_LEDS
+
+/*
+ * Timer definitions
+ *
+ * Only use timer 1 & 2
+ * (both run at 24MHz and will need the clock divider set to 16).
+ *
+ * Timer 0 runs at bus frequency
+ */
+#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
+#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
+#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
+
+#define INTEGRATOR_CSR_BASE 0x10000000
+#define INTEGRATOR_CSR_SIZE 0x10000000
+#endif /* INTEGRATOR_HARDWARE_H */
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
deleted file mode 100644
index 306d025d9730..000000000000
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/**************************************************************************
- * * Copyright ? ARM Limited 1998. All rights reserved.
- * ***********************************************************************/
-/* ************************************************************************
- *
- * Integrator address map
- *
- * ***********************************************************************/
-
-#ifndef __address_h
-#define __address_h 1
-
-/* ========================================================================
- * Integrator definitions
- * ========================================================================
- * ------------------------------------------------------------------------
- * Memory definitions
- * ------------------------------------------------------------------------
- * Integrator memory map
- *
- */
-#define INTEGRATOR_BOOT_ROM_LO 0x00000000
-#define INTEGRATOR_BOOT_ROM_HI 0x20000000
-#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
-#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
-
-/*
- * New Core Modules have different amounts of SSRAM, the amount of SSRAM
- * fitted can be found in HDR_STAT.
- *
- * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
- * the minimum amount of SSRAM fitted on any core module.
- *
- * New Core Modules also alias the SSRAM.
- *
- */
-#define INTEGRATOR_SSRAM_BASE 0x00000000
-#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
-#define INTEGRATOR_SSRAM_SIZE SZ_256K
-
-#define INTEGRATOR_FLASH_BASE 0x24000000
-#define INTEGRATOR_FLASH_SIZE SZ_32M
-
-#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
-#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
-
-/*
- * SDRAM is a SIMM therefore the size is not known.
- *
- */
-#define INTEGRATOR_SDRAM_BASE 0x00040000
-
-#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
-#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
-#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
-#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
-#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
-
-/*
- * Logic expansion modules
- *
- */
-#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
-#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
-#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
-#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
-#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
-
-/* ------------------------------------------------------------------------
- * Integrator header card registers
- * ------------------------------------------------------------------------
- *
- */
-#define INTEGRATOR_HDR_ID_OFFSET 0x00
-#define INTEGRATOR_HDR_PROC_OFFSET 0x04
-#define INTEGRATOR_HDR_OSC_OFFSET 0x08
-#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
-#define INTEGRATOR_HDR_STAT_OFFSET 0x10
-#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
-#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
-#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */
-#define INTEGRATOR_HDR_IC_OFFSET 0x40
-#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
-#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
-
-#define INTEGRATOR_HDR_BASE 0x10000000
-#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
-#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
-#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
-#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
-#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
-#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
-#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
-#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
-#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
-#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
-#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
-
-#define INTEGRATOR_HDR_CTRL_LED 0x01
-#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
-#define INTEGRATOR_HDR_CTRL_REMAP 0x04
-#define INTEGRATOR_HDR_CTRL_RESET 0x08
-#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
-#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
-#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
-#define INTEGRATOR_HDR_CTRL_SYNC 0x80
-
-#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
-#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
-#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
-#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
-#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
-#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
-#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
-#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
-#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
-#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
-#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
-#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
-#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
-#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
-#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
-#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
-#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
-#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
-#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
-#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
-#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
-#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
-#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
-#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
-#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
-#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
-#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
-#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
-#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
-#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
-#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
-#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
-
-#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
-#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
-#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
-#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
-#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
-#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
-#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
-#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
-#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
-#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
-#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
-
-#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
-#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
-#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
-#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
-#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
-
-#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5)
-
-
-/* ------------------------------------------------------------------------
- * Integrator system registers
- * ------------------------------------------------------------------------
- *
- */
-
-/*
- * System Controller
- *
- */
-#define INTEGRATOR_SC_ID_OFFSET 0x00
-#define INTEGRATOR_SC_OSC_OFFSET 0x04
-#define INTEGRATOR_SC_CTRLS_OFFSET 0x08
-#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
-#define INTEGRATOR_SC_DEC_OFFSET 0x10
-#define INTEGRATOR_SC_ARB_OFFSET 0x14
-#define INTEGRATOR_SC_LOCK_OFFSET 0x1C
-
-#define INTEGRATOR_SC_BASE 0x11000000
-#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
-#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
-#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
-#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
-#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
-#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
-#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
-#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
-
-#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
-#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
-#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
-#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
-#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
-#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
-
-#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
-#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
-#define INTEGRATOR_SC_OSC_PCI_MASK 0x100
-
-#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
-#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1)
-#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2)
-#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4)
-#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5)
-#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
-#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
-
-/*
- * External Bus Interface
- *
- */
-#define INTEGRATOR_EBI_BASE 0x12000000
-
-#define INTEGRATOR_EBI_CSR0_OFFSET 0x00
-#define INTEGRATOR_EBI_CSR1_OFFSET 0x04
-#define INTEGRATOR_EBI_CSR2_OFFSET 0x08
-#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
-#define INTEGRATOR_EBI_LOCK_OFFSET 0x20
-
-#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
-#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
-#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
-#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
-#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
-
-#define INTEGRATOR_EBI_8_BIT 0x00
-#define INTEGRATOR_EBI_16_BIT 0x01
-#define INTEGRATOR_EBI_32_BIT 0x02
-#define INTEGRATOR_EBI_WRITE_ENABLE 0x04
-#define INTEGRATOR_EBI_SYNC 0x08
-#define INTEGRATOR_EBI_WS_2 0x00
-#define INTEGRATOR_EBI_WS_3 0x10
-#define INTEGRATOR_EBI_WS_4 0x20
-#define INTEGRATOR_EBI_WS_5 0x30
-#define INTEGRATOR_EBI_WS_6 0x40
-#define INTEGRATOR_EBI_WS_7 0x50
-#define INTEGRATOR_EBI_WS_8 0x60
-#define INTEGRATOR_EBI_WS_9 0x70
-#define INTEGRATOR_EBI_WS_10 0x80
-#define INTEGRATOR_EBI_WS_11 0x90
-#define INTEGRATOR_EBI_WS_12 0xA0
-#define INTEGRATOR_EBI_WS_13 0xB0
-#define INTEGRATOR_EBI_WS_14 0xC0
-#define INTEGRATOR_EBI_WS_15 0xD0
-#define INTEGRATOR_EBI_WS_16 0xE0
-#define INTEGRATOR_EBI_WS_17 0xF0
-
-
-#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */
-#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */
-#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */
-#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */
-#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */
-#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
-#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
-
-/*
- * LED's & Switches
- *
- */
-#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
-#define INTEGRATOR_DBG_LEDS_OFFSET 0x04
-#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
-
-#define INTEGRATOR_DBG_BASE 0x1A000000
-#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
-#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
-#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
-
-#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */
-
-#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */
-#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */
-#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */
-#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */
-#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */
-#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
-
-/* ------------------------------------------------------------------------
- * KMI keyboard/mouse definitions
- * ------------------------------------------------------------------------
- */
-/* PS2 Keyboard interface */
-#define KMI0_BASE INTEGRATOR_KBD_BASE
-
-/* PS2 Mouse interface */
-#define KMI1_BASE INTEGRATOR_MOUSE_BASE
-
-/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
-
-/* ------------------------------------------------------------------------
- * Integrator Interrupt Controllers
- * ------------------------------------------------------------------------
- *
- * Offsets from interrupt controller base
- *
- * System Controller interrupt controller base is
- *
- * INTEGRATOR_IC_BASE + (header_number << 6)
- *
- * Core Module interrupt controller base is
- *
- * INTEGRATOR_HDR_IC
- *
- */
-#define IRQ_STATUS 0
-#define IRQ_RAW_STATUS 0x04
-#define IRQ_ENABLE 0x08
-#define IRQ_ENABLE_SET 0x08
-#define IRQ_ENABLE_CLEAR 0x0C
-
-#define INT_SOFT_SET 0x10
-#define INT_SOFT_CLEAR 0x14
-
-#define FIQ_STATUS 0x20
-#define FIQ_RAW_STATUS 0x24
-#define FIQ_ENABLE 0x28
-#define FIQ_ENABLE_SET 0x28
-#define FIQ_ENABLE_CLEAR 0x2C
-
-
-/* ------------------------------------------------------------------------
- * Interrupts
- * ------------------------------------------------------------------------
- *
- *
- * Each Core Module has two interrupts controllers, one on the core module
- * itself and one in the system controller on the motherboard. The
- * READ_INT macro in target.s reads both interrupt controllers and returns
- * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
- * and bits 24 to 31 are from the core module.
- *
- * The following definitions relate to the bitmask returned by READ_INT.
- *
- */
-
-/* ------------------------------------------------------------------------
- * LED's
- * ------------------------------------------------------------------------
- *
- */
-#define GREEN_LED 0x01
-#define YELLOW_LED 0x02
-#define RED_LED 0x04
-#define GREEN_LED_2 0x08
-#define ALL_LEDS 0x0F
-
-#define LED_BANK INTEGRATOR_DBG_LEDS
-
-/*
- * Timer definitions
- *
- * Only use timer 1 & 2
- * (both run at 24MHz and will need the clock divider set to 16).
- *
- * Timer 0 runs@bus frequency
- */
-
-#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
-#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
-#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
-
-#define INTEGRATOR_CSR_BASE 0x10000000
-#define INTEGRATOR_CSR_SIZE 0x10000000
-
-#endif
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index f4ef41707046..33d62de18a95 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -45,7 +45,6 @@
#include <linux/clk-provider.h>
#include <mach/hardware.h>
-#include <mach/platform.h>
#include <asm/hardware/arm_timer.h>
#include <asm/setup.h>
#include <asm/param.h> /* HZ */
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 9af1ed995faa..6734a4efe710 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -29,7 +29,6 @@
#include <linux/sys_soc.h>
#include <mach/hardware.h>
-#include <mach/platform.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index cb6ac58f5e07..e2b1b3a4c5d3 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -12,7 +12,6 @@
#include <linux/leds.h>
#include <mach/hardware.h>
-#include <mach/platform.h>
#include "cm.h"
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index c5e01b24d9fb..27d88afc4e2a 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -35,7 +35,6 @@
#include <video/vga.h>
#include <mach/hardware.h>
-#include <mach/platform.h>
#include <asm/mach/map.h>
#include <asm/signal.h>
--
1.8.5.3
^ permalink raw reply related
* [PATCH 4/6] ARM: integrator: localize the hardware.h header
From: Linus Walleij @ 2014-02-14 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392373771-17303-1-git-send-email-linus.walleij@linaro.org>
As we move toward multiplatform support for the Integrator family
we need to localize all <mach/*> headers. This moves the hardware.h
header down to the machine folder. There are no users outside the
machine in the kernel.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Jonathan Austin <jonathan.austin@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-integrator/core.c | 3 +-
arch/arm/mach-integrator/hardware.h | 354 +++++++++++++++++++++++
arch/arm/mach-integrator/include/mach/hardware.h | 354 -----------------------
arch/arm/mach-integrator/integrator_ap.c | 2 +-
arch/arm/mach-integrator/integrator_cp.c | 2 +-
arch/arm/mach-integrator/leds.c | 3 +-
arch/arm/mach-integrator/pci_v3.c | 3 +-
7 files changed, 359 insertions(+), 362 deletions(-)
create mode 100644 arch/arm/mach-integrator/hardware.h
delete mode 100644 arch/arm/mach-integrator/include/mach/hardware.h
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 7a330f541a9d..e3f3aca43efb 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -25,12 +25,11 @@
#include <linux/of.h>
#include <linux/of_address.h>
-#include <mach/hardware.h>
-
#include <asm/mach-types.h>
#include <asm/mach/time.h>
#include <asm/pgtable.h>
+#include "hardware.h"
#include "cm.h"
#include "common.h"
diff --git a/arch/arm/mach-integrator/hardware.h b/arch/arm/mach-integrator/hardware.h
new file mode 100644
index 000000000000..857ca5f8b9a6
--- /dev/null
+++ b/arch/arm/mach-integrator/hardware.h
@@ -0,0 +1,354 @@
+/*
+ * This file contains the hardware definitions of the Integrator.
+ *
+ * Copyright (C) 1998-1999 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef INTEGRATOR_HARDWARE_H
+#define INTEGRATOR_HARDWARE_H
+
+/*
+ * Where in virtual memory the IO devices (timers, system controllers
+ * and so on)
+ */
+#define IO_BASE 0xF0000000 // VA of IO
+#define IO_SIZE 0x0B000000 // How much?
+#define IO_START INTEGRATOR_HDR_BASE // PA of IO
+
+/* macro to get at IO space when running virtually */
+#ifdef CONFIG_MMU
+#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
+#else
+#define IO_ADDRESS(x) (x)
+#endif
+
+#define __io_address(n) ((void __iomem *)IO_ADDRESS(n))
+
+/*
+ * Integrator memory map
+ */
+#define INTEGRATOR_BOOT_ROM_LO 0x00000000
+#define INTEGRATOR_BOOT_ROM_HI 0x20000000
+#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
+#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
+
+/*
+ * New Core Modules have different amounts of SSRAM, the amount of SSRAM
+ * fitted can be found in HDR_STAT.
+ *
+ * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
+ * the minimum amount of SSRAM fitted on any core module.
+ *
+ * New Core Modules also alias the SSRAM.
+ *
+ */
+#define INTEGRATOR_SSRAM_BASE 0x00000000
+#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
+#define INTEGRATOR_SSRAM_SIZE SZ_256K
+
+#define INTEGRATOR_FLASH_BASE 0x24000000
+#define INTEGRATOR_FLASH_SIZE SZ_32M
+
+#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
+#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
+
+/*
+ * SDRAM is a SIMM therefore the size is not known.
+ */
+#define INTEGRATOR_SDRAM_BASE 0x00040000
+
+#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
+#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
+#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
+#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
+#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
+
+/*
+ * Logic expansion modules
+ *
+ */
+#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
+#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
+#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
+#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
+#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
+
+/*
+ * Integrator header card registers
+ */
+#define INTEGRATOR_HDR_ID_OFFSET 0x00
+#define INTEGRATOR_HDR_PROC_OFFSET 0x04
+#define INTEGRATOR_HDR_OSC_OFFSET 0x08
+#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
+#define INTEGRATOR_HDR_STAT_OFFSET 0x10
+#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
+#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
+#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */
+#define INTEGRATOR_HDR_IC_OFFSET 0x40
+#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
+#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
+
+#define INTEGRATOR_HDR_BASE 0x10000000
+#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
+#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
+#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
+#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
+#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
+#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
+#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
+#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
+#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
+#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
+#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
+
+#define INTEGRATOR_HDR_CTRL_LED 0x01
+#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
+#define INTEGRATOR_HDR_CTRL_REMAP 0x04
+#define INTEGRATOR_HDR_CTRL_RESET 0x08
+#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
+#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
+#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
+#define INTEGRATOR_HDR_CTRL_SYNC 0x80
+
+#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
+#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
+#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
+#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
+#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
+#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
+#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
+#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
+#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
+#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
+#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
+#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
+#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
+#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
+#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
+#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
+#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
+#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
+#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
+#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
+#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
+#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
+#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
+#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
+#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
+#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
+#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
+#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
+#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
+#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
+#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
+#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
+
+#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
+#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
+#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
+#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
+#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
+#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
+#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
+#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
+#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
+#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
+#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
+
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
+#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
+
+#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5)
+
+/*
+ * Integrator system registers
+ */
+
+/*
+ * System Controller
+ */
+#define INTEGRATOR_SC_ID_OFFSET 0x00
+#define INTEGRATOR_SC_OSC_OFFSET 0x04
+#define INTEGRATOR_SC_CTRLS_OFFSET 0x08
+#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
+#define INTEGRATOR_SC_DEC_OFFSET 0x10
+#define INTEGRATOR_SC_ARB_OFFSET 0x14
+#define INTEGRATOR_SC_LOCK_OFFSET 0x1C
+
+#define INTEGRATOR_SC_BASE 0x11000000
+#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
+#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
+#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
+#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
+#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
+#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
+#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
+#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
+
+#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
+#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
+#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
+#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
+#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
+#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
+
+#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
+#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
+#define INTEGRATOR_SC_OSC_PCI_MASK 0x100
+
+#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
+#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1)
+#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2)
+#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4)
+#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5)
+#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
+#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
+
+/*
+ * External Bus Interface
+ */
+#define INTEGRATOR_EBI_BASE 0x12000000
+
+#define INTEGRATOR_EBI_CSR0_OFFSET 0x00
+#define INTEGRATOR_EBI_CSR1_OFFSET 0x04
+#define INTEGRATOR_EBI_CSR2_OFFSET 0x08
+#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
+#define INTEGRATOR_EBI_LOCK_OFFSET 0x20
+
+#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
+#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
+#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
+#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
+#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
+
+#define INTEGRATOR_EBI_8_BIT 0x00
+#define INTEGRATOR_EBI_16_BIT 0x01
+#define INTEGRATOR_EBI_32_BIT 0x02
+#define INTEGRATOR_EBI_WRITE_ENABLE 0x04
+#define INTEGRATOR_EBI_SYNC 0x08
+#define INTEGRATOR_EBI_WS_2 0x00
+#define INTEGRATOR_EBI_WS_3 0x10
+#define INTEGRATOR_EBI_WS_4 0x20
+#define INTEGRATOR_EBI_WS_5 0x30
+#define INTEGRATOR_EBI_WS_6 0x40
+#define INTEGRATOR_EBI_WS_7 0x50
+#define INTEGRATOR_EBI_WS_8 0x60
+#define INTEGRATOR_EBI_WS_9 0x70
+#define INTEGRATOR_EBI_WS_10 0x80
+#define INTEGRATOR_EBI_WS_11 0x90
+#define INTEGRATOR_EBI_WS_12 0xA0
+#define INTEGRATOR_EBI_WS_13 0xB0
+#define INTEGRATOR_EBI_WS_14 0xC0
+#define INTEGRATOR_EBI_WS_15 0xD0
+#define INTEGRATOR_EBI_WS_16 0xE0
+#define INTEGRATOR_EBI_WS_17 0xF0
+
+
+#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */
+#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */
+#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */
+#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */
+#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */
+#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
+#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
+
+/*
+ * LED's & Switches
+ */
+#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
+#define INTEGRATOR_DBG_LEDS_OFFSET 0x04
+#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
+
+#define INTEGRATOR_DBG_BASE 0x1A000000
+#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
+#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
+#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
+
+#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */
+
+#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */
+#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */
+#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */
+#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */
+#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */
+#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
+
+/* PS2 Keyboard interface */
+#define KMI0_BASE INTEGRATOR_KBD_BASE
+
+/* PS2 Mouse interface */
+#define KMI1_BASE INTEGRATOR_MOUSE_BASE
+
+/*
+ * Integrator Interrupt Controllers
+ *
+ *
+ * Offsets from interrupt controller base
+ *
+ * System Controller interrupt controller base is
+ *
+ * INTEGRATOR_IC_BASE + (header_number << 6)
+ *
+ * Core Module interrupt controller base is
+ *
+ * INTEGRATOR_HDR_IC
+ */
+#define IRQ_STATUS 0
+#define IRQ_RAW_STATUS 0x04
+#define IRQ_ENABLE 0x08
+#define IRQ_ENABLE_SET 0x08
+#define IRQ_ENABLE_CLEAR 0x0C
+
+#define INT_SOFT_SET 0x10
+#define INT_SOFT_CLEAR 0x14
+
+#define FIQ_STATUS 0x20
+#define FIQ_RAW_STATUS 0x24
+#define FIQ_ENABLE 0x28
+#define FIQ_ENABLE_SET 0x28
+#define FIQ_ENABLE_CLEAR 0x2C
+
+
+/*
+ * LED's
+ */
+#define GREEN_LED 0x01
+#define YELLOW_LED 0x02
+#define RED_LED 0x04
+#define GREEN_LED_2 0x08
+#define ALL_LEDS 0x0F
+
+#define LED_BANK INTEGRATOR_DBG_LEDS
+
+/*
+ * Timer definitions
+ *
+ * Only use timer 1 & 2
+ * (both run at 24MHz and will need the clock divider set to 16).
+ *
+ * Timer 0 runs at bus frequency
+ */
+#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
+#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
+#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
+
+#define INTEGRATOR_CSR_BASE 0x10000000
+#define INTEGRATOR_CSR_SIZE 0x10000000
+
+#endif /* INTEGRATOR_HARDWARE_H */
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h
deleted file mode 100644
index 857ca5f8b9a6..000000000000
--- a/arch/arm/mach-integrator/include/mach/hardware.h
+++ /dev/null
@@ -1,354 +0,0 @@
-/*
- * This file contains the hardware definitions of the Integrator.
- *
- * Copyright (C) 1998-1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef INTEGRATOR_HARDWARE_H
-#define INTEGRATOR_HARDWARE_H
-
-/*
- * Where in virtual memory the IO devices (timers, system controllers
- * and so on)
- */
-#define IO_BASE 0xF0000000 // VA of IO
-#define IO_SIZE 0x0B000000 // How much?
-#define IO_START INTEGRATOR_HDR_BASE // PA of IO
-
-/* macro to get@IO space when running virtually */
-#ifdef CONFIG_MMU
-#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
-#else
-#define IO_ADDRESS(x) (x)
-#endif
-
-#define __io_address(n) ((void __iomem *)IO_ADDRESS(n))
-
-/*
- * Integrator memory map
- */
-#define INTEGRATOR_BOOT_ROM_LO 0x00000000
-#define INTEGRATOR_BOOT_ROM_HI 0x20000000
-#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
-#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
-
-/*
- * New Core Modules have different amounts of SSRAM, the amount of SSRAM
- * fitted can be found in HDR_STAT.
- *
- * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
- * the minimum amount of SSRAM fitted on any core module.
- *
- * New Core Modules also alias the SSRAM.
- *
- */
-#define INTEGRATOR_SSRAM_BASE 0x00000000
-#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
-#define INTEGRATOR_SSRAM_SIZE SZ_256K
-
-#define INTEGRATOR_FLASH_BASE 0x24000000
-#define INTEGRATOR_FLASH_SIZE SZ_32M
-
-#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
-#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
-
-/*
- * SDRAM is a SIMM therefore the size is not known.
- */
-#define INTEGRATOR_SDRAM_BASE 0x00040000
-
-#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
-#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
-#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
-#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
-#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
-
-/*
- * Logic expansion modules
- *
- */
-#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
-#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
-#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
-#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
-#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
-
-/*
- * Integrator header card registers
- */
-#define INTEGRATOR_HDR_ID_OFFSET 0x00
-#define INTEGRATOR_HDR_PROC_OFFSET 0x04
-#define INTEGRATOR_HDR_OSC_OFFSET 0x08
-#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
-#define INTEGRATOR_HDR_STAT_OFFSET 0x10
-#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
-#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
-#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */
-#define INTEGRATOR_HDR_IC_OFFSET 0x40
-#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
-#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
-
-#define INTEGRATOR_HDR_BASE 0x10000000
-#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
-#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
-#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
-#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
-#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
-#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
-#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
-#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
-#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
-#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
-#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
-
-#define INTEGRATOR_HDR_CTRL_LED 0x01
-#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
-#define INTEGRATOR_HDR_CTRL_REMAP 0x04
-#define INTEGRATOR_HDR_CTRL_RESET 0x08
-#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
-#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
-#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
-#define INTEGRATOR_HDR_CTRL_SYNC 0x80
-
-#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
-#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
-#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
-#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
-#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
-#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
-#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
-#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
-#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
-#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
-#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
-#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
-#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
-#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
-#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
-#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
-#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
-#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
-#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
-#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
-#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
-#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
-#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
-#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
-#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
-#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
-#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
-#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
-#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
-#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
-#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
-#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
-
-#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
-#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
-#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
-#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
-#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
-#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
-#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
-#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
-#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
-#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
-#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
-
-#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
-#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
-#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
-#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
-#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
-
-#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5)
-
-/*
- * Integrator system registers
- */
-
-/*
- * System Controller
- */
-#define INTEGRATOR_SC_ID_OFFSET 0x00
-#define INTEGRATOR_SC_OSC_OFFSET 0x04
-#define INTEGRATOR_SC_CTRLS_OFFSET 0x08
-#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
-#define INTEGRATOR_SC_DEC_OFFSET 0x10
-#define INTEGRATOR_SC_ARB_OFFSET 0x14
-#define INTEGRATOR_SC_LOCK_OFFSET 0x1C
-
-#define INTEGRATOR_SC_BASE 0x11000000
-#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
-#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
-#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
-#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
-#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
-#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
-#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
-#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
-
-#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
-#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
-#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
-#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
-#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
-#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
-
-#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
-#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
-#define INTEGRATOR_SC_OSC_PCI_MASK 0x100
-
-#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
-#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1)
-#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2)
-#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4)
-#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5)
-#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
-#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
-
-/*
- * External Bus Interface
- */
-#define INTEGRATOR_EBI_BASE 0x12000000
-
-#define INTEGRATOR_EBI_CSR0_OFFSET 0x00
-#define INTEGRATOR_EBI_CSR1_OFFSET 0x04
-#define INTEGRATOR_EBI_CSR2_OFFSET 0x08
-#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
-#define INTEGRATOR_EBI_LOCK_OFFSET 0x20
-
-#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
-#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
-#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
-#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
-#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
-
-#define INTEGRATOR_EBI_8_BIT 0x00
-#define INTEGRATOR_EBI_16_BIT 0x01
-#define INTEGRATOR_EBI_32_BIT 0x02
-#define INTEGRATOR_EBI_WRITE_ENABLE 0x04
-#define INTEGRATOR_EBI_SYNC 0x08
-#define INTEGRATOR_EBI_WS_2 0x00
-#define INTEGRATOR_EBI_WS_3 0x10
-#define INTEGRATOR_EBI_WS_4 0x20
-#define INTEGRATOR_EBI_WS_5 0x30
-#define INTEGRATOR_EBI_WS_6 0x40
-#define INTEGRATOR_EBI_WS_7 0x50
-#define INTEGRATOR_EBI_WS_8 0x60
-#define INTEGRATOR_EBI_WS_9 0x70
-#define INTEGRATOR_EBI_WS_10 0x80
-#define INTEGRATOR_EBI_WS_11 0x90
-#define INTEGRATOR_EBI_WS_12 0xA0
-#define INTEGRATOR_EBI_WS_13 0xB0
-#define INTEGRATOR_EBI_WS_14 0xC0
-#define INTEGRATOR_EBI_WS_15 0xD0
-#define INTEGRATOR_EBI_WS_16 0xE0
-#define INTEGRATOR_EBI_WS_17 0xF0
-
-
-#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */
-#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */
-#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */
-#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */
-#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */
-#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
-#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
-
-/*
- * LED's & Switches
- */
-#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
-#define INTEGRATOR_DBG_LEDS_OFFSET 0x04
-#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
-
-#define INTEGRATOR_DBG_BASE 0x1A000000
-#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
-#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
-#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
-
-#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */
-
-#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */
-#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */
-#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */
-#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */
-#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */
-#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
-
-/* PS2 Keyboard interface */
-#define KMI0_BASE INTEGRATOR_KBD_BASE
-
-/* PS2 Mouse interface */
-#define KMI1_BASE INTEGRATOR_MOUSE_BASE
-
-/*
- * Integrator Interrupt Controllers
- *
- *
- * Offsets from interrupt controller base
- *
- * System Controller interrupt controller base is
- *
- * INTEGRATOR_IC_BASE + (header_number << 6)
- *
- * Core Module interrupt controller base is
- *
- * INTEGRATOR_HDR_IC
- */
-#define IRQ_STATUS 0
-#define IRQ_RAW_STATUS 0x04
-#define IRQ_ENABLE 0x08
-#define IRQ_ENABLE_SET 0x08
-#define IRQ_ENABLE_CLEAR 0x0C
-
-#define INT_SOFT_SET 0x10
-#define INT_SOFT_CLEAR 0x14
-
-#define FIQ_STATUS 0x20
-#define FIQ_RAW_STATUS 0x24
-#define FIQ_ENABLE 0x28
-#define FIQ_ENABLE_SET 0x28
-#define FIQ_ENABLE_CLEAR 0x2C
-
-
-/*
- * LED's
- */
-#define GREEN_LED 0x01
-#define YELLOW_LED 0x02
-#define RED_LED 0x04
-#define GREEN_LED_2 0x08
-#define ALL_LEDS 0x0F
-
-#define LED_BANK INTEGRATOR_DBG_LEDS
-
-/*
- * Timer definitions
- *
- * Only use timer 1 & 2
- * (both run at 24MHz and will need the clock divider set to 16).
- *
- * Timer 0 runs@bus frequency
- */
-#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
-#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
-#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
-
-#define INTEGRATOR_CSR_BASE 0x10000000
-#define INTEGRATOR_CSR_SIZE 0x10000000
-
-#endif /* INTEGRATOR_HARDWARE_H */
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 33d62de18a95..9d5d6386aaee 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -44,7 +44,6 @@
#include <linux/sched_clock.h>
#include <linux/clk-provider.h>
-#include <mach/hardware.h>
#include <asm/hardware/arm_timer.h>
#include <asm/setup.h>
#include <asm/param.h> /* HZ */
@@ -55,6 +54,7 @@
#include <asm/mach/map.h>
#include <asm/mach/time.h>
+#include "hardware.h"
#include "cm.h"
#include "common.h"
#include "pci_v3.h"
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 6734a4efe710..c97ab88897cf 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -28,7 +28,6 @@
#include <linux/of_platform.h>
#include <linux/sys_soc.h>
-#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -39,6 +38,7 @@
#include <plat/clcd.h>
#include <plat/sched_clock.h>
+#include "hardware.h"
#include "cm.h"
#include "common.h"
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index e2b1b3a4c5d3..f1dcb57a59e2 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -11,8 +11,7 @@
#include <linux/slab.h>
#include <linux/leds.h>
-#include <mach/hardware.h>
-
+#include "hardware.h"
#include "cm.h"
#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 27d88afc4e2a..05e1f73a1e8d 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -34,14 +34,13 @@
#include <linux/of_pci.h>
#include <video/vga.h>
-#include <mach/hardware.h>
-
#include <asm/mach/map.h>
#include <asm/signal.h>
#include <asm/mach/pci.h>
#include <asm/irq_regs.h>
#include "pci_v3.h"
+#include "hardware.h"
/*
* Where in the memory map does PCI live?
--
1.8.5.3
^ permalink raw reply related
* [PATCH 5/6] ARM: integrator: register sched_clock directly
From: Linus Walleij @ 2014-02-14 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392373771-17303-1-git-send-email-linus.walleij@linaro.org>
The detour through plat-versatile/sched-clock.c is hard to migrate
to multiplatform set-up and it's very little code being duplicated
so let's just inline the sched_clock registration and cut one more
dependency to plat-versatile.
This also makes this sched_clock implementation compulsory.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Jonathan Austin <jonathan.austin@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-integrator/integrator_cp.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index c97ab88897cf..a938242b0c95 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -27,6 +27,7 @@
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/sys_soc.h>
+#include <linux/sched_clock.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
@@ -36,7 +37,6 @@
#include <asm/mach/time.h>
#include <plat/clcd.h>
-#include <plat/sched_clock.h>
#include "hardware.h"
#include "cm.h"
@@ -225,11 +225,14 @@ static struct clcd_board clcd_data = {
#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
+static u64 notrace intcp_read_sched_clock(void)
+{
+ return readl(REFCOUNTER);
+}
+
static void __init intcp_init_early(void)
{
-#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
- versatile_sched_clock_init(REFCOUNTER, 24000000);
-#endif
+ sched_clock_register(intcp_read_sched_clock, 32, 24000000);
}
static const struct of_device_id fpga_irq_of_match[] __initconst = {
--
1.8.5.3
^ permalink raw reply related
* [PATCH 6/6] RFC: ARM: integrator: get rid of <mach/memory.h>
From: Linus Walleij @ 2014-02-14 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392373771-17303-1-git-send-email-linus.walleij@linaro.org>
The Integrator has a custom <mach/memory.h> header defining the
BUS_OFFSET for *_to_bus and bus_to_* operations as offset from
0x80000000.
I have searched the documentation and cannot find any clue to
this set-up. The Integrators have no intrinsic DMA engine(s)
that need to perform any bus translations. The only thing I can
think of is the PCIv3 host found in the Integrator/AP. After
searching its documentation I cannot find any hint whatsoever
saying that it would perform DMA operations to memory offset
to 0x80000000. The PCIv3 driver does not configure anything
for DMA, and the hardware contains registers to configure
the local (CPU) side address translation. When I dump the
default values of these registers (the Linux driver does not
touch them) they contain zeroes meaning a 1-to-1 mapping to
the bus.
So patch the mapping to use the kernel default.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Jonathan Austin <jonathan.austin@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Admittedly I'm not certain about how DMA works in PCI scenarios
(only experienced with DMA engines) so some input here would be
appreciated. Like if DMA support is compulory for PCI hosts or
if it's somehow even unused on the PCIv3. And if someone has
ever tested some DMA:ing PCI card on this machine.
---
arch/arm/Kconfig | 1 -
arch/arm/mach-integrator/include/mach/memory.h | 34 --------------------------
2 files changed, 35 deletions(-)
delete mode 100644 arch/arm/mach-integrator/include/mach/memory.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e25419817791..c4094131314e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -325,7 +325,6 @@ config ARCH_INTEGRATOR
select HAVE_TCM
select ICST
select MULTI_IRQ_HANDLER
- select NEED_MACH_MEMORY_H
select PLAT_VERSATILE
select SPARSE_IRQ
select USE_OF
diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h
deleted file mode 100644
index 334d5e271889..000000000000
--- a/arch/arm/mach-integrator/include/mach/memory.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * arch/arm/mach-integrator/include/mach/memory.h
- *
- * Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PLAT_PHYS_OFFSET UL(0x00000000)
-
-#define BUS_OFFSET UL(0x80000000)
-#define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET)
-#define __bus_to_virt(x) ((x) - BUS_OFFSET + PAGE_OFFSET)
-#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET))
-#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET))
-
-#endif
--
1.8.5.3
^ permalink raw reply related
* [PATCH v3] input: sirfsoc-onkey - report onkey untouch event by detecting pin status
From: Xianglong Du @ 2014-02-14 10:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGsJ_4xqnZAO6vpkgTEHmfp9+nbWa1qwQ4pda6B2sSrEtbV3ZA@mail.gmail.com>
Tested-by: Xianglong Du <Xianglong.Du@csr.com>
________________________________________
From: Barry Song [21cnbao at gmail.com]
Sent: Friday, February 14, 2014 16:49
To: Dmitry Torokhov
Cc: linux-input at vger.kernel.org; linux-arm-kernel at lists.infradead.org; DL-SHA-WorkGroupLinux; Xianglong Du; Rongjun Ying; Barry Song
Subject: Re: [PATCH v3] input: sirfsoc-onkey - report onkey untouch event by detecting pin status
2014-02-14 15:57 GMT+08:00 Dmitry Torokhov <dmitry.torokhov@gmail.com>:
> Hi Barry,
>
> On Fri, Feb 14, 2014 at 11:20:01AM +0800, Barry Song wrote:
>> From: Xianglong Du <Xianglong.Du@csr.com>
>>
>> this patch adds a delayed_work to detect the untouch of onkey since HW will
>> not generate interrupt for it.
>>
>> at the same time, we move the KEY event to POWER instead of SUSPEND, which
>> will be suitable for both Android and Linux. Userspace PowerManager Daemon
>> will decide to suspend or shutdown based on how long we have touched onkey
>>
>> Signed-off-by: Xianglong Du <Xianglong.Du@csr.com>
>> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com>
>> Signed-off-by: Barry Song <Baohua.Song@csr.com>
>> ---
>> -v3: move to use custom devres action
>
> Thank you for making the changes, however it seems that we can control
> whether the device generates interrupts or not and so we can implement
> open and close methods. If patch below works then your
> cancel_delayed_work() call should go into sirfosc_pwrc_close() and we do
> not need to use devm_free_irq() not custom action.
this one looks making lots of senses. it makes sure HW will not
trigger any SW behaviour before probe() finishes, and also makes sure
HW will not trigger any SW behaviour in remove(). i'd like xianglong
to give a quick test on it.
>
> Thanks.
>
> --
> Dmitry
>
>
> Input: sirfsoc-onkey - implement open and close methods
>
> From: Dmitry Torokhov <dmitry.torokhov@gmail.com>
>
> We can control whetehr device generates interrupts or not so let's
> implement open and close methods of input device so that we do not do any
> processing until there are users.
>
> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
> ---
> drivers/input/misc/sirfsoc-onkey.c | 50 +++++++++++++++++++++++++++++-------
> 1 file changed, 40 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/input/misc/sirfsoc-onkey.c b/drivers/input/misc/sirfsoc-onkey.c
> index e8897c3..dc7db65 100644
> --- a/drivers/input/misc/sirfsoc-onkey.c
> +++ b/drivers/input/misc/sirfsoc-onkey.c
> @@ -49,6 +49,35 @@ static irqreturn_t sirfsoc_pwrc_isr(int irq, void *dev_id)
> return IRQ_HANDLED;
> }
>
> +static void sirfsoc_pwrc_toggle_interrupts(struct sirfsoc_pwrc_drvdata *pwrcdrv,
> + bool enable)
> +{
> + u32 int_mask;
> +
> + int_mask = sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK);
> + if (enable)
> + int_mask |= PWRC_ON_KEY_BIT;
> + else
> + int_mask &= ~PWRC_ON_KEY_BIT;
> + sirfsoc_rtc_iobrg_writel(int_mask, pwrcdrv->pwrc_base + PWRC_INT_MASK);
> +}
> +
> +static int sirfsoc_pwrc_open(struct input_dev *input)
> +{
> + struct sirfsoc_pwrc_drvdata *pwrcdrv = input_get_drvdata(input);
> +
> + sirfsoc_pwrc_toggle_interrupts(pwrcdrv, true);
> +
> + return 0;
> +}
> +
> +static void sirfsoc_pwrc_close(struct input_dev *input)
> +{
> + struct sirfsoc_pwrc_drvdata *pwrcdrv = input_get_drvdata(input);
> +
> + sirfsoc_pwrc_toggle_interrupts(pwrcdrv, false);
> +}
> +
> static const struct of_device_id sirfsoc_pwrc_of_match[] = {
> { .compatible = "sirf,prima2-pwrc" },
> {},
> @@ -70,7 +99,7 @@ static int sirfsoc_pwrc_probe(struct platform_device *pdev)
> }
>
> /*
> - * we can't use of_iomap because pwrc is not mapped in memory,
> + * We can't use of_iomap because pwrc is not mapped in memory,
> * the so-called base address is only offset in rtciobrg
> */
> error = of_property_read_u32(np, "reg", &pwrcdrv->pwrc_base);
> @@ -88,6 +117,11 @@ static int sirfsoc_pwrc_probe(struct platform_device *pdev)
> pwrcdrv->input->phys = "pwrc/input0";
> pwrcdrv->input->evbit[0] = BIT_MASK(EV_PWR);
>
> + pwrcdrv->input->open = sirfsoc_pwrc_open;
> + pwrcdrv->input->close = sirfsoc_pwrc_close;
> +
> + input_set_drvdata(pwrcdrv->input, pwrcdrv);
> +
> irq = platform_get_irq(pdev, 0);
> error = devm_request_irq(&pdev->dev, irq,
> sirfsoc_pwrc_isr, IRQF_SHARED,
> @@ -98,11 +132,6 @@ static int sirfsoc_pwrc_probe(struct platform_device *pdev)
> return error;
> }
>
> - sirfsoc_rtc_iobrg_writel(
> - sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK) |
> - PWRC_ON_KEY_BIT,
> - pwrcdrv->pwrc_base + PWRC_INT_MASK);
> -
> error = input_register_device(pwrcdrv->input);
> if (error) {
> dev_err(&pdev->dev,
> @@ -129,15 +158,16 @@ static int pwrc_resume(struct device *dev)
> {
> struct platform_device *pdev = to_platform_device(dev);
> struct sirfsoc_pwrc_drvdata *pwrcdrv = platform_get_drvdata(pdev);
> + struct input_dev *input = pwrcdrv->input;
>
> /*
> * Do not mask pwrc interrupt as we want pwrc work as a wakeup source
> * if users touch X_ONKEY_B, see arch/arm/mach-prima2/pm.c
> */
> - sirfsoc_rtc_iobrg_writel(
> - sirfsoc_rtc_iobrg_readl(
> - pwrcdrv->pwrc_base + PWRC_INT_MASK) | PWRC_ON_KEY_BIT,
> - pwrcdrv->pwrc_base + PWRC_INT_MASK);
> + mutex_lock(&input->mutex);
> + if (input->users)
> + sirfsoc_pwrc_toggle_interrupts(pwrcdrv, true);
> + mutex_unlock(&input->mutex);
>
> return 0;
> }
-barry
To report this email as spam click https://www.mailcontrol.com/sr/MZbqvYs5QwJvpeaetUwhCQ== .
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Keep up to date with CSR on our technical blog, www.csr.com/blog, CSR people blog, www.csr.com/people, YouTube, www.youtube.com/user/CSRplc, Facebook, www.facebook.com/pages/CSR/191038434253534, or follow us on Twitter at www.twitter.com/CSR_plc.
New for 2014, you can now access the wide range of products powered by aptX at www.aptx.com.
^ permalink raw reply
* [PATCH 1/2] clk: fixed-rate: use full DT node name
From: Mark Rutland @ 2014-02-14 10:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392358613-19962-1-git-send-email-swarren@wwwdotorg.org>
On Fri, Feb 14, 2014 at 06:16:52AM +0000, Stephen Warren wrote:
> clk-fixed-rate currently names clocks according to a node's name without
> the unit address. When faced with the legal and technically correct DT
> structure below, this causes rgistration attempts for 3 clocks with the
> same name, 2 of which fail.
>
> clocks {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <0>;
>
> clk_mmc: clock at 0 {
> compatible = "fixed-clock";
> reg = <0>;
> ...
> clk_i2c: clock at 1 {
> compatible = "fixed-clock";
> reg = <1>;
> ...
> clk_spi: clock at 2 {
> compatible = "fixed-clock";
> reg = <2>;
> ...
I'd argue that this case isn't valid.
The fixed-clock binding doesn't define a reg, yet simple bus binding
implies that the reg property of child nodes should be interpretted as
the same address space as their parent (MMIO in this case?). The
fixed-clock nodes reg proeprties clearly aren't MMIO addresses.
Additionally, the _requred_ ranges property is missing.
It's just nonsensical; rename them to clock_{0,1,..} instead and get rid
of the reg properties. Then they're named uniquely.
However, for cases where the reg value is meaningful the below patch
makes sense.
Thanks,
Mark.
>
> Solve this by naming the clocks after the full node name rather than the
> short version (e.g. /clocks/clock at 0).
>
> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
> ---
> Note that if this is accepted, I intend to submit a patch for the RPi DTS
> which uses the naming structure above, so it might be useful to place this
> patch in its own branch. Or, I could submit the cleanup after 3.15-rc1.
> ---
> drivers/clk/clk-fixed-rate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
> index 0fc56ab..3335b3c 100644
> --- a/drivers/clk/clk-fixed-rate.c
> +++ b/drivers/clk/clk-fixed-rate.c
> @@ -115,7 +115,7 @@ EXPORT_SYMBOL_GPL(clk_register_fixed_rate);
> void of_fixed_clk_setup(struct device_node *node)
> {
> struct clk *clk;
> - const char *clk_name = node->name;
> + const char *clk_name = node->full_name;
> u32 rate;
> u32 accuracy = 0;
>
> --
> 1.8.3.2
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH 2/2] ARM: bcm2835: fix clock DT node names
From: Mark Rutland @ 2014-02-14 10:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392358613-19962-2-git-send-email-swarren@wwwdotorg.org>
On Fri, Feb 14, 2014 at 06:16:53AM +0000, Stephen Warren wrote:
> DT nodes should be named according to the type of object that they
> represent rather than the identity. DT nodes that contain a reg
> property should include a unit address in their name. Fix these issues.
As mentioned on patch one, I don't think this makes sense. clock at N is
simply not correct, and if simple-bus weren't being abused it would be
far clearer that that is the case.
Please use clock_N rather than clock at N here, and get rid of the
meaningless reg values.
The simple-bus should either be removed or fixed up to meet the
requirements of the simple-bus binding (i.e. add a ranges property). I
would prefer the former.
Thanks,
Mark.
>
> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
> ---
> This is the bcm2835 patch which depends on patch 1. I guess this could
> also go through the clk tree if that makes it easier, although there's
> always the small risk of conflicts if you do that.
>
> arch/arm/boot/dts/bcm2835.dtsi | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
> index a2d4889..1cf1ae7 100644
> --- a/arch/arm/boot/dts/bcm2835.dtsi
> +++ b/arch/arm/boot/dts/bcm2835.dtsi
> @@ -155,21 +155,21 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> - clk_mmc: mmc {
> + clk_mmc: clock at 0 {
> compatible = "fixed-clock";
> reg = <0>;
> #clock-cells = <0>;
> clock-frequency = <100000000>;
> };
>
> - clk_i2c: i2c {
> + clk_i2c: clock at 1 {
> compatible = "fixed-clock";
> reg = <1>;
> #clock-cells = <0>;
> clock-frequency = <250000000>;
> };
>
> - clk_spi: spi {
> + clk_spi: clock at 2 {
> compatible = "fixed-clock";
> reg = <2>;
> #clock-cells = <0>;
> --
> 1.8.3.2
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH v2 1/9] ARM: centralize common multi-platform kconfig options
From: Linus Walleij @ 2014-02-14 10:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392153119-23248-2-git-send-email-robherring2@gmail.com>
On Tue, Feb 11, 2014 at 10:11 PM, Rob Herring <robherring2@gmail.com> wrote:
> From: Rob Herring <robh@kernel.org>
>
> Multi-platform requires various kconfig options to be selected, so
> platforms don't need to select them individually.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Russell King <linux@arm.linux.org.uk>
OK makes sense. Maybe a bit unintuitive that multiplat
make gpiolib wanted optional and then platforms override
this by requiring it, but whatever, I cannot think of anything
better.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH RESEND v2 00/12] clk/exynos convert clock IDs to macros
From: Tomasz Figa @ 2014-02-14 10:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FD60A8.8070402@samsung.com>
Hi Kukjin,
On 14.02.2014 01:17, Kukjin Kim wrote:
> On 02/14/14 09:10, Kukjin Kim wrote:
>> On 01/28/14 06:49, Mike Turquette wrote:
>>> Quoting Tomasz Figa (2014-01-07 07:17:22)
>>>> Hi Mike,
>>>>
>>>> On Tuesday 07 of January 2014 15:47:28 Andrzej Hajda wrote:
>>>>> Hi,
>>>>>
>>>>> This patch set adds header files with macros defining exynos clocks.
>>>>> Then it converts dts files and drivers to use macros instead
>>>>> of magic numbers or enums to describe clock bindings.
>>>>>
>>>>> The patch set is rebased on the latest samsung-clk/samsung-next
>>>>> branch.
>>>>>
>>>>> The patches are generated by script.
>>>>> Many clocks I have verified by hand.
>>>>> I have also tested it successfully on exynos4 based board.
>>>>>
>>>>> This is the 2nd version of the patchset.
>>>>> Changes:
>>>>> - corrected devicetree mailing list,
>>>>> - added comments to include/dt-bindings/clock/exynos4.h for
>>>>> clocks present only in particular chip,
>>>>> - added tab alignement in headers,
>>>>> - added comment to CLK_NR_CLKS,
>>>>> - added copyright headers,
>>>>> - split long lines in dts,
>>>>> - corrected example in bindings/clock/exynos5250-clock.txt, to point
>>>>> appropriate clocks.
>>>>
>>>> I believe this has been already acked before, so could you still take
>>>> it for 3.14? For now I'd merge only the patches adding headers and
>>>> updating clock drivers to avoid merge conflicts and then after
>>>> release of 3.14-rc1 we could early merge dts patches for 3.15.
>>>
>>> Hi Tomasz,
>>>
>>> Let's go ahead and merge this after 3.14-rc1. I'll take it in when that
>>> drops and the DTS data will go in during the same merge window.
>>>
>>
>> Hi Mike,
>>
>> As I talked to Tomasz, would be better to us if this series could be
>> handled in Samsung tree so I'm going to do it. How do you think?
>>
> Oops, already merged into mainline ;-)
> Sorry, please kindly ignore my previous e-mail.
As you probably found out already, we've merged clock-side part of the
series for 3.14 to ease things a bit and let you simply merge the
DT-side for 3.15.
Also, since there were patches floating on the ML still using clock
numbers, we decided to give them some more time to be applied, then stop
accepting such patches and then finally rerun Andrzej's script on your
tree and ask you to apply resulting conversion patches.
Since you seem to have already applied most of such floating patches,
Andrzej will send you new series soon.
Best regards,
Tomasz
^ permalink raw reply
* [PATCH 2/9] ARM: select HAVE_SMP for V7 multi-platform
From: Linus Walleij @ 2014-02-14 10:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392153119-23248-3-git-send-email-robherring2@gmail.com>
On Tue, Feb 11, 2014 at 10:11 PM, Rob Herring <robherring2@gmail.com> wrote:
> From: Rob Herring <robh@kernel.org>
>
> All V7 platforms can run SMP kernels, so make CONFIG_SMP visible for V7
> multi-platform builds.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 4/6] ARM: firmware: add prepare_idle() operation
From: Tomasz Figa @ 2014-02-14 10:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FDA6B4.6070404@nvidia.com>
On 14.02.2014 06:16, Alexandre Courbot wrote:
> On 02/13/2014 08:01 PM, Tomasz Figa wrote:
>> Hi Alexandre,
>>
>> On 07.02.2014 05:35, Alexandre Courbot wrote:
>>> Some firmwares do not put the CPU into idle mode themselves, but still
>>> need to be informed that the CPU is about to enter idle mode before this
>>> happens. Add a prepare_idle() operation to the firmware_ops structure to
>>> handle such cases.
>>>
>>> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
>>> ---
>>> arch/arm/include/asm/firmware.h | 4 ++++
>>> 1 file changed, 4 insertions(+)
>>
>> I wonder if .do_idle() couldn't simply return an appropriate error code
>> to let the upper layer know that it should proceed with normal CPU idle
>> activation, while still letting the firmware know that the CPU is going
>> to idle.
>
> In our particular case I agree it would be enough to use do_idle() to
> let the firmware know about the operation and have it return -ENOSYS so
> the kernel actually performs it. I'm afraid this might not fulfill all
> needs though (e.g. one can imagine a firmware where the OS needs to take
> action between the notification and the actual shutdown), and as Stephen
> pointed out that would make the name of the function ambiguous at best.
> I'd rather keep it the current way for clarity.
>
OK. I'm not strongly against this, just wanted some more thought on
this, so please move on.
Best regards,
Tomasz
^ permalink raw reply
* [PATCH RESEND v4 00/37] mtd: st_spi_fsm: Add new driver
From: Lee Jones @ 2014-02-14 10:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FA3B1A.2070304@st.com>
> Sorry for the delay. I have now had a quick look through the patches. Just a
> couple of points :-)
>
> * stfsm_probe(): stfsm_fetch_platform_configs() needs to be called *before*
> config() -- config() is based on platform capabilities. Conceptually,
> stfsm_fetch_platform_configs() should be called before stfsm_jedec_probe(), and
> FLASH_FLAG_32BIT_ADDR should be moved out of stfsm_fetch_platform_configs(),
> placed just after stfsm_jedec_probe() but before config().
>
> * fsm_wait_busy(): logic not quite correct if we get a P_ERR or E_ERR error
> after a timeout. I am also not sure about returning (uint8_t)-EIO. For what
> its worth, this is what I did in response to Brian's comment about the race
> condition:
Thanks Angus.
Brain,
If I fix up the review comments from Angus', Ludovic and Christophe
are you happy to finally accept the driver? Or do you have any final
review comments that you wish me to apply for v5?
> On 01/23/2014 10:30 AM, Lee Jones wrote:
> > Version 4:
> > Tended to Brian's review comments
> > - Checkpatch acceptance
> > - MODULE_DEVICE_TABLE() name slip correction
> > - Timeout issue(s) resolved
> > - Potential infinite loop mitigated
> > - Code clarity suggests heeded
> > - Duplication with MTD core code removed
> > - Upgraded to using ROUND_UP() helper
> > - Moved non-shared header code into main driver
> > - Relocated dynamic msg sequence stores into main struct
> > - Averted adaption of static (table) data
> > - Basic whitespace/spelling/data type/dev_err suggestions applied
> >
> > Version 3:
> > Okay, this thing should be fully functional now. Identify a chip
> > based on it's JEDEC ID, Read, Write, Erase (all or by sector).
> > Support for various chip quirks added too.
> >
> > Version 2:
> > The first bunch of these patches have been on the MLs before, but
> > didn't receive a great deal of attention for the most part. We are
> > a little more featureful this time however. We can now successfully
> > setup and configure the N25Q256. We still can't read/write/erase
> > it though. I'll start work on that next week and will provide it in
> > the next instalment.
> >
> > Version 1:
> > First stab at getting this thing Mainlined. It doesn't do a great deal
> > yet, but we are able to initialise the device and dynamically set it up
> > correctly based on an extracted JEDEC ID.
> >
> > Documentation/devicetree/bindings/mtd/st-fsm.txt | 26 ++
> > arch/arm/boot/dts/stih416-b2105.dts | 14 +
> > arch/arm/boot/dts/stih416-pinctrl.dtsi | 12 +
> > drivers/mtd/devices/Kconfig | 8 +
> > drivers/mtd/devices/Makefile | 1 +
> > drivers/mtd/devices/serial_flash_cmds.h | 81 ++++
> > drivers/mtd/devices/st_spi_fsm.c | 2124 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > 7 files changed, 2266 insertions(+)
> >
> >
>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 23/27] clocksource: sh_cmt: Add DT support
From: Mark Rutland @ 2014-02-14 10:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1392339605-20691-24-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
On Fri, Feb 14, 2014 at 01:00:01AM +0000, Laurent Pinchart wrote:
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> .../devicetree/bindings/timer/renesas,cmt.txt | 75 +++++++++++++++
> drivers/clocksource/sh_cmt.c | 104 +++++++++++++++++----
> 2 files changed, 160 insertions(+), 19 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/timer/renesas,cmt.txt
>
> diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt
> new file mode 100644
> index 0000000..28d4ab5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt
> @@ -0,0 +1,75 @@
> +* Renesas R-Car Compare Match Timer (CMT)
> +
> +The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
> +inputs and programmable compare match.
> +
> +Channels share hadware resources but their counter and compare match value are
> +independent. A particular CMT instance can implement only a subset of the
> +channels supported by the CMT model. Channels indices start from 0 and are
> +consecutive.
> +
> +Required Properties:
> +
> + - compatible: must contain one of the following.
> + - "renesas,cmt-32" for the 32-bit CMT
> + (CMT0 on sh7372, sh73a0 and r8a7740)
> + - "renesas,cmt-32-fast" for the 32-bit CMT with fast clock support
> + (CMT[234] on sh7372, sh73a0 and r8a7740)
> + - "renasas,cmt-48" for the 48-bit CMT
> + (CMT1 on sh7372, sh73a0 and r8a7740)
> + - "renesas,cmt-48-gen2" for the second generation 48-bit CMT
> + (CMT[01] on r8a73a4, r8a7790 and r8a7791)
> +
> + - reg: base address and length of the registers block for the timer module.
> + - interrupt-parent, interrupts: interrupt-specifier for the timer, one per
> + channel.
It might make more sense to describe the interrupt on the channel
subnode. It makes it far clearer which channel has which interrupt.
> + - clocks: phandle and clock-specifier pair for the functional clock.
> + - clock-names: must be "fck".
It would be nice to define the list once:
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in clock-names.
- clock-names: Should contain "fck" for the functional clock.
> +
> + - #address-cells: must be 1
> + - #size-cells: must be 0
> +
> + - renesas,channels-mask: integer bitmask of the channels implemented by the
> + timer instance.
This is implied by the presence of a subnode. Either remove this or the
subnodes.
> +
> +
> +Each channel is described by a sub-node named "channel@<idx>", where <idx> is
> +the channel index.
> +
> +Channels Required Properties:
> +
> + - reg: the channel index.
> +
> +Channels Optional Properties:
> +
> + - clock-source-rating: rating of the timer as a clock source device.
> + - clock-event-rating: rating of the timer as a clock event device.
This feels like a leak of Linux internals. Why do you need this?
> +
> +
> +Example: R8A7790 (R-Car H2) CMT0 node
> +
> + CMT0 on R8A7790 implements hardware channels 5 and 6 only and names
> + them channels 0 and 1 in the documentation.
> +
> + cmt0: timer at ffca0000 {
> + compatible = "renesas,cmt-48-gen2";
> + reg = <0 0xffca0000 0 0x1004>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
> + <0 142 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + renesas,channels-mask = <0x60>;
> +
> + channel at 0 {
> + reg = <0>;
> + clock-event-rating = <80>;
> + };
> + channel at 0 {
> + reg = <0>;
> + clock-source-rating = <80>;
> + };
Aaargh. Use the _real_ channel IDs for the reg proeprties and get rid of
the mask. It's pointlessly confusing.
Thanks,
Mark
^ permalink raw reply
* [PATCH v2 0/3] ARM: PCI: implement generic PCI host controller
From: Arnd Bergmann @ 2014-02-14 11:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140213182655.GE17248@obsidianresearch.com>
On Thursday 13 February 2014 11:26:55 Jason Gunthorpe wrote:
> The DT representation is very straightforward, just have more copies
> of what you already have. Each DT stanza should be represented in
> Linux a distinct PCI domain.
>
> In Linux you run into two small problems
> 1) PCI Domain numbers needs to be allocated dynamically
> * I think there should be a core thing to allocate a domain
> object w/ a struct device, and assign a unique domain number.
> We are already seeing drivers do things like keep track
> of their own domain numbers via a counter (pcie-designware.c)
> The host bridge object is similar to this but it isn't focused
> on a domain.
Right, see also my other comment I just sent in the "Re: [PATCH v2 3/3]
PCI: ARM: add support for generic PCI host controller" thread.
The host driver is the wrong place to pick a domain number, but someone
has to do it.
> 2) The space in the IO fixed mapping needs to be allocated to PCI
> host drivers dynamically
> * pci_ioremap_io_dynamic that takes a bus address + cpu_physical
> address and returns a Linux virtual address.
> The first caller can get a nice traslation where bus address ==
> Linux virtual address, everyone after can get best efforts.
I think we can have a helper that everything we need to do
with the I/O space:
* parse the ranges property
* pick an appropriate virtual address window
* ioremap the physical window there
* compute the io_offset
* pick a name for the resource
* request the io resource
* register the pci_host_bridge_window
> You will have overlapping physical IO bus addresses - each domain will
> have a 0 IO BAR - but those will have distinct CPU physical addresses
> and can then be uniquely mapped into the IO mapping. So at the struct
> resource level the two domains have disjoint IO addresses, but each
> domain uses a different IO offset..
This would be the common case, but when we have a generic helper function,
it's actually not that are to handle a couple of variations of that,
which we may see in the field and can easily be described with the
existing binding.
* If we allow multiple host bridges to be in the same PCI domain with
a split bus space, we should also allow them to have a split I/O
space, e.g. have two 32KB windows, both with io_offset=0. This would
imply that the second bridge can only support relocatable I/O BARs.
* Similar to that, you may have multiple 64KB windows with io_offset=0.
* Some system may have hardwire I/O windows at a high bus address larger
than IO_SPACE_LIMIT. This would mean a *negative* io_offset. I can't
see any reason why anyone would do this, but I also don't see a reason
to prevent it if we can easily keep the code generic enough to handle
it without adding extra code.
* A more obscure case would be to have multiple I/O windows on a bus.
This is allowed by the binding and by the pci_host_bridge_window,
and while again I don't see a use case, it also doesn't seem hard
to do, we just keep looping for all ranges rather than stop after
the first window.
Arnd
^ permalink raw reply
* [PATCH v7 02/12] mfd: omap-usb-host: Get clocks based on hardware revision
From: Roger Quadros @ 2014-02-14 11:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140214100701.GC7380@lee--X1>
On 02/14/2014 12:07 PM, Lee Jones wrote:
>> Not all revisions have all the clocks so get the necessary clocks
>> based on hardware revision.
>>
>> This should avoid un-necessary clk_get failure messages that were
>> observed earlier.
>>
>> Be more strict and always fail on clk_get() error.
>
> It might have been clearer if you'd broken these two pieces of
> functionality changes into two different patches. In future it would
> be preferred.
OK.
>
>> CC: Lee Jones <lee.jones@linaro.org>
>> CC: Samuel Ortiz <sameo@linux.intel.com>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>> drivers/mfd/omap-usb-host.c | 92 +++++++++++++++++++++++++++++++--------------
>> 1 file changed, 64 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
>> index 0c3c9a0..60a3bed 100644
>> --- a/drivers/mfd/omap-usb-host.c
>> +++ b/drivers/mfd/omap-usb-host.c
>> @@ -665,22 +665,41 @@ static int usbhs_omap_probe(struct platform_device *pdev)
>> goto err_mem;
>> }
>>
>> - need_logic_fck = false;
>> + /* Set all clocks as invalid to begin with */
>> + omap->ehci_logic_fck = omap->init_60m_fclk = ERR_PTR(-ENODEV);
>> + omap->utmi_p1_gfclk = omap->utmi_p2_gfclk = ERR_PTR(-ENODEV);
>> + omap->xclk60mhsp1_ck = omap->xclk60mhsp2_ck = ERR_PTR(-ENODEV);
>> +
>
> For readability you should probably do these one per line.
OK.
>
>> for (i = 0; i < omap->nports; i++) {
>> - if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
>> - is_ehci_hsic_mode(i))
>> - need_logic_fck |= true;
>> + omap->utmi_clk[i] = ERR_PTR(-ENODEV);
>> + omap->hsic480m_clk[i] = ERR_PTR(-ENODEV);
>> + omap->hsic60m_clk[i] = ERR_PTR(-ENODEV);
>> }
>>
>> - omap->ehci_logic_fck = ERR_PTR(-EINVAL);
>> - if (need_logic_fck) {
>> - omap->ehci_logic_fck = devm_clk_get(dev, "ehci_logic_fck");
>
> Has this clock been renamed, or is it no longer required?
It is only for OMAP3 and it's actual name is "usbhost_120m_fck".
"ehci_logic_fck" is just an alias.
>
> Perhaps you should be explicit in the commit log as to which clocks
> you're removing.
>
>> - if (IS_ERR(omap->ehci_logic_fck)) {
>> - ret = PTR_ERR(omap->ehci_logic_fck);
>> - dev_dbg(dev, "ehci_logic_fck failed:%d\n", ret);
>> + /* for OMAP3 i.e. USBHS REV1 */
>> + if (omap->usbhs_rev == OMAP_USBHS_REV1) {
>> + need_logic_fck = false;
>> + for (i = 0; i < omap->nports; i++) {
>> + if (is_ehci_phy_mode(pdata->port_mode[i]) ||
>> + is_ehci_tll_mode(pdata->port_mode[i]) ||
>> + is_ehci_hsic_mode(pdata->port_mode[i]))
>> +
>> + need_logic_fck |= true;
>> + }
>> +
>> + if (need_logic_fck) {
>> + omap->ehci_logic_fck = clk_get(dev, "usbhost_120m_fck");
>
> devm_clk_get()?
Indeed.
cheers,
-roger
^ permalink raw reply
* [PATCH RESEND v2 00/12] clk/exynos convert clock IDs to macros
From: Sachin Kamat @ 2014-02-14 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <52FDF2C9.6060403@samsung.com>
Hi Tomasz,
On 14 February 2014 16:11, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Kukjin,
>
>
> On 14.02.2014 01:17, Kukjin Kim wrote:
>>
>> On 02/14/14 09:10, Kukjin Kim wrote:
>>>
>>> On 01/28/14 06:49, Mike Turquette wrote:
>>>>
>>>> Quoting Tomasz Figa (2014-01-07 07:17:22)
>>>>>
>>>>> Hi Mike,
>>>>>
>>>>> On Tuesday 07 of January 2014 15:47:28 Andrzej Hajda wrote:
>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> This patch set adds header files with macros defining exynos clocks.
>>>>>> Then it converts dts files and drivers to use macros instead
>>>>>> of magic numbers or enums to describe clock bindings.
>>>>>>
>>>>>> The patch set is rebased on the latest samsung-clk/samsung-next
>>>>>> branch.
>>>>>>
>>>>>> The patches are generated by script.
>>>>>> Many clocks I have verified by hand.
>>>>>> I have also tested it successfully on exynos4 based board.
>>>>>>
>>>>>> This is the 2nd version of the patchset.
>>>>>> Changes:
>>>>>> - corrected devicetree mailing list,
>>>>>> - added comments to include/dt-bindings/clock/exynos4.h for
>>>>>> clocks present only in particular chip,
>>>>>> - added tab alignement in headers,
>>>>>> - added comment to CLK_NR_CLKS,
>>>>>> - added copyright headers,
>>>>>> - split long lines in dts,
>>>>>> - corrected example in bindings/clock/exynos5250-clock.txt, to point
>>>>>> appropriate clocks.
>>>>>
>>>>>
>>>>> I believe this has been already acked before, so could you still take
>>>>> it for 3.14? For now I'd merge only the patches adding headers and
>>>>> updating clock drivers to avoid merge conflicts and then after
>>>>> release of 3.14-rc1 we could early merge dts patches for 3.15.
>>>>
>>>>
>>>> Hi Tomasz,
>>>>
>>>> Let's go ahead and merge this after 3.14-rc1. I'll take it in when that
>>>> drops and the DTS data will go in during the same merge window.
>>>>
>>>
>>> Hi Mike,
>>>
>>> As I talked to Tomasz, would be better to us if this series could be
>>> handled in Samsung tree so I'm going to do it. How do you think?
>>>
>> Oops, already merged into mainline ;-)
>> Sorry, please kindly ignore my previous e-mail.
>
>
> As you probably found out already, we've merged clock-side part of the
> series for 3.14 to ease things a bit and let you simply merge the DT-side
> for 3.15.
>
> Also, since there were patches floating on the ML still using clock numbers,
> we decided to give them some more time to be applied, then stop accepting
> such patches and then finally rerun Andrzej's script on your tree and ask
> you to apply resulting conversion patches.
>
> Since you seem to have already applied most of such floating patches,
> Andrzej will send you new series soon.
There are still quite a few board support patches of Arndale-octa and 5420 SMDK
that need to be applied. I believe Kukjin will apply them over the weekend.
--
With warm regards,
Sachin
^ permalink raw reply
* use {readl|writel}_relaxed instead of readl/writel in i2c-designware-core ?
From: Jisheng Zhang @ 2014-02-14 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8705989.qzo882Ldx0@wuerfel>
Dear Arnd,
On Fri, 14 Feb 2014 01:09:44 -0800
Arnd Bergmann <arnd@arndb.de> wrote:
> On Friday 14 February 2014 15:54:38 Jisheng Zhang wrote:
> > Hi all,
> >
> > The writel/readl is too expensive especially on Cortex A9 w/ outer L2
> > cache. This introduce i2c read/write error on Marvell Berlin SoCs when
> > there are L2 cache maintenance operations at the same time.
> >
> > In our internal berlin bsp, we just replaced readl/writel with the relaxed
> > version. But AFAIK, the "relaxed" version doesn't exist on all
> > architectures. How to handle this issue?
>
> In case of i2c-designware, this is safe because that driver does not perform
> DMA. In other drivers, you may have to be more careful, to ensure that all
> MMIO is serialized with DMA operations performed by the driver.
>
> > Any suggestions are appreciated.
>
> I would definitely welcome a patch that adds a default _relaxed
> implementation to include/linux/io.h, like this:
>
> #ifndef readb_relaxed
> #define readb_relaxed(p) readb(p)
> #endif
>
> and then adds "#define readb_relaxed(p) readb_relaxed(p)" etc. to all
> architectures that have a non-macro definition for readb.
Thanks for the suggestions. I'll try to send out one RFC patch.
Thanks,
Jisheng
^ permalink raw reply
* [PATCH 1/2] PPC: powernv: remove redundant cpuidle_idle_call()
From: Preeti U Murthy @ 2014-02-14 11:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1391696188-14540-1-git-send-email-nicolas.pitre@linaro.org>
Hi Nicolas,
You will have to include the below patch with yours. You
could squash the two I guess, I have added the changelog
just for clarity. And you also might want to change the subject to
cpuidle/powernv. It gives a better picture.
Thanks
Regards
Preeti U Murthy
cpuidle/powernv: Add ppc64_runlatch_off/on() to idle routines
Following moving of cpuidle_idle_call() to the generic idle loop, we need to
add the runlatch functions to the idle routines on powernv which was earlier
taken care of by the arch specific idle routine.
Signed-off-by: Preeti U Murthy <preeti@linux.vnet.ibm.com>
---
drivers/cpuidle/cpuidle-powernv.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/cpuidle/cpuidle-powernv.c b/drivers/cpuidle/cpuidle-powernv.c
index 78fd174..f48607c 100644
--- a/drivers/cpuidle/cpuidle-powernv.c
+++ b/drivers/cpuidle/cpuidle-powernv.c
@@ -14,6 +14,7 @@
#include <asm/machdep.h>
#include <asm/firmware.h>
+#include <asm/runlatch.h>
struct cpuidle_driver powernv_idle_driver = {
.name = "powernv_idle",
@@ -30,12 +31,14 @@ static int snooze_loop(struct cpuidle_device *dev,
local_irq_enable();
set_thread_flag(TIF_POLLING_NRFLAG);
+ ppc64_runlatch_off();
while (!need_resched()) {
HMT_low();
HMT_very_low();
}
HMT_medium();
+ ppc64_runlatch_on();
clear_thread_flag(TIF_POLLING_NRFLAG);
smp_mb();
return index;
@@ -45,7 +48,9 @@ static int nap_loop(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
+ ppc64_runlatch_off();
power7_idle();
+ ppc64_runlatch_on();
return index;
}
On 02/06/2014 07:46 PM, Nicolas Pitre wrote:
> The core idle loop now takes care of it.
>
> Signed-off-by: Nicolas Pitre <nico@linaro.org>
> ---
> arch/powerpc/platforms/powernv/setup.c | 13 +------------
> 1 file changed, 1 insertion(+), 12 deletions(-)
>
> diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
> index 21166f65c9..a932feb290 100644
> --- a/arch/powerpc/platforms/powernv/setup.c
> +++ b/arch/powerpc/platforms/powernv/setup.c
> @@ -26,7 +26,6 @@
> #include <linux/of_fdt.h>
> #include <linux/interrupt.h>
> #include <linux/bug.h>
> -#include <linux/cpuidle.h>
>
> #include <asm/machdep.h>
> #include <asm/firmware.h>
> @@ -217,16 +216,6 @@ static int __init pnv_probe(void)
> return 1;
> }
>
> -void powernv_idle(void)
> -{
> - /* Hook to cpuidle framework if available, else
> - * call on default platform idle code
> - */
> - if (cpuidle_idle_call()) {
> - power7_idle();
> - }
> -}
> -
> define_machine(powernv) {
> .name = "PowerNV",
> .probe = pnv_probe,
> @@ -236,7 +225,7 @@ define_machine(powernv) {
> .show_cpuinfo = pnv_show_cpuinfo,
> .progress = pnv_progress,
> .machine_shutdown = pnv_shutdown,
> - .power_save = powernv_idle,
> + .power_save = power7_idle,
> .calibrate_decr = generic_calibrate_decr,
> #ifdef CONFIG_KEXEC
> .kexec_cpu_down = pnv_kexec_cpu_down,
>
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox