* [PATCH v2 6/7] ARM: dts: rockchip: add core rk3288 dtsi
From: Heiko Stübner @ 2014-07-18 0:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4868343.UFgjaXesOn@diego>
Node definitions shared by all rk3288 based boards.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/boot/dts/rk3288.dtsi | 552 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 552 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3288.dtsi
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
new file mode 100644
index 0000000..c8e387e
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -0,0 +1,552 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "rockchip,rk3288";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a12";
+ reg = <0x500>;
+ };
+ cpu at 501 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a12";
+ reg = <0x501>;
+ };
+ cpu at 502 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a12";
+ reg = <0x502>;
+ };
+ cpu at 503 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a12";
+ reg = <0x503>;
+ };
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ #clock-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ i2c1: i2c at ff140000 {
+ compatible = "rockchip,rk3288-i2c";
+ reg = <0xff140000 0x1000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at ff150000 {
+ compatible = "rockchip,rk3288-i2c";
+ reg = <0xff150000 0x1000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C3>;
+ status = "disabled";
+ };
+
+ i2c4: i2c at ff160000 {
+ compatible = "rockchip,rk3288-i2c";
+ reg = <0xff160000 0x1000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C4>;
+ status = "disabled";
+ };
+
+ i2c5: i2c at ff170000 {
+ compatible = "rockchip,rk3288-i2c";
+ reg = <0xff170000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C5>;
+ status = "disabled";
+ };
+
+ uart0: serial at ff180000 {
+ compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
+ reg = <0xff180000 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart1: serial at ff190000 {
+ compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
+ reg = <0xff190000 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart2: serial at ff690000 {
+ compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
+ reg = <0xff690000 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart3: serial at ff1b0000 {
+ compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
+ reg = <0xff1b0000 0x100>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart4: serial at ff1c0000 {
+ compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
+ reg = <0xff1c0000 0x100>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ i2c0: i2c at ff650000 {
+ compatible = "rockchip,rk3288-i2c";
+ reg = <0xff650000 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at ff660000 {
+ compatible = "rockchip,rk3288-i2c";
+ reg = <0xff660000 0x1000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C2>;
+ status = "disabled";
+ };
+
+ pmu: power-management at ff730000 {
+ compatible = "rockchip,rk3288-pmu", "syscon";
+ reg = <0xff730000 0x100>;
+ };
+
+ sgrf: syscon at ff740000 {
+ compatible = "rockchip,rk3288-sgrf", "syscon";
+ reg = <0xff740000 0x1000>;
+ };
+
+ cru: clock-controller at ff760000 {
+ compatible = "rockchip,rk3288-cru";
+ reg = <0xff760000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ grf: syscon at ff770000 {
+ compatible = "rockchip,rk3288-grf", "syscon";
+ reg = <0xff770000 0x1000>;
+ };
+
+ watchdog at ff800000 {
+ compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
+ reg = <0xff800000 0x100>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller at ffc01000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0xffc01000 0x1000>,
+ <0xffc02000 0x1000>,
+ <0xffc04000 0x2000>,
+ <0xffc06000 0x2000>;
+ interrupts = <GIC_PPI 9 0xf04>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3288-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmu>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0 at ff750000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff750000 0x100>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1 at ff780000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff780000 0x100>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2 at ff790000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff790000 0x100>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3 at ff7a0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff7a0000 0x100>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio4 at ff7b0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff7b0000 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio5 at ff7c0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff7c0000 0x100>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO5>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio6 at ff7d0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff7d0000 0x100>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO6>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio7: gpio7 at ff7e0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff7e0000 0x100>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO7>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio8: gpio8 at ff7f0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff7f0000 0x100>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO8>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg_pull_up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg_pull_down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg_pull_none {
+ bias-disable;
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
+ <0 16 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
+ <8 5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
+ <6 10 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
+ <2 17 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c4 {
+ i2c4_xfer: i2c4-xfer {
+ rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
+ <7 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c5 {
+ i2c5_xfer: i2c5-xfer {
+ rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
+ <7 20 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_cd: sdmcc-cd {
+ rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_bus1: sdmmc-bus1 {
+ rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
+ <6 17 RK_FUNC_1 &pcfg_pull_up>,
+ <6 18 RK_FUNC_1 &pcfg_pull_up>,
+ <6 19 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ emmc {
+ emmc_clk: emmc-clk {
+ rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ emmc_pwr: emmc-pwr {
+ rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ emmc_bus1: emmc-bus1 {
+ rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ emmc_bus4: emmc-bus4 {
+ rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
+ <3 1 RK_FUNC_2 &pcfg_pull_up>,
+ <3 2 RK_FUNC_2 &pcfg_pull_up>,
+ <3 3 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
+ <3 1 RK_FUNC_2 &pcfg_pull_up>,
+ <3 2 RK_FUNC_2 &pcfg_pull_up>,
+ <3 3 RK_FUNC_2 &pcfg_pull_up>,
+ <3 4 RK_FUNC_2 &pcfg_pull_up>,
+ <3 5 RK_FUNC_2 &pcfg_pull_up>,
+ <3 6 RK_FUNC_2 &pcfg_pull_up>,
+ <3 7 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
+ <4 17 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
+ <5 9 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
+ <7 23 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ /* no rts / cts for uart2 */
+ };
+
+ uart3 {
+ uart3_xfer: uart3-xfer {
+ rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
+ <7 8 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart3_cts: uart3-cts {
+ rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart3_rts: uart3-rts {
+ rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart4 {
+ uart4_xfer: uart4-xfer {
+ rockchip,pins = <5 12 3 &pcfg_pull_up>,
+ <5 13 3 &pcfg_pull_none>;
+ };
+
+ uart4_cts: uart4-cts {
+ rockchip,pins = <5 14 3 &pcfg_pull_none>;
+ };
+
+ uart4_rts: uart4-rts {
+ rockchip,pins = <5 15 3 &pcfg_pull_none>;
+ };
+ };
+ };
+};
--
1.9.0
^ permalink raw reply related
* [PATCH v2 5/7] ARM: rockchip: enable support for RK3288 SoCs
From: Heiko Stübner @ 2014-07-18 0:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4868343.UFgjaXesOn@diego>
Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/mach-rockchip/Kconfig | 1 +
arch/arm/mach-rockchip/rockchip.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index e4564c2..d168669 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -6,6 +6,7 @@ config ARCH_ROCKCHIP
select ARCH_REQUIRE_GPIOLIB
select ARM_GIC
select CACHE_L2X0
+ select HAVE_ARM_ARCH_TIMER
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select DW_APB_TIMER_OF
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index 968cc34..8ab9e0e 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -29,6 +29,7 @@ static const char * const rockchip_board_dt_compat[] = {
"rockchip,rk3066a",
"rockchip,rk3066b",
"rockchip,rk3188",
+ "rockchip,rk3288",
NULL,
};
--
1.9.0
^ permalink raw reply related
* [PATCH v2 4/7] ARM: Kconfig: set default gpio number for rockchip SoCs
From: Heiko Stübner @ 2014-07-18 0:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4868343.UFgjaXesOn@diego>
The new rk3288 needs a bigger gpio space, as it has 9 gpio banks.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Tested-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 87b63fd..8d1dee0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1574,6 +1574,7 @@ config ARCH_NR_GPIO
default 416 if ARCH_SUNXI
default 392 if ARCH_U8500
default 352 if ARCH_VT8500
+ default 288 if ARCH_ROCKCHIP
default 264 if MACH_H4700
default 0
help
--
1.9.0
^ permalink raw reply related
* [PATCH v2 3/7] ARM: rockchip: add debug uart used by rk3288
From: Heiko Stübner @ 2014-07-18 0:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4868343.UFgjaXesOn@diego>
The uarts on rk3288 are still compatible with the dw_8250, but located
at a different position and need DEBUG_UART_8250_WORD enabled.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Tested-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/Kconfig.debug | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index a8dbf5e..8dcc00d 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -613,6 +613,14 @@ choice
Say Y here if you want kernel low-level debugging support
on Rockchip based platforms.
+ config DEBUG_RK32_UART2
+ bool "Kernel low-level debugging messages via Rockchip RK32 UART2"
+ depends on ARCH_ROCKCHIP
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on Rockchip RK32xx based platforms.
+
config DEBUG_S3C_UART0
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
@@ -1096,6 +1104,7 @@ config DEBUG_UART_PHYS
default 0xf991e000 if DEBUG_QCOM_UARTDM
default 0xfcb00000 if DEBUG_HI3620_UART
default 0xfe800000 if ARCH_IOP32X
+ default 0xff690000 if DEBUG_RK32_UART2
default 0xffc02000 if DEBUG_SOCFPGA_UART
default 0xffd82340 if ARCH_IOP13XX
default 0xfff36000 if DEBUG_HIGHBANK_UART
@@ -1152,6 +1161,7 @@ config DEBUG_UART_VIRT
default 0xfec02000 if DEBUG_SOCFPGA_UART
default 0xfec12000 if DEBUG_MVEBU_UART || DEBUG_MVEBU_UART_ALTERNATE
default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
+ default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2
default 0xfed12000 if ARCH_KIRKWOOD
@@ -1186,7 +1196,7 @@ config DEBUG_UART_8250_WORD
ARCH_KEYSTONE || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
DEBUG_DAVINCI_DA8XX_UART2 || \
- DEBUG_BCM_KONA_UART
+ DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
config DEBUG_UART_8250_FLOW_CONTROL
bool "Enable flow control for 8250 UART"
--
1.9.0
^ permalink raw reply related
* [PATCH v2 2/7] ARM: rockchip: clarify usability of DEBUG_RK3X_UART debug_ll options
From: Heiko Stübner @ 2014-07-18 0:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4868343.UFgjaXesOn@diego>
The debug uart settings from the DEBUG_RK3X_UART options are usable on
all Rockchip SoCs from the rk30xx and rk31xx series but not on the
new rk3288 SoCs. Thus clarify their use to prevent confusion.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/Kconfig.debug | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 8f90595..a8dbf5e 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -582,7 +582,7 @@ choice
on Rockchip based platforms.
config DEBUG_RK3X_UART0
- bool "Kernel low-level debugging messages via Rockchip RK3X UART0"
+ bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART0"
depends on ARCH_ROCKCHIP
select DEBUG_UART_8250
help
@@ -590,7 +590,7 @@ choice
on Rockchip based platforms.
config DEBUG_RK3X_UART1
- bool "Kernel low-level debugging messages via Rockchip RK3X UART1"
+ bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART1"
depends on ARCH_ROCKCHIP
select DEBUG_UART_8250
help
@@ -598,7 +598,7 @@ choice
on Rockchip based platforms.
config DEBUG_RK3X_UART2
- bool "Kernel low-level debugging messages via Rockchip RK3X UART2"
+ bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART2"
depends on ARCH_ROCKCHIP
select DEBUG_UART_8250
help
@@ -606,7 +606,7 @@ choice
on Rockchip based platforms.
config DEBUG_RK3X_UART3
- bool "Kernel low-level debugging messages via Rockchip RK3X UART3"
+ bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART3"
depends on ARCH_ROCKCHIP
select DEBUG_UART_8250
help
--
1.9.0
^ permalink raw reply related
* [PATCH v2 1/7] dt-bindings: arm: add cortex-a12 and cortex-a17 cpu compatible properties
From: Heiko Stübner @ 2014-07-18 0:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4868343.UFgjaXesOn@diego>
As announced parts from ARM they will probably be used in socs shortly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 1fe72a0..bc6dc17 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -152,7 +152,9 @@ nodes to be present and contain the properties described below.
"arm,cortex-a7"
"arm,cortex-a8"
"arm,cortex-a9"
+ "arm,cortex-a12"
"arm,cortex-a15"
+ "arm,cortex-a17"
"arm,cortex-a53"
"arm,cortex-a57"
"arm,cortex-m0"
--
1.9.0
^ permalink raw reply related
* [PATCH v2 0/7] ARM: rockchip: add initial support for rk3288
From: Heiko Stübner @ 2014-07-18 0:18 UTC (permalink / raw)
To: linux-arm-kernel
This series adds the initial support for Rockchip rk3288 socs including
debug uart and devicetree files for the rk3288 evaluation board and
enables these boards to boot into an initramfs.
Boards using uboot need an updated bootloader, which must start the timer
supplying the architected timer, while the coreboot bootloader already does
this. It also depends on the patch
"irqchip: gic: Add binding probe for ARM GIC400"
which should have made it into the irqchip tree today.
changes since v1:
- adress comments from Olof Johansson and Doug Anderson
- remove soc parent-node
- clarify cortex-a9 debug-uart descriptions
- a lot of dts changes
Heiko Stuebner (7):
dt-bindings: arm: add cortex-a12 and cortex-a17 cpu compatible
properties
ARM: rockchip: clarify usability of DEBUG_RK3X_UART debug_ll options
ARM: rockchip: add debug uart used by rk3288
ARM: Kconfig: set default gpio number for rockchip SoCs
ARM: rockchip: enable support for RK3288 SoCs
ARM: dts: rockchip: add core rk3288 dtsi
ARM: dts: add rk3288 evaluation board
Documentation/devicetree/bindings/arm/cpus.txt | 2 +
arch/arm/Kconfig | 1 +
arch/arm/Kconfig.debug | 20 +-
arch/arm/boot/dts/rk3288-evb-act8846.dts | 134 ++++++
arch/arm/boot/dts/rk3288-evb-rk808.dts | 18 +
arch/arm/boot/dts/rk3288-evb.dtsi | 83 ++++
arch/arm/boot/dts/rk3288.dtsi | 552 +++++++++++++++++++++++++
arch/arm/mach-rockchip/Kconfig | 1 +
arch/arm/mach-rockchip/rockchip.c | 1 +
9 files changed, 807 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/boot/dts/rk3288-evb-act8846.dts
create mode 100644 arch/arm/boot/dts/rk3288-evb-rk808.dts
create mode 100644 arch/arm/boot/dts/rk3288-evb.dtsi
create mode 100644 arch/arm/boot/dts/rk3288.dtsi
--
1.9.0
^ permalink raw reply
* [PATCHv2] ARM: dts: Add I2S dt node for Exynos3250
From: Chanwoo Choi @ 2014-07-18 0:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1404874819-8257-1-git-send-email-cw00.choi@samsung.com>
On 07/09/2014 12:00 PM, Chanwoo Choi wrote:
> From: Tomasz Figa <t.figa@samsung.com>
>
> This patch add I2S (Inter-IC Sound) dt node which supports 1-port stereo
> (1 channels) IIS-bus for audio interface with DMA-based operation.
>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Inha Song <ideal.song@samsung.com>
> Tested-by: Inha Song <ideal.song@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
> Changes from v1:
> - Fix wrong name of property (pinctrl-names)
> - Change phanle name (i2s->i2s2)
>
> arch/arm/boot/dts/exynos3250.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
> index 3e678fa..77a06df 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -425,6 +425,19 @@
> status = "disabled";
> };
>
> + i2s2: i2s at 13970000 {
> + compatible = "samsung,s3c6410-i2s";
> + reg = <0x13970000 0x100>;
> + interrupts = <0 126 0>;
> + clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
> + clock-names = "iis", "i2s_opclk0";
> + dmas = <&pdma0 14>, <&pdma0 13>;
> + dma-names = "tx", "rx";
> + pinctrl-0 = <&i2s2_bus>;
> + pinctrl-names = "default";
> + status = "disabled";
> + };
> +
> pwm: pwm at 139D0000 {
> compatible = "samsung,exynos4210-pwm";
> reg = <0x139D0000 0x1000>;
>
Ping.
Best Regards,
Chanwoo Choi
^ permalink raw reply
* [RESEND PATCH] thermal: samsung: Add TMU support for Exynos3250 SoC
From: Chanwoo Choi @ 2014-07-18 0:00 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the registers, bit fields and compatible strings
required to support for the 1 TMU channels on Exynos3250.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
[Add MUX address setting bits by Jonghwa Lee]
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Amit Daniel Kachhap<amit.daniel@samsung.com>
---
.../devicetree/bindings/thermal/exynos-thermal.txt | 1 +
drivers/thermal/samsung/exynos_tmu.c | 7 +-
drivers/thermal/samsung/exynos_tmu.h | 3 +-
drivers/thermal/samsung/exynos_tmu_data.c | 89 ++++++++++++++++++++++
drivers/thermal/samsung/exynos_tmu_data.h | 7 ++
5 files changed, 105 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index c949092..ae738f5 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -3,6 +3,7 @@
** Required properties:
- compatible : One of the following:
+ "samsung,exynos3250-tmu"
"samsung,exynos4412-tmu"
"samsung,exynos4210-tmu"
"samsung,exynos5250-tmu"
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index d7ca9f4..a2a08ea 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -505,6 +505,10 @@ static irqreturn_t exynos_tmu_irq(int irq, void *id)
static const struct of_device_id exynos_tmu_match[] = {
{
+ .compatible = "samsung,exynos3250-tmu",
+ .data = (void *)EXYNOS3250_TMU_DRV_DATA,
+ },
+ {
.compatible = "samsung,exynos4210-tmu",
.data = (void *)EXYNOS4210_TMU_DRV_DATA,
},
@@ -677,7 +681,8 @@ static int exynos_tmu_probe(struct platform_device *pdev)
goto err_clk_sec;
}
- if (pdata->type == SOC_ARCH_EXYNOS4210 ||
+ if (pdata->type == SOC_ARCH_EXYNOS3250 ||
+ pdata->type == SOC_ARCH_EXYNOS4210 ||
pdata->type == SOC_ARCH_EXYNOS4412 ||
pdata->type == SOC_ARCH_EXYNOS5250 ||
pdata->type == SOC_ARCH_EXYNOS5260 ||
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index edd08cf..1b4a644 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -40,7 +40,8 @@ enum calibration_mode {
};
enum soc_type {
- SOC_ARCH_EXYNOS4210 = 1,
+ SOC_ARCH_EXYNOS3250 = 1,
+ SOC_ARCH_EXYNOS4210,
SOC_ARCH_EXYNOS4412,
SOC_ARCH_EXYNOS5250,
SOC_ARCH_EXYNOS5260,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index c1d81dc..aa8e0de 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -90,6 +90,95 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
};
#endif
+#if defined(CONFIG_SOC_EXYNOS3250)
+static const struct exynos_tmu_registers exynos3250_tmu_registers = {
+ .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+ .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+ .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+ .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+ .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
+ .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+ .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+ .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+ .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+ .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+ .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+ .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+ .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+ .tmu_status = EXYNOS_TMU_REG_STATUS,
+ .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+ .threshold_th0 = EXYNOS_THD_TEMP_RISE,
+ .threshold_th1 = EXYNOS_THD_TEMP_FALL,
+ .tmu_inten = EXYNOS_TMU_REG_INTEN,
+ .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+ .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+ .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+ .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+ .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+ .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+ .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
+ .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+ .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+ .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+ .emul_con = EXYNOS_EMUL_CON,
+ .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+ .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+ .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define EXYNOS3250_TMU_DATA \
+ .threshold_falling = 10, \
+ .trigger_levels[0] = 70, \
+ .trigger_levels[1] = 95, \
+ .trigger_levels[2] = 110, \
+ .trigger_levels[3] = 120, \
+ .trigger_enable[0] = true, \
+ .trigger_enable[1] = true, \
+ .trigger_enable[2] = true, \
+ .trigger_enable[3] = false, \
+ .trigger_type[0] = THROTTLE_ACTIVE, \
+ .trigger_type[1] = THROTTLE_ACTIVE, \
+ .trigger_type[2] = SW_TRIP, \
+ .trigger_type[3] = HW_TRIP, \
+ .max_trigger_level = 4, \
+ .gain = 8, \
+ .reference_voltage = 16, \
+ .noise_cancel_mode = 4, \
+ .cal_type = TYPE_TWO_POINT_TRIMMING, \
+ .efuse_value = 55, \
+ .min_efuse_value = 40, \
+ .max_efuse_value = 100, \
+ .first_point_trim = 25, \
+ .second_point_trim = 85, \
+ .default_temp_offset = 50, \
+ .freq_tab[0] = { \
+ .freq_clip_max = 800 * 1000, \
+ .temp_level = 70, \
+ }, \
+ .freq_tab[1] = { \
+ .freq_clip_max = 400 * 1000, \
+ .temp_level = 95, \
+ }, \
+ .freq_tab_count = 2, \
+ .registers = &exynos3250_tmu_registers, \
+ .features = (TMU_SUPPORT_EMULATION | \
+ TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+ TMU_SUPPORT_EMUL_TIME)
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS3250)
+struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
+ .tmu_data = {
+ {
+ EXYNOS3250_TMU_DATA,
+ .type = SOC_ARCH_EXYNOS3250,
+ .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
+ },
+ },
+ .tmu_count = 1,
+};
+#endif
+
#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
static const struct exynos_tmu_registers exynos4412_tmu_registers = {
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index d268981..f0979e5 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -148,6 +148,13 @@
#define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
#define EXYNOS5440_EFUSE_SWAP_OFFSET 8
+#if defined(CONFIG_SOC_EXYNOS3250)
+extern struct exynos_tmu_init_data const exynos3250_default_tmu_data;
+#define EXYNOS3250_TMU_DRV_DATA (&exynos3250_default_tmu_data)
+#else
+#define EXYNOS3250_TMU_DRV_DATA (NULL)
+#endif
+
#if defined(CONFIG_CPU_EXYNOS4210)
extern struct exynos_tmu_init_data const exynos4210_default_tmu_data;
#define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
--
1.8.0
^ permalink raw reply related
* [PATCH 3/3] ARM: shmobile: r7s72100: Remove legacy board support
From: Simon Horman @ 2014-07-17 23:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1405641497.git.horms+renesas@verge.net.au>
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
There's no legacy board anymore, genmai now boots with multiplatform
support only. Remove the leftovers.
Makefile.boot portion pointed out by Paul Bolle.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Wolfram Sang <wsa@sang-engineering.com>
Cc: Paul Bolle <pebolle@tiscali.nl>
[horms+renesas at verge.net.au: squashed in patch containing
Makefile.boot change]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/Kconfig | 8 --
arch/arm/mach-shmobile/Makefile | 1 -
arch/arm/mach-shmobile/Makefile.boot | 1 -
arch/arm/mach-shmobile/clock-r7s72100.c | 231 --------------------------------
arch/arm/mach-shmobile/r7s72100.h | 6 -
arch/arm/mach-shmobile/setup-r7s72100.c | 2 -
6 files changed, 249 deletions(-)
delete mode 100644 arch/arm/mach-shmobile/clock-r7s72100.c
delete mode 100644 arch/arm/mach-shmobile/r7s72100.h
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 85f55e8..384221d 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -146,14 +146,6 @@ config ARCH_R8A7791
select SYS_SUPPORTS_SH_CMT
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
-config ARCH_R7S72100
- bool "RZ/A1H (R7S72100)"
- select ARCH_WANT_OPTIONAL_GPIOLIB
- select ARM_GIC
- select CPU_V7
- select SH_CLK_CPG
- select SYS_SUPPORTS_SH_MTU2
-
comment "Renesas ARM SoCs Board Type"
config MACH_APE6EVM
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 411e236..dc9446f 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -31,7 +31,6 @@ obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o
-obj-$(CONFIG_ARCH_R7S72100) += clock-r7s72100.o
endif
# CPU reset vector handling objects
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index ebf97d4..a23e155 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -6,7 +6,6 @@ loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
-loadaddr-$(CONFIG_MACH_GENMAI) += 0x08008000
loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000
loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
deleted file mode 100644
index 3eb2ec4..0000000
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * r7a72100 clock framework support
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- * Copyright (C) 2012 Phil Edworthy
- * Copyright (C) 2011 Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/sh_clk.h>
-#include <linux/clkdev.h>
-
-#include "common.h"
-#include "r7s72100.h"
-
-/* Frequency Control Registers */
-#define FRQCR 0xfcfe0010
-#define FRQCR2 0xfcfe0014
-/* Standby Control Registers */
-#define STBCR3 0xfcfe0420
-#define STBCR4 0xfcfe0424
-#define STBCR7 0xfcfe0430
-#define STBCR9 0xfcfe0438
-#define STBCR10 0xfcfe043c
-
-#define PLL_RATE 30
-
-static struct clk_mapping cpg_mapping = {
- .phys = 0xfcfe0000,
- .len = 0x1000,
-};
-
-/* Fixed 32 KHz root clock for RTC */
-static struct clk r_clk = {
- .rate = 32768,
-};
-
-/*
- * Default rate for the root input clock, reset this with clk_set_rate()
- * from the platform code.
- */
-static struct clk extal_clk = {
- .rate = 13330000,
- .mapping = &cpg_mapping,
-};
-
-static unsigned long pll_recalc(struct clk *clk)
-{
- return clk->parent->rate * PLL_RATE;
-}
-
-static struct sh_clk_ops pll_clk_ops = {
- .recalc = pll_recalc,
-};
-
-static struct clk pll_clk = {
- .ops = &pll_clk_ops,
- .parent = &extal_clk,
- .flags = CLK_ENABLE_ON_INIT,
-};
-
-static unsigned long bus_recalc(struct clk *clk)
-{
- return clk->parent->rate / 3;
-}
-
-static struct sh_clk_ops bus_clk_ops = {
- .recalc = bus_recalc,
-};
-
-static struct clk bus_clk = {
- .ops = &bus_clk_ops,
- .parent = &pll_clk,
- .flags = CLK_ENABLE_ON_INIT,
-};
-
-static unsigned long peripheral0_recalc(struct clk *clk)
-{
- return clk->parent->rate / 12;
-}
-
-static struct sh_clk_ops peripheral0_clk_ops = {
- .recalc = peripheral0_recalc,
-};
-
-static struct clk peripheral0_clk = {
- .ops = &peripheral0_clk_ops,
- .parent = &pll_clk,
- .flags = CLK_ENABLE_ON_INIT,
-};
-
-static unsigned long peripheral1_recalc(struct clk *clk)
-{
- return clk->parent->rate / 6;
-}
-
-static struct sh_clk_ops peripheral1_clk_ops = {
- .recalc = peripheral1_recalc,
-};
-
-static struct clk peripheral1_clk = {
- .ops = &peripheral1_clk_ops,
- .parent = &pll_clk,
- .flags = CLK_ENABLE_ON_INIT,
-};
-
-struct clk *main_clks[] = {
- &r_clk,
- &extal_clk,
- &pll_clk,
- &bus_clk,
- &peripheral0_clk,
- &peripheral1_clk,
-};
-
-static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
-static int multipliers[] = { 1, 2, 1, 1 };
-
-static struct clk_div_mult_table div4_div_mult_table = {
- .divisors = div2,
- .nr_divisors = ARRAY_SIZE(div2),
- .multipliers = multipliers,
- .nr_multipliers = ARRAY_SIZE(multipliers),
-};
-
-static struct clk_div4_table div4_table = {
- .div_mult_table = &div4_div_mult_table,
-};
-
-enum { DIV4_I,
- DIV4_NR };
-
-#define DIV4(_reg, _bit, _mask, _flags) \
- SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
-
-/* The mask field specifies the div2 entries that are valid */
-struct clk div4_clks[DIV4_NR] = {
- [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
- | CLK_ENABLE_ON_INIT),
-};
-
-enum {
- MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
- MSTP97, MSTP96, MSTP95, MSTP94,
- MSTP74,
- MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
- MSTP33, MSTP_NR
-};
-
-static struct clk mstp_clks[MSTP_NR] = {
- [MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
- [MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
- [MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
- [MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
- [MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
- [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
- [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
- [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
- [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
- [MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
- [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
- [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
- [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
- [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
- [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
- [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
- [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
- [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
- [MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
-};
-
-static struct clk_lookup lookups[] = {
- /* main clocks */
- CLKDEV_CON_ID("rclk", &r_clk),
- CLKDEV_CON_ID("extal", &extal_clk),
- CLKDEV_CON_ID("pll_clk", &pll_clk),
- CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
-
- /* DIV4 clocks */
- CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
-
- /* MSTP clocks */
- CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
- CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
- CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
- CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
- CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
- CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
-
- /* ICK */
- CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
- CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
- CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
- CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
- CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
- CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
- CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
- CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
- CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP33]),
-};
-
-void __init r7s72100_clock_init(void)
-{
- int k, ret = 0;
-
- for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
- ret = clk_register(main_clks[k]);
-
- clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
- if (!ret)
- ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
-
- if (!ret)
- ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
-
- if (!ret)
- shmobile_clk_init();
- else
- panic("failed to setup rza1 clocks\n");
-}
diff --git a/arch/arm/mach-shmobile/r7s72100.h b/arch/arm/mach-shmobile/r7s72100.h
deleted file mode 100644
index 321ae4e..0000000
--- a/arch/arm/mach-shmobile/r7s72100.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_R7S72100_H__
-#define __ASM_R7S72100_H__
-
-void r7s72100_clock_init(void);
-
-#endif /* __ASM_R7S72100_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index d898cef..111437d 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -24,7 +24,6 @@
#include "common.h"
-#ifdef CONFIG_USE_OF
static const char *r7s72100_boards_compat_dt[] __initdata = {
"renesas,r7s72100",
NULL,
@@ -34,4 +33,3 @@ DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
.init_early = shmobile_init_delay,
.dt_compat = r7s72100_boards_compat_dt,
MACHINE_END
-#endif /* CONFIG_USE_OF */
--
2.0.1
^ permalink raw reply related
* [PATCH 2/3] ARM: shmobile: r7s72100: genmai: Remove legacy board file
From: Simon Horman @ 2014-07-17 23:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1405641497.git.horms+renesas@verge.net.au>
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The genmai board now boots using DT and multiplatform kernel with the
same feature set as the legacy board. Remove the legacy board file and
the board Kconfig option.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Wolfram Sang <wsa@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/Kconfig | 9 --
arch/arm/mach-shmobile/Makefile | 1 -
arch/arm/mach-shmobile/board-genmai.c | 174 ----------------------------------
3 files changed, 184 deletions(-)
delete mode 100644 arch/arm/mach-shmobile/board-genmai.c
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 4508643..85f55e8 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -43,10 +43,6 @@ config ARCH_R8A7791
comment "Renesas ARM SoCs Board Type"
-config MACH_GENMAI
- bool "Genmai board"
- depends on ARCH_R7S72100
-
config MACH_KOELSCH
bool "Koelsch board"
depends on ARCH_R8A7791
@@ -233,11 +229,6 @@ config MACH_BOCKW_REFERENCE
This is intended to aid developers
-config MACH_GENMAI
- bool "Genmai board"
- depends on ARCH_R7S72100
- select USE_OF
-
config MACH_MARZEN
bool "MARZEN board"
depends on ARCH_R8A7779
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 18b05a8..411e236 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -71,7 +71,6 @@ obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o
obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
-obj-$(CONFIG_MACH_GENMAI) += board-genmai.o
obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
obj-$(CONFIG_MACH_LAGER) += board-lager.o
obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
diff --git a/arch/arm/mach-shmobile/board-genmai.c b/arch/arm/mach-shmobile/board-genmai.c
deleted file mode 100644
index b5dee53..0000000
--- a/arch/arm/mach-shmobile/board-genmai.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * Genmai board support
- *
- * Copyright (C) 2013-2014 Renesas Solutions Corp.
- * Copyright (C) 2013 Magnus Damm
- * Copyright (C) 2014 Cogent Embedded, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/serial_sci.h>
-#include <linux/sh_eth.h>
-#include <linux/sh_timer.h>
-#include <linux/spi/rspi.h>
-#include <linux/spi/spi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "irqs.h"
-#include "r7s72100.h"
-
-/* Ether */
-static const struct sh_eth_plat_data ether_pdata __initconst = {
- .phy = 0x00, /* PD60610 */
- .edmac_endian = EDMAC_LITTLE_ENDIAN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
- .no_ether_link = 1
-};
-
-static const struct resource ether_resources[] __initconst = {
- DEFINE_RES_MEM(0xe8203000, 0x800),
- DEFINE_RES_MEM(0xe8204800, 0x200),
- DEFINE_RES_IRQ(gic_iid(359)),
-};
-
-static const struct platform_device_info ether_info __initconst = {
- .parent = &platform_bus,
- .name = "r7s72100-ether",
- .id = -1,
- .res = ether_resources,
- .num_res = ARRAY_SIZE(ether_resources),
- .data = ðer_pdata,
- .size_data = sizeof(ether_pdata),
- .dma_mask = DMA_BIT_MASK(32),
-};
-
-/* RSPI */
-#define RSPI_RESOURCE(idx, baseaddr, irq) \
-static const struct resource rspi##idx##_resources[] __initconst = { \
- DEFINE_RES_MEM(baseaddr, 0x24), \
- DEFINE_RES_IRQ_NAMED(irq, "error"), \
- DEFINE_RES_IRQ_NAMED(irq + 1, "rx"), \
- DEFINE_RES_IRQ_NAMED(irq + 2, "tx"), \
-}
-
-RSPI_RESOURCE(0, 0xe800c800, gic_iid(270));
-RSPI_RESOURCE(1, 0xe800d000, gic_iid(273));
-RSPI_RESOURCE(2, 0xe800d800, gic_iid(276));
-RSPI_RESOURCE(3, 0xe800e000, gic_iid(279));
-RSPI_RESOURCE(4, 0xe800e800, gic_iid(282));
-
-static const struct rspi_plat_data rspi_pdata __initconst = {
- .num_chipselect = 1,
-};
-
-#define r7s72100_register_rspi(idx) \
- platform_device_register_resndata(&platform_bus, "rspi-rz", idx, \
- rspi##idx##_resources, \
- ARRAY_SIZE(rspi##idx##_resources), \
- &rspi_pdata, sizeof(rspi_pdata))
-
-static const struct spi_board_info spi_info[] __initconst = {
- {
- .modalias = "wm8978",
- .max_speed_hz = 5000000,
- .bus_num = 4,
- .chip_select = 0,
- },
-};
-
-/* SCIF */
-#define R7S72100_SCIF(index, baseaddr, irq) \
-static const struct plat_sci_port scif##index##_platform_data = { \
- .type = PORT_SCIF, \
- .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \
- .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
- .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
- SCSCR_REIE, \
-}; \
- \
-static struct resource scif##index##_resources[] = { \
- DEFINE_RES_MEM(baseaddr, 0x100), \
- DEFINE_RES_IRQ(irq + 1), \
- DEFINE_RES_IRQ(irq + 2), \
- DEFINE_RES_IRQ(irq + 3), \
- DEFINE_RES_IRQ(irq), \
-} \
-
-R7S72100_SCIF(0, 0xe8007000, gic_iid(221));
-R7S72100_SCIF(1, 0xe8007800, gic_iid(225));
-R7S72100_SCIF(2, 0xe8008000, gic_iid(229));
-R7S72100_SCIF(3, 0xe8008800, gic_iid(233));
-R7S72100_SCIF(4, 0xe8009000, gic_iid(237));
-R7S72100_SCIF(5, 0xe8009800, gic_iid(241));
-R7S72100_SCIF(6, 0xe800a000, gic_iid(245));
-R7S72100_SCIF(7, 0xe800a800, gic_iid(249));
-
-#define r7s72100_register_scif(index) \
- platform_device_register_resndata(&platform_bus, "sh-sci", index, \
- scif##index##_resources, \
- ARRAY_SIZE(scif##index##_resources), \
- &scif##index##_platform_data, \
- sizeof(scif##index##_platform_data))
-
-static struct resource mtu2_resources[] __initdata = {
- DEFINE_RES_MEM(0xfcff0000, 0x400),
- DEFINE_RES_IRQ_NAMED(gic_iid(139), "tgi0a"),
-};
-
-#define r7s72100_register_mtu2() \
- platform_device_register_resndata(&platform_bus, "sh-mtu2", \
- -1, mtu2_resources, \
- ARRAY_SIZE(mtu2_resources), \
- NULL, 0)
-
-static void __init genmai_add_standard_devices(void)
-{
- r7s72100_clock_init();
- r7s72100_register_mtu2();
-
- platform_device_register_full(ðer_info);
-
- r7s72100_register_rspi(0);
- r7s72100_register_rspi(1);
- r7s72100_register_rspi(2);
- r7s72100_register_rspi(3);
- r7s72100_register_rspi(4);
- spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
-
- r7s72100_register_scif(0);
- r7s72100_register_scif(1);
- r7s72100_register_scif(2);
- r7s72100_register_scif(3);
- r7s72100_register_scif(4);
- r7s72100_register_scif(5);
- r7s72100_register_scif(6);
- r7s72100_register_scif(7);
-}
-
-static const char * const genmai_boards_compat_dt[] __initconst = {
- "renesas,genmai",
- NULL,
-};
-
-DT_MACHINE_START(GENMAI_DT, "genmai")
- .init_early = shmobile_init_delay,
- .init_machine = genmai_add_standard_devices,
- .dt_compat = genmai_boards_compat_dt,
-MACHINE_END
--
2.0.1
^ permalink raw reply related
* [PATCH 1/3] ARM: shmobile: r7s72100: genmai: Remove reference board file
From: Simon Horman @ 2014-07-17 23:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1405641497.git.horms+renesas@verge.net.au>
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The genmai board now boots using the generic R7S72100 DT machine with
the same feature set as the board file. Remove the board file.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Wolfram Sang <wsa@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/Makefile | 1 -
arch/arm/mach-shmobile/board-genmai-reference.c | 35 -------------------------
2 files changed, 36 deletions(-)
delete mode 100644 arch/arm/mach-shmobile/board-genmai-reference.c
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index dd542e7..18b05a8 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -62,7 +62,6 @@ obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
# Board objects
ifdef CONFIG_ARCH_SHMOBILE_MULTI
-obj-$(CONFIG_MACH_GENMAI) += board-genmai-reference.o
obj-$(CONFIG_MACH_KOELSCH) += board-koelsch-reference.o
obj-$(CONFIG_MACH_LAGER) += board-lager-reference.o
obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
diff --git a/arch/arm/mach-shmobile/board-genmai-reference.c b/arch/arm/mach-shmobile/board-genmai-reference.c
deleted file mode 100644
index bc52677..0000000
--- a/arch/arm/mach-shmobile/board-genmai-reference.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Genmai board support
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- * Copyright (C) 2013 Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/kernel.h>
-
-#include <asm/mach/arch.h>
-
-#include "common.h"
-
-static const char * const genmai_boards_compat_dt[] __initconst = {
- "renesas,genmai",
- NULL,
-};
-
-DT_MACHINE_START(GENMAI_DT, "genmai")
- .init_early = shmobile_init_delay,
- .dt_compat = genmai_boards_compat_dt,
-MACHINE_END
--
2.0.1
^ permalink raw reply related
* [GIT PULL] Renesas ARM Based SoC Boards Cleanups Updates for v3.17
From: Simon Horman @ 2014-07-17 23:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these Renesas ARM based SoC Boards Cleanups updates for v3.17.
This pull request is based on a merge of:
* "Fourth Round of Renesas ARM Based SoC Defconfig Updates for v3.17",
tagged as renesas-defconfig4-for-v3.17,
which I have sent a pull request for.
The reason for this dependency is to avoid attempts to use
genmai_defconfig after the board code it relies on has been removed.
* "Renesas ARM Based SoC DT Timers Updates for v3.17",
tagged as renesas-dt-timers-for-v3.17,
which I have sent a pull request for.
The following changes since commit b34fd6184cf689db8570d89c66b9ab9742c3e813:
Merge branch 'defconfig-for-v3.17' into cleanup-boards-for-v3.17.base (2014-07-17 00:03:15 +0900)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-cleanup-boards-for-v3.17
for you to fetch changes up to 53b04e7fb3b28517ff86a7ac9fcff86101fe6d5a:
ARM: shmobile: r7s72100: Remove legacy board support (2014-07-17 00:14:44 +0900)
----------------------------------------------------------------
Renesas ARM Based SoC Boards Cleanups for v3.17
Remove Genmai board code
----------------------------------------------------------------
Laurent Pinchart (3):
ARM: shmobile: r7s72100: genmai: Remove reference board file
ARM: shmobile: r7s72100: genmai: Remove legacy board file
ARM: shmobile: r7s72100: Remove legacy board support
arch/arm/mach-shmobile/Kconfig | 17 --
arch/arm/mach-shmobile/Makefile | 3 -
arch/arm/mach-shmobile/Makefile.boot | 1 -
arch/arm/mach-shmobile/board-genmai-reference.c | 35 ----
arch/arm/mach-shmobile/board-genmai.c | 174 ------------------
arch/arm/mach-shmobile/clock-r7s72100.c | 231 ------------------------
arch/arm/mach-shmobile/r7s72100.h | 6 -
arch/arm/mach-shmobile/setup-r7s72100.c | 2 -
8 files changed, 469 deletions(-)
delete mode 100644 arch/arm/mach-shmobile/board-genmai-reference.c
delete mode 100644 arch/arm/mach-shmobile/board-genmai.c
delete mode 100644 arch/arm/mach-shmobile/clock-r7s72100.c
delete mode 100644 arch/arm/mach-shmobile/r7s72100.h
^ permalink raw reply
* [PATCH 2/2] ARM: shmobile: defconfig: Remove MACH_GENMAI
From: Simon Horman @ 2014-07-17 23:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1405640905.git.horms+renesas@verge.net.au>
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The CONFIG_MACH_GENMAI is scheduled for removal so remove it from
shmobile_defconfig.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[horms+renesas at verge.net.au: revised changelog for updated commit order]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/configs/shmobile_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 6bc85a5..3b13614 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -14,7 +14,6 @@ CONFIG_ARCH_R7S72100=y
CONFIG_ARCH_R8A7779=y
CONFIG_ARCH_R8A7790=y
CONFIG_ARCH_R8A7791=y
-CONFIG_MACH_GENMAI=y
CONFIG_MACH_KOELSCH=y
CONFIG_MACH_LAGER=y
CONFIG_MACH_MARZEN=y
--
2.0.1
^ permalink raw reply related
* [PATCH 1/2] ARM: shmobile: genmai: remove defconfig
From: Simon Horman @ 2014-07-17 23:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1405640905.git.horms+renesas@verge.net.au>
The genmai board code is scheduled for removal and once
that occurs the defconfig will be of no use. Remove it.
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/configs/genmai_defconfig | 122 --------------------------------------
1 file changed, 122 deletions(-)
delete mode 100644 arch/arm/configs/genmai_defconfig
diff --git a/arch/arm/configs/genmai_defconfig b/arch/arm/configs/genmai_defconfig
deleted file mode 100644
index d238faf..0000000
--- a/arch/arm/configs/genmai_defconfig
+++ /dev/null
@@ -1,122 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_EMBEDDED=y
-CONFIG_PERF_EVENTS=y
-CONFIG_SLAB=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE_LEGACY=y
-CONFIG_ARCH_R7S72100=y
-CONFIG_MACH_GENMAI=y
-# CONFIG_SH_TIMER_CMT is not set
-# CONFIG_SH_TIMER_MTU2 is not set
-# CONFIG_SH_TIMER_TMU is not set
-# CONFIG_EM_TIMER_STI is not set
-CONFIG_ARM_ERRATA_430973=y
-CONFIG_ARM_ERRATA_458693=y
-CONFIG_ARM_ERRATA_460075=y
-CONFIG_ARM_ERRATA_743622=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_FORCE_MAX_ZONEORDER=13
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_KEXEC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_CORE is not set
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_CADENCE is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-CONFIG_SH_ETH=y
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=10
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_RIIC=y
-CONFIG_SPI=y
-CONFIG_SPI_RSPI=y
-# CONFIG_HWMON is not set
-CONFIG_THERMAL=y
-CONFIG_RCAR_THERMAL=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_DRM=y
-CONFIG_DRM_RCAR_DU=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SDHI=y
-CONFIG_MMC_SH_MMCIF=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_RTC_CLASS=y
-CONFIG_DMADEVICES=y
-CONFIG_SH_DMAE=y
-# CONFIG_IOMMU_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NFS_V4_1=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_ARM_UNWIND is not set
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
--
2.0.1
^ permalink raw reply related
* [GIT PULL] Fourth Round of Renesas ARM Based SoC Defconfig Updates for v3.17
From: Simon Horman @ 2014-07-17 23:55 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these fourth round of Renesas ARM based SoC defconfig
updates for v3.17.
This pull request is based on the previous round of
such requests, tagged as renesas-defconfig3-for-v3.17,
which you have merged into renesas/defconfig3.
I will follow-up with a pull request that removes
the Genmai board code.
The following changes since commit 8cbf869a0a278c4d39e50daa4f4101b394a72a93:
ARM: shmobile: Enable R-Car Gen 2 PCIe in shmobile_defconfig (2014-07-09 10:44:12 +0200)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-defconfig4-for-v3.17
for you to fetch changes up to 92db2b7af591d3c3212183a34856b4cb190b6999:
ARM: shmobile: defconfig: Remove MACH_GENMAI (2014-07-17 00:02:34 +0900)
----------------------------------------------------------------
Fourth Round of Renesas ARM Based SoC Defconfig Updates for v3.17
The genmai board code is going away so remove:
* The genmai defconfig
* MACH_GENMAI from shmobile defconfig
----------------------------------------------------------------
Laurent Pinchart (1):
ARM: shmobile: defconfig: Remove MACH_GENMAI
Simon Horman (1):
ARM: shmobile: genmai: remove defconfig
arch/arm/configs/genmai_defconfig | 122 ------------------------------------
arch/arm/configs/shmobile_defconfig | 1 -
2 files changed, 123 deletions(-)
delete mode 100644 arch/arm/configs/genmai_defconfig
^ permalink raw reply
* [PATCH] PM / OPP: cpufreq: Avoid sleeping while atomic
From: Stephen Boyd @ 2014-07-17 23:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKohpond9aNvX+x--G7AADkRhAu1iZ5mFW8pDvAXJ6yp_CCH_A@mail.gmail.com>
On 07/16/14 22:26, Viresh Kumar wrote:
> On 17 July 2014 05:05, Stephen Boyd <sboyd@codeaurora.org> wrote:
>> We allocate the cpufreq table after calling rcu_read_lock(),
>> which disables preemption. This causes scheduling while atomic
>> warnings. Use GFP_ATOMIC instead of GFP_KERNEL and update for
>> kcalloc while we're here.
> I am surprised to see that this isn't reported by anybody since the time
> it came into existence? Some special config option required to observe
> this?
First you need to enable sleeping while atomic checking, but in reality,
I assume nobody has tried inserting a cpufreq driver as a module. The
might_sleep() code has a check to see if the system_state is
SYSTEM_RUNNING. If it isn't running then there isn't a warning and
might_sleep() doesn't flag any problem. I wonder if that is actually the
right thing to do though? Perhaps the intention of that code is to skip
warning early on in the boot path when the scheduler isn't up and
running yet. But once the scheduler is running (which is fairly early
nowadays) I would think we want might_sleep() to trigger warnings. Maybe
that check in might_sleep() needs to be updated to check for "scheduler
running" instead of "system running"?
>
>> BUG: sleeping function called from invalid context at mm/slub.c:1246
>> in_atomic(): 0, irqs_disabled(): 0, pid: 80, name: modprobe
>> 5 locks held by modprobe/80:
>> #0: (&dev->mutex){......}, at: [<c050d484>] __driver_attach+0x48/0x98
>> #1: (&dev->mutex){......}, at: [<c050d494>] __driver_attach+0x58/0x98
>> #2: (subsys mutex#5){+.+.+.}, at: [<c050c114>] subsys_interface_register+0x38/0xc8
>> #3: (cpufreq_rwsem){.+.+.+}, at: [<c05a9c8c>] __cpufreq_add_dev.isra.22+0x84/0x92c
>> #4: (rcu_read_lock){......}, at: [<c05ab24c>] dev_pm_opp_init_cpufreq_table+0x18/0x10c
>> Preemption disabled at:[< (null)>] (null)
>>
>> CPU: 2 PID: 80 Comm: modprobe Not tainted 3.16.0-rc3-next-20140701-00035-g286857f216aa-dirty #217
>> [<c0214da8>] (unwind_backtrace) from [<c02123f8>] (show_stack+0x10/0x14)
>> [<c02123f8>] (show_stack) from [<c070141c>] (dump_stack+0x70/0xbc)
>> [<c070141c>] (dump_stack) from [<c02f4cb0>] (__kmalloc+0x124/0x250)
>> [<c02f4cb0>] (__kmalloc) from [<c05ab270>] (dev_pm_opp_init_cpufreq_table+0x3c/0x10c)
>> [<c05ab270>] (dev_pm_opp_init_cpufreq_table) from [<bf000508>] (cpufreq_init+0x48/0x378 [cpufreq_generic])
>> [<bf000508>] (cpufreq_init [cpufreq_generic]) from [<c05a9e08>] (__cpufreq_add_dev.isra.22+0x200/0x92c)
>> [<c05a9e08>] (__cpufreq_add_dev.isra.22) from [<c050c160>] (subsys_interface_register+0x84/0xc8)
>> [<c050c160>] (subsys_interface_register) from [<c05a9494>] (cpufreq_register_driver+0x108/0x2d8)
>> [<c05a9494>] (cpufreq_register_driver) from [<bf000888>] (generic_cpufreq_probe+0x50/0x74 [cpufreq_generic])
>> [<bf000888>] (generic_cpufreq_probe [cpufreq_generic]) from [<c050e994>] (platform_drv_probe+0x18/0x48)
>> [<c050e994>] (platform_drv_probe) from [<c050d1f4>] (driver_probe_device+0x128/0x370)
>> [<c050d1f4>] (driver_probe_device) from [<c050d4d0>] (__driver_attach+0x94/0x98)
>> [<c050d4d0>] (__driver_attach) from [<c050b778>] (bus_for_each_dev+0x54/0x88)
>> [<c050b778>] (bus_for_each_dev) from [<c050c894>] (bus_add_driver+0xe8/0x204)
>> [<c050c894>] (bus_add_driver) from [<c050dd48>] (driver_register+0x78/0xf4)
>> [<c050dd48>] (driver_register) from [<c0208870>] (do_one_initcall+0xac/0x1d8)
>> [<c0208870>] (do_one_initcall) from [<c028b6b4>] (load_module+0x190c/0x21e8)
>> [<c028b6b4>] (load_module) from [<c028c034>] (SyS_init_module+0xa4/0x110)
>> [<c028c034>] (SyS_init_module) from [<c020f0c0>] (ret_fast_syscall+0x0/0x48)
>>
>> Fixes: a0dd7b79657b "PM / OPP: Move cpufreq specific OPP functions out of generic OPP library"
> That looks to be wrong. This commit just moved things around and I can still
> see rcu_read_lock() before this commit.
>
Right. It seems that we moved to RCU in commit
0f5c890e9b9754d9aa5bf6ae2fc00cae65780d23 so the real Fixes line should be:
Fixes: 0f5c890e9b97 "PM / OPP: Remove cpufreq wrapper dependency on
internal data organization"
One way to avoid this problem is to put things back the way they were
before that change. Is there any real benefit to having this code live
in drivers/cpufreq/ instead of just under some config option in
drivers/base/power/opp.c?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* [PATCH v2 0/4] Support for Qualcomm QPNP PMIC's
From: Stephen Boyd @ 2014-07-17 23:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405613855-27572-1-git-send-email-svarbanov@mm-sol.com>
On 07/17/14 09:17, Stanimir Varbanov wrote:
> Hello everyone,
>
> Here is the continuation of patch sets sent recently about Qualcomm
> QPNP SPMI PMICs.
>
> The previous version of the patch set can be found at [1].
>
> Changes since v1:
> - removed completely custom *of* parser
> - renamed the mfd driver from qpnp-spmi to pm8xxx-spmi
> - now MFD_PM8XXX_SPMI Kconfig option depends on SPMI
>
> Removing of the custom *of* parser leads to that that the *reg* devicetree
> property cannot exist and therefore cannot be parsed to get PMIC peripheral
> resources. I took this step aside because no one from mfd drivers does this
> parsing. This will lead to inconvenience in the peripheral drivers to define
> internally the SPMI base addresses depending on the compatible property
> i.e. PMIC version.
We should teach the of platform layer to translate reg properties up
until the point that they can't be translated anymore. If they can't be
translated all the way back to cpu addresses we can make the resource
have IORESOURCE_REG instead of IORESOURCE_MEM and then said pmic
platform drivers can use platform_get_resource() with IORESOURCE_REG
instead of IORESOURCE_MEM to get the addresses.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* [PATCH] ARM: config: update multi_v7_defconfig
From: Javier Martinez Canillas @ 2014-07-17 22:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140717224413.GA21766@n2100.arm.linux.org.uk>
Hello Russell,
On Fri, Jul 18, 2014 at 12:44 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Fri, Jul 18, 2014 at 12:31:48AM +0200, Javier Martinez Canillas wrote:
>> In the case of the MAX77686, the mfd, regulator and clock drivers use
>> subsys_initcall() instead of module_init() but I wonder which of these
>> really need to be initialized at subsys init call time and which one
>> can just be built as a module.
>
> I think you're making a frequently made mistake concerning module
> initialisation.
>
> Having code initialised by subsys_initcall() (or indeed any other level)
> does not preclude it being a module:
>
> #ifndef MODULE
> ...
> #define subsys_initcall(fn) __define_initcall(fn, 4)
> ...
> #else /* MODULE */
> ...
> #define subsys_initcall(fn) module_init(fn)
> ...
> #endif
>
> So, subsys_initcall() automagically becomes module_init() when built
> as a module. There's no need to change anything here.
>
I was indeed confused, I should had looked at include/linux/init.h
before. Thanks a lot for the clarification.
Best regards,
Javier
^ permalink raw reply
* [PATCH] ARM: config: update multi_v7_defconfig
From: Russell King - ARM Linux @ 2014-07-17 22:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CABxcv==+cwoXA=WM3E7Zb62T0Epgqg_oH3UNU0vEe2DDPiCYPA@mail.gmail.com>
On Fri, Jul 18, 2014 at 12:31:48AM +0200, Javier Martinez Canillas wrote:
> In the case of the MAX77686, the mfd, regulator and clock drivers use
> subsys_initcall() instead of module_init() but I wonder which of these
> really need to be initialized at subsys init call time and which one
> can just be built as a module.
I think you're making a frequently made mistake concerning module
initialisation.
Having code initialised by subsys_initcall() (or indeed any other level)
does not preclude it being a module:
#ifndef MODULE
...
#define subsys_initcall(fn) __define_initcall(fn, 4)
...
#else /* MODULE */
...
#define subsys_initcall(fn) module_init(fn)
...
#endif
So, subsys_initcall() automagically becomes module_init() when built
as a module. There's no need to change anything here.
--
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH v3] ARM: dts: Add cros_ec to exynos5420-peach-pit and exynos5800-peach-pi
From: Javier Martinez Canillas @ 2014-07-17 22:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1403627332-4688-1-git-send-email-dianders@chromium.org>
Hello Kukjin,
On 06/24/2014 06:28 PM, Doug Anderson wrote:
> This adds cros_ec to exynos5420-peach-pit and exynos5800-peach-pi,
> including:
> * The keyboard
> * The i2c tunnel
> * The tps65090 under the i2c tunnel
> * The battery under the i2c tunnel
>
> To add extra motivation, it should be noted that tps65090 is one of
> the things needed to get display-related FETs turned on for pit and
> pi.
>
> Note that this relies on a few outstanding changes:
> * Needs (spi: s3c64xx: fix broken "cs_gpios" usage in the driver) and
> (spi: s3c64xx: for DT platofrms always get the chipselect info from
> DT node) to work properly and match the documented bindings. See
> <https://patchwork.kernel.org/patch/4346701/> and
> <https://patchwork.kernel.org/patch/4346711/>
>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> Tested-by: Tushar Behera <tushar.b@samsung.com>
>
Mark Brown as already applied the SPI DT binding fix from Naveen [0] which was
the dependency for this patch and he said that will try to send the whole series
to Torvalds before the 3.16-rc cycle ends.
So I think that it's safe now if you want to pick this patch.
Thanks a lot!
Best regards,
Javier
[0]:
https://git.kernel.org/cgit/linux/kernel/git/broonie/spi.git/commit/?h=for-next&id=306972cedfdedc662dd8e32a6397d0e29f2ac90e
^ permalink raw reply
* [PATCH] ARM: config: update multi_v7_defconfig
From: Javier Martinez Canillas @ 2014-07-17 22:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAD=FV=UFknqF_Mt7ArytFq4KdDsGDa+JR2KZzX9Xn+if-_Vw4g@mail.gmail.com>
Hello,
On Tue, Jul 15, 2014 at 5:59 PM, Doug Anderson <dianders@chromium.org> wrote:
>
> Is there a reason not to add more of the max77686 configs?
>
> +CONFIG_RTC_DRV_MAX77686=y
> +CONFIG_COMMON_CLK_MAX77686=y
AFAIK for the multi-platform defconfig we should try to build as a
module as many config options as possible to keep the kernel binary
size to a minimum.
In the case of the MAX77686, the mfd, regulator and clock drivers use
subsys_initcall() instead of module_init() but I wonder which of these
really need to be initialized at subsys init call time and which one
can just be built as a module. The only MAX77686 driver that uses
module_platform_driver() so it's initialized at device initcall time
is the rtc-max77686 driver which ironically is the only MAX77686
driver that doesn't define a MODULE_DEVICE_TABLE() so the module won't
be autoloaded.
Best regards,
Javier
^ permalink raw reply
* [PATCH] ARM: rockchip: Add cpu hotplug support for RK3XXX SoCs
From: Russell King - ARM Linux @ 2014-07-17 22:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405617110-1136-1-git-send-email-romain.perier@gmail.com>
On Thu, Jul 17, 2014 at 05:11:50PM +0000, Romain Perier wrote:
> +static DECLARE_COMPLETION(cpu_died);
> +
> +static int rockchip_cpu_kill(unsigned int cpu)
> +{
> + if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(1000))) {
> + pr_err("CPU%d: didn't die correctly\n", cpu);
> + return 0;
> + }
Please explain the point of this cpu_died thing.
I think you should read arch/arm/kernel/smp.c, searching for cpu_died
in there.
--
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH] CMA: generalize CMA reserved area management functionality (fixup)
From: Andrew Morton @ 2014-07-17 22:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405589767-17513-1-git-send-email-m.szyprowski@samsung.com>
On Thu, 17 Jul 2014 11:36:07 +0200 Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> MAX_CMA_AREAS is used by other subsystems (i.e. arch/arm/mm/dma-mapping.c),
> so we need to provide correct definition even if CMA is disabled.
> This patch fixes this issue.
>
> Reported-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> include/linux/cma.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/linux/cma.h b/include/linux/cma.h
> index 9a18a2b1934c..c077635cad76 100644
> --- a/include/linux/cma.h
> +++ b/include/linux/cma.h
> @@ -5,7 +5,11 @@
> * There is always at least global CMA area and a few optional
> * areas configured in kernel .config.
> */
> +#ifdef CONFIG_CMA
> #define MAX_CMA_AREAS (1 + CONFIG_CMA_AREAS)
> +#else
> +#define MAX_CMA_AREAS (0)
> +#endif
>
> struct cma;
Joonsoo already fixed this up, a bit differently:
http://ozlabs.org/~akpm/mmots/broken-out/cma-generalize-cma-reserved-area-management-functionality-fix.patch
Which approach makes more sense?
From: Joonsoo Kim <iamjoonsoo.kim@lge.com>
Subject: CMA: fix ARM build failure related to MAX_CMA_AREAS definition
If CMA is disabled, CONFIG_CMA_AREAS isn't defined so compile error
happens. To fix it, define MAX_CMA_AREAS if CONFIG_CMA_AREAS
isn't defined.
Signed-off-by: Joonsoo Kim <iamjoonsoo.kim@lge.com>
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
include/linux/cma.h | 6 ++++++
1 file changed, 6 insertions(+)
diff -puN include/linux/cma.h~cma-generalize-cma-reserved-area-management-functionality-fix include/linux/cma.h
--- a/include/linux/cma.h~cma-generalize-cma-reserved-area-management-functionality-fix
+++ a/include/linux/cma.h
@@ -5,8 +5,14 @@
* There is always at least global CMA area and a few optional
* areas configured in kernel .config.
*/
+#ifdef CONFIG_CMA_AREAS
#define MAX_CMA_AREAS (1 + CONFIG_CMA_AREAS)
+#else
+#define MAX_CMA_AREAS (0)
+
+#endif
+
struct cma;
extern phys_addr_t cma_get_base(struct cma *cma);
_
^ permalink raw reply
* [PATCH v2 1/8] dma: sun4i: Add support for the DMA engine on sun[457]i SoCs
From: Emilio López @ 2014-07-17 21:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140717205639.GH20328@lukather>
Hi Maxime,
El 17/07/14 17:56, Maxime Ripard escribi?:
> On Sun, Jul 06, 2014 at 01:05:08AM -0300, Emilio L?pez wrote:
>> This patch adds support for the DMA engine present on Allwinner A10,
>> A13, A10S and A20 SoCs. This engine has two kinds of channels: normal
>> and dedicated. The main difference is in the mode of operation;
>> while a single normal channel may be operating at any given time,
>> dedicated channels may operate simultaneously provided there is no
>> overlap of source or destination.
>>
>> Hardware documentation can be found on A10 User Manual (section 12), A13
>> User Manual (section 14) and A20 User Manual (section 1.12)
>>
>> Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
>> ---
>>(...)
>>
>> +config SUN4I_DMA
>> + tristate "Allwinner A10/A10S/A13/A20 DMA support"
>
> I'm not that fond of having an exhaustive list here. If some other SoC
> we didn't thought of or get a new SoC that uses this controller, this
> list won't be exhaustive anymore, which is even worse.
>
> Just mention the A10.
Ok
>> + depends on (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || (COMPILE_TEST && OF && ARM))
>
> This pretty much defeats the purpose of COMPILE_TEST
QCOM_BAM_DMA does it that way; it's better to get some coverage than
none I guess?
>
>> + select DMA_ENGINE
>> + select DMA_OF
>> + select DMA_VIRTUAL_CHANNELS
>
> I guess you could default to y for the SoCs where it's relevant.
Sounds good.
>
>> + help
>> + Enable support for the DMA controller present in the sun4i,
>> + sun5i and sun7i Allwinner ARM SoCs.
>> +
(...)
>> +
>> +/** Normal DMA register values **/
>> +
>> +/* Normal DMA source/destination data request type values */
>> +#define NDMA_DRQ_TYPE_SDRAM 0x16
>> +#define NDMA_DRQ_TYPE_LIMIT (0x1F + 1)
>
> Hmmm, I'm unsure what this is about... What is it supposed to do, and
> how is it different from BIT(5) ?
if (val < NDMA_DRQ_TYPE_LIMIT)
/* valid value */
else
/* invalid value */
0x1F is the last valid value
(...)
>> +
>> +static void set_pchan_interrupt(struct sun4i_dma_dev *priv,
>> + struct sun4i_dma_pchan *pchan,
>> + int half, int end)
>> +{
>> + u32 reg = readl_relaxed(priv->base + DMA_IRQ_ENABLE_REG);
>> + int pchan_number = pchan - priv->pchans;
>> +
>> + if (half)
>> + reg |= BIT(pchan_number * 2);
>> + else
>> + reg &= ~BIT(pchan_number * 2);
>> +
>> + if (end)
>> + reg |= BIT(pchan_number * 2 + 1);
>> + else
>> + reg &= ~BIT(pchan_number * 2 + 1);
>> +
>> + writel_relaxed(reg, priv->base + DMA_IRQ_ENABLE_REG);
>
> I don't see any interrupts here.
Hm?
> Is this suppose to be called with a
> lock taken? If so, it should be mentionned in some comment.
Good point, this should probably take a lock, I'll get it fixed.
(...)
>> +{
>> + struct sun4i_dma_contract *contract = to_sun4i_dma_contract(vd);
>> + struct sun4i_dma_promise *promise;
>> +
>> + /* Free all the demands and completed demands */
>> + list_for_each_entry(promise, &contract->demands, list) {
>> + kfree(promise);
>> + }
>> +
>> + list_for_each_entry(promise, &contract->completed_demands, list) {
>> + kfree(promise);
>> + }
>>
>
> Those brackets are useless.
Indeed, dropped.
>> + for_each_sg(sgl, sg, sg_len, i) {
>> + /* Figure out addresses */
>> + if (dir == DMA_MEM_TO_DEV) {
>> + srcaddr = sg_dma_address(sg);
>> + dstaddr = sconfig->dst_addr;
>> + } else {
>> + srcaddr = sconfig->src_addr;
>> + dstaddr = sg_dma_address(sg);
>> + }
>> +
>> + /* TODO: should this be configurable? */
>> + para = DDMA_MAGIC_SPI_PARAMETERS;
>
> What is it? Is it supposed to change from one client device to
> another?
These are the magic DMA engine timings that keep SPI going. I haven't
seen any interface on DMAEngine to configure timings, and so far they
seem to work for everything we support, so I've kept them here. I don't
know if other devices need different timings because, as usual, we only
have the "para" bitfield meanings, but no comment on what the values
should be when doing a certain operation :|
>> +
>> + /* And make a suitable promise */
>> + if (vchan->is_dedicated)
>> + promise = generate_ddma_promise(chan, srcaddr, dstaddr,
>> + sg_dma_len(sg), sconfig);
>> + else
>> + promise = generate_ndma_promise(chan, srcaddr, dstaddr,
>> + sg_dma_len(sg), sconfig);
>> +
>> + if (!promise)
>> + return NULL; /* TODO */
>
> TODO what?
/* TODO: properly kfree the promises generated in the loop */
(...)
>> +static enum dma_status sun4i_dma_tx_status(struct dma_chan *chan,
>> + dma_cookie_t cookie,
>> + struct dma_tx_state *state)
>> +{
>> + struct sun4i_dma_vchan *vchan = to_sun4i_dma_vchan(chan);
>> + struct sun4i_dma_pchan *pchan = vchan->pchan;
>> + struct sun4i_dma_contract *contract;
>> + struct sun4i_dma_promise *promise;
>> + struct virt_dma_desc *vd;
>> + unsigned long flags;
>> + enum dma_status ret;
>> + size_t bytes = 0;
>> +
>> + ret = dma_cookie_status(chan, cookie, state);
>> + if (ret == DMA_COMPLETE)
>> + return ret;
>> +
>> + spin_lock_irqsave(&vchan->vc.lock, flags);
>> + vd = vchan_find_desc(&vchan->vc, cookie);
>> + if (!vd) /* TODO */
>
> TODO what?
>
/* TODO: remove the TODO */
>> + goto exit;
>> + contract = to_sun4i_dma_contract(vd);
>> +
>> + list_for_each_entry(promise, &contract->demands, list) {
>> + bytes += promise->len;
>> + }
>
> Useless brackets
Dropped
Thanks for taking the time to review this!
Cheers,
Emilio
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