* [PATCH 0/2] Convert exynos PPMU driver to be built as module
From: Punit Agrawal @ 2014-07-18 14:09 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
There's no reason why the exynos PPMU can't be built as a module
except you need -
- The first patch exports the functions that are needed to build
devfreq drivers as modules.
- The second patch then converts the exynos PPMU devfreq driver to be
built as a module.
Compile tested only.
Thanks
Punit Agrawal (1):
PM / devfreq: exynos: Enable building exynos PPMU as module
?rjan Eide (1):
PM / devfreq: Export helper functions for drivers
drivers/devfreq/Kconfig | 2 +-
drivers/devfreq/devfreq.c | 3 +++
drivers/devfreq/exynos/exynos_ppmu.c | 3 +++
3 files changed, 7 insertions(+), 1 deletion(-)
--
1.7.10.4
^ permalink raw reply
* [PATCH 1/2] PM / devfreq: Export helper functions for drivers
From: Punit Agrawal @ 2014-07-18 14:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405692594-19352-1-git-send-email-punit.agrawal@arm.com>
From: ?rjan Eide <orjan.eide@arm.com>
These functions are indended for use by drivers and should be available
also when the driver is built as a module.
Cc: MyungJoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: ?rjan Eide <orjan.eide@arm.com>
---
drivers/devfreq/devfreq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 9f90369..30b538d8 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -1119,6 +1119,7 @@ struct dev_pm_opp *devfreq_recommended_opp(struct device *dev,
return opp;
}
+EXPORT_SYMBOL(devfreq_recommended_opp);
/**
* devfreq_register_opp_notifier() - Helper function to get devfreq notified
@@ -1142,6 +1143,7 @@ int devfreq_register_opp_notifier(struct device *dev, struct devfreq *devfreq)
return ret;
}
+EXPORT_SYMBOL(devfreq_register_opp_notifier);
/**
* devfreq_unregister_opp_notifier() - Helper function to stop getting devfreq
@@ -1168,6 +1170,7 @@ int devfreq_unregister_opp_notifier(struct device *dev, struct devfreq *devfreq)
return ret;
}
+EXPORT_SYMBOL(devfreq_unregister_opp_notifier);
static void devm_devfreq_opp_release(struct device *dev, void *res)
{
--
1.7.10.4
^ permalink raw reply related
* [PATCH 2/2] PM / devfreq: exynos: Enable building exynos PPMU as module
From: Punit Agrawal @ 2014-07-18 14:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405692594-19352-1-git-send-email-punit.agrawal@arm.com>
Export symbols from the PPMU driver needed to build the exynos bus
driver as a module.
Cc: MyungJoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
---
drivers/devfreq/Kconfig | 2 +-
drivers/devfreq/exynos/exynos_ppmu.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 49e74c1..77bf126 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -79,7 +79,7 @@ config ARM_EXYNOS4_BUS_DEVFREQ
This does not yet operate with optimal voltages.
config ARM_EXYNOS5_BUS_DEVFREQ
- bool "ARM Exynos5250 Bus DEVFREQ Driver"
+ tristate "ARM Exynos5250 Bus DEVFREQ Driver"
depends on SOC_EXYNOS5250
select ARCH_HAS_OPP
select DEVFREQ_GOV_SIMPLE_ONDEMAND
diff --git a/drivers/devfreq/exynos/exynos_ppmu.c b/drivers/devfreq/exynos/exynos_ppmu.c
index 75fcc51..97b75e5 100644
--- a/drivers/devfreq/exynos/exynos_ppmu.c
+++ b/drivers/devfreq/exynos/exynos_ppmu.c
@@ -73,6 +73,7 @@ void busfreq_mon_reset(struct busfreq_ppmu_data *ppmu_data)
exynos_ppmu_start(ppmu_base);
}
}
+EXPORT_SYMBOL(busfreq_mon_reset);
void exynos_read_ppmu(struct busfreq_ppmu_data *ppmu_data)
{
@@ -97,6 +98,7 @@ void exynos_read_ppmu(struct busfreq_ppmu_data *ppmu_data)
busfreq_mon_reset(ppmu_data);
}
+EXPORT_SYMBOL(exynos_read_ppmu);
int exynos_get_busier_ppmu(struct busfreq_ppmu_data *ppmu_data)
{
@@ -114,3 +116,4 @@ int exynos_get_busier_ppmu(struct busfreq_ppmu_data *ppmu_data)
return busy;
}
+EXPORT_SYMBOL(exynos_get_busier_ppmu);
--
1.7.10.4
^ permalink raw reply related
* [GIT PULL] at91: fixes for 3.16 #2
From: Nicolas Ferre @ 2014-07-18 14:12 UTC (permalink / raw)
To: linux-arm-kernel
Arnd, Olof, Kevin,
This is the latest regressions that we found while testing the at91sam9n12 and
at91sam9x5 platforms following our move to CCF.
I created a pull-request this time because I have 3 patches: there should be
no conflict anyway. This tag does not contain the fix that Olof had taken during
previous -rc cycle on purpose: this way it won't appear twice in the history.
Thanks, best regards,
The following changes since commit 971dc9ce106110745f246337f229013589354536:
ARM: at91/dt: sam9261: remove slow RC osc (2014-06-25 18:00:17 +0200)
are available in the git repository at:
git://github.com/at91linux/linux-at91.git tags/at91-fixes
for you to fetch changes up to e0d69e119fc6bf7cc3c9f791478108c1b925bb2e:
ARM: at91/dt: add missing clocks property to pwm node in sam9x5.dtsi (2014-07-18 15:56:35 +0200)
----------------------------------------------------------------
Second AT91 fixes series for 3.16
- fix clock definitions after the move to CCF for:
- at91sam9n12 (ohci)
- at91sam9x5 (ohci, pwm)
----------------------------------------------------------------
Bo Shen (1):
ARM: at91: at91sam9x5: correct typo error for ohci clock
Boris BREZILLON (2):
ARM: at91/dt: fix usb0 clocks definition in sam9n12 dtsi
ARM: at91/dt: add missing clocks property to pwm node in sam9x5.dtsi
arch/arm/boot/dts/at91sam9n12.dtsi | 2 +-
arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
--
Nicolas Ferre
^ permalink raw reply
* [PATCHv4 3/5] common: dma-mapping: Introduce common remapping functions
From: Catalin Marinas @ 2014-07-18 14:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOesGMimCAYnqxkKoYpZ2ws7x9eH4K1Yw3LnLz9HC6MWyHEo3A@mail.gmail.com>
On Wed, Jul 09, 2014 at 11:46:56PM +0100, Olof Johansson wrote:
> On Wed, Jul 2, 2014 at 11:03 AM, Laura Abbott <lauraa@codeaurora.org> wrote:
> > For architectures without coherent DMA, memory for DMA may
> > need to be remapped with coherent attributes. Factor out
> > the the remapping code from arm and put it in a
> > common location to reduced code duplication.
> >
> > Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
>
> Hm. The switch from ioremap to map_vm_area() here seems to imply that
> lib/ioremap can/should be reworked to use just wrap the vmalloc
> functions too?
ioremap_page_range() does not require the allocation of a map page array
and assumes that the mapped memory is physically contiguous. This would
be more efficient than the vmap() implementation which is generic enough
to allow non-contiguous memory allocations.
At some point, we'll have to support SMMU on arm64 and we can have 4
combinations of coherency and IOMMU. When an IOMMU is present, we don't
require physically contiguous memory but we may require non-cacheable
mappings, in which case vmap comes in handy.
--
Catalin
^ permalink raw reply
* [PATCH 0/6] net/macb: add HW features to macb driver
From: Cyrille Pitchen @ 2014-07-18 14:21 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
this series of patches adds new hardware features to macb driver. These
features can be enabled/disabled at runtime using ethtool. Depending on
hardware and design configuration, some are enabled by default whereas other
are disabled.
For instance, checksum offload features are enabled by default for gem designed
for packet buffer mode but disabled for fifo mode design or for old macb.
Besides, the scatter-gather feature is enabled and tested on macb but disabled
on sama5d3x gem. When testing this feature on sama5d3x gem, TX lockups occured
frequently.
These patches were made for net-next.git repository.
Cyrille Pitchen (5):
net/macb: add scatter-gather hw feature
net/macb: add TX checksum offload feature
net/macb: add RX checksum offload feature
ARM: at91: change compatibility string for sama5d3x gem
net/macb: enable scatter-gather feature and set DMA burst length for
sama5d4 gem
Nicolas Ferre (1):
net/macb: configure for FIFO mode and non-gigabit
arch/arm/boot/dts/sama5d3_gmac.dtsi | 2 +-
drivers/net/ethernet/cadence/macb.c | 409 ++++++++++++++++++++++++++++++------
drivers/net/ethernet/cadence/macb.h | 36 +++-
3 files changed, 375 insertions(+), 72 deletions(-)
--
1.8.2.2
^ permalink raw reply
* [PATCH 1/6] net/macb: configure for FIFO mode and non-gigabit
From: Cyrille Pitchen @ 2014-07-18 14:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1405689937.git.cyrille.pitchen@atmel.com>
From: Nicolas Ferre <nicolas.ferre@atmel.com>
This addition will also allow to configure DMA burst length.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/net/ethernet/cadence/macb.c | 72 +++++++++++++++++++++++++++----------
drivers/net/ethernet/cadence/macb.h | 19 ++++++++--
2 files changed, 71 insertions(+), 20 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index e9daa07..0896d88 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -264,7 +264,8 @@ static void macb_handle_link_change(struct net_device *dev)
reg |= MACB_BIT(FD);
if (phydev->speed == SPEED_100)
reg |= MACB_BIT(SPD);
- if (phydev->speed == SPEED_1000)
+ if (phydev->speed == SPEED_1000
+ && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
reg |= GEM_BIT(GBE);
macb_or_gem_writel(bp, NCFGR, reg);
@@ -337,7 +338,7 @@ static int macb_mii_probe(struct net_device *dev)
}
/* mask with MAC supported features */
- if (macb_is_gem(bp))
+ if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
phydev->supported &= PHY_GBIT_FEATURES;
else
phydev->supported &= PHY_BASIC_FEATURES;
@@ -1342,7 +1343,7 @@ static u32 macb_dbw(struct macb *bp)
/*
* Configure the receive DMA engine
* - use the correct receive buffer size
- * - set the possibility to use INCR16 bursts
+ * - set best burst length for DMA operations
* (if not supported by FIFO, it will fallback to default)
* - set both rx/tx packet buffers to full memory size
* These are configurable parameters for GEM.
@@ -1354,24 +1355,15 @@ static void macb_configure_dma(struct macb *bp)
if (macb_is_gem(bp)) {
dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
- dmacfg |= GEM_BF(FBLDO, 16);
+ if (bp->dma_burst_length)
+ dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
dmacfg &= ~GEM_BIT(ENDIA);
+ netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n", dmacfg);
gem_writel(bp, DMACFG, dmacfg);
}
}
-/*
- * Configure peripheral capacities according to integration options used
- */
-static void macb_configure_caps(struct macb *bp)
-{
- if (macb_is_gem(bp)) {
- if (GEM_BFEXT(IRQCOR, gem_readl(bp, DCFG1)) == 0)
- bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
- }
-}
-
static void macb_init_hw(struct macb *bp)
{
u32 config;
@@ -1394,7 +1386,6 @@ static void macb_init_hw(struct macb *bp)
bp->duplex = DUPLEX_HALF;
macb_configure_dma(bp);
- macb_configure_caps(bp);
/* Initialize TX and RX buffers */
macb_writel(bp, RBQP, bp->rx_ring_dma);
@@ -1783,17 +1774,59 @@ static const struct net_device_ops macb_netdev_ops = {
};
#if defined(CONFIG_OF)
+static struct macb_config pc302gem_config = {
+ .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE,
+ .dma_burst_length = 16,
+};
+
static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,at32ap7000-macb" },
{ .compatible = "cdns,at91sam9260-macb" },
{ .compatible = "cdns,macb" },
- { .compatible = "cdns,pc302-gem" },
- { .compatible = "cdns,gem" },
+ { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
+ { .compatible = "cdns,gem", .data = &pc302gem_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, macb_dt_ids);
#endif
+/*
+ * Configure peripheral capacities according to device tree
+ * and integration options used
+ */
+static void macb_configure_caps(struct macb *bp)
+{
+ u32 dcfg;
+ const struct of_device_id *match;
+
+ if (bp->pdev->dev.of_node) {
+ match = of_match_node(macb_dt_ids, bp->pdev->dev.of_node);
+ if (match && match->data) {
+ bp->caps = ((struct macb_config *)match->data)->caps;
+ /*
+ * As we have access to the matching node, configure
+ * DMA burst length as well
+ */
+ bp->dma_burst_length =
+ ((struct macb_config *)match->data)->dma_burst_length;
+ }
+ }
+
+ if (MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2)
+ bp->caps |= MACB_CAPS_MACB_IS_GEM;
+
+ if (macb_is_gem(bp)) {
+ dcfg = gem_readl(bp, DCFG1);
+ if (GEM_BFEXT(IRQCOR, dcfg) == 0)
+ bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
+ dcfg = gem_readl(bp, DCFG2);
+ if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
+ bp->caps |= MACB_CAPS_FIFO_MODE;
+ }
+
+ netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
+}
+
static int __init macb_probe(struct platform_device *pdev)
{
struct macb_platform_data *pdata;
@@ -1897,6 +1930,9 @@ static int __init macb_probe(struct platform_device *pdev)
dev->base_addr = regs->start;
+ /* setup capacities */
+ macb_configure_caps(bp);
+
/* setup appropriated routines according to adapter type */
if (macb_is_gem(bp)) {
bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 51c0244..7ce751b 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -305,6 +305,12 @@
#define GEM_DBWDEF_OFFSET 25
#define GEM_DBWDEF_SIZE 3
+/* Bitfields in DCFG2. */
+#define GEM_RX_PKT_BUFF_OFFSET 20
+#define GEM_RX_PKT_BUFF_SIZE 1
+#define GEM_TX_PKT_BUFF_OFFSET 21
+#define GEM_TX_PKT_BUFF_SIZE 1
+
/* Constants for CLK */
#define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1
@@ -326,7 +332,10 @@
#define MACB_MAN_CODE 2
/* Capability mask bits */
-#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x1
+#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
+#define MACB_CAPS_FIFO_MODE 0x10000000
+#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
+#define MACB_CAPS_MACB_IS_GEM 0x80000000
/* Bit manipulation macros */
#define MACB_BIT(name) \
@@ -554,6 +563,11 @@ struct macb_or_gem_ops {
int (*mog_rx)(struct macb *bp, int budget);
};
+struct macb_config {
+ u32 caps;
+ unsigned int dma_burst_length;
+};
+
struct macb {
void __iomem *regs;
@@ -595,6 +609,7 @@ struct macb {
unsigned int duplex;
u32 caps;
+ unsigned int dma_burst_length;
phy_interface_t phy_interface;
@@ -615,7 +630,7 @@ void macb_get_hwaddr(struct macb *bp);
static inline bool macb_is_gem(struct macb *bp)
{
- return MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2;
+ return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
}
#endif /* _MACB_H */
--
1.8.2.2
^ permalink raw reply related
* [PATCH 2/6] net/macb: add scatter-gather hw feature
From: Cyrille Pitchen @ 2014-07-18 14:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1405689937.git.cyrille.pitchen@atmel.com>
The scatter-gather feature will allow to enable the Generic Segmentation Offload.
Generic Segmentation Offload can be enabled/disabled using ethtool -K DEVNAME gso on|off.
e.g:
ethtool -K eth0 gso off
When enabled, the driver may be provided with socket buffers splitted into many fragments.
These fragments need to be queued into the TX ring in reverse order, starting from to the
last one down to the first one, to avoid a race condition with the MAC.
Especially the 'TX_USED' bit in word 1 of the transmit buffer descriptor of the
first fragment should be cleared at the very final step of the queueing algorithm.
This will tell the hardware that fragments are ready to be sent.
Also since the MAC only update the status word of the first buffer descriptor of the
ethernet frame, the queueing algorithm can no longer expect a 'TX_USED' bit to be set by
the MAC into the buffer descriptor following the one for last fragment of the skb.
This is why the driver sets the 'TX_USED' bit before queueing any fragment, so the end of
queue position is well defined for the MAC.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/net/ethernet/cadence/macb.c | 276 +++++++++++++++++++++++++++++-------
drivers/net/ethernet/cadence/macb.h | 15 +-
2 files changed, 239 insertions(+), 52 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 0896d88..06e9934 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -52,6 +52,9 @@
| MACB_BIT(TXERR))
#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
+#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
+#define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
+
/*
* Graceful stop timeouts in us. We should allow up to
* 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
@@ -468,6 +471,25 @@ static int macb_halt_tx(struct macb *bp)
return -ETIMEDOUT;
}
+static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
+{
+ if (tx_skb->mapping) {
+ if (tx_skb->mapped_as_page) {
+ dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
+ tx_skb->size, DMA_TO_DEVICE);
+ } else {
+ dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
+ tx_skb->size, DMA_TO_DEVICE);
+ }
+ tx_skb->mapping = 0;
+ }
+
+ if (tx_skb->skb) {
+ dev_kfree_skb_any(tx_skb->skb);
+ tx_skb->skb = NULL;
+ }
+}
+
static void macb_tx_error_task(struct work_struct *work)
{
struct macb *bp = container_of(work, struct macb, tx_error_task);
@@ -505,10 +527,23 @@ static void macb_tx_error_task(struct work_struct *work)
skb = tx_skb->skb;
if (ctrl & MACB_BIT(TX_USED)) {
- netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
- macb_tx_ring_wrap(tail), skb->data);
- bp->stats.tx_packets++;
- bp->stats.tx_bytes += skb->len;
+ /* skb is set for the last buffer of the frame */
+ while (!skb) {
+ macb_tx_unmap(bp, tx_skb);
+ tail++;
+ tx_skb = macb_tx_skb(bp, tail);
+ skb = tx_skb->skb;
+ }
+
+ /* ctrl still refers to the first buffer descriptor
+ * since it's the only one written back by the hardware
+ */
+ if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
+ netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
+ macb_tx_ring_wrap(tail), skb->data);
+ bp->stats.tx_packets++;
+ bp->stats.tx_bytes += skb->len;
+ }
} else {
/*
* "Buffers exhausted mid-frame" errors may only happen
@@ -522,10 +557,7 @@ static void macb_tx_error_task(struct work_struct *work)
desc->ctrl = ctrl | MACB_BIT(TX_USED);
}
- dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
- DMA_TO_DEVICE);
- tx_skb->skb = NULL;
- dev_kfree_skb(skb);
+ macb_tx_unmap(bp, tx_skb);
}
/* Make descriptor updates visible to hardware */
@@ -573,20 +605,35 @@ static void macb_tx_interrupt(struct macb *bp)
ctrl = desc->ctrl;
+ /* TX_USED bit is only set by hardware on the very first buffer
+ * descriptor of the transmitted frame.
+ */
if (!(ctrl & MACB_BIT(TX_USED)))
break;
- tx_skb = macb_tx_skb(bp, tail);
- skb = tx_skb->skb;
+ /* Process all buffers of the current transmitted frame */
+ for (;; tail++) {
+ tx_skb = macb_tx_skb(bp, tail);
+ skb = tx_skb->skb;
+
+ /* First, update TX stats if needed */
+ if (skb) {
+ netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
+ macb_tx_ring_wrap(tail), skb->data);
+ bp->stats.tx_packets++;
+ bp->stats.tx_bytes += skb->len;
+ }
- netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
- macb_tx_ring_wrap(tail), skb->data);
- dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
- DMA_TO_DEVICE);
- bp->stats.tx_packets++;
- bp->stats.tx_bytes += skb->len;
- tx_skb->skb = NULL;
- dev_kfree_skb_irq(skb);
+ /* Now we can safely release resources */
+ macb_tx_unmap(bp, tx_skb);
+
+ /* skb is set only for the last buffer of the frame.
+ * WARNING: at this point skb has been freed by
+ * macb_tx_unmap().
+ */
+ if (skb)
+ break;
+ }
}
bp->tx_tail = tail;
@@ -1002,15 +1049,142 @@ static void macb_poll_controller(struct net_device *dev)
}
#endif
-static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
+static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
+ unsigned int len)
+{
+ return (len + bp->max_tx_length - 1) / bp->max_tx_length;
+}
+
+static unsigned int macb_tx_map(struct macb *bp,
+ struct sk_buff *skb)
{
- struct macb *bp = netdev_priv(dev);
dma_addr_t mapping;
- unsigned int len, entry;
+ unsigned int len, entry, i, tx_head = bp->tx_head;
+ struct macb_tx_skb *tx_skb = NULL;
struct macb_dma_desc *desc;
- struct macb_tx_skb *tx_skb;
+ unsigned int offset, size, count = 0;
+ unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
+ unsigned int eof = 1;
u32 ctrl;
+
+ /* First, map non-paged data */
+ len = skb_headlen(skb);
+ offset = 0;
+ while (len) {
+ size = min(len, bp->max_tx_length);
+ entry = macb_tx_ring_wrap(tx_head);
+ tx_skb = &bp->tx_skb[entry];
+
+ mapping = dma_map_single(&bp->pdev->dev,
+ skb->data + offset,
+ size, DMA_TO_DEVICE);
+ if (dma_mapping_error(&bp->pdev->dev, mapping))
+ goto dma_error;
+
+ /* Save info to properly release resources */
+ tx_skb->skb = NULL;
+ tx_skb->mapping = mapping;
+ tx_skb->size = size;
+ tx_skb->mapped_as_page = false;
+
+ len -= size;
+ offset += size;
+ count++;
+ tx_head++;
+ }
+
+ /* Then, map paged data from fragments */
+ for (f = 0; f < nr_frags; f++) {
+ const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
+
+ len = skb_frag_size(frag);
+ offset = 0;
+ while (len) {
+ size = min(len, bp->max_tx_length);
+ entry = macb_tx_ring_wrap(tx_head);
+ tx_skb = &bp->tx_skb[entry];
+
+ mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
+ offset, size, DMA_TO_DEVICE);
+ if (dma_mapping_error(&bp->pdev->dev, mapping))
+ goto dma_error;
+
+ /* Save info to properly release resources */
+ tx_skb->skb = NULL;
+ tx_skb->mapping = mapping;
+ tx_skb->size = size;
+ tx_skb->mapped_as_page = true;
+
+ len -= size;
+ offset += size;
+ count++;
+ tx_head++;
+ }
+ }
+
+ /* Should never happen */
+ if (unlikely(tx_skb == NULL)) {
+ netdev_err(bp->dev, "BUG! empty skb!\n");
+ return 0;
+ }
+
+ /* This is the last buffer of the frame: save socket buffer */
+ tx_skb->skb = skb;
+
+ /* Update TX ring: update buffer descriptors in reverse order
+ * to avoid race condition
+ */
+
+ /* Set 'TX_USED' bit in buffer descriptor at tx_head position
+ * to set the end of TX queue
+ */
+ i = tx_head;
+ entry = macb_tx_ring_wrap(i);
+ ctrl = MACB_BIT(TX_USED);
+ desc = &bp->tx_ring[entry];
+ desc->ctrl = ctrl;
+
+ do {
+ i--;
+ entry = macb_tx_ring_wrap(i);
+ tx_skb = &bp->tx_skb[entry];
+ desc = &bp->tx_ring[entry];
+
+ ctrl = (u32)tx_skb->size;
+ if (eof) {
+ ctrl |= MACB_BIT(TX_LAST);
+ eof = 0;
+ }
+ if (unlikely(entry == (TX_RING_SIZE - 1)))
+ ctrl |= MACB_BIT(TX_WRAP);
+
+ /* Set TX buffer descriptor */
+ desc->addr = tx_skb->mapping;
+ wmb();
+ desc->ctrl = ctrl;
+ } while (i != bp->tx_head);
+
+ bp->tx_head = tx_head;
+
+ return count;
+
+dma_error:
+ netdev_err(bp->dev, "TX DMA map failed\n");
+
+ for (i = bp->tx_head; i != tx_head; i++) {
+ tx_skb = macb_tx_skb(bp, i);
+
+ macb_tx_unmap(bp, tx_skb);
+ }
+
+ return 0;
+}
+
+static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct macb *bp = netdev_priv(dev);
unsigned long flags;
+ unsigned int count, nr_frags, frag_size, f;
#if defined(DEBUG) && defined(VERBOSE_DEBUG)
netdev_vdbg(bp->dev,
@@ -1021,44 +1195,35 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
skb->data, 16, true);
#endif
- len = skb->len;
+ /*
+ * Count how many TX buffer descriptors are needed to send this
+ * socket buffer: skb fragments of jumbo frames may need to be
+ * splitted into many buffer descriptors.
+ */
+ count = macb_count_tx_descriptors(bp, skb_headlen(skb));
+ nr_frags = skb_shinfo(skb)->nr_frags;
+ for (f = 0; f < nr_frags; f++) {
+ frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
+ count += macb_count_tx_descriptors(bp, frag_size);
+ }
+
spin_lock_irqsave(&bp->lock, flags);
/* This is a hard error, log it. */
- if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
+ if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < count) {
netif_stop_queue(dev);
spin_unlock_irqrestore(&bp->lock, flags);
- netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
bp->tx_head, bp->tx_tail);
return NETDEV_TX_BUSY;
}
- entry = macb_tx_ring_wrap(bp->tx_head);
- netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
- mapping = dma_map_single(&bp->pdev->dev, skb->data,
- len, DMA_TO_DEVICE);
- if (dma_mapping_error(&bp->pdev->dev, mapping)) {
+ /* Map socket buffer for DMA transfer */
+ if (!macb_tx_map(bp, skb)) {
dev_kfree_skb_any(skb);
goto unlock;
}
- bp->tx_head++;
- tx_skb = &bp->tx_skb[entry];
- tx_skb->skb = skb;
- tx_skb->mapping = mapping;
- netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
- skb->data, (unsigned long)mapping);
-
- ctrl = MACB_BF(TX_FRMLEN, len);
- ctrl |= MACB_BIT(TX_LAST);
- if (entry == (TX_RING_SIZE - 1))
- ctrl |= MACB_BIT(TX_WRAP);
-
- desc = &bp->tx_ring[entry];
- desc->addr = mapping;
- desc->ctrl = ctrl;
-
/* Make newly initialized descriptor visible to hardware */
wmb();
@@ -1775,7 +1940,12 @@ static const struct net_device_ops macb_netdev_ops = {
#if defined(CONFIG_OF)
static struct macb_config pc302gem_config = {
- .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE,
+ .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
+ .dma_burst_length = 16,
+};
+
+static struct macb_config sama5d3_config = {
+ .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
.dma_burst_length = 16,
};
@@ -1785,6 +1955,7 @@ static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,macb" },
{ .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
{ .compatible = "cdns,gem", .data = &pc302gem_config },
+ { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, macb_dt_ids);
@@ -1861,9 +2032,6 @@ static int __init macb_probe(struct platform_device *pdev)
SET_NETDEV_DEV(dev, &pdev->dev);
- /* TODO: Actually, we have some interesting features... */
- dev->features |= 0;
-
bp = netdev_priv(dev);
bp->pdev = pdev;
bp->dev = dev;
@@ -1935,17 +2103,25 @@ static int __init macb_probe(struct platform_device *pdev)
/* setup appropriated routines according to adapter type */
if (macb_is_gem(bp)) {
+ bp->max_tx_length = GEM_MAX_TX_LEN;
bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
bp->macbgem_ops.mog_init_rings = gem_init_rings;
bp->macbgem_ops.mog_rx = gem_rx;
} else {
+ bp->max_tx_length = MACB_MAX_TX_LEN;
bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
bp->macbgem_ops.mog_init_rings = macb_init_rings;
bp->macbgem_ops.mog_rx = macb_rx;
}
+ /* Set features */
+ dev->hw_features = NETIF_F_SG;
+ if (bp->caps & MACB_CAPS_SG_DISABLED)
+ dev->hw_features &= ~NETIF_F_SG;
+ dev->features = dev->hw_features;
+
/* Set MII management clock divider */
config = macb_mdc_clk_div(bp);
config |= macb_dbw(bp);
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 7ce751b..7bf8285 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -335,6 +335,7 @@
#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
#define MACB_CAPS_FIFO_MODE 0x10000000
#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
+#define MACB_CAPS_SG_DISABLED 0x40000000
#define MACB_CAPS_MACB_IS_GEM 0x80000000
/* Bit manipulation macros */
@@ -468,14 +469,23 @@ struct macb_dma_desc {
#define MACB_TX_USED_OFFSET 31
#define MACB_TX_USED_SIZE 1
+#define GEM_TX_FRMLEN_OFFSET 0
+#define GEM_TX_FRMLEN_SIZE 14
+
/**
* struct macb_tx_skb - data about an skb which is being transmitted
- * @skb: skb currently being transmitted
- * @mapping: DMA address of the skb's data buffer
+ * @skb: skb currently being transmitted, only set for the last buffer
+ * of the frame
+ * @mapping: DMA address of the skb's fragment buffer
+ * @size: size of the DMA mapped buffer
+ * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
+ * false when buffer was mapped with dma_map_single()
*/
struct macb_tx_skb {
struct sk_buff *skb;
dma_addr_t mapping;
+ size_t size;
+ bool mapped_as_page;
};
/*
@@ -617,6 +627,7 @@ struct macb {
struct sk_buff *skb; /* holds skb until xmit interrupt completes */
dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
int skb_length; /* saved skb length for pci_unmap_single */
+ unsigned int max_tx_length;
};
extern const struct ethtool_ops macb_ethtool_ops;
--
1.8.2.2
^ permalink raw reply related
* [PATCH 3/6] net/macb: add TX checksum offload feature
From: Cyrille Pitchen @ 2014-07-18 14:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1405689937.git.cyrille.pitchen@atmel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/net/ethernet/cadence/macb.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 06e9934..9bdcd1b 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1524,6 +1524,10 @@ static void macb_configure_dma(struct macb *bp)
dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
dmacfg &= ~GEM_BIT(ENDIA);
+ if (bp->dev->features & NETIF_F_HW_CSUM)
+ dmacfg |= GEM_BIT(TXCOEN);
+ else
+ dmacfg &= ~GEM_BIT(TXCOEN);
netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n", dmacfg);
gem_writel(bp, DMACFG, dmacfg);
}
@@ -1923,6 +1927,27 @@ int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
}
EXPORT_SYMBOL_GPL(macb_ioctl);
+static int macb_set_features(struct net_device *netdev,
+ netdev_features_t features)
+{
+ struct macb *bp = netdev_priv(netdev);
+ netdev_features_t changed = features ^ netdev->features;
+
+ /* TX checksum offload */
+ if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
+ u32 dmacfg;
+
+ dmacfg = gem_readl(bp, DMACFG);
+ if (features & NETIF_F_HW_CSUM)
+ dmacfg |= GEM_BIT(TXCOEN);
+ else
+ dmacfg &= ~GEM_BIT(TXCOEN);
+ gem_writel(bp, DMACFG, dmacfg);
+ }
+
+ return 0;
+}
+
static const struct net_device_ops macb_netdev_ops = {
.ndo_open = macb_open,
.ndo_stop = macb_close,
@@ -1936,6 +1961,7 @@ static const struct net_device_ops macb_netdev_ops = {
#ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = macb_poll_controller,
#endif
+ .ndo_set_features = macb_set_features,
};
#if defined(CONFIG_OF)
@@ -2118,6 +2144,10 @@ static int __init macb_probe(struct platform_device *pdev)
/* Set features */
dev->hw_features = NETIF_F_SG;
+ if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE)) {
+ /* Checksum offload is only available on packet buffer design */
+ dev->hw_features |= NETIF_F_HW_CSUM;
+ }
if (bp->caps & MACB_CAPS_SG_DISABLED)
dev->hw_features &= ~NETIF_F_SG;
dev->features = dev->hw_features;
--
1.8.2.2
^ permalink raw reply related
* [PATCH 4/6] net/macb: add RX checksum offload feature
From: Cyrille Pitchen @ 2014-07-18 14:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1405689937.git.cyrille.pitchen@atmel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/net/ethernet/cadence/macb.c | 29 ++++++++++++++++++++++++++++-
drivers/net/ethernet/cadence/macb.h | 2 ++
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 9bdcd1b..6acd6e2 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -766,6 +766,8 @@ static int gem_rx(struct macb *bp, int budget)
skb->protocol = eth_type_trans(skb, bp->dev);
skb_checksum_none_assert(skb);
+ if (bp->dev->features & NETIF_F_RXCSUM)
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
bp->stats.rx_packets++;
bp->stats.rx_bytes += skb->len;
@@ -1506,6 +1508,18 @@ static u32 macb_dbw(struct macb *bp)
}
/*
+ * Configure the RX checksum offload
+ */
+static u32 macb_rxcsum(struct macb *bp)
+{
+ if (macb_is_gem(bp) &&
+ (bp->dev->features & NETIF_F_RXCSUM))
+ return GEM_BIT(RXCOEN);
+
+ return 0;
+}
+
+/*
* Configure the receive DMA engine
* - use the correct receive buffer size
* - set best burst length for DMA operations
@@ -1550,6 +1564,7 @@ static void macb_init_hw(struct macb *bp)
if (!(bp->dev->flags & IFF_BROADCAST))
config |= MACB_BIT(NBC); /* No BroadCast */
config |= macb_dbw(bp);
+ config |= macb_rxcsum(bp);
macb_writel(bp, NCFGR, config);
bp->speed = SPEED_10;
bp->duplex = DUPLEX_HALF;
@@ -1945,6 +1960,18 @@ static int macb_set_features(struct net_device *netdev,
gem_writel(bp, DMACFG, dmacfg);
}
+ /* RX checksum offload */
+ if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
+ u32 netcfg;
+
+ netcfg = gem_readl(bp, NCFGR);
+ if (features & NETIF_F_RXCSUM)
+ netcfg |= GEM_BIT(RXCOEN);
+ else
+ netcfg &= ~GEM_BIT(RXCOEN);
+ gem_writel(bp, NCFGR, netcfg);
+ }
+
return 0;
}
@@ -2146,7 +2173,7 @@ static int __init macb_probe(struct platform_device *pdev)
dev->hw_features = NETIF_F_SG;
if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE)) {
/* Checksum offload is only available on packet buffer design */
- dev->hw_features |= NETIF_F_HW_CSUM;
+ dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
}
if (bp->caps & MACB_CAPS_SG_DISABLED)
dev->hw_features &= ~NETIF_F_SG;
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 7bf8285..3678b83 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -164,6 +164,8 @@
#define GEM_CLK_SIZE 3
#define GEM_DBW_OFFSET 21
#define GEM_DBW_SIZE 2
+#define GEM_RXCOEN_OFFSET 24
+#define GEM_RXCOEN_SIZE 1
/* Constants for data bus width. */
#define GEM_DBW32 0
--
1.8.2.2
^ permalink raw reply related
* [PATCH v3 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards
From: Nicolas Ferre @ 2014-07-18 14:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405022394-8311-2-git-send-email-boris.brezillon@free-electrons.com>
On 10/07/2014 21:59, Boris BREZILLON :
> Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25)
> and board specific timing configs.
>
> Atmel has two different HW designs for its CPU modules: the first one
> (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors
> and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up
> resistor and PHYAD[1-2] to pull down resistors.
> As a result, Ronetix design will have its PHY available at address 0x1 and
> Embest design at 0x7.
> By defining both phys we're letting the phy core detect the one actually
> available on the MDIO bus.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> ---
>
> Florian, I dropped your Reviewed-by tag because this patch has slightly
> changed.
Hi Florian,
I would like to have your Ack on this one as we discussed this solution
with you.
Thanks, bye,
> arch/arm/boot/dts/sama5d3xcm.dtsi | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
> index b0b1331..755369e 100644
> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
> @@ -34,6 +34,36 @@
>
> macb0: ethernet at f0028000 {
> phy-mode = "rgmii";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethernet-phy at 1 {
> + reg = <0x1>;
> + interrupt-parent = <&pioB>;
> + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
> + txen-skew-ps = <800>;
> + txc-skew-ps = <3000>;
> + rxdv-skew-ps = <400>;
> + rxc-skew-ps = <3000>;
> + rxd0-skew-ps = <400>;
> + rxd1-skew-ps = <400>;
> + rxd2-skew-ps = <400>;
> + rxd3-skew-ps = <400>;
> + };
> +
> + ethernet-phy at 7 {
> + reg = <0x7>;
> + interrupt-parent = <&pioB>;
> + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
> + txen-skew-ps = <800>;
> + txc-skew-ps = <3000>;
> + rxdv-skew-ps = <400>;
> + rxc-skew-ps = <3000>;
> + rxd0-skew-ps = <400>;
> + rxd1-skew-ps = <400>;
> + rxd2-skew-ps = <400>;
> + rxd3-skew-ps = <400>;
> + };
> };
>
> pmc: pmc at fffffc00 {
>
--
Nicolas Ferre
^ permalink raw reply
* [PATCH v3 0/2] ARM: at91: remove phy fixup for sama5d3xek boards
From: Nicolas Ferre @ 2014-07-18 14:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405022394-8311-1-git-send-email-boris.brezillon@free-electrons.com>
On 10/07/2014 21:59, Boris BREZILLON :
> Hello,
>
> This patch removes a board specific hook for sama5d3xek boards from the
> sama5d3 generic DT board file.
>
> This hook (which register a phy fixup configuring board specific delays
> in the ksz9021 ethernet phy) is now replaced by the appropriate DT
> properties definitions in the sama5d3xcm.dtsi file.
>
> Best Regards,
On the whole series:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> Changes since v2:
> - define 2 phy nodes to handle Ronetix and Embest HW designs
>
> Changes since v1:
> - fix txc-skew-ps and rxc-skew-ps delays
> - remove phy address info to handle Ronetix and Embest HW designs
>
> Boris BREZILLON (2):
> ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek
> boards
> ARM: at91: remove phy fixup for sama5d3xek boards
>
> arch/arm/boot/dts/sama5d3xcm.dtsi | 30 ++++++++++++++++++++++++++++++
> arch/arm/mach-at91/board-dt-sama5.c | 22 ----------------------
> 2 files changed, 30 insertions(+), 22 deletions(-)
>
--
Nicolas Ferre
^ permalink raw reply
* [PATCH] ARM: dts: vf610-colibri: split device tree for carrier boards
From: Stefan Agner @ 2014-07-18 14:25 UTC (permalink / raw)
To: linux-arm-kernel
The Colibri VF61 is a module which needs a carrier board to actually
run. Different carrier board have different hardware support, hence
we should reflect this in the device tree files. This patch adds the
Colibri Evaluation Board, which supports almost all peripherals
defined in the Colibri standard.
Also align the compatible naming, file splitting and file naming with
the scheme which was choosen for the Tegra based modules.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/Makefile | 2 +-
arch/arm/boot/dts/vf610-colibri-eval-v3.dts | 46 +++++++++++
arch/arm/boot/dts/vf610-colibri.dts | 123 ----------------------------
arch/arm/boot/dts/vf610-colibri.dtsi | 113 +++++++++++++++++++++++++
4 files changed, 160 insertions(+), 124 deletions(-)
create mode 100644 arch/arm/boot/dts/vf610-colibri-eval-v3.dts
delete mode 100644 arch/arm/boot/dts/vf610-colibri.dts
create mode 100644 arch/arm/boot/dts/vf610-colibri.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index adb5ed9..acb552c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -216,7 +216,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6q-udoo.dtb \
imx6q-wandboard.dtb \
imx6sl-evk.dtb \
- vf610-colibri.dtb \
+ vf610-colibri-eval-v3.dtb \
vf610-cosmic.dtb \
vf610-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
new file mode 100644
index 0000000..7fb3066
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "vf610-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri VF61 on Colibri Evaluation Board";
+ compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
+
+ chosen {
+ bootargs = "console=ttyLP0,115200";
+ };
+};
+
+&esdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&fec1 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/vf610-colibri.dts b/arch/arm/boot/dts/vf610-colibri.dts
deleted file mode 100644
index aecc7db..0000000
--- a/arch/arm/boot/dts/vf610-colibri.dts
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright 2014 Toradex AG
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-/dts-v1/;
-#include "vf610.dtsi"
-
-/ {
- model = "Toradex Colibri VF61 COM";
- compatible = "toradex,vf610-colibri", "fsl,vf610";
-
- chosen {
- bootargs = "console=ttyLP0,115200";
- };
-
- memory {
- reg = <0x80000000 0x10000000>;
- };
-
- clocks {
- enet_ext {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- };
- };
-
-};
-
-&esdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_esdhc1>;
- bus-width = <4>;
- status = "okay";
-};
-
-&fec1 {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- status = "okay";
-};
-
-&L2 {
- arm,data-latency = <2 1 2>;
- arm,tag-latency = <3 2 3>;
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&iomuxc {
- vf610-colibri {
- pinctrl_esdhc1: esdhc1grp {
- fsl,fsl,pins = <
- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
- VF610_PAD_PTB20__GPIO_42 0x219d
- >;
- };
-
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
- VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
- >;
- };
-
- pinctrl_uart0: uart0grp {
- fsl,pins = <
- VF610_PAD_PTB10__UART0_TX 0x21a2
- VF610_PAD_PTB11__UART0_RX 0x21a1
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- VF610_PAD_PTB4__UART1_TX 0x21a2
- VF610_PAD_PTB5__UART1_RX 0x21a1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- VF610_PAD_PTD0__UART2_TX 0x21a2
- VF610_PAD_PTD1__UART2_RX 0x21a1
- VF610_PAD_PTD2__UART2_RTS 0x21a2
- VF610_PAD_PTD3__UART2_CTS 0x21a1
- >;
- };
- };
-};
diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi
new file mode 100644
index 0000000..e595c29
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "vf610.dtsi"
+
+/ {
+ model = "Toradex Colibri VF61 COM";
+ compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";
+
+ memory {
+ reg = <0x80000000 0x10000000>;
+ };
+
+ clocks {
+ enet_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+ };
+
+};
+
+&esdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1>;
+ bus-width = <4>;
+};
+
+&fec1 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+};
+
+&L2 {
+ arm,data-latency = <2 1 2>;
+ arm,tag-latency = <3 2 3>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+};
+
+&iomuxc {
+ vf610-colibri {
+ pinctrl_esdhc1: esdhc1grp {
+ fsl,pins = <
+ VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
+ VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
+ VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
+ VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
+ VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
+ VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
+ VF610_PAD_PTB20__GPIO_42 0x219d
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
+ VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
+ VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
+ VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
+ VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
+ VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
+ VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
+ VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
+ VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
+ >;
+ };
+
+ pinctrl_uart0: uart0grp {
+ fsl,pins = <
+ VF610_PAD_PTB10__UART0_TX 0x21a2
+ VF610_PAD_PTB11__UART0_RX 0x21a1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ VF610_PAD_PTB4__UART1_TX 0x21a2
+ VF610_PAD_PTB5__UART1_RX 0x21a1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ VF610_PAD_PTD0__UART2_TX 0x21a2
+ VF610_PAD_PTD1__UART2_RX 0x21a1
+ VF610_PAD_PTD2__UART2_RTS 0x21a2
+ VF610_PAD_PTD3__UART2_CTS 0x21a1
+ >;
+ };
+ };
+};
--
2.0.1
^ permalink raw reply related
* [PATCH v10 5/8] ata: ahci_platform: add a generic AHCI compatible
From: Hans de Goede @ 2014-07-18 14:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405686607-8126-6-git-send-email-antoine.tenart@free-electrons.com>
Hi,
On 07/18/2014 02:30 PM, Antoine T?nart wrote:
> The ahci_platform driver is a generic driver using the libahci_platform
> functions. Add a generic compatible to avoid having an endless list of
> compatibles with no differences for the same driver.
>
> Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com>
> ---
> drivers/ata/ahci_platform.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
> index 95f9ca82082a..61b15e784020 100644
> --- a/drivers/ata/ahci_platform.c
> +++ b/drivers/ata/ahci_platform.c
> @@ -77,6 +77,8 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
> ahci_platform_resume);
>
> static const struct of_device_id ahci_of_match[] = {
> + { .compatible = "generic-ahci", },
> + /* Keep the following compatibles for device tree compatibility */
> { .compatible = "snps,spear-ahci", },
> { .compatible = "snps,exynos5440-ahci", },
> { .compatible = "ibm,476gtr-ahci", },
>
I'm not against this, I've introduced the same for the ehci / uhci platform
driver after all, but this should be documented in Documentation/devicetree,
and please make sure to mention in the docs that the correct way to use this
inside a dts file is:
compatible = "manufacturer,soc-model-ahci", "generic-ahci";
So that we can later add quirks for the specific soc if necessary without
needing to change the dts.
Regards,
Hans
^ permalink raw reply
* [PATCH 5/6] ARM: at91: change compatibility string for sama5d3x gem
From: Cyrille Pitchen @ 2014-07-18 14:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1405689937.git.cyrille.pitchen@atmel.com>
this new compatibility string prevents macb/gem driver from using the
scatter-gather and gso features on sama5d3x boards.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
arch/arm/boot/dts/sama5d3_gmac.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
index a6cb050..de5ed59 100644
--- a/arch/arm/boot/dts/sama5d3_gmac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -74,7 +74,7 @@
};
macb0: ethernet at f0028000 {
- compatible = "cdns,pc302-gem", "cdns,gem";
+ compatible = "atmel,sama5d3-gem";
reg = <0xf0028000 0x100>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
--
1.8.2.2
^ permalink raw reply related
* [PATCH 6/6] net/macb: enable scatter-gather feature and set DMA burst length for sama5d4 gem
From: Cyrille Pitchen @ 2014-07-18 14:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1405689937.git.cyrille.pitchen@atmel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/net/ethernet/cadence/macb.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 6acd6e2..08105dc 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -2002,6 +2002,11 @@ static struct macb_config sama5d3_config = {
.dma_burst_length = 16,
};
+static struct macb_config sama5d4_config = {
+ .caps = 0,
+ .dma_burst_length = 4,
+};
+
static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,at32ap7000-macb" },
{ .compatible = "cdns,at91sam9260-macb" },
@@ -2009,6 +2014,7 @@ static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
{ .compatible = "cdns,gem", .data = &pc302gem_config },
{ .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
+ { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, macb_dt_ids);
--
1.8.2.2
^ permalink raw reply related
* [PATCH 1/2] arm: use generic fixmap.h
From: Leif Lindholm @ 2014-07-18 14:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1404938942.24950.12.camel@deneb.redhat.com>
On Wed, Jul 09, 2014 at 04:49:02PM -0400, Mark Salter wrote:
> On Wed, 2014-07-09 at 10:39 +0100, Leif Lindholm wrote:
> > diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
> > index 45aeaac..3c59cdf 100644
> > --- a/arch/arm/mm/highmem.c
> > +++ b/arch/arm/mm/highmem.c
> > @@ -20,16 +20,19 @@
> >
> > pte_t *fixmap_page_table;
> >
> > +#define __kmap_fix_to_virt(x) (__fix_to_virt(FIX_KMAP_NR_PTES - 1 - (x)))
>
> FIX_KMAP_END - (x) ?
>
> > +#define __kmap_virt_to_fix(x) (FIX_KMAP_NR_PTES - 1 - __fix_to_virt(x))
>
> shouldn't this use __virt_to_fix(x)?
Err, clearly.
Good thing I managed to mess up the end of the interface that actually
isn't used anywhere in the kernel(!).
Fixed in the below.
/
Leif
>From d0a82cd19000139d32232f415bcf46f476c16561 Mon Sep 17 00:00:00 2001
From: Mark Salter <msalter@redhat.com>
Date: Thu, 14 Nov 2013 11:37:32 -0500
Subject: [PATCH 1/2] arm: use generic fixmap.h
ARM is different from other architectures in that fixmap pages are
indexed with a positive offset from FIXADDR_START. Other architectures
index with a negative offset from FIXADDR_TOP. In order to use the
generic fixmap.h definitions, this patch redefines FIXADDR_TOP to be
inclusive of the useable range. That is, FIXADDR_TOP is the virtual
address of the topmost fixed page. The newly defined FIXADDR_END is
the first virtual address past the fixed mappings.
The patch also introduces local helper macros in highmem.c to reverse
the iteration order of fixmap pages.
Signed-off-by: Mark Salter <msalter@redhat.com>
[Rebased to 3.16-rc4, reverse kmap fixmap traversal]
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
---
arch/arm/include/asm/fixmap.h | 45 ++++++++++++++++++++++++++---------------
arch/arm/mm/highmem.c | 13 +++++++-----
arch/arm/mm/init.c | 2 +-
3 files changed, 38 insertions(+), 22 deletions(-)
diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h
index 74124b0..8992431 100644
--- a/arch/arm/include/asm/fixmap.h
+++ b/arch/arm/include/asm/fixmap.h
@@ -1,28 +1,41 @@
#ifndef _ASM_FIXMAP_H
#define _ASM_FIXMAP_H
+#include <asm/pgtable.h>
+
#define FIXADDR_START 0xffc00000UL
-#define FIXADDR_TOP 0xffe00000UL
-#define FIXADDR_SIZE (FIXADDR_TOP - FIXADDR_START)
+#define FIXADDR_END 0xffe00000UL
+#define FIXADDR_SIZE (FIXADDR_END - FIXADDR_START)
+#define FIXADDR_TOP (FIXADDR_END - PAGE_SIZE)
#define FIX_KMAP_NR_PTES (FIXADDR_SIZE >> PAGE_SHIFT)
-#define __fix_to_virt(x) (FIXADDR_START + ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x) (((x) - FIXADDR_START) >> PAGE_SHIFT)
+enum fixed_addresses {
+ FIX_KMAP_BEGIN,
+ FIX_KMAP_END = FIX_KMAP_NR_PTES - 1,
+ __end_of_fixed_addresses
+};
+
+/*
+ * Temporary boot-time mappings, used by early_ioremap(),
+ * before ioremap() is functional.
+ *
+ * (P)re-using the last pmd of the FIXADDR region, which is used for
+ * highmem later on, and statically aligned to 1MB.
+ * Growing down from FIXADDR_TOP
+ */
+#define NR_FIX_BTMAPS 32
+#define FIX_BTMAPS_SLOTS (PTRS_PER_PTE / NR_FIX_BTMAPS)
+#define TOTAL_FIX_BTMAPS (NR_FIX_BTMAPS * FIX_BTMAPS_SLOTS)
+#define FIX_BTMAP_END FIX_KMAP_BEGIN
+#define FIX_BTMAP_BEGIN (FIX_BTMAP_END + TOTAL_FIX_BTMAPS - 1)
-extern void __this_fixmap_does_not_exist(void);
+#define FIXMAP_PAGE_NORMAL (L_PTE_MT_WRITEBACK | L_PTE_YOUNG | L_PTE_PRESENT)
+#define FIXMAP_PAGE_IO (L_PTE_MT_DEV_NONSHARED | L_PTE_YOUNG | L_PTE_PRESENT)
-static inline unsigned long fix_to_virt(const unsigned int idx)
-{
- if (idx >= FIX_KMAP_NR_PTES)
- __this_fixmap_does_not_exist();
- return __fix_to_virt(idx);
-}
+extern void __early_set_fixmap(enum fixed_addresses idx,
+ phys_addr_t phys, pgprot_t flags);
-static inline unsigned int virt_to_fix(const unsigned long vaddr)
-{
- BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
- return __virt_to_fix(vaddr);
-}
+#include <asm-generic/fixmap.h>
#endif
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 45aeaac..2e5b773 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -20,16 +20,19 @@
pte_t *fixmap_page_table;
+#define __kmap_fix_to_virt(x) (__fix_to_virt(FIX_KMAP_NR_PTES - 1 - (x)))
+#define __kmap_virt_to_fix(x) (FIX_KMAP_NR_PTES - 1 - __virt_to_fix(x))
+
static inline void set_fixmap_pte(int idx, pte_t pte)
{
- unsigned long vaddr = __fix_to_virt(idx);
+ unsigned long vaddr = __kmap_fix_to_virt(idx);
set_pte_ext(fixmap_page_table + idx, pte, 0);
local_flush_tlb_kernel_page(vaddr);
}
static inline pte_t get_fixmap_pte(unsigned long vaddr)
{
- unsigned long idx = __virt_to_fix(vaddr);
+ unsigned long idx = __kmap_virt_to_fix(vaddr);
return *(fixmap_page_table + idx);
}
@@ -78,7 +81,7 @@ void *kmap_atomic(struct page *page)
type = kmap_atomic_idx_push();
idx = type + KM_TYPE_NR * smp_processor_id();
- vaddr = __fix_to_virt(idx);
+ vaddr = __kmap_fix_to_virt(idx);
#ifdef CONFIG_DEBUG_HIGHMEM
/*
* With debugging enabled, kunmap_atomic forces that entry to 0.
@@ -109,7 +112,7 @@ void __kunmap_atomic(void *kvaddr)
if (cache_is_vivt())
__cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE);
#ifdef CONFIG_DEBUG_HIGHMEM
- BUG_ON(vaddr != __fix_to_virt(idx));
+ BUG_ON(vaddr != __kmap_fix_to_virt(idx));
set_fixmap_pte(idx, __pte(0));
#else
(void) idx; /* to kill a warning */
@@ -132,7 +135,7 @@ void *kmap_atomic_pfn(unsigned long pfn)
type = kmap_atomic_idx_push();
idx = type + KM_TYPE_NR * smp_processor_id();
- vaddr = __fix_to_virt(idx);
+ vaddr = __kmap_fix_to_virt(idx);
#ifdef CONFIG_DEBUG_HIGHMEM
BUG_ON(!pte_none(*(fixmap_page_table + idx)));
#endif
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 659c75d..ad82c05 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -570,7 +570,7 @@ void __init mem_init(void)
MLK(DTCM_OFFSET, (unsigned long) dtcm_end),
MLK(ITCM_OFFSET, (unsigned long) itcm_end),
#endif
- MLK(FIXADDR_START, FIXADDR_TOP),
+ MLK(FIXADDR_START, FIXADDR_END),
MLM(VMALLOC_START, VMALLOC_END),
MLM(PAGE_OFFSET, (unsigned long)high_memory),
#ifdef CONFIG_HIGHMEM
--
1.7.10.4
^ permalink raw reply related
* [PATCH v2 1/2] clk: samsung: exynos4: Enable ARMCLK down feature
From: Krzysztof Kozlowski @ 2014-07-18 14:36 UTC (permalink / raw)
To: linux-arm-kernel
Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).
The feature behaves like very fast cpufreq ondemand governor. In idle
mode this reduces energy consumption on full frequency chosen by
cpufreq governor by approximately:
- Trats2: 6.5% (153 mA -> 143 mA)
- Trats: 33.0% (180 mA -> 120 mA)
- Gear1: 27.0% (180 mA -> 130 mA)
The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature and on Exynos4412 ARMCLK down is
enabled for all 4 cores.
Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and
Samsung Gear 1 (Exynos4212).
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
Changes since v1:
1. Add PWR_CTRL registers to the list of saved clk registers on
Exynos4x12. Suggested by Tomasz Figa.
2. Disable the clock up feature. (sug. Tomasz Figa)
3. Use macros for setting clock down ratio. (sug. Tomasz Figa)
4. Use num_possible_cpus() for exception on Exynos4x12. (sug. Tomasz
Figa)
5. Enable the clock down feature also on Exynos4210 Trats board.
---
drivers/clk/samsung/clk-exynos4.c | 46 +++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 7f4a473a7ad7..86c7709dc6d6 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -114,11 +114,27 @@
#define DIV_CPU1 0x14504
#define GATE_SCLK_CPU 0x14800
#define GATE_IP_CPU 0x14900
+#define PWR_CTRL1 0x15020
+#define E4X12_PWR_CTRL2 0x15024
#define E4X12_DIV_ISP0 0x18300
#define E4X12_DIV_ISP1 0x18304
#define E4X12_GATE_ISP0 0x18800
#define E4X12_GATE_ISP1 0x18804
+/* Below definitions are used for PWR_CTRL settings */
+#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
+#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
+#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
+#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
+#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
+#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
+#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
+
/* the exynos4 soc type */
enum exynos4_soc {
EXYNOS4210,
@@ -155,6 +171,7 @@ static unsigned long exynos4210_clk_save[] __initdata = {
E4210_GATE_IP_LCD1,
E4210_GATE_IP_PERIR,
E4210_MPLL_CON0,
+ PWR_CTRL1,
};
static unsigned long exynos4x12_clk_save[] __initdata = {
@@ -164,6 +181,8 @@ static unsigned long exynos4x12_clk_save[] __initdata = {
E4X12_DIV_ISP,
E4X12_DIV_CAM1,
E4X12_MPLL_CON0,
+ PWR_CTRL1,
+ E4X12_PWR_CTRL2,
};
static unsigned long exynos4_clk_pll_regs[] __initdata = {
@@ -1164,6 +1183,32 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static void __init exynos4_core_down_clock(enum exynos4_soc soc)
+{
+ unsigned int tmp;
+
+ /*
+ * Enable arm clock down (in idle) and set arm divider
+ * ratios in WFI/WFE state.
+ */
+ tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
+ PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
+ PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
+ PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
+ /* On Exynos4412 enable it also on core 2 and 3 */
+ if (num_possible_cpus() == 4)
+ tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
+ PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
+ __raw_writel(tmp, reg_base + PWR_CTRL1);
+
+ /*
+ * Disable the clock up feature on Exynos4x12, in case it was
+ * enabled by bootloader.
+ */
+ if (exynos4_soc == EXYNOS4X12)
+ __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
+}
+
/* register exynos4 clocks */
static void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc soc)
@@ -1250,6 +1295,7 @@ static void __init exynos4_clk_init(struct device_node *np,
samsung_clk_register_alias(ctx, exynos4_aliases,
ARRAY_SIZE(exynos4_aliases));
+ exynos4_core_down_clock(soc);
exynos4_clk_sleep_init();
pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
--
1.9.1
^ permalink raw reply related
* [PATCH v2 2/2] clk: samsung: exynos3250: Enable ARMCLK down feature
From: Krzysztof Kozlowski @ 2014-07-18 14:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405694193-29643-1-git-send-email-k.kozlowski@samsung.com>
Enable ARMCLK down feature on Exynos3250 SoC. The frequency of
ARMCLK will be reduced upon entering idle mode (WFI or WFE).
The feature behaves like very fast cpufreq ondemand governor.
The patch uses simillar settings as Exynos5250 (clk-exynos5250.c),
except it disables clock up feature.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
Changes since v1:
1. Add PWR_CTRL registers to the list of saved clk registers on
Exynos3250. Suggested by Tomasz Figa.
2. Disable the clock up feature. (sug. Tomasz Figa)
3. Use macros for setting clock down ratio. (sug. Tomasz Figa)
---
drivers/clk/samsung/clk-exynos3250.c | 41 ++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 7a17bd40d1dd..a50dc88f0e8f 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -87,6 +87,22 @@
#define SRC_CPU 0x14200
#define DIV_CPU0 0x14500
#define DIV_CPU1 0x14504
+#define PWR_CTRL1 0x15020
+#define PWR_CTRL2 0x15024
+
+/* Below definitions are used for PWR_CTRL settings */
+#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
+#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
+#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
+#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
+#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
+#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
+#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
/* list of PLLs to be registered */
enum exynos3250_plls {
@@ -168,6 +184,8 @@ static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
SRC_CPU,
DIV_CPU0,
DIV_CPU1,
+ PWR_CTRL1,
+ PWR_CTRL2,
};
static int exynos3250_clk_suspend(void)
@@ -748,6 +766,27 @@ static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = {
UPLL_LOCK, UPLL_CON0, NULL),
};
+static void __init exynos3_core_down_clock(void)
+{
+ unsigned int tmp;
+
+ /*
+ * Enable arm clock down (in idle) and set arm divider
+ * ratios in WFI/WFE state.
+ */
+ tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
+ PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
+ PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
+ PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
+ __raw_writel(tmp, reg_base + PWR_CTRL1);
+
+ /*
+ * Disable the clock up feature on Exynos4x12, in case it was
+ * enabled by bootloader.
+ */
+ __raw_writel(0x0, reg_base + PWR_CTRL2);
+}
+
static void __init exynos3250_cmu_init(struct device_node *np)
{
struct samsung_clk_provider *ctx;
@@ -775,6 +814,8 @@ static void __init exynos3250_cmu_init(struct device_node *np)
samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
+ exynos3_core_down_clock();
+
exynos3250_clk_sleep_init();
}
CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
--
1.9.1
^ permalink raw reply related
* [RFC PATCH] usb: dwc3: core: allow vendor drivers to check probe status
From: Felipe Balbi @ 2014-07-18 14:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140718071115.GH30888@lee--X1>
Hi,
On Fri, Jul 18, 2014 at 08:11:15AM +0100, Lee Jones wrote:
<snip>
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index eb69eb9..171ca52 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -47,6 +47,14 @@
> > >
> > > /* -------------------------------------------------------------------------- */
> > >
> > > +static bool is_enabled = false;
> > > +
> > > +int dwc3_is_enabled(void)
> > > +{
> > > + return is_enabled;
> > > +}
> > > +EXPORT_SYMBOL(dwc3_is_enabled);
> >
> > no, no, no, no. Let me try that again, hello no! You _do_ realise there
> > are systems with more than one dwc3 instance, right ? And this is the
> > most fragile possible way of doing this.
> >
> > You never explained what's a dwc3 subordinate driver, you don't show any
> > example of how this would be used and why/where does the PHY need to
> > poke into DWC3. Why isn't probe defer enough for you ? Which platform
> > are you working on ? what is the problem that you're trying to solve ?
> >
> > From this patch, all I can is NAK this patch with no mercy, sorry.
>
> That's okay, I knew this was going to happen hence the RFC status of
> the patch. In the DT case, I describe 'subordinate devices' as are
> drivers which register the DWC3 core using of_platform_populate(),
> so, for now:
>
> drivers/usb/dwc3/dwc3-exynos.c
> drivers/usb/dwc3/dwc3-keystone.c
> drivers/usb/dwc3/dwc3-omap.c
>
> We're attempting to use the same process; however, at the moment we are
> suffering with a 'boot order' issue. If the PHYs aren't up and we
> attempt to configure through the glue-layer our board locks up.
what are you configuring through the glue-layer ? Which glue-layer is
causing that ?
> Presumably waiting for a read to return, forever. Whist the core does
> the correct thing i.e. -EPROBE_DEFER, we (dwc3-st.c) have no way of
ah! finally, the glue layer.
> checking the return status of dwc3_probe(). As mentioned in the
yeah, because glue layers are not supposed to know. There should be no
coupling what so ever between glue layer and core driver, other than the
fact that glue layer is the one which triggers platform_device creation
through of_platform_population(). But the glue layer has (or should
have) no interest in exactly when the core driver finishes probing.
> commit message, another way of ensuring the PHYs are available is to
> request them, but this would mean an awful lot of code duplication.
>
> In your opinion, what's the best way to handle this?
How can I know ? You still haven't fully explained what you need. All
you said was that you're trying to "configure through the glue-layer".
Care to further explain what the problem really is ? I'm assuming below
is what you're concerned about which I had to go dig in the archives
because there was no reference to that patch anywhere here.
> +static void st_dwc3_init(struct st_dwc3 *dwc3_data)
> +{
> + u32 reg = st_dwc3_readl(dwc3_data->glue_base, USB2_CLKRST_CTRL);
> +
> + reg |= aux_clk_en(1) | ext_cfg_reset_n(1) | xhci_revision(1);
so you have auxiliary clock, an external config reset, what's this
xhci_revision ?
> + reg &= ~sw_pipew_reset_n(1);
another reset
> + st_dwc3_writel(dwc3_data->glue_base, USB2_CLKRST_CTRL, reg);
looks like it should be split between a CCF and reset drivers. Or maybe
a single driver which does both. Do you have a clock/reset control for
all IPs ? That might be a good way to hide stuff, driver would simply
call clk_get()/clk_prepare_enable() and reset_assert()/deassert() when
necessary (sure, this doesn't solve the 'when has that guy probe' but
you still haven't explained why you need it).
> + reg = st_dwc3_readl(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1);
> + reg |= SEL_OVERRIDE_VBUSVALID(1) | SEL_OVERRIDE_POWERPRESENT(1) |
> + SEL_OVERRIDE_BVALID(1);
this is not correct. You don't know if VBUS is really valid at this
time. We have used a gpio which gets pull high/low depending on the
state of VBUS/ID.
> + st_dwc3_writel(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1, reg);
> + udelay(100);
> +
> + reg = st_dwc3_readl(dwc3_data->glue_base, USB2_CLKRST_CTRL);
> + reg |= sw_pipew_reset_n(1);
> + st_dwc3_writel(dwc3_data->glue_base, USB2_CLKRST_CTRL, reg);
let me ask you something else. Isn't the DWC3_GUSB3PIPECTL_PHYSOFTRST
bit functional for you guys ? This sw_pipe2_reset_n looks suspicious.
ps: I read that the board hangs, but why ? Have you checked with IP
folks ? Maybe that's a silicon bug they're going to fix and we can hack
things for now with an errata ID/revision check ?
--
balbi
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^ permalink raw reply
* [GIT PULL 1/7] ARM: tegra: move fuse code out of arch/arm
From: Thierry Reding @ 2014-07-18 14:45 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 7171511eaec5bf23fb06078f59784a3a0626b38f:
Linux 3.16-rc1 (2014-06-15 17:45:28 -1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-3.17-fuse-move
for you to fetch changes up to 2fa937a767bd0933dfe6017cabd038ce52594171:
soc/tegra: fuse: fix dummy functions (2014-07-17 14:38:29 +0200)
----------------------------------------------------------------
ARM: tegra: move fuse code out of arch/arm
This branch moves code related to the Tegra fuses out of arch/arm and
into a centralized location which could be shared with ARM64. It also
adds support for reading the fuse data through sysfs.
Included is also some preparatory work that moves Tegra-related header
files from include/linux to include/soc/tegra as suggested by Arnd.
Furthermore the Tegra chip ID is now retrieved using a function rather
than a variable so that sanity checks can be done. This is convenient
in subsequent patches that will move some of the code that's currently
called from Tegra machine setup into regular initcalls so that it can
be reused on 64-bit ARM. The sanity checks help with verifying that no
code tries to obtain the Tegra chip ID before the underlying driver is
properly initialized.
----------------------------------------------------------------
Peter De Schrijver (5):
ARM: tegra: export apb dma readl/writel
ARM: tegra: move fuse exports to soc/tegra/fuse.h
soc/tegra: Add efuse driver for Tegra
soc/tegra: Add efuse and apbmisc bindings
soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
Stephen Warren (1):
soc/tegra: fuse: fix dummy functions
Thierry Reding (3):
ARM: tegra: Move includes to include/soc/tegra
ARM: tegra: Sort includes alphabetically
ARM: tegra: Use a function to get the chip ID
Documentation/ABI/testing/sysfs-driver-tegra-fuse | 11 +
.../bindings/fuse/nvidia,tegra20-fuse.txt | 40 ++++
.../bindings/misc/nvidia,tegra20-apbmisc.txt | 13 ++
arch/arm/boot/dts/tegra114.dtsi | 15 ++
arch/arm/boot/dts/tegra124.dtsi | 15 ++
arch/arm/boot/dts/tegra20.dtsi | 15 ++
arch/arm/boot/dts/tegra30.dtsi | 15 ++
arch/arm/mach-tegra/Makefile | 5 -
arch/arm/mach-tegra/apbio.c | 206 -----------------
arch/arm/mach-tegra/apbio.h | 22 --
arch/arm/mach-tegra/board-paz00.c | 3 +-
arch/arm/mach-tegra/cpuidle-tegra114.c | 10 +-
arch/arm/mach-tegra/cpuidle-tegra20.c | 16 +-
arch/arm/mach-tegra/cpuidle-tegra30.c | 10 +-
arch/arm/mach-tegra/cpuidle.c | 7 +-
arch/arm/mach-tegra/flowctrl.c | 11 +-
arch/arm/mach-tegra/fuse.c | 252 ---------------------
arch/arm/mach-tegra/fuse.h | 79 -------
arch/arm/mach-tegra/hotplug.c | 14 +-
arch/arm/mach-tegra/io.c | 8 +-
arch/arm/mach-tegra/irq.c | 8 +-
arch/arm/mach-tegra/platsmp.c | 29 +--
arch/arm/mach-tegra/pm-tegra20.c | 1 +
arch/arm/mach-tegra/pm-tegra30.c | 1 +
arch/arm/mach-tegra/pm.c | 33 +--
arch/arm/mach-tegra/pmc.c | 9 +-
arch/arm/mach-tegra/powergate.c | 15 +-
arch/arm/mach-tegra/reset-handler.S | 7 +-
arch/arm/mach-tegra/reset.c | 11 +-
arch/arm/mach-tegra/sleep-tegra30.S | 7 +-
arch/arm/mach-tegra/tegra.c | 28 +--
drivers/amba/tegra-ahb.c | 3 +-
drivers/clk/tegra/clk-periph-gate.c | 3 +-
drivers/clk/tegra/clk-tegra30.c | 5 +-
drivers/clk/tegra/clk.c | 3 +-
drivers/gpu/drm/tegra/gr3d.c | 3 +-
drivers/gpu/drm/tegra/sor.c | 3 +-
drivers/iommu/tegra-smmu.c | 3 +-
drivers/misc/fuse/Makefile | 1 +
drivers/pci/host/pci-tegra.c | 5 +-
drivers/soc/Makefile | 1 +
drivers/soc/tegra/Makefile | 1 +
drivers/soc/tegra/fuse/Makefile | 8 +
drivers/soc/tegra/fuse/fuse-tegra.c | 156 +++++++++++++
drivers/soc/tegra/fuse/fuse-tegra20.c | 215 ++++++++++++++++++
drivers/soc/tegra/fuse/fuse-tegra30.c | 224 ++++++++++++++++++
drivers/soc/tegra/fuse/fuse.h | 71 ++++++
.../soc/tegra/fuse/speedo-tegra114.c | 56 +++--
drivers/soc/tegra/fuse/speedo-tegra124.c | 168 ++++++++++++++
.../soc/tegra/fuse/speedo-tegra20.c | 45 ++--
.../soc/tegra/fuse/speedo-tegra30.c | 176 +++++++-------
drivers/soc/tegra/fuse/tegra-apbmisc.c | 112 +++++++++
include/linux/tegra-soc.h | 22 --
include/{linux/tegra-ahb.h => soc/tegra/ahb.h} | 6 +-
.../{linux/tegra-cpuidle.h => soc/tegra/cpuidle.h} | 6 +-
include/soc/tegra/fuse.h | 66 ++++++
.../tegra-powergate.h => soc/tegra/powergate.h} | 6 +-
57 files changed, 1436 insertions(+), 848 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-driver-tegra-fuse
create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
delete mode 100644 arch/arm/mach-tegra/apbio.c
delete mode 100644 arch/arm/mach-tegra/apbio.h
delete mode 100644 arch/arm/mach-tegra/fuse.c
delete mode 100644 arch/arm/mach-tegra/fuse.h
create mode 100644 drivers/misc/fuse/Makefile
create mode 100644 drivers/soc/tegra/Makefile
create mode 100644 drivers/soc/tegra/fuse/Makefile
create mode 100644 drivers/soc/tegra/fuse/fuse-tegra.c
create mode 100644 drivers/soc/tegra/fuse/fuse-tegra20.c
create mode 100644 drivers/soc/tegra/fuse/fuse-tegra30.c
create mode 100644 drivers/soc/tegra/fuse/fuse.h
rename arch/arm/mach-tegra/tegra114_speedo.c => drivers/soc/tegra/fuse/speedo-tegra114.c (55%)
create mode 100644 drivers/soc/tegra/fuse/speedo-tegra124.c
rename arch/arm/mach-tegra/tegra20_speedo.c => drivers/soc/tegra/fuse/speedo-tegra20.c (67%)
rename arch/arm/mach-tegra/tegra30_speedo.c => drivers/soc/tegra/fuse/speedo-tegra30.c (52%)
create mode 100644 drivers/soc/tegra/fuse/tegra-apbmisc.c
delete mode 100644 include/linux/tegra-soc.h
rename include/{linux/tegra-ahb.h => soc/tegra/ahb.h} (86%)
rename include/{linux/tegra-cpuidle.h => soc/tegra/cpuidle.h} (86%)
create mode 100644 include/soc/tegra/fuse.h
rename include/{linux/tegra-powergate.h => soc/tegra/powergate.h} (96%)
^ permalink raw reply
* [GIT PULL 2/7] ARM: tegra: core code changes for 3.17
From: Thierry Reding @ 2014-07-18 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405694740-4090-1-git-send-email-thierry.reding@gmail.com>
The following changes since commit dd849e581d7d23e1729c23bb2d6b85360ce4dd9d:
Merge branch 'for-3.17/fuse-move' into for-3.17/soc (2014-07-17 14:58:18 +0200)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-3.17-soc
for you to fetch changes up to 7232398abc6a7186e315425638c367d50c674718:
ARM: tegra: Convert PMC to a driver (2014-07-17 14:58:43 +0200)
----------------------------------------------------------------
ARM: tegra: core code changes for 3.17
Some of the code that's currently called from the Tegra machine setup
code is moved to regular initcalls. To catch dependency violations, the
various code paths now WARN if they're called to early. Not all of the
potential candidates are converted yet, but those that were have been
verified to work across all supported Tegra generations.
A new function, soc_is_tegra(), is also provided to make sure that the
initcalls can abort early if they aren't run on Tegra, which can happen
for multi-platform builds.
Finally this also moves out the PMC driver to drivers/soc/tegra so that
it can be shared with 64-bit ARM.
This is based on the for-3.17/fuse-move branch. The split is somewhat
arbitrary but allows the dependents of the for-3.17/fuse-move to pull
in as little code as necessary.
----------------------------------------------------------------
Thierry Reding (5):
soc/tegra: Implement runtime check for Tegra SoCs
ARM: tegra: Setup CPU hotplug in a pure initcall
ARM: tegra: Always lock the CPU reset vector
soc/tegra: fuse: Set up in early initcall
ARM: tegra: Convert PMC to a driver
arch/arm/mach-tegra/Makefile | 2 -
arch/arm/mach-tegra/board.h | 7 -
arch/arm/mach-tegra/hotplug.c | 16 +-
arch/arm/mach-tegra/platsmp.c | 2 +-
arch/arm/mach-tegra/pm.c | 32 +-
arch/arm/mach-tegra/pm.h | 10 +-
arch/arm/mach-tegra/pmc.c | 414 -------------
arch/arm/mach-tegra/pmc.h | 49 --
arch/arm/mach-tegra/powergate.c | 516 -----------------
arch/arm/mach-tegra/reset.c | 10 +-
arch/arm/mach-tegra/sleep.h | 3 -
arch/arm/mach-tegra/tegra.c | 9 +-
drivers/clk/tegra/clk-tegra30.c | 2 +-
drivers/gpu/drm/tegra/gr3d.c | 2 +-
drivers/gpu/drm/tegra/sor.c | 2 +-
drivers/pci/host/pci-tegra.c | 2 +-
drivers/soc/tegra/Makefile | 3 +
drivers/soc/tegra/common.c | 30 +
drivers/soc/tegra/fuse/fuse-tegra.c | 11 +-
drivers/soc/tegra/fuse/tegra-apbmisc.c | 7 +-
drivers/soc/tegra/pmc.c | 957 +++++++++++++++++++++++++++++++
include/soc/tegra/common.h | 14 +
include/soc/tegra/fuse.h | 1 -
include/soc/tegra/pm.h | 38 ++
include/soc/tegra/{powergate.h => pmc.h} | 31 +-
25 files changed, 1132 insertions(+), 1038 deletions(-)
delete mode 100644 arch/arm/mach-tegra/pmc.c
delete mode 100644 arch/arm/mach-tegra/pmc.h
delete mode 100644 arch/arm/mach-tegra/powergate.c
create mode 100644 drivers/soc/tegra/common.c
create mode 100644 drivers/soc/tegra/pmc.c
create mode 100644 include/soc/tegra/common.h
create mode 100644 include/soc/tegra/pm.h
rename include/soc/tegra/{powergate.h => pmc.h} (82%)
^ permalink raw reply
* [GIT PULL 3/7] ARM: tegra: rework PCIe regulators
From: Thierry Reding @ 2014-07-18 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405694740-4090-1-git-send-email-thierry.reding@gmail.com>
The following changes since commit 7171511eaec5bf23fb06078f59784a3a0626b38f:
Linux 3.16-rc1 (2014-06-15 17:45:28 -1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-3.17-pcie-regulators
for you to fetch changes up to 122ee17dc2adb5c4a63d3a29af9f4e6e331087e5:
ARM: tegra: Remove legacy PCIe power supply properties (2014-07-18 11:20:10 +0200)
----------------------------------------------------------------
ARM: tegra: rework PCIe regulators
This branch reworks the set of regulators that the Tegra PCIe driver
uses, so that the driver and DT bindings more correctly model what's
really going on in HW. For backwards-compatibility the driver will
fallback to using the old set of regulators if the new ones can't be
found.
I've made this a separate branch in case it needs to be pulled into the
PCIe tree to resolve any conflicts.
----------------------------------------------------------------
Thierry Reding (5):
PCI: tegra: Overhaul regulator usage
ARM: tegra: Add new PCIe regulator properties
PCI: tegra: Implement accurate power supply scheme
PCI: tegra: Remove deprecated power supply properties
ARM: tegra: Remove legacy PCIe power supply properties
.../bindings/pci/nvidia,tegra20-pcie.txt | 30 ++-
arch/arm/boot/dts/tegra20-harmony.dts | 8 +-
arch/arm/boot/dts/tegra20-tamonten.dtsi | 7 +-
arch/arm/boot/dts/tegra20-trimslice.dts | 8 +-
arch/arm/boot/dts/tegra30-beaver.dts | 12 +-
arch/arm/boot/dts/tegra30-cardhu.dtsi | 11 +-
drivers/pci/host/pci-tegra.c | 222 +++++++++++++++------
7 files changed, 222 insertions(+), 76 deletions(-)
^ permalink raw reply
* [GIT PULL 4/7] ARM: tegra: Add XUSB pad controller support
From: Thierry Reding @ 2014-07-18 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405694740-4090-1-git-send-email-thierry.reding@gmail.com>
The following changes since commit 7171511eaec5bf23fb06078f59784a3a0626b38f:
Linux 3.16-rc1 (2014-06-15 17:45:28 -1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-3.17-xusb-padctl
for you to fetch changes up to dc0a3938668706f3a63cde4ceb431e9189fb2a0a:
pinctrl: Add NVIDIA Tegra XUSB pad controller support (2014-07-11 14:41:06 +0200)
----------------------------------------------------------------
ARM: tegra: Add XUSB pad controller support
Adds device tree bindings and a driver for the XUSB pad controller found
on Tegra114 and later. This is a prerequisites for PCIe, SATA and XUSB
drivers which are all currently being reviewed or pending for merge.
This is a separate branch in case it needs to be pulled into the pinctrl
tree to resolve conflicts.
----------------------------------------------------------------
Thierry Reding (2):
of: Add NVIDIA Tegra XUSB pad controller binding
pinctrl: Add NVIDIA Tegra XUSB pad controller support
.../pinctrl/nvidia,tegra124-xusb-padctl.txt | 127 +++
drivers/pinctrl/Kconfig | 6 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-tegra-xusb.c | 973 +++++++++++++++++++++
include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 +
5 files changed, 1114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
create mode 100644 drivers/pinctrl/pinctrl-tegra-xusb.c
create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
^ permalink raw reply
* [GIT PULL 5/7] ARM: create a cros-ec-keyboard DT fragment
From: Thierry Reding @ 2014-07-18 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405694740-4090-1-git-send-email-thierry.reding@gmail.com>
The following changes since commit 7171511eaec5bf23fb06078f59784a3a0626b38f:
Linux 3.16-rc1 (2014-06-15 17:45:28 -1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-3.17-dt-cros-ec-kbd
for you to fetch changes up to 1a395e3b4f2e9038964c9eec392ed5300a4b5b83:
ARM: dts: Use the cros-ec-keyboard fragment in exynos5250-snow (2014-06-16 12:11:32 -0600)
----------------------------------------------------------------
ARM: create a cros-ec-keyboard DT fragment
This branch contains a series from Doug Anderson that creates a DT
include file to share some common DT content between Tegra and Exynos
boards that use cros-ec. I'll be pulling this into Tegra's for-3.17/dt
branch, and I assume the Samsung maintainers will do something similar.
----------------------------------------------------------------
Doug Anderson (3):
ARM: dts: Create a cros-ec-keyboard fragment
ARM: tegra: Use the cros-ec-keyboard fragment in venice2
ARM: dts: Use the cros-ec-keyboard fragment in exynos5250-snow
arch/arm/boot/dts/cros-ec-keyboard.dtsi | 105 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos5250-snow.dts | 93 +---------------------------
arch/arm/boot/dts/tegra124-venice2.dts | 96 +----------------------------
3 files changed, 111 insertions(+), 183 deletions(-)
create mode 100644 arch/arm/boot/dts/cros-ec-keyboard.dtsi
^ permalink raw reply
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