* [PATCHv3 13/16] cpuidle: mvebu: add Armada 38x support
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
This commit adds the list of cpuidle states supported by the Armada
38x SoC in the cpuidle-mvebu-v7 driver, as well as the necessary logic
around it to support this SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/cpuidle/cpuidle-mvebu-v7.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/cpuidle/cpuidle-mvebu-v7.c b/drivers/cpuidle/cpuidle-mvebu-v7.c
index d23597f..45371bb 100644
--- a/drivers/cpuidle/cpuidle-mvebu-v7.c
+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
@@ -1,5 +1,5 @@
/*
- * Marvell Armada 370 and Armada XP SoC cpuidle driver
+ * Marvell Armada 370, 38x and XP SoC cpuidle driver
*
* Copyright (C) 2014 Marvell
*
@@ -86,6 +86,21 @@ static struct cpuidle_driver armada370_idle_driver = {
.state_count = 2,
};
+static struct cpuidle_driver armada38x_idle_driver = {
+ .name = "armada_38x_idle",
+ .states[0] = ARM_CPUIDLE_WFI_STATE,
+ .states[1] = {
+ .enter = mvebu_v7_enter_idle,
+ .exit_latency = 10,
+ .power_usage = 5,
+ .target_residency = 100,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .name = "Idle",
+ .desc = "CPU and SCU power down",
+ },
+ .state_count = 2,
+};
+
static int mvebu_v7_cpuidle_probe(struct platform_device *pdev)
{
mvebu_v7_cpu_suspend = pdev->dev.platform_data;
@@ -94,6 +109,8 @@ static int mvebu_v7_cpuidle_probe(struct platform_device *pdev)
return cpuidle_register(&armadaxp_idle_driver, NULL);
else if (!strcmp(pdev->dev.driver->name, "cpuidle-armada-370"))
return cpuidle_register(&armada370_idle_driver, NULL);
+ else if (!strcmp(pdev->dev.driver->name, "cpuidle-armada-38x"))
+ return cpuidle_register(&armada38x_idle_driver, NULL);
else
return -EINVAL;
}
@@ -118,6 +135,16 @@ static struct platform_driver armada370_cpuidle_plat_driver = {
module_platform_driver(armada370_cpuidle_plat_driver);
+static struct platform_driver armada38x_cpuidle_plat_driver = {
+ .driver = {
+ .name = "cpuidle-armada-38x",
+ .owner = THIS_MODULE,
+ },
+ .probe = mvebu_v7_cpuidle_probe,
+};
+
+module_platform_driver(armada38x_cpuidle_plat_driver);
+
MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
MODULE_DESCRIPTION("Marvell EBU v7 cpuidle driver");
MODULE_LICENSE("GPL");
--
2.0.0
^ permalink raw reply related
* [PATCHv3 12/16] cpuidle: mvebu: add Armada 370 support
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
This commit adds the list of cpuidle states supported by the Armada
370 SoC in the cpuidle-mvebu-v7 driver, as well as the necessary logic
around it to support this SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/cpuidle/cpuidle-mvebu-v7.c | 35 +++++++++++++++++++++++++++++++++--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/cpuidle/cpuidle-mvebu-v7.c b/drivers/cpuidle/cpuidle-mvebu-v7.c
index 7252fd8..d23597f 100644
--- a/drivers/cpuidle/cpuidle-mvebu-v7.c
+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
@@ -70,11 +70,32 @@ static struct cpuidle_driver armadaxp_idle_driver = {
.state_count = 3,
};
+static struct cpuidle_driver armada370_idle_driver = {
+ .name = "armada_370_idle",
+ .states[0] = ARM_CPUIDLE_WFI_STATE,
+ .states[1] = {
+ .enter = mvebu_v7_enter_idle,
+ .exit_latency = 100,
+ .power_usage = 5,
+ .target_residency = 1000,
+ .flags = (CPUIDLE_FLAG_TIME_VALID |
+ MVEBU_V7_FLAG_DEEP_IDLE),
+ .name = "Deep Idle",
+ .desc = "CPU and L2 Fabric power down",
+ },
+ .state_count = 2,
+};
+
static int mvebu_v7_cpuidle_probe(struct platform_device *pdev)
{
-
mvebu_v7_cpu_suspend = pdev->dev.platform_data;
- return cpuidle_register(&armadaxp_idle_driver, NULL);
+
+ if (!strcmp(pdev->dev.driver->name, "cpuidle-armada-xp"))
+ return cpuidle_register(&armadaxp_idle_driver, NULL);
+ else if (!strcmp(pdev->dev.driver->name, "cpuidle-armada-370"))
+ return cpuidle_register(&armada370_idle_driver, NULL);
+ else
+ return -EINVAL;
}
static struct platform_driver armadaxp_cpuidle_plat_driver = {
@@ -87,6 +108,16 @@ static struct platform_driver armadaxp_cpuidle_plat_driver = {
module_platform_driver(armadaxp_cpuidle_plat_driver);
+static struct platform_driver armada370_cpuidle_plat_driver = {
+ .driver = {
+ .name = "cpuidle-armada-370",
+ .owner = THIS_MODULE,
+ },
+ .probe = mvebu_v7_cpuidle_probe,
+};
+
+module_platform_driver(armada370_cpuidle_plat_driver);
+
MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
MODULE_DESCRIPTION("Marvell EBU v7 cpuidle driver");
MODULE_LICENSE("GPL");
--
2.0.0
^ permalink raw reply related
* [PATCHv3 11/16] cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
This driver will be able to manage the cpuidle for more SoCs than just
Armada 370 and XP. It will also support Armada 38x and potentially
other SoC of the Marvell Armada EBU family. To take this into account,
this patch renames the driver and its symbols.
It also changes the driver name from cpuidle-armada-370-xp to
cpuidle-armada-xp, because separate platform drivers will be
registered for the other SoC types. This change must be done
simultaneously in the cpuidle driver and in the PMSU code in order to
remain bisectable.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/pmsu.c | 2 +-
drivers/cpuidle/Kconfig.arm | 12 +++----
drivers/cpuidle/Makefile | 2 +-
...{cpuidle-armada-370-xp.c => cpuidle-mvebu-v7.c} | 39 +++++++++++-----------
4 files changed, 27 insertions(+), 28 deletions(-)
rename drivers/cpuidle/{cpuidle-armada-370-xp.c => cpuidle-mvebu-v7.c} (58%)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 15e67bf..0cd2d09 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -76,7 +76,7 @@ extern void armada_370_xp_cpu_resume(void);
static void *mvebu_cpu_resume;
static struct platform_device mvebu_v7_cpuidle_device = {
- .name = "cpuidle-armada-370-xp",
+ .name = "cpuidle-armada-xp",
};
static struct of_device_id of_pmsu_table[] = {
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index b6d69e8..a563427 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -1,12 +1,6 @@
#
# ARM CPU Idle drivers
#
-config ARM_ARMADA_370_XP_CPUIDLE
- bool "CPU Idle Driver for Armada 370/XP family processors"
- depends on ARCH_MVEBU
- help
- Select this to enable cpuidle on Armada 370/XP processors.
-
config ARM_BIG_LITTLE_CPUIDLE
bool "Support for ARM big.LITTLE processors"
depends on ARCH_VEXPRESS_TC2_PM
@@ -61,3 +55,9 @@ config ARM_EXYNOS_CPUIDLE
depends on ARCH_EXYNOS
help
Select this to enable cpuidle for Exynos processors
+
+config ARM_MVEBU_V7_CPUIDLE
+ bool "CPU Idle Driver for mvebu v7 family processors"
+ depends on ARCH_MVEBU
+ help
+ Select this to enable cpuidle on Armada 370, 38x and XP processors.
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index d8bb1ff..11edb31 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -7,7 +7,7 @@ obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
##################################################################################
# ARM SoC drivers
-obj-$(CONFIG_ARM_ARMADA_370_XP_CPUIDLE) += cpuidle-armada-370-xp.o
+obj-$(CONFIG_ARM_MVEBU_V7_CPUIDLE) += cpuidle-mvebu-v7.o
obj-$(CONFIG_ARM_BIG_LITTLE_CPUIDLE) += cpuidle-big_little.o
obj-$(CONFIG_ARM_CLPS711X_CPUIDLE) += cpuidle-clps711x.o
obj-$(CONFIG_ARM_HIGHBANK_CPUIDLE) += cpuidle-calxeda.o
diff --git a/drivers/cpuidle/cpuidle-armada-370-xp.c b/drivers/cpuidle/cpuidle-mvebu-v7.c
similarity index 58%
rename from drivers/cpuidle/cpuidle-armada-370-xp.c
rename to drivers/cpuidle/cpuidle-mvebu-v7.c
index 28587d0..7252fd8 100644
--- a/drivers/cpuidle/cpuidle-armada-370-xp.c
+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
@@ -21,12 +21,11 @@
#include <linux/platform_device.h>
#include <asm/cpuidle.h>
-#define ARMADA_370_XP_MAX_STATES 3
-#define ARMADA_370_XP_FLAG_DEEP_IDLE 0x10000
+#define MVEBU_V7_FLAG_DEEP_IDLE 0x10000
-static int (*armada_370_xp_cpu_suspend)(int);
+static int (*mvebu_v7_cpu_suspend)(int);
-static int armada_370_xp_enter_idle(struct cpuidle_device *dev,
+static int mvebu_v7_enter_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
@@ -34,10 +33,10 @@ static int armada_370_xp_enter_idle(struct cpuidle_device *dev,
bool deepidle = false;
cpu_pm_enter();
- if (drv->states[index].flags & ARMADA_370_XP_FLAG_DEEP_IDLE)
+ if (drv->states[index].flags & MVEBU_V7_FLAG_DEEP_IDLE)
deepidle = true;
- ret = armada_370_xp_cpu_suspend(deepidle);
+ ret = mvebu_v7_cpu_suspend(deepidle);
if (ret)
return ret;
@@ -46,11 +45,11 @@ static int armada_370_xp_enter_idle(struct cpuidle_device *dev,
return index;
}
-static struct cpuidle_driver armada_370_xp_idle_driver = {
- .name = "armada_370_xp_idle",
+static struct cpuidle_driver armadaxp_idle_driver = {
+ .name = "armada_xp_idle",
.states[0] = ARM_CPUIDLE_WFI_STATE,
.states[1] = {
- .enter = armada_370_xp_enter_idle,
+ .enter = mvebu_v7_enter_idle,
.exit_latency = 10,
.power_usage = 50,
.target_residency = 100,
@@ -59,35 +58,35 @@ static struct cpuidle_driver armada_370_xp_idle_driver = {
.desc = "CPU power down",
},
.states[2] = {
- .enter = armada_370_xp_enter_idle,
+ .enter = mvebu_v7_enter_idle,
.exit_latency = 100,
.power_usage = 5,
.target_residency = 1000,
.flags = CPUIDLE_FLAG_TIME_VALID |
- ARMADA_370_XP_FLAG_DEEP_IDLE,
+ MVEBU_V7_FLAG_DEEP_IDLE,
.name = "MV CPU DEEP IDLE",
.desc = "CPU and L2 Fabric power down",
},
- .state_count = ARMADA_370_XP_MAX_STATES,
+ .state_count = 3,
};
-static int armada_370_xp_cpuidle_probe(struct platform_device *pdev)
+static int mvebu_v7_cpuidle_probe(struct platform_device *pdev)
{
- armada_370_xp_cpu_suspend = (void *)(pdev->dev.platform_data);
- return cpuidle_register(&armada_370_xp_idle_driver, NULL);
+ mvebu_v7_cpu_suspend = pdev->dev.platform_data;
+ return cpuidle_register(&armadaxp_idle_driver, NULL);
}
-static struct platform_driver armada_370_xp_cpuidle_plat_driver = {
+static struct platform_driver armadaxp_cpuidle_plat_driver = {
.driver = {
- .name = "cpuidle-armada-370-xp",
+ .name = "cpuidle-armada-xp",
.owner = THIS_MODULE,
},
- .probe = armada_370_xp_cpuidle_probe,
+ .probe = mvebu_v7_cpuidle_probe,
};
-module_platform_driver(armada_370_xp_cpuidle_plat_driver);
+module_platform_driver(armadaxp_cpuidle_plat_driver);
MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
-MODULE_DESCRIPTION("Armada 370/XP cpu idle driver");
+MODULE_DESCRIPTION("Marvell EBU v7 cpuidle driver");
MODULE_LICENSE("GPL");
--
2.0.0
^ permalink raw reply related
* [PATCHv3 10/16] ARM: mvebu: add CA9 MPcore SoC Controller node
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
The CA9 MPcore SoC Control block is a set of registers that allows to
configure certain internal aspects of the core blocks of the SoC
(Cortex-A9, L2 cache controller, etc.). In most cases, the default
values are fine so they aren't many reasons to touch those registers,
but there is one exception: to support cpuidle on Armada 38x, we need
to modify the value of the CA9 MPcore Reset Control register.
Therefore, this commit adds a new Device Tree binding for this
hardware block, and uses this new binding for the Armada 38x Device
Tree file.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree at vger.kernel.org
---
.../devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt | 14 ++++++++++++++
arch/arm/boot/dts/armada-38x.dtsi | 5 +++++
2 files changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt b/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt
new file mode 100644
index 0000000..8781073
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt
@@ -0,0 +1,14 @@
+Marvell Armada 38x CA9 MPcore SoC Controller
+============================================
+
+Required properties:
+
+- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
+
+- reg: should be the register base and length as documented in the
+ datasheet for the CA9 MPcore SoC Control registers
+
+mpcore-soc-ctrl at 20d20 {
+ compatible = "marvell,armada-380-mpcore-soc-ctrl";
+ reg = <0x20d20 0x6c>;
+};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 689fa1a..242d0ec 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -286,6 +286,11 @@
reg = <0x20800 0x10>;
};
+ mpcore-soc-ctrl at 20d20 {
+ compatible = "marvell,armada-380-mpcore-soc-ctrl";
+ reg = <0x20d20 0x6c>;
+ };
+
coherency-fabric at 21010 {
compatible = "marvell,armada-380-coherency-fabric";
reg = <0x21010 0x1c>;
--
2.0.0
^ permalink raw reply related
* [PATCHv3 09/16] ARM: mvebu: export the SCU address
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
The SCU address will be needed in other files than board-v7.c,
especially in pmsu.c for cpuidle related activities. So this patch
adds a function that allows to retrieve the virtual address at which
the SCU has been mapped.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/board-v7.c | 9 +++++++--
arch/arm/mach-mvebu/common.h | 2 ++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index f244622..6478626 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -34,14 +34,14 @@
#include "coherency.h"
#include "mvebu-soc-id.h"
+static void __iomem *scu_base;
+
/*
* Enables the SCU when available. Obviously, this is only useful on
* Cortex-A based SOCs, not on PJ4B based ones.
*/
static void __init mvebu_scu_enable(void)
{
- void __iomem *scu_base;
-
struct device_node *np =
of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
if (np) {
@@ -51,6 +51,11 @@ static void __init mvebu_scu_enable(void)
}
}
+void __iomem *mvebu_get_scu_base(void)
+{
+ return scu_base;
+}
+
/*
* Early versions of Armada 375 SoC have a bug where the BootROM
* leaves an external data abort pending. The kernel is hit by this
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index a97778e..3ccb40c 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -23,4 +23,6 @@ void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr);
void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr);
int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev);
+void __iomem *mvebu_get_scu_base(void);
+
#endif
--
2.0.0
^ permalink raw reply related
* [PATCHv3 08/16] ARM: mvebu: make the snoop disabling optional in mvebu_v7_pmsu_idle_prepare()
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
On some mvebu v7 SoCs (the ones using a Cortex-A9 core and not a PJ4B
core), the snoop disabling feature does not exist as the hardware
coherency is handled in a different way. Therefore, in preparation to
the introduction of the cpuidle support for those SoCs, this commit
modifies the mvebu_v7_psmu_idle_prepare() function to take several
flags, which allow to decide whether snooping should be disabled, and
whether we should use the deep idle mode or not.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/pmsu.c | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index ab525b7..15e67bf 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -191,8 +191,14 @@ static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
}
+enum pmsu_idle_prepare_flags {
+ PMSU_PREPARE_NORMAL = 0,
+ PMSU_PREPARE_DEEP_IDLE = BIT(0),
+ PMSU_PREPARE_SNOOP_DISABLE = BIT(1),
+};
+
/* No locking is needed because we only access per-CPU registers */
-static int mvebu_v7_pmsu_idle_prepare(bool deepidle)
+static int mvebu_v7_pmsu_idle_prepare(unsigned long flags)
{
unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
u32 reg;
@@ -216,26 +222,32 @@ static int mvebu_v7_pmsu_idle_prepare(bool deepidle)
reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
/* ask HW to power down the L2 Cache if needed */
- if (deepidle)
+ if (flags & PMSU_PREPARE_DEEP_IDLE)
reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
/* request power down */
reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
- /* Disable snoop disable by HW - SW is taking care of it */
- reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
- reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
- writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+ if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
+ /* Disable snoop disable by HW - SW is taking care of it */
+ reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+ reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
+ writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+ }
return 0;
}
int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
{
+ unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE;
int ret;
- ret = mvebu_v7_pmsu_idle_prepare(deepidle);
+ if (deepidle)
+ flags |= PMSU_PREPARE_DEEP_IDLE;
+
+ ret = mvebu_v7_pmsu_idle_prepare(flags);
if (ret)
return ret;
--
2.0.0
^ permalink raw reply related
* [PATCHv3 07/16] ARM: mvebu: use a local variable to store the resume address
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
The resume address used by the cpuidle code will not always be the
same depending on the SoC. Using a local variable to store the resume
address allows to keep the same function for the PM notifier but with
a different address. This address will be set during the
initialization of the cpuidle logic in pmsu.c.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/pmsu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index e976c3e..ab525b7 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -73,6 +73,8 @@ extern void ll_enable_coherency(void);
extern void armada_370_xp_cpu_resume(void);
+static void *mvebu_cpu_resume;
+
static struct platform_device mvebu_v7_cpuidle_device = {
.name = "cpuidle-armada-370-xp",
};
@@ -299,7 +301,7 @@ static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
{
if (action == CPU_PM_ENTER) {
unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
- mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
+ mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume);
} else if (action == CPU_PM_EXIT) {
mvebu_v7_pmsu_idle_exit();
}
@@ -320,6 +322,7 @@ static int __init armada_xp_cpuidle_init(void)
return -ENODEV;
of_node_put(np);
+ mvebu_cpu_resume = armada_370_xp_cpu_resume;
mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
return 0;
--
2.0.0
^ permalink raw reply related
* [PATCHv3 06/16] ARM: mvebu: make the cpuidle initialization more generic
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
In preparation to the addition of the cpuidle support for more SoCs,
this patch moves the Armada XP specific initialization to a separate
function.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/pmsu.c | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 501d450..e976c3e 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -311,31 +311,39 @@ static struct notifier_block mvebu_v7_cpu_pm_notifier = {
.notifier_call = mvebu_v7_cpu_pm_notify,
};
-static int __init mvebu_v7_cpu_pm_init(void)
+static int __init armada_xp_cpuidle_init(void)
{
struct device_node *np;
- /*
- * Check that all the requirements are available to enable
- * cpuidle. So far, it is only supported on Armada XP, cpuidle
- * needs the coherency fabric and the PMSU enabled
- */
-
- if (!of_machine_is_compatible("marvell,armadaxp"))
- return 0;
-
np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
if (!np)
- return 0;
+ return -ENODEV;
of_node_put(np);
+ mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
+
+ return 0;
+}
+
+static int __init mvebu_v7_cpu_pm_init(void)
+{
+ struct device_node *np;
+ int ret;
+
np = of_find_matching_node(NULL, of_pmsu_table);
if (!np)
return 0;
of_node_put(np);
+ if (of_machine_is_compatible("marvell,armadaxp"))
+ ret = armada_xp_cpuidle_init();
+ else
+ return 0;
+
+ if (ret)
+ return ret;
+
mvebu_v7_pmsu_enable_l2_powerdown_onidle();
- mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
platform_device_register(&mvebu_v7_cpuidle_device);
cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
--
2.0.0
^ permalink raw reply related
* [PATCHv3 05/16] ARM: mvebu: rename the armada_370_xp symbols to mvebu_v7 in pmsu.c
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Most of the function related to the PMSU are not specific to the
Armada 370 or Armada XP SoCs. They can also be used for most of the
other mvebu ARMv7 SoCs, and will actually be used to support cpuidle
on Armada 38x.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/armada-370-xp.h | 1 -
arch/arm/mach-mvebu/platsmp.c | 2 +-
arch/arm/mach-mvebu/pmsu.c | 34 +++++++++++++++++-----------------
arch/arm/mach-mvebu/pmsu.h | 2 ++
4 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 52c1603a..84cd90d 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -25,6 +25,5 @@ extern struct smp_operations armada_xp_smp_ops;
#endif
int armada_370_xp_pmsu_idle_enter(unsigned long deepidle);
-void armada_370_xp_pmsu_idle_exit(void);
#endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index b6fa9f0..6da2b72 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -108,7 +108,7 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
static void armada_xp_secondary_init(unsigned int cpu)
{
- armada_370_xp_pmsu_idle_exit();
+ mvebu_v7_pmsu_idle_exit();
}
static void __init armada_xp_smp_init_cpus(void)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 272a9c05..501d450 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -73,7 +73,7 @@ extern void ll_enable_coherency(void);
extern void armada_370_xp_cpu_resume(void);
-static struct platform_device armada_xp_cpuidle_device = {
+static struct platform_device mvebu_v7_cpuidle_device = {
.name = "cpuidle-armada-370-xp",
};
@@ -132,7 +132,7 @@ int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
return 0;
}
-static int __init armada_370_xp_pmsu_init(void)
+static int __init mvebu_v7_pmsu_init(void)
{
struct device_node *np;
struct resource res;
@@ -176,7 +176,7 @@ static int __init armada_370_xp_pmsu_init(void)
return ret;
}
-static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
+static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
{
u32 reg;
@@ -190,7 +190,7 @@ static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
}
/* No locking is needed because we only access per-CPU registers */
-static int armada_370_xp_prepare(unsigned long deepidle)
+static int mvebu_v7_pmsu_idle_prepare(bool deepidle)
{
unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
u32 reg;
@@ -233,7 +233,7 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
{
int ret;
- ret = armada_370_xp_prepare(deepidle);
+ ret = mvebu_v7_pmsu_idle_prepare(deepidle);
if (ret)
return ret;
@@ -272,7 +272,7 @@ static int armada_370_xp_cpu_suspend(unsigned long deepidle)
}
/* No locking is needed because we only access per-CPU registers */
-void armada_370_xp_pmsu_idle_exit(void)
+void mvebu_v7_pmsu_idle_exit(void)
{
unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
u32 reg;
@@ -294,24 +294,24 @@ void armada_370_xp_pmsu_idle_exit(void)
writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
}
-static int armada_370_xp_cpu_pm_notify(struct notifier_block *self,
+static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
unsigned long action, void *hcpu)
{
if (action == CPU_PM_ENTER) {
unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
} else if (action == CPU_PM_EXIT) {
- armada_370_xp_pmsu_idle_exit();
+ mvebu_v7_pmsu_idle_exit();
}
return NOTIFY_OK;
}
-static struct notifier_block armada_370_xp_cpu_pm_notifier = {
- .notifier_call = armada_370_xp_cpu_pm_notify,
+static struct notifier_block mvebu_v7_cpu_pm_notifier = {
+ .notifier_call = mvebu_v7_cpu_pm_notify,
};
-static int __init armada_370_xp_cpu_pm_init(void)
+static int __init mvebu_v7_cpu_pm_init(void)
{
struct device_node *np;
@@ -334,13 +334,13 @@ static int __init armada_370_xp_cpu_pm_init(void)
return 0;
of_node_put(np);
- armada_370_xp_pmsu_enable_l2_powerdown_onidle();
- armada_xp_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
- platform_device_register(&armada_xp_cpuidle_device);
- cpu_pm_register_notifier(&armada_370_xp_cpu_pm_notifier);
+ mvebu_v7_pmsu_enable_l2_powerdown_onidle();
+ mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
+ platform_device_register(&mvebu_v7_cpuidle_device);
+ cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
return 0;
}
-arch_initcall(armada_370_xp_cpu_pm_init);
-early_initcall(armada_370_xp_pmsu_init);
+arch_initcall(mvebu_v7_cpu_pm_init);
+early_initcall(mvebu_v7_pmsu_init);
diff --git a/arch/arm/mach-mvebu/pmsu.h b/arch/arm/mach-mvebu/pmsu.h
index ae50194..6b58c1f 100644
--- a/arch/arm/mach-mvebu/pmsu.h
+++ b/arch/arm/mach-mvebu/pmsu.h
@@ -16,4 +16,6 @@ int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
unsigned int crypto_eng_attribute,
phys_addr_t resume_addr_reg);
+void mvebu_v7_pmsu_idle_exit(void);
+
#endif /* __MACH_370_XP_PMSU_H */
--
2.0.0
^ permalink raw reply related
* [PATCHv3 04/16] ARM: mvebu: use the common function for Armada 375 SMP workaround
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Use the common function mvebu_setup_boot_addr_wa() introduced in the
commit "ARM: mvebu: Add a common function for the boot address work
around" instead of the dedicated version for Armada 375.
This commit also moves the workaround in the system-controller
module. Indeed the workaround on 375 is really related to setting the
boot address which is done by the system controller.
As a bonus we no longer use an harcoded value to access the register
storing the boot address.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/headsmp-a9.S | 15 ------------
arch/arm/mach-mvebu/platsmp-a9.c | 42 +++------------------------------
arch/arm/mach-mvebu/system-controller.c | 31 ++++++++++++++++++++++++
3 files changed, 34 insertions(+), 54 deletions(-)
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
index da5bb29..be51c99 100644
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -18,21 +18,6 @@
#include <asm/assembler.h>
__CPUINIT
-#define CPU_RESUME_ADDR_REG 0xf10182d4
-
-.global armada_375_smp_cpu1_enable_code_start
-.global armada_375_smp_cpu1_enable_code_end
-
-armada_375_smp_cpu1_enable_code_start:
-ARM_BE8(setend be)
- adr r0, 1f
- ldr r0, [r0]
- ldr r1, [r0]
-ARM_BE8(rev r1, r1)
- mov pc, r1
-1:
- .word CPU_RESUME_ADDR_REG
-armada_375_smp_cpu1_enable_code_end:
ENTRY(mvebu_cortex_a9_secondary_startup)
ARM_BE8(setend be)
diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
index 43aaf3f..47a71a9 100644
--- a/arch/arm/mach-mvebu/platsmp-a9.c
+++ b/arch/arm/mach-mvebu/platsmp-a9.c
@@ -20,33 +20,8 @@
#include <asm/smp_scu.h>
#include <asm/smp_plat.h>
#include "common.h"
-#include "mvebu-soc-id.h"
#include "pmsu.h"
-#define CRYPT0_ENG_ID 41
-#define CRYPT0_ENG_ATTR 0x1
-#define SRAM_PHYS_BASE 0xFFFF0000
-
-#define BOOTROM_BASE 0xFFF00000
-#define BOOTROM_SIZE 0x100000
-
-extern unsigned char armada_375_smp_cpu1_enable_code_end;
-extern unsigned char armada_375_smp_cpu1_enable_code_start;
-
-static void armada_375_smp_cpu1_enable_wa(void)
-{
- void __iomem *sram_virt_base;
-
- mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
- mvebu_mbus_add_window_by_id(CRYPT0_ENG_ID, CRYPT0_ENG_ATTR,
- SRAM_PHYS_BASE, SZ_64K);
- sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
-
- memcpy(sram_virt_base, &armada_375_smp_cpu1_enable_code_start,
- &armada_375_smp_cpu1_enable_code_end
- - &armada_375_smp_cpu1_enable_code_start);
-}
-
extern void mvebu_cortex_a9_secondary_startup(void);
static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
@@ -63,21 +38,10 @@ static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
* address.
*/
hw_cpu = cpu_logical_map(cpu);
-
- if (of_machine_is_compatible("marvell,armada375")) {
- u32 dev, rev;
-
- if (mvebu_get_soc_id(&dev, &rev) == 0 &&
- rev == ARMADA_375_Z1_REV)
- armada_375_smp_cpu1_enable_wa();
-
+ if (of_machine_is_compatible("marvell,armada375"))
mvebu_system_controller_set_cpu_boot_addr(mvebu_cortex_a9_secondary_startup);
- }
- else {
- mvebu_pmsu_set_cpu_boot_addr(hw_cpu,
- mvebu_cortex_a9_secondary_startup);
- }
-
+ else
+ mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cortex_a9_secondary_startup);
smp_wmb();
ret = mvebu_cpu_reset_deassert(hw_cpu);
if (ret) {
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index b2b4e3d..a068cb5 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -28,8 +28,14 @@
#include <linux/io.h>
#include <linux/reboot.h>
#include "common.h"
+#include "mvebu-soc-id.h"
+#include "pmsu.h"
+
+#define ARMADA_375_CRYPT0_ENG_TARGET 41
+#define ARMADA_375_CRYPT0_ENG_ATTR 1
static void __iomem *system_controller_base;
+static phys_addr_t system_controller_phys_base;
struct mvebu_system_controller {
u32 rstoutn_mask_offset;
@@ -121,10 +127,32 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
}
#ifdef CONFIG_SMP
+void mvebu_armada375_smp_wa_init(void)
+{
+ u32 dev, rev;
+ phys_addr_t resume_addr_reg;
+
+ if (mvebu_get_soc_id(&dev, &rev) != 0)
+ return;
+
+ if (rev != ARMADA_375_Z1_REV)
+ return;
+
+ resume_addr_reg = system_controller_phys_base +
+ mvebu_sc->resume_boot_addr;
+ mvebu_setup_boot_addr_wa(ARMADA_375_CRYPT0_ENG_TARGET,
+ ARMADA_375_CRYPT0_ENG_ATTR,
+ resume_addr_reg);
+}
+
void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
{
BUG_ON(system_controller_base == NULL);
BUG_ON(mvebu_sc->resume_boot_addr == 0);
+
+ if (of_machine_is_compatible("marvell,armada375"))
+ mvebu_armada375_smp_wa_init();
+
writel(virt_to_phys(boot_addr), system_controller_base +
mvebu_sc->resume_boot_addr);
}
@@ -138,7 +166,10 @@ static int __init mvebu_system_controller_init(void)
np = of_find_matching_node_and_match(NULL, of_system_controller_table,
&match);
if (np) {
+ struct resource res;
system_controller_base = of_iomap(np, 0);
+ of_address_to_resource(np, 0, &res);
+ system_controller_phys_base = res.start;
mvebu_sc = (struct mvebu_system_controller *)match->data;
of_node_put(np);
}
--
2.0.0
^ permalink raw reply related
* [PATCHv3 03/16] ARM: mvebu: add a common function for the boot address work around
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
On some of the mvebu SoCs and due to internal BootROM issue, the CPU
initial jump code must be placed in the SRAM memory of the SoC. In
order to achieve this, we have to unmap the BootROM and at some
specific location where the BootROM was placed, create a dedicated
MBus window for the SRAM. This SRAM is initialized with a few
instructions of code that allows to jump to the real secondary CPU
boot address. The SRAM used is the Crypto engine one.
This work around is currently needed for booting SMP on Armada 375 Z1
and will be needed for cpuidle support on Armada 370. Instead of
duplicating the same code, this commit introduces a common function to
handle it: mvebu_setup_boot_addr_wa().
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/pmsu.c | 47 +++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-mvebu/pmsu.h | 3 +++
arch/arm/mach-mvebu/pmsu_ll.S | 22 ++++++++++++++++++++
3 files changed, 72 insertions(+)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 9e18cce..272a9c05 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -22,6 +22,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/mbus.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/resource.h>
@@ -63,6 +64,10 @@ static void __iomem *pmsu_mp_base;
#define L2C_NFABRIC_PM_CTL 0x4
#define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20)
+#define SRAM_PHYS_BASE 0xFFFF0000
+#define BOOTROM_BASE 0xFFF00000
+#define BOOTROM_SIZE 0x100000
+
extern void ll_disable_coherency(void);
extern void ll_enable_coherency(void);
@@ -85,6 +90,48 @@ void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
}
+extern unsigned char mvebu_boot_wa_start;
+extern unsigned char mvebu_boot_wa_end;
+
+/*
+ * This function sets up the boot address workaround needed for SMP
+ * boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
+ * BootROM Mbus window, and instead remaps a crypto SRAM into which a
+ * custom piece of code is copied to replace the problematic BootROM.
+ */
+int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
+ unsigned int crypto_eng_attribute,
+ phys_addr_t resume_addr_reg)
+{
+ void __iomem *sram_virt_base;
+ u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start;
+
+ mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
+ mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
+ SRAM_PHYS_BASE, SZ_64K);
+
+ sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
+ if (!sram_virt_base) {
+ pr_err("Unable to map SRAM to setup the boot address WA\n");
+ return -ENOMEM;
+ }
+
+ memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);
+
+ /*
+ * The last word of the code copied in SRAM must contain the
+ * physical base address of the PMSU register. We
+ * intentionally store this address in the native endianness
+ * of the system.
+ */
+ __raw_writel((unsigned long)resume_addr_reg,
+ sram_virt_base + code_len - 4);
+
+ iounmap(sram_virt_base);
+
+ return 0;
+}
+
static int __init armada_370_xp_pmsu_init(void)
{
struct device_node *np;
diff --git a/arch/arm/mach-mvebu/pmsu.h b/arch/arm/mach-mvebu/pmsu.h
index 07a737c..ae50194 100644
--- a/arch/arm/mach-mvebu/pmsu.h
+++ b/arch/arm/mach-mvebu/pmsu.h
@@ -12,5 +12,8 @@
#define __MACH_MVEBU_PMSU_H
int armada_xp_boot_cpu(unsigned int cpu_id, void *phys_addr);
+int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
+ unsigned int crypto_eng_attribute,
+ phys_addr_t resume_addr_reg);
#endif /* __MACH_370_XP_PMSU_H */
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index fc3de68..17d7f3b 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -23,3 +23,25 @@ ARM_BE8(setend be ) @ go BE8 if entered LE
b cpu_resume
ENDPROC(armada_370_xp_cpu_resume)
+.global mvebu_boot_wa_start
+.global mvebu_boot_wa_end
+
+/* The following code will be executed from SRAM */
+ENTRY(mvebu_boot_wa_start)
+mvebu_boot_wa_start:
+ARM_BE8(setend be)
+ adr r0, 1f
+ ldr r0, [r0] @ load the address of the
+ @ resume register
+ ldr r0, [r0] @ load the value in the
+ @ resume register
+ARM_BE8(rev r0, r0) @ the value is stored LE
+ mov pc, r0 @ jump to this value
+/*
+ * the last word of this piece of code will be filled by the physical
+ * address of the boot address register just after being copied in SRAM
+ */
+1:
+ .long .
+mvebu_boot_wa_end:
+ENDPROC(mvebu_boot_wa_end)
--
2.0.0
^ permalink raw reply related
* [PATCHv3 02/16] ARM: mvebu: sort the #include of pmsu.c in alphabetic order
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Sorting the headers in alphabetic order will help to reduce conflicts
when adding new headers later.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/pmsu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 5fda549..9e18cce 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -19,13 +19,13 @@
#define pr_fmt(fmt) "mvebu-pmsu: " fmt
#include <linux/cpu_pm.h>
-#include <linux/kernel.h>
#include <linux/init.h>
-#include <linux/of_address.h>
#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
-#include <linux/smp.h>
#include <linux/resource.h>
+#include <linux/smp.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_plat.h>
--
2.0.0
^ permalink raw reply related
* [PATCHv3 01/16] ARM: mvebu: split again armada_370_xp_pmsu_idle_enter() in PMSU code
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
do_armada_370_xp_cpu_suspend() and armada_370_xp_pmsu_idle_prepare(),
have been merged into a single function called
armada_370_xp_pmsu_idle_enter() by the commit "bbb92284b6c8 ARM:
mvebu: slightly refactor/rename PMSU idle related functions", in
prepare for the introduction of the CPU hotplug support for Armada XP.
But for cpuidle the prepare function will be common to all the mvebu
SoCs that use the PMSU, while the suspend function will be specific to
each SoC. Keeping the prepare function separate will help reducing
code duplication while new SoC support is added.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/pmsu.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index b31a829..5fda549 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -143,7 +143,7 @@ static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
}
/* No locking is needed because we only access per-CPU registers */
-int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
+static int armada_370_xp_prepare(unsigned long deepidle)
{
unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
u32 reg;
@@ -179,6 +179,17 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+ return 0;
+}
+
+int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
+{
+ int ret;
+
+ ret = armada_370_xp_prepare(deepidle);
+ if (ret)
+ return ret;
+
v7_exit_coherency_flush(all);
ll_disable_coherency();
--
2.0.0
^ permalink raw reply related
* [PATCHv3 00/16] cpuidle for Marvell Armada 370 and 38x
From: Thomas Petazzoni @ 2014-07-23 13:00 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
Here comes the third version of the cpuidle support for Armada 370 and
Armada 38x.
We are hoping to see this patch series merged for 3.17.
Most patches are touching only arch/arm/mach-mvebu/ code so they
should be handled by the mvebu maintainers. However, patches 11-13 are
touching the mvebu cpuidle driver, with a possible issue on patch 11,
which touches both the cpuidle driver and the mach-mvebu code in order
to rename the driver without breaking functionality (if needed, we can
decide to split the commits, it would break functionality temporarly,
but not buildability).
Changes since v2
================
* According to the discussion with Daniel Lezcano (cpuidle
maintainer) and Arnd Bergmann, changed the cpuidle-mvebu-v7 driver
to actually register three separate cpuidle platform driver, one
per-SoC. This way, we don't need special platform data to convey
the SoC type being used, as this information is already available
by looking at the driver name.
This change impacts the patches "cpuidle: mvebu: rename the driver
from armada-370-xp to mvebu-v7", "cpuidle: mvebu: add Armada 370
support", "cpuidle: mvebu: add Armada 38x support", "ARM: mvebu:
add cpuidle support for Armada 370" and "ARM: mvebu: add cpuidle
support for Armada 38x". Other patches are unchanged. The patch
"cpuidle: mvebu: make the cpuidle driver capable of handling
multiple SoCs" was no longer needed, so it has been removed.
Changes since v1
================
* Series rebased on top of mvebu/fixes + mvebu/soc to take into
account the conflicts with the changes already merged on the PMSU
code.
* Adjusted the fix that sorts the #include statements in pmsu.c by
alphabetic order to really use the alphabetic order.
* Various improvements to the implementation of the common function
for the boot address workaround:
- Main function renamed from mvebu_boot_addr_wa() to
mvebu_setup_boot_addr_wa().
- Both target and attribute of the crypto SRAM MBus window are now
passed as arguments.
- Use appropriate types for arguments.
- Add error checking for ioremap() call.
- Use __raw_writel() instead of direct pointer dereference
- Fix the assembly code to work properly in big-endian
configurations.
* Misc small fixes in the migration of the Armada 375 SMP code to use
the common function for the boot address workaround: use correct
types, split in a separate function to reduce the indentation
level, use better naming for macros, etc.
* Re-organized the commits by grouping several patches that were
separate before, to for example have a single patch to introduce
the cpuidle support on Armada 370.
* Move back into the cpuidle driver the list of the cpuidle states
for each SoC.
* Numerous other small typos and improvements.
Thanks,
Thomas
Gregory CLEMENT (14):
ARM: mvebu: split again armada_370_xp_pmsu_idle_enter() in PMSU code
ARM: mvebu: sort the #include of pmsu.c in alphabetic order
ARM: mvebu: add a common function for the boot address work around
ARM: mvebu: use the common function for Armada 375 SMP workaround
ARM: mvebu: rename the armada_370_xp symbols to mvebu_v7 in pmsu.c
ARM: mvebu: make the cpuidle initialization more generic
ARM: mvebu: use a local variable to store the resume address
ARM: mvebu: make the snoop disabling optional in
mvebu_v7_pmsu_idle_prepare()
ARM: mvebu: export the SCU address
ARM: mvebu: add CA9 MPcore SoC Controller node
cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
ARM: mvebu: add cpuidle support for Armada 370
ARM: mvebu: add cpuidle support for Armada 38x
ARM: mvebu: defconfig: enable cpuidle support in mvebu_v7_defconfig
Thomas Petazzoni (2):
cpuidle: mvebu: add Armada 370 support
cpuidle: mvebu: add Armada 38x support
.../bindings/arm/armada-380-mpcore-soc-ctrl.txt | 14 ++
arch/arm/boot/dts/armada-38x.dtsi | 5 +
arch/arm/configs/mvebu_v7_defconfig | 2 +
arch/arm/mach-mvebu/armada-370-xp.h | 1 -
arch/arm/mach-mvebu/board-v7.c | 9 +-
arch/arm/mach-mvebu/common.h | 2 +
arch/arm/mach-mvebu/headsmp-a9.S | 15 --
arch/arm/mach-mvebu/platsmp-a9.c | 42 +---
arch/arm/mach-mvebu/platsmp.c | 2 +-
arch/arm/mach-mvebu/pmsu.c | 273 ++++++++++++++++++---
arch/arm/mach-mvebu/pmsu.h | 5 +
arch/arm/mach-mvebu/pmsu_ll.S | 36 +++
arch/arm/mach-mvebu/system-controller.c | 31 +++
drivers/cpuidle/Kconfig.arm | 12 +-
drivers/cpuidle/Makefile | 2 +-
drivers/cpuidle/cpuidle-armada-370-xp.c | 93 -------
drivers/cpuidle/cpuidle-mvebu-v7.c | 150 +++++++++++
17 files changed, 500 insertions(+), 194 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt
delete mode 100644 drivers/cpuidle/cpuidle-armada-370-xp.c
create mode 100644 drivers/cpuidle/cpuidle-mvebu-v7.c
--
2.0.0
^ permalink raw reply
* [PATCH v2 1/2] clk: samsung: exynos4: Enable ARMCLK down feature
From: Tomasz Figa @ 2014-07-23 12:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405694193-29643-1-git-send-email-k.kozlowski@samsung.com>
Hi Krzysztof,
On 18.07.2014 16:36, Krzysztof Kozlowski wrote:
> Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of
> ARMCLK will be reduced upon entering idle mode (WFI or WFE).
Will apply the whole series to Samsung clock tree.
Best regards,
Tomasz
^ permalink raw reply
* [PATCH v2 14/16] cpufreq: Add cpufreq driver for Tegra124
From: Tuomas Tynkkynen @ 2014-07-23 12:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140723070949.GB15759@ulmo.nvidia.com>
On 23/07/14 10:09, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Jul 21, 2014 at 06:39:00PM +0300, Tuomas Tynkkynen wrote:
> [...]
>> diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c
> [...]
>> +static int tegra124_cpu_switch_to_dfll(void)
>> +{
>> + struct clk *original_cpu_clk_parent;
>
> Maybe just "parent"?
>
>> + unsigned long rate;
>> + struct dev_pm_opp *opp;
>> + int ret;
>> +
>> + rate = clk_get_rate(cpu_clk);
>> + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
>> + if (IS_ERR(opp))
>> + return PTR_ERR(opp);
>> +
>> + ret = clk_set_rate(dfll_clk, rate);
>> + if (ret)
>> + return ret;
>> +
>> + original_cpu_clk_parent = clk_get_parent(cpu_clk);
>> + clk_set_parent(cpu_clk, pllp_clk);
>> + if (ret)
>> + return ret;
>> +
>> + ret = clk_prepare_enable(dfll_clk);
>> + if (ret)
>> + goto out_switch_to_original_parent;
>
> This could simply be "out" or "err" or anything else shorter than the
> above.
>
>> +
>> + clk_set_parent(cpu_clk, dfll_clk);
>> +
>> + return 0;
>> +
>> +out_switch_to_original_parent:
>> + clk_set_parent(cpu_clk, original_cpu_clk_parent);
>> +
>> + return ret;
>> +}
>> +
>> +static struct platform_device_info cpufreq_cpu0_devinfo = {
>> + .name = "cpufreq-cpu0",
>> +};
>> +
>> +static int tegra124_cpufreq_probe(struct platform_device *pdev)
>> +{
>> + int ret;
>> +
>> + cpu_dev = get_cpu_device(0);
>> + if (!cpu_dev)
>> + return -ENODEV;
>> +
>> + cpu_clk = of_clk_get_by_name(cpu_dev->of_node, "cpu_g");
>> + if (IS_ERR(cpu_clk))
>> + return PTR_ERR(cpu_clk);
>> +
>> + dfll_clk = of_clk_get_by_name(cpu_dev->of_node, "dfll");
>> + if (IS_ERR(dfll_clk)) {
>> + ret = PTR_ERR(dfll_clk);
>> + goto out_put_cpu_clk;
>> + }
>> +
>> + pllx_clk = of_clk_get_by_name(cpu_dev->of_node, "pll_x");
>> + if (IS_ERR(pllx_clk)) {
>> + ret = PTR_ERR(pllx_clk);
>> + goto out_put_dfll_clk;
>> + }
>> +
>> + pllp_clk = of_clk_get_by_name(cpu_dev->of_node, "pll_p");
>> + if (IS_ERR(pllp_clk)) {
>> + ret = PTR_ERR(pllp_clk);
>> + goto out_put_pllx_clk;
>> + }
>
> Can the above not be devm_clk_get(cpu_dev, "...") so that you can remove
> all the clk_put() calls in the cleanup code below?
That would allocate the clks under the cpu_dev's devres list, i.e. all the
clk_puts wouldn't happen when the cpufreq driver goes away, but only when
cpu_dev itself goes away.
>
>> +
>> + ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
>> + if (ret)
>> + goto out_put_pllp_clk;
>> +
>> + ret = tegra124_cpu_switch_to_dfll();
>> + if (ret)
>> + goto out_free_table;
>> +
>> + platform_device_register_full(&cpufreq_cpu0_devinfo);
>
> Should the cpufreq_cpu0_devinfo device perhaps be a child of pdev?
Yeah, I suppose it should.
>> +
>> + return 0;
>> +
>> +out_free_table:
>> + dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
>> +out_put_pllp_clk:
>> + clk_put(pllp_clk);
>> +out_put_pllx_clk:
>> + clk_put(pllx_clk);
>> +out_put_dfll_clk:
>> + clk_put(dfll_clk);
>> +out_put_cpu_clk:
>> + clk_put(cpu_clk);
>> +
>> + return ret;
>> +}
>> +
>> +static struct platform_driver tegra124_cpufreq_platdrv = {
>> + .driver = {
>> + .name = "cpufreq-tegra124",
>> + .owner = THIS_MODULE,
>> + },
>> + .probe = tegra124_cpufreq_probe,
>
> Note that simply leaving out .remove() here doesn't guarantee that the
> driver won't be unloaded. Also building it into the kernel doesn't
> prevent that. You can still unbind the driver via sysfs. So you'd need
> to add a .suppress_bind_attrs = true above.
I hadn't heard about suppress_bind_attrs before, it indeed sounds useful.
> But is there even a reason why we need that? Couldn't we make the
> driver's .remove() undo what .probe() did so that the driver can be
> unloaded?
I guess that could be done, though to fully undo everything the regulator
voltage would also need to be saved/restored.
> Otherwise it probably makes more sense not to use a driver (and dummy
> device) at all as Viresh already mentioned.
>
The dummy platform device is only required for probe deferral, if that
could be solved in a different way then yes.
>> +};
>> +
>> +static const struct of_device_id soc_of_matches[] = {
>> + { .compatible = "nvidia,tegra124", },
>> + {}
>> +};
>> +
>> +static int __init tegra_cpufreq_init(void)
>> +{
>> + int ret;
>> + struct platform_device *pdev;
>> +
>> + if (!of_find_matching_node(NULL, soc_of_matches))
>> + return -ENODEV;
>
> I think this could be of_machine_is_compatible() since there's only a
> single entry in the match table. If there's a good chance that we may
> end up with more entries, perhaps now would be a good time to add an
> of_match_machine() function?
I think this driver should work on Tegra132 without modifications.
of_match_machine() does sound useful for some of the other cpufreq
drivers as well and likely for your soc_is_tegra() from the PMC
series as well.
>
>> +
>> + ret = platform_driver_register(&tegra124_cpufreq_platdrv);
>> + if (ret)
>> + return ret;
>> +
>> + pdev = platform_device_register_simple("cpufreq-tegra124", -1, NULL, 0);
>> + if (IS_ERR(pdev)) {
>> + platform_driver_unregister(&tegra124_cpufreq_platdrv);
>> + return PTR_ERR(pdev);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +MODULE_AUTHOR("Tuomas Tynkkynen <ttynkkynen@nvidia.com>");
>> +MODULE_DESCRIPTION("cpufreq driver for nVIDIA Tegra124");
>
> We use "NVIDIA" everywhere nowadays.
>
>> +MODULE_LICENSE("GPLv2");
>
> The correct license string is "GPL v2".
>
>> +module_init(tegra_cpufreq_init);
>
> The placement of this is unusual. It should go immediately below the
> tegra_cpufreq_init() function.
>
Ok.
Thanks,
Tuomas
--
nvpublic
^ permalink raw reply
* [PATCH -next] ARM: mvebu: fix return value check in armada_xp_pmsu_cpufreq_init()
From: Jason Cooper @ 2014-07-23 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406038688-26417-1-git-send-email-weiyj_lk@163.com>
On Tue, Jul 22, 2014 at 10:18:08PM +0800, weiyj_lk at 163.com wrote:
> From: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
>
> In case of error, the function clk_get() returns ERR_PTR()
> and never returns NULL. The NULL test in the return value
> check should be replaced with IS_ERR().
>
> Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
> ---
> arch/arm/mach-mvebu/pmsu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Applied to mvebu/soc.
thx,
Jason.
^ permalink raw reply
* [PATCH v5 0/2] i2c: add DMA support for freescale i2c driver
From: Marek Vasut @ 2014-07-23 12:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406103883-3572-1-git-send-email-yao.yuan@freescale.com>
On Wednesday, July 23, 2014 at 10:24:41 AM, Yuan Yao wrote:
> Changed in v5:
> - add "*chan_dev = dma->chan_using->device->dev" for reduce the call time.
Did you check if the compiler generates different code ?
> - add the test logs.
[...]
Best regards,
Marek Vasut
^ permalink raw reply
* [GIT PULL] Xilinx Zynq dt changes for v3.17 - second pull request
From: Michal Simek @ 2014-07-23 12:26 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
please add these two patches to your arm-soc tree.
This branch is based on zynq/dt branch which is already
in your tree.
http://git.kernel.org/cgit/linux/kernel/git/arm/arm-soc.git/log/?h=zynq/dt
GPIO driver and binding are already available in Linus gpio tree
and it enables us to do testing on Linux-next.
Thanks,
Michal
The following changes since commit 8fe9346b945d76ddb3f08c00e34d701174c62fa0:
ARM: zynq: DT: Migrate UART to Cadence binding (2014-07-18 11:54:24 +0200)
are available in the git repository at:
git://git.xilinx.com/linux-xlnx.git tags/zynq-dt-for-3.17-2
for you to fetch changes up to e0a5c552caf7a4865f3d5aa077003ef2d35217db:
ARM: zynq: DT: Add GPIO node (2014-07-23 14:05:56 +0200)
----------------------------------------------------------------
arm: Xilinx Zynq dt patches for v3.17 second pull request
- Add GPIO and XADC node to dtsi
----------------------------------------------------------------
Soren Brinkmann (2):
ARM: zynq: DT: Add XADC node
ARM: zynq: DT: Add GPIO node
arch/arm/boot/dts/zynq-7000.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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^ permalink raw reply
* [GIT PULL] ARM: mvebu: DT fixes for v3.17 (round 3)
From: Jason Cooper @ 2014-07-23 12:18 UTC (permalink / raw)
To: linux-arm-kernel
All,
This is a small round of fixes for new nodes adding ethernet support to
Armada 375. Since the nodes were only added for v3.17, these patches
are queued for v3.17, instead of as fixes for v3.16-rcX.
This is an incremental pull request from tags/mvebu-dt-3.17-2 up to
tags/mvebu-dt-3.17-3 on the mvebu/dt branch.
Please pull.
thx,
Jason.
The following changes since commit 3843607838cc5436d02a6771e661969a54c2fee0:
ARM: mvebu: update Armada XP DT for dynamic frequency scaling (2014-07-16 12:54:13 +0000)
are available in the git repository at:
git://git.infradead.org/linux-mvebu.git tags/mvebu-dt-3.17-3
for you to fetch changes up to 112dc53db1c27594e3b1504189c2004115fb1914:
ARM: mvebu: Add missing MDIO clock in Armada 375 (2014-07-23 12:04:40 +0000)
----------------------------------------------------------------
mvebu DT changes for v3.17 (round 3)
- Armada 375
- Fix ethernet aliases for new node added for v3.17
- Add missing MDIO clock for new node added for v3.17
----------------------------------------------------------------
Ezequiel Garcia (1):
ARM: mvebu: Add missing MDIO clock in Armada 375
Marcin Wojtas (1):
ARM: mvebu: Add ethernet aliases required by U-Boot
arch/arm/boot/dts/armada-375.dtsi | 3 +++
1 file changed, 3 insertions(+)
^ permalink raw reply
* [PATCH v5 1/2] i2c: add DMA support for freescale i2c driver
From: Lothar Waßmann @ 2014-07-23 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <53CF9933.8030908@gmail.com>
Hi,
Varka Bhadram wrote:
> On 07/23/2014 04:41 PM, Yao Yuan wrote:
> > Hi,
> >
> > Thanks for your review.
> >
> > Lothar Wa?mann wrote:
> >> Yuan Yao wrote:
> >>> Add dma support for i2c. This function depend on DMA driver.
> >>> You can turn on it by write both the dmas and dma-name properties in dts node.
> >>>
> >>> Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
> >>> ---
> >>> drivers/i2c/busses/i2c-imx.c | 377
> > [...]
> >>> +
> >>> +fail_rx:
> >>> + dma_release_channel(dma->chan_rx);
> >>> +fail_tx:
> >>> + dma_release_channel(dma->chan_tx);
> >>> +fail_al:
> >>> + devm_kfree(dev, dma);
> >>>
> >> No need for this one (that's the whole point of using devm_kzalloc())!
> >>
> > When DMA request failed, I2C will switch to PIO mode. So if the failed reason is just like DMA channel request failed. At this time the DMA should free by devm_kfree(). Is it?
>
> If probe failed the memory will be freed automatically because
> we are using devm_kzalloc()...
>
> If we use devm_kzalloc() ,no need to free manually on fail...
>
Yes, but as Yuan Yao stated, the driver will still work
without DMA but carry around the unecessary allocated imx_i2c_dma
struct.
The devm_kfree() is not in the failure path of the driver's probe()
function, but in the function that tries to initialize the optional DMA
support.
Lothar Wa?mann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________
^ permalink raw reply
* [PATCH 0/6] net: mvpp2: Assorted fixes
From: Jason Cooper @ 2014-07-23 12:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405961296-5846-1-git-send-email-ezequiel.garcia@free-electrons.com>
On Mon, Jul 21, 2014 at 01:48:10PM -0300, Ezequiel Garcia wrote:
> This patchset contains a set of fixes for issues found while doing some
> more intensive tests on the recently accepted mvpp2 ethernet driver.
>
> David: if we are still in time, we'd like to get the driver fixes merged
> for v3.17-rc1.
>
> For the devicetree changes, it's already too late for that, since Jason
> Cooper has already posted the PRs for v3.17. I'll re-post them when
> v3.17-rc1 is released.
>
> As usual, feedback is welcome.
>
> Ezequiel Garcia (3):
> net: mvpp2: Fix the BM pool buffer release check
> net: mvpp2: Simplify BM pool buffers freeing
> ARM: mvebu: Add missing MDIO clock in Armada 375
>
> Marcin Wojtas (3):
> net: mvpp2: Fix the periodic XON enable bit
> net: mvpp2: Enable proper PHY polling and fix port functionality
> ARM: mvebu: Add ethernet aliases required by U-Boot
>
> arch/arm/boot/dts/armada-375.dtsi | 3 ++
> drivers/net/ethernet/marvell/mvpp2.c | 65 +++++++++++++++++++++++-------------
> 2 files changed, 44 insertions(+), 24 deletions(-)
Patches 5 and 6 (dtsi changes) applied to mvebu/dt for v3.17
thx,
Jason.
^ permalink raw reply
* [PATCH v5 1/2] i2c: add DMA support for freescale i2c driver
From: Lothar Waßmann @ 2014-07-23 12:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b1778af62e7b42b39381fb2699b34eb1@BL2PR03MB338.namprd03.prod.outlook.com>
Hi,
Yao Yuan wrote:
> Hi,
>
> Thanks for your review.
>
> Lothar Wa?mann wrote:
> > Yuan Yao wrote:
> > > Add dma support for i2c. This function depend on DMA driver.
> > > You can turn on it by write both the dmas and dma-name properties in dts node.
> > >
> > > Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
> > > ---
> > > drivers/i2c/busses/i2c-imx.c | 377
> [...]
> > > +
> > > +fail_rx:
> > > + dma_release_channel(dma->chan_rx);
> > > +fail_tx:
> > > + dma_release_channel(dma->chan_tx);
> > > +fail_al:
> > > + devm_kfree(dev, dma);
> > >
> > No need for this one (that's the whole point of using devm_kzalloc())!
> >
>
> When DMA request failed, I2C will switch to PIO mode. So if the failed reason is just like DMA channel request failed. At this time the DMA should free by devm_kfree(). Is it?
>
OK. I didn't notice that failing DMA support wasn't a showstopper for
the whole driver.
In this case I would remove the 'failed' from the messages inside
i2c_imx_dma_request() to make them more benign looking and output them
with dev_dbg(), so they can be en-/disabled with CONFIG_I2C_DEBUG_BUS.
What about returning -EPROBE_DEFER in appropriate cases (when there is
a chance that the DMA driver will be probed later than the I2C driver)?
Lothar Wa?mann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________
^ permalink raw reply
* [PATCH 2/2] Adding lenovo in vendor
From: benoitm974 @ 2014-07-23 12:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406117232-5962-1-git-send-email-yahoo@perenite.com>
Signed-off-by: benoitm974 <yahoo@perenite.com>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 46a311e..de81a87 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -72,6 +72,7 @@ keymile Keymile GmbH
lacie LaCie
lantiq Lantiq Semiconductor
lg LG Corporation
+lenovo LENOVO
linux Linux-specific binding
lsi LSI Corp. (LSI Logic)
lltc Linear Technology Corporation
--
1.9.1
^ permalink raw reply related
* [PATCH 1/2] Added dts defintion for Lenovo ix4-300d nas
From: benoitm974 @ 2014-07-23 12:07 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: benoitm974 <yahoo@perenite.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts | 267 +++++++++++++++++++++++++
2 files changed, 268 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index adb5ed9..f759dd2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -438,6 +438,7 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \
armada-xp-db.dtb \
armada-xp-gp.dtb \
armada-xp-netgear-rn2120.dtb \
+ armada-xp-lenovo-ix4300d.dtb \
armada-xp-matrix.dtb \
armada-xp-openblocks-ax3-4.dtb
dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts
new file mode 100644
index 0000000..e04e7a6
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4300d.dts
@@ -0,0 +1,267 @@
+/*
+ * Device Tree file for LENOVO IX4-300d
+ *
+ * Copyright (C) 2014, Benoit Masson <yahoo@perenite.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78230.dtsi"
+
+/ {
+ model = "LENOVO IX4-300d";
+ compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x20000000>; /* 512MB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+ pcie-controller {
+ status = "okay";
+
+ pcie at 1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie at 5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+
+ };
+
+ internal-regs {
+ pinctrl {
+ poweroff: poweroff {
+ marvell,pins = "mpp24";
+ marvell,function = "gpio";
+ };
+
+ power_button_pin: power-button-pin {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+
+ reset_button_pin: reset-button-pin {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+ select_button_pin: select-button-pin {
+ marvell,pins = "mpp41";
+ marvell,function = "gpio";
+ };
+
+ scroll_button_pin: scroll-button-pin {
+ marvell,pins = "mpp42";
+ marvell,function = "gpio";
+ };
+ hdd_led_pin: hdd-led-pin {
+ marvell,pins = "mpp26";
+ marvell,function = "gpio";
+ };
+ };
+
+ serial at 12000 {
+ clocks = <&coreclk 0>;
+ status = "okay";
+ };
+
+ mdio {
+ phy0: ethernet-phy at 0 { /* Marvell 88E1318 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy at 1 { /* Marvell 88E1318 */
+ reg = <1>;
+ };
+ };
+
+ ethernet at 70000 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+
+ ethernet at 74000 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ };
+
+ usb at 50000 {
+ status = "okay";
+ };
+
+ usb at 51000 {
+ status = "okay";
+ };
+
+ i2c at 11000 {
+ compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
+ clock-frequency = <400000>;
+ status = "okay";
+
+ adt7473 at 2e {
+ compatible = "adt7473";
+ reg = <0x2e>;
+ };
+
+ pcf8563 at 51 {
+ compatible = "pcf8563";
+ reg = <0x51>;
+ };
+
+ };
+ nand at d0000 {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+
+ partition at 0 {
+ label = "u-boot";
+ reg = <0x0000000 0xe0000>;
+ read-only;
+ };
+
+ partition at e0000 {
+ label = "u-boot-env";
+ reg = <0xe0000 0x20000>;
+ read-only;
+ };
+
+ partition at 100000 {
+ label = "u-boot-env2";
+ reg = <0x100000 0x20000>;
+ read-only;
+ };
+
+ partition at 120000 {
+ label = "zImage";
+ reg = <0x120000 0x400000>;
+ };
+
+ partition at 520000 {
+ label = "initrd";
+ reg = <0x520000 0x400000>;
+ };
+ partition at xE00000 {
+ label = "boot";
+ reg = <0xE00000 0x3F200000>;
+ };
+ partition at flash {
+ label = "flash";
+ reg = <0x0 0x40000000>;
+ };
+ };
+
+ };
+ };
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&power_button_pin &reset_button_pin &select_button_pin &scroll_button_pin>;
+ pinctrl-names = "default";
+
+ power-button {
+ label = "Power Button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+ reset-button {
+ label = "Reset Button";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ };
+ select-button {
+ label = "Select Button";
+ linux,code = <BTN_SELECT>;
+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ };
+ scroll-button {
+ label = "Scroll Button";
+ linux,code = <KEY_SCROLLDOWN>;
+ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ spi3 {
+ compatible = "spi-gpio";
+ status = "okay";
+ gpio-sck = <&gpio0 25 0>;
+ gpio-mosi = <&gpio1 15 0>; /*gpio 47*/
+ cs-gpios = <&gpio0 27 0 >;
+ num-chipselects = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio2: gpio2 at 0 {
+ compatible = "fairchild,74hc595";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0>;
+ registers-number = <2>;
+ spi-max-frequency = <100000>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&hdd_led_pin>;
+ pinctrl-names = "default";
+
+ hdd-led {
+ label = "ix4300d:blue:hdd";
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ power-led {
+ label = "ix4300d:power";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer"; /* init blinking while booting */
+ default-state = "on";
+ };
+
+ sysfail-led {
+ label = "ix4300d:sysfail:red";
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ sys-led {
+ label = "ix4300d:sys:blue";
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ hddfail-led {
+ label = "ix4300d:hddfail:red";
+ gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ };
+ /* warning: you need both eth1 & 0 to be initialize for poweroff to shutdown otherwise it reboots */
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-0 = <&poweroff>;
+ pinctrl-names = "default";
+ gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ };
+
+};
--
1.9.1
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