* [GIT PULL] non-urgent omap fixes for v3.17 merge window
From: Tony Lindgren @ 2014-07-24 11:51 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit cd3de83f147601356395b57a8673e9c5ff1e59d1:
Linux 3.16-rc4 (2014-07-06 12:37:51 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.17/fixes-not-urgent-signed
for you to fetch changes up to 00e4e5b5b0339bde4b0ecb23d7d7969a3bebd44d:
Merge remote-tracking branch 'roger/for-v3.17/gpmc-omap' into omap-for-v3.17/fixes-not-urgent (2014-07-15 00:24:39 -0700)
----------------------------------------------------------------
Fixes for omaps that were not considered urgent enough for the
rc series. Mostly a fix for GPMC allocation and omap5 ABB
(Adaptive Body Bias).
----------------------------------------------------------------
Andrii.Tseglytskyi (1):
ARM: dts: OMAP5: Add device nodes for ABB
Nicholas Krause (1):
omap16xx: Removes fixme no longer needed in ocpi_enable()
Rickard Strandqvist (1):
ARM: omap2+: usb-tusb6010.c: Cleaning up variable is set more than once
Rostislav Lisovy (1):
ARM: omap2+: gpmc-nand: Use dynamic platform_device_alloc()
Tony Lindgren (1):
Merge remote-tracking branch 'roger/for-v3.17/gpmc-omap' into omap-for-v3.17/fixes-not-urgent
arch/arm/boot/dts/omap5.dtsi | 60 +++++++++++++++++++++++++++++
arch/arm/mach-omap1/ocpi.c | 1 -
arch/arm/mach-omap2/gpmc-nand.c | 79 ++++++++++++++++++--------------------
arch/arm/mach-omap2/usb-tusb6010.c | 1 -
4 files changed, 97 insertions(+), 44 deletions(-)
^ permalink raw reply
* [PATCH v2 6/6] net/macb: enable scatter-gather feature and set DMA burst length for sama5d4 gem
From: Cyrille Pitchen @ 2014-07-24 11:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1406192657.git.cyrille.pitchen@atmel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/net/ethernet/cadence/macb.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 6836f88..ca5d779 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -2005,6 +2005,11 @@ static struct macb_config sama5d3_config = {
.dma_burst_length = 16,
};
+static struct macb_config sama5d4_config = {
+ .caps = 0,
+ .dma_burst_length = 4,
+};
+
static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,at32ap7000-macb" },
{ .compatible = "cdns,at91sam9260-macb" },
@@ -2012,6 +2017,7 @@ static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
{ .compatible = "cdns,gem", .data = &pc302gem_config },
{ .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
+ { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, macb_dt_ids);
--
1.8.2.2
^ permalink raw reply related
* [PATCH v2 5/6] ARM: at91: change compatibility string for sama5d3x gem
From: Cyrille Pitchen @ 2014-07-24 11:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1406192657.git.cyrille.pitchen@atmel.com>
this new compatibility string prevents macb/gem driver from using the
scatter-gather and gso features on sama5d3x boards.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
arch/arm/boot/dts/sama5d3_gmac.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
index a6cb050..de5ed59 100644
--- a/arch/arm/boot/dts/sama5d3_gmac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -74,7 +74,7 @@
};
macb0: ethernet at f0028000 {
- compatible = "cdns,pc302-gem", "cdns,gem";
+ compatible = "atmel,sama5d3-gem";
reg = <0xf0028000 0x100>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
--
1.8.2.2
^ permalink raw reply related
* [PATCH v2 4/6] net/macb: add RX checksum offload feature
From: Cyrille Pitchen @ 2014-07-24 11:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1406192657.git.cyrille.pitchen@atmel.com>
When RX checksum offload is enabled at GEM level (bit 24 set in the Network
Control Register), frames with invalid IP, TCP or UDP checksums are
discarted even if promiscuous mode is enabled (bit 4 set in the Network Control
Register).
This was verified with a simple userspace program, which corrupts UDP checksum
using libnetfilter_queue.
Then both IFF_PROMISC bit must be clear in dev->flags and NETIF_F_RXCSUM bit
must be set in dev->features to enable RX checksum offload at GEM level. This
way tcpdump is still able to capture corrupted frames.
Also skb->ip_summed is set to CHECKSUM_UNNECESSARY only when both TCP/IP or
UDP/IP checksums were verified by the GEM. Indeed the GEM may verify only IP
checksum but not the one for ICMP (or other protocol than TCP or UDP).
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/net/ethernet/cadence/macb.c | 36 ++++++++++++++++++++++++++++++++----
drivers/net/ethernet/cadence/macb.h | 19 +++++++++++++++++++
2 files changed, 51 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index cc36269..6836f88 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -765,6 +765,10 @@ static int gem_rx(struct macb *bp, int budget)
skb->protocol = eth_type_trans(skb, bp->dev);
skb_checksum_none_assert(skb);
+ if (bp->dev->features & NETIF_F_RXCSUM &&
+ !(bp->dev->flags & IFF_PROMISC) &&
+ GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
bp->stats.rx_packets++;
bp->stats.rx_bytes += skb->len;
@@ -1549,6 +1553,8 @@ static void macb_init_hw(struct macb *bp)
config |= MACB_BIT(BIG); /* Receive oversized frames */
if (bp->dev->flags & IFF_PROMISC)
config |= MACB_BIT(CAF); /* Copy All Frames */
+ else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
+ config |= GEM_BIT(RXCOEN);
if (!(bp->dev->flags & IFF_BROADCAST))
config |= MACB_BIT(NBC); /* No BroadCast */
config |= macb_dbw(bp);
@@ -1662,13 +1668,22 @@ void macb_set_rx_mode(struct net_device *dev)
cfg = macb_readl(bp, NCFGR);
- if (dev->flags & IFF_PROMISC)
+ if (dev->flags & IFF_PROMISC) {
/* Enable promiscuous mode */
cfg |= MACB_BIT(CAF);
- else if (dev->flags & (~IFF_PROMISC))
- /* Disable promiscuous mode */
+
+ /* Disable RX checksum offload */
+ if (macb_is_gem(bp))
+ cfg &= ~GEM_BIT(RXCOEN);
+ } else {
+ /* Disable promiscuous mode */
cfg &= ~MACB_BIT(CAF);
+ /* Enable RX checksum offload only if requested */
+ if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
+ cfg |= GEM_BIT(RXCOEN);
+ }
+
if (dev->flags & IFF_ALLMULTI) {
/* Enable all multicast mode */
macb_or_gem_writel(bp, HRB, -1);
@@ -1947,6 +1962,19 @@ static int macb_set_features(struct net_device *netdev,
gem_writel(bp, DMACFG, dmacfg);
}
+ /* RX checksum offload */
+ if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
+ u32 netcfg;
+
+ netcfg = gem_readl(bp, NCFGR);
+ if (features & NETIF_F_RXCSUM &&
+ !(netdev->flags & IFF_PROMISC))
+ netcfg |= GEM_BIT(RXCOEN);
+ else
+ netcfg &= ~GEM_BIT(RXCOEN);
+ gem_writel(bp, NCFGR, netcfg);
+ }
+
return 0;
}
@@ -2150,7 +2178,7 @@ static int __init macb_probe(struct platform_device *pdev)
dev->hw_features = NETIF_F_SG;
/* Checksum offload is only available on gem with packet buffer */
if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
- dev->hw_features |= NETIF_F_HW_CSUM;
+ dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
if (bp->caps & MACB_CAPS_SG_DISABLED)
dev->hw_features &= ~NETIF_F_SG;
dev->features = dev->hw_features;
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 7bf8285..517c09d 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -164,6 +164,8 @@
#define GEM_CLK_SIZE 3
#define GEM_DBW_OFFSET 21
#define GEM_DBW_SIZE 2
+#define GEM_RXCOEN_OFFSET 24
+#define GEM_RXCOEN_SIZE 1
/* Constants for data bus width. */
#define GEM_DBW32 0
@@ -452,6 +454,14 @@ struct macb_dma_desc {
#define MACB_RX_BROADCAST_OFFSET 31
#define MACB_RX_BROADCAST_SIZE 1
+/* RX checksum offload disabled: bit 24 clear in NCFGR */
+#define GEM_RX_TYPEID_MATCH_OFFSET 22
+#define GEM_RX_TYPEID_MATCH_SIZE 2
+
+/* RX checksum offload enabled: bit 24 set in NCFGR */
+#define GEM_RX_CSUM_OFFSET 22
+#define GEM_RX_CSUM_SIZE 2
+
#define MACB_TX_FRMLEN_OFFSET 0
#define MACB_TX_FRMLEN_SIZE 11
#define MACB_TX_LAST_OFFSET 15
@@ -472,6 +482,15 @@ struct macb_dma_desc {
#define GEM_TX_FRMLEN_OFFSET 0
#define GEM_TX_FRMLEN_SIZE 14
+/* Buffer descriptor constants */
+#define GEM_RX_CSUM_NONE 0
+#define GEM_RX_CSUM_IP_ONLY 1
+#define GEM_RX_CSUM_IP_TCP 2
+#define GEM_RX_CSUM_IP_UDP 3
+
+/* limit RX checksum offload to TCP and UDP packets */
+#define GEM_RX_CSUM_CHECKED_MASK 2
+
/**
* struct macb_tx_skb - data about an skb which is being transmitted
* @skb: skb currently being transmitted, only set for the last buffer
--
1.8.2.2
^ permalink raw reply related
* [PATCH v2 3/6] net/macb: add TX checksum offload feature
From: Cyrille Pitchen @ 2014-07-24 11:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1406192657.git.cyrille.pitchen@atmel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/net/ethernet/cadence/macb.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 2e4bfe3..cc36269 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1525,6 +1525,10 @@ static void macb_configure_dma(struct macb *bp)
dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
dmacfg &= ~GEM_BIT(ENDIA);
+ if (bp->dev->features & NETIF_F_HW_CSUM)
+ dmacfg |= GEM_BIT(TXCOEN);
+ else
+ dmacfg &= ~GEM_BIT(TXCOEN);
netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
dmacfg);
gem_writel(bp, DMACFG, dmacfg);
@@ -1925,6 +1929,27 @@ int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
}
EXPORT_SYMBOL_GPL(macb_ioctl);
+static int macb_set_features(struct net_device *netdev,
+ netdev_features_t features)
+{
+ struct macb *bp = netdev_priv(netdev);
+ netdev_features_t changed = features ^ netdev->features;
+
+ /* TX checksum offload */
+ if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
+ u32 dmacfg;
+
+ dmacfg = gem_readl(bp, DMACFG);
+ if (features & NETIF_F_HW_CSUM)
+ dmacfg |= GEM_BIT(TXCOEN);
+ else
+ dmacfg &= ~GEM_BIT(TXCOEN);
+ gem_writel(bp, DMACFG, dmacfg);
+ }
+
+ return 0;
+}
+
static const struct net_device_ops macb_netdev_ops = {
.ndo_open = macb_open,
.ndo_stop = macb_close,
@@ -1938,6 +1963,7 @@ static const struct net_device_ops macb_netdev_ops = {
#ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = macb_poll_controller,
#endif
+ .ndo_set_features = macb_set_features,
};
#if defined(CONFIG_OF)
@@ -2122,6 +2148,9 @@ static int __init macb_probe(struct platform_device *pdev)
/* Set features */
dev->hw_features = NETIF_F_SG;
+ /* Checksum offload is only available on gem with packet buffer */
+ if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
+ dev->hw_features |= NETIF_F_HW_CSUM;
if (bp->caps & MACB_CAPS_SG_DISABLED)
dev->hw_features &= ~NETIF_F_SG;
dev->features = dev->hw_features;
--
1.8.2.2
^ permalink raw reply related
* [PATCH v2 2/6] net/macb: add scatter-gather hw feature
From: Cyrille Pitchen @ 2014-07-24 11:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1406192657.git.cyrille.pitchen@atmel.com>
The scatter-gather feature will allow to enable the Generic Segmentation Offload.
Generic Segmentation Offload can be enabled/disabled using ethtool -K DEVNAME gso on|off.
e.g:
ethtool -K eth0 gso off
When enabled, the driver may be provided with socket buffers splitted into many fragments.
These fragments need to be queued into the TX ring in reverse order, starting from to the
last one down to the first one, to avoid a race condition with the MAC.
Especially the 'TX_USED' bit in word 1 of the transmit buffer descriptor of the
first fragment should be cleared at the very final step of the queueing algorithm.
This will tell the hardware that fragments are ready to be sent.
Also since the MAC only update the status word of the first buffer descriptor of the
ethernet frame, the queueing algorithm can no longer expect a 'TX_USED' bit to be set by
the MAC into the buffer descriptor following the one for last fragment of the skb.
This is why the driver sets the 'TX_USED' bit before queueing any fragment, so the end of
queue position is well defined for the MAC.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/net/ethernet/cadence/macb.c | 277 +++++++++++++++++++++++++++++-------
drivers/net/ethernet/cadence/macb.h | 15 +-
2 files changed, 240 insertions(+), 52 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 91870e9..2e4bfe3 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -52,6 +52,9 @@
| MACB_BIT(TXERR))
#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
+#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
+#define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
+
/*
* Graceful stop timeouts in us. We should allow up to
* 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
@@ -468,6 +471,24 @@ static int macb_halt_tx(struct macb *bp)
return -ETIMEDOUT;
}
+static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
+{
+ if (tx_skb->mapping) {
+ if (tx_skb->mapped_as_page)
+ dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
+ tx_skb->size, DMA_TO_DEVICE);
+ else
+ dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
+ tx_skb->size, DMA_TO_DEVICE);
+ tx_skb->mapping = 0;
+ }
+
+ if (tx_skb->skb) {
+ dev_kfree_skb_any(tx_skb->skb);
+ tx_skb->skb = NULL;
+ }
+}
+
static void macb_tx_error_task(struct work_struct *work)
{
struct macb *bp = container_of(work, struct macb, tx_error_task);
@@ -505,10 +526,23 @@ static void macb_tx_error_task(struct work_struct *work)
skb = tx_skb->skb;
if (ctrl & MACB_BIT(TX_USED)) {
- netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
- macb_tx_ring_wrap(tail), skb->data);
- bp->stats.tx_packets++;
- bp->stats.tx_bytes += skb->len;
+ /* skb is set for the last buffer of the frame */
+ while (!skb) {
+ macb_tx_unmap(bp, tx_skb);
+ tail++;
+ tx_skb = macb_tx_skb(bp, tail);
+ skb = tx_skb->skb;
+ }
+
+ /* ctrl still refers to the first buffer descriptor
+ * since it's the only one written back by the hardware
+ */
+ if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
+ netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
+ macb_tx_ring_wrap(tail), skb->data);
+ bp->stats.tx_packets++;
+ bp->stats.tx_bytes += skb->len;
+ }
} else {
/*
* "Buffers exhausted mid-frame" errors may only happen
@@ -522,10 +556,7 @@ static void macb_tx_error_task(struct work_struct *work)
desc->ctrl = ctrl | MACB_BIT(TX_USED);
}
- dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
- DMA_TO_DEVICE);
- tx_skb->skb = NULL;
- dev_kfree_skb(skb);
+ macb_tx_unmap(bp, tx_skb);
}
/* Make descriptor updates visible to hardware */
@@ -573,20 +604,35 @@ static void macb_tx_interrupt(struct macb *bp)
ctrl = desc->ctrl;
+ /* TX_USED bit is only set by hardware on the very first buffer
+ * descriptor of the transmitted frame.
+ */
if (!(ctrl & MACB_BIT(TX_USED)))
break;
- tx_skb = macb_tx_skb(bp, tail);
- skb = tx_skb->skb;
+ /* Process all buffers of the current transmitted frame */
+ for (;; tail++) {
+ tx_skb = macb_tx_skb(bp, tail);
+ skb = tx_skb->skb;
+
+ /* First, update TX stats if needed */
+ if (skb) {
+ netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
+ macb_tx_ring_wrap(tail), skb->data);
+ bp->stats.tx_packets++;
+ bp->stats.tx_bytes += skb->len;
+ }
- netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
- macb_tx_ring_wrap(tail), skb->data);
- dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
- DMA_TO_DEVICE);
- bp->stats.tx_packets++;
- bp->stats.tx_bytes += skb->len;
- tx_skb->skb = NULL;
- dev_kfree_skb_irq(skb);
+ /* Now we can safely release resources */
+ macb_tx_unmap(bp, tx_skb);
+
+ /* skb is set only for the last buffer of the frame.
+ * WARNING: at this point skb has been freed by
+ * macb_tx_unmap().
+ */
+ if (skb)
+ break;
+ }
}
bp->tx_tail = tail;
@@ -1002,15 +1048,145 @@ static void macb_poll_controller(struct net_device *dev)
}
#endif
-static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
+static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
+ unsigned int len)
+{
+ return (len + bp->max_tx_length - 1) / bp->max_tx_length;
+}
+
+static unsigned int macb_tx_map(struct macb *bp,
+ struct sk_buff *skb)
{
- struct macb *bp = netdev_priv(dev);
dma_addr_t mapping;
- unsigned int len, entry;
+ unsigned int len, entry, i, tx_head = bp->tx_head;
+ struct macb_tx_skb *tx_skb = NULL;
struct macb_dma_desc *desc;
- struct macb_tx_skb *tx_skb;
+ unsigned int offset, size, count = 0;
+ unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
+ unsigned int eof = 1;
u32 ctrl;
+
+ /* First, map non-paged data */
+ len = skb_headlen(skb);
+ offset = 0;
+ while (len) {
+ size = min(len, bp->max_tx_length);
+ entry = macb_tx_ring_wrap(tx_head);
+ tx_skb = &bp->tx_skb[entry];
+
+ mapping = dma_map_single(&bp->pdev->dev,
+ skb->data + offset,
+ size, DMA_TO_DEVICE);
+ if (dma_mapping_error(&bp->pdev->dev, mapping))
+ goto dma_error;
+
+ /* Save info to properly release resources */
+ tx_skb->skb = NULL;
+ tx_skb->mapping = mapping;
+ tx_skb->size = size;
+ tx_skb->mapped_as_page = false;
+
+ len -= size;
+ offset += size;
+ count++;
+ tx_head++;
+ }
+
+ /* Then, map paged data from fragments */
+ for (f = 0; f < nr_frags; f++) {
+ const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
+
+ len = skb_frag_size(frag);
+ offset = 0;
+ while (len) {
+ size = min(len, bp->max_tx_length);
+ entry = macb_tx_ring_wrap(tx_head);
+ tx_skb = &bp->tx_skb[entry];
+
+ mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
+ offset, size, DMA_TO_DEVICE);
+ if (dma_mapping_error(&bp->pdev->dev, mapping))
+ goto dma_error;
+
+ /* Save info to properly release resources */
+ tx_skb->skb = NULL;
+ tx_skb->mapping = mapping;
+ tx_skb->size = size;
+ tx_skb->mapped_as_page = true;
+
+ len -= size;
+ offset += size;
+ count++;
+ tx_head++;
+ }
+ }
+
+ /* Should never happen */
+ if (unlikely(tx_skb == NULL)) {
+ netdev_err(bp->dev, "BUG! empty skb!\n");
+ return 0;
+ }
+
+ /* This is the last buffer of the frame: save socket buffer */
+ tx_skb->skb = skb;
+
+ /* Update TX ring: update buffer descriptors in reverse order
+ * to avoid race condition
+ */
+
+ /* Set 'TX_USED' bit in buffer descriptor at tx_head position
+ * to set the end of TX queue
+ */
+ i = tx_head;
+ entry = macb_tx_ring_wrap(i);
+ ctrl = MACB_BIT(TX_USED);
+ desc = &bp->tx_ring[entry];
+ desc->ctrl = ctrl;
+
+ do {
+ i--;
+ entry = macb_tx_ring_wrap(i);
+ tx_skb = &bp->tx_skb[entry];
+ desc = &bp->tx_ring[entry];
+
+ ctrl = (u32)tx_skb->size;
+ if (eof) {
+ ctrl |= MACB_BIT(TX_LAST);
+ eof = 0;
+ }
+ if (unlikely(entry == (TX_RING_SIZE - 1)))
+ ctrl |= MACB_BIT(TX_WRAP);
+
+ /* Set TX buffer descriptor */
+ desc->addr = tx_skb->mapping;
+ /* desc->addr must be visible to hardware before clearing
+ * 'TX_USED' bit in desc->ctrl.
+ */
+ wmb();
+ desc->ctrl = ctrl;
+ } while (i != bp->tx_head);
+
+ bp->tx_head = tx_head;
+
+ return count;
+
+dma_error:
+ netdev_err(bp->dev, "TX DMA map failed\n");
+
+ for (i = bp->tx_head; i != tx_head; i++) {
+ tx_skb = macb_tx_skb(bp, i);
+
+ macb_tx_unmap(bp, tx_skb);
+ }
+
+ return 0;
+}
+
+static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct macb *bp = netdev_priv(dev);
unsigned long flags;
+ unsigned int count, nr_frags, frag_size, f;
#if defined(DEBUG) && defined(VERBOSE_DEBUG)
netdev_vdbg(bp->dev,
@@ -1021,44 +1197,34 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
skb->data, 16, true);
#endif
- len = skb->len;
+ /* Count how many TX buffer descriptors are needed to send this
+ * socket buffer: skb fragments of jumbo frames may need to be
+ * splitted into many buffer descriptors.
+ */
+ count = macb_count_tx_descriptors(bp, skb_headlen(skb));
+ nr_frags = skb_shinfo(skb)->nr_frags;
+ for (f = 0; f < nr_frags; f++) {
+ frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
+ count += macb_count_tx_descriptors(bp, frag_size);
+ }
+
spin_lock_irqsave(&bp->lock, flags);
/* This is a hard error, log it. */
- if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
+ if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < count) {
netif_stop_queue(dev);
spin_unlock_irqrestore(&bp->lock, flags);
- netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
bp->tx_head, bp->tx_tail);
return NETDEV_TX_BUSY;
}
- entry = macb_tx_ring_wrap(bp->tx_head);
- netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
- mapping = dma_map_single(&bp->pdev->dev, skb->data,
- len, DMA_TO_DEVICE);
- if (dma_mapping_error(&bp->pdev->dev, mapping)) {
+ /* Map socket buffer for DMA transfer */
+ if (!macb_tx_map(bp, skb)) {
dev_kfree_skb_any(skb);
goto unlock;
}
- bp->tx_head++;
- tx_skb = &bp->tx_skb[entry];
- tx_skb->skb = skb;
- tx_skb->mapping = mapping;
- netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
- skb->data, (unsigned long)mapping);
-
- ctrl = MACB_BF(TX_FRMLEN, len);
- ctrl |= MACB_BIT(TX_LAST);
- if (entry == (TX_RING_SIZE - 1))
- ctrl |= MACB_BIT(TX_WRAP);
-
- desc = &bp->tx_ring[entry];
- desc->addr = mapping;
- desc->ctrl = ctrl;
-
/* Make newly initialized descriptor visible to hardware */
wmb();
@@ -1776,7 +1942,12 @@ static const struct net_device_ops macb_netdev_ops = {
#if defined(CONFIG_OF)
static struct macb_config pc302gem_config = {
- .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE,
+ .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
+ .dma_burst_length = 16,
+};
+
+static struct macb_config sama5d3_config = {
+ .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
.dma_burst_length = 16,
};
@@ -1786,6 +1957,7 @@ static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,macb" },
{ .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
{ .compatible = "cdns,gem", .data = &pc302gem_config },
+ { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, macb_dt_ids);
@@ -1864,9 +2036,6 @@ static int __init macb_probe(struct platform_device *pdev)
SET_NETDEV_DEV(dev, &pdev->dev);
- /* TODO: Actually, we have some interesting features... */
- dev->features |= 0;
-
bp = netdev_priv(dev);
bp->pdev = pdev;
bp->dev = dev;
@@ -1938,17 +2107,25 @@ static int __init macb_probe(struct platform_device *pdev)
/* setup appropriated routines according to adapter type */
if (macb_is_gem(bp)) {
+ bp->max_tx_length = GEM_MAX_TX_LEN;
bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
bp->macbgem_ops.mog_init_rings = gem_init_rings;
bp->macbgem_ops.mog_rx = gem_rx;
} else {
+ bp->max_tx_length = MACB_MAX_TX_LEN;
bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
bp->macbgem_ops.mog_init_rings = macb_init_rings;
bp->macbgem_ops.mog_rx = macb_rx;
}
+ /* Set features */
+ dev->hw_features = NETIF_F_SG;
+ if (bp->caps & MACB_CAPS_SG_DISABLED)
+ dev->hw_features &= ~NETIF_F_SG;
+ dev->features = dev->hw_features;
+
/* Set MII management clock divider */
config = macb_mdc_clk_div(bp);
config |= macb_dbw(bp);
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 7ce751b..7bf8285 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -335,6 +335,7 @@
#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
#define MACB_CAPS_FIFO_MODE 0x10000000
#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
+#define MACB_CAPS_SG_DISABLED 0x40000000
#define MACB_CAPS_MACB_IS_GEM 0x80000000
/* Bit manipulation macros */
@@ -468,14 +469,23 @@ struct macb_dma_desc {
#define MACB_TX_USED_OFFSET 31
#define MACB_TX_USED_SIZE 1
+#define GEM_TX_FRMLEN_OFFSET 0
+#define GEM_TX_FRMLEN_SIZE 14
+
/**
* struct macb_tx_skb - data about an skb which is being transmitted
- * @skb: skb currently being transmitted
- * @mapping: DMA address of the skb's data buffer
+ * @skb: skb currently being transmitted, only set for the last buffer
+ * of the frame
+ * @mapping: DMA address of the skb's fragment buffer
+ * @size: size of the DMA mapped buffer
+ * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
+ * false when buffer was mapped with dma_map_single()
*/
struct macb_tx_skb {
struct sk_buff *skb;
dma_addr_t mapping;
+ size_t size;
+ bool mapped_as_page;
};
/*
@@ -617,6 +627,7 @@ struct macb {
struct sk_buff *skb; /* holds skb until xmit interrupt completes */
dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
int skb_length; /* saved skb length for pci_unmap_single */
+ unsigned int max_tx_length;
};
extern const struct ethtool_ops macb_ethtool_ops;
--
1.8.2.2
^ permalink raw reply related
* [PATCH v2 1/6] net/macb: configure for FIFO mode and non-gigabit
From: Cyrille Pitchen @ 2014-07-24 11:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1406192657.git.cyrille.pitchen@atmel.com>
From: Nicolas Ferre <nicolas.ferre@atmel.com>
This addition will also allow to configure DMA burst length.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
drivers/net/ethernet/cadence/macb.c | 75 ++++++++++++++++++++++++++++---------
drivers/net/ethernet/cadence/macb.h | 19 +++++++++-
2 files changed, 74 insertions(+), 20 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index e9daa07..91870e9 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -264,7 +264,8 @@ static void macb_handle_link_change(struct net_device *dev)
reg |= MACB_BIT(FD);
if (phydev->speed == SPEED_100)
reg |= MACB_BIT(SPD);
- if (phydev->speed == SPEED_1000)
+ if (phydev->speed == SPEED_1000 &&
+ bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
reg |= GEM_BIT(GBE);
macb_or_gem_writel(bp, NCFGR, reg);
@@ -337,7 +338,7 @@ static int macb_mii_probe(struct net_device *dev)
}
/* mask with MAC supported features */
- if (macb_is_gem(bp))
+ if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
phydev->supported &= PHY_GBIT_FEATURES;
else
phydev->supported &= PHY_BASIC_FEATURES;
@@ -1342,7 +1343,7 @@ static u32 macb_dbw(struct macb *bp)
/*
* Configure the receive DMA engine
* - use the correct receive buffer size
- * - set the possibility to use INCR16 bursts
+ * - set best burst length for DMA operations
* (if not supported by FIFO, it will fallback to default)
* - set both rx/tx packet buffers to full memory size
* These are configurable parameters for GEM.
@@ -1354,24 +1355,16 @@ static void macb_configure_dma(struct macb *bp)
if (macb_is_gem(bp)) {
dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
- dmacfg |= GEM_BF(FBLDO, 16);
+ if (bp->dma_burst_length)
+ dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
dmacfg &= ~GEM_BIT(ENDIA);
+ netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
+ dmacfg);
gem_writel(bp, DMACFG, dmacfg);
}
}
-/*
- * Configure peripheral capacities according to integration options used
- */
-static void macb_configure_caps(struct macb *bp)
-{
- if (macb_is_gem(bp)) {
- if (GEM_BFEXT(IRQCOR, gem_readl(bp, DCFG1)) == 0)
- bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
- }
-}
-
static void macb_init_hw(struct macb *bp)
{
u32 config;
@@ -1394,7 +1387,6 @@ static void macb_init_hw(struct macb *bp)
bp->duplex = DUPLEX_HALF;
macb_configure_dma(bp);
- macb_configure_caps(bp);
/* Initialize TX and RX buffers */
macb_writel(bp, RBQP, bp->rx_ring_dma);
@@ -1783,17 +1775,61 @@ static const struct net_device_ops macb_netdev_ops = {
};
#if defined(CONFIG_OF)
+static struct macb_config pc302gem_config = {
+ .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE,
+ .dma_burst_length = 16,
+};
+
static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,at32ap7000-macb" },
{ .compatible = "cdns,at91sam9260-macb" },
{ .compatible = "cdns,macb" },
- { .compatible = "cdns,pc302-gem" },
- { .compatible = "cdns,gem" },
+ { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
+ { .compatible = "cdns,gem", .data = &pc302gem_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, macb_dt_ids);
#endif
+/*
+ * Configure peripheral capacities according to device tree
+ * and integration options used
+ */
+static void macb_configure_caps(struct macb *bp)
+{
+ u32 dcfg;
+ const struct of_device_id *match;
+ const struct macb_config *config;
+
+ if (bp->pdev->dev.of_node) {
+ match = of_match_node(macb_dt_ids, bp->pdev->dev.of_node);
+ if (match && match->data) {
+ config = (const struct macb_config *)match->data;
+
+ bp->caps = config->caps;
+ /*
+ * As we have access to the matching node, configure
+ * DMA burst length as well
+ */
+ bp->dma_burst_length = config->dma_burst_length;
+ }
+ }
+
+ if (MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2)
+ bp->caps |= MACB_CAPS_MACB_IS_GEM;
+
+ if (macb_is_gem(bp)) {
+ dcfg = gem_readl(bp, DCFG1);
+ if (GEM_BFEXT(IRQCOR, dcfg) == 0)
+ bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
+ dcfg = gem_readl(bp, DCFG2);
+ if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
+ bp->caps |= MACB_CAPS_FIFO_MODE;
+ }
+
+ netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
+}
+
static int __init macb_probe(struct platform_device *pdev)
{
struct macb_platform_data *pdata;
@@ -1897,6 +1933,9 @@ static int __init macb_probe(struct platform_device *pdev)
dev->base_addr = regs->start;
+ /* setup capacities */
+ macb_configure_caps(bp);
+
/* setup appropriated routines according to adapter type */
if (macb_is_gem(bp)) {
bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 51c0244..7ce751b 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -305,6 +305,12 @@
#define GEM_DBWDEF_OFFSET 25
#define GEM_DBWDEF_SIZE 3
+/* Bitfields in DCFG2. */
+#define GEM_RX_PKT_BUFF_OFFSET 20
+#define GEM_RX_PKT_BUFF_SIZE 1
+#define GEM_TX_PKT_BUFF_OFFSET 21
+#define GEM_TX_PKT_BUFF_SIZE 1
+
/* Constants for CLK */
#define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1
@@ -326,7 +332,10 @@
#define MACB_MAN_CODE 2
/* Capability mask bits */
-#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x1
+#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
+#define MACB_CAPS_FIFO_MODE 0x10000000
+#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
+#define MACB_CAPS_MACB_IS_GEM 0x80000000
/* Bit manipulation macros */
#define MACB_BIT(name) \
@@ -554,6 +563,11 @@ struct macb_or_gem_ops {
int (*mog_rx)(struct macb *bp, int budget);
};
+struct macb_config {
+ u32 caps;
+ unsigned int dma_burst_length;
+};
+
struct macb {
void __iomem *regs;
@@ -595,6 +609,7 @@ struct macb {
unsigned int duplex;
u32 caps;
+ unsigned int dma_burst_length;
phy_interface_t phy_interface;
@@ -615,7 +630,7 @@ void macb_get_hwaddr(struct macb *bp);
static inline bool macb_is_gem(struct macb *bp)
{
- return MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2;
+ return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
}
#endif /* _MACB_H */
--
1.8.2.2
^ permalink raw reply related
* [PATCH v2 0/6] net/macb: add HW features to macb driver
From: Cyrille Pitchen @ 2014-07-24 11:50 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
this series of patches adds new hardware features to macb driver. These
features can be enabled/disabled at runtime using ethtool. Depending on
hardware and design configuration, some are enabled by default whereas other
are disabled.
For instance, checksum offload features are enabled by default for gem designed
for packet buffer mode but disabled for fifo mode design or for old macb.
Besides, the scatter-gather feature is enabled and tested on macb but disabled
on sama5d3x gem. When testing this feature on sama5d3x gem, TX lockups occured
frequently.
Also, the RX checksum offload feature is enabled at GEM level only when both
IFF_PROMISC bit is clear in dev->flags and NETIF_F_RXCSUM bit is set in
dev->features.
These patches were made for net-next.git repository.
Cyrille Pitchen (5):
net/macb: add scatter-gather hw feature
net/macb: add TX checksum offload feature
net/macb: add RX checksum offload feature
ARM: at91: change compatibility string for sama5d3x gem
net/macb: enable scatter-gather feature and set DMA burst length for
sama5d4 gem
Nicolas Ferre (1):
net/macb: configure for FIFO mode and non-gigabit
arch/arm/boot/dts/sama5d3_gmac.dtsi | 2 +-
drivers/net/ethernet/cadence/macb.c | 419 ++++++++++++++++++++++++++++++------
drivers/net/ethernet/cadence/macb.h | 53 ++++-
3 files changed, 399 insertions(+), 75 deletions(-)
--
1.8.2.2
^ permalink raw reply
* Kexec on arm64
From: Arun Chandran @ 2014-07-24 11:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406162287.4062.39.camel@smoke>
Hi,
On Thu, Jul 24, 2014 at 6:08 AM, Geoff Levand <geoff@infradead.org> wrote:
> Hi Arun,
>
> On Tue, 2014-07-22 at 18:55 +0530, Arun Chandran wrote:
>
>> I tried the same dtb with UP configuration. For UP kernel to compile
>> did the below modifications
>
> I'll test and fixup the kexec UP build in the next few days.
>
Ok.
> ...
>
>> With the default target configuration "kexec -e" failed to execute
>> in UP scenario also.
>>
>> But I had some luck when I did the same steps with L3 cache
>> disabled. According to http://www.spinics.net/lists/arm-kernel/msg329541.html
>> it has an L3 cache. Luckily I was able to disable it in u-boot.
>>
>> With the L3 cache disabled configuration I am able to
>> do "kexec -e". Please see the log attached.
>
> All memory management for the main cpu is done by the arch code. Kexec
> and cpu hot plug only work with the secondary cpus, so the problem would
> be in the arch memory code, either in setup_restart() for shutdown, or
> in the startup code.
>
> I guess setup_restart() is not doing something it needs to do for your
> platform.
>
I have done different experiments with L3 enabled in UP(uni processor) scenario.
Please note that in all the experiments first stage and second stage kernels
are same.
-- Experiment 1--
Kernel is modified to loop before jumping to the kexec "relocate_new_kernel"
code + other modification (disable Dcache turning off)
###############
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 3f7b0a2..e4ea22f 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -73,6 +73,8 @@ ENTRY(cpu_reset)
bic x1, x1, #1
msr sctlr_el1, x1 // disable the MMU
isb
+loop:
+ b loop
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 31cba91..888fe3f 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -70,10 +70,10 @@ static void setup_restart(void)
flush_cache_all();
/* Turn D-cache off */
- cpu_cache_off();
+ //cpu_cache_off();
/* Push out any further dirty data, and ensure cache is empty */
- flush_cache_all();
+ //flush_cache_all();
}
################
a) Load the second kernel "kexec -l"
b) Execute kexec -e; now it is looping @loop
c) Break into target using BDI3000
d) Flush L3 cache from BDI3000
c) Jump to relocate_new_kernel
CPU#0>rd
GPR00: 00000043eae0f000 0000000034d5d91c 0000004000000000 0000000000000004
CPU#0>go 0x00000043eae0f000
e) Kexeced kernel is booted without any issue.
--Experiment2--
Now revert only the Dcache disabling change
############
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 888fe3f..6bc85f78 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -70,10 +70,10 @@ static void setup_restart(void)
flush_cache_all();
/* Turn D-cache off */
- //cpu_cache_off();
+ cpu_cache_off();
/* Push out any further dirty data, and ensure cache is empty */
- //flush_cache_all();
+ flush_cache_all();
}
###############
Do the above steps a, b and c.
d)
>From BDI3000 I see strange value for x0
CPU#0>rd
GPR00: 000000000000003f 0000000034d5d918 0000004000000000 0000000000000004
e) Flush L3 cache from BDI3000
f) Jump to relocate_new_kernel (kexec -e prints this address)
machine_kexec:584: reboot_code_buffer_phys: 00000043f0381000
CPU#0>go 0x00000043f0381000
g) Kexeced kernel fails to boot
CPU#0>h
Core number : 0
Core state : debug (AArch64 EL1)
Debug entry cause : External Debug Request
Current PC : 0xffffffc000083200
Current CPSR : 0x000003c5 (EL1h)
So If i don't turn off the dcache and flush L3 using
BDI3000 things are working.
--Experiment3--
Added L3 flush code to kernel + other modification (disable Dcache turning off)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 0faa45a..5c546bb 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -233,6 +233,20 @@ section_table:
ENTRY(stext)
mov x21, x0 // x21=FDT
+flush_l3:
+ mov x2, #0x10
+ mov w1, #0x1f00
+ movk x2, #0x7e60, lsl #16
+ movk w1, #0x1600, lsl #16
+ str w1, [x2]
+ mov x4, #0
+wait_flush:
+ ldr w1, [x2]
+ add x4, x4 ,#1
+ tbz w1, #31, wait_done
+ b wait_flush
+wait_done:
+
bl el2_setup // Drop to EL1,
w20=cpu_boot_mode
bl __calc_phys_offset // x24=PHYS_OFFSET,
x28=PHYS_OFFSET-PAGE_OFFSET
bl set_cpu_boot_mode_flag
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 31cba91..888fe3f 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -70,10 +70,10 @@ static void setup_restart(void)
flush_cache_all();
/* Turn D-cache off */
- cpu_cache_off();
+ //cpu_cache_off();
/* Push out any further dirty data, and ensure cache is empty */
- flush_cache_all();
+ //flush_cache_all();
}
/*
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index c29dde1..3f7b0a2 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -73,7 +73,22 @@ ENTRY(cpu_reset)
bic x1, x1, #1
msr sctlr_el1, x1 // disable the MMU
isb
- bl secondary_shutdown
+
+flush_l3:
+ mov x2, #0x10
+ mov w1, #0x1f00
+ movk x2, #0x7e60, lsl #16
+ movk w1, #0x1600, lsl #16
+ str w1, [x2]
+ mov x4, #0
+wait_flush:
+ ldr w1, [x2]
+ add x4, x4 ,#1
+ tbz w1, #31, wait_done
+ b wait_flush
+wait_done:
+
+# bl secondary_shutdown
ret x0
ENDPROC(cpu_reset)
Now also kexeced kernel boots fine.
If i do the same with "Dcache turning off enabled"
booting of kexeced kernel fails.
--Arun
^ permalink raw reply related
* [PATCH 1/2] pinctrl: sunxi: use gpiolib API to mark a GPIO used as an IRQ
From: Maxime Ripard @ 2014-07-24 11:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1405358677-23657-2-git-send-email-wens@csie.org>
Hi Chen-Yu,
Sorry for the belated reply.
On Tue, Jul 15, 2014 at 01:24:36AM +0800, Chen-Yu Tsai wrote:
> When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
> the gpiolib so we can keep track of the usage centrally.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
It looks fine:
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply
* [GIT PULL] Few regression fixes for omaps for v3.16-rc series
From: Tony Lindgren @ 2014-07-24 11:43 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 1d29a0722f6c38f79785c9ffb911730598de84e2:
ARM: OMAP2+: Remove non working OMAP HDMI audio initialization (2014-07-08 01:08:44 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.16/fixes-rc6
for you to fetch changes up to 33753cd2ba41c72a0756edc5dc094d91602deda5:
ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable() (2014-07-23 01:48:24 -0700)
----------------------------------------------------------------
Two regression fixes for omaps and one fix for device signaling:
- L2 cache regression fix for a warning about trying to access
a read-only register
- GPMC ECC software fallback regression fix for omap3
- Fix for dra7 pinctrl pull-up direction that causes signal issues
for anybody trying to use the internal pull up or down
----------------------------------------------------------------
Christoph Fritz (1):
ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable()
Nishanth Menon (1):
pinctrl: dra: dt-bindings: Fix pull enable/disable
Sekhar Nori (1):
ARM: OMAP2+: l2c: squelch warning dump on power control setting
arch/arm/mach-omap2/gpmc-nand.c | 18 ++++++++++--------
arch/arm/mach-omap2/omap4-common.c | 4 ++++
include/dt-bindings/pinctrl/dra.h | 7 ++++---
3 files changed, 18 insertions(+), 11 deletions(-)
^ permalink raw reply
* [PATCH] spi/pxa2xx-pci: Enable DMA binding through device name
From: Arnd Bergmann @ 2014-07-24 11:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406196111-22861-1-git-send-email-hock.leong.kweh@intel.com>
On Thursday 24 July 2014 18:01:51 Kweh Hock Leong wrote:
> From: "Chew, Chiau Ee" <chiau.ee.chew@intel.com>
>
> Intel LPSS Baytrail supports two DMA controllers and SPI is only
> using one of the DMA controller. During DMA channel request,
> we need to ensure the requested Tx and Rx channels are from the correct
> DMA controller. Thus, we add extra checking in filter callback funtion
> by matching against the DMA controller device name.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
> Signed-off-by: Kweh, Hock Leong <hock.leong.kweh@intel.com>
I'm confused. Doesn't Bay Trail use ACPI to do the DMA
engine configuration? That should set find the right device/chan_id/slave_id
combination without any interaction, through the use of dma_request_slave_channel.
On a related note, there seems to be a bug in this driver, which
attempts to set the slave_id through dmaengine_slave_config(), which
is wrong in both cases, ACPI and filter functions.
Arnd
^ permalink raw reply
* [PATCH 00/14] arm64: eBPF JIT compiler
From: Will Deacon @ 2014-07-24 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CABg9mcvU44W5AkPLtyswNWdDdF_nnqvLyKqv7RWhpuRRSWDW3A@mail.gmail.com>
On Thu, Jul 24, 2014 at 05:55:36AM +0100, Z Lim wrote:
> On Wed, Jul 23, 2014 at 3:32 AM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
> > On Mon, Jul 21, 2014 at 04:49:29PM +0100, Alexei Starovoitov wrote:
> >> On Mon, Jul 21, 2014 at 2:16 AM, Will Deacon <will.deacon@arm.com> wrote:
> >> > On Fri, Jul 18, 2014 at 07:28:06PM +0100, Zi Shen Lim wrote:
> [...]
> >> >> This series applies against net-next and is tested working
> >> >> with lib/test_bpf on ARMv8 Foundation Model.
> >> >
> >> > Looks like it works on my Juno board too, so:
> >> >
> >> > Acked-by: Will Deacon <will.deacon@arm.com>
> >> >
> >> > for the series.
> >> >
> >> > It's a bit late for 3.17 now, so I guess we'll queue this for 3.18 (which
> >> > also means the dependency on -next isn't an issue). Perhaps you could repost
> >> > around -rc3?
> >>
> >> Thanks for testing! Nice to see it working on real hw.
> >> I'm not sure why you're proposing a 4+ week delay. The patches
> >> will rot instead of getting used and tested. Imo it makes sense to
> >> get them into net-next now for 3.17.
> >> JIT is disabled by sysctl by default anyway.
> >
> > We normally like some patches (especially new functionality) to sit in
> > linux-next for a while before the mering window (ideally starting with
> > -rc4 or -rc5). We are at -rc6 already, so getting close to the 3.17
> > merging window.
> >
> > Another aspect is that the arm64/bpf branch depends on the net tree, so
> > it can't easily go in via the arm64 tree for 3.17 (3.18 would not be a
> > problem).
>
> Hi Catalin, I take it you prefer this series going through arm64 tree,
> targeting 3.18, is that right?
Right.
> I understand your preference to have it sitting in linux-next for a
> longer period for arm64 material, I'll repost this again after 3.17 so
> it gets more exposure in linux-next.
Brill, thanks!
> BTW, are you open to this series going through net tree? I'm
> (preemptively) asking because during development of this series, I've
> had to rebase a couple times against net-next to handle dependencies.
> Or is the general practice to handle conflicts in linux-next itself?
We don't have a problem with it going via the -net tree if there's a reason
for doing so (i.e. a new dependency that crops up after your rebase) but we
should stick with the arm64 tree if we can.
Cheers,
Will
^ permalink raw reply
* [PATCH v2 1/3] usb: host: st-hcd: Add USB HCD support for STi SoCs
From: Lee Jones @ 2014-07-24 11:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406199616-10533-2-git-send-email-peter.griffin@linaro.org>
On Thu, 24 Jul 2014, Peter Griffin wrote:
> This driver adds support for the USB HCD present in STi
> SoC's from STMicroelectronics. It has been tested on the
> stih416-b2020 board.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/usb/host/Kconfig | 12 ++
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/st-hcd.c | 460 ++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 473 insertions(+)
> create mode 100644 drivers/usb/host/st-hcd.c
Looks good to me now:
Acked-by: Lee Jones <lee.jones@linaro.org>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 00/14] clk: sunxi: Improve MMC clocks support
From: Maxime Ripard @ 2014-07-24 11:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <53CA4CCA.5040303@redhat.com>
Hi Hans,
On Sat, Jul 19, 2014 at 12:47:38PM +0200, Hans de Goede wrote:
> Hi,
>
> On 07/17/2014 11:08 AM, Maxime Ripard wrote:
> >Hi everyone,
> >
> >Here is an attempt at improving the MMC clock support in the Allwinner
> >SoCs.
> >
> >Until now, the MMC clocks were having a custom phase function that was
> >directly setting an obscure value in the right register, because we
> >were not really having any idea of what these values were.
> >
> >Now that we have more informations, we can introduce a common function
> >call to get and set the phase of a particular clock, and use this in
> >both our provider and our client.
> >
> >Another issue we had so far on the A13 was that, out of reset, the
> >PLL6 driving the MMC was running too high to be working. We can solve
> >that by adding two new properties in the DT to setup the rate
> >constraints we might have on a clock.
>
> Looks good to me, thanks for working on this.
>
> Question have you dumped the raw mmc0 clk reg before and after this
> patch set to verify that the end result is the same ?
I did at 100MHz, but I was missing other test cases, so more testing
at the various other frequencies we might run at would be very much
welcome (and some cross-testing).
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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* [PATCH] spi/pxa2xx-pci: Enable DMA binding through device name
From: Andy Shevchenko @ 2014-07-24 11:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406196111-22861-1-git-send-email-hock.leong.kweh@intel.com>
On Thu, 2014-07-24 at 18:01 +0800, Kweh Hock Leong wrote:
> From: "Chew, Chiau Ee" <chiau.ee.chew@intel.com>
>
> Intel LPSS Baytrail supports two DMA controllers and SPI is only
> using one of the DMA controller. During DMA channel request,
> we need to ensure the requested Tx and Rx channels are from the correct
> DMA controller. Thus, we add extra checking in filter callback funtion
> by matching against the DMA controller device name.
I think this is bot good approach.
I already discussed with Mika how we could do this better for devices in
PCI mode. (Seems you have the problem only in PCI, right?)
So, for PCI case you have to get the device with BDF = BD0, where BDF is
Bus:Device:Function triplet for an SPI controller itself.
I don't know if it's good to enable CONFIG_PCI_QUIRKS and tweak
pci_dev_dma_source. In that case you just call pci_get_dma_source() and
get a PCI device of the DMA.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
> Signed-off-by: Kweh, Hock Leong <hock.leong.kweh@intel.com>
> ---
> drivers/spi/spi-pxa2xx-dma.c | 5 +++++
> drivers/spi/spi-pxa2xx-pci.c | 3 +++
> include/linux/spi/pxa2xx_spi.h | 1 +
> 3 files changed, 9 insertions(+)
>
> diff --git a/drivers/spi/spi-pxa2xx-dma.c b/drivers/spi/spi-pxa2xx-dma.c
> index c41ff14..4c4e918 100644
> --- a/drivers/spi/spi-pxa2xx-dma.c
> +++ b/drivers/spi/spi-pxa2xx-dma.c
> @@ -214,6 +214,11 @@ static bool pxa2xx_spi_dma_filter(struct dma_chan *chan, void *param)
> {
> const struct pxa2xx_spi_master *pdata = param;
>
> + if (pdata->dma_devname) {
> + if (strcmp(dev_name(chan->device->dev), pdata->dma_devname))
> + return false;
> + }
> +
> return chan->chan_id == pdata->tx_chan_id ||
> chan->chan_id == pdata->rx_chan_id;
> }
> diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c
> index c1865c9..7a21bce 100644
> --- a/drivers/spi/spi-pxa2xx-pci.c
> +++ b/drivers/spi/spi-pxa2xx-pci.c
> @@ -21,6 +21,7 @@ struct pxa_spi_info {
> int tx_chan_id;
> int rx_slave_id;
> int rx_chan_id;
> + char *dma_devname;
> };
>
> static struct pxa_spi_info spi_info_configs[] = {
> @@ -41,6 +42,7 @@ static struct pxa_spi_info spi_info_configs[] = {
> .tx_chan_id = 0,
> .rx_slave_id = 1,
> .rx_chan_id = 1,
> + .dma_devname = "0000:00:1e.0"
> },
> };
>
> @@ -72,6 +74,7 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
> spi_pdata.rx_slave_id = c->rx_slave_id;
> spi_pdata.rx_chan_id = c->rx_chan_id;
> spi_pdata.enable_dma = c->rx_slave_id >= 0 && c->tx_slave_id >= 0;
> + spi_pdata.dma_devname = c->dma_devname;
>
> ssp = &spi_pdata.ssp;
> ssp->phys_base = pci_resource_start(dev, 0);
> diff --git a/include/linux/spi/pxa2xx_spi.h b/include/linux/spi/pxa2xx_spi.h
> index 82d5111..264c3cb 100644
> --- a/include/linux/spi/pxa2xx_spi.h
> +++ b/include/linux/spi/pxa2xx_spi.h
> @@ -34,6 +34,7 @@ struct pxa2xx_spi_master {
> int tx_chan_id;
> int rx_slave_id;
> int tx_slave_id;
> + char *dma_devname;
>
> /* For non-PXA arches */
> struct ssp_device ssp;
--
Andy Shevchenko <andriy.shevchenko@intel.com>
Intel Finland Oy
^ permalink raw reply
* [PATCH v2 2/3] usb: host: st-hcd: Add st-hcd devicetree bindings documentation.
From: Lee Jones @ 2014-07-24 11:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406199616-10533-3-git-send-email-peter.griffin@linaro.org>
On Thu, 24 Jul 2014, Peter Griffin wrote:
> This patch documents the device tree documentation required for
> the ST HCD controller found in STMicroelectronics SoCs.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> Documentation/devicetree/bindings/usb/st-hcd.txt | 49 ++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/st-hcd.txt
If you've fixed the nits from the previous review, you should have
applied my Ack for this submission.
Acked-by: Lee Jones <lee.jones@linaro.org>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2 3/3] MAINTAINERS: Add st-hcd to ARCH/STI architecture
From: Lee Jones @ 2014-07-24 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406199616-10533-4-git-send-email-peter.griffin@linaro.org>
On Thu, 24 Jul 2014, Peter Griffin wrote:
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
I Acked, this already. Please carry them forward through revisions.
Acked-by: Lee Jones <lee.jones@linaro.org>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 702ca10..359a64e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1325,6 +1325,7 @@ F: drivers/pinctrl/pinctrl-st.c
> F: drivers/media/rc/st_rc.c
> F: drivers/i2c/busses/i2c-st.c
> F: drivers/tty/serial/st-asc.c
> +F: drivers/usb/host/st-hcd.c
>
> ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
> M: Lennert Buytenhek <kernel@wantstofly.org>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2 1/3] usb: host: st-hcd: Add USB HCD support for STi SoCs
From: Arnd Bergmann @ 2014-07-24 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406199616-10533-2-git-send-email-peter.griffin@linaro.org>
On Thursday 24 July 2014 12:00:14 Peter Griffin wrote:
> This driver adds support for the USB HCD present in STi
> SoC's from STMicroelectronics. It has been tested on the
> stih416-b2020 board.
Unfortunately, this seems to be done in a rather strange way,
I suspect you'll have to start over, but I'll let Alan and Greg
weigh in.
> +
> +struct st_hcd_dev {
> + int port_nr;
> + struct platform_device *ehci_device;
> + struct platform_device *ohci_device;
> + struct clk *ic_clk;
> + struct clk *ohci_clk;
> + struct reset_control *pwr;
> + struct reset_control *rst;
> + struct phy *phy;
> +};
The way you do this apparently is to create a device that encapsulates
the OHCI and the EHCI and then goes on to create child devices that
are bound to the real drivers.
The way it should be done however is to put the two host controllers
into DT directly and describe their resources (phy, clock, reset, ...)
using the DT bindings for those.
Depending on what kind of special requirements the ST version has,
this can be done either by using the generic ohci/ehci bindings
with extensions where necessary, or by creating a new binding and
new driver files that use 'ohci_init_driver'/'ehci_init_driver'
to inherit from the common code.
The first of the two approaches is preferred.
> + pdev->dev.parent = &parent->dev;
> + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
> + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
This is something we shouldn't ever do these days, the DMA settings
should come directly from DT without driver interaction.
Arnd
^ permalink raw reply
* [PATCHv3 2/7] ARM: mvebu: extend PMSU code to support dynamic frequency scaling
From: Jason Cooper @ 2014-07-24 11:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140724082902.0e64d454@free-electrons.com>
On Thu, Jul 24, 2014 at 08:29:02AM +0200, Thomas Petazzoni wrote:
> Dear Mike Turquette,
>
> On Wed, 23 Jul 2014 16:50:26 -0700, Mike Turquette wrote:
>
> > > * registers the frequency operating points supported by the CPU;
> > >
> > > * registers a clock notifier of the CPU clocks. The notifier function
> >
> > Where does this code register a clock notifier callback?
> >
> > > listens to the newly introduced APPLY_RATE_CHANGE event, and uses
> >
> > I don't see APPLY_RATE_CHANGE referenced.
>
> Yes, this is a mistake of the commit log, due to remains of the v2 of
> the patch series. Back in the v2, there was indeed a new clock notifier
> being used. But Stephen Boyd argued against that, and instead suggested
> to use a direct function call, which this v3 implements, as stated in
> the cover letter:
>
> - As suggested by Stephen Boyd, instead of using a new clock notifier
> that somewhat "hides" the dependency of the clk-cpu clock driver on
> the PMSU, use a direct call from the clk-cpu driver to the PMSU
> driver.
>
> The commit log of this commit was not adjusted consequently, and this
> is my fault. Jason, is it still time to change this commit log?
If there are no code changes, I'd prefer not to. We're rather late in
the game.
Even though it's not ideal, the commit in question does have a Link: tag
pointing at the patch email on which this conversation is based. So a
frustrated future developer won't be frustrated long. :)
thx,
Jason.
^ permalink raw reply
* [PATCH v4 3/3] crypto: Add Allwinner Security System crypto accelerator
From: Corentin LABBE @ 2014-07-24 11:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140724060054.GA6545@gondor.apana.org.au>
Le 24/07/2014 08:00, Herbert Xu a ?crit :
> On Sat, Jul 12, 2014 at 02:59:13PM +0200, LABBE Corentin wrote:
>>
>> +/* sunxi_hash_init: initialize request context
>> + * Activate the SS, and configure it for MD5 or SHA1
>> + */
>> +int sunxi_hash_init(struct ahash_request *areq)
>> +{
>> + const char *hash_type;
>> + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
>> + struct sunxi_req_ctx *op = crypto_ahash_ctx(tfm);
>> +
>> + mutex_lock(&ss->lock);
>> +
>> + hash_type = crypto_tfm_alg_name(areq->base.tfm);
>> +
>> + op->byte_count = 0;
>> + op->nbwait = 0;
>> + op->waitbuf = 0;
>> +
>> + /* Enable and configure SS for MD5 or SHA1 */
>> + if (strcmp(hash_type, "sha1") == 0)
>> + op->mode = SS_OP_SHA1;
>> + else
>> + op->mode = SS_OP_MD5;
>> +
>> + writel(op->mode | SS_ENABLED, ss->base + SS_CTL);
>> + return 0;
>
> The hash driver is completely broken. You are modifying tfm
> ctx data which is shared by all users of a single tfm. So
> if two users conduct hashes in parallel they will step all
> over each other.
So where can I store data for each request ?
>
> Worse, the unpaired mutex_lock will quickly lead to dead locks.
>
> You cannot assume that final will be called.
An user reported an equivalent problem when using openssl speed test with cryptodev.
Does cryptoqueue is a good answer to that problem since the device could handle only one transformation at a time ?
And perhaps with cryptoqueue, my first question is useless.
^ permalink raw reply
* [PATCH v2 3/3] MAINTAINERS: Add st-hcd to ARCH/STI architecture
From: Peter Griffin @ 2014-07-24 11:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406199616-10533-1-git-send-email-peter.griffin@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 702ca10..359a64e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1325,6 +1325,7 @@ F: drivers/pinctrl/pinctrl-st.c
F: drivers/media/rc/st_rc.c
F: drivers/i2c/busses/i2c-st.c
F: drivers/tty/serial/st-asc.c
+F: drivers/usb/host/st-hcd.c
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
--
1.9.1
^ permalink raw reply related
* [PATCH v2 2/3] usb: host: st-hcd: Add st-hcd devicetree bindings documentation.
From: Peter Griffin @ 2014-07-24 11:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406199616-10533-1-git-send-email-peter.griffin@linaro.org>
This patch documents the device tree documentation required for
the ST HCD controller found in STMicroelectronics SoCs.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
Documentation/devicetree/bindings/usb/st-hcd.txt | 49 ++++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/st-hcd.txt
diff --git a/Documentation/devicetree/bindings/usb/st-hcd.txt b/Documentation/devicetree/bindings/usb/st-hcd.txt
new file mode 100644
index 0000000..b963be2
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/st-hcd.txt
@@ -0,0 +1,49 @@
+ST HCD (Host Controller Driver) for USB 2.0 and 1.1
+
+The device node has the following properties.
+
+Required properties:
+ - compatible : must be "st,usb-300x"
+ - reg : physical base addresses of the controller and length of memory mapped
+ region
+ - reg-names : names associated to the reg defines above, should be "ehci" and "ohci"
+ - interrupts : interrupt numbers to the cpu
+ - interrupt-names : should be "ehci" and "ohci"
+
+ - pinctrl-names : a pinctrl state named "default" must be defined
+- pinctrl-0 : phandle referencing pin configuration of the USB controller
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+
+ - clocks : phandle list of usb clocks.
+ - clock-names : should be "ic" for interconnect clock and "ohci" for the 48MHz clock
+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+ - resets : phandle to the powerdown and reset controller for the USB IP
+ - reset-names : should be "powerdown" and "softreset".
+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
+See: Documentation/devicetree/bindings/reset/reset.txt
+
+Example:
+
+usb0: usb at fe100000 {
+ compatible = "st,usb-300x";
+ reg = <0xfe1ffc00 0x100>,
+ <0xfe1ffe00 0x100>;
+ reg-names = "ohci", "ehci";
+
+ interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>,
+ <GIC_SPI 149 IRQ_TYPE_NONE>;
+ interrupt-names = "ehci", "ohci";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&clk_s_a1_ls CLK_ICN_IF_2>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "ohci";
+
+ resets = <&powerdown STIH416_USB0_POWERDOWN>,
+ <&softreset STIH416_USB0_SOFTRESET>;
+ reset-names = "powerdown", "softreset";
+
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
+};
--
1.9.1
^ permalink raw reply related
* [PATCH v2 1/3] usb: host: st-hcd: Add USB HCD support for STi SoCs
From: Peter Griffin @ 2014-07-24 11:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406199616-10533-1-git-send-email-peter.griffin@linaro.org>
This driver adds support for the USB HCD present in STi
SoC's from STMicroelectronics. It has been tested on the
stih416-b2020 board.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/usb/host/Kconfig | 12 ++
drivers/usb/host/Makefile | 1 +
drivers/usb/host/st-hcd.c | 460 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 473 insertions(+)
create mode 100644 drivers/usb/host/st-hcd.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 61b7817..a5e7f71 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -753,6 +753,18 @@ config USB_HCD_SSB
If unsure, say N.
+config USB_HCD_ST
+ tristate "STMicroelectronics STi family HCD support"
+ depends on ARCH_STI && OF
+ select USB_OHCI_HCD_PLATFORM if USB_OHCI_HCD
+ select USB_EHCI_HCD_PLATFORM if USB_EHCI_HCD
+ select GENERIC_PHY
+ help
+ Enable support for the EHCI and OHCI host controller on ST
+ consumer electronics SoCs.
+
+ If unsure, say N.
+
config USB_HCD_TEST_MODE
bool "HCD test mode support"
---help---
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index af89a90..af0b81d 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -74,3 +74,4 @@ obj-$(CONFIG_USB_HCD_SSB) += ssb-hcd.o
obj-$(CONFIG_USB_FUSBH200_HCD) += fusbh200-hcd.o
obj-$(CONFIG_USB_FOTG210_HCD) += fotg210-hcd.o
obj-$(CONFIG_USB_MAX3421_HCD) += max3421-hcd.o
+obj-$(CONFIG_USB_HCD_ST) += st-hcd.o
diff --git a/drivers/usb/host/st-hcd.c b/drivers/usb/host/st-hcd.c
new file mode 100644
index 0000000..eaec345
--- /dev/null
+++ b/drivers/usb/host/st-hcd.c
@@ -0,0 +1,460 @@
+/*
+ * STMicroelectronics HCD (Host Controller Driver) for USB 2.0 and 1.1.
+ *
+ * Copyright (c) 2013 STMicroelectronics (R&D) Ltd.
+ * Authors: Stephen Gallimore <stephen.gallimore@st.com>
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/of.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_clock.h>
+#include <linux/delay.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/reset.h>
+#include <linux/phy/phy.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/usb/ehci_pdriver.h>
+
+#include "ohci.h"
+
+#define EHCI_CAPS_SIZE 0x10
+#define AHB2STBUS_INSREG01 (EHCI_CAPS_SIZE + 0x84)
+
+struct st_hcd_dev {
+ int port_nr;
+ struct platform_device *ehci_device;
+ struct platform_device *ohci_device;
+ struct clk *ic_clk;
+ struct clk *ohci_clk;
+ struct reset_control *pwr;
+ struct reset_control *rst;
+ struct phy *phy;
+};
+
+static inline void st_ehci_configure_bus(void __iomem *regs)
+{
+ /* Set EHCI packet buffer IN/OUT threshold to 128 bytes */
+ u32 threshold = 128 | (128 << 16);
+
+ writel(threshold, regs + AHB2STBUS_INSREG01);
+}
+
+static int st_hcd_enable_clocks(struct device *dev,
+ struct st_hcd_dev *hcd_dev)
+{
+ int err;
+
+ /*
+ * The interconnect input clock have either a fixed
+ * rate or the rate is defined on boot, so we are only concerned about
+ * enabling any gates for this clock.
+ */
+ err = clk_prepare_enable(hcd_dev->ic_clk);
+ if (err) {
+ dev_err(dev, "can't enable ic clock\n");
+ return err;
+ }
+
+ /*
+ * The 48MHz OHCI clock is usually provided by a programmable
+ * frequency synthesizer, which is often not programmed on boot/chip
+ * reset, so we set its rate here to ensure it is correct.
+ *
+ * However not all SoC's have a dedicated OHCI clock so it isn't fatal
+ * for this not to exist.
+ */
+ if (!hcd_dev->ohci_clk)
+ return 0;
+
+ err = clk_set_rate(hcd_dev->ohci_clk, 48000000);
+ if (err) {
+ dev_err(dev, "can't set OHCI clock rate\n");
+ goto error;
+ }
+ err = clk_prepare_enable(hcd_dev->ohci_clk);
+ if (err) {
+ dev_err(dev, "can't enable OHCI clock\n");
+ goto error;
+ }
+
+ return 0;
+error:
+ clk_disable_unprepare(hcd_dev->ic_clk);
+ return err;
+}
+
+static void st_hcd_disable_clocks(struct st_hcd_dev *hcd_dev)
+{
+ clk_disable_unprepare(hcd_dev->ohci_clk);
+ clk_disable_unprepare(hcd_dev->ic_clk);
+}
+
+static void st_hcd_assert_resets(struct device *dev,
+ struct st_hcd_dev *hcd_dev)
+{
+ int err;
+
+ err = reset_control_assert(hcd_dev->pwr);
+ if (err)
+ dev_err(dev, "unable to put into powerdown\n");
+
+ err = reset_control_assert(hcd_dev->rst);
+ if (err)
+ dev_err(dev, "unable to put into softreset\n");
+}
+
+static int st_hcd_deassert_resets(struct device *dev,
+ struct st_hcd_dev *hcd_dev)
+{
+ int err;
+
+ err = reset_control_deassert(hcd_dev->pwr);
+ if (err) {
+ dev_err(dev, "unable to bring out of powerdown\n");
+ return err;
+ }
+
+ err = reset_control_deassert(hcd_dev->rst);
+ if (err) {
+ dev_err(dev, "unable to bring out of softreset\n");
+ reset_control_assert(hcd_dev->pwr);
+ return err;
+ }
+
+ return 0;
+}
+
+static const struct usb_ehci_pdata ehci_pdata = {
+};
+
+static const struct usb_ohci_pdata ohci_pdata = {
+};
+
+static struct platform_device *st_hcd_device_create(const char *name, int id,
+ struct platform_device *parent)
+{
+ struct platform_device *pdev;
+ const char *platform_name;
+ struct resource *res;
+ struct resource hcd_res[2];
+ int ret;
+
+ res = platform_get_resource_byname(parent, IORESOURCE_MEM, name);
+ if (!res)
+ return ERR_PTR(-ENODEV);
+
+ hcd_res[0] = *res;
+
+ res = platform_get_resource_byname(parent, IORESOURCE_IRQ, name);
+ if (!res)
+ return ERR_PTR(-ENODEV);
+
+ hcd_res[1] = *res;
+
+ platform_name = kasprintf(GFP_KERNEL, "%s-platform", name);
+ if (!platform_name)
+ return ERR_PTR(-ENOMEM);
+
+ pdev = platform_device_alloc(platform_name, id);
+
+ kfree(platform_name);
+
+ if (!pdev)
+ return ERR_PTR(-ENOMEM);
+
+ pdev->dev.parent = &parent->dev;
+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+
+ ret = platform_device_add_resources(pdev, hcd_res, ARRAY_SIZE(hcd_res));
+ if (ret)
+ goto error;
+
+ if (!strcmp(name, "ohci"))
+ ret = platform_device_add_data(pdev, &ohci_pdata,
+ sizeof(ohci_pdata));
+ else
+ ret = platform_device_add_data(pdev, &ehci_pdata,
+ sizeof(ehci_pdata));
+
+ if (ret)
+ goto error;
+
+ ret = platform_device_add(pdev);
+ if (ret)
+ goto error;
+
+ return pdev;
+
+error:
+ platform_device_put(pdev);
+ return ERR_PTR(ret);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int st_hcd_resume(struct device *dev)
+{
+ struct st_hcd_dev *hcd_dev = dev_get_drvdata(dev);
+ struct usb_hcd *ehci_hcd = platform_get_drvdata(hcd_dev->ehci_device);
+ int err;
+
+ pinctrl_pm_select_default_state(dev);
+
+ err = st_hcd_enable_clocks(dev, hcd_dev);
+ if (err)
+ return err;
+
+ err = phy_init(hcd_dev->phy);
+ if (err) {
+ dev_err(dev, "phy initialization failed\n");
+ goto err_disable_clocks;
+ }
+
+ err = phy_power_on(hcd_dev->phy);
+ if (err && (err != -ENOTSUPP)) {
+ dev_err(dev, "phy power on failed\n");
+ goto err_phy_exit;
+ }
+
+ err = st_hcd_deassert_resets(dev, hcd_dev);
+ if (err)
+ goto err_phy_off;
+
+ st_ehci_configure_bus(ehci_hcd->regs);
+
+ return 0;
+
+err_phy_off:
+ phy_power_off(hcd_dev->phy);
+err_phy_exit:
+ phy_exit(hcd_dev->phy);
+err_disable_clocks:
+ st_hcd_disable_clocks(hcd_dev);
+
+ return err;
+}
+
+static int st_hcd_suspend(struct device *dev)
+{
+ struct st_hcd_dev *hcd_dev = dev_get_drvdata(dev);
+ int err;
+
+ err = reset_control_assert(hcd_dev->pwr);
+ if (err) {
+ dev_err(dev, "unable to put into powerdown\n");
+ return err;
+ }
+
+ err = reset_control_assert(hcd_dev->rst);
+ if (err) {
+ dev_err(dev, "unable to put into softreset\n");
+ return err;
+ }
+
+ err = phy_power_off(hcd_dev->phy);
+ if (err && (err != -ENOTSUPP)) {
+ dev_err(dev, "phy power off failed\n");
+ return err;
+ }
+
+ phy_exit(hcd_dev->phy);
+
+ st_hcd_disable_clocks(hcd_dev);
+
+ pinctrl_pm_select_sleep_state(dev);
+
+ return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(st_hcd_pm, st_hcd_suspend, st_hcd_resume);
+
+static int st_hcd_probe_clocks(struct device *dev,
+ struct st_hcd_dev *hcd_dev)
+{
+ hcd_dev->ic_clk = devm_clk_get(dev, "ic");
+ if (IS_ERR(hcd_dev->ic_clk)) {
+ dev_err(dev, "ic clock not found\n");
+ return PTR_ERR(hcd_dev->ic_clk);
+ }
+
+ /* Some SoCs don't have a dedicated ohci clk */
+ hcd_dev->ohci_clk = devm_clk_get(dev, "ohci");
+ if (IS_ERR(hcd_dev->ohci_clk)) {
+ hcd_dev->ohci_clk = NULL;
+ dev_info(dev, "48MHz OHCI clock not found\n");
+ }
+
+ return st_hcd_enable_clocks(dev, hcd_dev);
+}
+
+
+static int st_hcd_probe_resets(struct device *dev,
+ struct st_hcd_dev *hcd_dev)
+{
+ hcd_dev->pwr = devm_reset_control_get(dev, "powerdown");
+ if (IS_ERR(hcd_dev->pwr)) {
+ dev_err(dev, "power reset control not found\n");
+ return PTR_ERR(hcd_dev->pwr);
+ }
+
+ hcd_dev->rst = devm_reset_control_get(dev, "softreset");
+ if (IS_ERR(hcd_dev->rst)) {
+ dev_err(dev, "soft reset control not found\n");
+ return PTR_ERR(hcd_dev->rst);
+ }
+
+ return st_hcd_deassert_resets(dev, hcd_dev);
+}
+
+static int st_hcd_probe_ehci_setup(struct platform_device *pdev)
+{
+ struct resource *res;
+ void __iomem *ehci_regs;
+
+ /*
+ * We need to do some integration specific setup in the EHCI
+ * controller, which the EHCI platform driver does not provide any
+ * hooks to allow us to do during its initialisation.
+ */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
+ ehci_regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ehci_regs))
+ return PTR_ERR(ehci_regs);
+
+ st_ehci_configure_bus(ehci_regs);
+ devm_iounmap(&pdev->dev, ehci_regs);
+
+ return 0;
+}
+
+static int st_hcd_remove(struct platform_device *pdev)
+{
+ struct st_hcd_dev *hcd_dev = platform_get_drvdata(pdev);
+
+ platform_device_unregister(hcd_dev->ehci_device);
+ platform_device_unregister(hcd_dev->ohci_device);
+
+ phy_power_off(hcd_dev->phy);
+
+ phy_exit(hcd_dev->phy);
+
+ st_hcd_assert_resets(&pdev->dev, hcd_dev);
+
+ st_hcd_disable_clocks(hcd_dev);
+
+ return 0;
+}
+
+static int st_hcd_probe(struct platform_device *pdev)
+{
+ struct st_hcd_dev *hcd_dev;
+ int id;
+ int err;
+
+ id = of_alias_get_id(pdev->dev.of_node, "usb");
+ if (id < 0) {
+ dev_err(&pdev->dev, "No ID specified via DT alias\n");
+ return -ENODEV;
+ }
+
+ hcd_dev = devm_kzalloc(&pdev->dev, sizeof(*hcd_dev), GFP_KERNEL);
+ if (!hcd_dev)
+ return -ENOMEM;
+
+ hcd_dev->port_nr = id;
+
+ err = st_hcd_probe_clocks(&pdev->dev, hcd_dev);
+ if (err)
+ return err;
+
+ err = st_hcd_probe_resets(&pdev->dev, hcd_dev);
+ if (err)
+ goto err_disable_clocks;
+
+ err = st_hcd_probe_ehci_setup(pdev);
+ if (err)
+ goto err_assert_resets;
+
+ hcd_dev->phy = devm_phy_get(&pdev->dev, "usb2-phy");
+ if (IS_ERR(hcd_dev->phy)) {
+ dev_err(&pdev->dev, "no PHY configured\n");
+ err = PTR_ERR(hcd_dev->phy);
+ goto err_assert_resets;
+ }
+
+ err = phy_init(hcd_dev->phy);
+ if (err) {
+ dev_err(&pdev->dev, "phy initialization failed\n");
+ goto err_assert_resets;
+ }
+
+ err = phy_power_on(hcd_dev->phy);
+ if (err && (err != -ENOTSUPP)) {
+ dev_err(&pdev->dev, "phy power on failed\n");
+ goto err_phy_exit;
+ }
+
+ hcd_dev->ehci_device = st_hcd_device_create("ehci", id, pdev);
+ if (IS_ERR(hcd_dev->ehci_device)) {
+ err = PTR_ERR(hcd_dev->ehci_device);
+ goto err_phy_off;
+ }
+
+ hcd_dev->ohci_device = st_hcd_device_create("ohci", id, pdev);
+ if (IS_ERR(hcd_dev->ohci_device)) {
+ err = PTR_ERR(hcd_dev->ohci_device);
+ goto err_remove_ehci;
+ }
+
+ platform_set_drvdata(pdev, hcd_dev);
+
+ return 0;
+
+err_remove_ehci:
+ platform_device_del(hcd_dev->ehci_device);
+err_phy_off:
+ phy_power_off(hcd_dev->phy);
+err_phy_exit:
+ phy_exit(hcd_dev->phy);
+err_assert_resets:
+ st_hcd_assert_resets(&pdev->dev, hcd_dev);
+err_disable_clocks:
+ st_hcd_disable_clocks(hcd_dev);
+
+ return err;
+}
+
+static const struct of_device_id st_hcd_match[] = {
+ { .compatible = "st,usb-300x" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, st_hcd_match);
+
+static struct platform_driver st_hcd_driver = {
+ .probe = st_hcd_probe,
+ .remove = st_hcd_remove,
+ .driver = {
+ .name = "st-hcd",
+ .pm = &st_hcd_pm,
+ .of_match_table = st_hcd_match,
+ },
+};
+
+module_platform_driver(st_hcd_driver);
+
+MODULE_DESCRIPTION("STMicroelectronics On-Chip USB Host Controller");
+MODULE_AUTHOR("Stephen Gallimore <stephen.gallimore@st.com>");
+MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related
* [PATCH v2 0/3] Add USB HCD support for STi SoCs
From: Peter Griffin @ 2014-07-24 11:00 UTC (permalink / raw)
To: linux-arm-kernel
This driver adds support for the USB HCD controller present in STi
SoC's from STMicroelectronics. It has been tested on the stih416-b2020
board.
The original author is no longer with the company and therefore emails
to his address bounce, thus I have not added him to CC.
Changes since v1:
- Correct s/OCHI/OHCI/ spelling
- Improve kconfig help message
- Various formating / spelling nits identified by Lee Jones
- Make driver depend on OF & remove node checks in code
- Use devm_ioremap_resource
- Remove unnecessary header files
Peter Griffin (3):
usb: host: st-hcd: Add USB HCD support for STi SoCs
usb: host: st-hcd: Add st-hcd devicetree bindings documentation.
MAINTAINERS: Add st-hcd to ARCH/STI architecture
Documentation/devicetree/bindings/usb/st-hcd.txt | 51 +++
MAINTAINERS | 1 +
drivers/usb/host/Kconfig | 13 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/st-hcd.c | 471 +++++++++++++++++++++++
5 files changed, 537 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/st-hcd.txt
create mode 100644 drivers/usb/host/st-hcd.c
--
1.9.1
^ permalink raw reply
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