* [PATCH v2 4/4] ARM64: dts: meson-gxbb: Add SPIFC node
From: Kevin Hilman @ 2016-09-12 17:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473409738-27175-5-git-send-email-jbrunet@baylibre.com>
Jerome Brunet <jbrunet@baylibre.com> writes:
> From: Neil Armstrong <narmstrong@baylibre.com>
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Applied,
Kevin
^ permalink raw reply
* [PATCH] ARM: decompressor: reset ttbcr fields to use TTBR0 on ARMv7
From: Robin Murphy @ 2016-09-12 17:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473663420-18629-1-git-send-email-sramana@codeaurora.org>
On 12/09/16 07:57, Srinivas Ramana wrote:
> If the bootloader uses the long descriptor format and jumps to
> kernel decompressor code, TTBCR may not be in a right state.
> Before enabling the MMU, it is required to clear the TTBCR.PD0
> field to use TTBR0 for translation table walks.
>
> The 'commit dbece45894d3a ("ARM: 7501/1: decompressor:
> reset ttbcr for VMSA ARMv7 cores")' does the reset of TTBCR.N, but
> doesn't consider all the bits for the size of TTBCR.N.
>
> Clear TTBCR.PD0 field and reset all the three bits of TTBCR.N to
> indicate the use of TTBR0 and the correct base address width.
>
> Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
> ---
> arch/arm/boot/compressed/head.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index af11c2f8f3b7..fc6d541549a2 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -779,7 +779,7 @@ __armv7_mmu_cache_on:
> orrne r0, r0, #1 @ MMU enabled
> movne r1, #0xfffffffd @ domain 0 = client
> bic r6, r6, #1 << 31 @ 32-bit translation system
Hmm, if TTBCR.EAE _was_ actually set...
> - bic r6, r6, #3 << 0 @ use only ttbr0
> + bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
> mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
> mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
> mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
...then strictly the TLBIALL needs to happen after the ISB following
this update. Otherwise per B3.10.2 of DDI406C.c I think we might be into
unpredictable territory - i.e. if the TLB happens to treat long- and
short-descriptor entries differently then the TLBI beforehand (with EAE
set) may be at liberty to only discard long-descriptor entries and leave
bogus short-descriptor entries sitting around.
In other words, something like (completely untested):
---8<---
diff --git a/arch/arm/boot/compressed/head.S
b/arch/arm/boot/compressed/head.S
index af11c2f8f3b7..536b7781024a 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -764,7 +764,6 @@ __armv7_mmu_cache_on:
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
tst r11, #0xf @ VMSA
- mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
#endif
mrc p15, 0, r0, c1, c0, 0 @ read control reg
bic r0, r0, #1 << 28 @ clear SCTLR.TRE
@@ -783,8 +782,11 @@ __armv7_mmu_cache_on:
mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
-#endif
mcr p15, 0, r0, c7, c5, 4 @ ISB
+ mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
+#else
+ mcr p15, 0, r0, c7, c5, 4 @ ISB
+#endif
mcr p15, 0, r0, c1, c0, 0 @ load control register
mrc p15, 0, r0, c1, c0, 0 @ and read it back
---8<---
Robin.
^ permalink raw reply related
* [PATCH] ARM: dts: wheat: add DU support
From: Sergei Shtylyov @ 2016-09-12 17:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <15676050.WJW1jK1n2R@wasted.cogentembedded.com>
On 09/02/2016 12:29 AM, Sergei Shtylyov wrote:
> Define the Wheat board dependent part of the DU device node.
> Add the device nodes for the Analog Devices ADV7513 HDMI transmitters
> connected to DU0/1. Add the necessary subnodes to interconnect DU with
> HDMI transmitters/connectors.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20160901-v4.8-rc4' of Simon Horman's
> 'renesas.git' repo plus the Wheat CAN and SDHI patches posted earlier...
> The path depends on the 2 DRM patches just posted in order to work correctly!
In principle, both these patches have been queued by the maintainers...
Simon, are you going to wait till they hit media_tree.git? Linus' tree?
MBR, Sergei
^ permalink raw reply
* [PATCH V5] perf tools: adding support for address filters
From: Mathieu Poirier @ 2016-09-12 17:53 UTC (permalink / raw)
To: linux-arm-kernel
This patch makes it possible to use the current filter
framework with address filters. That way address filters for
HW tracers such as CoreSight and IntelPT can be communicated
to the kernel drivers.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
Changes for V5:
- Modified perf_evsel__append_filter() to take a string format
rather than an operation.
Changes for V4:
- Added support for address filters over more than one
nibble.
- Removed Jiri's ack, this version is too different from
what was reviewed.
Changes for V3:
- Added Jiri's ack.
- Rebased to v4.8-rc5.
Changes for V2:
- Rebased to v4.8-rc4.
- Revisited error path.
tools/perf/util/evsel.c | 4 ++--
tools/perf/util/evsel.h | 2 +-
tools/perf/util/parse-events.c | 40 +++++++++++++++++++++++++++++++++++-----
3 files changed, 38 insertions(+), 8 deletions(-)
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index d40f852d2de2..a9bb277f221f 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -1047,14 +1047,14 @@ int perf_evsel__set_filter(struct perf_evsel *evsel, const char *filter)
}
int perf_evsel__append_filter(struct perf_evsel *evsel,
- const char *op, const char *filter)
+ const char *fmt, const char *filter)
{
char *new_filter;
if (evsel->filter == NULL)
return perf_evsel__set_filter(evsel, filter);
- if (asprintf(&new_filter,"(%s) %s (%s)", evsel->filter, op, filter) > 0) {
+ if (asprintf(&new_filter, fmt, evsel->filter, filter) > 0) {
free(evsel->filter);
evsel->filter = new_filter;
return 0;
diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h
index 8ceb7ebb51f5..50595c8c7207 100644
--- a/tools/perf/util/evsel.h
+++ b/tools/perf/util/evsel.h
@@ -236,7 +236,7 @@ void perf_evsel__set_sample_id(struct perf_evsel *evsel,
int perf_evsel__set_filter(struct perf_evsel *evsel, const char *filter);
int perf_evsel__append_filter(struct perf_evsel *evsel,
- const char *op, const char *filter);
+ const char *fmt, const char *filter);
int perf_evsel__apply_filter(struct perf_evsel *evsel, int ncpus, int nthreads,
const char *filter);
int perf_evsel__apply_drv_configs(struct perf_evsel *evsel,
diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
index 2eb8b1ed4cc8..8e683979ccd8 100644
--- a/tools/perf/util/parse-events.c
+++ b/tools/perf/util/parse-events.c
@@ -1760,20 +1760,50 @@ foreach_evsel_in_last_glob(struct perf_evlist *evlist,
static int set_filter(struct perf_evsel *evsel, const void *arg)
{
const char *str = arg;
+ bool found = false;
+ int nr_addr_filters = 0;
+ struct perf_pmu *pmu = NULL;
- if (evsel == NULL || evsel->attr.type != PERF_TYPE_TRACEPOINT) {
- fprintf(stderr,
- "--filter option should follow a -e tracepoint option\n");
- return -1;
+ if (evsel == NULL)
+ goto err;
+
+ if (evsel->attr.type == PERF_TYPE_TRACEPOINT) {
+ if (perf_evsel__append_filter(evsel,
+ "(%s) && (%s)", str) < 0) {
+ fprintf(stderr,
+ "not enough memory to hold filter string\n");
+ return -1;
+ }
+
+ return 0;
}
- if (perf_evsel__append_filter(evsel, "&&", str) < 0) {
+ while ((pmu = perf_pmu__scan(pmu)) != NULL)
+ if (pmu->type == evsel->attr.type) {
+ found = true;
+ break;
+ }
+
+ if (found)
+ perf_pmu__scan_file(pmu, "nr_addr_filters",
+ "%d", &nr_addr_filters);
+
+ if (!nr_addr_filters)
+ goto err;
+
+ if (perf_evsel__append_filter(evsel, "%s,%s", str) < 0) {
fprintf(stderr,
"not enough memory to hold filter string\n");
return -1;
}
return 0;
+
+err:
+ fprintf(stderr,
+ "--filter option should follow a -e tracepoint or HW tracer option\n");
+
+ return -1;
}
int parse_filter(const struct option *opt, const char *str,
--
2.7.4
^ permalink raw reply related
* [4.8.0-rc1] am335x-evm boot failure: n_tty_receive_buf_common: "Unable to handle kernel paging request.."
From: Grygorii Strashko @ 2016-09-12 17:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAALWOA_=9fMG156H_XSZBjeckQUK-moDWoRE6_kr-8=Z_-KZuA@mail.gmail.com>
Hi Matthijs,
On 09/10/2016 01:23 AM, Matthijs van Duin wrote:
> If you look more carefully the first problem is actually a bus error:
> [ 15.776190] Unhandled fault: external abort on non-linefetch (0x1028)
> at 0xf9e3e044
> [ 15.825925] PC is at omap_hwmod_read+0x14/0x28
> [ 15.830583] LR is at omap_rtc_wait_not_busy+0x1c/0x44
>
> I have no idea how the kernel manages to continue after a bus error in
> a driver (inside local_irq_disable even), but I wouldn't be inclined
> to take any later errors seriously.
>
> See also the "4.8 crash on BeagleBone" thread on linux-omap.
>
Thanks for your comments.
I knew about RTc problem with 4.8, so I've reported n_tty_receive_buf_common problem
"in advance" and waited for fix to be merged before re-testing it.
So, log is below and issue is still here in 4.8.0-rc6 :( Boot failed 10 times from 100.
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.8.0-rc6-13910-g9395452 (lcpdbld at dflsdit-build06.dal.design.ti.com) (gcc version 4.9.3 20150413 (prerelease) (Linaro GCC 4.9-2015.05) ) #1 SMP Mon Sep 12 05:20:40 CDT 2016
[ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] OF: fdt:Machine model: TI AM335x EVM
[ 0.000000] cma: Reserved 16 MiB at 0xbe800000
[ 0.000000] Memory policy: Data cache writeback
[ 0.000000] CPU: All CPU(s) started in SVC mode.
[ 0.000000] AM335X ES2.1 (sgx neon )
[ 0.000000] percpu: Embedded 15 pages/cpu @ef6b7000 s31168 r8192 d22080 u61440
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 259904
[ 0.000000] Kernel command line: console=ttyO0,115200n8 earlyprintk=serial,ttyO0,115200n8 rootwait ip=:::::eth0:dhcp root=/dev/nfs rw nfsroot=192.168.1.254:/home/NFS_exports/am335x-evm/autofs/8820840e10ba8f8ed7842d9999fc04a3,nolock,v3,tcp,rsize=4096,wsize=4096
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 999636K/1046528K available (7168K kernel code, 772K rwdata, 2368K rodata, 1024K init, 8122K bss, 30508K reserved, 16384K cma-reserved, 243712K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0800000 (8160 kB)
[ 0.000000] .init : 0xc0b00000 - 0xc0c00000 (1024 kB)
[ 0.000000] .data : 0xc0c00000 - 0xc0cc11ac ( 773 kB)
[ 0.000000] .bss : 0xc0cc3000 - 0xc14b1878 (8123 kB)
[ 0.000000] Running RCU self tests
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU lockdep checking is enabled.
[ 0.000000] Build-time adjustment of leaf fanout to 32.
[ 0.000000] RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=1
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts
[ 0.000000] OMAP clockevent source: timer2 at 24000000 Hz
[ 0.000019] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
[ 0.000042] clocksource: timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
[ 0.000094] OMAP clocksource: timer1 at 24000000 Hz
[ 0.000653] clocksource_probe: no matching clocksources found
[ 0.001585] Console: colour dummy device 80x30
[ 0.001645] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[ 0.001655] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.001663] ... MAX_LOCK_DEPTH: 48
[ 0.001671] ... MAX_LOCKDEP_KEYS: 8191
[ 0.001679] ... CLASSHASH_SIZE: 4096
[ 0.001687] ... MAX_LOCKDEP_ENTRIES: 32768
[ 0.001695] ... MAX_LOCKDEP_CHAINS: 65536
[ 0.001702] ... CHAINHASH_SIZE: 32768
[ 0.001711] memory used by lock dependency info: 5167 kB
[ 0.001719] per task-struct memory footprint: 1536 bytes
[ 0.001756] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
[ 0.078616] pid_max: default: 32768 minimum: 301
[ 0.079087] Security Framework initialized
[ 0.079234] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.079251] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.082794] CPU: Testing write buffer coherency: ok
[ 0.084361] CPU0: thread -1, cpu 0, socket -1, mpidr 0
[ 0.084441] Setting up static identity map for 0x80100000 - 0x80100070
[ 0.089124] Brought up 1 CPUs
[ 0.089150] SMP: Total of 1 processors activated (996.14 BogoMIPS).
[ 0.089161] CPU: All CPU(s) started in SVC mode.
[ 0.093177] devtmpfs: initialized
[ 0.137436] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
[ 0.138367] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.140281] pinctrl core: initialized pinctrl subsystem
[ 0.145507] NET: Registered protocol family 16
[ 0.151271] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.199354] omap_hwmod: debugss: _wait_target_disable failed
[ 0.251659] cpuidle: using governor menu
[ 0.265457] OMAP GPIO hardware version 0.1
[ 0.291518] omap-gpmc 50000000.gpmc: could not find pctldev for node /ocp/l4_wkup at 44c00000/scm at 210000/pinmux at 800/nandflash_pins_s0, deferring probe
[ 0.297679] No ATAGs?
[ 0.297706] hw-breakpoint: debug architecture 0x4 unsupported.
[ 0.297958] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[ 0.297974] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[ 0.345358] edma 49000000.edma: TI EDMA DMA engine driver
[ 0.352391] SCSI subsystem initialized
[ 0.354164] omap_i2c 44e0b000.i2c: could not find pctldev for node /ocp/l4_wkup at 44c00000/scm at 210000/pinmux at 800/pinmux_i2c0_pins, deferring probe
[ 0.354281] omap_i2c 4802a000.i2c: could not find pctldev for node /ocp/l4_wkup at 44c00000/scm at 210000/pinmux at 800/pinmux_i2c1_pins, deferring probe
[ 0.354607] pps_core: LinuxPPS API ver. 1 registered
[ 0.354620] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.354674] PTP clock support registered
[ 0.359492] clocksource: Switched to clocksource timer1
[ 0.463483] VFS: Disk quotas dquot_6.6.0
[ 0.463673] VFS: Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[ 0.496612] NET: Registered protocol family 2
[ 0.498732] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.498901] TCP bind hash table entries: 8192 (order: 6, 294912 bytes)
[ 0.501410] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.501734] UDP hash table entries: 512 (order: 3, 40960 bytes)
[ 0.502061] UDP-Lite hash table entries: 512 (order: 3, 40960 bytes)
[ 0.503022] NET: Registered protocol family 1
[ 0.505158] RPC: Registered named UNIX socket transport module.
[ 0.505186] RPC: Registered udp transport module.
[ 0.505196] RPC: Registered tcp transport module.
[ 0.505207] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.508251] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
[ 0.513177] futex hash table entries: 256 (order: 2, 16384 bytes)
[ 0.513402] audit: initializing netlink subsys (disabled)
[ 0.513663] audit: type=2000 audit(0.510:1): initialized
[ 0.517866] workingset: timestamp_bits=14 max_order=18 bucket_order=4
[ 0.521013] NFS: Registering the id_resolver key type
[ 0.521391] Key type id_resolver registered
[ 0.521409] Key type id_legacy registered
[ 0.521572] jffs2: version 2.2. (NAND) (SUMMARY) 2001-2006 Red Hat, Inc.
[ 0.527094] bounce: pool size: 64 pages
[ 0.527269] io scheduler noop registered
[ 0.527283] io scheduler deadline registered
[ 0.527408] io scheduler cfq registered (default)
[ 0.530203] pinctrl-single 44e10800.pinmux: 142 pins at pa f9e10800 size 568
[ 0.534684] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 0.541159] omap_uart 44e09000.serial: no wakeirq for uart0
[ 0.541880] 44e09000.serial: ttyO0 at MMIO 0x44e09000 (irq = 158, base_baud = 3000000) is a OMAP UART0
[ 1.275391] console [ttyO0] enabled
[ 1.281126] omap_uart 48022000.serial: no wakeirq for uart1
[ 1.287365] 48022000.serial: ttyO1 at MMIO 0x48022000 (irq = 159, base_baud = 3000000) is a OMAP UART1
[ 1.338657] brd: module loaded
[ 1.367185] loop: module loaded
[ 1.373352] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 1.383884] libphy: Fixed MDIO Bus: probed
[ 1.459543] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
[ 1.465952] davinci_mdio 4a101000.mdio: detected phy mask fffffffe
[ 1.476726] libphy: 4a101000.mdio: probed
[ 1.481137] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver Atheros 8031 ethernet
[ 1.492442] cpsw 4a100000.ethernet: Detected MACID = c8:a0:30:a1:c2:d7
[ 1.504676] mousedev: PS/2 mouse device common for all mice
[ 1.510690] i2c /dev entries driver
[ 1.516891] omap_hsmmc 48060000.mmc: Got CD GPIO
[ 1.671388] ledtrig-cpu: registered to indicate activity on CPUs
[ 1.679632] oprofile: using arm/armv7
[ 1.684246] Initializing XFRM netlink socket
[ 1.689112] NET: Registered protocol family 10
[ 1.700808] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 1.709717] NET: Registered protocol family 17
[ 1.714478] NET: Registered protocol family 15
[ 1.719607] Key type dns_resolver registered
[ 1.724306] omap_voltage_late_init: Voltage driver support not added
[ 1.731044] sr_dev_init: No voltage domain specified for smartreflex0. Cannot initialize
[ 1.739556] sr_dev_init: No voltage domain specified for smartreflex1. Cannot initialize
[ 1.748791] ThumbEE CPU extension supported.
[ 1.753396] Registering SWP/SWPB emulation handler
[ 1.758421] SmartReflex Class3 initialized
[ 1.764038] omap_hsmmc 47810000.mmc: card claims to support voltages below defined range
[ 1.778738] omap-gpmc 50000000.gpmc: omap_device: omap_device_enable() called from invalid state 1
[ 1.788330] omap-gpmc 50000000.gpmc: use pm_runtime_put_sync_suspend() in driver?
[ 1.796265] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[ 1.801939] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[ 1.813067] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
[ 1.819934] nand: Micron MT29F2G08ABAEAWP
[ 1.824144] nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
[ 1.832203] nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme
[ 1.838097] 10 ofpart partitions found on MTD device 8000000.nand
[ 1.844531] Creating 10 MTD partitions on "8000000.nand":
[ 1.850242] 0x000000000000-0x000000020000 : "NAND.SPL"
[ 1.864561] 0x000000020000-0x000000040000 : "NAND.SPL.backup1"
[ 1.875983] 0x000000040000-0x000000060000 : "NAND.SPL.backup2"
[ 1.887439] 0x000000060000-0x000000080000 : "NAND.SPL.backup3"
[ 1.898545] 0x000000080000-0x0000000c0000 : "NAND.u-boot-spl-os"
[ 1.909708] random: fast init done
[ 1.917243] mmc0: new high speed SDIO card at address 0001
[ 1.929183] 0x0000000c0000-0x0000001c0000 : "NAND.u-boot"
[ 1.941324] 0x0000001c0000-0x0000001e0000 : "NAND.u-boot-env"
[ 1.951872] 0x0000001e0000-0x000000200000 : "NAND.u-boot-env.backup1"
[ 1.963047] 0x000000200000-0x000000a00000 : "NAND.kernel"
[ 1.976300] 0x000000a00000-0x000010000000 : "NAND.file-system"
[ 2.110733] tps65910 0-002d: No interrupt support, no core IRQ
[ 2.121219] vrtc: supplied by vbat
[ 2.131238] vio: supplied by vbat
[ 2.137933] vdd1: supplied by vbat
[ 2.145263] vdd2: supplied by vbat
[ 2.155614] vdig1: supplied by vbat
[ 2.162564] vdig2: supplied by vbat
[ 2.169254] vpll: supplied by vbat
[ 2.176017] vdac: supplied by vbat
[ 2.182717] vaux1: supplied by vbat
[ 2.189509] vaux2: supplied by vbat
[ 2.196300] vaux33: supplied by vbat
[ 2.203191] vmmc: supplied by vbat
[ 2.209980] vbb: supplied by vbat
[ 2.216430] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
[ 2.227018] omap_i2c 4802a000.i2c: bus 1 rev0.11 at 100 kHz
[ 2.234335] omap_hsmmc 48060000.mmc: Got CD GPIO
[ 2.302447] hctosys: unable to open rtc device (rtc0)
[ 2.307765] sr_init: No PMIC hook to init smartreflex
[ 2.313456] sr_init: platform driver register failed for SR
[ 2.350611] net eth0: initializing cpsw version 1.12 (0)
[ 2.450430] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=-1)
[ 2.463803] libphy: PHY 4a101000.mdio:01 not found
[ 2.468834] net eth0: phy "4a101000.mdio:01" not found on slave 1, err -19
[ 2.484836] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 2.499624] mmc1: host does not support reading read-only switch, assuming write-enable
[ 2.510945] mmc1: new high speed SDHC card at address aaaa
[ 2.520613] mmcblk1: mmc1:aaaa SU08G 7.40 GiB
[ 2.530180] mmcblk1: p1 p2 p3
[ 6.640484] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[ 6.659633] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 6.689483] Sending DHCP requests ., OK
[ 6.750215] IP-Config: Got DHCP answer from 192.168.1.254, my address is 192.168.1.190
[ 6.759281] IP-Config: Complete:
[ 6.762801] device=eth0, hwaddr=c8:a0:30:a1:c2:d7, ipaddr=192.168.1.190, mask=255.255.255.0, gw=192.168.1.254
[ 6.773684] host=192.168.1.190, domain=tidfarm-02.internal.ti.com, nis-domain=(none)
[ 6.782278] bootserver=192.168.1.254, rootserver=192.168.1.254, rootpath= nameserver0=192.0.2.2, nameserver1=192.0.2.3
[ 6.794660] lis3_reg: disabling
[ 6.797962] wlan-en-regulator: disabling
[ 6.837717] VFS: Mounted root (nfs filesystem) on device 0:14.
[ 6.846579] devtmpfs: mounted
[ 6.852447] Freeing unused kernel memory: 1024K (c0b00000 - c0c00000)
[ 7.402796] systemd[1]: System time before build time, advancing clock.
[ 7.613300] systemd[1]: systemd 229 running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN)
[ 7.634620] systemd[1]: Detected architecture arm.
Welcome to [1mArago 2016.07[0m!
[ 7.674036] systemd[1]: Set hostname to <am335x-evm>.
[ 8.901409] systemd[1]: Reached target Remote File Systems.
[[0;32m OK [0m] Reached target Remote File Systems.
[ 8.946707] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
[[0;32m OK [0m] Listening on /dev/initctl Compatibility Named Pipe.
[ 8.981758] systemd[1]: Listening on Journal Socket (/dev/log).
[[0;32m OK [0m] Listening on Journal Socket (/dev/log).
[ 9.021277] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[[0;32m OK [0m] Started Dispatch Password Requests to Console Directory Watch.
[ 9.059914] systemd[1]: Reached target Swap.
[[0;32m OK [0m] Reached target Swap.
[ 9.092890] systemd[1]: Listening on udev Control Socket.
[[0;32m OK [0m] Listening on udev Control Socket.
[ 9.131059] systemd[1]: Listening on Network Service Netlink Socket.
[[0;32m OK [0m] Listening on Network Service Netlink Socket.
[[0;32m OK [0m] Listening on Journal Audit Socket.
[[0;32m OK [0m] Listening on udev Kernel Socket.
[[0;32m OK [0m] Listening on Journal Socket.
[[0;32m OK [0m] Listening on Syslog Socket.
[[0;32m OK [0m] Created slice System Slice.
[[0;32m OK [0m] Created slice system-getty.slice.
Mounting Temporary Directory...
Starting Create list of required st... nodes for the current kernel...
Starting Setup Virtual Console...
Starting Remount Root and Kernel File Systems...
Starting Load Kernel Modules...
Mounting POSIX Message Queue File System...
Mounting Debug File System...
[[0;32m OK [0m] Created slice User and Session Slice.
[[0;32m OK [0m] Reached target Slices.
Starting Journal Service...
[[0;32m OK [0m] Started Forward Password Requests to Wall Directory Watch.
[[0;32m OK [0m] Reached target Paths.
[[0;32m OK [0m] Created slice system-serial\x2dgetty.slice.
[[0;32m OK [0m] Mounted Debug File System.
[[0;32m OK [0m] Mounted POSIX Message Queue File System.
[[0;32m OK [0m] Mounted Temporary Directory.
[[0;32m OK [0m] Started Create list of required sta...ce nodes for the current kernel.
[[0;32m OK [0m] Started Setup Virtual Console.
[[0;32m OK [0m] Started Remount Root and Kernel File Systems.
[[0;1;31mFAILED[0m] Failed to start Load Kernel Modules.
See 'systemctl status systemd-modules-load.service' for details.
[[0;32m OK [0m] Started Journal Service.
Mounting Configuration File System...
Starting Apply Kernel Variables...
Starting udev Coldplug all Devices...
Starting Flush Journal to Persistent Storage...
Starting Create Static Device Nodes in /dev...
[[0;32m OK [0m] Mounted Configuration File System.
[[0;32m OK [0m] Started Apply Kernel Variables.
[ 11.528911] systemd-journald[108]: Received request to flush runtime journal from PID 1
[[0;32m OK [0m] Started Flush Journal to Persistent Storage.
[[0;32m OK [0m] Started Create Static Device Nodes in /dev.
Starting udev Kernel Device Manager...
[[0;32m OK [0m] Reached target Local File Systems (Pre).
Mounting /var/volatile...
Mounting /media/ram...
[[0;32m OK [0m] Mounted /var/volatile.
[[0;32m OK [0m] Mounted /media/ram.
Starting Load/Save Random Seed...
[[0;32m OK [0m] Reached target Local File Systems.
Starting Create Volatile Files and Directories...
[[0;32m OK [0m] Started udev Kernel Device Manager.
[[0;32m OK [0m] Started Load/Save Random Seed.
[[0;32m OK [0m] Started Create Volatile Files and Directories.
Starting Update UTMP about System Boot/Shutdown...
Starting Network Time Synchronization...
[[0;32m OK [0m] Started Update UTMP about System Boot/Shutdown.
[ 14.259996] random: crng init done
[[0;32m OK [0m] Started Network Time Synchronization.
Starting Synchronize System and HW clocks...
[[0;32m OK [0m] Reached target System Time Synchronized.
[[0;1;31mFAILED[0m] Failed to start Synchronize System and HW clocks.
See 'systemctl status sync-clocks.service' for details.
[ 15.320043] backlight supply power not found, using dummy regulator
[ 15.495920] input: matrix_keypad at 0 as /devices/platform/matrix_keypad at 0/input/input0
[ 15.507099] backlight supply power not found, using dummy regulator
[ 15.896508] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
[ 15.905551] backlight supply power not found, using dummy regulator
[[0;32m OK [0m] Started udev Coldplug all Devices.
[ 15.984386] backlight supply power not found, using dummy regulator
[[0;32m OK [0m] Reached target System Initialization.
[ 16.070501] omap_rtc 44e3e000.rtc: rtc core: registered 44e3e000.rtc as rtc0
[[0;32m OK [0m] Listening on RPCbind Server Activation Socket.
[ 16.081234] backlight supply power not found, using dummy regulator
[[0;32m OK [0m] Listening on D-Bus System Message Bus Socket.
[ 16.245427] backlight supply power not found, using dummy regulator
[[0;32m OK [0m] Listening on dropbear.socket.
[[0;32m OK [0m] Reached target Sockets.
[[0;32m OK [0m] Reached target Basic System.
[[0;32m OK [0m] Started D-Bus System Message Bus.
[ 17.805752] tsl2550 1-0039: standard operating mode
[ 17.842234] tsl2550 1-0039: support ver. 1.2 enabled
[ 17.848683] backlight supply power not found, using dummy regulator
[ 17.886401] lis3lv02d: 16 bits lis331dlh sensor found
[ 18.050713] input: ST LIS3LV02DL Accelerometer as /devices/platform/lis3lv02d/input/input1
[ 18.121114] backlight supply power not found, using dummy regulator
[ 18.482681] backlight supply power not found, using dummy regulator
[ 18.654570] lm75 1-0048: hwmon0: sensor 'tmp275'
[ 18.661075] backlight supply power not found, using dummy regulator
[ 18.968529] omap_rng 48310000.rng: OMAP Random Number Generator ver. 20
[ 18.976964] backlight supply power not found, using dummy regulator
[ 19.201619] backlight supply power not found, using dummy regulator
[ 19.323419] backlight supply power not found, using dummy regulator
Starting Network Service...
Starting Login Service...
Starting Permit User Sessions...
[[0;32m OK [0m] Started System Logging Service.
Starting Print notice about GPLv3 packages...
Starting uim-sysfs.service...
[[0;32m OK [0m] Started Kernel Logging Service.
[[0;32m OK [0m] Started strongSwan IPsec IKEv1/IKEv2 daemon using ipsec.conf.
[[0;32m OK [0m] Started Daily Cleanup of Temporary Directories.
[[0;32m OK [0m] Reached target Timers.
[[0;32m OK [0m] Started Permit User Sessions.
[[0;32m OK [0m] Found device /dev/ttyO0.
[ 25.250490] input: volume_keys at 0 as /devices/platform/volume_keys at 0/input/input2
[ 25.808394] asoc-simple-card sound: tlv320aic3x-hifi <-> 4803c000.mcasp mapping ok
[[0;32m OK [0m] Started Network Service.
[ 30.220412] EXT4-fs (mmcblk1p2): mounting ext3 file system using the ext4 subsystem
[ 30.242502] EXT4-fs (mmcblk1p3): mounting ext3 file system using the ext4 subsystem
[ 30.474149] EXT4-fs (mmcblk1p2): warning: maximal mount count reached, running e2fsck is recommended
[ 30.488925] EXT4-fs (mmcblk1p3): warning: maximal mount count reached, running e2fsck is recommended
[ 30.654914] EXT4-fs (mmcblk1p3): mounted filesystem with ordered data mode. Opts: (null)
[ 30.668221] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. Opts: (null)
[ 30.732853] FAT-fs (mmcblk1p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[[0;32m OK [0m] Found device /dev/ttyS0.
[[0;32m OK [0m] Found device /dev/ttyS3.
[ 35.870145] Unable to handle kernel paging request at virtual address 00002244
[ 35.877743] pgd = c0004000
[ 35.880736] [00002244] *pgd=00000000
[ 35.884506] Internal error: Oops: 5 [#1] SMP ARM
[ 35.889346] Modules linked in: snd_soc_simple_card snd_soc_simple_card_utils gpio_keys evdev snd_soc_davinci_mcasp snd_soc_omap snd_soc_tlv320aic3x snd_soc_edma pwm_tiecap snd_soc_core omap_rng rng_core lm75 thermal_sys wlcore_sdio snd_pcm_dmaengine hwmon snd_pcm lis3lv02d_i2c tsl2550 lis3lv02d input_polldev snd_timer snd soundcore musb_am335x rtc_omap ti_am335x_tscadc omap_wdt matrix_keypad matrix_keymap pwm_bl autofs4
[ 35.928550] CPU: 0 PID: 172 Comm: kworker/u2:2 Not tainted 4.8.0-rc6-13910-g9395452 #1
[ 35.936842] Hardware name: Generic AM33XX (Flattened Device Tree)
[ 35.943250] Workqueue: events_unbound flush_to_ldisc
[ 35.948456] task: ed8aa0c0 task.stack: ed86c000
[ 35.953203] PC is at n_tty_receive_buf_common+0x48/0x9c8
[ 35.958775] LR is at __bfs+0x160/0x294
[ 35.962701] pc : [<c04fc740>] lr : [<c018e930>] psr: 80000013
[ 35.962701] sp : ed86de28 ip : 0000009a fp : edb9d400
[ 35.974725] r10: c0cbe740 r9 : c0c029cc r8 : ee814c24
[ 35.980196] r7 : ed9703c0 r6 : ee814c00 r5 : ee814c04 r4 : 00000000
[ 35.987033] r3 : 00002000 r2 : 00000000 r1 : 0000000e r0 : 00000001
[ 35.993871] Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
[ 36.001346] Control: 10c5387d Table: add68019 DAC: 00000051
[ 36.007364] Process kworker/u2:2 (pid: 172, stack limit = 0xed86c218)
[ 36.014111] Stack: (0xed86de28 to 0xed86e000)
[ 36.018678] de20: eda4ed18 00000100 eda4ec18 00000000 00000000 00002000
[ 36.027248] de40: 00000001 00000000 edb9d6c4 ee836c00 ee838f00 edb9d530 c0c029cc eda4ec00
[ 36.035818] de60: ee814c04 ee814c00 ed9703c0 ee814c24 c0c029cc c0cbe740 c0cbd983 c04fd0d4
[ 36.044388] de80: 00000001 ee814c04 ee814c00 c04ff954 eef17100 ee814c04 ee836c00 ee838f00
[ 36.052958] dea0: ed86dec8 c0154724 00000001 00000000 c015466c 00000008 00000000 00000000
[ 36.061527] dec0: c0154cac 00000088 c1491624 c0e1a2c4 00000000 c09dcc7c eef17100 ee836c00
[ 36.070097] dee0: eef17118 00000088 ee836c34 ed86c000 c0c02100 ee836c00 eef17100 c0154c38
[ 36.078666] df00: eefbcdc0 eef17100 c0154c00 00000000 eefbcdc0 eef17100 c0154c00 00000000
[ 36.087236] df20: 00000000 00000000 00000000 c015ac80 c0c029cc 00000000 00000000 eef17100
[ 36.095805] df40: 00000000 00000000 dead4ead ffffffff ffffffff c0cc4e74 00000000 00000000
[ 36.104376] df60: c099e8ec ed86df64 ed86df64 00000000 00000000 dead4ead ffffffff ffffffff
[ 36.112945] df80: c0cc4e74 00000000 00000000 c099e8ec ed86df90 ed86df90 eefbcdc0 eefbcdc0
[ 36.121514] dfa0: c015abac 00000000 00000000 c01078f0 00000000 00000000 00000000 00000000
[ 36.130084] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 36.138653] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
[ 36.147235] [<c04fc740>] (n_tty_receive_buf_common) from [<c04fd0d4>] (n_tty_receive_buf2+0x14/0x1c)
[ 36.156806] [<c04fd0d4>] (n_tty_receive_buf2) from [<c04ff954>] (flush_to_ldisc+0xc4/0xdc)
[ 36.165481] [<c04ff954>] (flush_to_ldisc) from [<c0154724>] (process_one_work+0x1e0/0x6bc)
[ 36.174146] [<c0154724>] (process_one_work) from [<c0154c38>] (worker_thread+0x38/0x4d0)
[ 36.182632] [<c0154c38>] (worker_thread) from [<c015ac80>] (kthread+0xd4/0xf0)
[ 36.190211] [<c015ac80>] (kthread) from [<c01078f0>] (ret_from_fork+0x14/0x24)
[ 36.197783] Code: e58d3014 e28b3fb1 e58d3020 e59d3014 (e5931244)
[ 36.204499] ---[ end trace d359ab6fc09c1b55 ]---
--
regards,
-grygorii
^ permalink raw reply
* [PATCH v3 2/2] atomic64: No need for CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
From: Vineet Gupta @ 2016-09-12 17:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473703083-8625-1-git-send-email-vgupta@synopsys.com>
This came to light when implementing native 64-bit atomics for ARCv2.
The atomic64 self-test code uses CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
to check whether atomic64_dec_if_positive() is available.
It seems it was needed when not every arch defined it.
However as of current code the Kconfig option seems needless
- for CONFIG_GENERIC_ATOMIC64 it is auto-enabled in lib/Kconfig and a
generic definition of API is present lib/atomic64.c
- arches with native 64-bit atomics select it in arch/*/Kconfig and
define the API in their headers
So I see no point in keeping the Kconfig option
Compile tested for:
- blackfin (CONFIG_GENERIC_ATOMIC64)
- x86 (!CONFIG_GENERIC_ATOMIC64)
- ia64
Cc: Richard Henderson <rth@twiddle.net>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
Cc: Helge Deller <deller@gmx.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Metcalf <cmetcalf@mellanox.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86 at kernel.org
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Matthew Wilcox <willy@linux.intel.com>
Cc: Alexander Potapenko <glider@google.com>
Cc: Andrey Ryabinin <aryabinin@virtuozzo.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: Ming Lin <ming.l@ssi.samsung.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Borislav Petkov <bp@suse.de>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: linux-alpha at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-mips at linux-mips.org
Cc: linux-parisc at vger.kernel.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-s390 at vger.kernel.org
Cc: sparclinux at vger.kernel.org
Cc: linux-snps-arc at lists.infradead.org
Cc: linux-arch at vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
---
arch/alpha/Kconfig | 1 -
arch/arm/Kconfig | 1 -
arch/arm64/Kconfig | 1 -
arch/mips/Kconfig | 1 -
arch/parisc/Kconfig | 1 -
arch/powerpc/Kconfig | 1 -
arch/s390/Kconfig | 1 -
arch/sparc/Kconfig | 1 -
arch/tile/Kconfig | 1 -
arch/x86/Kconfig | 1 -
lib/Kconfig | 3 ---
lib/atomic64_test.c | 4 ----
12 files changed, 17 deletions(-)
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 7f312d80b43b..0e49d39ea74a 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -15,7 +15,6 @@ config ALPHA
select GENERIC_IRQ_SHOW
select ARCH_WANT_IPC_PARSE_VERSION
select ARCH_HAVE_NMI_SAFE_CMPXCHG
- select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select AUDIT_ARCH
select GENERIC_CLOCKEVENTS
select GENERIC_SMP_IDLE_THREAD
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a9c4e48bb7ec..2a50957c7bfb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1,7 +1,6 @@
config ARM
bool
default y
- select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select ARCH_HAS_DEVMEM_IS_ALLOWED
select ARCH_HAS_ELF_RANDOMIZE
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index bc3f00f586f1..3df2ca7efbcc 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -6,7 +6,6 @@ config ARM64
select ACPI_MCFG if ACPI
select ARCH_HAS_DEVMEM_IS_ALLOWED
select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
- select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select ARCH_HAS_ELF_RANDOMIZE
select ARCH_HAS_GCOV_PROFILE_ALL
select ARCH_HAS_KCOV
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 26388562e300..5bbea197c220 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -30,7 +30,6 @@ config MIPS
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
select RTC_LIB if !MACH_LOONGSON64
select GENERIC_ATOMIC64 if !64BIT
- select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select HAVE_DMA_CONTIGUOUS
select HAVE_DMA_API_DEBUG
select GENERIC_IRQ_PROBE
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index af12c2db9bb8..8a96bdcc3807 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -14,7 +14,6 @@ config PARISC
select BUILDTIME_EXTABLE_SORT
select HAVE_PERF_EVENTS
select GENERIC_ATOMIC64 if !64BIT
- select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select BROKEN_RODATA
select GENERIC_IRQ_PROBE
select GENERIC_PCI_IOMAP
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 927d2ab2ce08..18d1b42cf545 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -113,7 +113,6 @@ config PPC
select HAVE_DEBUG_KMEMLEAK
select ARCH_HAS_SG_CHAIN
select GENERIC_ATOMIC64 if PPC32
- select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select HAVE_PERF_EVENTS
select HAVE_PERF_REGS
select HAVE_PERF_USER_STACK_DUMP
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index c109f073d454..d89d97ac83c4 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -67,7 +67,6 @@ config DEBUG_RODATA
config S390
def_bool y
- select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select ARCH_HAS_DEVMEM_IS_ALLOWED
select ARCH_HAS_ELF_RANDOMIZE
select ARCH_HAS_GCOV_PROFILE_ALL
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 59b09600dd32..bfedbe0cb7b2 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -22,7 +22,6 @@ config SPARC
select HAVE_ARCH_TRACEHOOK
select HAVE_EXIT_THREAD
select SYSCTL_EXCEPTION_TRACE
- select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select RTC_CLASS
select RTC_DRV_M48T59
select RTC_SYSTOHC
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 78da75b670bc..4583c0320059 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -3,7 +3,6 @@
config TILE
def_bool y
- select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select ARCH_HAS_DEVMEM_IS_ALLOWED
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select ARCH_WANT_FRAME_POINTERS
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 2a1f0ce7c59a..018076fcffcf 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -23,7 +23,6 @@ config X86
select ARCH_CLOCKSOURCE_DATA
select ARCH_DISCARD_MEMBLOCK
select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
- select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select ARCH_HAS_DEVMEM_IS_ALLOWED
select ARCH_HAS_ELF_RANDOMIZE
select ARCH_HAS_FAST_MULTIPLIER
diff --git a/lib/Kconfig b/lib/Kconfig
index d79909dc01ec..0e74df3c5441 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -457,9 +457,6 @@ config NLATTR
config GENERIC_ATOMIC64
bool
-config ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
- def_bool y if GENERIC_ATOMIC64
-
config LRU_CACHE
tristate
diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c
index dbb369145dda..46042901130f 100644
--- a/lib/atomic64_test.c
+++ b/lib/atomic64_test.c
@@ -213,7 +213,6 @@ static __init void test_atomic64(void)
r += one;
BUG_ON(v.counter != r);
-#ifdef CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
INIT(onestwos);
BUG_ON(atomic64_dec_if_positive(&v) != (onestwos - 1));
r -= one;
@@ -226,9 +225,6 @@ static __init void test_atomic64(void)
INIT(-one);
BUG_ON(atomic64_dec_if_positive(&v) != (-one - one));
BUG_ON(v.counter != r);
-#else
-#warning Please implement atomic64_dec_if_positive for your architecture and select the above Kconfig symbol
-#endif
INIT(onestwos);
BUG_ON(!atomic64_inc_not_zero(&v));
--
2.7.4
^ permalink raw reply related
* [PATCH v2 00/17] Make rpmsg a framework
From: Bjorn Andersson @ 2016-09-12 18:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160912165233.GB21885@linaro.org>
On Mon 12 Sep 09:52 PDT 2016, Lina Iyer wrote:
> Hi Bjorn,
>
> On Thu, Sep 01 2016 at 16:28 -0600, Bjorn Andersson wrote:
> >This series splits the virtio rpmsg bus driver into a rpmsg bus and a virtio
> >backend/wireformat.
> >
> >
> >As we discussed the Qualcomm SMD implementation a couple of years back people
> >suggested that I should make it "a rpmsg thingie". With the introduction of the
> >Qualcomm 8996 platform, we must support a variant of the communication
> >mechanism that share many of the characteristics of SMD, but are different
> >enough that it can't be done in a single implementation. As such there is
> >enough benefit to do the necessary work and being able to make SMD a "rpmsg
> >thingie".
> >
> >On-top of this series I have patches to switch the current smd clients over to
> >rpmsg (and by that drop the existing SMD implementation).
> >
> >All this allows me to implement the new backend and reuse all existing SMD
> >drivers with the new mechanism.
> >
>
> RPM Communication has to supported even when IRQs are disabled. The most
> important use of this communication is to set the wake up time for the
> CPU subsystem when all the CPUs are powered off.
Can you point me to the downstream code where this is implemented so I
can have a look? Do you expect to get the response on that request?
> In addition to that,
> "sleep" votes that are sent by the application processor subsystem to
> allow system to go into deep sleep modes can only be triggered when the
> CPU PM domains are power collapsed, drivers do not have a knowledge of
> when that happens.
Do you mean the actual sleep votes can only be with the CPU PM domains
collapsed?
It's been a while since I dug through that code, but there was several
cases where sleep votes would be sent out during normal execution as
well, and then there's the optimization of flushing out all cached sleep
votes when we're on the way down.
> This has to be done by a platform code that registers
> for CPU PM domain power_off/on callbacks.
>
Ok, sounds like we have a legit use case for improving this.
> Using rpmsg may be nice for RPM SMD communication, but mutexes need to
> go away for this driver to be any useful than bare bones active mode
> resource requests for QCOM SoCs. By not doing that now, we lock
> ourselves out of using this SMD driver in the near future when CPU PM
> domains are available in the kernel with an ability to do system low
> power modes.
>
The last time I looked at this there where no cases when it was
_required_ to support transmitting requests to the rpm from IRQ context.
iirc we could set up the sleep votes in normal context and the
transition was triggered through SAW(?)
> I hope you would make rpmsg work in IRQ disabled contexts first before
> porting the SMD driver.
>
There are two parts of this request;
The first is to be able to send data from irq context. The proposed
patches doesn't affect the implementation of send, so it's just a matter
of changing qcom_smd_send() and make the necessary adjustments in the
rpm driver.
In the event of the tx fifo being full we normally do want to sleep on
there being space, but if we switch to spinlocks you would be able to
issue an rpmsg_trysend() which would bypass this - and you can roll a
busy wait in the caller.
The other part is how to receive responses in this mode. Messages are
pulled off the fifo in IRQ context and delivered to the consumer in IRQ
context. But if you have irqs disabled then this wouldn't be triggered.
So if you need your responses we need to figure something out here. And
part of the ugliness of downstream is the need to drain the fifo just
enough before going to sleep, so that the RPM won't stall on a full
fifo.
Regards,
Bjorn
^ permalink raw reply
* [PATCH v2 1/2] pinctrl: meson-gxbb: add the missing SDIO interrupt pin
From: Kevin Hilman @ 2016-09-12 18:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160911123903.20027-2-martin.blumenstingl@googlemail.com>
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> This adds the SDIO interrupt pin which can be used by sd_emmc_a.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
>
> Fixes: 29885a656511 ("pinctrl: meson-gxbb: add the pins for the
> SDIO/sd_emmc_a controller")
Acked-by: Kevin Hilman <khilman@baylibre.com>
^ permalink raw reply
* [PATCH] dmaengine: cleanup with list_first_entry_or_null()
From: Masahiro Yamada @ 2016-09-12 18:08 UTC (permalink / raw)
To: linux-arm-kernel
The combo of list_empty() check and return list_first_entry()
can be replaced with list_first_entry_or_null().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/dma/coh901318.c | 22 ++++------------------
drivers/dma/ep93xx_dma.c | 6 ++----
drivers/dma/ste_dma40.c | 36 +++++-------------------------------
drivers/dma/virt-dma.h | 6 ++----
4 files changed, 13 insertions(+), 57 deletions(-)
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index e4acd63..a373eca 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -1553,15 +1553,8 @@ coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
static struct coh901318_desc *
coh901318_first_active_get(struct coh901318_chan *cohc)
{
- struct coh901318_desc *d;
-
- if (list_empty(&cohc->active))
- return NULL;
-
- d = list_first_entry(&cohc->active,
- struct coh901318_desc,
- node);
- return d;
+ return list_first_entry_or_null(&cohc->active, struct coh901318_desc,
+ node);
}
static void
@@ -1579,15 +1572,8 @@ coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
static struct coh901318_desc *
coh901318_first_queued(struct coh901318_chan *cohc)
{
- struct coh901318_desc *d;
-
- if (list_empty(&cohc->queue))
- return NULL;
-
- d = list_first_entry(&cohc->queue,
- struct coh901318_desc,
- node);
- return d;
+ return list_first_entry_or_null(&cohc->queue, struct coh901318_desc,
+ node);
}
static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index 21f08cc..2ffaca2 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -262,10 +262,8 @@ static void ep93xx_dma_set_active(struct ep93xx_dma_chan *edmac,
static struct ep93xx_dma_desc *
ep93xx_dma_get_active(struct ep93xx_dma_chan *edmac)
{
- if (list_empty(&edmac->active))
- return NULL;
-
- return list_first_entry(&edmac->active, struct ep93xx_dma_desc, node);
+ return list_first_entry_or_null(&edmac->active,
+ struct ep93xx_dma_desc, node);
}
/**
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 8b18e44..e43d2bb 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -941,15 +941,7 @@ static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
{
- struct d40_desc *d;
-
- if (list_empty(&d40c->active))
- return NULL;
-
- d = list_first_entry(&d40c->active,
- struct d40_desc,
- node);
- return d;
+ return list_first_entry_or_null(&d40c->active, struct d40_desc, node);
}
/* remove desc from current queue and add it to the pending_queue */
@@ -962,36 +954,18 @@ static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
{
- struct d40_desc *d;
-
- if (list_empty(&d40c->pending_queue))
- return NULL;
-
- d = list_first_entry(&d40c->pending_queue,
- struct d40_desc,
- node);
- return d;
+ return list_first_entry_or_null(&d40c->pending_queue, struct d40_desc,
+ node);
}
static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
{
- struct d40_desc *d;
-
- if (list_empty(&d40c->queue))
- return NULL;
-
- d = list_first_entry(&d40c->queue,
- struct d40_desc,
- node);
- return d;
+ return list_first_entry_or_null(&d40c->queue, struct d40_desc, node);
}
static struct d40_desc *d40_first_done(struct d40_chan *d40c)
{
- if (list_empty(&d40c->done))
- return NULL;
-
- return list_first_entry(&d40c->done, struct d40_desc, node);
+ return list_first_entry_or_null(&d40c->done, struct d40_desc, node);
}
static int d40_psize_2_burst_size(bool is_log, int psize)
diff --git a/drivers/dma/virt-dma.h b/drivers/dma/virt-dma.h
index d9731ca..a030ae7 100644
--- a/drivers/dma/virt-dma.h
+++ b/drivers/dma/virt-dma.h
@@ -123,10 +123,8 @@ static inline void vchan_cyclic_callback(struct virt_dma_desc *vd)
*/
static inline struct virt_dma_desc *vchan_next_desc(struct virt_dma_chan *vc)
{
- if (list_empty(&vc->desc_issued))
- return NULL;
-
- return list_first_entry(&vc->desc_issued, struct virt_dma_desc, node);
+ return list_first_entry_or_null(&vc->desc_issued,
+ struct virt_dma_desc, node);
}
/**
--
1.9.1
^ permalink raw reply related
* [PATCH v5 0/5] dts: sun8i-h3: complete UART I2C for H3
From: jorik at kippendief.biz @ 2016-09-12 18:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Jorik Jonker <jorik@kippendief.biz>
This is my fifth attempt to complete the UART/I2C definitions on H3.
Many thanks to Maxime and Chen-Yu for helping me understand the
philosophy behind the DTS/DTSI structure. I hope I get it and five
times is a charm :-)
Changes since v4:
* RTS/CTS for UART1 is split off in seperate pinmux to make uart1-3
consistent.
* UART0 is left untouched
* UARTs 1-3 are associated and re-disabled in DTS instead of DTSI
Best,
Jorik
Jorik Jonker (5):
dts: sun8i-h3: add pinmux definitions for UART2-3
dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux
dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards
dts: sun8i-h3: add pinmux definitions for I2C0-2
dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 2 +-
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 18 ++++++
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 18 ++++++
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 18 ++++++
arch/arm/boot/dts/sun8i-h3.dtsi | 85 ++++++++++++++++++++++++-
5 files changed, 138 insertions(+), 3 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v5 1/5] dts: sun8i-h3: add pinmux definitions for UART2-3
From: jorik at kippendief.biz @ 2016-09-12 18:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473703967-21356-1-git-send-email-jorik@kippendief.biz>
From: Jorik Jonker <jorik@kippendief.biz>
These are the pinmux definitions for UART2-3 on H3. These UARTs can only
be muxed to these pins, so _a and @0 do not really make sense. I have
left out RTS/CTS, since these are rarely used. These can easily be
enabled using an additional pinmux set.
Signed-off-by: Jorik Jonker <jorik@kippendief.biz>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index fdf9fdb..665fa32 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -373,6 +373,20 @@
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ uart2_pins: uart2 {
+ allwinner,pins = "PA0", "PA1";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins: uart3 {
+ allwinner,pins = "PG13", "PG14";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
timer at 01c20c00 {
--
2.7.4
^ permalink raw reply related
* [PATCH v5 2/5] dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux
From: jorik at kippendief.biz @ 2016-09-12 18:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473703967-21356-1-git-send-email-jorik@kippendief.biz>
From: Jorik Jonker <jorik@kippendief.biz>
This was done to make UART1-3 on H3 consistent, and less complicated to
enable UART1-3 on the breakout header on the several H3 board (notably
Orange Pi's). This patch adds a bit of complexity for the existing Banana
Pi, which already had the RTS/CTS associated on UART1.
The RTS/CTS for UART2-3 could be defined in the same way, but since
there is no actual use case for them at the moment, they are left out.
Signed-off-by: Jorik Jonker <jorik@kippendief.biz>
---
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 2 +-
arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++++++++--
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index f3b1d5f..06fddaa 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -185,7 +185,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_a>;
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 665fa32..742bced 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -367,8 +367,15 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
- uart1_pins_a: uart1 at 0 {
- allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+ uart1_pins: uart1 {
+ allwinner,pins = "PG6", "PG7";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_rts_cts_pins: uart1_rts_cts {
+ allwinner,pins = "PG8", "PG9";
allwinner,function = "uart1";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
--
2.7.4
^ permalink raw reply related
* [PATCH v5 3/5] dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards
From: jorik at kippendief.biz @ 2016-09-12 18:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473703967-21356-1-git-send-email-jorik@kippendief.biz>
From: Jorik Jonker <jorik@kippendief.biz>
These H3 boards all expose UART1-3 on their expansion header. Since
other functions can be muxed to these pins, they are explicitly
disabled. To enable them, one could use DT overlays or U-boot commands:
=> fdt set /soc/serial at 01c28c00 status okay
Signed-off-by: Jorik Jonker <jorik@kippendief.biz>
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 18 ++++++++++++++++++
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 18 ++++++++++++++++++
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 18 ++++++++++++++++++
3 files changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index f93f5d1..9aa2bb7 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -176,6 +176,24 @@
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ status = "disabled";
+};
+
&usb1_vbus_pin_a {
allwinner,pins = "PG13";
};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 0adf932..5c9b5bf 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -139,6 +139,24 @@
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ status = "disabled";
+};
+
&usbphy {
/* USB VBUS is always on */
status = "okay";
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index daf50b9..3ec9712 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -161,6 +161,24 @@
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ status = "disabled";
+};
+
&usbphy {
/* USB VBUS is always on */
status = "okay";
--
2.7.4
^ permalink raw reply related
* [PATCH v5 4/5] dts: sun8i-h3: add pinmux definitions for I2C0-2
From: jorik at kippendief.biz @ 2016-09-12 18:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473703967-21356-1-git-send-email-jorik@kippendief.biz>
From: Jorik Jonker <jorik@kippendief.biz>
These are the only possible pins for these peripherals according to the
datasheet.
Signed-off-by: Jorik Jonker <jorik@kippendief.biz>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 742bced..ed6628d 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -327,6 +327,27 @@
interrupt-controller;
#interrupt-cells = <3>;
+ i2c0_pins: i2c0 {
+ allwinner,pins = "PA11", "PA12";
+ allwinner,function = "i2c0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c1_pins: i2c1 {
+ allwinner,pins = "PA18", "PA19";
+ allwinner,function = "i2c1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c2_pins: i2c2 {
+ allwinner,pins = "PE12", "PE13";
+ allwinner,function = "i2c2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc0_pins_a: mmc0 at 0 {
allwinner,pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
--
2.7.4
^ permalink raw reply related
* [PATCH v5 5/5] dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC
From: jorik at kippendief.biz @ 2016-09-12 18:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473703967-21356-1-git-send-email-jorik@kippendief.biz>
From: Jorik Jonker <jorik@kippendief.biz>
These peripherals can only be muxed to these pins, so they are
associated in the DTSI instead of the board files. This makes it very
easy to enable them using overlays or u-boot commands:
=> fdt set /soc/i2c at 01c2ac00 status okay
Signed-off-by: Jorik Jonker <jorik@kippendief.biz>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index ed6628d..bfc9200 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -483,6 +483,45 @@
status = "disabled";
};
+ i2c0: i2c at 01c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c at 01c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c at 01c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
gic: interrupt-controller at 01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
--
2.7.4
^ permalink raw reply related
* [PATCH v2 00/17] Make rpmsg a framework
From: Jeffrey Hugo @ 2016-09-12 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160912180015.GH405@tuxbot>
On 9/12/2016 12:00 PM, Bjorn Andersson wrote:
> On Mon 12 Sep 09:52 PDT 2016, Lina Iyer wrote:
>
>> Hi Bjorn,
>>
>> On Thu, Sep 01 2016 at 16:28 -0600, Bjorn Andersson wrote:
>>> This series splits the virtio rpmsg bus driver into a rpmsg bus and a virtio
>>> backend/wireformat.
>>>
>>>
>>> As we discussed the Qualcomm SMD implementation a couple of years back people
>>> suggested that I should make it "a rpmsg thingie". With the introduction of the
>>> Qualcomm 8996 platform, we must support a variant of the communication
>>> mechanism that share many of the characteristics of SMD, but are different
>>> enough that it can't be done in a single implementation. As such there is
>>> enough benefit to do the necessary work and being able to make SMD a "rpmsg
>>> thingie".
>>>
>>> On-top of this series I have patches to switch the current smd clients over to
>>> rpmsg (and by that drop the existing SMD implementation).
>>>
>>> All this allows me to implement the new backend and reuse all existing SMD
>>> drivers with the new mechanism.
>>>
>>
>> RPM Communication has to supported even when IRQs are disabled. The most
>> important use of this communication is to set the wake up time for the
>> CPU subsystem when all the CPUs are powered off.
>
> Can you point me to the downstream code where this is implemented so I
> can have a look? Do you expect to get the response on that request?
Have a look at -
smd_mask_receive_interrupt()
smd_is_pkt_avail()
Every request to the RPM generates a response. The Linux RPM driver may
decide to let the response sit in the fifo, or it may need to read and
process it.
>
>> In addition to that,
>> "sleep" votes that are sent by the application processor subsystem to
>> allow system to go into deep sleep modes can only be triggered when the
>> CPU PM domains are power collapsed, drivers do not have a knowledge of
>> when that happens.
>
> Do you mean the actual sleep votes can only be with the CPU PM domains
> collapsed?
>
> It's been a while since I dug through that code, but there was several
> cases where sleep votes would be sent out during normal execution as
> well, and then there's the optimization of flushing out all cached sleep
> votes when we're on the way down.
>
>> This has to be done by a platform code that registers
>> for CPU PM domain power_off/on callbacks.
>>
>
> Ok, sounds like we have a legit use case for improving this.
>
>> Using rpmsg may be nice for RPM SMD communication, but mutexes need to
>> go away for this driver to be any useful than bare bones active mode
>> resource requests for QCOM SoCs. By not doing that now, we lock
>> ourselves out of using this SMD driver in the near future when CPU PM
>> domains are available in the kernel with an ability to do system low
>> power modes.
>>
>
> The last time I looked at this there where no cases when it was
> _required_ to support transmitting requests to the rpm from IRQ context.
I no longer work on SMD, but when I did this was in fact a strict
requirement. If I recall correctly, there was a parameter in the RPM
driver for the transmit function that indicated if the request was being
made in atomic context or not, which would change the behavior of how
the transmit was handled.
>
> iirc we could set up the sleep votes in normal context and the
> transition was triggered through SAW(?)
>
>> I hope you would make rpmsg work in IRQ disabled contexts first before
>> porting the SMD driver.
>>
>
> There are two parts of this request;
>
> The first is to be able to send data from irq context. The proposed
> patches doesn't affect the implementation of send, so it's just a matter
> of changing qcom_smd_send() and make the necessary adjustments in the
> rpm driver.
>
> In the event of the tx fifo being full we normally do want to sleep on
> there being space, but if we switch to spinlocks you would be able to
> issue an rpmsg_trysend() which would bypass this - and you can roll a
> busy wait in the caller.
>
>
>
> The other part is how to receive responses in this mode. Messages are
> pulled off the fifo in IRQ context and delivered to the consumer in IRQ
> context. But if you have irqs disabled then this wouldn't be triggered.
>
> So if you need your responses we need to figure something out here. And
> part of the ugliness of downstream is the need to drain the fifo just
> enough before going to sleep, so that the RPM won't stall on a full
> fifo.
>
> Regards,
> Bjorn
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH v2 2/2] ARM64: dts: meson-gxbb: add the SDIO pins
From: Kevin Hilman @ 2016-09-12 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160911123903.20027-3-martin.blumenstingl@googlemail.com>
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> From: Neil Armstrong <narmstrong@baylibre.com>
>
> This is used to configure the pins of the sd_emmc_a controller to
> which an SDIO module is connected (when available).
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Applied,
Kevin
^ permalink raw reply
* [PATCH 4/9] mtd: nand: Add function to convert ONFI mode to data_interface
From: Boris Brezillon @ 2016-09-12 18:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160912063511.flb3se54dy4itlru@pengutronix.de>
On Mon, 12 Sep 2016 08:35:11 +0200
Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Fri, Sep 09, 2016 at 02:35:22PM +0200, Boris Brezillon wrote:
> > On Fri, 9 Sep 2016 14:05:07 +0200
> > Sascha Hauer <s.hauer@pengutronix.de> wrote:
> >
> > > onfi_init_data_interface() initializes a data interface with
> > > values from a given ONFI mode.
> > >
> > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > ---
> > > drivers/mtd/nand/nand_timings.c | 16 ++++++++++++++++
> > > include/linux/mtd/nand.h | 2 ++
> > > 2 files changed, 18 insertions(+)
> > >
> > > diff --git a/drivers/mtd/nand/nand_timings.c b/drivers/mtd/nand/nand_timings.c
> > > index 9af2ebc..ece4ff2 100644
> > > --- a/drivers/mtd/nand/nand_timings.c
> > > +++ b/drivers/mtd/nand/nand_timings.c
> > > @@ -269,3 +269,19 @@ const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode)
> > > return &onfi_sdr_timings[mode].timings.sdr;
> > > }
> > > EXPORT_SYMBOL(onfi_async_timing_mode_to_sdr_timings);
> > > +
> > > +/**
> > > + * onfi_init_data_interface - [NAND Interface] Initialize a data interface from
> > > + * given ONFI mode
> > > + * @iface: The data interface to be initialized
> > > + * @mode: The ONFI timing mode
> > > + */
> > > +int onfi_init_data_interface(struct nand_data_interface *iface, int mode)
> >
> > Can we choose a more future proof prototype (like the one I suggested)
> > for this function. Passing the nand_chip will later allow to extract
> > extended timings (tR, tPROG, tCCS, ...) from the param page, and
> > passing the interface type makes it compatible with DDR mode.
>
> Ok, will change as you suggested to:
>
> int onfi_init_data_interface(struct nand_chip *chip,
> struct nand_data_interface *iface,
> enum nand_data_interface_type type,
> int timing_mode)
>
> Before I send another round: Are the other patches ok?
Yes.
^ permalink raw reply
* [PATCH v2 2/6] ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.
From: Stefan Wahren @ 2016-09-12 18:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473668576-22256-3-git-send-email-kraxel@redhat.com>
Hi Gerd,
> Gerd Hoffmann <kraxel@redhat.com> hat am 12. September 2016 um 10:22
> geschrieben:
>
>
> From: Eric Anholt <eric@anholt.net>
>
> The BCM2835-ARM-Peripherals.pdf documentation specifies what the
> function selects do for the pins, and there are a bunch of obvious
> groupings to be made. With these created, we'll be able to replace
> bcm2835-rpi.dtsi's main "set all of these pins to alt0" with
> references to specific groups we want enabled.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
>
> squashed in:
> ARM: dts: bcm283x: Add the emmc pin group to bcm283x.dtsi.
> ARM: dts: bcm283x: Add a group for mapping pins 48-53 to sdhost.
> ARM: dts: bcm283x: Add a new EMMC pin group from the downstream tree.
>
> fixups by kraxel:
> * fix spi0 name
> * sort & group entries
> * use pull defines
> * add dpi group
this looks like a changelog. Please move this at the proper place before the
first "diff" and specify the version.
>
> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> ---
> arch/arm/boot/dts/bcm283x.dtsi | 203
> +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 203 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
> index 4d9f3ab..7b03b63 100644
> --- a/arch/arm/boot/dts/bcm283x.dtsi
> +++ b/arch/arm/boot/dts/bcm283x.dtsi
> @@ -131,6 +131,209 @@
>
> interrupt-controller;
> #interrupt-cells = <2>;
> +
> + /* Defines pin muxing groups according to
> + * BCM2835-ARM-Peripherals.pdf page 102.
> + *
> + * While each pin can have its mux selected
> + * for various functions individually, some
> + * groups only make sense to switch to a
> + * particular function together.
> + */
> + dpi_gpio4: dpi_gpio4 {
> + brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
> + 12 13 14 15 16 17 18 19
> + 20 21 22 23 24 25 26 27>;
> + brcm,function = <BCM2835_FSEL_ALT2>;
> + };
s/dpi_gpio4/dpi_gpio0
> + emmc_gpio22: emmc_gpio22 {
> + brcm,pins = <22 23 24 25 26 27>;
> + brcm,function = <BCM2835_FSEL_ALT3>;
> + };
> + emmc_gpio34: emmc_gpio34 {
> + brcm,pins = <34 35 36 37 38 39>;
> + brcm,function = <BCM2835_FSEL_ALT3>;
> + brcm,pull = <BCM2835_PUD_OFF
> + BCM2835_PUD_UP
> + BCM2835_PUD_UP
> + BCM2835_PUD_UP
> + BCM2835_PUD_UP
> + BCM2835_PUD_UP>;
> + };
> + emmc_gpio48: emmc_gpio48 {
> + brcm,pins = <48 49 50 51 52 53>;
> + brcm,function = <BCM2835_FSEL_ALT3>;
> + };
Sorry, i didn't notice this before. The naming of these groups suggest 3 muxes
for the same eMMC interface. I thought there is a eMMC interface and a SD host
interface with different DMA channels.
> +
> ...
> +
> + sdhost_gpio48: sdhost_gpio48 {
> + brcm,pins = <48 49 50 51 52 53>;
> + brcm,function = <BCM2835_FSEL_ALT0>;
> + };
I think this incorrect. There is no function ALT0 for these pins, only ALT3.
Regards
Stefan
^ permalink raw reply
* [PATCH v3] arm64: Improve kprobes test for atomic sequence
From: David Long @ 2016-09-12 18:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160913012936.489d3dc7a0b5a9e0f0670745@kernel.org>
On 09/12/2016 12:29 PM, Masami Hiramatsu wrote:
> On Sun, 11 Sep 2016 21:53:43 -0400
> David Long <dave.long@linaro.org> wrote:
>
>> On 09/10/2016 01:48 AM, Masami Hiramatsu wrote:
>>> On Fri, 9 Sep 2016 15:26:09 -0400
>>> David Long <dave.long@linaro.org> wrote:
>>>
>>>> From: "David A. Long" <dave.long@linaro.org>
>>>>
>>>> Kprobes searches backwards a finite number of instructions to determine if
>>>> there is an attempt to probe a load/store exclusive sequence. It stops when
>>>> it hits the maximum number of instructions or a load or store exclusive.
>>>> However this means it can run up past the beginning of the function and
>>>> start looking at literal constants. This has been shown to cause a false
>>>> positive and blocks insertion of the probe. To fix this, further limit the
>>>> backwards search to stop if it hits a symbol address from kallsyms. The
>>>> presumption is that this is the entry point to this code (particularly for
>>>> the common case of placing probes at the beginning of functions).
>>>>
>>>> This also improves efficiency by not searching code that is not part of the
>>>> function. There may be some possibility that the label might not denote the
>>>> entry path to the probed instruction but the likelihood seems low and this
>>>> is just another example of how the kprobes user really needs to be
>>>> careful about what they are doing.
>>>
>>> Of course user should be careful, but also, in such case, kernel can reject
>>> to probe it.
>>>
>>
>> I'm not exactly sure what you mean. I'm just saying when everything
>> goes right we still cannot promise perfection in detecting a probe
>> within an atomic sequence. This patch will reject a probe that is after
>> a ldx and has no intervening kallsyms label (and assuming it's within
>> the defined maximum count of subsequent instructions).
>>
>
> Hmm, what I meant was the below code.
>
>>>> + /*
>>>> + * If there's a symbol defined in front of and near enough to
>>>> + * the probe address assume it is the entry point to this
>>>> + * code and use it to further limit how far back we search
>>>> + * when determining if we're in an atomic sequence. If we could
>>>> + * not find any symbol skip the atomic test altogether as we
>>>> + * could otherwise end up searching irrelevant text/literals.
>>>> + * KPROBES depends on KALLSYMS so this last case should never
>>>> + * happen.
>>>> + */
>>>> + if (kallsyms_lookup_size_offset((unsigned long) addr, &size, &offset)) {
>>>> + if (offset < (MAX_ATOMIC_CONTEXT_SIZE*sizeof(kprobe_opcode_t)))
>>>> + scan_end = addr - (offset / sizeof(kprobe_opcode_t));
>>>> + else
>>>> + scan_end = addr - MAX_ATOMIC_CONTEXT_SIZE;
>>>
>>> } else
>>> return INSN_REJECTED;
>>>
>>> that is what I expected...
>
> As you said above,
>
>>>> + * KPROBES depends on KALLSYMS so this last case should never
>>>> + * happen.
>
> If it should never happen, it also would be better to reject it because
> it is unexpected result.
>
> Thank you,
>
OK, cool. Sounds like we're on the same page.
-dl
^ permalink raw reply
* [PATCH v4] arm64: Improve kprobes test for atomic sequence
From: David Long @ 2016-09-12 18:21 UTC (permalink / raw)
To: linux-arm-kernel
From: "David A. Long" <dave.long@linaro.org>
Kprobes searches backwards a finite number of instructions to determine if
there is an attempt to probe a load/store exclusive sequence. It stops when
it hits the maximum number of instructions or a load or store exclusive.
However this means it can run up past the beginning of the function and
start looking at literal constants. This has been shown to cause a false
positive and blocks insertion of the probe. To fix this, further limit the
backwards search to stop if it hits a symbol address from kallsyms. The
presumption is that this is the entry point to this code (particularly for
the common case of placing probes at the beginning of functions).
This also improves efficiency by not searching code that is not part of the
function. There may be some possibility that the label might not denote the
entry path to the probed instruction but the likelihood seems low and this
is just another example of how the kprobes user really needs to be
careful about what they are doing.
Signed-off-by: David A. Long <dave.long@linaro.org>
---
arch/arm64/kernel/probes/decode-insn.c | 48 ++++++++++++++++------------------
1 file changed, 23 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/kernel/probes/decode-insn.c b/arch/arm64/kernel/probes/decode-insn.c
index 37e47a9..d1731bf 100644
--- a/arch/arm64/kernel/probes/decode-insn.c
+++ b/arch/arm64/kernel/probes/decode-insn.c
@@ -16,6 +16,7 @@
#include <linux/kernel.h>
#include <linux/kprobes.h>
#include <linux/module.h>
+#include <linux/kallsyms.h>
#include <asm/kprobes.h>
#include <asm/insn.h>
#include <asm/sections.h>
@@ -122,7 +123,7 @@ arm_probe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
static bool __kprobes
is_probed_address_atomic(kprobe_opcode_t *scan_start, kprobe_opcode_t *scan_end)
{
- while (scan_start > scan_end) {
+ while (scan_start >= scan_end) {
/*
* atomic region starts from exclusive load and ends with
* exclusive store.
@@ -142,33 +143,30 @@ arm_kprobe_decode_insn(kprobe_opcode_t *addr, struct arch_specific_insn *asi)
{
enum kprobe_insn decoded;
kprobe_opcode_t insn = le32_to_cpu(*addr);
- kprobe_opcode_t *scan_start = addr - 1;
- kprobe_opcode_t *scan_end = addr - MAX_ATOMIC_CONTEXT_SIZE;
-#if defined(CONFIG_MODULES) && defined(MODULES_VADDR)
- struct module *mod;
-#endif
-
- if (addr >= (kprobe_opcode_t *)_text &&
- scan_end < (kprobe_opcode_t *)_text)
- scan_end = (kprobe_opcode_t *)_text;
-#if defined(CONFIG_MODULES) && defined(MODULES_VADDR)
- else {
- preempt_disable();
- mod = __module_address((unsigned long)addr);
- if (mod && within_module_init((unsigned long)addr, mod) &&
- !within_module_init((unsigned long)scan_end, mod))
- scan_end = (kprobe_opcode_t *)mod->init_layout.base;
- else if (mod && within_module_core((unsigned long)addr, mod) &&
- !within_module_core((unsigned long)scan_end, mod))
- scan_end = (kprobe_opcode_t *)mod->core_layout.base;
- preempt_enable();
+ kprobe_opcode_t *scan_end = NULL;
+ unsigned long size = 0, offset = 0;
+
+ /*
+ * If there's a symbol defined in front of and near enough to
+ * the probe address assume it is the entry point to this
+ * code and use it to further limit how far back we search
+ * when determining if we're in an atomic sequence. If we could
+ * not find any symbol skip the atomic test altogether as we
+ * could otherwise end up searching irrelevant text/literals.
+ * KPROBES depends on KALLSYMS so this last case should never
+ * happen.
+ */
+ if (kallsyms_lookup_size_offset((unsigned long) addr, &size, &offset)) {
+ if (offset < (MAX_ATOMIC_CONTEXT_SIZE*sizeof(kprobe_opcode_t)))
+ scan_end = addr - (offset / sizeof(kprobe_opcode_t));
+ else
+ scan_end = addr - MAX_ATOMIC_CONTEXT_SIZE;
}
-#endif
decoded = arm_probe_decode_insn(insn, asi);
- if (decoded == INSN_REJECTED ||
- is_probed_address_atomic(scan_start, scan_end))
- return INSN_REJECTED;
+ if (decoded != INSN_REJECTED && scan_end)
+ if (is_probed_address_atomic(addr - 1, scan_end))
+ return INSN_REJECTED;
return decoded;
}
--
2.5.0
^ permalink raw reply related
* [PATCH v2 1/3] Documentation: dtb: xgene: Add PMD clock binding
From: Hoan Tran @ 2016-09-12 18:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160912153703.GA26444@rob-hp-laptop>
On Mon, Sep 12, 2016 at 8:37 AM, Rob Herring <robh@kernel.org> wrote:
> On Fri, Sep 02, 2016 at 05:40:53PM -0700, Hoan Tran wrote:
>> Add APM X-Gene clock binding documentation for PMD clock.
>>
>> Signed-off-by: Hoan Tran <hotran@apm.com>
>> ---
>> Documentation/devicetree/bindings/clock/xgene.txt | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/xgene.txt b/Documentation/devicetree/bindings/clock/xgene.txt
>> index 82f9638..e6e12ae 100644
>> --- a/Documentation/devicetree/bindings/clock/xgene.txt
>> +++ b/Documentation/devicetree/bindings/clock/xgene.txt
>> @@ -8,6 +8,7 @@ Required properties:
>> - compatible : shall be one of the following:
>> "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
>> "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
>> + "apm,xgene-pmd-clock" - for a X-Gene PMD clock
>> "apm,xgene-device-clock" - for a X-Gene device clock
>> "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
>> "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
>> @@ -22,6 +23,15 @@ Required properties for SoC or PCP PLL clocks:
>> Optional properties for PLL clocks:
>> - clock-names : shall be the name of the PLL. If missing, use the device name.
>>
>> +Required properties for PMD clocks:
>> +- reg : shall be the physical register address for the pmd clock.
>> +- clocks : shall be the input parent clock phandle for the clock.
>> +- #clock-cells : shall be set to 1.
>> +- clock-output-names : shall be the name of the clock referenced by derive
>> + clock.
>> +Optional properties for PLL clocks:
>> +- clock-names : shall be the name of the clock. If missing, use the device name.
>> +
>> Required properties for device clocks:
>> - reg : shall be a list of address and length pairs describing the CSR
>> reset and/or the divider. Either may be omitted, but at least
>> @@ -59,6 +69,14 @@ For example:
>> type = <0>;
>> };
>>
>> + pmd0clk: pmd0clk {
>
> Needs a unit address.
>
>> + compatible = "apm,xgene-pmd-clock";
>> + #clock-cells = <1>;
>> + clocks = <&pmdpll 0>;
>> + reg = <0x0 0x7E200200 0x0 0x10>;
>
> Lowercase hex please.
>
> With those,
>
> Acked-by: Rob Herring <robh@kernel.org>
Thanks, Rob ! I'll send another version soon.
Regards
Hoan
>
>
>> + clock-output-names = "pmd0clk";
>> + };
>> +
>> socpll: socpll at 17000120 {
>> compatible = "apm,xgene-socpll-clock";
>> #clock-cells = <1>;
>> --
>> 1.9.1
>>
^ permalink raw reply
* [PATCH v3 0/3] clk: xgene: Add PMD clock support
From: Hoan Tran @ 2016-09-12 18:23 UTC (permalink / raw)
To: linux-arm-kernel
Add X-Gene PMD clock support.
PMD clock is implemented for a single register field.
Output rate = parent_rate * (denominator - scale) / denominator
with
- denominator = bitmask of register field + 1
- scale = value of register field
For example, for bitmask is 0x7, denominator will be 8 and scale
will be computed and programmed accordingly.
v3
* Minor changes on dt binding document.
v2
* Imply clock shift and width by the compatible string as Rob's comments
v1
* Initial
Hoan Tran (3):
Documentation: dtb: xgene: Add PMD clock binding
clk: xgene: Add PMD clock
arm64: dts: xgene: Add DT node for APM X-Gene 2 CPU clocks
Documentation/devicetree/bindings/clock/xgene.txt | 18 ++
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 56 ++++++
drivers/clk/clk-xgene.c | 221 ++++++++++++++++++++++
3 files changed, 295 insertions(+)
--
1.9.1
^ permalink raw reply
* [PATCH v3 1/3] Documentation: dtb: xgene: Add PMD clock binding
From: Hoan Tran @ 2016-09-12 18:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473704605-28126-1-git-send-email-hotran@apm.com>
Add APM X-Gene clock binding documentation for PMD clock.
Signed-off-by: Hoan Tran <hotran@apm.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/clock/xgene.txt | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/xgene.txt b/Documentation/devicetree/bindings/clock/xgene.txt
index 82f9638..8233e77 100644
--- a/Documentation/devicetree/bindings/clock/xgene.txt
+++ b/Documentation/devicetree/bindings/clock/xgene.txt
@@ -8,6 +8,7 @@ Required properties:
- compatible : shall be one of the following:
"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
+ "apm,xgene-pmd-clock" - for a X-Gene PMD clock
"apm,xgene-device-clock" - for a X-Gene device clock
"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
@@ -22,6 +23,15 @@ Required properties for SoC or PCP PLL clocks:
Optional properties for PLL clocks:
- clock-names : shall be the name of the PLL. If missing, use the device name.
+Required properties for PMD clocks:
+- reg : shall be the physical register address for the pmd clock.
+- clocks : shall be the input parent clock phandle for the clock.
+- #clock-cells : shall be set to 1.
+- clock-output-names : shall be the name of the clock referenced by derive
+ clock.
+Optional properties for PLL clocks:
+- clock-names : shall be the name of the clock. If missing, use the device name.
+
Required properties for device clocks:
- reg : shall be a list of address and length pairs describing the CSR
reset and/or the divider. Either may be omitted, but at least
@@ -59,6 +69,14 @@ For example:
type = <0>;
};
+ pmd0clk: pmd0clk at 7e200200 {
+ compatible = "apm,xgene-pmd-clock";
+ #clock-cells = <1>;
+ clocks = <&pmdpll 0>;
+ reg = <0x0 0x7e200200 0x0 0x10>;
+ clock-output-names = "pmd0clk";
+ };
+
socpll: socpll at 17000120 {
compatible = "apm,xgene-socpll-clock";
#clock-cells = <1>;
--
1.9.1
^ permalink raw reply related
* [PATCH v3 2/3] clk: xgene: Add PMD clock
From: Hoan Tran @ 2016-09-12 18:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473704605-28126-1-git-send-email-hotran@apm.com>
Add X-Gene PMD clock support.
PMD clock is implemented for a single register field.
Output rate = parent_rate * (denominator - scale) / denominator
with
- denominator = bitmask of register field + 1
- scale = values of register field
For example, for bitmask is 0x7, denominator will be 8 and scale
will be computed and programmed accordingly.
Signed-off-by: Hoan Tran <hotran@apm.com>
---
drivers/clk/clk-xgene.c | 221 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 221 insertions(+)
diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index 3433132..5daddf5 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -217,6 +217,226 @@ static void xgene_pcppllclk_init(struct device_node *np)
xgene_pllclk_init(np, PLL_TYPE_PCP);
}
+/**
+ * struct xgene_clk_pmd - PMD clock
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @reg: register containing the fractional scale multiplier (scaler)
+ * @shift: shift to the unit bit field
+ * @denom: 1/denominator unit
+ * @lock: register lock
+ * Flags:
+ * XGENE_CLK_PMD_SCALE_INVERTED - By default the scaler is the value read
+ * from the register plus one. For example,
+ * 0 for (0 + 1) / denom,
+ * 1 for (1 + 1) / denom and etc.
+ * If this flag is set, it is
+ * 0 for (denom - 0) / denom,
+ * 1 for (denom - 1) / denom and etc.
+ *
+ */
+struct xgene_clk_pmd {
+ struct clk_hw hw;
+ void __iomem *reg;
+ u8 shift;
+ u32 mask;
+ u64 denom;
+ u32 flags;
+ spinlock_t *lock;
+};
+
+#define to_xgene_clk_pmd(_hw) container_of(_hw, struct xgene_clk_pmd, hw)
+
+#define XGENE_CLK_PMD_SCALE_INVERTED BIT(0)
+#define XGENE_CLK_PMD_SHIFT 8
+#define XGENE_CLK_PMD_WIDTH 3
+
+static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw);
+ unsigned long flags = 0;
+ u64 ret, scale;
+ u32 val;
+
+ if (fd->lock)
+ spin_lock_irqsave(fd->lock, flags);
+ else
+ __acquire(fd->lock);
+
+ val = clk_readl(fd->reg);
+
+ if (fd->lock)
+ spin_unlock_irqrestore(fd->lock, flags);
+ else
+ __release(fd->lock);
+
+ ret = (u64)parent_rate;
+
+ scale = (val & fd->mask) >> fd->shift;
+ if (fd->flags & XGENE_CLK_PMD_SCALE_INVERTED)
+ scale = fd->denom - scale;
+ else
+ scale++;
+
+ /* freq = parent_rate * scaler / denom */
+ do_div(ret, fd->denom);
+ ret *= scale;
+ if (ret == 0)
+ ret = (u64)parent_rate;
+
+ return ret;
+}
+
+static long xgene_clk_pmd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw);
+ u64 ret, scale;
+
+ if (!rate || rate >= *parent_rate)
+ return *parent_rate;
+
+ /* freq = parent_rate * scaler / denom */
+ ret = rate * fd->denom;
+ scale = DIV_ROUND_UP_ULL(ret, *parent_rate);
+
+ ret = (u64)*parent_rate * scale;
+ do_div(ret, fd->denom);
+
+ return ret;
+}
+
+static int xgene_clk_pmd_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw);
+ unsigned long flags = 0;
+ u64 scale, ret;
+ u32 val;
+
+ /*
+ * Compute the scaler:
+ *
+ * freq = parent_rate * scaler / denom, or
+ * scaler = freq * denom / parent_rate
+ */
+ ret = rate * fd->denom;
+ scale = DIV_ROUND_UP_ULL(ret, (u64)parent_rate);
+
+ /* Check if inverted */
+ if (fd->flags & XGENE_CLK_PMD_SCALE_INVERTED)
+ scale = fd->denom - scale;
+ else
+ scale--;
+
+ if (fd->lock)
+ spin_lock_irqsave(fd->lock, flags);
+ else
+ __acquire(fd->lock);
+
+ val = clk_readl(fd->reg);
+ val &= ~fd->mask;
+ val |= (scale << fd->shift);
+ clk_writel(val, fd->reg);
+
+ if (fd->lock)
+ spin_unlock_irqrestore(fd->lock, flags);
+ else
+ __release(fd->lock);
+
+ return 0;
+}
+
+static const struct clk_ops xgene_clk_pmd_ops = {
+ .recalc_rate = xgene_clk_pmd_recalc_rate,
+ .round_rate = xgene_clk_pmd_round_rate,
+ .set_rate = xgene_clk_pmd_set_rate,
+};
+
+static struct clk *
+xgene_register_clk_pmd(struct device *dev,
+ const char *name, const char *parent_name,
+ unsigned long flags, void __iomem *reg, u8 shift,
+ u8 width, u64 denom, u32 clk_flags, spinlock_t *lock)
+{
+ struct xgene_clk_pmd *fd;
+ struct clk_init_data init;
+ struct clk *clk;
+
+ fd = kzalloc(sizeof(*fd), GFP_KERNEL);
+ if (!fd)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &xgene_clk_pmd_ops;
+ init.flags = flags;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ fd->reg = reg;
+ fd->shift = shift;
+ fd->mask = (BIT(width) - 1) << shift;
+ fd->denom = denom;
+ fd->flags = clk_flags;
+ fd->lock = lock;
+ fd->hw.init = &init;
+
+ clk = clk_register(dev, &fd->hw);
+ if (IS_ERR(clk)) {
+ pr_err("%s: could not register clk %s\n", __func__, name);
+ kfree(fd);
+ return NULL;
+ }
+
+ return clk;
+}
+
+static void xgene_pmdclk_init(struct device_node *np)
+{
+ const char *clk_name = np->full_name;
+ void __iomem *csr_reg;
+ struct resource res;
+ struct clk *clk;
+ u64 denom;
+ u32 flags = 0;
+ int rc;
+
+ /* Check if the entry is disabled */
+ if (!of_device_is_available(np))
+ return;
+
+ /* Parse the DTS register for resource */
+ rc = of_address_to_resource(np, 0, &res);
+ if (rc != 0) {
+ pr_err("no DTS register for %s\n", np->full_name);
+ return;
+ }
+ csr_reg = of_iomap(np, 0);
+ if (!csr_reg) {
+ pr_err("Unable to map resource for %s\n", np->full_name);
+ return;
+ }
+ of_property_read_string(np, "clock-output-names", &clk_name);
+
+ denom = BIT(XGENE_CLK_PMD_WIDTH);
+ flags |= XGENE_CLK_PMD_SCALE_INVERTED;
+
+ clk = xgene_register_clk_pmd(NULL, clk_name,
+ of_clk_get_parent_name(np, 0), 0,
+ csr_reg, XGENE_CLK_PMD_SHIFT,
+ XGENE_CLK_PMD_WIDTH, denom,
+ flags, &clk_lock);
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ clk_register_clkdev(clk, clk_name, NULL);
+ pr_debug("Add %s clock\n", clk_name);
+ } else {
+ if (csr_reg)
+ iounmap(csr_reg);
+ }
+}
+
/* IP Clock */
struct xgene_dev_parameters {
void __iomem *csr_reg; /* CSR for IP clock */
@@ -543,6 +763,7 @@ err:
CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
+CLK_OF_DECLARE(xgene_pmd_clock, "apm,xgene-pmd-clock", xgene_pmdclk_init);
CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock",
xgene_socpllclk_init);
CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock",
--
1.9.1
^ permalink raw reply related
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