* [PATCH 04/10] [v3] dt-bindings: qoriq-clock: update for more SoCs
From: shh.xie at gmail.com @ 2016-09-13 8:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473754203-22970-1-git-send-email-shh.xie@gmail.com>
From: Shaohui Xie <Shaohui.Xie@nxp.com>
Adds compatible for SoCs which use clockgen, the SoCs are LS1043A,
LS1046A, LS2080A.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
---
change in v3:
1. new patch.
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 16a3ec4..df9cb5a 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -32,6 +32,9 @@ Required properties:
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
* "fsl,ls1021a-clockgen"
+ * "fsl,ls1043a-clockgen"
+ * "fsl,ls1046a-clockgen"
+ * "fsl,ls2080a-clockgen"
Chassis-version clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 05/10][v3] dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a
From: shh.xie at gmail.com @ 2016-09-13 8:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473754203-22970-1-git-send-email-shh.xie@gmail.com>
From: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
---
change in V3:
1. new patch.
Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
index 032a760..fc33ca0 100644
--- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
@@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller
Required properties:
- reg: Physical base address and size of the controller's register area.
- compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
- chip could be ls1021a, ls2080a, ls1043a etc.
+ chip could be ls1021a, ls1043a, ls1046a, ls2080a etc.
- clocks: Input clock specifier. Refer to common clock bindings.
- interrupts: Interrupt specifier. Refer to interrupt binding.
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 06/10] [v3] arm64: dts: add QorIQ LS1046A SoC support
From: shh.xie at gmail.com @ 2016-09-13 8:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473754203-22970-1-git-send-email-shh.xie@gmail.com>
From: Mingkai Hu <Mingkai.Hu@nxp.com>
LS1046A is an SoC with 4 ARMv8 A72 cores and most other IP blocks
are similar to LS1043A which also complies to Freescale Chassis 2.1
spec.
Created LS1046A SoC DTSI file to be included by board level DTS
files.
Signed-off-by: Horia Geant? <horia.geanta@nxp.com>
Signed-off-by: Mihai Bantea <mihai.bantea@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
---
changs in V3:
1. sorted soc nodes in order of unit address.
2. added comments for psci.
3. changed pmu compatible to "arm,cortex-a72-pmu".
4. fixed timer and gic interrupt.
changes in V2:
1. addressed Arnd's comments.
removed memory size property.
refined devices' names.
removed PCIe and MSI nodes.
2. updated interrupt properties with readable defines.
3. removed clock-names property from I2C and watchdog nodes.
4. added crypto nodes.
binding of crypto nodes available at:
http://patchwork.ozlabs.org/patch/663184/
5. added CPU idle-states node.
6. added ddr controller node.
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 515 +++++++++++++++++++++++++
1 file changed, 515 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
new file mode 100644
index 0000000..38806ca
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -0,0 +1,515 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor, Inc.
+ *
+ * Mingkai Hu <mingkai.hu@nxp.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "fsl,ls1046a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ crypto = &crypto;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0>;
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_PH20>;
+ };
+
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x1>;
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_PH20>;
+ };
+
+ cpu2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x2>;
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_PH20>;
+ };
+
+ cpu3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x3>;
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_PH20>;
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
+ };
+
+ idle-states {
+ /*
+ * PSCI node is not added default, U-boot will add missing
+ * parts if it determines to use PSCI.
+ */
+ entry-method = "arm,psci";
+
+ CPU_PH20: cpu-ph20 {
+ compatible = "arm,idle-state";
+ idle-state-name = "PH20";
+ arm,psci-suspend-param = <0x00010000>;
+ entry-latency-us = <1000>;
+ exit-latency-us = <1000>;
+ min-residency-us = <3000>;
+ };
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ reboot {
+ compatible ="syscon-reboot";
+ regmap = <&dcfg>;
+ offset = <0xb0>;
+ mask = <0x02>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
+ };
+
+ gic: interrupt-controller at 1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1410000 0 0x10000>, /* GICD */
+ <0x0 0x1420000 0 0x20000>, /* GICC */
+ <0x0 0x1440000 0 0x20000>, /* GICH */
+ <0x0 0x1460000 0 0x20000>; /* GICV */
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ddr: memory-controller at 1080000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1080000 0x0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ };
+
+ ifc: ifc at 1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ qspi: quadspi at 1550000 {
+ compatible = "fsl,ls1021a-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1550000 0x0 0x10000>,
+ <0x0 0x40000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "qspi_en", "qspi";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
+ big-endian;
+ fsl,qspi-has-second-chip;
+ status = "disabled";
+ };
+
+ esdhc: esdhc at 1560000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x1560000 0x0 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <0>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ big-endian;
+ bus-width = <4>;
+ };
+
+ scfg: scfg at 1570000 {
+ compatible = "fsl,ls1046a-scfg", "syscon";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ big-endian;
+ };
+
+ crypto: crypto at 1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+
+ sec_jr0: jr at 10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr at 20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr at 30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr at 40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ dcfg: dcfg at 1ee0000 {
+ compatible = "fsl,ls1046a-dcfg", "syscon";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ big-endian;
+ };
+
+ clockgen: clocking at 1ee1000 {
+ compatible = "fsl,ls1046a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ dspi: dspi at 2100000 {
+ compatible = "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 1>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ i2c0: i2c at 2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ dmas = <&edma0 1 39>,
+ <&edma0 1 38>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c1: i2c at 2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 21a0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 21b0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ duart0: serial at 21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ };
+
+ duart1: serial at 21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ };
+
+ duart2: serial at 21d0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0500 0x0 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ };
+
+ duart3: serial at 21d0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0600 0x0 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ };
+
+ gpio0: gpio at 2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio at 2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 2320000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 2330000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ lpuart0: serial at 2950000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2950000 0x0 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial at 2960000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2960000 0x0 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial at 2970000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2970000 0x0 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial at 2980000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2980000 0x0 0x1000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial at 2990000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2990000 0x0 0x1000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial at 29a0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x29a0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ wdog0: watchdog at 2ad0000 {
+ compatible = "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ big-endian;
+ };
+
+ edma0: edma at 2c00000 {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x2c00000 0x0 0x10000>,
+ <0x0 0x2c10000 0x0 0x10000>,
+ <0x0 0x2c20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ big-endian;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clockgen 4 1>,
+ <&clockgen 4 1>;
+ };
+
+ usb0: usb at 2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+
+ usb1: usb at 3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+
+ usb2: usb at 3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+
+ sata: sata at 3200000 {
+ compatible = "fsl,ls1046a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 1>;
+ };
+ };
+};
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 07/10] [v3] Documentation: DT: Add entry for QorIQ LS1046A-RDB board
From: shh.xie at gmail.com @ 2016-09-13 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473754203-22970-1-git-send-email-shh.xie@gmail.com>
From: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
changes from V1 to V3:
1. none.
Documentation/devicetree/bindings/arm/fsl.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index a81277f..d6acdb3 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -155,6 +155,10 @@ LS1046A SoC
Required root node properties:
- compatible = "fsl,ls1046a";
+LS1046A ARMv8 based RDB Board
+Required root node properties:
+ - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
+
LS2080A SoC
Required root node properties:
- compatible = "fsl,ls2080a";
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 08/10] [v3] arm64: dts: add LS1046A-RDB board support
From: shh.xie at gmail.com @ 2016-09-13 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473754203-22970-1-git-send-email-shh.xie@gmail.com>
From: Mingkai Hu <Mingkai.Hu@nxp.com>
The LS1046A reference design board (RDB) is a high-performance computing,
evaluation, and development platform that supports the LS1046A SoC.
Signed-off-by: Mingkai Hu <Mingkai.Hu@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
---
changs in V3:
1. move 'status' of ifc node at the end of property list.
changes in V2:
1. updated aliases of serial nodes.
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 150 ++++++++++++++++++++++
2 files changed, 151 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 1b7783d..9c81b9e 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,5 +1,6 @@
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
new file mode 100644
index 0000000..d1ccc00
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -0,0 +1,150 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor, Inc.
+ *
+ * Mingkai Hu <mingkai.hu@nxp.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1046a.dtsi"
+
+/ {
+ model = "LS1046A RDB Board";
+ compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
+
+ aliases {
+ serial0 = &duart0;
+ serial1 = &duart1;
+ serial2 = &duart2;
+ serial3 = &duart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ ina220 at 40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ temp-sensor at 4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+
+ eeprom at 56 {
+ compatible = "atmel,24c512";
+ reg = <0x52>;
+ };
+
+ eeprom at 57 {
+ compatible = "atmel,24c512";
+ reg = <0x53>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ rtc at 51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ };
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NAND Flashe and CPLD on board */
+ ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
+ status = "okay";
+
+ nand at 0,0 {
+ compatible = "fsl,ifc-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x10000>;
+ };
+
+ cpld: board-control at 2,0 {
+ compatible = "fsl,ls1046ardb-cpld";
+ reg = <0x2 0x0 0x0000100>;
+ };
+};
+
+&qspi {
+ num-cs = <2>;
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fs512s at 0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+
+ qflash1: s25fs512s at 1 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <1>;
+ };
+};
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 09/10] [v3] Documentation: DT: Add entry for QorIQ LS1046A-QDS board
From: shh.xie at gmail.com @ 2016-09-13 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473754203-22970-1-git-send-email-shh.xie@gmail.com>
From: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
changes from V1 to V3:
1. none.
Documentation/devicetree/bindings/arm/fsl.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index d6acdb3..d6ee9c6 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -155,6 +155,10 @@ LS1046A SoC
Required root node properties:
- compatible = "fsl,ls1046a";
+LS1046A ARMv8 based QDS Board
+Required root node properties:
+ - compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
+
LS1046A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 10/10] [v3] arm64: dts: add LS1046A-QDS board support
From: shh.xie at gmail.com @ 2016-09-13 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473754203-22970-1-git-send-email-shh.xie@gmail.com>
From: Shaohui Xie <Shaohui.Xie@nxp.com>
The LS1046A QorIQ development system (QDS) board is a high-performance
computing, evaluation, development, and test platform supporting the
LS1046A SoC.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
---
changes in V3:
1. none.
changes in V2:
1. updated aliases of serial nodes.
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 212 ++++++++++++++++++++++
2 files changed, 213 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 9c81b9e..6602718 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,5 +1,6 @@
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
new file mode 100644
index 0000000..290e5b0
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -0,0 +1,212 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor, Inc.
+ *
+ * Shaohui Xie <Shaohui.Xie@nxp.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1046a.dtsi"
+
+/ {
+ model = "LS1046A QDS Board";
+ compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ serial0 = &duart0;
+ serial1 = &duart1;
+ serial2 = &duart2;
+ serial3 = &duart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&dspi {
+ bus-num = <0>;
+ status = "okay";
+
+ flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+
+ flash at 1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst25wf040b", "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ };
+
+ flash at 2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "en25s64", "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ pca9547 at 77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ ina220 at 40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220 at 41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ rtc at 51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ /* IRQ10_B */
+ interrupts = <0 150 0x4>;
+ };
+
+ eeprom at 56 {
+ compatible = "atmel,24c512";
+ reg = <0x56>;
+ };
+
+ eeprom at 57 {
+ compatible = "atmel,24c512";
+ reg = <0x57>;
+ };
+
+ temp-sensor at 4c {
+ compatible = "adi,adt7461a";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x1 0x0 0x0 0x7e800000 0x00010000
+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
+ status = "okay";
+
+ nor at 0,0 {
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand at 1,0 {
+ compatible = "fsl,ifc-nand";
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ fpga: board-control at 2,0 {
+ compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
+ reg = <0x2 0x0 0x0000100>;
+ };
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&qspi {
+ num-cs = <2>;
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s at 0 {
+ compatible = "spansion,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl
From: Linus Walleij @ 2016-09-13 8:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473432124-6784-6-git-send-email-alexandre.torgue@st.com>
On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue@st.com> wrote:
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Patch applied to the pinctrl tree.
I am happy with this solution.
As I see it, it doesn't hurt to add this into the pinctrl
tree while the irqchip stuff and DTS stuff get merged
into different trees orthogonally.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v5 6/9] pinctrl: Add IRQ support to STM32 gpios
From: Linus Walleij @ 2016-09-13 8:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473432124-6784-7-git-send-email-alexandre.torgue@st.com>
On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue@st.com> wrote:
> This patch adds IRQ support to STM32 gpios.
>
> The EXTI controller has 16 lines dedicated to GPIOs.
> EXTI line n can be connected to only line n of one of the GPIO ports, for
> example EXTI0 can be connected to either PA0, or PB0, or PC0...
> This port selection is done by specifying the port number into System
> Config registers.
>
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Nicely isolated from the other irq stuff and abstracted.
It's complex but this is as clean as we can make it,
thanks for your efforts.
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v5 14/14] drivers: acpi: iort: introduce iort_iommu_configure
From: Nate Watterson @ 2016-09-13 8:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160909142343.13314-15-lorenzo.pieralisi@arm.com>
On 2016-09-09 10:23, Lorenzo Pieralisi wrote:
> DT based systems have a generic kernel API to configure IOMMUs
> for devices (ie of_iommu_configure()).
>
> On ARM based ACPI systems, the of_iommu_configure() equivalent can
> be implemented atop ACPI IORT kernel API, with the corresponding
> functions to map device identifiers to IOMMUs and retrieve the
> corresponding IOMMU operations necessary for DMA operations set-up.
>
> By relying on the iommu_fwspec generic kernel infrastructure,
> implement the IORT based IOMMU configuration for ARM ACPI systems
> and hook it up in the ACPI kernel layer that implements DMA
> configuration for a device.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Hanjun Guo <hanjun.guo@linaro.org>
> Cc: Tomasz Nowicki <tn@semihalf.com>
> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
> ---
> drivers/acpi/arm64/iort.c | 96
> +++++++++++++++++++++++++++++++++++++++++++++++
> drivers/acpi/scan.c | 7 +++-
> include/linux/acpi_iort.h | 6 +++
> 3 files changed, 108 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index 7c68eb4..55a4ae9 100644
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@ -19,6 +19,7 @@
> #define pr_fmt(fmt) "ACPI: IORT: " fmt
>
> #include <linux/acpi_iort.h>
> +#include <linux/iommu-fwspec.h>
> #include <linux/kernel.h>
> #include <linux/list.h>
> #include <linux/pci.h>
> @@ -27,6 +28,8 @@
>
> #define IORT_TYPE_MASK(type) (1 << (type))
> #define IORT_MSI_TYPE (1 << ACPI_IORT_NODE_ITS_GROUP)
> +#define IORT_IOMMU_TYPE ((1 << ACPI_IORT_NODE_SMMU) | \
> + (1 << ACPI_IORT_NODE_SMMU_V3))
>
> struct iort_its_msi_chip {
> struct list_head list;
> @@ -467,6 +470,99 @@ struct irq_domain *iort_get_device_domain(struct
> device *dev, u32 req_id)
> return irq_find_matching_fwnode(handle, DOMAIN_BUS_PCI_MSI);
> }
>
> +static int __get_pci_rid(struct pci_dev *pdev, u16 alias, void *data)
> +{
> + u32 *rid = data;
> +
> + *rid = alias;
> + return 0;
> +}
> +
> +static int arm_smmu_iort_xlate(struct device *dev, u32 streamid,
> + struct fwnode_handle *fwnode)
> +{
> + int ret = iommu_fwspec_init(dev, fwnode);
> +
> + if (!ret)
> + ret = iommu_fwspec_add_ids(dev, &streamid, 1);
> +
> + return ret;
> +}
> +
> +static const struct iommu_ops *iort_iommu_xlate(struct device *dev,
> + struct acpi_iort_node *node,
> + u32 streamid)
> +{
> + struct fwnode_handle *iort_fwnode = NULL;
> + int ret;
> +
> + if (node) {
> + iort_fwnode = iort_get_fwnode(node);
> + if (!iort_fwnode)
> + return NULL;
> +
> + ret = arm_smmu_iort_xlate(dev, streamid,
> + iort_fwnode);
> + if (!ret)
> + return fwspec_iommu_get_ops(iort_fwnode);
> + }
> +
> + return NULL;
> +}
> +
> +/**
> + * iort_iommu_configure - Set-up IOMMU configuration for a device.
> + *
> + * @dev: device to configure
> + *
> + * Returns: iommu_ops pointer on configuration success
> + * NULL on configuration failure
> + */
> +const struct iommu_ops *iort_iommu_configure(struct device *dev)
> +{
> + struct acpi_iort_node *node, *parent;
> + const struct iommu_ops *ops = NULL;
> + u32 streamid = 0;
> +
> + if (dev_is_pci(dev)) {
> + struct pci_bus *bus = to_pci_dev(dev)->bus;
> + u32 rid;
> +
> + pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid,
> + &rid);
> +
> + node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX,
> + iort_match_node_callback, &bus->dev);
> + if (!node)
> + return NULL;
> +
> + parent = iort_node_map_rid(node, rid, &streamid,
> + IORT_IOMMU_TYPE);
> +
> + ops = iort_iommu_xlate(dev, parent, streamid);
> +
> + } else {
> + int i = 0;
> +
> + node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT,
> + iort_match_node_callback, dev);
> + if (!node)
> + return NULL;
> +
Nothing wrong with your code here, but wanted to warn you that there
appears to be a bug in iort_match_node_callback() for NAMED_COMPONENTS.
iort_match_node_callback() {
acpi_status status = AE_NOT_FOUND;
...
case ACPI_IORT_NODE_NAMED_COMPONENT: {
...
status = acpi_get_name(adev->handle, ACPI_FULL_PATHNAME, &buf);
if (ACPI_FAILURE(status)) {
dev_warn(dev, "Can't get device full path name\n");
break;
}
ncomp = (struct acpi_iort_named_component *)node->node_data;
if (!strcmp(ncomp->device_name, buf.pointer))
status = AE_OK;
acpi_os_free(buf.pointer);
break;
}
...
return status;
}
Notice how if strcmp() fails, status remains set to the status of the
call
to acpi_get_name() which must have been OK since we would have broken
out
of the switch statement otherwise. This is causing all manner of
platform
devices not even described in the IORT to get hooked up using the IDs of
the first properly iommu-attached NAMED_COMPONENT device found in the
IORT.
> + parent = iort_node_get_id(node, &streamid,
> + IORT_IOMMU_TYPE, i++);
> +
> + while (parent) {
> + ops = iort_iommu_xlate(dev, parent, streamid);
> +
> + parent = iort_node_get_id(node, &streamid,
> + IORT_IOMMU_TYPE, i++);
> + }
> + }
> +
> + return ops;
> +}
> +
> static void __init acpi_iort_register_irq(int hwirq, const char *name,
> int trigger,
> struct resource *res)
> diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
> index 9614232..7e56a85 100644
> --- a/drivers/acpi/scan.c
> +++ b/drivers/acpi/scan.c
> @@ -7,6 +7,7 @@
> #include <linux/slab.h>
> #include <linux/kernel.h>
> #include <linux/acpi.h>
> +#include <linux/acpi_iort.h>
> #include <linux/signal.h>
> #include <linux/kthread.h>
> #include <linux/dmi.h>
> @@ -1377,11 +1378,15 @@ enum dev_dma_attr acpi_get_dma_attr(struct
> acpi_device *adev)
> */
> void acpi_dma_configure(struct device *dev, enum dev_dma_attr attr)
> {
> + const struct iommu_ops *iommu;
> +
> + iommu = iort_iommu_configure(dev);
> +
> /*
> * Assume dma valid range starts at 0 and covers the whole
> * coherent_dma_mask.
> */
> - arch_setup_dma_ops(dev, 0, dev->coherent_dma_mask + 1, NULL,
> + arch_setup_dma_ops(dev, 0, dev->coherent_dma_mask + 1, iommu,
> attr == DEV_DMA_COHERENT);
> }
>
> diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h
> index 1ed4f8f..167649a 100644
> --- a/include/linux/acpi_iort.h
> +++ b/include/linux/acpi_iort.h
> @@ -36,6 +36,8 @@ struct irq_domain *iort_get_device_domain(struct
> device *dev, u32 req_id);
> int iort_set_fwnode(struct acpi_iort_node *iort_node,
> struct fwnode_handle *fwnode);
> struct fwnode_handle *iort_get_fwnode(struct acpi_iort_node *node);
> +/* IOMMU interface */
> +const struct iommu_ops *iort_iommu_configure(struct device *dev);
> #else
> static inline void acpi_iort_init(void) { }
> static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id)
> @@ -49,6 +51,10 @@ static inline int iort_set_fwnode(struct
> acpi_iort_node *iort_node,
> static inline
> struct fwnode_handle *iort_get_fwnode(struct acpi_iort_node *node)
> { return NULL; }
> +/* IOMMU interface */
> +static inline
> +const struct iommu_ops *iort_iommu_configure(struct device *dev)
> +{ return NULL; }
> #endif
>
> #define IORT_ACPI_DECLARE(name, table_id, fn) \
--
Qualcomm Datacenter Technologies, Inc. on behalf of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a
Linux
Foundation Collaborative Project.
^ permalink raw reply
* [PATCH v5 07/14] drivers: acpi: iort: add support for ARM SMMU platform devices creation
From: Hanjun Guo @ 2016-09-13 8:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7a63cf312b6e9714cdce1d0aca88cf4d@codeaurora.org>
On 2016/9/13 15:46, nwatters at codeaurora.org wrote:
> On 2016-09-09 10:23, Lorenzo Pieralisi wrote:
>> In ARM ACPI systems, IOMMU components are specified through static
>> IORT table entries. In order to create platform devices for the
>> corresponding ARM SMMU components, IORT kernel code should be made
>> able to parse IORT table entries and create platform devices
>> dynamically.
>>
>> This patch adds the generic IORT infrastructure required to create
>> platform devices for ARM SMMUs.
>>
>> ARM SMMU versions have different resources requirement therefore this
>> patch also introduces an IORT specific structure (ie iort_iommu_config)
>> that contains hooks (to be defined when the corresponding ARM SMMU
>> driver support is added to the kernel) to be used to define the
>> platform devices names, init the IOMMUs, count their resources and
>> finally initialize them.
>>
>> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> Cc: Hanjun Guo <hanjun.guo@linaro.org>
>> Cc: Tomasz Nowicki <tn@semihalf.com>
>> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
>> ---
>> drivers/acpi/arm64/iort.c | 131
>> ++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 131 insertions(+)
>>
>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>> index b89b3d3..e0a9b16 100644
>> --- a/drivers/acpi/arm64/iort.c
>> +++ b/drivers/acpi/arm64/iort.c
>> @@ -22,6 +22,7 @@
>> #include <linux/kernel.h>
>> #include <linux/list.h>
>> #include <linux/pci.h>
>> +#include <linux/platform_device.h>
>> #include <linux/slab.h>
>>
>> struct iort_its_msi_chip {
>> @@ -424,6 +425,135 @@ struct irq_domain *iort_get_device_domain(struct
>> device *dev, u32 req_id)
>> return irq_find_matching_fwnode(handle, DOMAIN_BUS_PCI_MSI);
>> }
>>
>> +struct iort_iommu_config {
>> + const char *name;
>> + int (*iommu_init)(struct acpi_iort_node *node);
>> + bool (*iommu_is_coherent)(struct acpi_iort_node *node);
>> + int (*iommu_count_resources)(struct acpi_iort_node *node);
>> + void (*iommu_init_resources)(struct resource *res,
>> + struct acpi_iort_node *node);
>> +};
>> +
>> +static __init
>> +const struct iort_iommu_config *iort_get_iommu_cfg(struct
>> acpi_iort_node *node)
>> +{
>> + return NULL;
>> +}
>> +
>> +/**
>> + * iort_add_smmu_platform_device() - Allocate a platform device for SMMU
>> + * @fwnode: IORT node associated fwnode handle
>> + * @node: Pointer to SMMU ACPI IORT node
>> + *
>> + * Returns: 0 on success, <0 failure
>> + */
>> +static int __init iort_add_smmu_platform_device(struct fwnode_handle
>> *fwnode,
>> + struct acpi_iort_node *node)
>> +{
>> + struct platform_device *pdev;
>> + struct resource *r;
>> + enum dev_dma_attr attr;
>> + int ret, count;
>> + const struct iort_iommu_config *ops = iort_get_iommu_cfg(node);
>> +
>> + if (!ops)
>> + return -ENODEV;
>> +
>> + pdev = platform_device_alloc(ops->name, PLATFORM_DEVID_AUTO);
>> + if (!pdev)
>> + return PTR_ERR(pdev);
>> +
>> + count = ops->iommu_count_resources(node);
>> +
>> + r = kcalloc(count, sizeof(*r), GFP_KERNEL);
>> + if (!r) {
>> + ret = -ENOMEM;
>> + goto dev_put;
>> + }
>> +
>> + ops->iommu_init_resources(r, node);
>> +
>> + ret = platform_device_add_resources(pdev, r, count);
>> + /*
>> + * Resources are duplicated in platform_device_add_resources,
>> + * free their allocated memory
>> + */
>> + kfree(r);
>> +
>> + if (ret)
>> + goto dev_put;
>> +
>> + /*
>> + * Add a copy of IORT node pointer to platform_data to
>> + * be used to retrieve IORT data information.
>> + */
>> + ret = platform_device_add_data(pdev, &node, sizeof(node));
>> + if (ret)
>> + goto dev_put;
>> +
>> + pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask),
>> GFP_KERNEL);
>> + if (!pdev->dev.dma_mask) {
>> + ret = -ENOMEM;
>> + goto dev_put;
>> + }
>> +
>> + pdev->dev.fwnode = fwnode;
>> +
>> + /*
>> + * Set default dma mask value for the table walker,
>> + * to be overridden on probing with correct value.
>> + */
>> + *pdev->dev.dma_mask = DMA_BIT_MASK(32);
>> + pdev->dev.coherent_dma_mask = *pdev->dev.dma_mask;
>> +
>> + attr = ops->iommu_is_coherent(node) ?
>> + DEV_DMA_COHERENT : DEV_DMA_NON_COHERENT;
>> +
>> + /* Configure DMA for the page table walker */
>> + acpi_dma_configure(&pdev->dev, attr);
>> +
>> + ret = platform_device_add(pdev);
>> + if (ret)
>> + goto dma_deconfigure;
>> +
>> + return 0;
>> +
>> +dma_deconfigure:
>> + acpi_dma_deconfigure(&pdev->dev);
>> + kfree(pdev->dev.dma_mask);
>> +
>> +dev_put:
>> + platform_device_put(pdev);
>> +
>> + return ret;
>> +}
>> +
>> +static acpi_status __init iort_match_iommu_callback(struct
>> acpi_iort_node *node,
>> + void *context)
>> +{
>> + int ret;
>> + struct fwnode_handle *fwnode;
>> +
>> + fwnode = iort_get_fwnode(node);
>> +
>> + if (!fwnode)
>> + return AE_NOT_FOUND;
>> +
>> + ret = iort_add_smmu_platform_device(fwnode, node);
>> + if (ret) {
>> + pr_err("Error in platform device creation\n");
>> + return AE_ERROR;
>> + }
>> +
>> + return AE_OK;
>> +}
>> +
>> +static void __init iort_smmu_init(void)
>> +{
>> + iort_scan_node(ACPI_IORT_NODE_SMMU, iort_match_iommu_callback,
>> NULL);
>> + iort_scan_node(ACPI_IORT_NODE_SMMU_V3, iort_match_iommu_callback,
>> NULL);
>
> Since iort_scan_node() returns after the first successful match it finds,
> only the first SMMU_V3 in my IORT is being enumerated. I think you need
> to go back to the "iterator" like approach you had been using or make
> iort_match_iommu_callback() always return a non-AE_OK value so the scan
> continues and has a chance to visit all of the SMMU_V3 nodes.
Please use the updated version of IORT patch (aka Tomasz's v11)
then things will work fine.
Thanks
Hanjun
^ permalink raw reply
* [PATCH v5 14/14] drivers: acpi: iort: introduce iort_iommu_configure
From: Hanjun Guo @ 2016-09-13 8:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57647b7518907dd9bd682e5e5a55ca80@codeaurora.org>
Hi Nate,
On 2016/9/13 16:14, Nate Watterson wrote:
> On 2016-09-09 10:23, Lorenzo Pieralisi wrote:
>> DT based systems have a generic kernel API to configure IOMMUs
>> for devices (ie of_iommu_configure()).
>>
>> On ARM based ACPI systems, the of_iommu_configure() equivalent can
>> be implemented atop ACPI IORT kernel API, with the corresponding
>> functions to map device identifiers to IOMMUs and retrieve the
>> corresponding IOMMU operations necessary for DMA operations set-up.
>>
>> By relying on the iommu_fwspec generic kernel infrastructure,
>> implement the IORT based IOMMU configuration for ARM ACPI systems
>> and hook it up in the ACPI kernel layer that implements DMA
>> configuration for a device.
>>
>> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> Cc: Hanjun Guo <hanjun.guo@linaro.org>
>> Cc: Tomasz Nowicki <tn@semihalf.com>
>> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
>> ---
>> drivers/acpi/arm64/iort.c | 96
>> +++++++++++++++++++++++++++++++++++++++++++++++
>> drivers/acpi/scan.c | 7 +++-
>> include/linux/acpi_iort.h | 6 +++
>> 3 files changed, 108 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>> index 7c68eb4..55a4ae9 100644
>> --- a/drivers/acpi/arm64/iort.c
>> +++ b/drivers/acpi/arm64/iort.c
>> @@ -19,6 +19,7 @@
>> #define pr_fmt(fmt) "ACPI: IORT: " fmt
>>
>> #include <linux/acpi_iort.h>
>> +#include <linux/iommu-fwspec.h>
>> #include <linux/kernel.h>
>> #include <linux/list.h>
>> #include <linux/pci.h>
>> @@ -27,6 +28,8 @@
>>
>> #define IORT_TYPE_MASK(type) (1 << (type))
>> #define IORT_MSI_TYPE (1 << ACPI_IORT_NODE_ITS_GROUP)
>> +#define IORT_IOMMU_TYPE ((1 << ACPI_IORT_NODE_SMMU) | \
>> + (1 << ACPI_IORT_NODE_SMMU_V3))
>>
>> struct iort_its_msi_chip {
>> struct list_head list;
>> @@ -467,6 +470,99 @@ struct irq_domain *iort_get_device_domain(struct
>> device *dev, u32 req_id)
>> return irq_find_matching_fwnode(handle, DOMAIN_BUS_PCI_MSI);
>> }
>>
>> +static int __get_pci_rid(struct pci_dev *pdev, u16 alias, void *data)
>> +{
>> + u32 *rid = data;
>> +
>> + *rid = alias;
>> + return 0;
>> +}
>> +
>> +static int arm_smmu_iort_xlate(struct device *dev, u32 streamid,
>> + struct fwnode_handle *fwnode)
>> +{
>> + int ret = iommu_fwspec_init(dev, fwnode);
>> +
>> + if (!ret)
>> + ret = iommu_fwspec_add_ids(dev, &streamid, 1);
>> +
>> + return ret;
>> +}
>> +
>> +static const struct iommu_ops *iort_iommu_xlate(struct device *dev,
>> + struct acpi_iort_node *node,
>> + u32 streamid)
>> +{
>> + struct fwnode_handle *iort_fwnode = NULL;
>> + int ret;
>> +
>> + if (node) {
>> + iort_fwnode = iort_get_fwnode(node);
>> + if (!iort_fwnode)
>> + return NULL;
>> +
>> + ret = arm_smmu_iort_xlate(dev, streamid,
>> + iort_fwnode);
>> + if (!ret)
>> + return fwspec_iommu_get_ops(iort_fwnode);
>> + }
>> +
>> + return NULL;
>> +}
>> +
>> +/**
>> + * iort_iommu_configure - Set-up IOMMU configuration for a device.
>> + *
>> + * @dev: device to configure
>> + *
>> + * Returns: iommu_ops pointer on configuration success
>> + * NULL on configuration failure
>> + */
>> +const struct iommu_ops *iort_iommu_configure(struct device *dev)
>> +{
>> + struct acpi_iort_node *node, *parent;
>> + const struct iommu_ops *ops = NULL;
>> + u32 streamid = 0;
>> +
>> + if (dev_is_pci(dev)) {
>> + struct pci_bus *bus = to_pci_dev(dev)->bus;
>> + u32 rid;
>> +
>> + pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid,
>> + &rid);
>> +
>> + node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX,
>> + iort_match_node_callback, &bus->dev);
>> + if (!node)
>> + return NULL;
>> +
>> + parent = iort_node_map_rid(node, rid, &streamid,
>> + IORT_IOMMU_TYPE);
>> +
>> + ops = iort_iommu_xlate(dev, parent, streamid);
>> +
>> + } else {
>> + int i = 0;
>> +
>> + node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT,
>> + iort_match_node_callback, dev);
>> + if (!node)
>> + return NULL;
>> +
>
> Nothing wrong with your code here, but wanted to warn you that there
> appears to be a bug in iort_match_node_callback() for NAMED_COMPONENTS.
>
> iort_match_node_callback() {
> acpi_status status = AE_NOT_FOUND;
> ...
> case ACPI_IORT_NODE_NAMED_COMPONENT: {
> ...
> status = acpi_get_name(adev->handle, ACPI_FULL_PATHNAME, &buf);
> if (ACPI_FAILURE(status)) {
> dev_warn(dev, "Can't get device full path name\n");
> break;
> }
>
> ncomp = (struct acpi_iort_named_component *)node->node_data;
> if (!strcmp(ncomp->device_name, buf.pointer))
> status = AE_OK;
>
> acpi_os_free(buf.pointer);
> break;
> }
> ...
> return status;
> }
>
> Notice how if strcmp() fails, status remains set to the status of the call
> to acpi_get_name() which must have been OK since we would have broken out
> of the switch statement otherwise. This is causing all manner of platform
> devices not even described in the IORT to get hooked up using the IDs of
> the first properly iommu-attached NAMED_COMPONENT device found in the IORT.
As I said in previous email, please use the new version of IORT patch
set :)
Thanks
Hanjun
^ permalink raw reply
* [PATCH v5 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl
From: Linus Walleij @ 2016-09-13 8:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473432124-6784-6-git-send-email-alexandre.torgue@st.com>
On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
<alexandre.torgue@st.com> wrote:
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> index 587bffb..a0eed99 100644
> --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
> @@ -14,6 +14,9 @@ Required properies:
> - #size-cells : The value of this property must be 1
> - ranges : defines mapping between pin controller node (parent) to
> gpio-bank node (children).
> + - interrupt-parent: phandle of the interrupt parent to which the external
> + GPIO interrupts are forwarded to.
> + - st,syscfg: phandle of the syscfg node used for IRQ mux selection.
Actually this doc is incomplete.
This is a phandle + offset, not just a phandle.
It is a small detail so I don't care much, either send a patch to
fix up this doc (I have already merged it) or patch the driver
to not retrieve the offset and instead use
#define SYSCFG_OFFSET 0x08
or something...
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support
From: Marc Zyngier @ 2016-09-13 8:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473432124-6784-3-git-send-email-alexandre.torgue@st.com>
On 09/09/16 15:41, Alexandre TORGUE wrote:
> The STM32 external interrupt controller consists of edge detectors that
> generate interrupts requests or wake-up events.
>
> Each line can be independently configured as interrupt or wake-up source,
> and triggers either on rising, falling or both edges. Each line can also
> be masked independently.
>
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v4 01/10] arm64: KVM: Use static keys for selecting the GIC backend
From: Christoffer Dall @ 2016-09-13 8:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473691764-29424-2-git-send-email-vladimir.murzin@arm.com>
On Mon, Sep 12, 2016 at 03:49:15PM +0100, Vladimir Murzin wrote:
> Currently GIC backend is selected via alternative framework and this
> is fine. We are going to introduce vgic-v3 to 32-bit world and there
> we don't have patching framework in hand, so we can either check
> support for GICv3 every time we need to choose which backend to use or
> try to optimise it by using static keys. The later looks quite
> promising because we can share logic involved in selecting GIC backend
> between architectures if both uses static keys.
>
> This patch moves arm64 from alternative to static keys framework for
> selecting GIC backend. For that we embed static key into vgic_global
> and enable the key during vgic initialisation based on what has
> already been exposed by the host GIC driver.
>
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
> arch/arm64/kvm/hyp/switch.c | 21 +++++++++++----------
> include/kvm/arm_vgic.h | 4 ++++
> virt/kvm/arm/vgic/vgic-init.c | 4 ++++
> virt/kvm/arm/vgic/vgic.c | 2 +-
> 4 files changed, 20 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
> index 5a84b45..d5c4cc5 100644
> --- a/arch/arm64/kvm/hyp/switch.c
> +++ b/arch/arm64/kvm/hyp/switch.c
> @@ -16,6 +16,8 @@
> */
>
> #include <linux/types.h>
> +#include <linux/jump_label.h>
> +
> #include <asm/kvm_asm.h>
> #include <asm/kvm_hyp.h>
>
> @@ -126,17 +128,13 @@ static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
> write_sysreg(0, vttbr_el2);
> }
>
> -static hyp_alternate_select(__vgic_call_save_state,
> - __vgic_v2_save_state, __vgic_v3_save_state,
> - ARM64_HAS_SYSREG_GIC_CPUIF);
> -
> -static hyp_alternate_select(__vgic_call_restore_state,
> - __vgic_v2_restore_state, __vgic_v3_restore_state,
> - ARM64_HAS_SYSREG_GIC_CPUIF);
> -
> static void __hyp_text __vgic_save_state(struct kvm_vcpu *vcpu)
> {
> - __vgic_call_save_state()(vcpu);
> + if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
It's a bit weird that we use _unlikely for GICv3 (at least if/when GICv3
hardware becomes mainstream), but as we don't have another primitive for
the 'default disabled' case, I suppose that's the best we can do.
> + __vgic_v3_save_state(vcpu);
> + else
> + __vgic_v2_save_state(vcpu);
> +
> write_sysreg(read_sysreg(hcr_el2) & ~HCR_INT_OVERRIDE, hcr_el2);
> }
>
> @@ -149,7 +147,10 @@ static void __hyp_text __vgic_restore_state(struct kvm_vcpu *vcpu)
> val |= vcpu->arch.irq_lines;
> write_sysreg(val, hcr_el2);
>
> - __vgic_call_restore_state()(vcpu);
> + if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
> + __vgic_v3_restore_state(vcpu);
> + else
> + __vgic_v2_restore_state(vcpu);
> }
>
> static bool __hyp_text __true_value(void)
> diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
> index 19b698e..994665a 100644
> --- a/include/kvm/arm_vgic.h
> +++ b/include/kvm/arm_vgic.h
> @@ -23,6 +23,7 @@
> #include <linux/types.h>
> #include <kvm/iodev.h>
> #include <linux/list.h>
> +#include <linux/jump_label.h>
>
> #define VGIC_V3_MAX_CPUS 255
> #define VGIC_V2_MAX_CPUS 8
> @@ -63,6 +64,9 @@ struct vgic_global {
>
> /* Only needed for the legacy KVM_CREATE_IRQCHIP */
> bool can_emulate_gicv2;
> +
> + /* GIC system register CPU interface */
> + struct static_key_false gicv3_cpuif;
Documentation/static-keys.txt says that we are not supposed to use
struct static_key_false directly. This will obviously work quite
nicely, but we could consider adding a pair of
DECLARE_STATIC_KEY_TRUE/FALSE macros that don't have the assignments,
but obviously this will need an ack from other maintainers.
Thoughts?
> };
>
> extern struct vgic_global kvm_vgic_global_state;
> diff --git a/virt/kvm/arm/vgic/vgic-init.c b/virt/kvm/arm/vgic/vgic-init.c
> index 83777c1..14d6718 100644
> --- a/virt/kvm/arm/vgic/vgic-init.c
> +++ b/virt/kvm/arm/vgic/vgic-init.c
> @@ -405,6 +405,10 @@ int kvm_vgic_hyp_init(void)
> break;
> case GIC_V3:
> ret = vgic_v3_probe(gic_kvm_info);
> + if (!ret) {
> + static_branch_enable(&kvm_vgic_global_state.gicv3_cpuif);
> + kvm_info("GIC system register CPU interface\n");
nit: add enabled to the info message?
> + }
> break;
> default:
> ret = -ENODEV;
> diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
> index e83b7fe..8a529a7 100644
> --- a/virt/kvm/arm/vgic/vgic.c
> +++ b/virt/kvm/arm/vgic/vgic.c
> @@ -29,7 +29,7 @@
> #define DEBUG_SPINLOCK_BUG_ON(p)
> #endif
>
> -struct vgic_global __section(.hyp.text) kvm_vgic_global_state;
> +struct vgic_global __section(.hyp.text) kvm_vgic_global_state = {.gicv3_cpuif = STATIC_KEY_FALSE_INIT,};
>
> /*
> * Locking order is always:
> --
> 1.7.9.5
>
Overall this looks really nice, as long as we're clear on the static
keys stuff.
Thanks!
-Christoffer
^ permalink raw reply
* [PATCH v5 2/3] mfd: add support for Allwinner SoCs ADC
From: Lee Jones @ 2016-09-13 8:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a48580b4-1494-d474-b33c-007f898b29b7@free-electrons.com>
On Tue, 13 Sep 2016, Quentin Schulz wrote:
> On 12/09/2016 15:56, Lee Jones wrote:
> > On Mon, 12 Sep 2016, Quentin Schulz wrote:
> >> On 12/09/2016 11:59, Lee Jones wrote:
> >>> On Mon, 12 Sep 2016, Quentin Schulz wrote:
> >>>
> >>>> On 12/09/2016 11:18, Lee Jones wrote:
> >>>>> On Thu, 08 Sep 2016, Quentin Schulz wrote:
> >>>>> [...]
> >>>>>> +
> >>>>>> +MODULE_DEVICE_TABLE(of, sun4i_gpadc_mfd_of_match);
> >>>>>
> >>>>> Place this directly under the table.
> >>>>>
> >>>>>> +static struct platform_driver sun4i_gpadc_mfd_driver = {
> >>>>>> + .driver = {
> >>>>>> + .name = "sun4i-adc-mfd",
> >>>>>> + .of_match_table = of_match_ptr(sun4i_gpadc_mfd_of_match),
> >>>>>> + },
> >>>>>> + .probe = sun4i_gpadc_mfd_probe,
> >>>>>
> >>>>> No .remove?
> >>>>>
> >>>>
> >>>> No, everything in probe is handled with devm functions.
> >>>
> >>> Don't you need to undo the register write you did?
> >>>
> >>
> >> The regmap_write I use is there to disable all interrupts on hardware
> >> side before the irq_chip handles all interrupts by itself. The
> >> interrupts are not used in the MFD driver.
> >>
> >> Thus, I chose to disable the hardware interrupts in the remove function
> >> of drivers using the interrupts (only the IIO yet but the touchscreen
> >> driver later also which will be using a third interrupt). When the MFD
> >> driver is removed, the MFD cells will all be removed, thus calling their
> >> own remove functions, thus disabling hardware interrupts used in each
> >> driver. So the hardware interrupts disabling would be called twice.
> >
> > This does send some little alarm bells ringing. I'd normally expect
> > the .remove function to undo everything you did in .probe. So, if you
> > are disabling the IRQs from within the leaf drivers, shouldn't you be
> > initialising them in the leaf driver's respective .probes?
> >
>
> I use the regmap_write in the MFD driver's probe to disable all
> interrupts before requesting irq_chip to guarantee the interrupts are in
> a known state, being disabled. It is to insure no interrupt will occur
> unwittingly before we want the leaf drivers to handle them.
>
> The disabling of irqs in the remove is handled rather by
> devm_regmap_del_irq_chip than by an explicit regmap_write in the
> driver's removal function. It performs the exact same thing.
>
> I always use devm functions for requesting either an irq_chip or the
> irqs themselves. In that case, when the device is removed, the irqs are
> freed on leaf drivers' (where the irqs are requested) removal while the
> removal of irq_chip in the MFD driver will also free all irqs mapped to
> this irq_chip thanks to devm_regmap_del_irq_chip. Therefore, the
> interrupts are disabled by devm functions.
>
> The regmap_update_bits in probe and removal of the ADC driver to disable
> irqs are actually redundant because the devm functions already handle
> the irqs disabling.
Okay. So long as you've thought about it, I'm happy.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v5 07/14] drivers: acpi: iort: add support for ARM SMMU platform devices creation
From: Lorenzo Pieralisi @ 2016-09-13 8:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <fb4acfd5-b7fd-636f-53f3-13dc6fb8b713@linaro.org>
On Tue, Sep 13, 2016 at 04:15:31PM +0800, Hanjun Guo wrote:
[...]
> >>+static acpi_status __init iort_match_iommu_callback(struct
> >>acpi_iort_node *node,
> >>+ void *context)
> >>+{
> >>+ int ret;
> >>+ struct fwnode_handle *fwnode;
> >>+
> >>+ fwnode = iort_get_fwnode(node);
> >>+
> >>+ if (!fwnode)
> >>+ return AE_NOT_FOUND;
> >>+
> >>+ ret = iort_add_smmu_platform_device(fwnode, node);
> >>+ if (ret) {
> >>+ pr_err("Error in platform device creation\n");
> >>+ return AE_ERROR;
> >>+ }
> >>+
> >>+ return AE_OK;
> >>+}
> >>+
> >>+static void __init iort_smmu_init(void)
> >>+{
> >>+ iort_scan_node(ACPI_IORT_NODE_SMMU, iort_match_iommu_callback,
> >>NULL);
> >>+ iort_scan_node(ACPI_IORT_NODE_SMMU_V3, iort_match_iommu_callback,
> >>NULL);
> >
> >Since iort_scan_node() returns after the first successful match it finds,
> >only the first SMMU_V3 in my IORT is being enumerated. I think you need
> >to go back to the "iterator" like approach you had been using or make
> >iort_match_iommu_callback() always return a non-AE_OK value so the scan
> >continues and has a chance to visit all of the SMMU_V3 nodes.
>
> Please use the updated version of IORT patch (aka Tomasz's v11)
> then things will work fine.
Nate is right, I was too keen on using iort_scan_node(), it does
not really work here (unless as he said I return a value !AE_OK in
the callback, which is horrible), I reverted back to the iterator
approach and I can push out a fixed up branch if useful before next
posting.
Thanks,
Lorenzo
^ permalink raw reply
* [PATCH v5 12/14] drivers: acpi: iort: replace rid map type with type mask
From: Hanjun Guo @ 2016-09-13 8:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160909142343.13314-13-lorenzo.pieralisi@arm.com>
Hi Lorenzo,
On 2016/9/9 22:23, Lorenzo Pieralisi wrote:
> IORT tables provide data that allow the kernel to carry out
> device ID mappings between endpoints and system components
> (eg interrupt controllers, IOMMUs). When the mapping for a
> given device ID is carried out, the translation mechanism
> is done on a per-subsystem basis rather than a component
> subtype (ie the IOMMU kernel layer will look for mappings
> from a device to all IORT node types corresponding to IOMMU
> components), therefore the corresponding mapping API should
> work on a range (ie mask) of IORT node types corresponding
> to a common set of components (eg IOMMUs) rather than a
> specific node type.
>
> Upgrade the IORT iort_node_map_rid() API to work with a
> type mask instead of a single node type so that it can
> be used for mappings that span multiple components types
> (ie IOMMUs).
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Hanjun Guo <hanjun.guo@linaro.org>
> Cc: Tomasz Nowicki <tn@semihalf.com>
> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
> ---
> drivers/acpi/arm64/iort.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index a12dda9..36ea93e 100644
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@ -25,6 +25,9 @@
> #include <linux/platform_device.h>
> #include <linux/slab.h>
>
> +#define IORT_TYPE_MASK(type) (1 << (type))
> +#define IORT_MSI_TYPE (1 << ACPI_IORT_NODE_ITS_GROUP)
> +
> struct iort_its_msi_chip {
> struct list_head list;
> struct fwnode_handle *fw_node;
> @@ -283,7 +286,7 @@ static int iort_id_map(struct acpi_iort_id_mapping *map, u8 type, u32 rid_in,
>
> static struct acpi_iort_node *iort_node_map_rid(struct acpi_iort_node *node,
> u32 rid_in, u32 *rid_out,
> - u8 type)
> + u8 type_mask)
> {
> u32 rid = rid_in;
>
> @@ -292,7 +295,7 @@ static struct acpi_iort_node *iort_node_map_rid(struct acpi_iort_node *node,
> struct acpi_iort_id_mapping *map;
> int i;
>
> - if (node->type == type) {
> + if (IORT_TYPE_MASK(node->type) & type_mask) {
> if (rid_out)
> *rid_out = rid;
> return node;
> @@ -365,7 +368,7 @@ u32 iort_msi_map_rid(struct device *dev, u32 req_id)
> if (!node)
> return req_id;
>
> - iort_node_map_rid(node, req_id, &dev_id, ACPI_IORT_NODE_ITS_GROUP);
> + iort_node_map_rid(node, req_id, &dev_id, IORT_MSI_TYPE);
> return dev_id;
> }
I think you forgot to update another function which is ok in your v4
patch set:
@@ -411,7 +414,7 @@ iort_dev_find_its_id(struct device *dev, u32 req_id,
unsigned int idx,
return -ENXIO;
}
- node = iort_node_map_rid(node, req_id, NULL, ACPI_IORT_NODE_ITS_GROUP);
+ node = iort_node_map_rid(node, req_id, NULL, IORT_MSI_TYPE);
if (!node) {
dev_err(dev, "can't find related ITS node\n");
return -ENXIO;
Others are look good to me.
Thanks
Hanjun
^ permalink raw reply
* [PATCH 1/6] gpio: constify gpio_chip structures
From: Linus Walleij @ 2016-09-13 8:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473596082-32690-2-git-send-email-Julia.Lawall@lip6.fr>
On Sun, Sep 11, 2016 at 2:14 PM, Julia Lawall <Julia.Lawall@lip6.fr> wrote:
> These structures are only used to copy into other structures, so declare
> them as const.
(...)
>
> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Patch applied, awesome work as always, thanks!
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 1/3] arm64: alternative: add auto-nop infrastructure
From: Ard Biesheuvel @ 2016-09-13 8:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473242830-26246-2-git-send-email-mark.rutland@arm.com>
On 7 September 2016 at 11:07, Mark Rutland <mark.rutland@arm.com> wrote:
> In some cases, one side of an alternative sequence is simply a number of
> NOPs used to balance the other side. Keeping track of this manually is
> tedious, and the presence of large chains of NOPs makes the code more
> painful to read than necessary.
>
> To ameliorate matters, this patch adds a new alternative_else_nop_endif,
> which automatically balances an alternative sequence with a trivial NOP
> sled.
>
> In many cases, we would like a NOP-sled in the default case, and
> instructions patched in in the presence of a feature. To enable the NOPs
> to be generated automatically for this case, this patch also adds a new
> alternative_if, and updates alternative_else and alternative_endif to
> work with either alternative_if or alternative_endif.
>
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> Cc: Andre Przywara <andre.przywara@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Dave Martin <dave.martin@arm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> ---
> arch/arm64/include/asm/alternative.h | 71 +++++++++++++++++++++++++++---------
> 1 file changed, 54 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm64/include/asm/alternative.h b/arch/arm64/include/asm/alternative.h
> index 8746ff6..4ddbf1c 100644
> --- a/arch/arm64/include/asm/alternative.h
> +++ b/arch/arm64/include/asm/alternative.h
> @@ -90,34 +90,55 @@ void apply_alternatives(void *start, size_t length);
> .endm
>
> /*
> - * Begin an alternative code sequence.
> + * Alternative sequences
> + *
> + * The code for the case where the capability is not present will be
> + * assembled and linked as normal. There are no restrictions on this
> + * code.
> + *
> + * The code for the case where the capability is present will be
> + * assembled into a special section to be used for dynamic patching.
> + * Code for that case must:
> + *
> + * 1. Be exactly the same length (in bytes) as the default code
> + * sequence.
> *
> - * The code that follows this macro will be assembled and linked as
> - * normal. There are no restrictions on this code.
> + * 2. Not contain a branch target that is used outside of the
> + * alternative sequence it is defined in (branches into an
> + * alternative sequence are not fixed up).
> + */
> +
> +/*
> + * Begin an alternative code sequence.
> */
> .macro alternative_if_not cap
> + .set .Lasm_alt_mode, 0
Given that only a single copy of this symbol will exist in an object
file, is it still possible to use both variants in a single
compilation/assembly unit?
> .pushsection .altinstructions, "a"
> altinstruction_entry 661f, 663f, \cap, 662f-661f, 664f-663f
> .popsection
> 661:
> .endm
>
> +.macro alternative_if cap
> + .set .Lasm_alt_mode, 1
> + .pushsection .altinstructions, "a"
> + altinstruction_entry 663f, 661f, \cap, 664f-663f, 662f-661f
> + .popsection
> + .pushsection .altinstr_replacement, "ax"
> + .align 2 /* So GAS knows label 661 is suitably aligned */
> +661:
> +.endm
> +
> /*
> - * Provide the alternative code sequence.
> - *
> - * The code that follows this macro is assembled into a special
> - * section to be used for dynamic patching. Code that follows this
> - * macro must:
> - *
> - * 1. Be exactly the same length (in bytes) as the default code
> - * sequence.
> - *
> - * 2. Not contain a branch target that is used outside of the
> - * alternative sequence it is defined in (branches into an
> - * alternative sequence are not fixed up).
> + * Provide the other half of the alternative code sequence.
> */
> .macro alternative_else
> -662: .pushsection .altinstr_replacement, "ax"
> +662:
> + .if .Lasm_alt_mode==0
> + .pushsection .altinstr_replacement, "ax"
> + .else
> + .popsection
> + .endif
> 663:
> .endm
>
> @@ -125,11 +146,27 @@ void apply_alternatives(void *start, size_t length);
> * Complete an alternative code sequence.
> */
> .macro alternative_endif
> -664: .popsection
> +664:
> + .if .Lasm_alt_mode==0
> + .popsection
> + .endif
> .org . - (664b-663b) + (662b-661b)
> .org . - (662b-661b) + (664b-663b)
> .endm
>
> +/*
> + * Provides a trivial alternative or default sequence consisting solely
> + * of NOPs. The number of NOPs is chosen automatically to match the
> + * previous case.
> + */
> +.macro alternative_else_nop_endif
> +alternative_else
> +.rept (662b-661b) / 4
> + nop
> +.endr
> +alternative_endif
> +.endm
> +
> #define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \
> alternative_insn insn1, insn2, cap, IS_ENABLED(cfg)
>
> --
> 1.9.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 4/6] pinctrl: stm32: constify gpio_chip structures
From: Linus Walleij @ 2016-09-13 8:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473596082-32690-5-git-send-email-Julia.Lawall@lip6.fr>
On Sun, Sep 11, 2016 at 2:14 PM, Julia Lawall <Julia.Lawall@lip6.fr> wrote:
> These structures are only used to copy into other structures, so declare
> them as const.
(...)
> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Patch applied, after some fuzzing.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v4 07/10] ARM: Introduce MPIDR_LEVEL_SHIFT macro
From: Christoffer Dall @ 2016-09-13 8:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473691764-29424-8-git-send-email-vladimir.murzin@arm.com>
On Mon, Sep 12, 2016 at 03:49:21PM +0100, Vladimir Murzin wrote:
> vgic-v3 driver uses architecture specific MPIDR_LEVEL_SHIFT macro to
> encode the affinity in a form compatible with ICC_SGI* registers.
> Unfortunately, that macro is missing on ARM, so let's add it.
>
> Cc: Russell King <rmk+kernel@armlinux.org.uk>
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
> arch/arm/include/asm/cputype.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
> index 1ee94c7..e2d94c1 100644
> --- a/arch/arm/include/asm/cputype.h
> +++ b/arch/arm/include/asm/cputype.h
> @@ -55,6 +55,7 @@
>
> #define MPIDR_LEVEL_BITS 8
> #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
> +#define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level)
>
I'm not sure I follow the correctness of this completely.
This is called from vgic_v3_dispatch_sgi, which takes a u64 value, which
may have something in the Aff3 field, which we now shift left 24 bits,
but that is not the Aff3 field of AArch32's MPIDR.
What is the rationale for this making sense again?
Thanks,
-Christoffer
> #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
> ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
> --
> 1.7.9.5
>
^ permalink raw reply
* [PATCH 3/6] pinctrl: mediatek: constify gpio_chip structures
From: Linus Walleij @ 2016-09-13 8:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473596082-32690-4-git-send-email-Julia.Lawall@lip6.fr>
On Sun, Sep 11, 2016 at 2:14 PM, Julia Lawall <Julia.Lawall@lip6.fr> wrote:
> These structures are only used to copy into other structures, so declare
> them as const.
(...)
> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 3/3] arm: dts: thermal: add thermal/auxadc node.
From: Matthias Brugger @ 2016-09-13 8:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473241631.8994.2.camel@mtksdaap41>
On 07/09/16 11:47, Dawei Chien wrote:
> On Tue, 2016-09-06 at 11:28 +0800, Dawei Chien wrote:
>> Dear Rui,
>>
>> On Tue, 2016-09-06 at 08:30 +0800, Zhang Rui wrote:
>>> On ?, 2016-09-06 at 08:24 +0800, Zhang Rui wrote:
>>>> On ?, 2016-08-18 at 11:50 +0800, Dawei Chien wrote:
>>>>>
>>>>> This adds the thermal controller and auxadc nodes
>>>>> to the Mediatek MT2701 dtsi file.
>>>>>
>>>>> Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
>>>>> ---
>>>>> This patch depned on:
>>>>> https://patchwork.kernel.org/patch/9249589/
>>>>> https://patchwork.kernel.org/patch/9249589/
>>>> Hmm, does this mean that I should take all these three patches and
>>>> hold
>>>> the patches in next merge window until the above patch has been
>>>> merged?
>>>>
>> Yes, this patch is base on auxadc patchset.
>>
>>> Patch 3/3 can not be applied on top of upstream kernel, so I guess it
>>> still has some other dependencies.
>>> I think I can apply patch 1, 2 first. And patch 3/3 should be handled
>>> in the dt tree.
>>
>> Sorry, this patch is also need Mediatek's clock patchset what I miss to
>> add in dependency list, I would resend this dt tree once clock patch
>> merge, or resend this for right dependency on next version, thank you.
>
> Actually, since patch1/patch2 would be OK so far, I would just only
> resend patch3 after MTK clock pathcset ready, I prefer to merge
> patch1/patch2 if possible, thank you.
>
From my side that's ok.
Regards,
Matthias
>
>>> thanks,
>>> rui
>>>> thanks,
>>>> rui
>>>>>
>>>>> ---
>>>>> arch/arm/boot/dts/mt2701.dtsi | 44
>>>>> +++++++++++++++++++++++++++++++++++++++++
>>>>> 1 file changed, 44 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/mt2701.dtsi
>>>>> b/arch/arm/boot/dts/mt2701.dtsi
>>>>> index e9150a4..cee4724 100644
>>>>> --- a/arch/arm/boot/dts/mt2701.dtsi
>>>>> +++ b/arch/arm/boot/dts/mt2701.dtsi
>>>>> @@ -87,6 +87,36 @@
>>>>> clock-output-names = "rtc32k";
>>>>> };
>>>>>
>>>>> + thermal-zones {
>>>>> + cpu_thermal: cpu_thermal {
>>>>> + polling-delay-passive = <1000>; /*
>>>>> milliseconds */
>>>>> + polling-delay = <1000>; /* milliseconds */
>>>>> +
>>>>> + thermal-sensors = <&thermal 0>;
>>>>> + sustainable-power = <1000>;
>>>>> +
>>>>> + trips {
>>>>> + threshold: trip-point at 0 {
>>>>> + temperature = <68000>;
>>>>> + hysteresis = <2000>;
>>>>> + type = "passive";
>>>>> + };
>>>>> +
>>>>> + target: trip-point at 1 {
>>>>> + temperature = <85000>;
>>>>> + hysteresis = <2000>;
>>>>> + type = "passive";
>>>>> + };
>>>>> +
>>>>> + cpu_crit: cpu_crit at 0 {
>>>>> + temperature = <115000>;
>>>>> + hysteresis = <2000>;
>>>>> + type = "critical";
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> timer {
>>>>> compatible = "arm,armv7-timer";
>>>>> interrupt-parent = <&gic>;
>>>>> @@ -222,4 +252,18 @@
>>>>> clock-names = "baud", "bus";
>>>>> status = "disabled";
>>>>> };
>>>>> +
>>>>> + thermal: thermal at 1100b000 {
>>>>> + #thermal-sensor-cells = <0>;
>>>>> + compatible = "mediatek,mt2701-thermal";
>>>>> + reg = <0 0x1100b000 0 0x1000>;
>>>>> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
>>>>> + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg
>>>>> CLK_PERI_AUXADC>;
>>>>> + clock-names = "therm", "auxadc";
>>>>> + resets = <&pericfg 0x10>;
>>>>> + reset-names = "therm";
>>>>> + mediatek,auxadc = <&auxadc>;
>>>>> + mediatek,apmixedsys = <&apmixedsys>;
>>>>> + };
>>>>> +
>>>>> };
>>>> --
>>>> To unsubscribe from this list: send the line "unsubscribe linux-pm"
>>>> in
>>>> the body of a message to majordomo at vger.kernel.org
>>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>
>
^ permalink raw reply
* [PATCH v5 07/14] drivers: acpi: iort: add support for ARM SMMU platform devices creation
From: Hanjun Guo @ 2016-09-13 8:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160913082441.GA28804@red-moon>
On 2016/9/13 16:24, Lorenzo Pieralisi wrote:
> On Tue, Sep 13, 2016 at 04:15:31PM +0800, Hanjun Guo wrote:
>
> [...]
>
>>>> +static acpi_status __init iort_match_iommu_callback(struct
>>>> acpi_iort_node *node,
>>>> + void *context)
>>>> +{
>>>> + int ret;
>>>> + struct fwnode_handle *fwnode;
>>>> +
>>>> + fwnode = iort_get_fwnode(node);
>>>> +
>>>> + if (!fwnode)
>>>> + return AE_NOT_FOUND;
>>>> +
>>>> + ret = iort_add_smmu_platform_device(fwnode, node);
>>>> + if (ret) {
>>>> + pr_err("Error in platform device creation\n");
>>>> + return AE_ERROR;
>>>> + }
>>>> +
>>>> + return AE_OK;
>>>> +}
>>>> +
>>>> +static void __init iort_smmu_init(void)
>>>> +{
>>>> + iort_scan_node(ACPI_IORT_NODE_SMMU, iort_match_iommu_callback,
>>>> NULL);
>>>> + iort_scan_node(ACPI_IORT_NODE_SMMU_V3, iort_match_iommu_callback,
>>>> NULL);
>>>
>>> Since iort_scan_node() returns after the first successful match it finds,
>>> only the first SMMU_V3 in my IORT is being enumerated. I think you need
>>> to go back to the "iterator" like approach you had been using or make
>>> iort_match_iommu_callback() always return a non-AE_OK value so the scan
>>> continues and has a chance to visit all of the SMMU_V3 nodes.
>>
>> Please use the updated version of IORT patch (aka Tomasz's v11)
>> then things will work fine.
>
> Nate is right, I was too keen on using iort_scan_node(), it does
> not really work here (unless as he said I return a value !AE_OK in
> the callback, which is horrible), I reverted back to the iterator
> approach and I can push out a fixed up branch if useful before next
> posting.
Ah, sorry, I just noticed "the first SMMU_V3" which is pretty similar
with the second problem which is noticed by Nate...
Thanks
Hanjun
^ permalink raw reply
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