* [PATCH v7 00/22] Generic DT bindings for PCI IOMMUs and ARM SMMU
From: Auger Eric @ 2016-09-13 12:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1473695704.git.robin.murphy@arm.com>
Hi Robin
On 12/09/2016 18:13, Robin Murphy wrote:
> Hi all,
>
> To any more confusing fixups and crazily numbered extra patches, here's
> a quick v7 with everything rebased into the right order. The significant
> change this time is to implement iommu_fwspec properly from the start,
> which ends up being far simpler and more robust than faffing about
> introducing it somewhere 'less intrusive' to move toward core code later.
>
> New branch in the logical place:
>
> git://linux-arm.org/linux-rm iommu/generic-v7
I just tested your branch on AMD overdrive *without* updating the device
tree description according to the new syntax and I get a kernel oops.
See logs attached. Continuing my investigations ...
Best Regards
Eric
>
> Robin.
>
> Mark Rutland (1):
> Docs: dt: add PCI IOMMU map bindings
>
> Robin Murphy (21):
> of/irq: Break out msi-map lookup (again)
> iommu/of: Handle iommu-map property for PCI
> iommu: Introduce iommu_fwspec
> Docs: dt: document ARM SMMUv3 generic binding usage
> iommu/arm-smmu: Fall back to global bypass
> iommu/arm-smmu: Implement of_xlate() for SMMUv3
> iommu/arm-smmu: Support non-PCI devices with SMMUv3
> iommu/arm-smmu: Set PRIVCFG in stage 1 STEs
> iommu/arm-smmu: Handle stream IDs more dynamically
> iommu/arm-smmu: Consolidate stream map entry state
> iommu/arm-smmu: Keep track of S2CR state
> iommu/arm-smmu: Refactor mmu-masters handling
> iommu/arm-smmu: Streamline SMMU data lookups
> iommu/arm-smmu: Add a stream map entry iterator
> iommu/arm-smmu: Intelligent SMR allocation
> iommu/arm-smmu: Convert to iommu_fwspec
> Docs: dt: document ARM SMMU generic binding usage
> iommu/arm-smmu: Wire up generic configuration support
> iommu/arm-smmu: Set domain geometry
> iommu/dma: Add support for mapping MSIs
> iommu/dma: Avoid PCI host bridge windows
>
> .../devicetree/bindings/iommu/arm,smmu-v3.txt | 8 +-
> .../devicetree/bindings/iommu/arm,smmu.txt | 63 +-
> .../devicetree/bindings/pci/pci-iommu.txt | 171 ++++
> arch/arm64/mm/dma-mapping.c | 2 +-
> drivers/gpu/drm/exynos/exynos_drm_iommu.h | 2 +-
> drivers/iommu/Kconfig | 2 +-
> drivers/iommu/arm-smmu-v3.c | 386 +++++----
> drivers/iommu/arm-smmu.c | 962 ++++++++++-----------
> drivers/iommu/dma-iommu.c | 161 +++-
> drivers/iommu/iommu.c | 56 ++
> drivers/iommu/of_iommu.c | 52 +-
> drivers/irqchip/irq-gic-v2m.c | 3 +
> drivers/irqchip/irq-gic-v3-its.c | 3 +
> drivers/of/irq.c | 78 +-
> drivers/of/of_pci.c | 102 +++
> include/linux/device.h | 3 +
> include/linux/dma-iommu.h | 12 +-
> include/linux/iommu.h | 38 +
> include/linux/of_pci.h | 10 +
> 19 files changed, 1323 insertions(+), 791 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/pci-iommu.txt
>
-------------- next part --------------
[ 3.185447] CPU features: detected feature: 32-bit EL0 Support
[ 3.185455] CPU: All CPU(s) started at EL2
[ 3.185475] alternatives: patching kernel code
[ 3.188549] devtmpfs: initialized
[ 3.189484] SMBIOS 3.0.0 present.
[ 3.189570] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 3.189750] pinctrl core: initialized pinctrl subsystem
[ 3.190113] NET: Registered protocol family 16
[ 3.205134] cpuidle: using governor menu
[ 3.205292] arm-smmu: deprecated "mmu-masters" DT property in use; DMA API support unavailable
[ 3.205319] arm-smmu e0600000.smmu: probing hardware configuration...
[ 3.205326] arm-smmu e0600000.smmu: SMMUv1 with:
[ 3.205334] arm-smmu e0600000.smmu: stage 2 translation
[ 3.205341] arm-smmu e0600000.smmu: non-coherent table walk
[ 3.205348] arm-smmu e0600000.smmu: (IDR0.CTTW overridden by dma-coherent property)
[ 3.205358] arm-smmu e0600000.smmu: stream matching with 32 register groups, mask 0x7fff
[ 3.205369] arm-smmu e0600000.smmu: 8 context banks (8 stage-2 only)
[ 3.205377] arm-smmu e0600000.smmu: Supported page sizes: 0x60211000
[ 3.205384] arm-smmu e0600000.smmu: Stage-2: 40-bit IPA -> 40-bit PA
[ 3.205489] arm-smmu: deprecated "mmu-masters" DT property in use; DMA API support unavailable
[ 3.205512] arm-smmu e0800000.smmu: probing hardware configuration...
[ 3.205519] arm-smmu e0800000.smmu: SMMUv1 with:
[ 3.205525] arm-smmu e0800000.smmu: stage 2 translation
[ 3.205533] arm-smmu e0800000.smmu: non-coherent table walk
[ 3.205539] arm-smmu e0800000.smmu: (IDR0.CTTW overridden by dma-coherent property)
[ 3.205550] arm-smmu e0800000.smmu: stream matching with 32 register groups, mask 0x7fff
[ 3.205560] arm-smmu e0800000.smmu: 8 context banks (8 stage-2 only)
[ 3.205567] arm-smmu e0800000.smmu: Supported page sizes: 0x60211000
[ 3.205574] arm-smmu e0800000.smmu: Stage-2: 40-bit IPA -> 40-bit PA
[ 3.205670] arm-smmu: deprecated "mmu-masters" DT property in use; DMA API support unavailable
[ 3.205692] arm-smmu e0a00000.smmu: probing hardware configuration...
[ 3.205699] arm-smmu e0a00000.smmu: SMMUv1 with:
[ 3.205705] arm-smmu e0a00000.smmu: stage 2 translation
[ 3.205712] arm-smmu e0a00000.smmu: non-coherent table walk
[ 3.205719] arm-smmu e0a00000.smmu: (IDR0.CTTW overridden by dma-coherent property)
[ 3.205729] arm-smmu e0a00000.smmu: stream matching with 32 register groups, mask 0x7fff
[ 3.205738] arm-smmu e0a00000.smmu: 8 context banks (8 stage-2 only)
[ 3.205745] arm-smmu e0a00000.smmu: Supported page sizes: 0x60211000
[ 3.205752] arm-smmu e0a00000.smmu: Stage-2: 40-bit IPA -> 40-bit PA
[ 3.205801] vdso: 2 pages (1 code @ ffff0000088c6000, 1 data @ ffff000008dd4000)
[ 3.205814] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 3.206098] DMA: preallocated 256 KiB pool for atomic allocations
[ 3.206186] Serial: AMBA PL011 UART driver
[ 3.207040] e1010000.serial: ttyAMA0 at MMIO 0xe1010000 (irq = 20, base_baud = 0) is a PL011 rev3
[ 3.995110] console [ttyAMA0] enabled
[ 3.999198] OF: amba_device_add() failed (-19) for /smb/gpio at e0020000
[ 4.006287] iommu: Adding device e0700000.xgmac to group 0
[ 4.027943] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 4.034596] ACPI: Interpreter disabled.
[ 4.038537] Unable to handle kernel paging request at virtual address ffffff8030010000
[ 4.046452] pgd = ffff000008f61000
[ 4.049845] [ffffff8030010000] *pgd=0000000000000000
[ 4.054807] Internal error: Oops: 96000004 [#1] PREEMPT SMP
[ 4.060371] Modules linked in:
[ 4.063419] CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.8.0-rc4-26782-g83cf8c5 #14
[ 4.070982] Hardware name: Default string Default string/Default string, BIOS WOD5527X 05/25/2015
[ 4.079846] task: ffff8003ec108000 task.stack: ffff8003ec110000
[ 4.085761] PC is at __arm_v7s_map+0x1cc/0x378
[ 4.090196] LR is at __arm_v7s_map+0xb4/0x378
[ 4.094543] pc : [<ffff000008522604>] lr : [<ffff0000085224ec>] pstate: 20000045
[ 4.101931] sp : ffff8003ec113bf0
[ 4.105236] x29: ffff8003ec113bf0 x28: 0000000000001000
[ 4.110543] x27: ffffff8030010000 x26: ffff8003eb47e518
[ 4.115850] x25: 0000000000000001 x24: ffffff8030010004
[ 4.121155] x23: 000000000000000c x22: ffff8003eb47e500
[ 4.126461] x21: 0000000000001000 x20: 0000000000000000
[ 4.131767] x19: ffffff8030010000 x18: 000000000000000e
[ 4.137072] x17: 00000000000040ff x16: 0000000000000000
[ 4.142379] x15: 000000000000008c x14: 0000000000000006
[ 4.147684] x13: 0000000000000007 x12: 0000000000000020
[ 4.152990] x11: 0000000000000003 x10: ffff000008dd6000
[ 4.158295] x9 : 0000000000000004 x8 : 0000000000000e71
[ 4.163601] x7 : ffffff8030010000 x6 : ffffff8030010000
[ 4.168907] x5 : 0000000000000002 x4 : 0000000000000000
[ 4.174212] x3 : 0000000000000001 x2 : 0000000000000001
[ 4.179518] x1 : 0000000000000e7d x0 : 0000000000000004
[ 4.184824]
[ 4.186306] Process swapper/0 (pid: 1, stack limit = 0xffff8003ec110020)
[ 4.192998] Stack: (0xffff8003ec113bf0 to 0xffff8003ec114000)
[ 4.198735] 3be0: ffff8003ec113c70 ffff0000085224ec
[ 4.206558] 3c00: 0000000000001000 0000000000000000 0000000000000000 ffff8003eb47e500
[ 4.214381] 3c20: 0000000000000014 0000000000001000 0000000000000000 ffff8003eb47e518
[ 4.222203] 3c40: ffff800030008000 0000000000001000 0000000000000000 ffff8003eb47e518
[ 4.230026] 3c60: ffff8003ec113c70 ffffff8030010000 ffff8003ec113cf0 ffff0000085227f8
[ 4.237848] 3c80: ffff8003eb47e568 0000000000001000 0000000000000000 000000000000002a
[ 4.245671] 3ca0: 0000000000000001 0000000000001000 0000000000000001 ffff8003ec113d88
[ 4.253493] 3cc0: ffff8003ec113d80 0000000000001000 0000000000000002 000000000000000f
[ 4.261315] 3ce0: ffff800030010000 ffff000008bc2520 ffff8003ec113d20 ffff000008d0036c
[ 4.269137] 3d00: ffff8003eb47e568 000000000000000c 0000000000000000 000000000000002a
[ 4.276960] 3d20: ffff8003ec113dd0 ffff00000808335c ffff000008d0019c ffff8003ec110000
[ 4.284782] 3d40: 0000000000000000 ffff000008f1c000 ffff000008cc0498 ffff000008cad0a0
[ 4.292605] 3d60: ffff000008d2ab20 ffff000008f1c000 0000000000000109 0000000000000000
[ 4.300427] 3d80: 0000000000000001 0000000001111000 0000002000000020 ffff000008e750b0
[ 4.308249] 3da0: 0000000000000000 000000003000806a 4000400000000020 00000000800b8204
[ 4.316072] 3dc0: 0000000000000000 0000000000000000 ffff8003ec113e40 ffff000008cc0d54
[ 4.323894] 3de0: ffff000008d95df0 ffff000008d2aa70 0000000000000004 ffff000008f1c000
[ 4.331717] 3e00: ffff8003ec113e00 ffff000008ef8f38 0000000000000000 0000000400000004
[ 4.339539] 3e20: ffff000008ef8ec0 0000000000000000 ffff000008cc0498 ffff000008cad0a0
[ 4.347361] 3e40: ffff8003ec113ea0 ffff0000088a7f88 ffff0000088a7f78 0000000000000000
[ 4.355183] 3e60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 4.363006] 3e80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 4.370828] 3ea0: 0000000000000000 ffff000008082e90 ffff0000088a7f78 0000000000000000
[ 4.378650] 3ec0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 4.386473] 3ee0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 4.394295] 3f00: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 4.402117] 3f20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 4.409940] 3f40: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 4.417762] 3f60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 4.425584] 3f80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 4.433406] 3fa0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 4.441229] 3fc0: 0000000000000000 0000000000000005 0000000000000000 0000000000000000
[ 4.449051] 3fe0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 4.456873] Call trace:
[ 4.459310] Exception stack(0xffff8003ec113a20 to 0xffff8003ec113b50)
[ 4.465742] 3a20: ffffff8030010000 0001000000000000 ffff8003ec113bf0 ffff000008522604
[ 4.473565] 3a40: 0000000002088021 ffff8003eb47e518 ffff8003fff4db00 ffff8003ffe81400
[ 4.481388] 3a60: ffff000008dd5000 0208802100008001 0000000000000000 0000000000000000
[ 4.489210] 3a80: ffff8003ec113b80 ffff00000820247c 0000000000000040 0000000000000000
[ 4.497032] 3aa0: ffff8003ec110000 0000000000000003 0000000002088021 ffff000008521cbc
[ 4.504854] 3ac0: 0000000000000004 0000000000000e7d 0000000000000001 0000000000000001
[ 4.512677] 3ae0: 0000000000000000 0000000000000002 ffffff8030010000 ffffff8030010000
[ 4.520499] 3b00: 0000000000000e71 0000000000000004 ffff000008dd6000 0000000000000003
[ 4.528321] 3b20: 0000000000000020 0000000000000007 0000000000000006 000000000000008c
[ 4.536143] 3b40: 0000000000000000 00000000000040ff
[ 4.541012] [<ffff000008522604>] __arm_v7s_map+0x1cc/0x378
[ 4.546489] [<ffff0000085224ec>] __arm_v7s_map+0xb4/0x378
[ 4.551879] [<ffff0000085227f8>] arm_v7s_map+0x48/0xc4
[ 4.557010] [<ffff000008d0036c>] arm_v7s_do_selftests+0x1d0/0x4b4
[ 4.563096] [<ffff00000808335c>] do_one_initcall+0x38/0x12c
[ 4.568662] [<ffff000008cc0d54>] kernel_init_freeable+0x1a8/0x24c
[ 4.574748] [<ffff0000088a7f88>] kernel_init+0x10/0xfc
[ 4.579878] [<ffff000008082e90>] ret_from_fork+0x10/0x40
[ 4.585181] Code: aa1b03f3 8b180378 f9003fa7 710004bf (b9400266)
[ 4.591280] ---[ end trace d091d1618c2826ea ]---
[ 4.595897] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[ 4.595897]
[ 4.605024] SMP: stopping secondary CPUs
[ 4.608942] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[ 4.608942]
^ permalink raw reply
* [PATCH v1 1/2] ARM: dts: add rockchip PX3 Evaluation board
From: Andreas Färber @ 2016-09-13 12:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473529440-6202-1-git-send-email-andy.yan@rock-chips.com>
Hi Andy,
This patch didn't make it to linux-rockchip list somehow...
Not sure why I'm CC'ed, I don't have access to such a board to check, so
just a couple formal nitpicks:
Am 10.09.2016 um 19:44 schrieb Andy Yan:
> PX3 EVB is designed by Rockchip for automotive field,
> which intergrated with CVBS(TP2825)/MIPI DSI/LVDS/HDMI
"integrated"
but the grammar is somewhat incorrect with "which" referring to field -
I assume you meant "with integrated CVBS..."?
> video input/output interface, WIFI/BT/GPS(on a module
Also please always leave a space before an opening parenthesis in
English text. Similarly above, spaces around "/" would help recognize
that MIPI DSI belongs together rather than being two lists.
If nothing else applies below then maybe Heiko can edit it for you?
> named S500 which based on MT6620), Gsensor BMA250E and
> light&proximity sensor STK3410.
>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>
> ---
>
> Changes in v1:
> - board rename
> - add vendor prefix for i2c interfaced sensors
> - use stdout-path to set the default console
>
> Documentation/devicetree/bindings/arm/rockchip.txt | 4 +
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/rk3188-px3-evb.dts | 337 +++++++++++++++++++++
> 3 files changed, 342 insertions(+)
> create mode 100644 arch/arm/boot/dts/rk3188-px3-evb.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
> index 6668645..6da3881 100644
> --- a/Documentation/devicetree/bindings/arm/rockchip.txt
> +++ b/Documentation/devicetree/bindings/arm/rockchip.txt
> @@ -21,6 +21,10 @@ Rockchip platforms device tree bindings
> Required root node properties:
> - compatible = "radxa,rock", "rockchip,rk3188";
>
> +- Rockchip PX3 Evaluation board:
> + Required root node properties:
> + - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
How compatible is PX3 with RK3188? It is a separate SoC product:
http://www.rock-chips.com/a/en/products/rkpower/2015/1125/730.html
Wondering whether or not to drop the third compatible string.
> +
> - Radxa Rock2 Square board:
> Required root node properties:
> - compatible = "radxa,rock2-square", "rockchip,rk3288";
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index faacd52..88d27a2 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -620,6 +620,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
> rk3066a-marsboard.dtb \
> rk3066a-rayeager.dtb \
> rk3188-radxarock.dtb \
> + rk3188-px3-evb.dtb \
Affects file naming as well: px3-evb.dtb?
> rk3228-evb.dtb \
> rk3229-evb.dtb \
> rk3288-evb-act8846.dtb \
> diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts
> new file mode 100644
> index 0000000..f6bc738
> --- /dev/null
> +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts
> @@ -0,0 +1,337 @@
> +/*
> + * Copyright (c) 2016 Andy Yan <andy.yan@rock-chips.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/input/input.h>
> +#include "rk3188.dtsi"
I'm surprised there is no [rk3188-]px3.dtsi here! Surely some automotive
vendor may design their own board with it and should have at least the
two trailing compatible strings pre-set.
> +
> +/ {
> + model = "Rockchip PX3-EVB";
> + compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
> +
> + chosen {
> + stdout-path = "serial2:115200n8";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x60000000 0x80000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + autorepeat;
> +
> + power {
> + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + label = "GPIO Key Power";
> + linux,input-type = <1>;
> + wakeup-source;
> + debounce-interval = <100>;
> + };
> + };
> +
> + vcc_sys: vsys-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vsys";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-boot-on;
> + };
> +};
> +
> +&cpu0 {
> + cpu0-supply = <&vdd_cpu>;
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + /* Accelerometer */
Space after tab intentional?
> + bma250 at 18 {
> + compatible = "bosch,bma250";
> + reg = <0x18>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + stk3410 at 48 {
> + compatible = "sensortek,STK3310";
> + reg = <0x48>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
> + };
Generally it is undesired to repeat the compatible name as node name -
did you compare other .dts files? (e.g., accelerometer at 18 would be
self-documenting) If this is a copy from an existing .dts then please
ignore this comment.
> +};
> +
> +&i2c1 {
> + status = "okay";
> + clock-frequency = <400000>;
Insert white line?
> + rk808: pmic at 1c {
> + compatible = "rockchip,rk818";
> + reg = <0x1c>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
> + rockchip,system-power-controller;
> + wakeup-source;
> + #clock-cells = <1>;
> + clock-output-names = "xin32k", "rk808-clkout2";
> +
> + vcc1-supply = <&vcc_sys>;
> + vcc2-supply = <&vcc_sys>;
> + vcc3-supply = <&vcc_sys>;
> + vcc4-supply = <&vcc_sys>;
> + vcc6-supply = <&vcc_sys>;
> + vcc7-supply = <&vcc_sys>;
> + vcc8-supply = <&vcc_io>;
> + vcc9-supply = <&vcc_io>;
> +
> + regulators {
> + vdd_cpu: DCDC_REG1 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-name = "vdd_arm";
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdd_gpu: DCDC_REG2 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <1250000>;
> + regulator-name = "vdd_gpu";
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1000000>;
> + };
> + };
> +
> + vcc_ddr: DCDC_REG3 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-name = "vcc_ddr";
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + vcc_io: DCDC_REG4 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc_io";
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + vcc_cif: LDO_REG1 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc_cif";
> + };
> +
> + vcc_jetta33: LDO_REG2 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc_jetta33";
> + };
> +
> + vdd_10: LDO_REG3 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-name = "vdd_10";
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1000000>;
> + };
> + };
> +
> + lvds_12: LDO_REG4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "lvds_12";
> + };
> +
> + lvds_25: LDO_REG5 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "lvds_25";
> + };
> +
> + cif_18: LDO_REG6 {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-name = "cif_18";
> + };
> +
> + vcc_sd: LDO_REG7 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc_sd";
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + wl_18: LDO_REG8 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "wl_18";
> + };
> +
> + lcd_33: SWITCH_REG1 {
> + regulator-name = "lcd_33";
> + };
> + };
> + };
> +
> +};
> +
> +&i2c2 {
> + gsl1680: touchscreen at 40 {
> + compatible = "silead,gsl1680";
> + reg = <0x40>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
> + power-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
> + touchscreen-size-x = <800>;
> + touchscreen-size-y = <1280>;
> + silead,max-fingers = <5>;
> + };
> +};
> +
> +&emmc {
> + bus-width = <8>;
> + cap-mmc-highspeed;
> + disable-wp;
> + non-removable;
> + num-slots = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>;
> + status = "okay";
> +};
> +
> +&mmc0 {
> + num-slots = <1>;
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
> + vmmc-supply = <&vcc_sd>;
> +
> + bus-width = <4>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + disable-wp;
> +};
> +
> +&pwm1 {
> + status = "okay";
> +};
> +
> +&pwm2 {
> + status = "okay";
> +};
> +
> +&pwm3 {
> + status = "okay";
> +};
> +
> +&pinctrl {
> + pcfg_output_low: pcfg-output-low {
> + output-low;
> + };
> +
> + usb {
> + host_vbus_drv: host-vbus-drv {
> + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + otg_vbus_drv: otg-vbus-drv {
> + rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> +
> +&usbphy {
> + status = "okay";
> +};
> +
> +&usb_host {
> + status = "okay";
> +};
> +
> +&usb_otg {
> + status = "okay";
> +};
> +
> +&wdt {
> + status = "okay";
> +};
Otherwise formally looks fine.
Cheers,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply
* [GIT PULL] Immutable branch between MFD and Regulator due for the v4.9 merge window
From: Lee Jones @ 2016-09-13 12:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160827075544.26316-4-wens@csie.org>
Mark,
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git tags/ib-mfd-regulator-v4.9
for you to fetch changes up to 2ca342d391e3d8b56ed64626db8cfba8101b7c1d:
regulator: axp20x: Support AXP806 variant (2016-09-13 12:49:45 +0100)
----------------------------------------------------------------
Immutable branch between MFD and Regulator due for the v4.9 merge window
----------------------------------------------------------------
Chen-Yu Tsai (1):
regulator: axp20x: Support AXP806 variant
drivers/regulator/axp20x-regulator.c | 118 ++++++++++++++++++++++++++++++++---
1 file changed, 111 insertions(+), 7 deletions(-)
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2 1/2] ARM: dts: imx6ul: Add DTS for liteSOM module
From: Sébastien Szymanski @ 2016-09-13 11:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160913094951.26394-1-m.niestroj@grinn-global.com>
Hello,
On 09/13/2016 11:49 AM, Marcin Niestroj wrote:
> +
> +&cpu0 {
> + arm-supply = <®_arm>;
> + soc-supply = <®_soc>;
> +};
These supplies are already set in the imx6ul.dtsi file.
Regards,
--
S?bastien Szymanski
^ permalink raw reply
* [PATCH v11 5/8] clocksource/drivers/arm_arch_timer: Simplify ACPI support code.
From: Fu Wei @ 2016-09-13 11:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57D7E543.3060301@codeaurora.org>
Hi Timur
On 09/13/2016 07:38 PM, Timur Tabi wrote:
> Fu Wei wrote:
>> I have prepared v12 (rebase to rc6 and on the top of IORT v11),
>> should I send it now
>
> Yes.
>
> Please don't wait to release new versions of your patches. Time is running out to get these into 4.9.
>
yes, v12 is posted
working on v13(improving memory-mapped timer code following Marc's suggestion)
--
Best regards,
Fu Wei
Software Engineer
Red Hat
^ permalink raw reply
* [PATCH] dmaengine: cleanup with list_first_entry_or_null()
From: Linus Walleij @ 2016-09-13 11:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473703697-903-1-git-send-email-yamada.masahiro@socionext.com>
On Mon, Sep 12, 2016 at 8:08 PM, Masahiro Yamada
<yamada.masahiro@socionext.com> wrote:
> The combo of list_empty() check and return list_first_entry()
> can be replaced with list_first_entry_or_null().
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Excellent deep semantics patch!
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v11 5/8] clocksource/drivers/arm_arch_timer: Simplify ACPI support code.
From: Timur Tabi @ 2016-09-13 11:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CADyBb7v-b1bKGBdH6J78UhfCcQd=BJLFoZ16GNgmrd2EucjYDA@mail.gmail.com>
Fu Wei wrote:
> I have prepared v12 (rebase to rc6 and on the top of IORT v11),
> should I send it now
Yes.
Please don't wait to release new versions of your patches. Time is
running out to get these into 4.9.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the
Code Aurora Forum, hosted by The Linux Foundation.
^ permalink raw reply
* [PATCH V6 2/5] PCI/ACPI: Check platform specific ECAM quirks
From: Dongdong Liu @ 2016-09-13 11:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <bac9f822-ce0a-7070-94df-4d66fc30f774@semihalf.com>
Hi Tomasz
? 2016/9/13 14:32, Tomasz Nowicki ??:
> Hi Liu,
>
> On 13.09.2016 04:36, Dongdong Liu wrote:
>> Hi Tomasz
>>
>> ? 2016/9/10 3:24, Tomasz Nowicki ??:
>>> Some platforms may not be fully compliant with generic set of PCI config
>>> accessors. For these cases we implement the way to overwrite CFG
>>> accessors
>>> set and configuration space range.
>>>
>>> In first place pci_mcfg_parse() saves machine's IDs and revision number
>>> (these come from MCFG header) in order to match against known quirk
>>> entries.
>>> Then the algorithm traverses available quirk list (static array),
>>> matches against <oem_id, oem_table_id, rev, domain, bus number range> and
>>> returns custom PCI config ops and/or CFG resource structure.
>>>
>>> When adding new quirk there are two possibilities:
>>> 1. Override default pci_generic_ecam_ops ops but CFG resource comes
>>> from MCFG
>>> { "OEM_ID", "OEM_TABLE_ID", <REV>, <DOMAIN>, <BUS_NR>, &foo_ops,
>>> MCFG_RES_EMPTY },
>>> 2. Override default pci_generic_ecam_ops ops and CFG resource. For
>>> this case
>>> it is also allowed get CFG resource from quirk entry w/o having it in
>>> MCFG.
>>> { "OEM_ID", "OEM_TABLE_ID", <REV>, <DOMAIN>, <BUS_NR>, &boo_ops,
>>> DEFINE_RES_MEM(START, SIZE) },
>>>
>>> pci_generic_ecam_ops and MCFG entries will be used for platforms
>>> free from quirks.
>>>
>>> Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
>>> Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
>>> Signed-off-by: Christopher Covington <cov@codeaurora.org>
>>> ---
>>> drivers/acpi/pci_mcfg.c | 80
>>> +++++++++++++++++++++++++++++++++++++++++++++----
>>> 1 file changed, 74 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
>>> index ffcc651..2b8acc7 100644
>>> --- a/drivers/acpi/pci_mcfg.c
>>> +++ b/drivers/acpi/pci_mcfg.c
>>> @@ -32,6 +32,59 @@ struct mcfg_entry {
>>> u8 bus_start;
>>> u8 bus_end;
>>> };
>>> +struct mcfg_fixup {
>>> + char oem_id[ACPI_OEM_ID_SIZE + 1];
>>> + char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
>>> + u32 oem_revision;
>>> + u16 seg;
>>> + struct resource bus_range;
>>> + struct pci_ecam_ops *ops;
>>> + struct resource cfgres;
>>> +};
>>> +
>>> +#define MCFG_DOM_ANY (-1)
>>> +#define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
>>> + ((end) - (start) + 1), \
>>> + NULL, IORESOURCE_BUS)
>>> +#define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
>>> +#define MCFG_RES_EMPTY DEFINE_RES_NAMED(0, 0, NULL, 0)
>>> +
>>> +static struct mcfg_fixup mcfg_quirks[] = {
>>> +/* { OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
>>> +};
>>> +
>>> +static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
>>> +static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
>>> +static u32 mcfg_oem_revision;
>>> +
>>> +static void pci_mcfg_match_quirks(struct acpi_pci_root *root,
>>> + struct resource *cfgres,
>>> + struct pci_ecam_ops **ecam_ops)
>>> +{
>>> + struct mcfg_fixup *f;
>>> + int i;
>>> +
>>> + /*
>>> + * First match against PCI topology <domain:bus> then use OEM ID,
>>> OEM
>>> + * table ID, and OEM revision from MCFG table standard header.
>>> + */
>>> + for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++,
>>> f++) {
>>> + if (f->seg == root->segment &&
>>
>> why not use MCFG_DOM_RANGE, I think MCFG_DOM_RANGE is better.
>> if drop MCFG_DOM_RANGE, mcfg_quirks[] will be more complex.
>>
>> static struct mcfg_fixup mcfg_quirks[] = {
>> /* { OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
>> #ifdef CONFIG_PCI_HOST_THUNDER_ECAM
>> /* SoC pass1.x */
>> { "CAVIUM", "THUNDERX", 2, 0, MCFG_BUS_ANY, &pci_thunder_ecam_ops,
>> MCFG_RES_EMPTY},
>> { "CAVIUM", "THUNDERX", 2, 1, MCFG_BUS_ANY, &pci_thunder_ecam_ops,
>> MCFG_RES_EMPTY},
>> { "CAVIUM", "THUNDERX", 2, 2, MCFG_BUS_ANY, &pci_thunder_ecam_ops,
>> MCFG_RES_EMPTY},
>> { "CAVIUM", "THUNDERX", 2, 3, MCFG_BUS_ANY, &pci_thunder_ecam_ops,
>> MCFG_RES_EMPTY},
>> { "CAVIUM", "THUNDERX", 2, 10, MCFG_BUS_ANY, &pci_thunder_ecam_ops,
>> MCFG_RES_EMPTY},
>> { "CAVIUM", "THUNDERX", 2, 11, MCFG_BUS_ANY, &pci_thunder_ecam_ops,
>> MCFG_RES_EMPTY},
>> { "CAVIUM", "THUNDERX", 2, 12, MCFG_BUS_ANY, &pci_thunder_ecam_ops,
>> MCFG_RES_EMPTY},
>> { "CAVIUM", "THUNDERX", 2, 13, MCFG_BUS_ANY, &pci_thunder_ecam_ops,
>> MCFG_RES_EMPTY},
>> #endif
>> .....
>> };
>>
>> As PATCH v5 we only need define mcfg_quirks as below, It looks better.
>> static struct pci_cfg_fixup mcfg_quirks[] __initconst = {
>> /* { OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, pci_ops, init_hook
>> }, */
>> #ifdef CONFIG_PCI_HOST_THUNDER_PEM
>> /* Pass2.0 */
>> { "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(4, 9), MCFG_BUS_ANY, NULL,
>> thunder_pem_cfg_init },
>> { "CAVIUM", "THUNDERX", 1, MCFG_DOM_RANGE(14, 19), MCFG_BUS_ANY, NULL,
>> thunder_pem_cfg_init },
>> #endif
>> #ifdef CONFIG_PCI_HISI_ACPI
>> { "HISI ", "HIP05 ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
>> NULL, hisi_pcie_acpi_hip05_init},
>> { "HISI ", "HIP06 ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
>> NULL, hisi_pcie_acpi_hip06_init},
>> { "HISI ", "HIP07 ", 0, MCFG_DOM_RANGE(0, 15), MCFG_BUS_ANY,
>> NULL, hisi_pcie_acpi_hip07_init},
>> #endif
>> };
>
> Note this series disallow hisi_pcie_acpi_hip07_init() call. According to the Bjorn suggestion I rework quirk code to override ops and CFG resources only. Giving that I do not see the way to use MCFG_DOM_RANGE macro. For HISI you would need to get CFG range for each possible case:
>
> #ifdef CONFIG_PCI_HISI_ACPI
> { "HISI ", "HIP05 ", 0, 0, MCFG_BUS_ANY, &hisi_pcie_ops,
> DEFINE_RES_MEM(start0, size0)},
> { "HISI ", "HIP05 ", 0, 1, MCFG_BUS_ANY, &hisi_pcie_ops,
> DEFINE_RES_MEM(start1, size1)},
> { "HISI ", "HIP05 ", 0, 2, MCFG_BUS_ANY, &hisi_pcie_ops,
> DEFINE_RES_MEM(start2, size2)},
> { "HISI ", "HIP05 ", 0, 3, MCFG_BUS_ANY, &hisi_pcie_ops,
> DEFINE_RES_MEM(start3, size3)},
> [...]
> #endif
>
> Indeed there are more entries here but you do not have to define the same resource array in driver.
Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.
RC config resource with hardcode as DEFINE_RES_MEM(0xb0070000, SZ_4K),
EP config resource we get it from MCFG table.
So we need to override ops, but config resource we only need to hardcode with RC config resource.
Our host controller ACPI support patch can be found:
https://lkml.org/lkml/2016/8/31/340
This patch is based on RFC V5 quirk mechanism.
Based on V6 quirk mechanism, we have to change it as below:
#ifdef CONFIG_PCI_HISI_ACPI
{ "HISI ", "HIP05 ", 0, 0, MCFG_BUS_ANY, &hisi_pcie_hip05_ops,
MCFG_RES_EMPTY},
{ "HISI ", "HIP05 ", 0, 1, MCFG_BUS_ANY, &hisi_pcie_hip05_ops,
MCFG_RES_EMPTY},
{ "HISI ", "HIP05 ", 0, 2, MCFG_BUS_ANY, &hisi_pcie_hip05_ops,
MCFG_RES_EMPTY},
{ "HISI ", "HIP05 ", 0, 3, MCFG_BUS_ANY, &hisi_pcie_hip05_ops,
MCFG_RES_EMPTY},
{ "HISI ", "HIP06 ", 0, 0, MCFG_BUS_ANY, &hisi_pcie_hip06_ops,
MCFG_RES_EMPTY},
{ "HISI ", "HIP06 ", 0, 1, MCFG_BUS_ANY, &hisi_pcie_hip06_ops,
MCFG_RES_EMPTY},
{ "HISI ", "HIP06 ", 0, 2, MCFG_BUS_ANY, &hisi_pcie_hip06_ops,
MCFG_RES_EMPTY},
{ "HISI ", "HIP06 ", 0, 3, MCFG_BUS_ANY, &hisi_pcie_hip06_ops,
MCFG_RES_EMPTY},
{ "HISI ", "HIP07 ", 0, 0, MCFG_BUS_ANY, &hisi_pcie_hip07_ops,
MCFG_RES_EMPTY},
{ "HISI ", "HIP07 ", 0, 1, MCFG_BUS_ANY, &hisi_pcie_hip07_ops,
MCFG_RES_EMPTY},
....
{ "HISI ", "HIP07 ", 0, 15, MCFG_BUS_ANY, &hisi_pcie_hip07_ops,
MCFG_RES_EMPTY},
#endif
struct pci_ecam_ops hisi_pci_hip05_ops = {
.bus_shift = 20,
.init = hisi_pci_hip05_init,
.pci_ops = {
.map_bus = pci_ecam_map_bus,
.read = hisi_pcie_acpi_rd_conf,
.write = hisi_pcie_acpi_wr_conf,
}
};
struct pci_ecam_ops hisi_pci_hip06_ops = {
.bus_shift = 20,
.init = hisi_pci_hip06_init,
.pci_ops = {
.map_bus = pci_ecam_map_bus,
.read = hisi_pcie_acpi_rd_conf,
.write = hisi_pcie_acpi_wr_conf,
}
};
hisi_pci_hipxx_init function is used to get RC config resource with hardcode.
.....
So I hope we can use MCFG_DOM_RANGE, Then I can change it as below.
#ifdef CONFIG_PCI_HISI_ACPI
{ "HISI ", "HIP05 ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
&hisi_pcie_hip05_ops, MCFG_RES_EMPTY},
{ "HISI ", "HIP06 ", 0, MCFG_DOM_RANGE(0, 3), MCFG_BUS_ANY,
&hisi_pcie_hip06_ops, MCFG_RES_EMPTY},
{ "HISI ", "HIP07 ", 0, MCFG_DOM_RANGE(0, 15), MCFG_BUS_ANY,
&hisi_pcie_hip07_ops, MCFG_RES_EMPTY},
#endif
Thanks
Dongdong
>
> Thanks,
> Tomasz
>
> .
>
^ permalink raw reply
* [PATCH v2 1/2] pinctrl: meson-gxbb: add the missing SDIO interrupt pin
From: Linus Walleij @ 2016-09-13 11:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160911123903.20027-2-martin.blumenstingl@googlemail.com>
On Sun, Sep 11, 2016 at 2:39 PM, Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
> This adds the SDIO interrupt pin which can be used by sd_emmc_a.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
>
> Fixes: 29885a656511 ("pinctrl: meson-gxbb: add the pins for the
> SDIO/sd_emmc_a controller")
Patch applied with Kevin's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* ARM, SoC: About the use DT-defined properties by 3rd-party drivers
From: Timur Tabi @ 2016-09-13 11:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57D7CF17.2050905@laposte.net>
Sebastian Frias wrote:
> Let's make an abstraction of the word 'binding', 'create a binding', etc. and
> just focus on this:
> - Somebody submits a DT file that contains properties and nodes that are
> *not used* by any Linux driver.
> - Said properties and nodes serve as HW description for HW blocks for which
> *there is no* Linux driver.
>
> The goal of the above is to use the DT as the authoritative (and single)
> source of HW definition.
No.
I've grown weary of this discussion. We have explained multiple times
why this is impractical. Using the DT to document hardware makes no
sense. No one is going to do that, and anyone who attempts to submit a
DT binding without an actual driver will get rejected.
^ permalink raw reply
* [PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins
From: Linus Walleij @ 2016-09-13 11:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473409738-27175-2-git-send-email-jbrunet@baylibre.com>
On Fri, Sep 9, 2016 at 10:28 AM, Jerome Brunet <jbrunet@baylibre.com> wrote:
> Add EE domains pins for the SPI flash controller
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This patch does not apply on the latest pinctrl devel
branch:
https://git.kernel.org/cgit/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel
Please rebase, include Kevin's ACK and resend.
Goes for all pinctrl portions of the patch series.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v12 7/8] clocksource/drivers/arm_arch_timer: Add GTDT support for memory-mapped timer
From: Fu Wei @ 2016-09-13 11:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57D7DC59.6000705@arm.com>
Hi Marc,
On 09/13/2016 07:00 PM, Marc Zyngier wrote:
> Argh, new version...
>
> On 13/09/16 11:39, fu.wei at linaro.org wrote:
>> From: Fu Wei <fu.wei@linaro.org>
>>
>> The patch add memory-mapped timer register support by using the information
>> provided by the new GTDT driver of ACPI.
>>
>> Signed-off-by: Fu Wei <fu.wei@linaro.org>
>> ---
>> drivers/clocksource/arm_arch_timer.c | 127 ++++++++++++++++++++++++++++++++++-
>> 1 file changed, 124 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
>> index 0197ef9..d33802b 100644
>> --- a/drivers/clocksource/arm_arch_timer.c
>> +++ b/drivers/clocksource/arm_arch_timer.c
>> @@ -888,7 +888,128 @@ CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
>> arch_timer_mem_init);
>>
>> #ifdef CONFIG_ACPI_GTDT
>> -/* Initialize per-processor generic timer */
>> +static struct gt_timer_data __init *arch_timer_mem_get_timer(
>> + struct gt_block_data *gt_blocks)
>> +{
>> + struct gt_block_data *gt_block = gt_blocks;
>> + struct gt_timer_data *best_frame = NULL;
>> + void __iomem *cntctlbase;
>> + u32 cnttidr;
>> + int i;
>> +
>> + /*
>> + * According to ARMv8 Architecture Reference Manual(ARM),
>> + * the size of CNTCTLBase frame of memory-mapped timer
>> + * is SZ_4K(Offset 0x000 ? 0xFFF).
>> + */
>> + cntctlbase = ioremap(gt_block->cntctlbase_phy, SZ_4K);
>> + if (!cntctlbase) {
>> + pr_err("Failed to map mem timer control frame base address\n");
>> + return NULL;
>> + }
>> + cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
>> +
>> + /*
>> + * Try to find a virtual capable frame. Otherwise fall back to a
>> + * physical capable frame.
>> + */
>> + for (i = 0; i < gt_block->timer_count; i++) {
>> + int n;
>> + u32 cntacr;
>> +
>> + n = gt_block->timer[i].frame_nr;
>> +
>> + /* Try enabling everything, and see what sticks */
>> + cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
>> + CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
>> + writel_relaxed(cntacr, cntctlbase + CNTACR(n));
>> + cntacr = readl_relaxed(cntctlbase + CNTACR(n));
>> +
>> + if ((cnttidr & CNTTIDR_VIRT(n)) &&
>> + !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
>> + best_frame = >_block->timer[i];
>> + arch_timer_mem_use_virtual = true;
>> + break;
>> + }
>> +
>> + if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
>> + continue;
>> +
>> + best_frame = >_block->timer[i];
>> + }
>> + iounmap(cntctlbase);
> As I just said in my reply to the same patch in v11, all of this is
> duplicating existing infrastructure that already exists for DT. Please
> consider decoupling the core driver code from the firmware side and make
> this reusable.
Great thanks for your help, I am working on it now.
Any suggestion for other arm_arch_timer patches?
> Thanks,
>
> M.
--
Best regards,
Fu Wei
Software Engineer
Red Hat
^ permalink raw reply
* [PATCH] mfd: atmel-hlcdc: Do not sleep in atomic context
From: Lee Jones @ 2016-09-13 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473164369-10033-1-git-send-email-boris.brezillon@free-electrons.com>
On Tue, 06 Sep 2016, Boris Brezillon wrote:
> readl_poll_timeout() calls usleep_range(), but
> regmap_atmel_hlcdc_reg_write() is called in atomic context (regmap
> spinlock held).
>
> Replace the readl_poll_timeout() call by readl_poll_timeout_atomic().
>
> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> Fixes: ea31c0cf9b07 ("mfd: atmel-hlcdc: Implement config synchronization")
> Cc: <stable@vger.kernel.org>
> ---
> drivers/mfd/atmel-hlcdc.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
Applied, thanks.
> diff --git a/drivers/mfd/atmel-hlcdc.c b/drivers/mfd/atmel-hlcdc.c
> index eca7ea69b81c..4b15b0840f16 100644
> --- a/drivers/mfd/atmel-hlcdc.c
> +++ b/drivers/mfd/atmel-hlcdc.c
> @@ -50,8 +50,9 @@ static int regmap_atmel_hlcdc_reg_write(void *context, unsigned int reg,
> if (reg <= ATMEL_HLCDC_DIS) {
> u32 status;
>
> - readl_poll_timeout(hregmap->regs + ATMEL_HLCDC_SR, status,
> - !(status & ATMEL_HLCDC_SIP), 1, 100);
> + readl_poll_timeout_atomic(hregmap->regs + ATMEL_HLCDC_SR,
> + status, !(status & ATMEL_HLCDC_SIP),
> + 1, 100);
> }
>
> writel(val, hregmap->regs + reg);
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH] arm64/efi: efi_init error handling fix
From: Matt Fleming @ 2016-09-13 11:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c57dfbbe-a2a7-e8af-7d94-20f86126053c@huawei.com>
On Wed, 07 Sep, at 07:15:48PM, Yisheng Xie wrote:
>
>
> On 2016/9/5 21:57, Matt Fleming wrote:
> > On Fri, 02 Sep, at 11:26:18AM, Will Deacon wrote:
> >> On Fri, Sep 02, 2016 at 06:18:39PM +0800, Xie Yisheng wrote:
> >>> From: Yisheng Xie <xieyisheng1@huawei.com>
> >>>
> >>> diff --git a/drivers/firmware/efi/arm-init.c b/drivers/firmware/efi/arm-init.c
> >>> index c49d50e..5080e40 100644
> >>> --- a/drivers/firmware/efi/arm-init.c
> >>> +++ b/drivers/firmware/efi/arm-init.c
> >>> @@ -243,8 +243,10 @@ void __init efi_init(void)
> >>> "Unexpected EFI_MEMORY_DESCRIPTOR version %ld",
> >>> efi.memmap.desc_version);
> >>>
> >>> - if (uefi_init() < 0)
> >>> + if (uefi_init() < 0) {
> >>> + early_memunmap(efi.memmap.map, params.mmap_size);
> >>> return;
> >>> + }
> >
> > This should be a call to efi_memmap_unmap() because the EFI_MEMMAP
> > flag also needs clearing.
> >
> Hi Matt,
> Thanks for your reply.
> You mean call the function efi_unmap_memmap() like x86?
>
> however, it seems no need to clear EFI_MEMMAP here. For arm*, the flag
> EFI_MEMMAP is set in function reserve_regions(), which is called
> only when uefi_init() return 0:
>
> efi_init()
> -> reserve_regions()
> -> set_bit(EFI_MEMMAP, &efi.flags);
This patch should be against the 'next' branch here,
https://git.kernel.org/cgit/linux/kernel/git/mfleming/efi.git/log/?h=next
My comments were made with that branch in mind.
^ permalink raw reply
* [PATCH v1 1/2] ARM: dts: add rockchip PX3 Evaluation board
From: Heiko Stuebner @ 2016-09-13 11:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <94379f31-00bb-4873-5a93-f6eeead55180@rock-chips.com>
Hi Andy,
Am Dienstag, 13. September 2016, 18:06:12 CEST schrieb Andy Yan:
> Hi Heiko:
>
> Is there any further suggestion about this series?
nope, all fine. I've now applied both patches, after moving some minor stuff
around (alphabetical ordering etc). While it is in branches targeted at 4.9 it
may very well only make it into 4.10.
I've also dropped the stk3310 i2c node from both until the binding is figured
out and moved the px3 board binding to the px5 patch, so that we can sort
entries correctly but don't produce merge conflicts.
If you have time, please give it a final look:
https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?id=a55e2f1b7423ab8b1c3fefbac7ae752e8a4b7edc
https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?id=d42f818e056116237ac8b6a3f72e5bfc38681589
Heiko
^ permalink raw reply
* [PATCH v12 7/8] clocksource/drivers/arm_arch_timer: Add GTDT support for memory-mapped timer
From: Marc Zyngier @ 2016-09-13 11:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473763144-5653-8-git-send-email-fu.wei@linaro.org>
Argh, new version...
On 13/09/16 11:39, fu.wei at linaro.org wrote:
> From: Fu Wei <fu.wei@linaro.org>
>
> The patch add memory-mapped timer register support by using the information
> provided by the new GTDT driver of ACPI.
>
> Signed-off-by: Fu Wei <fu.wei@linaro.org>
> ---
> drivers/clocksource/arm_arch_timer.c | 127 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 124 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index 0197ef9..d33802b 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -888,7 +888,128 @@ CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
> arch_timer_mem_init);
>
> #ifdef CONFIG_ACPI_GTDT
> -/* Initialize per-processor generic timer */
> +static struct gt_timer_data __init *arch_timer_mem_get_timer(
> + struct gt_block_data *gt_blocks)
> +{
> + struct gt_block_data *gt_block = gt_blocks;
> + struct gt_timer_data *best_frame = NULL;
> + void __iomem *cntctlbase;
> + u32 cnttidr;
> + int i;
> +
> + /*
> + * According to ARMv8 Architecture Reference Manual(ARM),
> + * the size of CNTCTLBase frame of memory-mapped timer
> + * is SZ_4K(Offset 0x000 ? 0xFFF).
> + */
> + cntctlbase = ioremap(gt_block->cntctlbase_phy, SZ_4K);
> + if (!cntctlbase) {
> + pr_err("Failed to map mem timer control frame base address\n");
> + return NULL;
> + }
> + cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
> +
> + /*
> + * Try to find a virtual capable frame. Otherwise fall back to a
> + * physical capable frame.
> + */
> + for (i = 0; i < gt_block->timer_count; i++) {
> + int n;
> + u32 cntacr;
> +
> + n = gt_block->timer[i].frame_nr;
> +
> + /* Try enabling everything, and see what sticks */
> + cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
> + CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
> + writel_relaxed(cntacr, cntctlbase + CNTACR(n));
> + cntacr = readl_relaxed(cntctlbase + CNTACR(n));
> +
> + if ((cnttidr & CNTTIDR_VIRT(n)) &&
> + !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
> + best_frame = >_block->timer[i];
> + arch_timer_mem_use_virtual = true;
> + break;
> + }
> +
> + if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
> + continue;
> +
> + best_frame = >_block->timer[i];
> + }
> + iounmap(cntctlbase);
As I just said in my reply to the same patch in v11, all of this is
duplicating existing infrastructure that already exists for DT. Please
consider decoupling the core driver code from the firmware side and make
this reusable.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v7 11/11] arm64: dts: r8a7796: salvator-x: Enable UHS-I SDR-104
From: Simon Horman @ 2016-09-13 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473764228-24768-1-git-send-email-horms+renesas@verge.net.au>
Add the sd-uhs-sdr104 property to SDHI0 and SDHI1.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index a9947d45cccc..91440eb2237e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -134,6 +134,7 @@
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
@@ -148,6 +149,7 @@
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* [PATCH v7 10/11] arm64: dts: r8a7796: salvator-x: enable UHS for SDHI 0 & 3
From: Simon Horman @ 2016-09-13 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473764228-24768-1-git-send-email-horms+renesas@verge.net.au>
Based on work for the r8a7796 by Wolfram Sang.
Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index a8373c248ad1..a9947d45cccc 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -97,11 +97,25 @@
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data4", "sdhi3_ctrl";
function = "sdhi3";
+ power-source = <3300>;
+ };
+
+ sdhi3_pins_uhs: sd3_uhs {
+ groups = "sdhi3_data4", "sdhi3_ctrl";
+ function = "sdhi3";
+ power-source = <1800>;
};
};
@@ -111,25 +125,29 @@
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
+ sd-uhs-sdr50;
status = "okay";
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi3_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi3>;
vqmmc-supply = <&vccq_sdhi3>;
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
+ sd-uhs-sdr50;
status = "okay";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* [PATCH v7 09/11] arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3
From: Simon Horman @ 2016-09-13 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473764228-24768-1-git-send-email-horms+renesas@verge.net.au>
Enable the exposed SD card slots in the DT of the r8a7796/salvator-x.
Based on work for the r8a7795/salvator-x by Ai Kyuse.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 84 ++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index 13db7d61c26c..a8373c248ad1 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -10,6 +10,7 @@
/dts-v1/;
#include "r8a7796.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Salvator-X board based on r8a7796";
@@ -29,6 +30,55 @@
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi3: regulator-vcc-sdhi3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI3 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi3: regulator-vccq-sdhi3 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI3 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
};
&pfc {
@@ -43,12 +93,46 @@
groups = "scif_clk_a";
function = "scif_clk";
};
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ };
+
+ sdhi3_pins: sd3 {
+ groups = "sdhi3_data4", "sdhi3_ctrl";
+ function = "sdhi3";
+ };
};
&extal_clk {
clock-frequency = <16666666>;
};
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&sdhi3 {
+ pinctrl-0 = <&sdhi3_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&vcc_sdhi3>;
+ vqmmc-supply = <&vccq_sdhi3>;
+ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* [PATCH v7 08/11] arm64: dts: r8a7796: add SDHI nodes
From: Simon Horman @ 2016-09-13 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473764228-24768-1-git-send-email-horms+renesas@verge.net.au>
Add SDHI nodes to the DT of the r8a7796 SoC.
Based on the DT of the r8a7795 SoC.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 42 ++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 9217da983525..3aae29fdd9d7 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -251,5 +251,47 @@
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
+
+ sdhi0: sd at ee100000 {
+ compatible = "renesas,sdhi-r8a7796";
+ reg = <0 0xee100000 0 0x2000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ max-frequency = <200000000>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ sdhi1: sd at ee120000 {
+ compatible = "renesas,sdhi-r8a7796";
+ reg = <0 0xee120000 0 0x2000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 313>;
+ max-frequency = <200000000>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ sdhi2: sd at ee140000 {
+ compatible = "renesas,sdhi-r8a7796";
+ reg = <0 0xee140000 0 0x2000>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ max-frequency = <200000000>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ cap-mmc-highspeed;
+ status = "disabled";
+ };
+
+ sdhi3: sd at ee160000 {
+ compatible = "renesas,sdhi-r8a7796";
+ reg = <0 0xee160000 0 0x2000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ max-frequency = <200000000>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ cap-mmc-highspeed;
+ status = "disabled";
+ };
};
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* [PATCH v7 07/11] ARM: dts: alt: Enable UHS-I SDR-50 and SDR-104
From: Simon Horman @ 2016-09-13 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473764228-24768-1-git-send-email-horms+renesas@verge.net.au>
Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1}.
And the sd-uhs-sdr104 property to SDHI0.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794-alt.dts | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 8d1b35afaf82..ccb80d66076f 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -207,11 +207,25 @@
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
};
};
@@ -255,23 +269,28 @@
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
status = "okay";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* [PATCH v7 06/11] ARM: dts: r8a7794: set maximum frequency for SDHI clocks
From: Simon Horman @ 2016-09-13 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473764228-24768-1-git-send-email-horms+renesas@verge.net.au>
Define the upper limit otherwise the driver cannot utilize max speeds.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 9365580a194f..57e0d27cb82e 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -731,6 +731,7 @@
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -743,6 +744,7 @@
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
<&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -755,6 +757,7 @@
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
<&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
status = "disabled";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* [PATCH v7 05/11] ARM: dts: koelsch: Enable UHS-I SDR-50 and SDR-104
From: Simon Horman @ 2016-09-13 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473764228-24768-1-git-send-email-horms+renesas@verge.net.au>
Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1,2}.
And the sd-uhs-sdr104 property to SDHI0.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791-koelsch.dts | 34 +++++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index f8a7d090fd01..be90639d2635 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -360,16 +360,37 @@
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
};
sdhi2_pins: sd2 {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
};
qspi_pins: qspi {
@@ -454,33 +475,40 @@
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi2>;
vqmmc-supply = <&vccq_sdhi2>;
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
status = "okay";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* [PATCH v7 04/11] ARM: dts: r8a7791: set maximum frequency for SDHI clocks
From: Simon Horman @ 2016-09-13 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473764228-24768-1-git-send-email-horms+renesas@verge.net.au>
Define the upper limit otherwise the driver cannot utilize max speeds.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 162b55c665a3..b07c799f72f2 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -584,6 +584,7 @@
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -596,6 +597,7 @@
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
<&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -608,6 +610,7 @@
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
<&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
status = "disabled";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* [PATCH v7 03/11] arm64: dts: r8a7795: salvator-x: Enable UHS-I SDR-104
From: Simon Horman @ 2016-09-13 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473764228-24768-1-git-send-email-horms+renesas@verge.net.au>
Add the sd-uhs-sdr104 property to SDHI0 and SDHI1.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v5
* New patch
---
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index ff4e4fe843ed..8964b1ea3cea 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -394,6 +394,7 @@
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
@@ -408,6 +409,7 @@
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
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