* ARM, SoC: About the use DT-defined properties by 3rd-party drivers
From: Mark Rutland @ 2016-09-13 15:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57D8137F.8040508@laposte.net>
On Tue, Sep 13, 2016 at 04:55:59PM +0200, Sebastian Frias wrote:
> On 09/13/2016 03:12 PM, Mark Rutland wrote:
> >> Exactly, that is why I was thinking it would take less "review" time.
> >> Indeed, if there is no driver, why would it matter what those bindings
> >> are?
> >
> > If you believe that the bindings don't matter, then there is absolutely
> > no reason for them to exist in the first place.
> >
> > If those binding matter to *anyone*, then those collating the bindings
> > have some responsibility of stewardship, and that includes
> > review/maintenance/etc.
>
> The thing is that right now it seems the "responsibility of stewardship"
> lies only within "Linux", whereas DT is proposed as open for everybody,
> Bootloaders, FreeBSD, etc.
>
> In that case, shouldn't the "responsibility" be shared?
Ideally, yes.
Which is one of the reasons devicetree.org was set up as a common forum
for projects to collaborate on devicetree.
Thanks,
Mark.
^ permalink raw reply
* [PATCH 3/3] PCI: Xilinx NWL PCIe: Fix Error for multi function device for legacy interrupts.
From: Thomas Petazzoni @ 2016-09-13 15:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160913153402.GA4138@localhost>
Hello,
On Tue, 13 Sep 2016 10:34:02 -0500, Bjorn Helgaas wrote:
> > After looking at this myself, I'm not happy with this either. It feels
> > like there are bugs lurking here and we're just hiding one of them.
> >
> > Here are the callers of irq_domain_add_linear() for legacy INTx in
> > drivers/pci/host:
> >
> > advk_pcie_init_irq_domain LEGACY_IRQ_NUM (4)
> > dra7xx_pcie_init_irq_domain 4
> > ks_dw_pcie_host_init MAX_LEGACY_IRQS (4)
> > altera_pcie_init_irq_domain INTX_NUM + 1 (5)
> > nwl_pcie_init_irq_domain INTX_NUM + 1 (5)
> > xilinx_pcie_init_irq_domain 4
>
> The altera change corresponding to this was 99496bd2971f ("PCI: altera: Fix
> error when INTx is 4"). I should have noticed this inconsistency back
> then.
>
> Are aardvark, dra7xx, keystone, and xilinx (non-NWL) broken because they
> only request 4 IRQs and only INTA, INTB, and INTC work?
>
> > I think all of these use the of_irq_parse_and_map_pci() path you
> > mentioned, so if the problem is in the way that path works, I would
> > think these should *all* be requesting the same number of interrupts
> > in the domain.
> >
> > I agree with Marc that we should request 4 IRQs, because that's what
> > we need. If we can't do that for some reason, we ought to at least
> > make all these callers the same.
Thanks for Cc'ing about this issue. Indeed, the Aardvark driver
supports all of INT{A,B,C,D}, so the current situation doesn't work. As
suggested, the simplest solution is to just allocate an irq domain with
5 IRQs, like is done in the Altera driver.
However, my feeling is that a more correct solution would be to have a
translation between the PCI_INTERRUPT_PIN value (in the range 0x1 to
0x4) to the hwirq value (in the range 0x0 to 0x3).
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [RFC PATCH 0/5] arm64: Signal context expansion
From: Dave Martin @ 2016-09-13 15:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9969568a-f969-d904-52b3-14f80c3abec4@redhat.com>
On Tue, Sep 13, 2016 at 11:28:21AM +0200, Florian Weimer wrote:
> On 09/12/2016 05:30 PM, Dave Martin wrote:
> >On Mon, Sep 12, 2016 at 04:01:17PM +0100, Szabolcs Nagy wrote:
> >>i assume the kernel can avoid saving SVE regs when
> >>they are not used by the process.
> >
> >I can (and do), in my patches (not posted yet).
> >
> >The real issue here is that a recently updated shared library might be
> >optimised to use SVE, where the program using it is an older, SVE-
> >unaware binary.
> >
> >(think of an optimised math library using some new fancy SVE-based
> >number crunching internally).
>
> In my little world, binaries are expected to do run-time CPU feature
> discovery and fall back to the baseline ABI if the system does not support
> ABI extensions. This means that a personality flag can disable the
> extension, the optimized math libraries run with the slower baseline code
> instead, and the rest of the application sees the expected kernel interface.
>
> From this perspective, it is quite important that it is possible to get
> legacy applications running on newer hardware, preferably with out wrapping
> them in a dedicated VM.
>
> I understand that there are other environments were this is less of a
> concern, but I also believe that the age of an architecture factors less
> into this than one might want.
Agreed. I'll need to think some more about how this should work in
general.
This series by itself doesn't change the ABI unless something allocates
enough signal frame data to exceed the historical frame size -- which
for now cannot happen.
What I may do is split off the extra_context part of the series (without
which the signal frame never grows).
SVE will still fit if the vector length is below a certain limit.
Cheers
---Dave
^ permalink raw reply
* [PATCH v2 2/2] MMC: meson: initial support for GXBB platforms
From: Kevin Hilman @ 2016-09-13 15:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAPDyKFpPCkCRB436zdZ664st9xwA6wTWkFtT=U4HTwwAn-_emg@mail.gmail.com>
Ulf Hansson <ulf.hansson@linaro.org> writes:
> On 4 August 2016 at 01:18, Kevin Hilman <khilman@baylibre.com> wrote:
>> Initial support for the SD/eMMC controller in the Amlogic S905/GXBB
>> family of SoCs.
>>
>> Currently working for the SD and eMMC interfaces, but not yet tested
>> for SDIO.
>>
>> Tested external SD card and internal eMMC on meson-gxbb-p200 and
>> meson-gxbb-odroidc2.
>>
>> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
>> ---
>> MAINTAINERS | 1 +
>> drivers/mmc/host/Kconfig | 10 +
>> drivers/mmc/host/Makefile | 1 +
>> drivers/mmc/host/meson-gxbb.c | 918 ++++++++++++++++++++++++++++++++++++++++++
>> 4 files changed, 930 insertions(+)
>> create mode 100644 drivers/mmc/host/meson-gxbb.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 7304d2e37a98..3762e46811f3 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -972,6 +972,7 @@ F: arch/arm/mach-meson/
>> F: arch/arm/boot/dts/meson*
>> F: arch/arm64/boot/dts/amlogic/
>> F: drivers/pinctrl/meson/
>> +F: drivers/mmc/host/meson*
>> N: meson
>>
>> ARM/Annapurna Labs ALPINE ARCHITECTURE
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index 0aa484c10c0a..4c3d091f7548 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -332,6 +332,16 @@ config MMC_SDHCI_IPROC
>>
>> If unsure, say N.
>>
>> +config MMC_MESON_GXBB
>> + tristate "Amlogic S905/GXBB SD/MMC Host Controller support"
>> + depends on ARCH_MESON && MMC
>> + help
>> + This selects support for the Amlogic SD/MMC Host Controller
>> + found on the S905/GXBB family of SoCs. This controller is
>> + MMC 5.1 compliant and support SD, eMMC and SDIO interfaces.
>> +
>> + If you have a controller with this interface, say Y here.
>> +
>> config MMC_MOXART
>> tristate "MOXART SD/MMC Host Controller support"
>> depends on ARCH_MOXART && MMC
>> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>> index af918d261ff9..3e0de57f55b9 100644
>> --- a/drivers/mmc/host/Makefile
>> +++ b/drivers/mmc/host/Makefile
>> @@ -53,6 +53,7 @@ obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
>> obj-$(CONFIG_MMC_VUB300) += vub300.o
>> obj-$(CONFIG_MMC_USHC) += ushc.o
>> obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
>> +obj-$(CONFIG_MMC_MESON_GXBB) += meson-gxbb.o
>> obj-$(CONFIG_MMC_MOXART) += moxart-mmc.o
>> obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o
>> obj-$(CONFIG_MMC_USDHI6ROL0) += usdhi6rol0.o
>> diff --git a/drivers/mmc/host/meson-gxbb.c b/drivers/mmc/host/meson-gxbb.c
>> new file mode 100644
>> index 000000000000..10eac41cf31a
>> --- /dev/null
>> +++ b/drivers/mmc/host/meson-gxbb.c
>> @@ -0,0 +1,918 @@
>> +/*
>> + * This file is provided under a dual BSD/GPLv2 license. When using or
>> + * redistributing this file, you may do so under either license.
>> + *
>> + * GPL LICENSE SUMMARY
>> + *
>> + * Copyright (c) 2016 BayLibre, SAS.
>> + * Author: Kevin Hilman <khilman@baylibre.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of version 2 of the GNU General Public License as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful, but
>> + * WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> + * General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
>> + * The full GNU General Public License is included in this distribution
>> + * in the file called COPYING.
>> + *
>> + * BSD LICENSE
>> + *
>> + * Copyright (c) 2016 BayLibre, SAS.
>> + * Author: Kevin Hilman <khilman@baylibre.com>
>> + *
>> + * Redistribution and use in source and binary forms, with or without
>> + * modification, are permitted provided that the following conditions
>> + * are met:
>> + *
>> + * * Redistributions of source code must retain the above copyright
>> + * notice, this list of conditions and the following disclaimer.
>> + * * Redistributions in binary form must reproduce the above copyright
>> + * notice, this list of conditions and the following disclaimer in
>> + * the documentation and/or other materials provided with the
>> + * distribution.
>> + * * Neither the name of Intel Corporation nor the names of its
>> + * contributors may be used to endorse or promote products derived
>> + * from this software without specific prior written permission.
>> + *
>> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
>> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
>> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
>> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
>> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
>> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
>> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
>> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
>> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>> + */
>
> Lots of licence text. Isn't it enough to state dual BSD/GPLv2?
>
> [...]
>
>> +
>> +struct meson_host {
>> + struct device *dev;
>> + struct mmc_host *mmc;
>> + struct mmc_request *mrq;
>> + struct mmc_command *cmd;
>> +
>> + spinlock_t lock;
>> + void __iomem *regs;
>> +#ifdef USE_REGMAP
>> + struct regmap *regmap;
>> +#endif
>> + int irq;
>> + u32 ocr_mask;
>> + struct clk *core_clk;
>> + struct clk_mux mux;
>> + struct clk *mux_clk;
>> + struct clk *mux_parent[MUX_CLK_NUM_PARENTS];
>> + unsigned long mux_parent_rate[MUX_CLK_NUM_PARENTS];
>> +
>> + struct clk_divider cfg_div;
>> + struct clk *cfg_div_clk;
>> +
>> + unsigned int bounce_buf_size;
>> + void *bounce_buf;
>> + dma_addr_t bounce_dma_addr;
>> +
>> + unsigned long clk_rate;
>> + unsigned long clk_src_rate;
>> + unsigned short clk_src_div;
>> +};
>> +
>> +#define reg_read(host, offset) readl(host->regs + offset)
>> +#define reg_write(host, offset, val) writel(val, host->regs + offset)
>
> I am not a fan of macros, especially when I don't think they improves the code.
>
> Could we just stick to use readl/writel() directly instead!?
>
Yes, I'll remove these. They are leftover from when I was using macros
to switch between readl/writel and regmap accessors.
>
>> +static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate)
>> +{
>> + struct mmc_host *mmc = host->mmc;
>> + int ret = 0;
>> + u32 cfg;
>> +
>> + if (clk_rate) {
>> + if (WARN_ON(clk_rate > mmc->f_max))
>> + clk_rate = mmc->f_max;
>> + else if (WARN_ON(clk_rate < mmc->f_min))
>> + clk_rate = mmc->f_min;
>> + }
>> +
>> + if (clk_rate == host->clk_rate)
>> + return 0;
>> +
>> + /* stop clock */
>> + cfg = reg_read(host, SD_EMMC_CFG);
>> + if (!(cfg & CFG_STOP_CLOCK)) {
>> + cfg |= CFG_STOP_CLOCK;
>> + reg_write(host, SD_EMMC_CFG, cfg);
>> + }
>> +
>> + dev_dbg(host->dev, "change clock rate %lu -> %lu\n",
>> + host->clk_rate, clk_rate);
>> + ret = clk_set_rate(host->cfg_div_clk, clk_rate);
>> + if (clk_rate && clk_rate != clk_get_rate(host->cfg_div_clk))
>> + dev_warn(host->dev, "divider requested rate %lu != actual rate %lu: ret=%d\n",
>> + clk_rate, clk_get_rate(host->cfg_div_clk), ret);
>> + else
>> + host->clk_rate = clk_rate;
>> +
>> + /* (re)start clock, if non-zero */
>> + if (clk_rate) {
>> + cfg = reg_read(host, SD_EMMC_CFG);
>> + cfg &= ~CFG_STOP_CLOCK;
>> + reg_write(host, SD_EMMC_CFG, cfg);
>> + }
>
> You probably want to update mmc->actual_clock, which is useful for
> debugging purpose.
OK, I hadn't noticed that field. I'll just drop my own host->clk_rate
and use that.
>> +
>> + return ret;
>> +}
>> +
>> +static int meson_mmc_clk_init(struct meson_host *host)
>> +{
>> + struct clk_init_data init;
>> + char clk_name[32];
>> + int i, ret = 0;
>> + const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
>> + unsigned int mux_parent_count = 0;
>> + const char *clk_div_parents[1];
>> + unsigned int f_min = UINT_MAX;
>> + u32 clk_reg, cfg;
>> +
>> + /* get the mux parents from DT */
>> + for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
>> + char name[16];
>> +
>> + snprintf(name, sizeof(name), "clkin%d", i);
>> + host->mux_parent[i] = devm_clk_get(host->dev, name);
>> + if (IS_ERR(host->mux_parent[i])) {
>> + ret = PTR_ERR(host->mux_parent[i]);
>> + if (PTR_ERR(host->mux_parent[i]) != -EPROBE_DEFER)
>> + dev_err(host->dev, "Missing clock %s\n", name);
>> + host->mux_parent[i] = NULL;
>> + return ret;
>> + }
>> +
>> + host->mux_parent_rate[i] = clk_get_rate(host->mux_parent[i]);
>> + mux_parent_names[i] = __clk_get_name(host->mux_parent[i]);
>> + mux_parent_count++;
>> + if (host->mux_parent_rate[i] < f_min)
>> + f_min = host->mux_parent_rate[i];
>> + }
>> +
>> + /* cacluate f_min based on input clocks, and max divider value */
>> + if (f_min != UINT_MAX)
>> + f_min = DIV_ROUND_UP(CLK_SRC_XTAL_RATE, CLK_DIV_MAX);
>> + else
>> + f_min = 4000000; /* default min: 400 MHz */
>> + host->mmc->f_min = f_min;
>> +
>> + /* create the mux */
>> + snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
>> + init.name = clk_name;
>> + init.ops = &clk_mux_ops;
>> + init.flags = CLK_IS_BASIC;
>> + init.parent_names = mux_parent_names;
>> + init.num_parents = mux_parent_count;
>> +
>> + host->mux.reg = host->regs + SD_EMMC_CLOCK;
>> + host->mux.shift = CLK_SRC_SHIFT;
>> + host->mux.mask = CLK_SRC_MASK;
>> + host->mux.flags = 0;
>> + host->mux.table = NULL;
>> + host->mux.hw.init = &init;
>> +
>> + host->mux_clk = devm_clk_register(host->dev, &host->mux.hw);
>
> I think it would make sense to add a comment here to clarify why you
> register a clock like this.
>
> I assume it's beacuse you benefit from the clock framwork about
> acheiving the best/closest reqeust clockrate, as it take into account
> muxes/parent clocks as well!?
Correct. This IP block has an internal mux and divider, so I want to
take advanate of the clock framework features to model those clocks.
>> + if (WARN_ON(PTR_ERR_OR_ZERO(host->mux_clk)))
>> + return PTR_ERR(host->mux_clk);
>> +
>> + /* create the divider */
>> + snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
>> + init.name = devm_kstrdup(host->dev, clk_name, GFP_KERNEL);
>> + init.ops = &clk_divider_ops;
>> + init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
>> + clk_div_parents[0] = __clk_get_name(host->mux_clk);
>> + init.parent_names = clk_div_parents;
>> + init.num_parents = ARRAY_SIZE(clk_div_parents);
>> +
>> + host->cfg_div.reg = host->regs + SD_EMMC_CLOCK;
>> + host->cfg_div.shift = CLK_DIV_SHIFT;
>> + host->cfg_div.width = CLK_DIV_WIDTH;
>> + host->cfg_div.hw.init = &init;
>> + host->cfg_div.flags = CLK_DIVIDER_ONE_BASED |
>> + CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ALLOW_ZERO;
>> +
>> + host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw);
>
> Ditto.
>
>> + if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk)))
>> + return PTR_ERR(host->cfg_div_clk);
>> +
>> + /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
>> + clk_reg = 0;
>> + clk_reg |= CLK_PHASE_180 << CLK_PHASE_SHIFT;
>> + clk_reg |= CLK_SRC_XTAL << CLK_SRC_SHIFT;
>> + clk_reg |= CLK_DIV_MAX << CLK_DIV_SHIFT;
>> + clk_reg &= ~CLK_ALWAYS_ON;
>> + reg_write(host, SD_EMMC_CLOCK, clk_reg);
>> +
>> + clk_prepare_enable(host->cfg_div_clk);
>> +
>> + /* Ensure clock starts in "auto" mode, not "always on" */
>> + cfg = reg_read(host, SD_EMMC_CFG);
>> + cfg &= ~CFG_CLK_ALWAYS_ON;
>> + cfg |= CFG_AUTO_CLK;
>> + reg_write(host, SD_EMMC_CFG, cfg);
>> +
>> + meson_mmc_clk_set(host, f_min);
>> +
>> + return ret;
>> +}
>> +
>> +static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>> +{
>> + struct meson_host *host = mmc_priv(mmc);
>> + u32 bus_width;
>> + u32 val, orig;
>> +
>> + /*
>> + * GPIO regulator, only controls switching between 1v8 and
>> + * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
>> + */
>
> I don't follow. Shouldn't you call regulator_enable|disable() for the
> above regulator? Why not?
>
>> + switch (ios->power_mode) {
>> + case MMC_POWER_UP:
>> + if (!IS_ERR(mmc->supply.vmmc))
>> + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
>
> The above comment talks about 1v8 and 3v3, which seems to me that you
> are changing the I/O voltage, but that's not what *vmmc* should be
> used for.
>
> If this is about I/O voltage, you shall instead use *vqmmc* and the
> corresponding mmc_regulator_set_vqmmc() to change the voltage level.
>
> This also leaves me to ask, then how do you control the power to the
> card? This is actually what the *vmmc* should be used for.
I'll respin this whole section based on your clarifications. I was
confused about how the various regulators are meant to be used. Thanks
for clarifying.
>
>> + }
>> +
>> + meson_mmc_clk_set(host, ios->clock);
>> +
>> + /* Bus width */
>> + val = reg_read(host, SD_EMMC_CFG);
>> + switch (ios->bus_width) {
>> + case MMC_BUS_WIDTH_1:
>> + bus_width = CFG_BUS_WIDTH_1;
>> + break;
>> + case MMC_BUS_WIDTH_4:
>> + bus_width = CFG_BUS_WIDTH_4;
>> + break;
>> + case MMC_BUS_WIDTH_8:
>> + bus_width = CFG_BUS_WIDTH_8;
>> + break;
>> + default:
>> + dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
>> + ios->bus_width);
>> + bus_width = CFG_BUS_WIDTH_4;
>> + return;
>> + }
>> +
>> + val = reg_read(host, SD_EMMC_CFG);
>> + orig = val;
>> +
>> + val &= ~(CFG_BUS_WIDTH_MASK << CFG_BUS_WIDTH_SHIFT);
>> + val |= bus_width << CFG_BUS_WIDTH_SHIFT;
>> +
>> + val &= ~(CFG_BLK_LEN_MASK << CFG_BLK_LEN_SHIFT);
>> + val |= ilog2(SD_EMMC_CFG_BLK_SIZE) << CFG_BLK_LEN_SHIFT;
>> +
>> + val &= ~(CFG_RESP_TIMEOUT_MASK << CFG_RESP_TIMEOUT_SHIFT);
>> + val |= ilog2(SD_EMMC_CFG_RESP_TIMEOUT) << CFG_RESP_TIMEOUT_SHIFT;
>> +
>> + val &= ~(CFG_RC_CC_MASK << CFG_RC_CC_SHIFT);
>> + val |= ilog2(SD_EMMC_CFG_CMD_GAP) << CFG_RC_CC_SHIFT;
>> +
>> + reg_write(host, SD_EMMC_CFG, val);
>> +
>> + if (val != orig)
>> + dev_dbg(host->dev, "%s: SD_EMMC_CFG: 0x%08x -> 0x%08x\n",
>> + __func__, orig, val);
>> +}
>> +
>
> [...]
>
>> +
>> +static int meson_mmc_probe(struct platform_device *pdev)
>> +{
>> + struct device_node *np = pdev->dev.of_node;
>> + struct resource *res;
>> + struct meson_host *host;
>> + struct mmc_host *mmc;
>> + int ret;
>> +
>> + mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
>> + if (!mmc)
>> + return -ENOMEM;
>> + host = mmc_priv(mmc);
>> + host->mmc = mmc;
>> + host->dev = &pdev->dev;
>> + dev_set_drvdata(&pdev->dev, host);
>> +
>> + spin_lock_init(&host->lock);
>> +
>> + host->core_clk = devm_clk_get(&pdev->dev, "core");
>> + if (IS_ERR(host->core_clk)) {
>> + ret = PTR_ERR(host->core_clk);
>> + if (ret == -EPROBE_DEFER)
>> + dev_dbg(&pdev->dev,
>> + "Missing core clock. EPROBE_DEFER\n");
>> + else
>> + dev_err(&pdev->dev,
>> + "Unable to get core clk (ret=%d).\n", ret);
>
> I think these prints are unessarry, they should be printed by other
> frameworks already, right!?
OK, I'll drop these.
>> + goto free_host;
>> + }
>> +
>> + /* Voltage supply */
>> + mmc_of_parse_voltage(np, &host->ocr_mask);
>
> This looks odd.
>
> Usally we get "ocr_avail" when asking the vmmc regulator about its
> supported voltage range, via calling the below
> mmc_regulator_get_supply() API. Can you explain why thay isn't work
> for you?
You're right, that's working fine. I'll drop this.
>> + ret = mmc_regulator_get_supply(mmc);
>> + if (ret == -EPROBE_DEFER) {
>> + dev_dbg(&pdev->dev, "Missing regulator: EPROBE_DEFER");
>
> The print shouldn't be needed, please remove.
OK.
>> + goto free_host;
>> + }
>> +
>> + if (!mmc->ocr_avail)
>> + mmc->ocr_avail = host->ocr_mask;
>
> mmc->ocr_avail needs to be assigned to a valid value. This fallback
> doesn't cover that as host->ocr_mask may very well be zero.
Dropped this as it's now handled elsewhere.
>> +
>> + ret = mmc_of_parse(mmc);
>> + if (ret) {
>> + dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
>> + goto free_host;
>> + }
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res) {
>> + ret = -ENODEV;
>> + goto free_host;
>> + }
>> + host->regs = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(host->regs)) {
>> + ret = PTR_ERR(host->regs);
>> + goto free_host;
>> + }
>> +
>> + host->irq = platform_get_irq(pdev, 0);
>> + if (host->irq == 0) {
>> + dev_err(&pdev->dev, "failed to get interrupt resource.\n");
>> + ret = -EINVAL;
>> + goto free_host;
>> + }
>> +
>> + ret = devm_request_threaded_irq(&pdev->dev, host->irq,
>> + meson_mmc_irq, meson_mmc_irq_thread,
>> + IRQF_SHARED, DRIVER_NAME, host);
>> + if (ret)
>> + goto free_host;
>> +
>> + /* data bounce buffer */
>> + host->bounce_buf_size = SZ_512K;
>> + host->bounce_buf =
>> + dma_alloc_coherent(host->dev, host->bounce_buf_size,
>> + &host->bounce_dma_addr, GFP_KERNEL);
>> + if (host->bounce_buf == NULL) {
>> + dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
>> + ret = -ENOMEM;
>> + goto free_host;
>> + }
>> +
>> + clk_prepare_enable(host->core_clk);
>> +
>> + ret = meson_mmc_clk_init(host);
>> + if (ret)
>> + goto free_host;
>> +
>> + /* Stop execution */
>> + reg_write(host, SD_EMMC_START, 0);
>> +
>> + /* clear, ack, enable all interrupts */
>> + reg_write(host, SD_EMMC_IRQ_EN, 0);
>> + reg_write(host, SD_EMMC_STATUS, IRQ_EN_MASK);
>> +
>> + mmc->ops = &meson_mmc_ops;
>> + mmc_add_host(mmc);
>> +
>> + return 0;
>> +
>> +free_host:
>> + dev_dbg(host->dev, "Failed to probe: ret=%d\n", ret);
>> + if (host->core_clk)
>> + clk_disable_unprepare(host->core_clk);
>> + mmc_free_host(mmc);
>> + return ret;
>> +}
>> +
>
> [...]
>
>> +
>> +static const struct of_device_id meson_mmc_of_match[] = {
>> + {
>> + .compatible = "amlogic,meson-gxbb-mmc",
>
> You need to fold in a DT documentation patch, in this series as to
> describe all the required/optional resourses for the device. That of
> course also includes the compatible string.
That was all part of PATCH 1/2 of this series, or was there something
else missing from that patch?
Thanks for the review,
Kevin
^ permalink raw reply
* [GIT PULL] Allwinner DT changes for 4.9, take 2
From: Arnd Bergmann @ 2016-09-13 15:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160911204420.GA11949@lukather>
On Sunday, September 11, 2016 10:44:20 PM CEST Maxime Ripard wrote:
> Allwinner DT changes for 4.9, take 2
>
> A second set of device tree changes, this time switching a few SoCs to the
> new sunxi-ng clock framework. We also added the support for a new SoC
> (NextThing GR8 and its evaluation board), and the support for the DRM
> driver in the A33.
>
>
Pulled into *next/late* because of the dependency, rather than next/dt.
I think this is better so we can send off the other next/dt changes
early on during the merge window without considering the dependency.
If the clk git gets sent before our pull requests, we might just
merge next/late back into next/dt.
Thanks,
Arnd
^ permalink raw reply
* [PATCH 1/6] PCI: xilinx: Keep both legacy and MSI interrupt references.
From: Bjorn Helgaas @ 2016-09-13 15:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1472724886-28301-1-git-send-email-bharatku@xilinx.com>
On Thu, Sep 01, 2016 at 03:44:41PM +0530, Bharat Kumar Gogada wrote:
> When built with MSI support the legacy domain reference is being
> overwritten with MSI.
> Instead creating two separate domains for MSI and legacy interrupts.
>
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Applied all these (except [5/6]) with Michal's ack to pci/host-xilinx for
v4.9, thanks!
I already applied Po Liu's patch ("PCI: xilinx: Relax device number
checking to allow SR-IOV") to pci/virtualization. This is identical to
[5/6], so I dropped [5/6] to avoid a conflict.
> ---
> drivers/pci/host/pcie-xilinx.c | 26 +++++++++++++++-----------
> 1 file changed, 15 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
> index a30e016..bd64677 100644
> --- a/drivers/pci/host/pcie-xilinx.c
> +++ b/drivers/pci/host/pcie-xilinx.c
> @@ -101,7 +101,8 @@
> * @msi_pages: MSI pages
> * @root_busno: Root Bus number
> * @dev: Device pointer
> - * @irq_domain: IRQ domain pointer
> + * @msi_domain: MSI IRQ domain pointer
> + * @leg_domain: Legacy IRQ domain pointer
> * @resources: Bus Resources
> */
> struct xilinx_pcie_port {
> @@ -110,7 +111,8 @@ struct xilinx_pcie_port {
> unsigned long msi_pages;
> u8 root_busno;
> struct device *dev;
> - struct irq_domain *irq_domain;
> + struct irq_domain *msi_domain;
> + struct irq_domain *leg_domain;
> struct list_head resources;
> };
>
> @@ -281,7 +283,7 @@ static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
> if (hwirq < 0)
> return hwirq;
>
> - irq = irq_create_mapping(port->irq_domain, hwirq);
> + irq = irq_create_mapping(port->msi_domain, hwirq);
> if (!irq)
> return -EINVAL;
>
> @@ -443,7 +445,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
> /* Handle INTx Interrupt */
> val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
> XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
> - generic_handle_irq(irq_find_mapping(port->irq_domain,
> + generic_handle_irq(irq_find_mapping(port->leg_domain,
> val));
> }
> }
> @@ -526,12 +528,14 @@ static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
> }
>
> for (i = 0; i < num_irqs; i++) {
> - irq = irq_find_mapping(port->irq_domain, i);
> + irq = irq_find_mapping(port->leg_domain, i);
> if (irq > 0)
> irq_dispose_mapping(irq);
> }
> -
> - irq_domain_remove(port->irq_domain);
> + if (port->leg_domain)
> + irq_domain_remove(port->leg_domain);
> + if (port->msi_domain)
> + irq_domain_remove(port->msi_domain);
> }
>
> /**
> @@ -553,21 +557,21 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
> return -ENODEV;
> }
>
> - port->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
> + port->leg_domain = irq_domain_add_linear(pcie_intc_node, 4,
> &intx_domain_ops,
> port);
> - if (!port->irq_domain) {
> + if (!port->leg_domain) {
> dev_err(dev, "Failed to get a INTx IRQ domain\n");
> return -ENODEV;
> }
>
> /* Setup MSI */
> if (IS_ENABLED(CONFIG_PCI_MSI)) {
> - port->irq_domain = irq_domain_add_linear(node,
> + port->msi_domain = irq_domain_add_linear(node,
> XILINX_NUM_MSI_IRQS,
> &msi_domain_ops,
> &xilinx_pcie_msi_chip);
> - if (!port->irq_domain) {
> + if (!port->msi_domain) {
> dev_err(dev, "Failed to get a MSI IRQ domain\n");
> return -ENODEV;
> }
> --
> 2.1.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v5 06/14] drivers: acpi: implement acpi_dma_configure
From: Lorenzo Pieralisi @ 2016-09-13 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ea01f486-8be6-f87a-caed-96fadade054c@arm.com>
On Tue, Sep 13, 2016 at 03:41:06PM +0100, Robin Murphy wrote:
> On 09/09/16 15:23, Lorenzo Pieralisi wrote:
> > On DT based systems, the of_dma_configure() API implements DMA
> > configuration for a given device. On ACPI systems an API equivalent to
> > of_dma_configure() is missing which implies that it is currently not
> > possible to set-up DMA operations for devices through the ACPI generic
> > kernel layer.
> >
> > This patch fills the gap by introducing acpi_dma_configure/deconfigure()
> > calls that for now are just wrappers around arch_setup_dma_ops() and
> > arch_teardown_dma_ops() and also updates ACPI and PCI core code to use
> > the newly introduced acpi_dma_configure/acpi_dma_deconfigure functions.
> >
> > The DMA range size passed to arch_setup_dma_ops() is sized according
> > to the device coherent_dma_mask (starting at address 0x0), mirroring the
> > DT probing path behaviour when a dma-ranges property is not provided
> > for the device being probed; this changes the current arch_setup_dma_ops()
> > call parameters in the ACPI probing case, but since arch_setup_dma_ops()
> > is a NOP on all architectures but ARM/ARM64 this patch does not change
> > the current kernel behaviour on them.
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Acked-by: Bjorn Helgaas <bhelgaas@google.com> [pci]
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Robin Murphy <robin.murphy@arm.com>
> > Cc: Tomasz Nowicki <tn@semihalf.com>
> > Cc: Joerg Roedel <joro@8bytes.org>
> > Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
> > ---
> > drivers/acpi/glue.c | 4 ++--
> > drivers/acpi/scan.c | 24 ++++++++++++++++++++++++
> > drivers/pci/probe.c | 3 +--
> > include/acpi/acpi_bus.h | 2 ++
> > include/linux/acpi.h | 5 +++++
> > 5 files changed, 34 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/acpi/glue.c b/drivers/acpi/glue.c
> > index 5ea5dc2..f8d6564 100644
> > --- a/drivers/acpi/glue.c
> > +++ b/drivers/acpi/glue.c
> > @@ -227,8 +227,7 @@ int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
> >
> > attr = acpi_get_dma_attr(acpi_dev);
> > if (attr != DEV_DMA_NOT_SUPPORTED)
> > - arch_setup_dma_ops(dev, 0, 0, NULL,
> > - attr == DEV_DMA_COHERENT);
> > + acpi_dma_configure(dev, attr);
Here's the call for non-PCI devices ;-)
> > acpi_physnode_link_name(physical_node_name, node_id);
> > retval = sysfs_create_link(&acpi_dev->dev.kobj, &dev->kobj,
> > @@ -251,6 +250,7 @@ int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
> > return 0;
> >
> > err:
> > + acpi_dma_deconfigure(dev);
> > ACPI_COMPANION_SET(dev, NULL);
> > put_device(dev);
> > put_device(&acpi_dev->dev);
> > diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
> > index e878fc7..9614232 100644
> > --- a/drivers/acpi/scan.c
> > +++ b/drivers/acpi/scan.c
> > @@ -1370,6 +1370,30 @@ enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev)
> > return DEV_DMA_NON_COHERENT;
> > }
> >
> > +/**
> > + * acpi_dma_configure - Set-up DMA configuration for the device.
> > + * @dev: The pointer to the device
> > + * @attr: device dma attributes
> > + */
> > +void acpi_dma_configure(struct device *dev, enum dev_dma_attr attr)
> > +{
> > + /*
> > + * Assume dma valid range starts at 0 and covers the whole
> > + * coherent_dma_mask.
> > + */
> > + arch_setup_dma_ops(dev, 0, dev->coherent_dma_mask + 1, NULL,
> > + attr == DEV_DMA_COHERENT);
>
> This looks a bit hairy - if we're setting up the DMA configuration at
> this point can we really always rely on the device already having a
> valid DMA mask? I think it would make sense to at least check, and apply
> the standard default 32-bit mask if not.
That's a good point, but we would be changing the x86/IA64 probing path
if we do what you suggest; so I think you are right and it should be a
safe change to make but I still need to make sure we do not break
anything in the process.
> > +}
> > +
> > +/**
> > + * acpi_dma_deconfigure - Tear-down DMA configuration for the device.
> > + * @dev: The pointer to the device
> > + */
> > +void acpi_dma_deconfigure(struct device *dev)
> > +{
> > + arch_teardown_dma_ops(dev);
> > +}
>
> As touched upon in the dwc-usb3 thread, is it worth exporting these for
> the benefit of modular bus/glue code, to match of_dma_configure()?
I think yes, I will do.
> > static void acpi_init_coherency(struct acpi_device *adev)
> > {
> > unsigned long long cca = 0;
> > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> > index 93f280d..e96d482 100644
> > --- a/drivers/pci/probe.c
> > +++ b/drivers/pci/probe.c
> > @@ -1734,8 +1734,7 @@ static void pci_dma_configure(struct pci_dev *dev)
> > if (attr == DEV_DMA_NOT_SUPPORTED)
> > dev_warn(&dev->dev, "DMA not supported.\n");
> > else
> > - arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
> > - attr == DEV_DMA_COHERENT);
> > + acpi_dma_configure(&dev->dev, attr);
> > }
>
> What about non-PCI stuff? I see there's at least an
> acpi_create_platform_device() which I'd also kind of expect to see as a
> caller (which indeed might also tie in with the aforementioned default
> mask initialisation).
See above (acpi_bind_one()).
Thanks for having a look,
Lorenzo
>
> Robin.
>
> >
> > pci_put_host_bridge_device(bridge);
> > diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
> > index c1a524d..4242c31 100644
> > --- a/include/acpi/acpi_bus.h
> > +++ b/include/acpi/acpi_bus.h
> > @@ -573,6 +573,8 @@ struct acpi_pci_root {
> >
> > bool acpi_dma_supported(struct acpi_device *adev);
> > enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev);
> > +void acpi_dma_configure(struct device *dev, enum dev_dma_attr attr);
> > +void acpi_dma_deconfigure(struct device *dev);
> >
> > struct acpi_device *acpi_find_child_device(struct acpi_device *parent,
> > u64 address, bool check_children);
> > diff --git a/include/linux/acpi.h b/include/linux/acpi.h
> > index c5eaf2f..05d4e48 100644
> > --- a/include/linux/acpi.h
> > +++ b/include/linux/acpi.h
> > @@ -729,6 +729,11 @@ static inline enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev)
> > return DEV_DMA_NOT_SUPPORTED;
> > }
> >
> > +static inline void acpi_dma_configure(struct device *dev,
> > + enum dev_dma_attr attr) { }
> > +
> > +static inline void acpi_dma_deconfigure(struct device *dev) { }
> > +
> > #define ACPI_PTR(_ptr) (NULL)
> >
> > static inline void acpi_device_set_enumerated(struct acpi_device *adev)
> >
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-acpi" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [RFC PATCH 0/5] arm64: Signal context expansion
From: Florian Weimer @ 2016-09-13 16:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160913155151.GA1574@e103592.cambridge.arm.com>
On 09/13/2016 05:52 PM, Dave Martin wrote:
> Agreed. I'll need to think some more about how this should work in
> general.
Thanks.
Depending on some SVE implementations details (which I know nothing
about, I only saw some public overview slides), we may also need
additional storage space to preserve SVE registers in the dynamic
linker. Due to lazy binding, this code cn be called from a signal
handler, so this needs to be factored into stack size requirements as well.
Problematic are register width extensions used for argument passing and
callee-saved registers whose width has been extended. Both are
particularly challenging to deal with if existing vector instructions
clear the extension part (which may be desirable for other reasons).
The size of the jmp_buf type is a concern as well.
Florian
^ permalink raw reply
* [PATCH 1/3] pci: pci-aardvark: move to MSI handling using generic MSI support
From: Bjorn Helgaas @ 2016-09-13 16:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57C93B7F.8050909@arm.com>
On Fri, Sep 02, 2016 at 09:42:39AM +0100, Marc Zyngier wrote:
> Hi Thomas,
>
> I haven't checked things is details (mostly because the resulting diff
> is impossible to read), but one thing caught my eye:
I agree, it's too bad the diff is so hard to read.
> On 01/09/16 16:38, Thomas Petazzoni wrote:
> > The MSI support introduced with the initial Aardvark driver was based
> > on the msi_controller structure and the of_pci_msi_chip_add() /
> > of_pci_find_msi_chip_by_node() API, which are being deprecated in
> > favor of the generic MSI support.
> >
> > Therefore, this commit updates the Aardvark driver to use the generic
> > MSI support.
> >
> > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> > ---
> > drivers/pci/host/pci-aardvark.c | 172 ++++++++++++++++------------------------
> > 1 file changed, 67 insertions(+), 105 deletions(-)
> >
> > diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
> > index ef9893f..0675cfa 100644
> > --- a/drivers/pci/host/pci-aardvark.c
> > +++ b/drivers/pci/host/pci-aardvark.c
>
> [...]
>
> > -static int advk_pcie_setup_msi_irq(struct msi_controller *chip,
> > - struct pci_dev *pdev,
> > - struct msi_desc *desc)
> > +static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
> > + unsigned int virq,
> > + unsigned int nr_irqs, void *args)
> > {
> > - struct advk_pcie *pcie = pdev->bus->sysdata;
> > - struct msi_msg msg;
> > - int virq, hwirq;
> > - phys_addr_t msi_msg_phys;
> > -
> > - /* We support MSI, but not MSI-X */
> > - if (desc->msi_attrib.is_msix)
> > - return -EINVAL;
>
> You used not to support MSIX...
>
> [...]
>
> > @@ -677,30 +650,25 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
> > {
> > struct device *dev = &pcie->pdev->dev;
> > struct device_node *node = dev->of_node;
> > - struct irq_chip *msi_irq_chip;
> > - struct msi_controller *msi;
> > + struct irq_chip *bottom_ic, *msi_ic;
> > + struct msi_domain_info *msi_di;
> > phys_addr_t msi_msg_phys;
> > - int ret;
> > -
> > - msi_irq_chip = &pcie->msi_irq_chip;
> >
> > - msi_irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-msi",
> > - dev_name(dev));
> > - if (!msi_irq_chip->name)
> > - return -ENOMEM;
> > + mutex_init(&pcie->msi_used_lock);
> >
> > - msi_irq_chip->irq_enable = pci_msi_unmask_irq;
> > - msi_irq_chip->irq_disable = pci_msi_mask_irq;
> > - msi_irq_chip->irq_mask = pci_msi_mask_irq;
> > - msi_irq_chip->irq_unmask = pci_msi_unmask_irq;
> > + bottom_ic = &pcie->msi_bottom_irq_chip;
> >
> > - msi = &pcie->msi;
> > + bottom_ic->name = "MSI";
> > + bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
> > + bottom_ic->irq_set_affinity = advk_msi_set_affinity;
> >
> > - msi->setup_irq = advk_pcie_setup_msi_irq;
> > - msi->teardown_irq = advk_pcie_teardown_msi_irq;
> > - msi->of_node = node;
> > + msi_ic = &pcie->msi_irq_chip;
> > + msi_ic->name = "advk-MSI";
> >
> > - mutex_init(&pcie->msi_used_lock);
> > + msi_di = &pcie->msi_domain_info;
> > + msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
> > + MSI_FLAG_PCI_MSIX;
>
> And yet you now advertize MSIX support. Was this an oversight in the
> original code?
If this is a fix, it'd be nice to have two patches:
1) make the fix
2) convert to new API
^ permalink raw reply
* [PATCH 0/3] nvmem: add lpc18xx OTP memory driver
From: Joachim Eastwood @ 2016-09-13 16:12 UTC (permalink / raw)
To: linux-arm-kernel
This patch set adds a simple read-only nvmem driver for the
internal OTP (One Time Programmable) memory found on all
LPC18xx/43xx devices. Write support is coming later when
the required firmware driver for the boot ROM goes upstream.
Note that dtsi patch is only included for reference. I intend
to take it myself through the lpc18xx tree once the bindings
are accepted and the driver goes upstream.
Joachim Eastwood (3):
nvmem: add NXP LPC18xx OTP driver
nvmem: dt: document lpc1850 OTP binding
ARM: dts: lpc18xx: add otp node
.../devicetree/bindings/nvmem/lpc1850-otp.txt | 20 ++++
arch/arm/boot/dts/lpc18xx.dtsi | 12 ++
drivers/nvmem/Kconfig | 10 ++
drivers/nvmem/Makefile | 2 +
drivers/nvmem/lpc18xx_otp.c | 123 +++++++++++++++++++++
5 files changed, 167 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt
create mode 100644 drivers/nvmem/lpc18xx_otp.c
--
2.9.3
^ permalink raw reply
* [PATCH 1/3] nvmem: add NXP LPC18xx OTP driver
From: Joachim Eastwood @ 2016-09-13 16:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160913161241.22492-1-manabian@gmail.com>
Add simple read only driver for the internal OTP (One Time Programmable)
memory found on all NXP LPC18xx and LPC43xx devices.
The OTP memory is split into 4 banks each with 4 32-bits word. Some of
the banks contain predefined data while others are for general purpose
and user programmable via the OTP API in ROM. Note that writing to the
OTP memory is not yet supported.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
---
drivers/nvmem/Kconfig | 10 ++++
drivers/nvmem/Makefile | 2 +
drivers/nvmem/lpc18xx_otp.c | 123 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 135 insertions(+)
create mode 100644 drivers/nvmem/lpc18xx_otp.c
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index f550c45..282037b 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -35,6 +35,16 @@ config NVMEM_LPC18XX_EEPROM
To compile this driver as a module, choose M here: the module
will be called nvmem_lpc18xx_eeprom.
+config NVMEM_LPC18XX_OTP
+ tristate "NXP LPC18XX OTP Memory Support"
+ depends on ARCH_LPC18XX || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ Say Y here to include support for NXP LPC18xx OTP memory found on
+ all LPC18xx and LPC43xx devices.
+ To compile this driver as a module, choose M here: the module
+ will be called nvmem_lpc18xx_otp.
+
config NVMEM_MXS_OCOTP
tristate "Freescale MXS On-Chip OTP Memory Support"
depends on ARCH_MXS || COMPILE_TEST
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 45ab1ae..df485a9 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -10,6 +10,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o
nvmem-imx-ocotp-y := imx-ocotp.o
obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o
nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o
+obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o
+nvmem_lpc18xx_otp-y := lpc18xx_otp.o
obj-$(CONFIG_NVMEM_MXS_OCOTP) += nvmem-mxs-ocotp.o
nvmem-mxs-ocotp-y := mxs-ocotp.o
obj-$(CONFIG_MTK_EFUSE) += nvmem_mtk-efuse.o
diff --git a/drivers/nvmem/lpc18xx_otp.c b/drivers/nvmem/lpc18xx_otp.c
new file mode 100644
index 0000000..b78ed0b
--- /dev/null
+++ b/drivers/nvmem/lpc18xx_otp.c
@@ -0,0 +1,123 @@
+/*
+ * NXP LPC18xx/43xx OTP memory NVMEM driver
+ *
+ * Copyright (c) 2016 Joachim Eastwood <manabian@gmail.com>
+ *
+ * Based on the imx ocotp driver,
+ * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * TODO: add support for writing OTP register via API in boot ROM.
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+/*
+ * LPC18xx OTP memory contains 4 banks with 4 32-bit words. Bank 0 starts
+ * at offset 0 from the base.
+ *
+ * Bank 0 contains the part ID for Flashless devices and is reseverd for
+ * devices with Flash.
+ * Bank 1/2 is generale purpose or AES key storage for secure devices.
+ * Bank 3 contains control data, USB ID and generale purpose words.
+ */
+#define LPC18XX_OTP_NUM_BANKS 4
+#define LPC18XX_OTP_WORDS_PER_BANK 4
+#define LPC18XX_OTP_WORD_SIZE sizeof(u32)
+#define LPC18XX_OTP_SIZE (LPC18XX_OTP_NUM_BANKS * \
+ LPC18XX_OTP_WORDS_PER_BANK * \
+ LPC18XX_OTP_WORD_SIZE)
+
+struct lpc18xx_otp {
+ void __iomem *base;
+};
+
+static int lpc18xx_otp_read(void *context, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct lpc18xx_otp *otp = context;
+ unsigned int count = bytes >> 2;
+ u32 index = offset >> 2;
+ u32 *buf = val;
+ int i;
+
+ if (count > (LPC18XX_OTP_SIZE - index))
+ count = LPC18XX_OTP_SIZE - index;
+
+ for (i = index; i < (index + count); i++)
+ *buf++ = readl(otp->base + i * LPC18XX_OTP_WORD_SIZE);
+
+ return 0;
+}
+
+static struct nvmem_config lpc18xx_otp_nvmem_config = {
+ .name = "lpc18xx-otp",
+ .read_only = true,
+ .word_size = LPC18XX_OTP_WORD_SIZE,
+ .stride = LPC18XX_OTP_WORD_SIZE,
+ .owner = THIS_MODULE,
+ .reg_read = lpc18xx_otp_read,
+};
+
+static int lpc18xx_otp_probe(struct platform_device *pdev)
+{
+ struct nvmem_device *nvmem;
+ struct lpc18xx_otp *otp;
+ struct resource *res;
+
+ otp = devm_kzalloc(&pdev->dev, sizeof(*otp), GFP_KERNEL);
+ if (!otp)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ otp->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(otp->base))
+ return PTR_ERR(otp->base);
+
+ lpc18xx_otp_nvmem_config.size = LPC18XX_OTP_SIZE;
+ lpc18xx_otp_nvmem_config.dev = &pdev->dev;
+ lpc18xx_otp_nvmem_config.priv = otp;
+
+ nvmem = nvmem_register(&lpc18xx_otp_nvmem_config);
+ if (IS_ERR(nvmem))
+ return PTR_ERR(nvmem);
+
+ platform_set_drvdata(pdev, nvmem);
+
+ return 0;
+}
+
+static int lpc18xx_otp_remove(struct platform_device *pdev)
+{
+ struct nvmem_device *nvmem = platform_get_drvdata(pdev);
+ return nvmem_unregister(nvmem);
+}
+
+static const struct of_device_id lpc18xx_otp_dt_ids[] = {
+ { .compatible = "nxp,lpc1850-otp" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, lpc18xx_otp_dt_ids);
+
+static struct platform_driver lpc18xx_otp_driver = {
+ .probe = lpc18xx_otp_probe,
+ .remove = lpc18xx_otp_remove,
+ .driver = {
+ .name = "lpc18xx_otp",
+ .of_match_table = lpc18xx_otp_dt_ids,
+ },
+};
+module_platform_driver(lpc18xx_otp_driver);
+
+MODULE_AUTHOR("Joachim Eastwoood <manabian@gmail.com>");
+MODULE_DESCRIPTION("NXP LPC18xx OTP NVMEM driver");
+MODULE_LICENSE("GPL v2");
--
2.9.3
^ permalink raw reply related
* [PATCH 2/3] nvmem: dt: document lpc1850 OTP binding
From: Joachim Eastwood @ 2016-09-13 16:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160913161241.22492-1-manabian@gmail.com>
Documenation for the LPC18xx/43xx OTP memory bindings.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
---
.../devicetree/bindings/nvmem/lpc1850-otp.txt | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt
diff --git a/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt b/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt
new file mode 100644
index 0000000..853b6a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt
@@ -0,0 +1,20 @@
+* NXP LPC18xx OTP memory
+
+Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
+
+Required properties:
+ - compatible: Should be "nxp,lpc1850-otp"
+ - reg: Must contain an entry with the physical base address and length
+ for each entry in reg-names.
+ - address-cells: must be set to 1.
+ - size-cells: must be set to 1.
+
+See nvmem.txt for more information.
+
+Example:
+ otp: otp at 40045000 {
+ compatible = "nxp,lpc1850-otp";
+ reg = <0x40045000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
--
2.9.3
^ permalink raw reply related
* [PATCH 3/3] ARM: dts: lpc18xx: add otp node
From: Joachim Eastwood @ 2016-09-13 16:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160913161241.22492-1-manabian@gmail.com>
Add node for the internal OTP (One Time Programmable) memory found
on all LPC18xx/43xx SoCs.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
---
arch/arm/boot/dts/lpc18xx.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi
index c6508ed..7ef0bc8 100644
--- a/arch/arm/boot/dts/lpc18xx.dtsi
+++ b/arch/arm/boot/dts/lpc18xx.dtsi
@@ -250,6 +250,18 @@
};
};
+ otp at 40045000 {
+ compatible = "nxp,lpc1850-otp";
+ reg = <0x40045000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Flashless devices has part ID in OTP bank 0 */
+ part_id: identification at 0 {
+ reg = <0x0 0x10>;
+ };
+ };
+
rtc: rtc at 40046000 {
compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
reg = <0x40046000 0x1000>;
--
2.9.3
^ permalink raw reply related
* pull request: linux-firmware: Update Mediatek MT8173 VPU firmware
From: Kyle McMartin @ 2016-09-13 16:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473337757-19723-1-git-send-email-andrew-ct.chen@mediatek.com>
On Thu, Sep 08, 2016 at 08:29:16PM +0800, Andrew-CT Chen wrote:
> Hi linux-firmware maintainers,
>
> The following changes since commit c883a6b6186bb2415761d287cbac773062911212:
>
> rtl_bt: Add firmware and config file for RTL8822BE (2016-08-31 02:38:31 +0100)
>
> are available in the git repository at:
>
> https://github.com/andrewct-chen/linux_fw_vpu_v1.0.2.git decoder_mdp
>
> for you to fetch changes up to 5b0873b6e750f906fe4244fd173df919c66e1b73:
>
> mediatek: Update firmware for decoder and MDP (2016-09-08 18:58:37 +0800)
>
Pulled, thanks.
regards, --Kyle
^ permalink raw reply
* [PATCH v5 07/14] drivers: acpi: iort: add support for ARM SMMU platform devices creation
From: Lorenzo Pieralisi @ 2016-09-13 16:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b0de32c2-01a5-2437-daa0-13044526b474@arm.com>
On Tue, Sep 13, 2016 at 04:25:55PM +0100, Robin Murphy wrote:
[...]
> > +/**
> > + * iort_add_smmu_platform_device() - Allocate a platform device for SMMU
> > + * @fwnode: IORT node associated fwnode handle
> > + * @node: Pointer to SMMU ACPI IORT node
> > + *
> > + * Returns: 0 on success, <0 failure
> > + */
> > +static int __init iort_add_smmu_platform_device(struct fwnode_handle *fwnode,
> > + struct acpi_iort_node *node)
> > +{
> > + struct platform_device *pdev;
> > + struct resource *r;
> > + enum dev_dma_attr attr;
> > + int ret, count;
> > + const struct iort_iommu_config *ops = iort_get_iommu_cfg(node);
> > +
> > + if (!ops)
> > + return -ENODEV;
> > +
> > + pdev = platform_device_alloc(ops->name, PLATFORM_DEVID_AUTO);
> > + if (!pdev)
> > + return PTR_ERR(pdev);
> > +
> > + count = ops->iommu_count_resources(node);
> > +
> > + r = kcalloc(count, sizeof(*r), GFP_KERNEL);
> > + if (!r) {
> > + ret = -ENOMEM;
> > + goto dev_put;
> > + }
> > +
> > + ops->iommu_init_resources(r, node);
> > +
> > + ret = platform_device_add_resources(pdev, r, count);
> > + /*
> > + * Resources are duplicated in platform_device_add_resources,
> > + * free their allocated memory
> > + */
> > + kfree(r);
> > +
> > + if (ret)
> > + goto dev_put;
> > +
> > + /*
> > + * Add a copy of IORT node pointer to platform_data to
> > + * be used to retrieve IORT data information.
> > + */
> > + ret = platform_device_add_data(pdev, &node, sizeof(node));
> > + if (ret)
> > + goto dev_put;
> > +
> > + pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
> > + if (!pdev->dev.dma_mask) {
> > + ret = -ENOMEM;
> > + goto dev_put;
> > + }
>
> Since this is exclusively for creating SMMUs, and we know they should
> never have weird shenanigans going on requiring different masks, I'd be
> inclined to just point dev.dma_mask at dev.coherent_dma_mask and be done
> with it.
That sounds reasonable yes, I will do.
> > +
> > + pdev->dev.fwnode = fwnode;
> > +
> > + /*
> > + * Set default dma mask value for the table walker,
> > + * to be overridden on probing with correct value.
> > + */
> > + *pdev->dev.dma_mask = DMA_BIT_MASK(32);
> > + pdev->dev.coherent_dma_mask = *pdev->dev.dma_mask;
> > +
> > + attr = ops->iommu_is_coherent(node) ?
> > + DEV_DMA_COHERENT : DEV_DMA_NON_COHERENT;
> > +
> > + /* Configure DMA for the page table walker */
> > + acpi_dma_configure(&pdev->dev, attr);
>
> Oh look, some more code which would be simpler if acpi_dma_configure()
> set the default mask itself ;)
Eheh I have no objections, apart from the effect that change can
have on non-ARM probing paths, it could also help remove some code
from ACPI core while at it.
Thanks !
Lorenzo
>
> Robin.
>
> > +
> > + ret = platform_device_add(pdev);
> > + if (ret)
> > + goto dma_deconfigure;
> > +
> > + return 0;
> > +
> > +dma_deconfigure:
> > + acpi_dma_deconfigure(&pdev->dev);
> > + kfree(pdev->dev.dma_mask);
> > +
> > +dev_put:
> > + platform_device_put(pdev);
> > +
> > + return ret;
> > +}
> > +
> > +static acpi_status __init iort_match_iommu_callback(struct acpi_iort_node *node,
> > + void *context)
> > +{
> > + int ret;
> > + struct fwnode_handle *fwnode;
> > +
> > + fwnode = iort_get_fwnode(node);
> > +
> > + if (!fwnode)
> > + return AE_NOT_FOUND;
> > +
> > + ret = iort_add_smmu_platform_device(fwnode, node);
> > + if (ret) {
> > + pr_err("Error in platform device creation\n");
> > + return AE_ERROR;
> > + }
> > +
> > + return AE_OK;
> > +}
> > +
> > +static void __init iort_smmu_init(void)
> > +{
> > + iort_scan_node(ACPI_IORT_NODE_SMMU, iort_match_iommu_callback, NULL);
> > + iort_scan_node(ACPI_IORT_NODE_SMMU_V3, iort_match_iommu_callback, NULL);
> > +}
> > +
> > void __init acpi_iort_init(void)
> > {
> > acpi_status status;
> > @@ -436,4 +566,5 @@ void __init acpi_iort_init(void)
> > }
> >
> > acpi_probe_device_table(iort);
> > + iort_smmu_init();
> > }
> >
>
^ permalink raw reply
* [PATCH v5 2/9] drivers: irqchip: Add STM32 external interrupts support
From: Alexandre Torgue @ 2016-09-13 16:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.20.1609131713490.6233@nanos>
Hi Thomas,
On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
> On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
>> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
>> + unsigned int nr_irqs)
>> +{
>> + struct irq_data *data = irq_get_irq_data(virq);
>> +
>> + irq_gc_mask_clr_bit(data->parent_data);
>
> I have a hard time to understand this. The irq domain is not hierarchical.
Actually, I wanted to test ".free" callback function of gpio_irq_domain
in STM32 pinctrl driver. To do that I modified gpio driver: just after
getting virq through gpio_to_irq, I called "irq_dispose_mapping(virq)".
I know it is dirty but I thought it was the only way to test.
Doing that, I see that ".free" callback of gpio domain is called but as
it is hirerchical ".free" callback for parent domain (exti one) is also
called. I observed that virq was well unmapped, but not masked at exti
level. It is for this reason than I added
"irq_gc_mask_clr_bit(data->parent_data);" which mask interrupt at exti
level.
Maybe this use case can never happen ? (and in this case all this stuff
is not needed)
>
>> + irq_domain_reset_irq_data(data);
>
>> + domain = irq_domain_add_linear(node, nr_exti,
>> + &irq_exti_domain_ops, NULL);
>
> It's a simple linear domain. So how can data->parent_data be a valid
> irq_data pointer? Answer: It can't!
This Exti domain is parent of stm32 gpio domain. When ".free" callback
of stm32 gpio domain is called then ".free" callback of Exti domain will
be automatically called. Those both ".free" callbacks are called with
"virq". This virq is created through stm32 gpio domain (in stm32 pinctrl
driver), data and parent->data are then associated to it.
Sorry if it is not clear.
Regards
Alex
>
> But it doesn't blow up in your face simply because the alloc/free callbacks
> are never invoked for simple non hierarchical domains. So you should have
> removed that stuff after copying some other irqchip driver.
>
> Thanks,
>
> tglx
>
^ permalink raw reply
* [PATCH 1/2] PCI: save and restore device state during bus reset
From: Bjorn Helgaas @ 2016-09-13 16:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1472770801-30671-1-git-send-email-okaya@codeaurora.org>
On Thu, Sep 01, 2016 at 07:00:00PM -0400, Sinan Kaya wrote:
> A secondary bus reset causes settings to be lost by all downstream
> devices on the tree. The code is currently saving and restoring device
> states only when called from the VFIO path via pci_probe_reset_bus
> and pci_reset_bus functions.
>
> Moving the save and restore into pci_reset_bridge_secondary_bus
> so that all users of the API have the same behavior.
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> ---
> drivers/pci/pci.c | 36 +++++++++++++++---------------------
> 1 file changed, 15 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index aab9d51..b209378 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -3860,19 +3860,6 @@ void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
> pci_reset_secondary_bus(dev);
> }
>
> -/**
> - * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
> - * @dev: Bridge device
> - *
> - * Use the bridge control register to assert reset on the secondary bus.
> - * Devices on the secondary bus are left in power-on state.
> - */
> -void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
> -{
> - pcibios_reset_secondary_bus(dev);
> -}
> -EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
> -
> static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
> {
> struct pci_dev *pdev;
> @@ -4362,6 +4349,21 @@ static void pci_slot_restore(struct pci_slot *slot)
> }
> }
>
> +/**
> + * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
> + * @dev: Bridge device
> + *
> + * Use the bridge control register to assert reset on the secondary bus.
> + * Devices on the secondary bus are left in power-on state.
This comment is no longer correct (you don't leave the devices in
power-on state).
> + */
> +void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
> +{
> + pci_bus_save_and_disable(dev->bus);
"dev" is a bridge, and dev->bus is the bus on the *primary* side of
the bridge, so I think this saves and disables the bridge itself.
Don't you want dev->subordinate here instead?
> + pcibios_reset_secondary_bus(dev);
> + pci_bus_restore(dev->bus);
> +}
> +EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
> +
> static int pci_slot_reset(struct pci_slot *slot, int probe)
> {
> int rc;
> @@ -4504,12 +4506,8 @@ int pci_reset_bus(struct pci_bus *bus)
> if (rc)
> return rc;
>
> - pci_bus_save_and_disable(bus);
> -
> rc = pci_bus_reset(bus, 0);
>
> - pci_bus_restore(bus);
> -
> return rc;
> }
> EXPORT_SYMBOL_GPL(pci_reset_bus);
> @@ -4528,8 +4526,6 @@ int pci_try_reset_bus(struct pci_bus *bus)
> if (rc)
> return rc;
>
> - pci_bus_save_and_disable(bus);
> -
> if (pci_bus_trylock(bus)) {
> might_sleep();
> pci_reset_bridge_secondary_bus(bus->self);
> @@ -4537,8 +4533,6 @@ int pci_try_reset_bus(struct pci_bus *bus)
> } else
> rc = -EAGAIN;
>
> - pci_bus_restore(bus);
> -
> return rc;
> }
> EXPORT_SYMBOL_GPL(pci_try_reset_bus);
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH v2] iommu/io-pgtable-arm: Check for v7s-incapable systems
From: Robin Murphy @ 2016-09-13 17:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2e473e263ac469bd6d3b09e7756c138325e10969.1473773198.git.robin.murphy@arm.com>
On machines with no 32-bit addressable RAM whatsoever, we shouldn't
even touch the v7s format as it's never going to work.
Fixes: e5fc9753b1a8 ("iommu/io-pgtable: Add ARMv7 short descriptor support")
Reported-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
Apparently, in my haste, I overlooked that not everything that can do
COMPILE_TEST also has a PHYS_OFFSET.
drivers/iommu/io-pgtable-arm-v7s.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index def8ca1c982d..f50e51c1a9c8 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -633,6 +633,10 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
{
struct arm_v7s_io_pgtable *data;
+#ifdef PHYS_OFFSET
+ if (upper_32_bits(PHYS_OFFSET))
+ return NULL;
+#endif
if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS)
return NULL;
--
2.8.1.dirty
^ permalink raw reply related
* [RFC PATCH] pci: support for configurable PCI endpoint
From: Kishon Vijay Abraham I @ 2016-09-13 17:10 UTC (permalink / raw)
To: linux-arm-kernel
This patch series
*) adds PCI endpoint core layer
*) modifies designware/dra7xx driver to be configured in EP mode
*) adds a PCI endpoint *test* function driver
Known Limitation:
*) Does not support multi-function devices
TODO:
*) access buffers in RC
*) MSI interrupts
*) Enable user space control for the RC side PCI driver
*) Adapt all other users of designware to use the new design
HOW TO:
ON THE EP SIDE:
***************
/* EP function is configured using configfs */
# mount -t configfs none /sys/kernel/config
/* PCI EP core layer creates "pci_ep" entry in configfs */
# cd /sys/kernel/config/pci_ep/
/*
* This is the 1st step in creating an endpoint function. This
* creates the endpoint function device *instance*. The string
* before the .<num> suffix will identify the driver this
* EP function will bind to.
* Just pci_epf_test is also valid. The .<num> suffix is used
* if there are multiple PCI controllers and all of them wants
* to use the same function.
*/
# mkdir pci_epf_test.0
/*
* When the above command is given, the function device will
* also be bound to a function driver. To find the list of
* function drivers available in the system, use the following
* command. To create a new driver, the following can be referred
* drivers/pci/endpoint/functions/pci-epf-test.c
*/
# ls /sys/bus/pci-epf/drivers
pci_epf_test
/* Now configure the endpoint function */
# cd pci_epf_test.0
/* These are the fields that can be configured */
# ls
baseclass_code function revid vendorid
cache_line_size interrupt_pin subclass_code
deviceid peripheral subsys_id
epc progif_code subsys_vendor_id
/* The function driver will populate these fields with default values */
# cat vendorid
0xffff
# cat interrupt_pin
0x0001
/* The user can configure any of these fields */
# echo 0x104c > vendorid
/*
* Next is binding this function driver to the controller driver. In
* order to find the possible controller drivers that this function
* driver can be bound to, the following sysfs entry can be used
*/
# ls /sys/class/pci_epc/
51000000.pci
/* Now bind the function driver to the controller driver */
# echo "51000000.pcie" > epc
[ 494.743487] dra7-pcie 51000000.pcie: no free inbound window
[ 494.749367] pci_epf_test pci_epf_test.0: failed to set BAR4
[ 494.755238] dra7-pcie 51000000.pcie: no free inbound window
[ 494.761451] pci_epf_test pci_epf_test.0: failed to set BAR5
/*
* the above error messages are due to non availability of free
* inbound windows. So the function drivers in dra7xx can use
* only 4 (BAR0..BAR3) BARs
*/
/****** PCI endpoint is configured ******/
ON THE HOST SIDE:
*****************
# modprobe pci_endpoint_test
[ 8.197560] ****** Testing pci-endpoint-test Device ******
[ 9.056990] Reset: OKAY
[ 9.059753] BAR1 OKAY
[ 9.062419] BAR2 OKAY
[ 9.069506] BAR3 OKAY
[ 9.071880] BAR4 NOT OKAY
[ 9.074618] BAR5 NOT OKAY
[ 9.379257] Legacy IRQ: OKAY
[ 9.382281] ****** End Test ******
/*
* Rightnow these tests gets executed as soon as the pci_endpoint_test
* module gets inserted. These will be modified so that user/user script
* can control this. Once the functionality for EP to access RC buffer
* is added, more tests can be added including throughput measurement tests.
*/
Kishon Vijay Abraham I (11):
pci: endpoint: add EP core layer to enable EP controller and EP
functions
pci: endpoint: introduce configfs entry for configuring EP functions
Documentation: PCI: guide to use PCI Endpoint Core Layer
pci: endpoint: functions: add an EP function to test PCI
pci: rename *host* directory to *controller*
pci: controller: split designware into *core* and *host*
pci: controller: designware: Add EP mode support
pci: controller: dra7xx: Add EP mode support
misc: add a new host side PCI endpoint test driver
ARM: dts: DRA7: Modify pcie1 dt node for EP mode
HACK: pci: controller: dra7xx: disable smart idle
Documentation/PCI/00-INDEX | 5 +
Documentation/PCI/pci-endpoint.txt | 199 ++++++++++
Documentation/PCI/pci-test.txt | 79 ++++
.../devicetree/bindings/pci/designware-pcie.txt | 26 +-
Documentation/devicetree/bindings/pci/ti-pci.txt | 30 +-
MAINTAINERS | 50 +--
arch/arm/boot/dts/dra7.dtsi | 43 +--
drivers/Makefile | 4 +
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 1 +
drivers/misc/pci_endpoint_test.c | 291 +++++++++++++++
drivers/pci/Kconfig | 3 +-
drivers/pci/Makefile | 3 -
drivers/pci/{host => controller}/Kconfig | 109 +++++-
drivers/pci/{host => controller}/Makefile | 2 +
drivers/pci/{host => controller}/pci-aardvark.c | 0
drivers/pci/{host => controller}/pci-dra7xx.c | 340 +++++++++++++----
drivers/pci/{host => controller}/pci-exynos.c | 0
drivers/pci/{host => controller}/pci-host-common.c | 0
.../pci/{host => controller}/pci-host-generic.c | 0
drivers/pci/{host => controller}/pci-hyperv.c | 0
drivers/pci/{host => controller}/pci-imx6.c | 0
drivers/pci/{host => controller}/pci-keystone-dw.c | 0
drivers/pci/{host => controller}/pci-keystone.c | 0
drivers/pci/{host => controller}/pci-keystone.h | 0
drivers/pci/{host => controller}/pci-layerscape.c | 0
drivers/pci/{host => controller}/pci-mvebu.c | 0
drivers/pci/{host => controller}/pci-rcar-gen2.c | 0
drivers/pci/{host => controller}/pci-tegra.c | 0
.../pci/{host => controller}/pci-thunder-ecam.c | 0
drivers/pci/{host => controller}/pci-thunder-pem.c | 0
drivers/pci/{host => controller}/pci-versatile.c | 0
drivers/pci/{host => controller}/pci-xgene-msi.c | 0
drivers/pci/{host => controller}/pci-xgene.c | 0
drivers/pci/{host => controller}/pcie-altera-msi.c | 0
drivers/pci/{host => controller}/pcie-altera.c | 0
drivers/pci/{host => controller}/pcie-armada8k.c | 0
drivers/pci/{host => controller}/pcie-artpec6.c | 0
drivers/pci/controller/pcie-designware-ep.c | 228 ++++++++++++
.../pcie-designware-host.c} | 294 +++------------
.../{host => controller}/pcie-designware-plat.c | 0
drivers/pci/controller/pcie-designware.c | 233 ++++++++++++
drivers/pci/controller/pcie-designware.h | 238 ++++++++++++
drivers/pci/{host => controller}/pcie-hisi.c | 0
drivers/pci/{host => controller}/pcie-iproc-bcma.c | 0
drivers/pci/{host => controller}/pcie-iproc-msi.c | 0
.../pci/{host => controller}/pcie-iproc-platform.c | 0
drivers/pci/{host => controller}/pcie-iproc.c | 0
drivers/pci/{host => controller}/pcie-iproc.h | 0
drivers/pci/{host => controller}/pcie-qcom.c | 0
drivers/pci/{host => controller}/pcie-rcar.c | 0
drivers/pci/{host => controller}/pcie-spear13xx.c | 0
drivers/pci/{host => controller}/pcie-xilinx-nwl.c | 0
drivers/pci/{host => controller}/pcie-xilinx.c | 0
drivers/pci/endpoint/Kconfig | 25 ++
drivers/pci/endpoint/Makefile | 6 +
drivers/pci/endpoint/functions/Kconfig | 12 +
drivers/pci/endpoint/functions/Makefile | 5 +
drivers/pci/endpoint/functions/pci-epf-test.c | 272 ++++++++++++++
drivers/pci/endpoint/pci-ep-cfs.c | 275 ++++++++++++++
drivers/pci/endpoint/pci-epc-core.c | 389 ++++++++++++++++++++
drivers/pci/endpoint/pci-epf-core.c | 338 +++++++++++++++++
drivers/pci/host/pcie-designware.h | 89 -----
include/linux/mod_devicetable.h | 10 +
include/linux/pci-epc.h | 100 +++++
include/linux/pci-epf.h | 159 ++++++++
66 files changed, 3373 insertions(+), 492 deletions(-)
create mode 100644 Documentation/PCI/pci-endpoint.txt
create mode 100644 Documentation/PCI/pci-test.txt
create mode 100644 drivers/misc/pci_endpoint_test.c
rename drivers/pci/{host => controller}/Kconfig (79%)
rename drivers/pci/{host => controller}/Makefile (93%)
rename drivers/pci/{host => controller}/pci-aardvark.c (100%)
rename drivers/pci/{host => controller}/pci-dra7xx.c (62%)
rename drivers/pci/{host => controller}/pci-exynos.c (100%)
rename drivers/pci/{host => controller}/pci-host-common.c (100%)
rename drivers/pci/{host => controller}/pci-host-generic.c (100%)
rename drivers/pci/{host => controller}/pci-hyperv.c (100%)
rename drivers/pci/{host => controller}/pci-imx6.c (100%)
rename drivers/pci/{host => controller}/pci-keystone-dw.c (100%)
rename drivers/pci/{host => controller}/pci-keystone.c (100%)
rename drivers/pci/{host => controller}/pci-keystone.h (100%)
rename drivers/pci/{host => controller}/pci-layerscape.c (100%)
rename drivers/pci/{host => controller}/pci-mvebu.c (100%)
rename drivers/pci/{host => controller}/pci-rcar-gen2.c (100%)
rename drivers/pci/{host => controller}/pci-tegra.c (100%)
rename drivers/pci/{host => controller}/pci-thunder-ecam.c (100%)
rename drivers/pci/{host => controller}/pci-thunder-pem.c (100%)
rename drivers/pci/{host => controller}/pci-versatile.c (100%)
rename drivers/pci/{host => controller}/pci-xgene-msi.c (100%)
rename drivers/pci/{host => controller}/pci-xgene.c (100%)
rename drivers/pci/{host => controller}/pcie-altera-msi.c (100%)
rename drivers/pci/{host => controller}/pcie-altera.c (100%)
rename drivers/pci/{host => controller}/pcie-armada8k.c (100%)
rename drivers/pci/{host => controller}/pcie-artpec6.c (100%)
create mode 100644 drivers/pci/controller/pcie-designware-ep.c
rename drivers/pci/{host/pcie-designware.c => controller/pcie-designware-host.c} (64%)
rename drivers/pci/{host => controller}/pcie-designware-plat.c (100%)
create mode 100644 drivers/pci/controller/pcie-designware.c
create mode 100644 drivers/pci/controller/pcie-designware.h
rename drivers/pci/{host => controller}/pcie-hisi.c (100%)
rename drivers/pci/{host => controller}/pcie-iproc-bcma.c (100%)
rename drivers/pci/{host => controller}/pcie-iproc-msi.c (100%)
rename drivers/pci/{host => controller}/pcie-iproc-platform.c (100%)
rename drivers/pci/{host => controller}/pcie-iproc.c (100%)
rename drivers/pci/{host => controller}/pcie-iproc.h (100%)
rename drivers/pci/{host => controller}/pcie-qcom.c (100%)
rename drivers/pci/{host => controller}/pcie-rcar.c (100%)
rename drivers/pci/{host => controller}/pcie-spear13xx.c (100%)
rename drivers/pci/{host => controller}/pcie-xilinx-nwl.c (100%)
rename drivers/pci/{host => controller}/pcie-xilinx.c (100%)
create mode 100644 drivers/pci/endpoint/Kconfig
create mode 100644 drivers/pci/endpoint/Makefile
create mode 100644 drivers/pci/endpoint/functions/Kconfig
create mode 100644 drivers/pci/endpoint/functions/Makefile
create mode 100644 drivers/pci/endpoint/functions/pci-epf-test.c
create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c
create mode 100644 drivers/pci/endpoint/pci-epc-core.c
create mode 100644 drivers/pci/endpoint/pci-epf-core.c
delete mode 100644 drivers/pci/host/pcie-designware.h
create mode 100644 include/linux/pci-epc.h
create mode 100644 include/linux/pci-epf.h
--
1.7.9.5
^ permalink raw reply
* [RFC PATCH] pci: endpoint: add EP core layer to enable EP controller and EP functions
From: Kishon Vijay Abraham I @ 2016-09-13 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473786653-12759-1-git-send-email-kishon@ti.com>
Introduce a new EP core layer in order to support endpoint functions
in linux kernel. This comprises of EPC library
(Endpoint Controller Library) and EPF library (Endpoint
Function Library). EPC library implements functions that is specific
to an endpoint controller and EPF library implements functions
that is specific to an endpoint function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/Makefile | 1 +
drivers/pci/Kconfig | 1 +
drivers/pci/endpoint/Kconfig | 21 ++
drivers/pci/endpoint/Makefile | 5 +
drivers/pci/endpoint/pci-epc-core.c | 389 +++++++++++++++++++++++++++++++++++
drivers/pci/endpoint/pci-epf-core.c | 338 ++++++++++++++++++++++++++++++
include/linux/mod_devicetable.h | 10 +
include/linux/pci-epc.h | 100 +++++++++
include/linux/pci-epf.h | 159 ++++++++++++++
9 files changed, 1024 insertions(+)
create mode 100644 drivers/pci/endpoint/Kconfig
create mode 100644 drivers/pci/endpoint/Makefile
create mode 100644 drivers/pci/endpoint/pci-epc-core.c
create mode 100644 drivers/pci/endpoint/pci-epf-core.c
create mode 100644 include/linux/pci-epc.h
create mode 100644 include/linux/pci-epf.h
diff --git a/drivers/Makefile b/drivers/Makefile
index 53abb4a..8c070ad 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_GENERIC_PHY) += phy/
obj-$(CONFIG_PINCTRL) += pinctrl/
obj-$(CONFIG_GPIOLIB) += gpio/
obj-y += pwm/
+obj-$(CONFIG_PCI_ENDPOINT) += pci/endpoint/
obj-$(CONFIG_PCI) += pci/
obj-$(CONFIG_PARISC) += parisc/
obj-$(CONFIG_RAPIDIO) += rapidio/
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 67f9916..5f116a6 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -133,3 +133,4 @@ config PCI_HYPERV
source "drivers/pci/hotplug/Kconfig"
source "drivers/pci/host/Kconfig"
+source "drivers/pci/endpoint/Kconfig"
diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
new file mode 100644
index 0000000..a6d827c
--- /dev/null
+++ b/drivers/pci/endpoint/Kconfig
@@ -0,0 +1,21 @@
+#
+# PCI Endpoint Support
+#
+
+menu "PCI Endpoint"
+
+config PCI_ENDPOINT
+ tristate "PCI Endpoint Support"
+ help
+ Enable this configuration option to support configurable PCI
+ endpoint. This should be enabled if the platform has a PCI
+ controller that can operate in endpoint mode.
+
+ Enabling this option will build the endpoint library, which
+ includes endpoint controller library and endpoint function
+ library.
+
+ If in doubt, say "N" to disable Endpoint support.
+
+endmenu
+
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
new file mode 100644
index 0000000..dbc5517
--- /dev/null
+++ b/drivers/pci/endpoint/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for PCI Endpoint Support
+#
+
+obj-$(CONFIG_PCI_ENDPOINT) := pci-epc-core.o pci-epf-core.o
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
new file mode 100644
index 0000000..003d2ee
--- /dev/null
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -0,0 +1,389 @@
+/**
+ * pci-epc-core.c - PCI Endpoint *Controller* (EPC) library
+ *
+ * Copyright (C) 2016 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+
+static struct class *pci_epc_class;
+
+static void devm_pci_epc_release(struct device *dev, void *res)
+{
+ struct pci_epc *epc = *(struct pci_epc **)res;
+
+ pci_epc_destroy(epc);
+}
+
+static int devm_pci_epc_match(struct device *dev, void *res, void *match_data)
+{
+ struct pci_epc **epc = res;
+
+ return *epc == match_data;
+}
+
+/**
+ * pci_epc_unbind_epf() - unbind the endpoint function and endpoint controller
+ * @epf: the endpoint function which has requested for unbinding
+ *
+ * Invoke to unbind the endpoint function and endpoint controller
+ */
+void pci_epc_unbind_epf(struct pci_epf *epf)
+{
+ struct pci_epc *epc = epf->epc;
+
+ pci_epf_unbind(epf);
+ module_put(epc->ops->owner);
+ epf->epc = NULL;
+ epc->epf = NULL;
+}
+EXPORT_SYMBOL_GPL(pci_epc_unbind_epf);
+
+/**
+ * pci_epc_bind_epf() - bind the endpoint function with an endpoint controller
+ * @epf: endpoint function which has to be bound to an endpoint controller
+ *
+ * Invoke to bind the endpoint function with an endpoint controller based on
+ * pci_epc_name.
+ */
+int pci_epc_bind_epf(struct pci_epf *epf)
+{
+ int ret = -EINVAL;
+ struct pci_epc *epc;
+ struct device *dev;
+ struct class_dev_iter iter;
+
+ class_dev_iter_init(&iter, pci_epc_class, NULL, NULL);
+ while ((dev = class_dev_iter_next(&iter))) {
+ if (strcmp(epf->pci_epc_name, dev_name(dev)))
+ continue;
+
+ epc = to_pci_epc(dev);
+ if (epc->epf) {
+ ret = -EBUSY;
+ goto err;
+ }
+
+ if (!try_module_get(epc->ops->owner)) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ epf->epc = epc;
+ epc->epf = epf;
+
+ dma_set_coherent_mask(&epf->dev, epc->dev.coherent_dma_mask);
+ epf->dev.dma_mask = epc->dev.dma_mask;
+
+ pci_epf_bind(epf);
+ class_dev_iter_exit(&iter);
+ return 0;
+ }
+
+err:
+ class_dev_iter_exit(&iter);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_bind_epf);
+
+/**
+ * pci_epc_stop() - stop the PCI link
+ * @epc: the link of the EPC device that has to be stopped
+ *
+ * Invoke to stop the PCI link
+ */
+void pci_epc_stop(struct pci_epc *epc)
+{
+ if (IS_ERR(epc) || !epc->ops->stop)
+ return;
+
+ spin_lock_irq(&epc->irq_lock);
+ epc->ops->stop(epc);
+ spin_unlock_irq(&epc->irq_lock);
+}
+EXPORT_SYMBOL_GPL(pci_epc_stop);
+
+/**
+ * pci_epc_start() - start the PCI link
+ * @epc: the link of the EPC device that has to be started
+ *
+ * Invoke to start the PCI link
+ */
+int pci_epc_start(struct pci_epc *epc)
+{
+ int ret;
+
+ if (IS_ERR(epc))
+ return -EINVAL;
+
+ if (!epc->ops->start)
+ return 0;
+
+ spin_lock_irq(&epc->irq_lock);
+ ret = epc->ops->start(epc);
+ spin_unlock_irq(&epc->irq_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_start);
+
+/**
+ * pci_epc_raise_irq() - interrupt the host system
+ * @epc: the EPC device which has to interrupt the host
+ * @type: specify the type of interrupt; legacy or MSI
+ *
+ * Invoke to raise an MSI or legacy interrupt
+ */
+int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type)
+{
+ int ret;
+
+ if (IS_ERR(epc))
+ return -EINVAL;
+
+ if (!epc->ops->raise_irq)
+ return 0;
+
+ spin_lock_irq(&epc->irq_lock);
+ ret = epc->ops->raise_irq(epc, type);
+ spin_unlock_irq(&epc->irq_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_raise_irq);
+
+/**
+ * pci_epc_clear_bar() - reset the BAR
+ * @epc: the EPC device for which the BAR has to be cleared
+ * @bar: the bar number that has to be reset
+ *
+ * Invoke to reset the BAR of the endpoint device.
+ */
+void pci_epc_clear_bar(struct pci_epc *epc, int bar)
+{
+ if (IS_ERR(epc))
+ return;
+
+ if (!epc->ops->clear_bar)
+ return;
+
+ spin_lock_irq(&epc->irq_lock);
+ epc->ops->clear_bar(epc, bar);
+ spin_unlock_irq(&epc->irq_lock);
+}
+EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
+
+/**
+ * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space
+ * @epc: the EPC device on which BAR has to be configured
+ * @bar: the bar number that has to be configured
+ * @size: the size of the addr space
+ * @flags: specify memory allocation/io allocation/32bit address/64 bit address
+ *
+ * Invoke to configure the BAR of the endpoint device.
+ */
+int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
+ dma_addr_t bar_phys, size_t size, int flags)
+{
+ int ret;
+
+ if (IS_ERR(epc))
+ return -EINVAL;
+
+ if (!epc->ops->set_bar)
+ return 0;
+
+ spin_lock_irq(&epc->irq_lock);
+ ret = epc->ops->set_bar(epc, bar, bar_phys, size, flags);
+ spin_unlock_irq(&epc->irq_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_set_bar);
+
+/**
+ * pci_epc_write_header() - write standard configuration header
+ * @epc: the EPC device to which the configuration header should be written
+ * @header: standard configuration header fields
+ *
+ * Invoke to write the configuration header to the endpoint controller. Every
+ * endpoint controller will have a dedicated location to which the standard
+ * configuration header would be written. The callback function should write
+ * the header fields to this dedicated location.
+ */
+int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *header)
+{
+ int ret;
+
+ if (IS_ERR(epc))
+ return -EINVAL;
+
+ if (!epc->ops->write_header)
+ return 0;
+
+ spin_lock_irq(&epc->irq_lock);
+ ret = epc->ops->write_header(epc, header);
+ spin_unlock_irq(&epc->irq_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_epc_write_header);
+
+/**
+ * pci_epc_destroy() - destroy the EPC device
+ * @epc: the EPC device that has to be destroyed
+ *
+ * Invoke to destroy the PCI EPC device
+ */
+void pci_epc_destroy(struct pci_epc *epc)
+{
+ device_unregister(&epc->dev);
+ kfree(epc);
+}
+EXPORT_SYMBOL_GPL(pci_epc_destroy);
+
+/**
+ * devm_pci_epc_destroy() - destroy the EPC device
+ * @dev: device that wants to destroy the EPC
+ * @epc: the EPC device that has to be destroyed
+ *
+ * Invoke to destroy the devres associated with this
+ * pci_epc and destroy the EPC device.
+ */
+void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc)
+{
+ int r;
+
+ r = devres_destroy(dev, devm_pci_epc_release, devm_pci_epc_match,
+ epc);
+ dev_WARN_ONCE(dev, r, "couldn't find PCI EPC resource\n");
+}
+EXPORT_SYMBOL_GPL(devm_pci_epc_destroy);
+
+/**
+ * __pci_epc_create() - create a new endpoint controller (EPC) device
+ * @dev: device that is creating the new EPC
+ * @ops: function pointers for performing EPC operations
+ * @owner: the owner of the module that creates the EPC device
+ *
+ * Invoke to create a new EPC device and add it to pci_epc class.
+ */
+struct pci_epc *
+__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
+ struct module *owner)
+{
+ int ret;
+ struct pci_epc *epc;
+
+ if (WARN_ON(!dev)) {
+ ret = -EINVAL;
+ goto err_ret;
+ }
+
+ epc = kzalloc(sizeof(*epc), GFP_KERNEL);
+ if (!epc) {
+ ret = -ENOMEM;
+ goto err_ret;
+ }
+
+ spin_lock_init(&epc->irq_lock);
+
+ device_initialize(&epc->dev);
+ dma_set_coherent_mask(&epc->dev, dev->coherent_dma_mask);
+ epc->dev.class = pci_epc_class;
+ epc->dev.dma_mask = dev->dma_mask;
+ epc->ops = ops;
+
+ ret = dev_set_name(&epc->dev, "%s", dev_name(dev));
+ if (ret)
+ goto put_dev;
+
+ ret = device_add(&epc->dev);
+ if (ret)
+ goto put_dev;
+
+ return epc;
+
+put_dev:
+ put_device(&epc->dev);
+ kfree(epc);
+
+err_ret:
+ return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(__pci_epc_create);
+
+/**
+ * __devm_pci_epc_create() - create a new endpoint controller (EPC) device
+ * @dev: device that is creating the new EPC
+ * @ops: function pointers for performing EPC operations
+ * @owner: the owner of the module that creates the EPC device
+ *
+ * Invoke to create a new EPC device and add it to pci_epc class.
+ * While at that, it also associates the device with the pci_epc using devres.
+ * On driver detach, release function is invoked on the devres data,
+ * then, devres data is freed.
+ */
+struct pci_epc *
+__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
+ struct module *owner)
+{
+ struct pci_epc **ptr, *epc;
+
+ ptr = devres_alloc(devm_pci_epc_release, sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return ERR_PTR(-ENOMEM);
+
+ epc = __pci_epc_create(dev, ops, owner);
+ if (!IS_ERR(epc)) {
+ *ptr = epc;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return epc;
+}
+EXPORT_SYMBOL_GPL(__devm_pci_epc_create);
+
+static int __init pci_epc_init(void)
+{
+ pci_epc_class = class_create(THIS_MODULE, "pci_epc");
+ if (IS_ERR(pci_epc_class)) {
+ pr_err("failed to create pci epc class --> %ld\n",
+ PTR_ERR(pci_epc_class));
+ return PTR_ERR(pci_epc_class);
+ }
+
+ return 0;
+}
+module_init(pci_epc_init);
+
+static void __exit pci_epc_exit(void)
+{
+ class_destroy(pci_epc_class);
+}
+module_exit(pci_epc_exit);
+
+MODULE_DESCRIPTION("PCI EPC Library");
+MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c
new file mode 100644
index 0000000..2802267
--- /dev/null
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -0,0 +1,338 @@
+/**
+ * pci-epf-core.c - PCI Endpoint *Function* (EPF) library
+ *
+ * Copyright (C) 2016 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+
+static struct bus_type pci_epf_bus_type;
+static struct device_type pci_epf_type;
+
+/**
+ * pci_epf_linkup() - Notify the function driver that EPC device has
+ * established a connection with the Root Complex.
+ * @epf: the EPF device bound to the EPC device which has established
+ * the connection with the host
+ *
+ * Invoke to notify the function driver that EPC device has established
+ * a connection with the Root Complex.
+ */
+void pci_epf_linkup(struct pci_epf *epf)
+{
+ epf->driver->ops->linkup(epf);
+}
+EXPORT_SYMBOL_GPL(pci_epf_linkup);
+
+/**
+ * pci_epf_unbind() - Notify the function driver that the binding between the
+ * EPF device and EPC device has been lost
+ * @epf: the EPF device which has lost the binding with the EPC device
+ *
+ * Invoke to notify the function driver that the binding between the EPF device
+ * and EPC device has been lost.
+ */
+void pci_epf_unbind(struct pci_epf *epf)
+{
+ epf->driver->ops->unbind(epf);
+ module_put(epf->driver->owner);
+}
+EXPORT_SYMBOL_GPL(pci_epf_unbind);
+
+/**
+ * pci_epf_bind() - Notify the function driver that the EPF device has been
+ * bound to a EPC device
+ * @epf: the EPF device which has been bound to the EPC device
+ *
+ * Invoke to notify the function driver that it has been bound to a EPC device
+ */
+int pci_epf_bind(struct pci_epf *epf)
+{
+ if (!try_module_get(epf->driver->owner))
+ return -EAGAIN;
+
+ return epf->driver->ops->bind(epf);
+}
+EXPORT_SYMBOL_GPL(pci_epf_bind);
+
+/**
+ * pci_epf_free_space() - free the allocated PCI EPF register space
+ * @addr: the virtual address of the PCI EPF register space
+ * @bar: the bar number corresponding to the register space
+ *
+ * Invoke to free the allocated PCI EPF register space.
+ */
+void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar)
+{
+ struct device *dev = &epf->dev;
+
+ if (!addr)
+ return;
+
+ dma_free_coherent(dev, epf->bar[bar].size, addr,
+ epf->bar[bar].phys_addr);
+
+ epf->bar[bar].phys_addr = 0;
+ epf->bar[bar].size = 0;
+}
+EXPORT_SYMBOL_GPL(pci_epf_free_space);
+
+/**
+ * pci_epf_alloc_space() - allocate memory for the PCI EPF register space
+ * @size: the size of the memory that has to be allocated
+ * @bar: the bar number corresponding to the allocated register space
+ *
+ * Invoke to allocate memory for the PCI EPF register space.
+ */
+void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar)
+{
+ void *space;
+ struct device *dev = &epf->dev;
+ dma_addr_t phys_addr;
+
+ if (size < 128)
+ size = 128;
+ size = roundup_pow_of_two(size);
+
+ space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
+ if (!space) {
+ dev_err(dev, "failed to allocate mem space\n");
+ return NULL;
+ }
+
+ epf->bar[bar].phys_addr = phys_addr;
+ epf->bar[bar].size = size;
+
+ return space;
+}
+EXPORT_SYMBOL_GPL(pci_epf_alloc_space);
+
+/**
+ * pci_epf_unregister_driver() - unregister the PCI EPF driver
+ * @driver: the PCI EPF driver that has to be unregistered
+ *
+ * Invoke to unregister the PCI EPF driver.
+ */
+void pci_epf_unregister_driver(struct pci_epf_driver *driver)
+{
+ driver_unregister(&driver->driver);
+}
+EXPORT_SYMBOL_GPL(pci_epf_unregister_driver);
+
+/**
+ * __pci_epf_register_driver() - register a new PCI EPF driver
+ * @driver: structure representing PCI EPF driver
+ * @owner: the owner of the module that registers the PCI EPF driver
+ *
+ * Invoke to register a new PCI EPF driver.
+ */
+int __pci_epf_register_driver(struct pci_epf_driver *driver,
+ struct module *owner)
+{
+ int ret;
+
+ if (!driver->ops)
+ return -EINVAL;
+
+ if (!driver->ops->bind || !driver->ops->unbind || !driver->ops->linkup)
+ return -EINVAL;
+
+ driver->driver.bus = &pci_epf_bus_type;
+ driver->driver.owner = owner;
+
+ ret = driver_register(&driver->driver);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(__pci_epf_register_driver);
+
+/**
+ * pci_epf_destroy() - destroy the created PCI EPF device
+ * @epf: the PCI EPF device that has to be destroyed.
+ *
+ * Invoke to destroy the PCI EPF device created by invoking pci_epf_create().
+ */
+void pci_epf_destroy(struct pci_epf *epf)
+{
+ device_unregister(&epf->dev);
+}
+EXPORT_SYMBOL_GPL(pci_epf_destroy);
+
+/**
+ * pci_epf_create() - create a new PCI EPF device
+ * @name: the name of the PCI EPF device. This name will be used to bind the
+ * the EPF device to a EPF driver
+ *
+ * Invoke to create a new PCI EPF device by providing the name of the function
+ * device.
+ */
+struct pci_epf *pci_epf_create(const char *name)
+{
+ int ret;
+ struct pci_epf *epf;
+ struct device *dev;
+ char *func_name;
+ char *buf;
+
+ epf = kzalloc(sizeof(*epf), GFP_KERNEL);
+ if (!epf) {
+ ret = -ENOMEM;
+ goto err_ret;
+ }
+
+ buf = kstrdup(name, GFP_KERNEL);
+ if (!buf) {
+ ret = -ENOMEM;
+ goto free_epf;
+ }
+
+ func_name = buf;
+ buf = strchrnul(buf, '.');
+ *buf = '\0';
+
+ epf->name = kstrdup(func_name, GFP_KERNEL);
+ if (!epf->name) {
+ ret = -ENOMEM;
+ goto free_epf;
+ }
+
+ dev = &epf->dev;
+ device_initialize(dev);
+ dev->bus = &pci_epf_bus_type;
+ dev->type = &pci_epf_type;
+
+ ret = dev_set_name(dev, "%s", name);
+ if (ret)
+ goto put_dev;
+
+ ret = device_add(dev);
+ if (ret)
+ goto put_dev;
+
+ kfree(func_name);
+ return epf;
+
+put_dev:
+ put_device(dev);
+ kfree(epf->name);
+ kfree(func_name);
+
+free_epf:
+ kfree(epf);
+
+err_ret:
+ return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(pci_epf_create);
+
+static void pci_epf_dev_release(struct device *dev)
+{
+ struct pci_epf *epf = to_pci_epf(dev);
+
+ kfree(epf->name);
+ kfree(epf);
+}
+
+static struct device_type pci_epf_type = {
+ .release = pci_epf_dev_release,
+};
+
+static const struct pci_epf_device_id *
+pci_epf_match_id(const struct pci_epf_device_id *id, const struct pci_epf *epf)
+{
+ while (id->name[0]) {
+ if (strcmp(epf->name, id->name) == 0)
+ return id;
+ id++;
+ }
+
+ return NULL;
+}
+
+static int pci_epf_device_match(struct device *dev, struct device_driver *drv)
+{
+ struct pci_epf *epf = to_pci_epf(dev);
+ struct pci_epf_driver *driver = to_pci_epf_driver(drv);
+
+ if (driver->id_table)
+ return pci_epf_match_id(driver->id_table, epf) != NULL;
+
+ return !strcmp(epf->name, drv->name);
+}
+
+static int pci_epf_device_probe(struct device *dev)
+{
+ struct pci_epf *epf = to_pci_epf(dev);
+ struct pci_epf_driver *driver = to_pci_epf_driver(dev->driver);
+
+ if (!driver->probe)
+ return -ENODEV;
+
+ epf->driver = driver;
+
+ return driver->probe(epf);
+}
+
+static int pci_epf_device_remove(struct device *dev)
+{
+ int ret;
+ struct pci_epf *epf = to_pci_epf(dev);
+ struct pci_epf_driver *driver = to_pci_epf_driver(dev->driver);
+
+ ret = driver->remove(epf);
+ epf->driver = NULL;
+
+ return ret;
+}
+
+static struct bus_type pci_epf_bus_type = {
+ .name = "pci-epf",
+ .match = pci_epf_device_match,
+ .probe = pci_epf_device_probe,
+ .remove = pci_epf_device_remove,
+};
+
+static int __init pci_epf_init(void)
+{
+ int ret;
+
+ ret = bus_register(&pci_epf_bus_type);
+ if (ret) {
+ pr_err("failed to register pci epf bus --> %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+module_init(pci_epf_init);
+
+static void __exit pci_epf_exit(void)
+{
+ bus_unregister(&pci_epf_bus_type);
+}
+module_exit(pci_epf_exit);
+
+MODULE_DESCRIPTION("PCI EPF Library");
+MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index ed84c07..946cef1 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -427,6 +427,16 @@ struct i2c_device_id {
kernel_ulong_t driver_data; /* Data private to the driver */
};
+/* pci_epf */
+
+#define PCI_EPF_NAME_SIZE 20
+#define PCI_EPF_MODULE_PREFIX "pci_epf:"
+
+struct pci_epf_device_id {
+ char name[PCI_EPF_NAME_SIZE];
+ kernel_ulong_t driver_data;
+};
+
/* spi */
#define SPI_NAME_SIZE 32
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
new file mode 100644
index 0000000..78e4178
--- /dev/null
+++ b/include/linux/pci-epc.h
@@ -0,0 +1,100 @@
+/**
+ * pci-epc.h - PCI Endpoint *Controller* (EPC) header file
+ *
+ * Copyright (C) 2016 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ */
+
+#ifndef __DRIVERS_PCI_EPC_H
+#define __DRIVERS_PCI_EPC_H
+
+#include <linux/pci-epf.h>
+
+struct pci_epc;
+
+enum pci_epc_irq_type {
+ PCI_EPC_IRQ_UNKNOWN,
+ PCI_EPC_IRQ_LEGACY,
+ PCI_EPC_IRQ_MSI,
+};
+
+/**
+ * struct pci_epc_ops - set of function pointers for performing EPC operations
+ * @write_header: ops to populate configuration space header
+ * @set_bar: ops to configure the BAR
+ * @clear_bar: ops to reset the BAR
+ * @alloc_addr_space: ops to allocate *in* PCI controller address space
+ * @free_addr_space: ops to free the allocated address space
+ * @raise_irq: ops to raise a legacy or MSI interrupt
+ * @start: ops to start the PCI link
+ * @stop: ops to stop the PCI link
+ * @owner: the module owner containing the ops
+ */
+struct pci_epc_ops {
+ int (*write_header)(struct pci_epc *pci_epc,
+ struct pci_epf_header *hdr);
+ int (*set_bar)(struct pci_epc *epc, enum pci_barno bar,
+ dma_addr_t bar_phys, size_t size, int flags);
+ void (*clear_bar)(struct pci_epc *epc, enum pci_barno bar);
+ void *(*alloc_addr_space)(struct pci_epc *pci_epc, size_t size);
+ void (*free_addr_space)(struct pci_epc *pci_epc);
+ int (*raise_irq)(struct pci_epc *pci_epc,
+ enum pci_epc_irq_type type);
+ int (*start)(struct pci_epc *epc);
+ void (*stop)(struct pci_epc *epc);
+ struct module *owner;
+};
+
+/**
+ * struct pci_epc - represents the PCI EPC device
+ * @dev: PCI EPC device
+ * @ops: function pointers for performing endpoint operations
+ * @mutex: mutex to protect pci_epc ops
+ */
+struct pci_epc {
+ struct device dev;
+ /* support only single function PCI device for now */
+ struct pci_epf *epf;
+ const struct pci_epc_ops *ops;
+ spinlock_t irq_lock;
+};
+
+#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
+
+#define pci_epc_create(dev, ops) \
+ __pci_epc_create((dev), (ops), THIS_MODULE)
+#define devm_pci_epc_create(dev, ops) \
+ __devm_pci_epc_create((dev), (ops), THIS_MODULE)
+
+static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
+{
+ dev_set_drvdata(&epc->dev, data);
+}
+
+static inline void *epc_get_drvdata(struct pci_epc *epc)
+{
+ return dev_get_drvdata(&epc->dev);
+}
+
+struct pci_epc *
+__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
+ struct module *owner);
+struct pci_epc *
+__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
+ struct module *owner);
+void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
+void pci_epc_destroy(struct pci_epc *epc);
+int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *hdr);
+int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
+ dma_addr_t bar_phys, size_t size, int flags);
+void pci_epc_clear_bar(struct pci_epc *epc, int bar);
+int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type);
+int pci_epc_start(struct pci_epc *epc);
+void pci_epc_stop(struct pci_epc *epc);
+int pci_epc_bind_epf(struct pci_epf *epf);
+void pci_epc_unbind_epf(struct pci_epf *epf);
+#endif /* __DRIVERS_PCI_EPC_H */
diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
new file mode 100644
index 0000000..337e474
--- /dev/null
+++ b/include/linux/pci-epf.h
@@ -0,0 +1,159 @@
+/**
+ * pci-epf.h - PCI Endpoint *Function* (EPF) header file
+ *
+ * Copyright (C) 2016 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ */
+
+#ifndef __DRIVERS_PCI_EPF_H
+#define __DRIVERS_PCI_EPF_H
+
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+
+struct pci_epf;
+
+enum pci_interrupt_pin {
+ PCI_INTERRUPT_UNKNOWN,
+ PCI_INTERRUPT_INTA,
+ PCI_INTERRUPT_INTB,
+ PCI_INTERRUPT_INTC,
+ PCI_INTERRUPT_INTD,
+};
+
+enum pci_barno {
+ BAR_0,
+ BAR_1,
+ BAR_2,
+ BAR_3,
+ BAR_4,
+ BAR_5,
+};
+
+/**
+ * struct pci_epf_header - represents standard configuration header
+ * @vendorid: identifies device manufacturer
+ * @deviceid: identifies a particular device
+ * @revid: specifies a device specific revision identifier
+ * @progif_code: identifies a specific register-level programming interface
+ * @subclass_code: identifies more specifically the function of the device
+ * @baseclass_code: broadly classifies the type of function the device performs
+ * @cache_line_size: specifies the system cacheline size in units of DWORDs
+ * @subsys_vendor_id: vendor of the add-in card or subsystem
+ * @subsys_id: id specific to vendor
+ * @interrupt_pin: interrupt pin the device (or device function) uses
+ */
+struct pci_epf_header {
+ u16 vendorid;
+ u16 deviceid;
+ u8 revid;
+ u8 progif_code;
+ u8 subclass_code;
+ u8 baseclass_code;
+ u8 cache_line_size;
+ u16 subsys_vendor_id;
+ u16 subsys_id;
+ enum pci_interrupt_pin interrupt_pin;
+};
+
+/**
+ * struct pci_epf_ops - set of function pointers for performing EPF operations
+ * @bind: ops to perform when a EPC device has been bound to EPF device
+ * @unbind: ops to perform when a binding has been lost between a EPC device
+ * and EPF device
+ * @linkup: ops to perform when the EPC device has established a connection with
+ * a host system
+ */
+struct pci_epf_ops {
+ int (*bind)(struct pci_epf *epf);
+ void (*unbind)(struct pci_epf *epf);
+ void (*linkup)(struct pci_epf *epf);
+};
+
+/**
+ * struct pci_epf_driver - represents the PCI EPF driver
+ * @probe: ops to perform when a new EPF device has been bound to the EPF driver
+ * @remove: ops to perform when the binding between the EPF device and EPF
+ * driver is broken
+ * @driver: PCI EPF driver
+ * @ops: set of function pointers for performing EPF operations
+ * @owner: the owner of the module that registers the PCI EPF driver
+ * @id_table: identifies EPF devices for probing
+ */
+struct pci_epf_driver {
+ int (*probe)(struct pci_epf *epf);
+ int (*remove)(struct pci_epf *epf);
+
+ struct device_driver driver;
+ struct pci_epf_ops *ops;
+ struct module *owner;
+ const struct pci_epf_device_id *id_table;
+};
+
+#define to_pci_epf_driver(drv) (container_of((drv), struct pci_epf_driver, \
+ driver))
+
+/**
+ * struct pci_epf_bar - represents the BAR of EPF device
+ * @phys_addr: physical address that should be mapped to the BAR
+ * @size: the size of the address space present in BAR
+ */
+struct pci_epf_bar {
+ dma_addr_t phys_addr;
+ size_t size;
+};
+
+/**
+ * struct pci_epf - represents the PCI EPF device
+ * @dev: the PCI EPF device
+ * @name: the name of the PCI EPF device
+ * @header: represents standard configuration header
+ * @bar: represents the BAR of EPF device
+ * @epc: the EPC device to which this EPF device is bound
+ * @driver: the EPF driver to which this EPF device is bound
+ * @pci_epc_name: the name of the EPC device to which this EPF device is bound
+ * @hw_devname: the name of the peripheral device associated with this EPF
+ * device
+ */
+struct pci_epf {
+ struct device dev;
+ const char *name;
+ struct pci_epf_header *header;
+ struct pci_epf_bar bar[6];
+
+ struct pci_epc *epc;
+ struct pci_epf_driver *driver;
+ const char *pci_epc_name;
+ const char *hw_devname;
+};
+
+#define to_pci_epf(dev) container_of((dev), struct pci_epf, dev)
+
+#define pci_epf_register_driver(driver) \
+ __pci_epf_register_driver((driver), THIS_MODULE)
+
+static inline void epf_set_drvdata(struct pci_epf *epf, void *data)
+{
+ dev_set_drvdata(&epf->dev, data);
+}
+
+static inline void *epf_get_drvdata(struct pci_epf *epf)
+{
+ return dev_get_drvdata(&epf->dev);
+}
+
+struct pci_epf *pci_epf_create(const char *name);
+void pci_epf_destroy(struct pci_epf *epf);
+int __pci_epf_register_driver(struct pci_epf_driver *driver,
+ struct module *owner);
+void pci_epf_unregister_driver(struct pci_epf_driver *driver);
+void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar);
+void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar);
+int pci_epf_bind(struct pci_epf *epf);
+void pci_epf_unbind(struct pci_epf *epf);
+void pci_epf_linkup(struct pci_epf *epf);
+#endif /* __DRIVERS_PCI_EPF_H */
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH] pci: endpoint: introduce configfs entry for configuring EP functions
From: Kishon Vijay Abraham I @ 2016-09-13 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473786653-12759-1-git-send-email-kishon@ti.com>
Introduce a new configfs entry to configure the EP function (like
configuring the standard configuration header entries) and to
bind the function with a controller.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/endpoint/Kconfig | 4 +-
drivers/pci/endpoint/Makefile | 3 +-
drivers/pci/endpoint/pci-ep-cfs.c | 275 +++++++++++++++++++++++++++++++++++++
3 files changed, 280 insertions(+), 2 deletions(-)
create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c
diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
index a6d827c..f1dd206 100644
--- a/drivers/pci/endpoint/Kconfig
+++ b/drivers/pci/endpoint/Kconfig
@@ -13,7 +13,9 @@ config PCI_ENDPOINT
Enabling this option will build the endpoint library, which
includes endpoint controller library and endpoint function
- library.
+ library. This will also enable the configfs entry required to
+ configure the endpoint function and used to bind the
+ function with a endpoint controller.
If in doubt, say "N" to disable Endpoint support.
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
index dbc5517..67c88bf 100644
--- a/drivers/pci/endpoint/Makefile
+++ b/drivers/pci/endpoint/Makefile
@@ -2,4 +2,5 @@
# Makefile for PCI Endpoint Support
#
-obj-$(CONFIG_PCI_ENDPOINT) := pci-epc-core.o pci-epf-core.o
+obj-$(CONFIG_PCI_ENDPOINT) := pci-epc-core.o pci-epf-core.o \
+ pci-ep-cfs.o
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c
new file mode 100644
index 0000000..d11ae34
--- /dev/null
+++ b/drivers/pci/endpoint/pci-ep-cfs.c
@@ -0,0 +1,275 @@
+/**
+ * pci-ep-cfs.c - configfs to configure the PCI endpoint
+ *
+ * Copyright (C) 2016 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/configfs.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+
+struct pci_epf_info {
+ struct config_item pci_epf;
+ struct pci_epf *epf;
+};
+
+static inline struct pci_epf_info *to_pci_epf_info(struct config_item *item)
+{
+ return container_of(item, struct pci_epf_info, pci_epf);
+}
+
+#define PCI_EPF_HEADER_R(_name) \
+static ssize_t pci_epf_##_name##_show(struct config_item *item, \
+ char *page) \
+{ \
+ return sprintf(page, "0x%04x\n", \
+ to_pci_epf_info(item)->epf->header->_name); \
+}
+
+#define PCI_EPF_HEADER_W_u32(_name) \
+static ssize_t pci_epf_##_name##_store(struct config_item *item, \
+ const char *page, size_t len) \
+{ \
+ u32 val; \
+ int ret; \
+ ret = kstrtou32(page, 0, &val); \
+ if (ret) \
+ return ret; \
+ to_pci_epf_info(item)->epf->header->_name = val; \
+ return len; \
+}
+
+#define PCI_EPF_HEADER_W_u16(_name) \
+static ssize_t pci_epf_##_name##_store(struct config_item *item, \
+ const char *page, size_t len) \
+{ \
+ u16 val; \
+ int ret; \
+ ret = kstrtou16(page, 0, &val); \
+ if (ret) \
+ return ret; \
+ to_pci_epf_info(item)->epf->header->_name = val; \
+ return len; \
+}
+
+#define PCI_EPF_HEADER_W_u8(_name) \
+static ssize_t pci_epf_##_name##_store(struct config_item *item, \
+ const char *page, size_t len) \
+{ \
+ u8 val; \
+ int ret; \
+ ret = kstrtou8(page, 0, &val); \
+ if (ret) \
+ return ret; \
+ to_pci_epf_info(item)->epf->header->_name = val; \
+ return len; \
+}
+
+#define PCI_EPF_HEADER_RW(_name, _type) \
+ PCI_EPF_HEADER_R(_name) \
+ PCI_EPF_HEADER_W_##_type(_name)
+
+static ssize_t pci_epf_peripheral_store(struct config_item *item,
+ const char *page, size_t len)
+{
+ struct pci_epf_info *epf_info = to_pci_epf_info(item);
+ char *dev_name;
+
+ dev_name = kstrdup(page, GFP_KERNEL);
+ if (!dev_name)
+ return -ENOMEM;
+ if (dev_name[len - 1] == '\n')
+ dev_name[len - 1] = '\0';
+
+ epf_info->epf->hw_devname = dev_name;
+ return len;
+}
+
+static ssize_t pci_epf_peripheral_show(struct config_item *item,
+ char *page)
+{
+ return sprintf(page, "%s\n",
+ to_pci_epf_info(item)->epf->hw_devname);
+}
+
+static ssize_t pci_epf_function_show(struct config_item *item,
+ char *page)
+{
+ return sprintf(page, "%s\n",
+ to_pci_epf_info(item)->epf->name);
+}
+
+static ssize_t pci_epf_epc_store(struct config_item *item,
+ const char *page, size_t len)
+{
+ int ret;
+ struct pci_epf_info *epf_info = to_pci_epf_info(item);
+ char *epc_name;
+
+ epc_name = kstrdup(page, GFP_KERNEL);
+ if (!epc_name)
+ return -ENOMEM;
+ if (epc_name[len - 1] == '\n')
+ epc_name[len - 1] = '\0';
+
+ if (epf_info->epf->epc)
+ pci_epc_unbind_epf(epf_info->epf);
+
+ epf_info->epf->pci_epc_name = epc_name;
+ ret = pci_epc_bind_epf(epf_info->epf);
+ if (ret)
+ return -EINVAL;
+
+ return len;
+}
+
+static ssize_t pci_epf_epc_show(struct config_item *item,
+ char *page)
+{
+ return sprintf(page, "%s\n",
+ to_pci_epf_info(item)->epf->pci_epc_name);
+}
+
+PCI_EPF_HEADER_RW(vendorid, u16);
+PCI_EPF_HEADER_RW(deviceid, u16);
+PCI_EPF_HEADER_RW(revid, u16);
+PCI_EPF_HEADER_RW(progif_code, u16);
+PCI_EPF_HEADER_RW(subclass_code, u16);
+PCI_EPF_HEADER_RW(baseclass_code, u16);
+PCI_EPF_HEADER_RW(cache_line_size, u16);
+PCI_EPF_HEADER_RW(subsys_vendor_id, u16);
+PCI_EPF_HEADER_RW(subsys_id, u16);
+PCI_EPF_HEADER_RW(interrupt_pin, u16);
+
+CONFIGFS_ATTR(pci_epf_, vendorid);
+CONFIGFS_ATTR(pci_epf_, deviceid);
+CONFIGFS_ATTR(pci_epf_, revid);
+CONFIGFS_ATTR(pci_epf_, progif_code);
+CONFIGFS_ATTR(pci_epf_, subclass_code);
+CONFIGFS_ATTR(pci_epf_, baseclass_code);
+CONFIGFS_ATTR(pci_epf_, cache_line_size);
+CONFIGFS_ATTR(pci_epf_, subsys_vendor_id);
+CONFIGFS_ATTR(pci_epf_, subsys_id);
+CONFIGFS_ATTR(pci_epf_, interrupt_pin);
+CONFIGFS_ATTR(pci_epf_, peripheral);
+CONFIGFS_ATTR_RO(pci_epf_, function);
+CONFIGFS_ATTR(pci_epf_, epc);
+
+static struct configfs_attribute *pci_epf_attrs[] = {
+ &pci_epf_attr_vendorid,
+ &pci_epf_attr_deviceid,
+ &pci_epf_attr_revid,
+ &pci_epf_attr_progif_code,
+ &pci_epf_attr_subclass_code,
+ &pci_epf_attr_baseclass_code,
+ &pci_epf_attr_cache_line_size,
+ &pci_epf_attr_subsys_vendor_id,
+ &pci_epf_attr_subsys_id,
+ &pci_epf_attr_interrupt_pin,
+ &pci_epf_attr_peripheral,
+ &pci_epf_attr_function,
+ &pci_epf_attr_epc,
+ NULL,
+};
+
+static void pci_epf_release(struct config_item *item)
+{
+ struct pci_epf_info *epf_info = to_pci_epf_info(item);
+
+ pci_epf_destroy(epf_info->epf);
+ kfree(epf_info);
+}
+
+static struct configfs_item_operations pci_epf_ops = {
+ .release = pci_epf_release,
+};
+
+static struct config_item_type pci_epf_type = {
+ .ct_item_ops = &pci_epf_ops,
+ .ct_attrs = pci_epf_attrs,
+ .ct_owner = THIS_MODULE,
+};
+
+static struct config_item *pci_epf_make(struct config_group *group,
+ const char *name)
+{
+ struct pci_epf_info *epf_info;
+ struct pci_epf *epf;
+
+ epf_info = kzalloc(sizeof(*epf_info), GFP_KERNEL);
+ if (!epf_info)
+ return ERR_PTR(-ENOMEM);
+
+ epf = pci_epf_create(name);
+ if (IS_ERR(epf)) {
+ pr_err("failed to create endpoint function device\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ epf_info->epf = epf;
+
+ config_item_init_type_name(&epf_info->pci_epf, name,
+ &pci_epf_type);
+
+ return &epf_info->pci_epf;
+}
+
+static struct configfs_group_operations pci_ep_ops = {
+ .make_item = pci_epf_make,
+};
+
+static struct config_item_type pci_ep_type = {
+ .ct_group_ops = &pci_ep_ops,
+ .ct_owner = THIS_MODULE,
+};
+
+static struct configfs_subsystem pci_ep_cfs_subsys = {
+ .su_group = {
+ .cg_item = {
+ .ci_namebuf = "pci_ep",
+ .ci_type = &pci_ep_type,
+ },
+ },
+ .su_mutex = __MUTEX_INITIALIZER(pci_ep_cfs_subsys.su_mutex),
+};
+
+static int __init pci_ep_cfs_init(void)
+{
+ int ret;
+
+ config_group_init(&pci_ep_cfs_subsys.su_group);
+
+ ret = configfs_register_subsystem(&pci_ep_cfs_subsys);
+ if (ret)
+ pr_err("Error %d while registering subsystem %s\n",
+ ret, pci_ep_cfs_subsys.su_group.cg_item.ci_namebuf);
+
+ return ret;
+}
+module_init(pci_ep_cfs_init);
+
+static void __exit pci_ep_cfs_exit(void)
+{
+ configfs_unregister_subsystem(&pci_ep_cfs_subsys);
+}
+module_exit(pci_ep_cfs_exit);
+
+MODULE_DESCRIPTION("PCI EP CONFIGFS");
+MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH] Documentation: PCI: guide to use PCI Endpoint Core Layer
From: Kishon Vijay Abraham I @ 2016-09-13 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473786653-12759-1-git-send-email-kishon@ti.com>
Add Documentation to let users enable endpoint mode in the PCI
controller and add new PCI endpoint function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/PCI/00-INDEX | 2 +
Documentation/PCI/pci-endpoint.txt | 199 ++++++++++++++++++++++++++++++++++++
2 files changed, 201 insertions(+)
create mode 100644 Documentation/PCI/pci-endpoint.txt
diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index 147231f..e422b8151 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -12,3 +12,5 @@ pci.txt
- info on the PCI subsystem for device driver authors
pcieaer-howto.txt
- the PCI Express Advanced Error Reporting Driver Guide HOWTO
+pci-endpoint.txt
+ - guide to add endpoint controller driver and endpoint function driver.
diff --git a/Documentation/PCI/pci-endpoint.txt b/Documentation/PCI/pci-endpoint.txt
new file mode 100644
index 0000000..a453aaa
--- /dev/null
+++ b/Documentation/PCI/pci-endpoint.txt
@@ -0,0 +1,199 @@
+ PCI ENDPOINT FRAMEWORK
+ Kishon Vijay Abraham I <kishon@ti.com>
+
+This document is a guide to use the PCI Endpoint Framework in order to create
+endpoint controller driver, endpoint function driver and using configfs
+interface to bind the function driver to the controller driver.
+
+1. Introduction
+
+*Linux* has a comprehensive PCI subsystem to support PCI controllers that
+operates in Root Complex mode. The subsystem has capability to scan PCI bus,
+assign memory resources and irq resources, load PCI driver (based on
+vendorid, deviceid), support other services like hot-plug, power management,
+advanced error reporting and virtual channels.
+
+However PCI controller IPs integrated in certain SoC is capable of operating
+either in Root Complex mode or Endpoint mode. PCI Endpoint Framework will
+add endpoint mode support in *Linux*. This will help to run Linux in an
+EP system which can have a wide variety of use cases from testing or
+validation, co-processor accelerator etc..
+
+2. PCI Endpoint Core
+
+The PCI Endpoint Core layer comprises of 3 components: the Endpoint Controller
+library, the Endpoint Function library and the configfs layer to bind the
+endpoint function with the endpoint controller.
+
+2.1 PCI Endpoint Controller(EPC) Library
+
+The EPC library provides APIs to be used by the controller that can operate
+in endpoint mode. It also provides APIs to be used by function driver/library
+in order to implement a particular endpoint function.
+
+2.1.1 APIs for the PCI controller Driver
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI controller driver.
+
+*) devm_pci_epc_create()/pci_epc_create()
+
+ The PCI controller driver should implement the following ops:
+ * write_header: ops to populate configuration space header
+ * set_bar: ops to configure the BAR
+ * clear_bar: ops to reset the BAR
+ * alloc_addr_space: ops to allocate *in* PCI controller address space
+ * free_addr_space: ops to free the allocated address space
+ * raise_irq: ops to raise a legacy or MSI interrupt
+ * start: ops to start the PCI link
+ * stop: ops to stop the PCI link
+
+ The PCI controller driver can then create a new EPC device by invoking
+ devm_pci_epc_create/pci_epc_create.
+
+*) devm_pci_epc_destroy()/pci_epc_destroy()
+
+ The PCI controller driver can destroy the EPC device created by either
+ devm_pci_epc_create or pci_epc_create using devm_pci_epc_destroy() or
+ /pci_epc_destroy()
+
+2.1.2 APIs for the PCI Endpoint Function Driver
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI endpoint function driver.
+
+*) pci_epc_write_header()
+
+ The PCI endpoint function driver should use pci_epc_write_header() to
+ write the standard configuration header to the endpoint controller.
+
+*) pci_epc_set_bar()
+
+ The PCI endpoint function driver should use pci_epc_set_bar() to configure
+ the Base Address Register in order for the host to assign PCI addr space.
+ Register space of the function driver is usually configured
+ using this API.
+
+*) pci_epc_clear_bar()
+
+ The PCI endpoint function driver should use pci_epc_clear_bar() to reset
+ the BAR.
+
+*) pci_epc_raise_irq()
+
+ The PCI endpoint function driver should use pci_epc_raise_irq() to raise
+ Legacy Interrupt or MSI Interrupt.
+
+*) pci_epc_start()
+
+ The PCI endpoint function driver should invoke pci_epc_start() once it
+ has configured the endpoint function and wants to start the PCI link.
+
+*) pci_epc_stop()
+
+ The PCI endpoint function driver should invoke pci_epc_stop() to stop
+ the PCI LINK.
+
+2.1.3 APIs for the PCI Endpoint Function Library
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI endpoint function library.
+
+*) pci_epc_bind_epf()
+
+ The PCI endpoint function library uses pci_epc_bind_epf() to bind the
+ function driver with a controller driver. The binding will be based on
+ the endpoint controller function name (as seen in /sys/class/pci_epc/).
+
+*) pci_epc_unbind_epf()
+
+ The PCI endpoint function library uses pci_epc_unbind_epf() to unbind
+ the function driver from the controller driver. After unbind the controller
+ driver can be bound to any other function driver.
+
+2.2 PCI Endpoint Function(EPF) Library
+
+The EPF library provides APIs to be used by the function driver and the EPC
+library in order to provide endpoint mode functionality.
+
+2.2.1 APIs for the PCI Endpoint Function Driver
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI endpoint function driver.
+
+*) pci_epf_register_driver()
+
+ The PCI Endpoint Function driver should implement the following ops:
+ * bind: ops to perform when a EPC device has been bound to EPF device
+ * unbind: ops to perform when a binding has been lost between a EPC
+ device and EPF device
+ * linkup: ops to perform when the EPC device has established a
+ connection with a host system
+
+ The PCI Function driver can then register the PCI EPF driver by using
+ pci_epf_register_driver().
+
+*) pci_epf_unregister_driver()
+
+ The PCI Function driver can unregister the PCI EPF driver by using
+ pci_epf_unregister_driver().
+
+*) pci_epf_alloc_space()
+
+ The PCI Function driver can allocate space for a particular BAR using
+ pci_epf_alloc_space().
+
+*) pci_epf_free_space()
+
+ The PCI Function driver can free the allocated space
+ (using pci_epf_alloc_space) by invoking pci_epf_free_space().
+
+2.2.2 APIs for the PCI Endpoint Controller Library
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI endpoint controller library.
+
+*) pci_epf_bind()
+
+ The PCI endpoint controller library invokes pci_epf_bind() when the EPF
+ device has been bound to a EPC device.
+
+*) pci_epf_unbind()
+
+ The PCI endpoint controller library invokes pci_epf_unbind() when the
+ binding between EPC device and EPF device is lost.
+
+*) pci_epf_linkup()
+
+ The PCI endpoint controller library invokes pci_epf_linkup() when the
+ EPC device has established the connection to the host.
+
+2.3 CONFIGFS
+
+The PCI Endpoint Core exposes configfs entry (pci_ep) in order to configure the
+PCI Endpoint Function and in order to bind the endpoint function
+with the endpoint controller. Every folder in pci_ep/ represent a PCI
+endpoint function.
+
+The following entries can be used to configure the standard configuration
+header of the endpoint function.
+ vendorid
+ deviceid
+ revid
+ progif_code
+ subclass_code
+ baseclass_code
+ cache_line_size
+ subsys_vendor_id
+ subsys_id
+ interrupt_pin
+
+The following entries has special meaning:
+ function: this readonly entry shows the name using which the function
+ driver will be bound to this function
+ epc : the name of the EPC device this function should be bound to.
+ The name of the EPC device should be from /sys/class/pci_epc.
+
+3. Known Limitations
+
+The Endpoint Core doesn't support adding multi-function devices.
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH] pci: endpoint: functions: add an EP function to test PCI
From: Kishon Vijay Abraham I @ 2016-09-13 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473786653-12759-1-git-send-email-kishon@ti.com>
This adds a new endpoint function driver (to program the virtual
test device) making use of the EP-core library. The complete
usage of the test function is described in
Documentation/PCI/pci-test.txt (included in this commit).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/PCI/00-INDEX | 3 +
Documentation/PCI/pci-test.txt | 79 +++++++
drivers/pci/endpoint/Kconfig | 2 +
drivers/pci/endpoint/Makefile | 2 +-
drivers/pci/endpoint/functions/Kconfig | 12 ++
drivers/pci/endpoint/functions/Makefile | 5 +
drivers/pci/endpoint/functions/pci-epf-test.c | 272 +++++++++++++++++++++++++
7 files changed, 374 insertions(+), 1 deletion(-)
create mode 100644 Documentation/PCI/pci-test.txt
create mode 100644 drivers/pci/endpoint/functions/Kconfig
create mode 100644 drivers/pci/endpoint/functions/Makefile
create mode 100644 drivers/pci/endpoint/functions/pci-epf-test.c
diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index e422b8151..e5a583c 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -14,3 +14,6 @@ pcieaer-howto.txt
- the PCI Express Advanced Error Reporting Driver Guide HOWTO
pci-endpoint.txt
- guide to add endpoint controller driver and endpoint function driver.
+pci-test.txt
+ - description of the PCI EP function that can be used to test PCI
+ functionality
diff --git a/Documentation/PCI/pci-test.txt b/Documentation/PCI/pci-test.txt
new file mode 100644
index 0000000..2bc796b
--- /dev/null
+++ b/Documentation/PCI/pci-test.txt
@@ -0,0 +1,79 @@
+ PCI TEST
+ Kishon Vijay Abraham I <kishon@ti.com>
+
+Traditionally PCI RC has always been validated by using standard
+PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
+However with the addition of EP-core in linux kernel, it is possible
+to configure a PCI controller that can operate in EP mode to work as
+a test device.
+
+The PCI endpoint test device is a completely software device used to
+test the endpoint functionality and serve as a sample driver for other
+PCI endpoint devices.
+
+The PCI endpoint test device has four registers:
+
+ 1) PCI_ENDPOINT_TEST_COMMAND
+ 2) PCI_ENDPOINT_TEST_STATUS
+ 3) PCI_ENDPOINT_TEST_SRC_ADDR
+ 4) PCI_ENDPOINT_TEST_DST_ADDR
+
+Since this is a virtual device, all these registers will be present
+in RAM and will be allocated using one of the standard memory allocation
+API (in this case dma_alloc_coherent)
+
+*) PCI_ENDPOINT_TEST_COMMAND:
+
+This register will be used by the host driver to indicate the function
+that the endpoint device must perform.
+
+Bitfield Description:
+ Bit 0: reset the PCI endpoint device
+ Bit 1: raise irq
+ Bit 2: Copy the data from source addr to destination address
+
+*) PCI_ENDPOINT_TEST_STATUS
+
+This register reflects the status of the PCI endpoint device.
+
+Bitfield Description:
+ Bit 0: PCI endpoint device is in initialized state
+ Bit 1: Copy is in progress
+ Bit 2: Copy is done
+ Bit 3: IRQ is raised
+ Bit 4: Source address is invalid
+ Bit 5: Destination address is invalid
+
+*) PCI_ENDPOINT_TEST_SRC_ADDR
+
+This register contains the source address for the COPY command.
+
+*) PCI_ENDPOINT_TEST_DST_ADDR
+
+This register contains the destination address for the COPY command.
+
+PCI ENDPOINT TEST DRIVER (EP SIDE)
+==================================
+
+The Endpoint side function driver is present in
+drivers/pci/endpoint/functions/pci-epf-test.c
+
+This function driver creates the PCI endpoint test device and then
+waits for commands from the host driver. If the host driver sets
+Bit 1 (raise irq) in the COMMAND register, the endpoint driver
+will raise an irq. Similarly it resets the device if Bit 0 is set
+and starts copying the data if Bit 2 is set.
+
+The function driver is also responsible for updating the STATUS
+register.
+
+PCI ENDPOINT TEST DRIVER (HOST SIDE)
+====================================
+
+The host side PCI driver is present in
+drivers/misc/pci_endpoint_test.c
+
+The PCI driver for the test device performs 3 tests
+ *) Verifying addresses programmed in BAR
+ *) Raise legacy IRQ
+ *) Copy data from source address to destination address (TODO)
diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
index f1dd206..0e3dc8c 100644
--- a/drivers/pci/endpoint/Kconfig
+++ b/drivers/pci/endpoint/Kconfig
@@ -19,5 +19,7 @@ config PCI_ENDPOINT
If in doubt, say "N" to disable Endpoint support.
+source "drivers/pci/endpoint/functions/Kconfig"
+
endmenu
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
index 67c88bf..89310d1 100644
--- a/drivers/pci/endpoint/Makefile
+++ b/drivers/pci/endpoint/Makefile
@@ -3,4 +3,4 @@
#
obj-$(CONFIG_PCI_ENDPOINT) := pci-epc-core.o pci-epf-core.o \
- pci-ep-cfs.o
+ pci-ep-cfs.o functions/
diff --git a/drivers/pci/endpoint/functions/Kconfig b/drivers/pci/endpoint/functions/Kconfig
new file mode 100644
index 0000000..175edad
--- /dev/null
+++ b/drivers/pci/endpoint/functions/Kconfig
@@ -0,0 +1,12 @@
+#
+# PCI Endpoint Functions
+#
+
+config PCI_EPF_TEST
+ tristate "PCI Endpoint Test driver"
+ depends on PCI_ENDPOINT
+ help
+ Enable this configuration option to enable the test driver
+ for PCI Endpoint.
+
+ If in doubt, say "N" to disable Endpoint test driver.
diff --git a/drivers/pci/endpoint/functions/Makefile b/drivers/pci/endpoint/functions/Makefile
new file mode 100644
index 0000000..53c120e
--- /dev/null
+++ b/drivers/pci/endpoint/functions/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for PCI Endpoint Functions
+#
+
+obj-$(CONFIG_PCI_EPF_TEST) := pci-epf-test.o
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
new file mode 100644
index 0000000..a7585b1
--- /dev/null
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -0,0 +1,272 @@
+/**
+ * pci-epf-test.c - Test driver to test endpoint functionality
+ *
+ * Copyright (C) 2016 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/pci_ids.h>
+
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+#include <linux/pci_regs.h>
+
+#define COMMAND_RESET BIT(0)
+#define COMMAND_RAISE_IRQ BIT(1)
+#define COMMAND_COPY BIT(2)
+
+#define STATUS_INITIALIZED BIT(0)
+#define STATUS_COPY_PROGRESS BIT(1)
+#define STATUS_COPY_DONE BIT(2)
+#define STATUS_IRQ_RAISED BIT(3)
+#define STATUS_SOURCE_ADDR_INVALID BIT(4)
+#define STATUS_DEST_ADDR_INVALID BIT(5)
+
+#define TIMER_RESOLUTION 5
+
+struct pci_epf_test {
+ struct timer_list timer;
+ void *reg[6];
+ struct pci_epf *epf;
+};
+
+struct pci_epf_test_reg {
+ u32 command;
+ u32 status;
+ u64 src_addr;
+ u64 dst_addr;
+};
+
+struct pci_epf_header test_header = {
+ .vendorid = PCI_ANY_ID,
+ .deviceid = PCI_ANY_ID,
+ .baseclass_code = PCI_CLASS_OTHERS,
+ .interrupt_pin = PCI_INTERRUPT_INTA,
+};
+
+static int bar_size[] = { 512, 1024, 16384, 131072, 1048576};
+
+static void pci_epf_test_cmd_handler(unsigned long data)
+{
+ struct pci_epf_test *epf_test = (struct pci_epf_test *)data;
+ struct pci_epf *epf = epf_test->epf;
+ struct pci_epc *epc = epf->epc;
+ struct pci_epf_test_reg *reg = epf_test->reg[0];
+ unsigned long timer;
+
+ if (!reg->command)
+ goto reset_handler;
+
+ if (reg->command & COMMAND_RESET)
+ reg->status = STATUS_INITIALIZED;
+
+ if (reg->command & COMMAND_RAISE_IRQ) {
+ reg->status |= STATUS_IRQ_RAISED;
+ pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY);
+ }
+
+ reg->command = 0;
+
+reset_handler:
+ timer = jiffies + msecs_to_jiffies(TIMER_RESOLUTION);
+ mod_timer(&epf_test->timer, timer);
+}
+
+static void pci_epf_test_linkup(struct pci_epf *epf)
+{
+ struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+ unsigned long timer;
+
+ setup_timer(&epf_test->timer, pci_epf_test_cmd_handler,
+ (unsigned long)epf_test);
+ timer = jiffies + msecs_to_jiffies(TIMER_RESOLUTION);
+ mod_timer(&epf_test->timer, timer);
+}
+
+static void pci_epf_test_unbind(struct pci_epf *epf)
+{
+ struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+ struct pci_epc *epc = epf->epc;
+ int bar;
+
+ del_timer(&epf_test->timer);
+ pci_epc_stop(epc);
+ for (bar = BAR_0; bar <= BAR_5; bar++) {
+ if (epf_test->reg[bar]) {
+ pci_epf_free_space(epf, epf_test->reg[bar], bar);
+ pci_epc_clear_bar(epc, bar);
+ }
+ }
+
+ epf->pci_epc_name = NULL;
+}
+
+static int pci_epf_test_set_bar(struct pci_epf *epf)
+{
+ int flags;
+ int bar;
+ int ret;
+ struct pci_epf_bar *epf_bar;
+ struct pci_epc *epc = epf->epc;
+ struct device *dev = &epf->dev;
+ struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+
+ flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32;
+ if (sizeof(dma_addr_t) == 0x8)
+ flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
+
+ for (bar = BAR_0; bar <= BAR_5; bar++) {
+ epf_bar = &epf->bar[bar];
+ ret = pci_epc_set_bar(epc, bar, epf_bar->phys_addr,
+ epf_bar->size, flags);
+ if (ret) {
+ pci_epf_free_space(epf, epf_test->reg[bar], bar);
+ dev_err(dev, "failed to set BAR%d\n", bar);
+ if (bar == BAR_0)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int pci_epf_test_alloc_space(struct pci_epf *epf)
+{
+ struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+ struct device *dev = &epf->dev;
+ void *base;
+ int bar;
+
+ base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg),
+ BAR_0);
+ if (!base) {
+ dev_err(dev, "failed to allocated register space\n");
+ return -ENOMEM;
+ }
+ epf_test->reg[0] = base;
+
+ for (bar = BAR_1; bar <= BAR_5; bar++) {
+ base = pci_epf_alloc_space(epf, bar_size[bar - 1], bar);
+ if (!base)
+ dev_err(dev, "failed to allocate space for BAR%d\n",
+ bar);
+ epf_test->reg[bar] = base;
+ }
+
+ return 0;
+}
+
+static int pci_epf_test_bind(struct pci_epf *epf)
+{
+ int ret;
+ struct pci_epf_header *header = epf->header;
+ struct pci_epc *epc = epf->epc;
+ struct device *dev = &epf->dev;
+
+ ret = pci_epc_write_header(epc, header);
+ if (ret) {
+ dev_err(dev, "configuration header write failed\n");
+ return ret;
+ }
+
+ ret = pci_epf_test_alloc_space(epf);
+ if (ret)
+ return ret;
+
+ ret = pci_epf_test_set_bar(epf);
+ if (ret)
+ return ret;
+
+ ret = pci_epc_start(epc);
+ if (ret) {
+ dev_err(dev, "failed to start endpoint controller\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int pci_epf_test_probe(struct pci_epf *epf)
+{
+ struct pci_epf_test *epf_test;
+ struct device *dev = &epf->dev;
+
+ epf_test = devm_kzalloc(dev, sizeof(*epf_test), GFP_KERNEL);
+ if (!epf)
+ return -ENOMEM;
+
+ epf->header = &test_header;
+ epf_test->epf = epf;
+
+ epf_set_drvdata(epf, epf_test);
+ return 0;
+}
+
+static int pci_epf_test_remove(struct pci_epf *epf)
+{
+ struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+
+ pci_epc_unbind_epf(epf_test->epf);
+ kfree(epf_test);
+ return 0;
+}
+
+struct pci_epf_ops ops = {
+ .unbind = pci_epf_test_unbind,
+ .bind = pci_epf_test_bind,
+ .linkup = pci_epf_test_linkup,
+};
+
+static const struct pci_epf_device_id pci_epf_test_ids[] = {
+ {
+ .name = "pci_epf_test",
+ },
+ {},
+};
+
+static struct pci_epf_driver test_driver = {
+ .driver.name = "pci_epf_test",
+ .probe = pci_epf_test_probe,
+ .remove = pci_epf_test_remove,
+ .id_table = pci_epf_test_ids,
+ .ops = &ops,
+ .owner = THIS_MODULE,
+};
+
+static int __init pci_epf_test_init(void)
+{
+ int ret;
+
+ ret = pci_epf_register_driver(&test_driver);
+ if (ret) {
+ pr_err("failed to register pci epf test driver --> %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+module_init(pci_epf_test_init);
+
+static void __exit pci_epf_test_exit(void)
+{
+ pci_epf_unregister_driver(&test_driver);
+}
+module_exit(pci_epf_test_exit);
+
+MODULE_DESCRIPTION("PCI EPF TEST DRIVER");
+MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH] pci: rename *host* directory to *controller*
From: Kishon Vijay Abraham I @ 2016-09-13 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473786653-12759-1-git-send-email-kishon@ti.com>
No functional change. Renamed the *host* directory present inside
drivers/pci to *controller*. Some of the controllers present in
drivers/pci/host is capable of operating in endpoint mode.
So having these drivers in *host* directory might not be appropriate.
This is in preparation for adding endpoint mode support for some of
controller drivers present here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
MAINTAINERS | 50 ++++++++++----------
drivers/Makefile | 3 ++
drivers/pci/Kconfig | 2 +-
drivers/pci/Makefile | 3 --
drivers/pci/{host => controller}/Kconfig | 35 +++++++++++++-
drivers/pci/{host => controller}/Makefile | 0
drivers/pci/{host => controller}/pci-aardvark.c | 0
drivers/pci/{host => controller}/pci-dra7xx.c | 0
drivers/pci/{host => controller}/pci-exynos.c | 0
drivers/pci/{host => controller}/pci-host-common.c | 0
.../pci/{host => controller}/pci-host-generic.c | 0
drivers/pci/{host => controller}/pci-hyperv.c | 0
drivers/pci/{host => controller}/pci-imx6.c | 0
drivers/pci/{host => controller}/pci-keystone-dw.c | 0
drivers/pci/{host => controller}/pci-keystone.c | 0
drivers/pci/{host => controller}/pci-keystone.h | 0
drivers/pci/{host => controller}/pci-layerscape.c | 0
drivers/pci/{host => controller}/pci-mvebu.c | 0
drivers/pci/{host => controller}/pci-rcar-gen2.c | 0
drivers/pci/{host => controller}/pci-tegra.c | 0
.../pci/{host => controller}/pci-thunder-ecam.c | 0
drivers/pci/{host => controller}/pci-thunder-pem.c | 0
drivers/pci/{host => controller}/pci-versatile.c | 0
drivers/pci/{host => controller}/pci-xgene-msi.c | 0
drivers/pci/{host => controller}/pci-xgene.c | 0
drivers/pci/{host => controller}/pcie-altera-msi.c | 0
drivers/pci/{host => controller}/pcie-altera.c | 0
drivers/pci/{host => controller}/pcie-armada8k.c | 0
drivers/pci/{host => controller}/pcie-artpec6.c | 0
.../{host => controller}/pcie-designware-plat.c | 0
drivers/pci/{host => controller}/pcie-designware.c | 0
drivers/pci/{host => controller}/pcie-designware.h | 0
drivers/pci/{host => controller}/pcie-hisi.c | 0
drivers/pci/{host => controller}/pcie-iproc-bcma.c | 0
drivers/pci/{host => controller}/pcie-iproc-msi.c | 0
.../pci/{host => controller}/pcie-iproc-platform.c | 0
drivers/pci/{host => controller}/pcie-iproc.c | 0
drivers/pci/{host => controller}/pcie-iproc.h | 0
drivers/pci/{host => controller}/pcie-qcom.c | 0
drivers/pci/{host => controller}/pcie-rcar.c | 0
drivers/pci/{host => controller}/pcie-spear13xx.c | 0
drivers/pci/{host => controller}/pcie-xilinx-nwl.c | 0
drivers/pci/{host => controller}/pcie-xilinx.c | 0
43 files changed, 62 insertions(+), 31 deletions(-)
rename drivers/pci/{host => controller}/Kconfig (93%)
rename drivers/pci/{host => controller}/Makefile (100%)
rename drivers/pci/{host => controller}/pci-aardvark.c (100%)
rename drivers/pci/{host => controller}/pci-dra7xx.c (100%)
rename drivers/pci/{host => controller}/pci-exynos.c (100%)
rename drivers/pci/{host => controller}/pci-host-common.c (100%)
rename drivers/pci/{host => controller}/pci-host-generic.c (100%)
rename drivers/pci/{host => controller}/pci-hyperv.c (100%)
rename drivers/pci/{host => controller}/pci-imx6.c (100%)
rename drivers/pci/{host => controller}/pci-keystone-dw.c (100%)
rename drivers/pci/{host => controller}/pci-keystone.c (100%)
rename drivers/pci/{host => controller}/pci-keystone.h (100%)
rename drivers/pci/{host => controller}/pci-layerscape.c (100%)
rename drivers/pci/{host => controller}/pci-mvebu.c (100%)
rename drivers/pci/{host => controller}/pci-rcar-gen2.c (100%)
rename drivers/pci/{host => controller}/pci-tegra.c (100%)
rename drivers/pci/{host => controller}/pci-thunder-ecam.c (100%)
rename drivers/pci/{host => controller}/pci-thunder-pem.c (100%)
rename drivers/pci/{host => controller}/pci-versatile.c (100%)
rename drivers/pci/{host => controller}/pci-xgene-msi.c (100%)
rename drivers/pci/{host => controller}/pci-xgene.c (100%)
rename drivers/pci/{host => controller}/pcie-altera-msi.c (100%)
rename drivers/pci/{host => controller}/pcie-altera.c (100%)
rename drivers/pci/{host => controller}/pcie-armada8k.c (100%)
rename drivers/pci/{host => controller}/pcie-artpec6.c (100%)
rename drivers/pci/{host => controller}/pcie-designware-plat.c (100%)
rename drivers/pci/{host => controller}/pcie-designware.c (100%)
rename drivers/pci/{host => controller}/pcie-designware.h (100%)
rename drivers/pci/{host => controller}/pcie-hisi.c (100%)
rename drivers/pci/{host => controller}/pcie-iproc-bcma.c (100%)
rename drivers/pci/{host => controller}/pcie-iproc-msi.c (100%)
rename drivers/pci/{host => controller}/pcie-iproc-platform.c (100%)
rename drivers/pci/{host => controller}/pcie-iproc.c (100%)
rename drivers/pci/{host => controller}/pcie-iproc.h (100%)
rename drivers/pci/{host => controller}/pcie-qcom.c (100%)
rename drivers/pci/{host => controller}/pcie-rcar.c (100%)
rename drivers/pci/{host => controller}/pcie-spear13xx.c (100%)
rename drivers/pci/{host => controller}/pcie-xilinx-nwl.c (100%)
rename drivers/pci/{host => controller}/pcie-xilinx.c (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index a5e1270..3db2531 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5662,7 +5662,7 @@ F: arch/x86/kernel/cpu/mshyperv.c
F: drivers/hid/hid-hyperv.c
F: drivers/hv/
F: drivers/input/serio/hyperv-keyboard.c
-F: drivers/pci/host/pci-hyperv.c
+F: drivers/pci/controller/pci-hyperv.c
F: drivers/net/hyperv/
F: drivers/scsi/storvsc_drv.c
F: drivers/video/fbdev/hyperv_fb.c
@@ -8945,7 +8945,7 @@ L: rfi at lists.rocketboards.org (moderated for non-subscribers)
L: linux-pci at vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/pci/altera-pcie.txt
-F: drivers/pci/host/pcie-altera.c
+F: drivers/pci/controller/pcie-altera.c
PCI DRIVER FOR ARM VERSATILE PLATFORM
M: Rob Herring <robh@kernel.org>
@@ -8953,7 +8953,7 @@ L: linux-pci at vger.kernel.org
L: linux-arm-kernel at lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/pci/versatile.txt
-F: drivers/pci/host/pci-versatile.c
+F: drivers/pci/controller/pci-versatile.c
PCI DRIVER FOR APPLIEDMICRO XGENE
M: Tanmay Inamdar <tinamdar@apm.com>
@@ -8961,7 +8961,7 @@ L: linux-pci at vger.kernel.org
L: linux-arm-kernel at lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/pci/xgene-pci.txt
-F: drivers/pci/host/pci-xgene.c
+F: drivers/pci/controller/pci-xgene.c
PCI DRIVER FOR FREESCALE LAYERSCAPE
M: Minghuan Lian <minghuan.Lian@freescale.com>
@@ -8971,7 +8971,7 @@ L: linuxppc-dev at lists.ozlabs.org
L: linux-pci at vger.kernel.org
L: linux-arm-kernel at lists.infradead.org
S: Maintained
-F: drivers/pci/host/*layerscape*
+F: drivers/pci/controller/*layerscape*
PCI DRIVER FOR IMX6
M: Richard Zhu <Richard.Zhu@freescale.com>
@@ -8979,14 +8979,14 @@ M: Lucas Stach <l.stach@pengutronix.de>
L: linux-pci at vger.kernel.org
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
-F: drivers/pci/host/*imx6*
+F: drivers/pci/controller/*imx6*
PCI DRIVER FOR TI KEYSTONE
M: Murali Karicheri <m-karicheri2@ti.com>
L: linux-pci at vger.kernel.org
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
-F: drivers/pci/host/*keystone*
+F: drivers/pci/controller/*keystone*
PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
M: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
@@ -8994,14 +8994,14 @@ M: Jason Cooper <jason@lakedaemon.net>
L: linux-pci at vger.kernel.org
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
-F: drivers/pci/host/*mvebu*
+F: drivers/pci/controller/*mvebu*
PCI DRIVER FOR AARDVARK (Marvell Armada 3700)
M: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
L: linux-pci at vger.kernel.org
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
-F: drivers/pci/host/pci-aardvark.c
+F: drivers/pci/controller/pci-aardvark.c
PCI DRIVER FOR NVIDIA TEGRA
M: Thierry Reding <thierry.reding@gmail.com>
@@ -9009,7 +9009,7 @@ L: linux-tegra at vger.kernel.org
L: linux-pci at vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
-F: drivers/pci/host/pci-tegra.c
+F: drivers/pci/controller/pci-tegra.c
PCI DRIVER FOR TI DRA7XX
M: Kishon Vijay Abraham I <kishon@ti.com>
@@ -9017,14 +9017,14 @@ L: linux-omap at vger.kernel.org
L: linux-pci at vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/pci/ti-pci.txt
-F: drivers/pci/host/pci-dra7xx.c
+F: drivers/pci/controller/pci-dra7xx.c
PCI DRIVER FOR RENESAS R-CAR
M: Simon Horman <horms@verge.net.au>
L: linux-pci at vger.kernel.org
L: linux-renesas-soc at vger.kernel.org
S: Maintained
-F: drivers/pci/host/*rcar*
+F: drivers/pci/controller/*rcar*
PCI DRIVER FOR SAMSUNG EXYNOS
M: Jingoo Han <jingoohan1@gmail.com>
@@ -9032,30 +9032,30 @@ L: linux-pci at vger.kernel.org
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
L: linux-samsung-soc at vger.kernel.org (moderated for non-subscribers)
S: Maintained
-F: drivers/pci/host/pci-exynos.c
+F: drivers/pci/controller/pci-exynos.c
PCI DRIVER FOR SYNOPSIS DESIGNWARE
M: Jingoo Han <jingoohan1@gmail.com>
M: Pratyush Anand <pratyush.anand@gmail.com>
L: linux-pci at vger.kernel.org
S: Maintained
-F: drivers/pci/host/*designware*
+F: drivers/pci/controller/*designware*
PCI DRIVER FOR SYNOPSYS PROTOTYPING DEVICE
M: Joao Pinto <jpinto@synopsys.com>
L: linux-pci at vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/designware-pcie.txt
-F: drivers/pci/host/pcie-designware-plat.c
+F: drivers/pci/controller/pcie-designware-plat.c
PCI DRIVER FOR GENERIC OF HOSTS
M: Will Deacon <will.deacon@arm.com>
L: linux-pci at vger.kernel.org
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
-F: Documentation/devicetree/bindings/pci/host-generic-pci.txt
-F: drivers/pci/host/pci-host-common.c
-F: drivers/pci/host/pci-host-generic.c
+F: Documentation/devicetree/bindings/pci/controller-generic-pci.txt
+F: drivers/pci/controller/pci-host-common.c
+F: drivers/pci/controller/pci-host-generic.c
PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD)
M: Keith Busch <keith.busch@intel.com>
@@ -9067,7 +9067,7 @@ PCIE DRIVER FOR ST SPEAR13XX
M: Pratyush Anand <pratyush.anand@gmail.com>
L: linux-pci at vger.kernel.org
S: Maintained
-F: drivers/pci/host/*spear*
+F: drivers/pci/controller/*spear*
PCI MSI DRIVER FOR ALTERA MSI IP
M: Ley Foon Tan <lftan@altera.com>
@@ -9075,7 +9075,7 @@ L: rfi at lists.rocketboards.org (moderated for non-subscribers)
L: linux-pci at vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
-F: drivers/pci/host/pcie-altera-msi.c
+F: drivers/pci/controller/pcie-altera-msi.c
PCI MSI DRIVER FOR APPLIEDMICRO XGENE
M: Duc Dang <dhdang@apm.com>
@@ -9083,7 +9083,7 @@ L: linux-pci at vger.kernel.org
L: linux-arm-kernel at lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
-F: drivers/pci/host/pci-xgene-msi.c
+F: drivers/pci/controller/pci-xgene-msi.c
PCIE DRIVER FOR AXIS ARTPEC
M: Niklas Cassel <niklas.cassel@axis.com>
@@ -9092,7 +9092,7 @@ L: linux-arm-kernel at axis.com
L: linux-pci at vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/axis,artpec*
-F: drivers/pci/host/*artpec*
+F: drivers/pci/controller/*artpec*
PCIE DRIVER FOR HISILICON
M: Zhou Wang <wangzhou1@hisilicon.com>
@@ -9100,14 +9100,14 @@ M: Gabriele Paoloni <gabriele.paoloni@huawei.com>
L: linux-pci at vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
-F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/controller/pcie-hisi.c
PCIE DRIVER FOR QUALCOMM MSM
M: Stanimir Varbanov <svarbanov@mm-sol.com>
L: linux-pci at vger.kernel.org
L: linux-arm-msm at vger.kernel.org
S: Maintained
-F: drivers/pci/host/*qcom*
+F: drivers/pci/controller/*qcom*
PCIE DRIVER FOR CAVIUM THUNDERX
M: David Daney <david.daney@cavium.com>
@@ -9115,7 +9115,7 @@ L: linux-pci at vger.kernel.org
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Supported
F: Documentation/devicetree/bindings/pci/pci-thunder-*
-F: drivers/pci/host/pci-thunder-*
+F: drivers/pci/controller/pci-thunder-*
PCMCIA SUBSYSTEM
P: Linux PCMCIA Team
diff --git a/drivers/Makefile b/drivers/Makefile
index 8c070ad..10cb1ad 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -16,6 +16,9 @@ obj-$(CONFIG_GPIOLIB) += gpio/
obj-y += pwm/
obj-$(CONFIG_PCI_ENDPOINT) += pci/endpoint/
obj-$(CONFIG_PCI) += pci/
+# PCI controller drivers
+obj-y += pci/controller/
+
obj-$(CONFIG_PARISC) += parisc/
obj-$(CONFIG_RAPIDIO) += rapidio/
obj-y += video/
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 5f116a6..c603a8a 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -132,5 +132,5 @@ config PCI_HYPERV
PCI devices from a PCI backend to support PCI driver domains.
source "drivers/pci/hotplug/Kconfig"
-source "drivers/pci/host/Kconfig"
+source "drivers/pci/controller/Kconfig"
source "drivers/pci/endpoint/Kconfig"
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 8db5079..b924cc9 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -65,6 +65,3 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
obj-$(CONFIG_OF) += of.o
ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
-
-# PCI host controller drivers
-obj-y += host/
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/controller/Kconfig
similarity index 93%
rename from drivers/pci/host/Kconfig
rename to drivers/pci/controller/Kconfig
index 9b485d8..4c55c2d 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -1,10 +1,10 @@
-menu "PCI host controller drivers"
- depends on PCI
+menu "PCI controller drivers"
config PCI_DRA7XX
bool "TI DRA7xx PCIe controller"
depends on OF && HAS_IOMEM && TI_PIPE3
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
select PCIE_DW
help
Enables support for the PCIe controller in the DRA7xx SoC. There
@@ -16,12 +16,14 @@ config PCI_MVEBU
depends on ARCH_MVEBU || ARCH_DOVE
depends on ARM
depends on OF
+ depends on PCI
config PCI_AARDVARK
bool "Aardvark PCIe controller"
depends on ARCH_MVEBU && ARM64
depends on OF
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
help
Add support for Aardvark 64bit PCIe Host Controller. This
controller is part of the South Bridge of the Marvel Armada
@@ -31,6 +33,7 @@ config PCIE_XILINX_NWL
bool "NWL PCIe Core"
depends on ARCH_ZYNQMP
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
help
Say 'Y' here if you want kernel support for Xilinx
NWL PCIe controller. The controller can act as Root Port
@@ -40,6 +43,7 @@ config PCIE_XILINX_NWL
config PCIE_DW_PLAT
bool "Platform bus based DesignWare PCIe Controller"
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
select PCIE_DW
---help---
This selects the DesignWare PCIe controller support. Select this if
@@ -52,6 +56,7 @@ config PCIE_DW_PLAT
config PCIE_DW
bool
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
config PCI_EXYNOS
bool "Samsung Exynos PCIe controller"
@@ -59,17 +64,20 @@ config PCI_EXYNOS
depends on PCI_MSI_IRQ_DOMAIN
select PCIEPORTBUS
select PCIE_DW
+ depends on PCI
config PCI_IMX6
bool "Freescale i.MX6 PCIe controller"
depends on SOC_IMX6Q
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
select PCIEPORTBUS
select PCIE_DW
config PCI_TEGRA
bool "NVIDIA Tegra PCIe controller"
depends on ARCH_TEGRA && !ARM64
+ depends on PCI
help
Say Y here if you want support for the PCIe host controller found
on NVIDIA Tegra SoCs.
@@ -78,6 +86,7 @@ config PCI_RCAR_GEN2
bool "Renesas R-Car Gen2 Internal PCI controller"
depends on ARM
depends on ARCH_RENESAS || COMPILE_TEST
+ depends on PCI
help
Say Y here if you want internal PCI support on R-Car Gen2 SoC.
There are 3 internal PCI controllers available with a single
@@ -87,16 +96,19 @@ config PCIE_RCAR
bool "Renesas R-Car PCIe controller"
depends on ARCH_RENESAS || (ARM && COMPILE_TEST)
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
help
Say Y here if you want PCIe controller support on R-Car SoCs.
config PCI_HOST_COMMON
bool
+ depends on PCI
select PCI_ECAM
config PCI_HOST_GENERIC
bool "Generic PCI host controller"
depends on (ARM || ARM64) && OF
+ depends on PCI
select PCI_HOST_COMMON
select IRQ_DOMAIN
help
@@ -107,6 +119,7 @@ config PCIE_SPEAR13XX
bool "STMicroelectronics SPEAr PCIe controller"
depends on ARCH_SPEAR13XX
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
select PCIEPORTBUS
select PCIE_DW
help
@@ -116,6 +129,7 @@ config PCI_KEYSTONE
bool "TI Keystone PCIe controller"
depends on ARCH_KEYSTONE
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
select PCIE_DW
select PCIEPORTBUS
help
@@ -127,6 +141,7 @@ config PCI_KEYSTONE
config PCIE_XILINX
bool "Xilinx AXI PCIe host bridge support"
depends on ARCH_ZYNQ || MICROBLAZE
+ depends on PCI
help
Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
Host Bridge driver.
@@ -135,6 +150,7 @@ config PCI_XGENE
bool "X-Gene PCIe controller"
depends on ARCH_XGENE
depends on OF
+ depends on PCI
select PCIEPORTBUS
help
Say Y here if you want internal PCI support on APM X-Gene SoC.
@@ -145,6 +161,7 @@ config PCI_XGENE_MSI
bool "X-Gene v1 PCIe MSI feature"
depends on PCI_XGENE
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
default y
help
Say Y here if you want PCIe MSI support for the APM X-Gene v1 SoC.
@@ -154,6 +171,7 @@ config PCI_LAYERSCAPE
bool "Freescale Layerscape PCIe controller"
depends on OF && (ARM || ARCH_LAYERSCAPE)
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
select PCIE_DW
select MFD_SYSCON
help
@@ -162,9 +180,11 @@ config PCI_LAYERSCAPE
config PCI_VERSATILE
bool "ARM Versatile PB PCI controller"
depends on ARCH_VERSATILE
+ depends on PCI
config PCIE_IPROC
tristate
+ depends on PCI
help
This enables the iProc PCIe core controller support for Broadcom's
iProc family of SoCs. An appropriate bus interface driver needs
@@ -174,6 +194,7 @@ config PCIE_IPROC_PLATFORM
tristate "Broadcom iProc PCIe platform bus driver"
depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)
depends on OF
+ depends on PCI
select PCIE_IPROC
default ARCH_BCM_IPROC
help
@@ -183,6 +204,7 @@ config PCIE_IPROC_PLATFORM
config PCIE_IPROC_BCMA
tristate "Broadcom iProc PCIe BCMA bus driver"
depends on ARM && (ARCH_BCM_IPROC || COMPILE_TEST)
+ depends on PCI
select PCIE_IPROC
select BCMA
select PCI_DOMAINS
@@ -195,6 +217,7 @@ config PCIE_IPROC_MSI
bool "Broadcom iProc PCIe MSI support"
depends on PCIE_IPROC_PLATFORM || PCIE_IPROC_BCMA
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
default ARCH_BCM_IPROC
help
Say Y here if you want to enable MSI support for Broadcom's iProc
@@ -204,6 +227,7 @@ config PCIE_ALTERA
bool "Altera PCIe controller"
depends on ARM || NIOS2
depends on OF_PCI
+ depends on PCI
select PCI_DOMAINS
help
Say Y here if you want to enable PCIe controller support on Altera
@@ -213,6 +237,7 @@ config PCIE_ALTERA_MSI
bool "Altera PCIe MSI feature"
depends on PCIE_ALTERA
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
help
Say Y here if you want PCIe MSI support for the Altera FPGA.
This MSI driver supports Altera MSI to GIC controller IP.
@@ -221,6 +246,7 @@ config PCI_HISI
depends on OF && ARM64
bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
select PCIEPORTBUS
select PCIE_DW
help
@@ -231,6 +257,7 @@ config PCIE_QCOM
bool "Qualcomm PCIe controller"
depends on ARCH_QCOM && OF
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
select PCIE_DW
select PCIEPORTBUS
help
@@ -241,6 +268,7 @@ config PCIE_QCOM
config PCI_HOST_THUNDER_PEM
bool "Cavium Thunder PCIe controller to off-chip devices"
depends on OF && ARM64
+ depends on PCI
select PCI_HOST_COMMON
help
Say Y here if you want PCIe support for CN88XX Cavium Thunder SoCs.
@@ -248,6 +276,7 @@ config PCI_HOST_THUNDER_PEM
config PCI_HOST_THUNDER_ECAM
bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
depends on OF && ARM64
+ depends on PCI
select PCI_HOST_COMMON
help
Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
@@ -256,6 +285,7 @@ config PCIE_ARMADA_8K
bool "Marvell Armada-8K PCIe controller"
depends on ARCH_MVEBU
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
select PCIE_DW
select PCIEPORTBUS
help
@@ -268,6 +298,7 @@ config PCIE_ARTPEC6
bool "Axis ARTPEC-6 PCIe controller"
depends on MACH_ARTPEC6
depends on PCI_MSI_IRQ_DOMAIN
+ depends on PCI
select PCIE_DW
select PCIEPORTBUS
help
diff --git a/drivers/pci/host/Makefile b/drivers/pci/controller/Makefile
similarity index 100%
rename from drivers/pci/host/Makefile
rename to drivers/pci/controller/Makefile
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
similarity index 100%
rename from drivers/pci/host/pci-aardvark.c
rename to drivers/pci/controller/pci-aardvark.c
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/controller/pci-dra7xx.c
similarity index 100%
rename from drivers/pci/host/pci-dra7xx.c
rename to drivers/pci/controller/pci-dra7xx.c
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/controller/pci-exynos.c
similarity index 100%
rename from drivers/pci/host/pci-exynos.c
rename to drivers/pci/controller/pci-exynos.c
diff --git a/drivers/pci/host/pci-host-common.c b/drivers/pci/controller/pci-host-common.c
similarity index 100%
rename from drivers/pci/host/pci-host-common.c
rename to drivers/pci/controller/pci-host-common.c
diff --git a/drivers/pci/host/pci-host-generic.c b/drivers/pci/controller/pci-host-generic.c
similarity index 100%
rename from drivers/pci/host/pci-host-generic.c
rename to drivers/pci/controller/pci-host-generic.c
diff --git a/drivers/pci/host/pci-hyperv.c b/drivers/pci/controller/pci-hyperv.c
similarity index 100%
rename from drivers/pci/host/pci-hyperv.c
rename to drivers/pci/controller/pci-hyperv.c
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/controller/pci-imx6.c
similarity index 100%
rename from drivers/pci/host/pci-imx6.c
rename to drivers/pci/controller/pci-imx6.c
diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/controller/pci-keystone-dw.c
similarity index 100%
rename from drivers/pci/host/pci-keystone-dw.c
rename to drivers/pci/controller/pci-keystone-dw.c
diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/controller/pci-keystone.c
similarity index 100%
rename from drivers/pci/host/pci-keystone.c
rename to drivers/pci/controller/pci-keystone.c
diff --git a/drivers/pci/host/pci-keystone.h b/drivers/pci/controller/pci-keystone.h
similarity index 100%
rename from drivers/pci/host/pci-keystone.h
rename to drivers/pci/controller/pci-keystone.h
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/controller/pci-layerscape.c
similarity index 100%
rename from drivers/pci/host/pci-layerscape.c
rename to drivers/pci/controller/pci-layerscape.c
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
similarity index 100%
rename from drivers/pci/host/pci-mvebu.c
rename to drivers/pci/controller/pci-mvebu.c
diff --git a/drivers/pci/host/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
similarity index 100%
rename from drivers/pci/host/pci-rcar-gen2.c
rename to drivers/pci/controller/pci-rcar-gen2.c
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
similarity index 100%
rename from drivers/pci/host/pci-tegra.c
rename to drivers/pci/controller/pci-tegra.c
diff --git a/drivers/pci/host/pci-thunder-ecam.c b/drivers/pci/controller/pci-thunder-ecam.c
similarity index 100%
rename from drivers/pci/host/pci-thunder-ecam.c
rename to drivers/pci/controller/pci-thunder-ecam.c
diff --git a/drivers/pci/host/pci-thunder-pem.c b/drivers/pci/controller/pci-thunder-pem.c
similarity index 100%
rename from drivers/pci/host/pci-thunder-pem.c
rename to drivers/pci/controller/pci-thunder-pem.c
diff --git a/drivers/pci/host/pci-versatile.c b/drivers/pci/controller/pci-versatile.c
similarity index 100%
rename from drivers/pci/host/pci-versatile.c
rename to drivers/pci/controller/pci-versatile.c
diff --git a/drivers/pci/host/pci-xgene-msi.c b/drivers/pci/controller/pci-xgene-msi.c
similarity index 100%
rename from drivers/pci/host/pci-xgene-msi.c
rename to drivers/pci/controller/pci-xgene-msi.c
diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
similarity index 100%
rename from drivers/pci/host/pci-xgene.c
rename to drivers/pci/controller/pci-xgene.c
diff --git a/drivers/pci/host/pcie-altera-msi.c b/drivers/pci/controller/pcie-altera-msi.c
similarity index 100%
rename from drivers/pci/host/pcie-altera-msi.c
rename to drivers/pci/controller/pcie-altera-msi.c
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/controller/pcie-altera.c
similarity index 100%
rename from drivers/pci/host/pcie-altera.c
rename to drivers/pci/controller/pcie-altera.c
diff --git a/drivers/pci/host/pcie-armada8k.c b/drivers/pci/controller/pcie-armada8k.c
similarity index 100%
rename from drivers/pci/host/pcie-armada8k.c
rename to drivers/pci/controller/pcie-armada8k.c
diff --git a/drivers/pci/host/pcie-artpec6.c b/drivers/pci/controller/pcie-artpec6.c
similarity index 100%
rename from drivers/pci/host/pcie-artpec6.c
rename to drivers/pci/controller/pcie-artpec6.c
diff --git a/drivers/pci/host/pcie-designware-plat.c b/drivers/pci/controller/pcie-designware-plat.c
similarity index 100%
rename from drivers/pci/host/pcie-designware-plat.c
rename to drivers/pci/controller/pcie-designware-plat.c
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/controller/pcie-designware.c
similarity index 100%
rename from drivers/pci/host/pcie-designware.c
rename to drivers/pci/controller/pcie-designware.c
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/controller/pcie-designware.h
similarity index 100%
rename from drivers/pci/host/pcie-designware.h
rename to drivers/pci/controller/pcie-designware.h
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/controller/pcie-hisi.c
similarity index 100%
rename from drivers/pci/host/pcie-hisi.c
rename to drivers/pci/controller/pcie-hisi.c
diff --git a/drivers/pci/host/pcie-iproc-bcma.c b/drivers/pci/controller/pcie-iproc-bcma.c
similarity index 100%
rename from drivers/pci/host/pcie-iproc-bcma.c
rename to drivers/pci/controller/pcie-iproc-bcma.c
diff --git a/drivers/pci/host/pcie-iproc-msi.c b/drivers/pci/controller/pcie-iproc-msi.c
similarity index 100%
rename from drivers/pci/host/pcie-iproc-msi.c
rename to drivers/pci/controller/pcie-iproc-msi.c
diff --git a/drivers/pci/host/pcie-iproc-platform.c b/drivers/pci/controller/pcie-iproc-platform.c
similarity index 100%
rename from drivers/pci/host/pcie-iproc-platform.c
rename to drivers/pci/controller/pcie-iproc-platform.c
diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c
similarity index 100%
rename from drivers/pci/host/pcie-iproc.c
rename to drivers/pci/controller/pcie-iproc.c
diff --git a/drivers/pci/host/pcie-iproc.h b/drivers/pci/controller/pcie-iproc.h
similarity index 100%
rename from drivers/pci/host/pcie-iproc.h
rename to drivers/pci/controller/pcie-iproc.h
diff --git a/drivers/pci/host/pcie-qcom.c b/drivers/pci/controller/pcie-qcom.c
similarity index 100%
rename from drivers/pci/host/pcie-qcom.c
rename to drivers/pci/controller/pcie-qcom.c
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c
similarity index 100%
rename from drivers/pci/host/pcie-rcar.c
rename to drivers/pci/controller/pcie-rcar.c
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/controller/pcie-spear13xx.c
similarity index 100%
rename from drivers/pci/host/pcie-spear13xx.c
rename to drivers/pci/controller/pcie-spear13xx.c
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
similarity index 100%
rename from drivers/pci/host/pcie-xilinx-nwl.c
rename to drivers/pci/controller/pcie-xilinx-nwl.c
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/controller/pcie-xilinx.c
similarity index 100%
rename from drivers/pci/host/pcie-xilinx.c
rename to drivers/pci/controller/pcie-xilinx.c
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH] pci: controller: split designware into *core* and *host*
From: Kishon Vijay Abraham I @ 2016-09-13 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473786653-12759-1-git-send-email-kishon@ti.com>
No functional change. Split the designware core driver into
*core* driver and *host* only driver. This is in preparation
to add endpoint support in designware. The *endpoint* driver will
reuse the *core* driver.
This also modifies the dra7xx code to use the new architecture.
TODO: All other platforms using designware core should also
be modified accordingly.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/controller/Kconfig | 48 +-
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pci-dra7xx.c | 117 +++-
.../{pcie-designware.c => pcie-designware-host.c} | 294 ++------
drivers/pci/controller/pcie-designware.c | 741 ++------------------
drivers/pci/controller/pcie-designware.h | 158 ++++-
6 files changed, 367 insertions(+), 992 deletions(-)
copy drivers/pci/controller/{pcie-designware.c => pcie-designware-host.c} (64%)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 4c55c2d..249db74 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -3,13 +3,29 @@ menu "PCI controller drivers"
config PCI_DRA7XX
bool "TI DRA7xx PCIe controller"
depends on OF && HAS_IOMEM && TI_PIPE3
+ help
+ Enables support for the PCIe controller in the DRA7xx SoC. There
+ are two instances of PCIe controller in DRA7xx. This controller can
+ work either as EP or RC. In order to enable host specific features
+ PCI_DRA7XX_HOST must be selected. This reuses the Designware core.
+
+if PCI_DRA7XX
+
+choice
+ bool "PCIe Mode"
+
+config PCI_DRA7XX_HOST
+ bool "Host Only Mode"
depends on PCI_MSI_IRQ_DOMAIN
depends on PCI
- select PCIE_DW
+ select PCIE_DW_HOST
help
- Enables support for the PCIe controller in the DRA7xx SoC. There
- are two instances of PCIe controller in DRA7xx. This controller can
- act both as EP and RC. This reuses the Designware core.
+ Enables support for the PCIe controller in the DRA7xx SoC to work in
+ host mode.
+
+endchoice
+
+endif
config PCI_MVEBU
bool "Marvell EBU PCIe controller"
@@ -44,7 +60,7 @@ config PCIE_DW_PLAT
bool "Platform bus based DesignWare PCIe Controller"
depends on PCI_MSI_IRQ_DOMAIN
depends on PCI
- select PCIE_DW
+ select PCIE_DW_HOST
---help---
This selects the DesignWare PCIe controller support. Select this if
you have a PCIe controller on Platform bus.
@@ -55,16 +71,20 @@ config PCIE_DW_PLAT
config PCIE_DW
bool
+
+config PCIE_DW_HOST
+ bool
depends on PCI_MSI_IRQ_DOMAIN
depends on PCI
+ select PCIE_DW
config PCI_EXYNOS
bool "Samsung Exynos PCIe controller"
depends on SOC_EXYNOS5440
depends on PCI_MSI_IRQ_DOMAIN
select PCIEPORTBUS
- select PCIE_DW
depends on PCI
+ select PCIE_DW_HOST
config PCI_IMX6
bool "Freescale i.MX6 PCIe controller"
@@ -72,7 +92,7 @@ config PCI_IMX6
depends on PCI_MSI_IRQ_DOMAIN
depends on PCI
select PCIEPORTBUS
- select PCIE_DW
+ select PCIE_DW_HOST
config PCI_TEGRA
bool "NVIDIA Tegra PCIe controller"
@@ -121,7 +141,7 @@ config PCIE_SPEAR13XX
depends on PCI_MSI_IRQ_DOMAIN
depends on PCI
select PCIEPORTBUS
- select PCIE_DW
+ select PCIE_DW_HOST
help
Say Y here if you want PCIe support on SPEAr13XX SoCs.
@@ -130,7 +150,7 @@ config PCI_KEYSTONE
depends on ARCH_KEYSTONE
depends on PCI_MSI_IRQ_DOMAIN
depends on PCI
- select PCIE_DW
+ select PCIE_DW_HOST
select PCIEPORTBUS
help
Say Y here if you want to enable PCI controller support on Keystone
@@ -172,7 +192,7 @@ config PCI_LAYERSCAPE
depends on OF && (ARM || ARCH_LAYERSCAPE)
depends on PCI_MSI_IRQ_DOMAIN
depends on PCI
- select PCIE_DW
+ select PCIE_DW_HOST
select MFD_SYSCON
help
Say Y here if you want PCIe controller support on Layerscape SoCs.
@@ -248,7 +268,7 @@ config PCI_HISI
depends on PCI_MSI_IRQ_DOMAIN
depends on PCI
select PCIEPORTBUS
- select PCIE_DW
+ select PCIE_DW_HOST
help
Say Y here if you want PCIe controller support on HiSilicon
Hip05 and Hip06 SoCs
@@ -258,7 +278,7 @@ config PCIE_QCOM
depends on ARCH_QCOM && OF
depends on PCI_MSI_IRQ_DOMAIN
depends on PCI
- select PCIE_DW
+ select PCIE_DW_HOST
select PCIEPORTBUS
help
Say Y here to enable PCIe controller support on Qualcomm SoCs. The
@@ -286,7 +306,7 @@ config PCIE_ARMADA_8K
depends on ARCH_MVEBU
depends on PCI_MSI_IRQ_DOMAIN
depends on PCI
- select PCIE_DW
+ select PCIE_DW_HOST
select PCIEPORTBUS
help
Say Y here if you want to enable PCIe controller support on
@@ -299,7 +319,7 @@ config PCIE_ARTPEC6
depends on MACH_ARTPEC6
depends on PCI_MSI_IRQ_DOMAIN
depends on PCI
- select PCIE_DW
+ select PCIE_DW_HOST
select PCIEPORTBUS
help
Say Y here to enable PCIe controller support on Axis ARTPEC-6
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 8843410..ee6bb85 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_PCIE_DW) += pcie-designware.o
+obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
diff --git a/drivers/pci/controller/pci-dra7xx.c b/drivers/pci/controller/pci-dra7xx.c
index 81b3949..dc5b8ef 100644
--- a/drivers/pci/controller/pci-dra7xx.c
+++ b/drivers/pci/controller/pci-dra7xx.c
@@ -68,10 +68,10 @@ struct dra7xx_pcie {
struct phy **phy;
int phy_count;
struct device *dev;
- struct pcie_port pp;
+ struct dw_pcie *pci;
};
-#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
+#define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
{
@@ -84,50 +84,54 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
writel(value, pcie->base + offset);
}
-static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset)
+static inline u32 dra7xx_pcie_readl_dbi(void __iomem *base, u32 offset)
{
- return readl(pp->dbi_base + offset);
+ return readl(base + offset);
}
-static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset,
- u32 value)
+static inline void dra7xx_pcie_writel_dbi(void __iomem *base, u32 offset,
+ u32 value)
{
- writel(value, pp->dbi_base + offset);
+ writel(value, base + offset);
}
-static int dra7xx_pcie_link_up(struct pcie_port *pp)
+static int dra7xx_pcie_link_up(struct dw_pcie *pci)
{
- struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
+ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
return !!(reg & LINK_UP);
}
-static int dra7xx_pcie_establish_link(struct pcie_port *pp)
+static int dra7xx_pcie_start_link(struct dw_pcie *pci)
{
- struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
+ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
u32 reg;
- if (dw_pcie_link_up(pp)) {
- dev_err(pp->dev, "link is already up\n");
- return 0;
+ if (dw_pcie_link_up(pci)) {
+ dev_err(pci->dev, "link is already up\n");
+ return -EBUSY;
}
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
reg |= LTSSM_EN;
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
- return dw_pcie_wait_for_link(pp);
+ return 0;
}
-static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
+static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
{
- struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
+ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
+ u32 reg;
- dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
- ~INTERRUPTS);
- dra7xx_pcie_writel(dra7xx,
- PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
+ reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
+ reg &= ~LTSSM_EN;
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
+}
+
+static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
+{
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
~LEG_EP_INTERRUPTS & ~MSI);
@@ -140,8 +144,25 @@ static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
LEG_EP_INTERRUPTS);
}
+static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
+{
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
+ ~INTERRUPTS);
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
+ INTERRUPTS);
+}
+
+static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
+{
+ dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
+ dra7xx_pcie_enable_msi_interrupts(dra7xx);
+}
+
static void dra7xx_pcie_host_init(struct pcie_port *pp)
{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
+
pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
@@ -149,14 +170,16 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
dw_pcie_setup_rc(pp);
- dra7xx_pcie_establish_link(pp);
+ dra7xx_pcie_start_link(pci);
+ dw_pcie_wait_for_link(pci);
+
if (IS_ENABLED(CONFIG_PCI_MSI))
dw_pcie_msi_init(pp);
- dra7xx_pcie_enable_interrupts(pp);
+
+ dra7xx_pcie_enable_interrupts(dra7xx);
}
-static struct pcie_host_ops dra7xx_pcie_host_ops = {
- .link_up = dra7xx_pcie_link_up,
+static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
.host_init = dra7xx_pcie_host_init,
};
@@ -175,7 +198,8 @@ static const struct irq_domain_ops intx_domain_ops = {
static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
{
- struct device *dev = pp->dev;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct device *dev = pci->dev;
struct device_node *node = dev->of_node;
struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
@@ -197,7 +221,8 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
{
struct pcie_port *pp = arg;
- struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
u32 reg;
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
@@ -281,9 +306,9 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
struct pcie_port *pp;
struct resource *res;
struct device *dev = &pdev->dev;
+ struct dw_pcie *pci = dra7xx->pci;
- pp = &dra7xx->pp;
- pp->dev = dev;
+ pp = &pci->pp;
pp->ops = &dra7xx_pcie_host_ops;
pp->irq = platform_get_irq(pdev, 1);
@@ -308,8 +333,8 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
- pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
- if (!pp->dbi_base)
+ pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
+ if (!pci->dbi_base)
return -ENOMEM;
ret = dw_pcie_host_init(pp);
@@ -321,6 +346,12 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
return 0;
}
+static const struct dw_pcie_ops dw_pcie_ops = {
+ .start_link = dra7xx_pcie_start_link,
+ .stop_link = dra7xx_pcie_stop_link,
+ .link_up = dra7xx_pcie_link_up,
+};
+
static int __init dra7xx_pcie_probe(struct platform_device *pdev)
{
u32 reg;
@@ -331,6 +362,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
struct phy **phy;
void __iomem *base;
struct resource *res;
+ struct dw_pcie *pci;
struct dra7xx_pcie *dra7xx;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
@@ -343,6 +375,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
if (!dra7xx)
return -ENOMEM;
+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci)
+ return -ENOMEM;
+
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(dev, "missing IRQ resource\n");
@@ -388,8 +424,12 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
}
}
+ pci->dev = dev;
+ pci->ops = &dw_pcie_ops;
+
dra7xx->base = base;
dra7xx->phy = phy;
+ dra7xx->pci = pci;
dra7xx->dev = dev;
dra7xx->phy_count = phy_count;
@@ -446,7 +486,8 @@ err_phy:
static int __exit dra7xx_pcie_remove(struct platform_device *pdev)
{
struct dra7xx_pcie *dra7xx = platform_get_drvdata(pdev);
- struct pcie_port *pp = &dra7xx->pp;
+ struct dw_pcie *pci = dra7xx->pci;
+ struct pcie_port *pp = &pci->pp;
struct device *dev = &pdev->dev;
int count = dra7xx->phy_count;
@@ -466,13 +507,13 @@ static int __exit dra7xx_pcie_remove(struct platform_device *pdev)
static int dra7xx_pcie_suspend(struct device *dev)
{
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
- struct pcie_port *pp = &dra7xx->pp;
+ struct dw_pcie *pci = dra7xx->pci;
u32 val;
/* clear MSE */
- val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
+ val = dra7xx_pcie_readl_dbi(pci->dbi_base, PCI_COMMAND);
val &= ~PCI_COMMAND_MEMORY;
- dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
+ dra7xx_pcie_writel_dbi(pci->dbi_base, PCI_COMMAND, val);
return 0;
}
@@ -480,13 +521,13 @@ static int dra7xx_pcie_suspend(struct device *dev)
static int dra7xx_pcie_resume(struct device *dev)
{
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
- struct pcie_port *pp = &dra7xx->pp;
+ struct dw_pcie *pci = dra7xx->pci;
u32 val;
/* set MSE */
- val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
+ val = dra7xx_pcie_readl_dbi(pci->dbi_base, PCI_COMMAND);
val |= PCI_COMMAND_MEMORY;
- dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
+ dra7xx_pcie_writel_dbi(pci->dbi_base, PCI_COMMAND, val);
return 0;
}
diff --git a/drivers/pci/controller/pcie-designware.c b/drivers/pci/controller/pcie-designware-host.c
similarity index 64%
copy from drivers/pci/controller/pcie-designware.c
copy to drivers/pci/controller/pcie-designware-host.c
index 12afce1..8a21ccb 100644
--- a/drivers/pci/controller/pcie-designware.c
+++ b/drivers/pci/controller/pcie-designware-host.c
@@ -11,165 +11,39 @@
* published by the Free Software Foundation.
*/
-#include <linux/irq.h>
#include <linux/irqdomain.h>
-#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
-#include <linux/pci.h>
#include <linux/pci_regs.h>
#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/delay.h>
#include "pcie-designware.h"
-/* Synopsis specific PCIE configuration registers */
-#define PCIE_PORT_LINK_CONTROL 0x710
-#define PORT_LINK_MODE_MASK (0x3f << 16)
-#define PORT_LINK_MODE_1_LANES (0x1 << 16)
-#define PORT_LINK_MODE_2_LANES (0x3 << 16)
-#define PORT_LINK_MODE_4_LANES (0x7 << 16)
-#define PORT_LINK_MODE_8_LANES (0xf << 16)
-
-#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
-#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
-#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
-#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
-#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
-#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
-#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
-
-#define PCIE_MSI_ADDR_LO 0x820
-#define PCIE_MSI_ADDR_HI 0x824
-#define PCIE_MSI_INTR0_ENABLE 0x828
-#define PCIE_MSI_INTR0_MASK 0x82C
-#define PCIE_MSI_INTR0_STATUS 0x830
-
-#define PCIE_ATU_VIEWPORT 0x900
-#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
-#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
-#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
-#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
-#define PCIE_ATU_CR1 0x904
-#define PCIE_ATU_TYPE_MEM (0x0 << 0)
-#define PCIE_ATU_TYPE_IO (0x2 << 0)
-#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
-#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
-#define PCIE_ATU_CR2 0x908
-#define PCIE_ATU_ENABLE (0x1 << 31)
-#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
-#define PCIE_ATU_LOWER_BASE 0x90C
-#define PCIE_ATU_UPPER_BASE 0x910
-#define PCIE_ATU_LIMIT 0x914
-#define PCIE_ATU_LOWER_TARGET 0x918
-#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
-#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
-#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
-#define PCIE_ATU_UPPER_TARGET 0x91C
-
-/* PCIe Port Logic registers */
-#define PLR_OFFSET 0x700
-#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
-#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
-
static struct pci_ops dw_pcie_ops;
-int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
-{
- if ((uintptr_t)addr & (size - 1)) {
- *val = 0;
- return PCIBIOS_BAD_REGISTER_NUMBER;
- }
-
- if (size == 4)
- *val = readl(addr);
- else if (size == 2)
- *val = readw(addr);
- else if (size == 1)
- *val = readb(addr);
- else {
- *val = 0;
- return PCIBIOS_BAD_REGISTER_NUMBER;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
-{
- if ((uintptr_t)addr & (size - 1))
- return PCIBIOS_BAD_REGISTER_NUMBER;
-
- if (size == 4)
- writel(val, addr);
- else if (size == 2)
- writew(val, addr);
- else if (size == 1)
- writeb(val, addr);
- else
- return PCIBIOS_BAD_REGISTER_NUMBER;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
-{
- if (pp->ops->readl_rc)
- pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
- else
- *val = readl(pp->dbi_base + reg);
-}
-
-static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
-{
- if (pp->ops->writel_rc)
- pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
- else
- writel(val, pp->dbi_base + reg);
-}
-
static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
u32 *val)
{
+ struct dw_pcie *pci;
+
if (pp->ops->rd_own_conf)
return pp->ops->rd_own_conf(pp, where, size, val);
- return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
+ pci = to_dw_pcie_from_pp(pp);
+ return dw_pcie_read(pci->dbi_base + where, size, val);
}
static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
u32 val)
{
+ struct dw_pcie *pci;
+
if (pp->ops->wr_own_conf)
return pp->ops->wr_own_conf(pp, where, size, val);
- return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
-}
-
-static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
- int type, u64 cpu_addr, u64 pci_addr, u32 size)
-{
- u32 val;
-
- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
- PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
- PCIE_ATU_LIMIT);
- dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
- dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
- dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-
- /*
- * Make sure ATU enable takes effect before any subsequent config
- * and I/O accesses.
- */
- dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
+ pci = to_dw_pcie_from_pp(pp);
+ return dw_pcie_write(pci->dbi_base + where, size, val);
}
static struct irq_chip dw_msi_irq_chip = {
@@ -386,35 +260,6 @@ static struct msi_controller dw_pcie_msi_chip = {
.teardown_irq = dw_msi_teardown_irq,
};
-int dw_pcie_wait_for_link(struct pcie_port *pp)
-{
- int retries;
-
- /* check if the link is up or not */
- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
- if (dw_pcie_link_up(pp)) {
- dev_info(pp->dev, "link up\n");
- return 0;
- }
- usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
- }
-
- dev_err(pp->dev, "phy link never came up\n");
-
- return -ETIMEDOUT;
-}
-
-int dw_pcie_link_up(struct pcie_port *pp)
-{
- u32 val;
-
- if (pp->ops->link_up)
- return pp->ops->link_up(pp);
-
- val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
- return val & PCIE_PHY_DEBUG_R1_LINK_UP;
-}
-
static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq)
{
@@ -430,8 +275,10 @@ static const struct irq_domain_ops msi_domain_ops = {
int dw_pcie_host_init(struct pcie_port *pp)
{
- struct device_node *np = pp->dev->of_node;
- struct platform_device *pdev = to_platform_device(pp->dev);
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct device *dev = pci->dev;
+ struct device_node *np = dev->of_node;
+ struct platform_device *pdev = to_platform_device(pci->dev);
struct pci_bus *bus, *child;
struct resource *cfg_res;
int i, ret;
@@ -445,14 +292,14 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->cfg0_base = cfg_res->start;
pp->cfg1_base = cfg_res->start + pp->cfg0_size;
} else if (!pp->va_cfg0_base) {
- dev_err(pp->dev, "missing *config* reg space\n");
+ dev_err(dev, "missing *config* reg space\n");
}
ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
if (ret)
return ret;
- ret = devm_request_pci_bus_resources(&pdev->dev, &res);
+ ret = devm_request_pci_bus_resources(dev, &res);
if (ret)
goto error;
@@ -466,7 +313,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->io_bus_addr = pp->io->start - win->offset;
ret = pci_remap_iospace(pp->io, pp->io_base);
if (ret)
- dev_warn(pp->dev, "error %d: failed to map resource %pR\n",
+ dev_warn(dev, "error %d: failed to map resource %pR\n",
ret, pp->io);
break;
case IORESOURCE_MEM:
@@ -488,11 +335,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
}
}
- if (!pp->dbi_base) {
- pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
- resource_size(pp->cfg));
- if (!pp->dbi_base) {
- dev_err(pp->dev, "error with ioremap\n");
+ if (!pci->dbi_base) {
+ pci->dbi_base = devm_ioremap(dev, pp->cfg->start,
+ resource_size(pp->cfg));
+ if (!pci->dbi_base) {
+ dev_err(dev, "error with ioremap\n");
ret = -ENOMEM;
goto error;
}
@@ -501,36 +348,36 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->mem_base = pp->mem->start;
if (!pp->va_cfg0_base) {
- pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
+ pp->va_cfg0_base = devm_ioremap(dev, pp->cfg0_base,
pp->cfg0_size);
if (!pp->va_cfg0_base) {
- dev_err(pp->dev, "error with ioremap in function\n");
+ dev_err(dev, "error with ioremap in function\n");
ret = -ENOMEM;
goto error;
}
}
if (!pp->va_cfg1_base) {
- pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
+ pp->va_cfg1_base = devm_ioremap(dev, pp->cfg1_base,
pp->cfg1_size);
if (!pp->va_cfg1_base) {
- dev_err(pp->dev, "error with ioremap\n");
+ dev_err(dev, "error with ioremap\n");
ret = -ENOMEM;
goto error;
}
}
- ret = of_property_read_u32(np, "num-lanes", &pp->lanes);
+ ret = of_property_read_u32(np, "num-lanes", &pci->lanes);
if (ret)
- pp->lanes = 0;
+ pci->lanes = 0;
if (IS_ENABLED(CONFIG_PCI_MSI)) {
if (!pp->ops->msi_host_init) {
- pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
+ pp->irq_domain = irq_domain_add_linear(np,
MAX_MSI_IRQS, &msi_domain_ops,
&dw_pcie_msi_chip);
if (!pp->irq_domain) {
- dev_err(pp->dev, "irq domain init failed\n");
+ dev_err(dev, "irq domain init failed\n");
ret = -ENXIO;
goto error;
}
@@ -549,12 +396,12 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->root_bus_nr = pp->busn->start;
if (IS_ENABLED(CONFIG_PCI_MSI)) {
- bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
+ bus = pci_scan_root_bus_msi(dev, pp->root_bus_nr,
&dw_pcie_ops, pp, &res,
&dw_pcie_msi_chip);
- dw_pcie_msi_chip.dev = pp->dev;
+ dw_pcie_msi_chip.dev = dev;
} else
- bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
+ bus = pci_scan_root_bus(dev, pp->root_bus_nr, &dw_pcie_ops,
pp, &res);
if (!bus) {
ret = -ENOMEM;
@@ -590,6 +437,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
u32 busdev, cfg_size;
u64 cpu_addr;
void __iomem *va_cfg_base;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
if (pp->ops->rd_other_conf)
return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
@@ -609,11 +457,11 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
va_cfg_base = pp->va_cfg1_base;
}
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
type, cpu_addr,
busdev, cfg_size);
- ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ ret = dw_pcie_read(va_cfg_base + where, size, val);
+ dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
@@ -627,6 +475,7 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
u32 busdev, cfg_size;
u64 cpu_addr;
void __iomem *va_cfg_base;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
if (pp->ops->wr_other_conf)
return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
@@ -646,11 +495,11 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
va_cfg_base = pp->va_cfg1_base;
}
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
type, cpu_addr,
busdev, cfg_size);
- ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ ret = dw_pcie_write(va_cfg_base + where, size, val);
+ dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
@@ -660,9 +509,11 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
static int dw_pcie_valid_config(struct pcie_port *pp,
struct pci_bus *bus, int dev)
{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+
/* If there is no link, then there is no device */
if (bus->number != pp->root_bus_nr) {
- if (!dw_pcie_link_up(pp))
+ if (!dw_pcie_link_up(pci))
return 0;
}
@@ -718,70 +569,33 @@ static struct pci_ops dw_pcie_ops = {
void dw_pcie_setup_rc(struct pcie_port *pp)
{
u32 val;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ void __iomem *base = pci->dbi_base;
- /* set the number of lanes */
- dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
- val &= ~PORT_LINK_MODE_MASK;
- switch (pp->lanes) {
- case 1:
- val |= PORT_LINK_MODE_1_LANES;
- break;
- case 2:
- val |= PORT_LINK_MODE_2_LANES;
- break;
- case 4:
- val |= PORT_LINK_MODE_4_LANES;
- break;
- case 8:
- val |= PORT_LINK_MODE_8_LANES;
- break;
- default:
- dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);
- return;
- }
- dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
-
- /* set link width speed control register */
- dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
- val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
- switch (pp->lanes) {
- case 1:
- val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
- break;
- case 2:
- val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
- break;
- case 4:
- val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
- break;
- case 8:
- val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
- break;
- }
- dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ dw_pcie_setup(pci);
/* setup RC BARs */
- dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
- dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 0x00000004);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x4, 0x00000000);
/* setup interrupt pins */
- dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
+ dw_pcie_read_dbi(pci, base, PCI_INTERRUPT_LINE, 0x4, &val);
val &= 0xffff00ff;
val |= 0x00000100;
- dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
+ dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_LINE, 0x4, val);
/* setup bus numbers */
- dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
+ dw_pcie_read_dbi(pci, base, PCI_PRIMARY_BUS, 0x4, &val);
val &= 0xff000000;
val |= 0x00010100;
- dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
+ dw_pcie_write_dbi(pci, base, PCI_PRIMARY_BUS, 0x4, val);
/* setup command register */
- dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
+ dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4, &val);
val &= 0xffff0000;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
- dw_pcie_writel_rc(pp, val, PCI_COMMAND);
+ dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val);
/*
* If the platform provides ->rd_other_conf, it means the platform
@@ -789,7 +603,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
* we should not program the ATU here.
*/
if (!pp->ops->rd_other_conf)
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+ dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
PCIE_ATU_TYPE_MEM, pp->mem_base,
pp->mem_bus_addr, pp->mem_size);
diff --git a/drivers/pci/controller/pcie-designware.c b/drivers/pci/controller/pcie-designware.c
index 12afce1..e52a020 100644
--- a/drivers/pci/controller/pcie-designware.c
+++ b/drivers/pci/controller/pcie-designware.c
@@ -1,5 +1,5 @@
/*
- * Synopsys Designware PCIe host controller driver
+ * Synopsys Designware PCIe controller driver
*
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -11,73 +11,14 @@
* published by the Free Software Foundation.
*/
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/msi.h>
-#include <linux/of_address.h>
-#include <linux/of_pci.h>
+#include <linux/of.h>
#include <linux/pci.h>
-#include <linux/pci_regs.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
#include <linux/delay.h>
#include "pcie-designware.h"
-/* Synopsis specific PCIE configuration registers */
-#define PCIE_PORT_LINK_CONTROL 0x710
-#define PORT_LINK_MODE_MASK (0x3f << 16)
-#define PORT_LINK_MODE_1_LANES (0x1 << 16)
-#define PORT_LINK_MODE_2_LANES (0x3 << 16)
-#define PORT_LINK_MODE_4_LANES (0x7 << 16)
-#define PORT_LINK_MODE_8_LANES (0xf << 16)
-
-#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
-#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
-#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
-#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
-#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
-#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
-#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
-
-#define PCIE_MSI_ADDR_LO 0x820
-#define PCIE_MSI_ADDR_HI 0x824
-#define PCIE_MSI_INTR0_ENABLE 0x828
-#define PCIE_MSI_INTR0_MASK 0x82C
-#define PCIE_MSI_INTR0_STATUS 0x830
-
-#define PCIE_ATU_VIEWPORT 0x900
-#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
-#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
-#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
-#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
-#define PCIE_ATU_CR1 0x904
-#define PCIE_ATU_TYPE_MEM (0x0 << 0)
-#define PCIE_ATU_TYPE_IO (0x2 << 0)
-#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
-#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
-#define PCIE_ATU_CR2 0x908
-#define PCIE_ATU_ENABLE (0x1 << 31)
-#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
-#define PCIE_ATU_LOWER_BASE 0x90C
-#define PCIE_ATU_UPPER_BASE 0x910
-#define PCIE_ATU_LIMIT 0x914
-#define PCIE_ATU_LOWER_TARGET 0x918
-#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
-#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
-#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
-#define PCIE_ATU_UPPER_TARGET 0x91C
-
-/* PCIe Port Logic registers */
-#define PLR_OFFSET 0x700
-#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
-#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
-
-static struct pci_ops dw_pcie_ops;
-
-int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
+int dw_pcie_read(void __iomem *addr, int size, u32 *val)
{
if ((uintptr_t)addr & (size - 1)) {
*val = 0;
@@ -98,7 +39,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
return PCIBIOS_SUCCESSFUL;
}
-int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
+int dw_pcie_write(void __iomem *addr, int size, u32 val)
{
if ((uintptr_t)addr & (size - 1))
return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -115,614 +56,110 @@ int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
return PCIBIOS_SUCCESSFUL;
}
-static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
-{
- if (pp->ops->readl_rc)
- pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
- else
- *val = readl(pp->dbi_base + reg);
-}
-
-static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
-{
- if (pp->ops->writel_rc)
- pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
- else
- writel(val, pp->dbi_base + reg);
-}
-
-static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
- u32 *val)
-{
- if (pp->ops->rd_own_conf)
- return pp->ops->rd_own_conf(pp, where, size, val);
-
- return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
-}
-
-static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
- u32 val)
+void dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, int size, u32 *val)
{
- if (pp->ops->wr_own_conf)
- return pp->ops->wr_own_conf(pp, where, size, val);
-
- return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
-}
-
-static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
- int type, u64 cpu_addr, u64 pci_addr, u32 size)
-{
- u32 val;
-
- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
- PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
- PCIE_ATU_LIMIT);
- dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
- dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
- dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+ int ret;
- /*
- * Make sure ATU enable takes effect before any subsequent config
- * and I/O accesses.
- */
- dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
-}
-
-static struct irq_chip dw_msi_irq_chip = {
- .name = "PCI-MSI",
- .irq_enable = pci_msi_unmask_irq,
- .irq_disable = pci_msi_mask_irq,
- .irq_mask = pci_msi_mask_irq,
- .irq_unmask = pci_msi_unmask_irq,
-};
-
-/* MSI int handler */
-irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
-{
- unsigned long val;
- int i, pos, irq;
- irqreturn_t ret = IRQ_NONE;
-
- for (i = 0; i < MAX_MSI_CTRLS; i++) {
- dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
- (u32 *)&val);
- if (val) {
- ret = IRQ_HANDLED;
- pos = 0;
- while ((pos = find_next_bit(&val, 32, pos)) != 32) {
- irq = irq_find_mapping(pp->irq_domain,
- i * 32 + pos);
- dw_pcie_wr_own_conf(pp,
- PCIE_MSI_INTR0_STATUS + i * 12,
- 4, 1 << pos);
- generic_handle_irq(irq);
- pos++;
- }
- }
+ if (pci->ops->read_dbi) {
+ pci->ops->read_dbi(pci, base + reg, size, val);
+ return;
}
- return ret;
-}
-
-void dw_pcie_msi_init(struct pcie_port *pp)
-{
- u64 msi_target;
-
- pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
- msi_target = virt_to_phys((void *)pp->msi_data);
-
- /* program the msi_data */
- dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
- (u32)(msi_target & 0xffffffff));
- dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
- (u32)(msi_target >> 32 & 0xffffffff));
-}
-
-static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
-{
- unsigned int res, bit, val;
-
- res = (irq / 32) * 12;
- bit = irq % 32;
- dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
- val &= ~(1 << bit);
- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
+ ret = dw_pcie_read(base + reg, size, val);
+ if (ret)
+ dev_err(pci->dev, "read DBI address failed\n");
}
-static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
- unsigned int nvec, unsigned int pos)
+void dw_pcie_write_dbi(struct dw_pcie *pci, void *base, u32 reg,
+ int size, u32 val)
{
- unsigned int i;
+ int ret;
- for (i = 0; i < nvec; i++) {
- irq_set_msi_desc_off(irq_base, i, NULL);
- /* Disable corresponding interrupt on MSI controller */
- if (pp->ops->msi_clear_irq)
- pp->ops->msi_clear_irq(pp, pos + i);
- else
- dw_pcie_msi_clear_irq(pp, pos + i);
+ if (pci->ops->write_dbi) {
+ pci->ops->write_dbi(pci, base + reg, size, val);
+ return;
}
- bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
-}
-
-static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
-{
- unsigned int res, bit, val;
-
- res = (irq / 32) * 12;
- bit = irq % 32;
- dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
- val |= 1 << bit;
- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
+ ret = dw_pcie_write(base + reg, size, val);
+ if (ret)
+ dev_err(pci->dev, "write DBI address failed\n");
}
-static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
+void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
+ int type, u64 cpu_addr, u64 pci_addr,
+ u32 size)
{
- int irq, pos0, i;
- struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(desc);
-
- pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
- order_base_2(no_irqs));
- if (pos0 < 0)
- goto no_valid_irq;
-
- irq = irq_find_mapping(pp->irq_domain, pos0);
- if (!irq)
- goto no_valid_irq;
+ u32 val;
+ void __iomem *base = pci->dbi_base;
+
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
+ PCIE_ATU_REGION_OUTBOUND | index);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4,
+ lower_32_bits(cpu_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4,
+ upper_32_bits(cpu_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4,
+ lower_32_bits(cpu_addr + size - 1));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
+ lower_32_bits(pci_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
+ upper_32_bits(pci_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4, PCIE_ATU_ENABLE);
/*
- * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
- * descs so there is no need to allocate descs here. We can therefore
- * assume that if irq_find_mapping above returns non-zero, then the
- * descs are also successfully allocated.
+ * Make sure ATU enable takes effect before any subsequent config
+ * and I/O accesses.
*/
-
- for (i = 0; i < no_irqs; i++) {
- if (irq_set_msi_desc_off(irq, i, desc) != 0) {
- clear_irq_range(pp, irq, i, pos0);
- goto no_valid_irq;
- }
- /*Enable corresponding interrupt in MSI interrupt controller */
- if (pp->ops->msi_set_irq)
- pp->ops->msi_set_irq(pp, pos0 + i);
- else
- dw_pcie_msi_set_irq(pp, pos0 + i);
- }
-
- *pos = pos0;
- desc->nvec_used = no_irqs;
- desc->msi_attrib.multiple = order_base_2(no_irqs);
-
- return irq;
-
-no_valid_irq:
- *pos = pos0;
- return -ENOSPC;
-}
-
-static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
-{
- struct msi_msg msg;
- u64 msi_target;
-
- if (pp->ops->get_msi_addr)
- msi_target = pp->ops->get_msi_addr(pp);
- else
- msi_target = virt_to_phys((void *)pp->msi_data);
-
- msg.address_lo = (u32)(msi_target & 0xffffffff);
- msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
-
- if (pp->ops->get_msi_data)
- msg.data = pp->ops->get_msi_data(pp, pos);
- else
- msg.data = pos;
-
- pci_write_msi_msg(irq, &msg);
-}
-
-static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
- struct msi_desc *desc)
-{
- int irq, pos;
- struct pcie_port *pp = pdev->bus->sysdata;
-
- if (desc->msi_attrib.is_msix)
- return -EINVAL;
-
- irq = assign_irq(1, desc, &pos);
- if (irq < 0)
- return irq;
-
- dw_msi_setup_msg(pp, irq, pos);
-
- return 0;
+ dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4, &val);
}
-static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
- int nvec, int type)
-{
-#ifdef CONFIG_PCI_MSI
- int irq, pos;
- struct msi_desc *desc;
- struct pcie_port *pp = pdev->bus->sysdata;
-
- /* MSI-X interrupts are not supported */
- if (type == PCI_CAP_ID_MSIX)
- return -EINVAL;
-
- WARN_ON(!list_is_singular(&pdev->dev.msi_list));
- desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
-
- irq = assign_irq(nvec, desc, &pos);
- if (irq < 0)
- return irq;
-
- dw_msi_setup_msg(pp, irq, pos);
-
- return 0;
-#else
- return -EINVAL;
-#endif
-}
-
-static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
-{
- struct irq_data *data = irq_get_irq_data(irq);
- struct msi_desc *msi = irq_data_get_msi_desc(data);
- struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
-
- clear_irq_range(pp, irq, 1, data->hwirq);
-}
-
-static struct msi_controller dw_pcie_msi_chip = {
- .setup_irq = dw_msi_setup_irq,
- .setup_irqs = dw_msi_setup_irqs,
- .teardown_irq = dw_msi_teardown_irq,
-};
-
-int dw_pcie_wait_for_link(struct pcie_port *pp)
+int dw_pcie_wait_for_link(struct dw_pcie *pci)
{
int retries;
/* check if the link is up or not */
for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
- if (dw_pcie_link_up(pp)) {
- dev_info(pp->dev, "link up\n");
+ if (dw_pcie_link_up(pci)) {
+ dev_info(pci->dev, "link up\n");
return 0;
}
usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
}
- dev_err(pp->dev, "phy link never came up\n");
+ dev_err(pci->dev, "phy link never came up\n");
return -ETIMEDOUT;
}
-int dw_pcie_link_up(struct pcie_port *pp)
+int dw_pcie_link_up(struct dw_pcie *pci)
{
u32 val;
- if (pp->ops->link_up)
- return pp->ops->link_up(pp);
+ if (pci->ops->link_up)
+ return pci->ops->link_up(pci);
- val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
+ val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
return val & PCIE_PHY_DEBUG_R1_LINK_UP;
}
-static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
- irq_hw_number_t hwirq)
+void dw_pcie_setup(struct dw_pcie *pci)
{
- irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
- irq_set_chip_data(irq, domain->host_data);
-
- return 0;
-}
-
-static const struct irq_domain_ops msi_domain_ops = {
- .map = dw_pcie_msi_map,
-};
-
-int dw_pcie_host_init(struct pcie_port *pp)
-{
- struct device_node *np = pp->dev->of_node;
- struct platform_device *pdev = to_platform_device(pp->dev);
- struct pci_bus *bus, *child;
- struct resource *cfg_res;
- int i, ret;
- LIST_HEAD(res);
- struct resource_entry *win;
-
- cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
- if (cfg_res) {
- pp->cfg0_size = resource_size(cfg_res)/2;
- pp->cfg1_size = resource_size(cfg_res)/2;
- pp->cfg0_base = cfg_res->start;
- pp->cfg1_base = cfg_res->start + pp->cfg0_size;
- } else if (!pp->va_cfg0_base) {
- dev_err(pp->dev, "missing *config* reg space\n");
- }
-
- ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
- if (ret)
- return ret;
-
- ret = devm_request_pci_bus_resources(&pdev->dev, &res);
- if (ret)
- goto error;
-
- /* Get the I/O and memory ranges from DT */
- resource_list_for_each_entry(win, &res) {
- switch (resource_type(win->res)) {
- case IORESOURCE_IO:
- pp->io = win->res;
- pp->io->name = "I/O";
- pp->io_size = resource_size(pp->io);
- pp->io_bus_addr = pp->io->start - win->offset;
- ret = pci_remap_iospace(pp->io, pp->io_base);
- if (ret)
- dev_warn(pp->dev, "error %d: failed to map resource %pR\n",
- ret, pp->io);
- break;
- case IORESOURCE_MEM:
- pp->mem = win->res;
- pp->mem->name = "MEM";
- pp->mem_size = resource_size(pp->mem);
- pp->mem_bus_addr = pp->mem->start - win->offset;
- break;
- case 0:
- pp->cfg = win->res;
- pp->cfg0_size = resource_size(pp->cfg)/2;
- pp->cfg1_size = resource_size(pp->cfg)/2;
- pp->cfg0_base = pp->cfg->start;
- pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
- break;
- case IORESOURCE_BUS:
- pp->busn = win->res;
- break;
- }
- }
-
- if (!pp->dbi_base) {
- pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
- resource_size(pp->cfg));
- if (!pp->dbi_base) {
- dev_err(pp->dev, "error with ioremap\n");
- ret = -ENOMEM;
- goto error;
- }
- }
-
- pp->mem_base = pp->mem->start;
-
- if (!pp->va_cfg0_base) {
- pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
- pp->cfg0_size);
- if (!pp->va_cfg0_base) {
- dev_err(pp->dev, "error with ioremap in function\n");
- ret = -ENOMEM;
- goto error;
- }
- }
-
- if (!pp->va_cfg1_base) {
- pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
- pp->cfg1_size);
- if (!pp->va_cfg1_base) {
- dev_err(pp->dev, "error with ioremap\n");
- ret = -ENOMEM;
- goto error;
- }
- }
+ u32 val;
+ int ret;
+ void __iomem *base = pci->dbi_base;
+ struct device *dev = pci->dev;
+ struct device_node *np = dev->of_node;
- ret = of_property_read_u32(np, "num-lanes", &pp->lanes);
+ ret = of_property_read_u32(np, "num-lanes", &pci->lanes);
if (ret)
- pp->lanes = 0;
-
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- if (!pp->ops->msi_host_init) {
- pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
- MAX_MSI_IRQS, &msi_domain_ops,
- &dw_pcie_msi_chip);
- if (!pp->irq_domain) {
- dev_err(pp->dev, "irq domain init failed\n");
- ret = -ENXIO;
- goto error;
- }
-
- for (i = 0; i < MAX_MSI_IRQS; i++)
- irq_create_mapping(pp->irq_domain, i);
- } else {
- ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
- if (ret < 0)
- goto error;
- }
- }
-
- if (pp->ops->host_init)
- pp->ops->host_init(pp);
-
- pp->root_bus_nr = pp->busn->start;
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
- &dw_pcie_ops, pp, &res,
- &dw_pcie_msi_chip);
- dw_pcie_msi_chip.dev = pp->dev;
- } else
- bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
- pp, &res);
- if (!bus) {
- ret = -ENOMEM;
- goto error;
- }
-
- if (pp->ops->scan_bus)
- pp->ops->scan_bus(pp);
-
-#ifdef CONFIG_ARM
- /* support old dtbs that incorrectly describe IRQs */
- pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
-#endif
-
- pci_bus_size_bridges(bus);
- pci_bus_assign_resources(bus);
-
- list_for_each_entry(child, &bus->children, node)
- pcie_bus_configure_settings(child);
-
- pci_bus_add_devices(bus);
- return 0;
-
-error:
- pci_free_resource_list(&res);
- return ret;
-}
-
-static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
- u32 devfn, int where, int size, u32 *val)
-{
- int ret, type;
- u32 busdev, cfg_size;
- u64 cpu_addr;
- void __iomem *va_cfg_base;
-
- if (pp->ops->rd_other_conf)
- return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
-
- busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
- PCIE_ATU_FUNC(PCI_FUNC(devfn));
-
- if (bus->parent->number == pp->root_bus_nr) {
- type = PCIE_ATU_TYPE_CFG0;
- cpu_addr = pp->cfg0_base;
- cfg_size = pp->cfg0_size;
- va_cfg_base = pp->va_cfg0_base;
- } else {
- type = PCIE_ATU_TYPE_CFG1;
- cpu_addr = pp->cfg1_base;
- cfg_size = pp->cfg1_size;
- va_cfg_base = pp->va_cfg1_base;
- }
-
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
- type, cpu_addr,
- busdev, cfg_size);
- ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_IO, pp->io_base,
- pp->io_bus_addr, pp->io_size);
-
- return ret;
-}
-
-static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
- u32 devfn, int where, int size, u32 val)
-{
- int ret, type;
- u32 busdev, cfg_size;
- u64 cpu_addr;
- void __iomem *va_cfg_base;
-
- if (pp->ops->wr_other_conf)
- return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
-
- busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
- PCIE_ATU_FUNC(PCI_FUNC(devfn));
-
- if (bus->parent->number == pp->root_bus_nr) {
- type = PCIE_ATU_TYPE_CFG0;
- cpu_addr = pp->cfg0_base;
- cfg_size = pp->cfg0_size;
- va_cfg_base = pp->va_cfg0_base;
- } else {
- type = PCIE_ATU_TYPE_CFG1;
- cpu_addr = pp->cfg1_base;
- cfg_size = pp->cfg1_size;
- va_cfg_base = pp->va_cfg1_base;
- }
-
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
- type, cpu_addr,
- busdev, cfg_size);
- ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_IO, pp->io_base,
- pp->io_bus_addr, pp->io_size);
-
- return ret;
-}
-
-static int dw_pcie_valid_config(struct pcie_port *pp,
- struct pci_bus *bus, int dev)
-{
- /* If there is no link, then there is no device */
- if (bus->number != pp->root_bus_nr) {
- if (!dw_pcie_link_up(pp))
- return 0;
- }
-
- /* access only one slot on each root port */
- if (bus->number == pp->root_bus_nr && dev > 0)
- return 0;
-
- /*
- * do not read more than one device on the bus directly attached
- * to RC's (Virtual Bridge's) DS side.
- */
- if (bus->primary == pp->root_bus_nr && dev > 0)
- return 0;
-
- return 1;
-}
-
-static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
- int size, u32 *val)
-{
- struct pcie_port *pp = bus->sysdata;
-
- if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- if (bus->number == pp->root_bus_nr)
- return dw_pcie_rd_own_conf(pp, where, size, val);
-
- return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
-}
-
-static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
- int where, int size, u32 val)
-{
- struct pcie_port *pp = bus->sysdata;
-
- if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- if (bus->number == pp->root_bus_nr)
- return dw_pcie_wr_own_conf(pp, where, size, val);
-
- return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
-}
-
-static struct pci_ops dw_pcie_ops = {
- .read = dw_pcie_rd_conf,
- .write = dw_pcie_wr_conf,
-};
-
-void dw_pcie_setup_rc(struct pcie_port *pp)
-{
- u32 val;
+ pci->lanes = 0;
/* set the number of lanes */
- dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
+ dw_pcie_read_dbi(pci, base, PCIE_PORT_LINK_CONTROL, 0x4, &val);
val &= ~PORT_LINK_MODE_MASK;
- switch (pp->lanes) {
+ switch (pci->lanes) {
case 1:
val |= PORT_LINK_MODE_1_LANES;
break;
@@ -736,15 +173,15 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
val |= PORT_LINK_MODE_8_LANES;
break;
default:
- dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);
+ dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->lanes);
return;
}
- dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
+ dw_pcie_write_dbi(pci, base, PCIE_PORT_LINK_CONTROL, 0x4, val);
/* set link width speed control register */
- dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
+ dw_pcie_read_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4, &val);
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
- switch (pp->lanes) {
+ switch (pci->lanes) {
case 1:
val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
break;
@@ -758,49 +195,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
break;
}
- dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
-
- /* setup RC BARs */
- dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
- dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
-
- /* setup interrupt pins */
- dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
- val &= 0xffff00ff;
- val |= 0x00000100;
- dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
-
- /* setup bus numbers */
- dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
- val &= 0xff000000;
- val |= 0x00010100;
- dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
-
- /* setup command register */
- dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
- val &= 0xffff0000;
- val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
- dw_pcie_writel_rc(pp, val, PCI_COMMAND);
-
- /*
- * If the platform provides ->rd_other_conf, it means the platform
- * uses its own address translation component rather than ATU, so
- * we should not program the ATU here.
- */
- if (!pp->ops->rd_other_conf)
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_TYPE_MEM, pp->mem_base,
- pp->mem_bus_addr, pp->mem_size);
-
- dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
-
- /* program correct class for RC */
- dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
-
- dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
- val |= PORT_LOGIC_SPEED_CHANGE;
- dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
+ dw_pcie_write_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4, val);
}
MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
diff --git a/drivers/pci/controller/pcie-designware.h b/drivers/pci/controller/pcie-designware.h
index f437f9b..53eaa50 100644
--- a/drivers/pci/controller/pcie-designware.h
+++ b/drivers/pci/controller/pcie-designware.h
@@ -14,6 +14,59 @@
#ifndef _PCIE_DESIGNWARE_H
#define _PCIE_DESIGNWARE_H
+#include <linux/irq.h>
+#include <linux/msi.h>
+#include <linux/pci.h>
+
+/* Synopsis specific PCIE configuration registers */
+#define PCIE_PORT_LINK_CONTROL 0x710
+#define PORT_LINK_MODE_MASK (0x3f << 16)
+#define PORT_LINK_MODE_1_LANES (0x1 << 16)
+#define PORT_LINK_MODE_2_LANES (0x3 << 16)
+#define PORT_LINK_MODE_4_LANES (0x7 << 16)
+#define PORT_LINK_MODE_8_LANES (0xf << 16)
+
+#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
+#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
+#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
+#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
+#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
+#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
+#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
+
+#define PCIE_MSI_ADDR_LO 0x820
+#define PCIE_MSI_ADDR_HI 0x824
+#define PCIE_MSI_INTR0_ENABLE 0x828
+#define PCIE_MSI_INTR0_MASK 0x82C
+#define PCIE_MSI_INTR0_STATUS 0x830
+
+#define PCIE_ATU_VIEWPORT 0x900
+#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
+#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
+#define PCIE_ATU_CR1 0x904
+#define PCIE_ATU_TYPE_MEM (0x0 << 0)
+#define PCIE_ATU_TYPE_IO (0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_CR2 0x908
+#define PCIE_ATU_ENABLE (0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
+#define PCIE_ATU_LOWER_BASE 0x90C
+#define PCIE_ATU_UPPER_BASE 0x910
+#define PCIE_ATU_LIMIT 0x914
+#define PCIE_ATU_LOWER_TARGET 0x918
+#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET 0x91C
+
+/* PCIe Port Logic registers */
+#define PLR_OFFSET 0x700
+#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
+#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
+
/*
* Maximum number of MSI IRQs can be 256 per controller. But keep
* it 32 as of now. Probably we will never need more than 32. If needed,
@@ -27,10 +80,34 @@
#define LINK_WAIT_USLEEP_MIN 90000
#define LINK_WAIT_USLEEP_MAX 100000
+struct dw_pcie;
+struct pcie_port;
+
+enum dw_pcie_device_mode {
+ DW_PCIE_UNKNOWN_TYPE,
+ DW_PCIE_EP_TYPE,
+ DW_PCIE_LEG_EP_TYPE,
+ DW_PCIE_RC_TYPE,
+};
+
+struct dw_pcie_host_ops {
+ int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
+ int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
+ int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
+ unsigned int devfn, int where, int size, u32 *val);
+ int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
+ unsigned int devfn, int where, int size, u32 val);
+ void (*host_init)(struct pcie_port *pp);
+ void (*msi_set_irq)(struct pcie_port *pp, int irq);
+ void (*msi_clear_irq)(struct pcie_port *pp, int irq);
+ phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
+ u32 (*get_msi_data)(struct pcie_port *pp, int pos);
+ void (*scan_bus)(struct pcie_port *pp);
+ int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
+};
+
struct pcie_port {
- struct device *dev;
u8 root_bus_nr;
- void __iomem *dbi_base;
u64 cfg0_base;
void __iomem *va_cfg0_base;
u32 cfg0_size;
@@ -48,42 +125,69 @@ struct pcie_port {
struct resource *mem;
struct resource *busn;
int irq;
- u32 lanes;
- struct pcie_host_ops *ops;
+ const struct dw_pcie_host_ops *ops;
int msi_irq;
struct irq_domain *irq_domain;
unsigned long msi_data;
DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
};
-struct pcie_host_ops {
- void (*readl_rc)(struct pcie_port *pp,
- void __iomem *dbi_base, u32 *val);
- void (*writel_rc)(struct pcie_port *pp,
- u32 val, void __iomem *dbi_base);
- int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
- int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
- int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
- unsigned int devfn, int where, int size, u32 *val);
- int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
- unsigned int devfn, int where, int size, u32 val);
- int (*link_up)(struct pcie_port *pp);
- void (*host_init)(struct pcie_port *pp);
- void (*msi_set_irq)(struct pcie_port *pp, int irq);
- void (*msi_clear_irq)(struct pcie_port *pp, int irq);
- phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
- u32 (*get_msi_data)(struct pcie_port *pp, int pos);
- void (*scan_bus)(struct pcie_port *pp);
- int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
+struct dw_pcie_ops {
+ void (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, int size,
+ u32 *val);
+ void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base,
+ int size, u32 val);
+ int (*link_up)(struct dw_pcie *pcie);
+ int (*start_link)(struct dw_pcie *pcie);
+ void (*stop_link)(struct dw_pcie *pcie);
};
-int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);
-int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
+struct dw_pcie {
+ struct device *dev;
+ void __iomem *dbi_base;
+ void __iomem *dbi_base2;
+ u32 lanes;
+ const struct dw_pcie_ops *ops;
+ struct pcie_port pp;
+};
+
+#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
+
+int dw_pcie_wait_for_link(struct dw_pcie *pci);
+int dw_pcie_link_up(struct dw_pcie *pci);
+void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
+ int type, u64 cpu_addr, u64 pci_addr,
+ u32 size);
+int dw_pcie_read(void __iomem *addr, int size, u32 *val);
+int dw_pcie_write(void __iomem *addr, int size, u32 val);
+void dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, int size, u32 *val);
+void dw_pcie_write_dbi(struct dw_pcie *pci, void *base, u32 reg,
+ int size, u32 val);
+void dw_pcie_setup(struct dw_pcie *pci);
+
+#ifdef CONFIG_PCIE_DW_HOST
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
void dw_pcie_msi_init(struct pcie_port *pp);
-int dw_pcie_wait_for_link(struct pcie_port *pp);
-int dw_pcie_link_up(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
int dw_pcie_host_init(struct pcie_port *pp);
+#else
+static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
+{
+ return IRQ_NONE;
+}
+
+static inline void dw_pcie_msi_init(struct pcie_port *pp)
+{
+}
+
+static inline void dw_pcie_setup_rc(struct pcie_port *pp)
+{
+}
+static inline int dw_pcie_host_init(struct pcie_port *pp)
+{
+ return 0;
+}
+#endif
#endif /* _PCIE_DESIGNWARE_H */
--
1.7.9.5
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