* [PATCH 4/7] phy: meson: add USB2 PHY support for Meson8b and GXBB
From: Martin Blumenstingl @ 2016-09-14 21:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473842240.6816.1.camel@pengutronix.de>
On Wed, Sep 14, 2016 at 10:37 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> Am Dienstag, den 13.09.2016, 17:59 -0700 schrieb Kevin Hilman:
>> Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
>>
>> > On Tue, Sep 13, 2016 at 5:28 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
>>
>> [...]
>>
>> >>> I added Philipp and Hans to this thread - maybe they can comment on this.
>> >>> To sum it up, our problem is:
>> >>> - there are two separate USB PHYs on Meson GXBB
>> >>> - both are sharing the same reset line (provided by the reset-meson driver)
>> >>> - during initialization of the PHYs we must only call
>> >>> reset_control_reset(rstc) once (if we do it for the first *and* second
>> >>> PHY then the first PHY gets confused once the second PHY uses the
>> >>> reset because the first PHY's state is reset as well)
>> >>
>> >> If you have an initially asserted reset line and you can enable the
>> >> first module by deasserting the reset via reset_control_deassert (and
>> >> reset_control_assert to signal when the module may be disabled again
>> >> after use), shared resets are for you.
>> >>
>> >> If you need a reset pulse or have no direct control over the reset line,
>> >> (device_reset), the reset framework currently has no solution for this.
>> >> The ugly thing about reset_control_once would be that it can't re-reset
>> >> modules when unloading and reloading driver modules.
>> >
>> > The corresponding reset driver in question is reset-meson, which only
>> > implements reset (assert/deassert are not implemented). However, I
>> > don't know if this is due to hardware design.
>> > I think the hardware implements the latter, but maybe Neil can give
>> > more information here (I currently don't have access to my board so I
>> > cannot test how the hardware actually behaves).
>>
>> It's implemented that way because the hardware only supports a reset
>> pulse.
>
> Would it be possible to bring down both PHYs drivers, pull the reset
> line once, and then bring the drivers back up again?
I guess that this is the rmmod case: I haven't tested it yet but that
should work (even with the current code and .dts)
^ permalink raw reply
* [PATCH v3 2/3] clk: xgene: Add PMD clock
From: Hoan Tran @ 2016-09-14 21:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914205541.GB7243@codeaurora.org>
On Wed, Sep 14, 2016 at 1:55 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 09/12, Hoan Tran wrote:
>> Add X-Gene PMD clock support.
>>
>> PMD clock is implemented for a single register field.
>> Output rate = parent_rate * (denominator - scale) / denominator
>> with
>> - denominator = bitmask of register field + 1
>> - scale = values of register field
>>
>> For example, for bitmask is 0x7, denominator will be 8 and scale
>> will be computed and programmed accordingly.
>>
>> Signed-off-by: Hoan Tran <hotran@apm.com>
>> ---
>
> Applied to clk-next
Thanks, Stephen !
Hoan
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 3/3] arm64: dts: xgene: Add DT node for APM X-Gene 2 CPU clocks
From: Hoan Tran @ 2016-09-14 21:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914205556.GC7243@codeaurora.org>
Hi Stephen,
On Wed, Sep 14, 2016 at 1:55 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 09/12, Hoan Tran wrote:
>> Add DT nodes to enable APM X-Gene 2 CPU clocks.
>>
>> Signed-off-by: Hoan Tran <hotran@apm.com>
>> ---
>
> This can go through arm-soc? I'm not applying this.
Yes, I can go through arm-soc.
Thanks
Hoan
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 3/3] Revert "ARM: dts: dra7: Move to operating-points-v2 table"
From: Dave Gerlach @ 2016-09-14 20:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914205717.21975-1-d-gerlach@ti.com>
This reverts commit f80bc97fd0a9711ef11bdb3e63c2c01115a82c47.
The original commit updated the cpufreq operating points tables for
dra7xx but was merged before the driver making use of the node was
merged, which breaks the existing cpufreq implementation on the system,
so revert the patch until the ti-cpufreq driver is merged.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 26 +++++---------------------
arch/arm/boot/dts/dra74x.dtsi | 1 -
2 files changed, 5 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d9bfb94a2992..a0fbbf18d50c 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -82,9 +82,11 @@
compatible = "arm,cortex-a15";
reg = <0>;
- operating-points-v2 = <&cpu0_opp_table>;
- ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>;
- ti,syscon-rev = <&scm_wkup 0x204>;
+ operating-points = <
+ /* kHz uV */
+ 1000000 1060000
+ 1176000 1160000
+ >;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
@@ -98,24 +100,6 @@
};
};
- cpu0_opp_table: opp_table0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp_nom at 1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <1060000 850000 1150000>;
- opp-supported-hw = <0xFF 0x01>;
- opp-suspend;
- };
-
- opp_od at 1176000000 {
- opp-hz = /bits/ 64 <1176000000>;
- opp-microvolt = <1160000 885000 1160000>;
- opp-supported-hw = <0xFF 0x02>;
- };
- };
-
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 8987b3e180a1..0a78347e6615 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -17,7 +17,6 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
- operating-points-v2 = <&cpu0_opp_table>;
};
};
--
2.9.3
^ permalink raw reply related
* [PATCH 2/3] Revert "ARM: dts: am33xx: Move to operating-points-v2 table and ti-cpufreq driver"
From: Dave Gerlach @ 2016-09-14 20:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914205717.21975-1-d-gerlach@ti.com>
This reverts commit 4317be1162108bcdf50dc53dfb48eac94dcff25c.
The original commit updated the cpufreq operating points tables for
am33xx but was merged before the driver making use of the node was
merged, which breaks the existing cpufreq implementation on the system,
so revert the patch until the ti-cpufreq driver is merged.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/boot/dts/am33xx.dtsi | 88 +++++++------------------------------------
1 file changed, 13 insertions(+), 75 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 98748c61ed99..9e214bfd32d2 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -45,9 +45,19 @@
device_type = "cpu";
reg = <0>;
- operating-points-v2 = <&cpu0_opp_table>;
- ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>;
- ti,syscon-rev = <&scm_conf 0x600>;
+ /*
+ * To consider voltage drop between PMIC and SoC,
+ * tolerance value is reduced to 2% from 4% and
+ * voltage value is increased as a precaution.
+ */
+ operating-points = <
+ /* kHz uV */
+ 720000 1285000
+ 600000 1225000
+ 500000 1125000
+ 275000 1125000
+ >;
+ voltage-tolerance = <2>; /* 2 percentage */
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
@@ -56,78 +66,6 @@
};
};
- cpu0_opp_table: opp_table0 {
- compatible = "operating-points-v2";
-
- /*
- * The three following nodes are marked with opp-suspend
- * because the can not be enabled simultaneously on a
- * single SoC.
- */
- opp50 at 300000000 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <950000 931000 969000>;
- opp-supported-hw = <0x06 0x0010>;
- opp-suspend;
- };
-
- opp100 at 275000000 {
- opp-hz = /bits/ 64 <275000000>;
- opp-microvolt = <1100000 1078000 1122000>;
- opp-supported-hw = <0x01 0x00FF>;
- opp-suspend;
- };
-
- opp100 at 300000000 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <1100000 1078000 1122000>;
- opp-supported-hw = <0x06 0x0020>;
- opp-suspend;
- };
-
- opp100 at 500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <1100000 1078000 1122000>;
- opp-supported-hw = <0x01 0xFFFF>;
- };
-
- opp100 at 600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1100000 1078000 1122000>;
- opp-supported-hw = <0x06 0x0040>;
- };
-
- opp120 at 600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1200000 1176000 1224000>;
- opp-supported-hw = <0x01 0xFFFF>;
- };
-
- opp120 at 720000000 {
- opp-hz = /bits/ 64 <720000000>;
- opp-microvolt = <1200000 1176000 1224000>;
- opp-supported-hw = <0x06 0x0080>;
- };
-
- oppturbo at 720000000 {
- opp-hz = /bits/ 64 <720000000>;
- opp-microvolt = <1260000 1234800 1285200>;
- opp-supported-hw = <0x01 0xFFFF>;
- };
-
- oppturbo at 800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <1260000 1234800 1285200>;
- opp-supported-hw = <0x06 0x0100>;
- };
-
- oppnitro at 1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <1325000 1298500 1351500>;
- opp-supported-hw = <0x04 0x0200>;
- };
- };
-
pmu {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
--
2.9.3
^ permalink raw reply related
* [PATCH 1/3] Revert "ARM: dts: am335x-boneblack: Enable 1GHz OPP for cpu"
From: Dave Gerlach @ 2016-09-14 20:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914205717.21975-1-d-gerlach@ti.com>
This reverts commit c36e6ec904876de1935b1d74d2d711e6f5ceb572.
The original commit updated the cpufreq operating points tables for
am335x-boneblack but was merged before the driver making use of the node
was merged, which breaks the existing cpufreq implementation on the
system, so revert the patch until the ti-cpufreq driver is merged.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/boot/dts/am335x-boneblack.dts | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index ca721670bd91..55c0e954b146 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -33,17 +33,6 @@
status = "okay";
};
-&cpu0_opp_table {
- /*
- * All PG 2.0 silicon may not support 1GHz but some of the early
- * BeagleBone Blacks have PG 2.0 silicon which is guaranteed
- * to support 1GHz OPP so enable it for PG 2.0 on this board.
- */
- oppnitro at 1000000000 {
- opp-supported-hw = <0x06 0x0100>;
- };
-};
-
&am33xx_pinmux {
nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
pinctrl-single,pins = <
--
2.9.3
^ permalink raw reply related
* [PATCH 0/3] ARM: dts: am33xx/dra7xx: Fix cpufreq regression
From: Dave Gerlach @ 2016-09-14 20:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
CPUFreq on am335x and dra7 platforms got broken by two things:
- Updated OPPv2 nodes in device tree were merged before driver to
handle them was accepted.
- OMAP platforms now use the new cpufreq-dt-platdev driver to create
cpufreq-dt platform device but non OMAP TI devices were not changed
over to this driver.
This series addresses the first issue listed above by reverting three of
the dts patches that got merged to restore OPPv1 tables. The second issue
is addressed by [1].
With both this series and that patch we will have the existing cpufreq
support restored on am335x and dra7xx.
Regards,
Dave
[1] http://marc.info/?l=linux-pm&m=147388573513082&w=2
Dave Gerlach (3):
Revert "ARM: dts: am335x-boneblack: Enable 1GHz OPP for cpu"
Revert "ARM: dts: am33xx: Move to operating-points-v2 table and
ti-cpufreq driver"
Revert "ARM: dts: dra7: Move to operating-points-v2 table"
arch/arm/boot/dts/am335x-boneblack.dts | 11 -----
arch/arm/boot/dts/am33xx.dtsi | 88 +++++-----------------------------
arch/arm/boot/dts/dra7.dtsi | 26 ++--------
arch/arm/boot/dts/dra74x.dtsi | 1 -
4 files changed, 18 insertions(+), 108 deletions(-)
--
2.9.3
^ permalink raw reply
* [PATCH v3 3/3] arm64: dts: xgene: Add DT node for APM X-Gene 2 CPU clocks
From: Stephen Boyd @ 2016-09-14 20:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473704605-28126-4-git-send-email-hotran@apm.com>
On 09/12, Hoan Tran wrote:
> Add DT nodes to enable APM X-Gene 2 CPU clocks.
>
> Signed-off-by: Hoan Tran <hotran@apm.com>
> ---
This can go through arm-soc? I'm not applying this.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 2/3] clk: xgene: Add PMD clock
From: Stephen Boyd @ 2016-09-14 20:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473704605-28126-3-git-send-email-hotran@apm.com>
On 09/12, Hoan Tran wrote:
> Add X-Gene PMD clock support.
>
> PMD clock is implemented for a single register field.
> Output rate = parent_rate * (denominator - scale) / denominator
> with
> - denominator = bitmask of register field + 1
> - scale = values of register field
>
> For example, for bitmask is 0x7, denominator will be 8 and scale
> will be computed and programmed accordingly.
>
> Signed-off-by: Hoan Tran <hotran@apm.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 1/3] Documentation: dtb: xgene: Add PMD clock binding
From: Stephen Boyd @ 2016-09-14 20:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473704605-28126-2-git-send-email-hotran@apm.com>
On 09/12, Hoan Tran wrote:
> Add APM X-Gene clock binding documentation for PMD clock.
>
> Signed-off-by: Hoan Tran <hotran@apm.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [kernel-hardening] [PATCH v3 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching
From: David Brown @ 2016-09-14 20:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473788797-10879-1-git-send-email-catalin.marinas@arm.com>
On Tue, Sep 13, 2016 at 06:46:30PM +0100, Catalin Marinas wrote:
>This is the third version of the arm64 PAN emulation using TTBR0_EL1
>switching. The series has not yet included the alternative nop patches
>from Mark Rutland, nor the empty_zero_page from Ard B. This will be done
>in a subsequent version once 4.9-rc1 is out (which will include Mark's
>alternative nop patches).
I've tested these with a bunch of reboots in both qemu and HiKey and
have not seen the efi failure.
David
^ permalink raw reply
* [PATCH] cpufreq: ti: Use generic platdev driver
From: Dave Gerlach @ 2016-09-14 20:41 UTC (permalink / raw)
To: linux-arm-kernel
Now that the cpufreq-dt-platdev is used to create the cpufreq-dt platform
device for all OMAP platforms and the platform code that did it
before has been removed, add ti,am33xx and ti,dra7xx to the machine list
in cpufreq-dt-platdev which had relied on the removed platform code to do
this previously.
Fixes: 7694ca6e1d6f ("cpufreq: omap: Use generic platdev driver")
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 0bb44d5b5df4..d5e8ba50f8a3 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -68,6 +68,8 @@ static const struct of_device_id machines[] __initconst = {
{ .compatible = "sigma,tango4" },
+ { .compatible = "ti,am33xx", },
+ { .compatible = "ti,dra7", },
{ .compatible = "ti,omap2", },
{ .compatible = "ti,omap3", },
{ .compatible = "ti,omap4", },
--
2.9.3
^ permalink raw reply related
* [PATCH v13 8/8] acpi/arm64: Add SBSA Generic Watchdog support in GTDT driver
From: fu.wei at linaro.org @ 2016-09-14 20:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473883781-9571-1-git-send-email-fu.wei@linaro.org>
From: Fu Wei <fu.wei@linaro.org>
This driver adds support for parsing SBSA Generic Watchdog timer
in GTDT, parse all info in SBSA Generic Watchdog Structure in GTDT,
and creating a platform device with that information.
This allows the operating system to obtain device data from the
resource of platform device. The platform device named "sbsa-gwdt"
can be used by the ARM SBSA Generic Watchdog driver.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
drivers/acpi/arm64/gtdt.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++
drivers/watchdog/Kconfig | 1 +
2 files changed, 88 insertions(+)
diff --git a/drivers/acpi/arm64/gtdt.c b/drivers/acpi/arm64/gtdt.c
index b6021db..6d9fdd3 100644
--- a/drivers/acpi/arm64/gtdt.c
+++ b/drivers/acpi/arm64/gtdt.c
@@ -14,6 +14,7 @@
#include <linux/acpi.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/platform_device.h>
#include <clocksource/arm_arch_timer.h>
@@ -220,3 +221,89 @@ int __init gtdt_arch_timer_mem_init(struct gt_block_data *data)
return index;
}
+
+/*
+ * Initialize a SBSA generic Watchdog platform device info from GTDT
+ */
+static int __init gtdt_import_sbsa_gwdt(struct acpi_gtdt_watchdog *wd,
+ int index)
+{
+ struct platform_device *pdev;
+ int irq = map_gt_gsi(wd->timer_interrupt, wd->timer_flags);
+ int no_irq = 1;
+
+ /*
+ * According to SBSA specification the size of refresh and control
+ * frames of SBSA Generic Watchdog is SZ_4K(Offset 0x000 ? 0xFFF).
+ */
+ struct resource res[] = {
+ DEFINE_RES_MEM(wd->control_frame_address, SZ_4K),
+ DEFINE_RES_MEM(wd->refresh_frame_address, SZ_4K),
+ DEFINE_RES_IRQ(irq),
+ };
+
+ pr_debug("found a Watchdog (0x%llx/0x%llx gsi:%u flags:0x%x).\n",
+ wd->refresh_frame_address, wd->control_frame_address,
+ wd->timer_interrupt, wd->timer_flags);
+
+ if (!(wd->refresh_frame_address && wd->control_frame_address)) {
+ pr_err(FW_BUG "failed to get the Watchdog base address.\n");
+ return -EINVAL;
+ }
+
+ if (!wd->timer_interrupt)
+ pr_warn(FW_BUG "failed to get the Watchdog interrupt.\n");
+ else if (irq <= 0)
+ pr_warn("failed to map the Watchdog interrupt.\n");
+ else
+ no_irq = 0;
+
+ /*
+ * Add a platform device named "sbsa-gwdt" to match the platform driver.
+ * "sbsa-gwdt": SBSA(Server Base System Architecture) Generic Watchdog
+ * The platform driver (like drivers/watchdog/sbsa_gwdt.c)can get device
+ * info below by matching this name.
+ */
+ pdev = platform_device_register_simple("sbsa-gwdt", index, res,
+ ARRAY_SIZE(res) - no_irq);
+ if (IS_ERR(pdev)) {
+ acpi_unregister_gsi(wd->timer_interrupt);
+ return PTR_ERR(pdev);
+ }
+
+ return 0;
+}
+
+static int __init gtdt_sbsa_gwdt_init(void)
+{
+ struct acpi_table_header *table;
+ void *platform_timer;
+ int index = 0;
+ int ret;
+
+ if (acpi_disabled)
+ return 0;
+
+ if (ACPI_FAILURE(acpi_get_table(ACPI_SIG_GTDT, 0, &table)))
+ return -EINVAL;
+
+ ret = acpi_gtdt_init(table);
+ if (ret <= 0)
+ return ret;
+
+ for_each_platform_timer(platform_timer) {
+ if (!is_watchdog(platform_timer))
+ continue;
+ ret = gtdt_import_sbsa_gwdt(platform_timer, index);
+ if (ret)
+ break;
+ index++;
+ }
+
+ if (index)
+ pr_info("found %d SBSA generic Watchdog(s).\n", index);
+
+ return ret;
+}
+
+device_initcall(gtdt_sbsa_gwdt_init);
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 1bffe00..341964a 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -205,6 +205,7 @@ config ARM_SBSA_WATCHDOG
tristate "ARM SBSA Generic Watchdog"
depends on ARM64
depends on ARM_ARCH_TIMER
+ depends on ACPI_GTDT || !ACPI
select WATCHDOG_CORE
help
ARM SBSA Generic Watchdog has two stage timeouts:
--
2.7.4
^ permalink raw reply related
* [PATCH v13 7/8] clocksource/drivers/arm_arch_timer: Add GTDT support for memory-mapped timer
From: fu.wei at linaro.org @ 2016-09-14 20:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473883781-9571-1-git-send-email-fu.wei@linaro.org>
From: Fu Wei <fu.wei@linaro.org>
The patch add memory-mapped timer register support by using the information
provided by the new GTDT driver of ACPI.
Also refactor original memory-mapped timer dt support for reusing some common
code.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
---
drivers/clocksource/arm_arch_timer.c | 238 +++++++++++++++++++++++++----------
1 file changed, 172 insertions(+), 66 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 0197ef9..ddca6e3 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -57,6 +57,7 @@
static unsigned arch_timers_present __initdata;
static void __iomem *arch_counter_base;
+static void __iomem *cntctlbase __initdata;
struct arch_timer {
void __iomem *base;
@@ -656,15 +657,56 @@ out:
return err;
}
-static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
+static int __init arch_timer_mem_register(struct device_node *np, void *frame)
{
- int ret;
- irq_handler_t func;
+ struct device_node *frame_node = NULL;
+ struct gt_timer_data *frame_data = NULL;
struct arch_timer *t;
+ void __iomem *base;
+ irq_handler_t func;
+ unsigned int irq;
+ int ret;
+
+ if (np) {
+ frame_node = (struct device_node *)frame;
+ base = of_iomap(frame_node, 0);
+ arch_timer_detect_rate(base, np);
+ if (arch_timer_mem_use_virtual)
+ irq = irq_of_parse_and_map(frame_node, VIRT_SPI);
+ else
+ irq = irq_of_parse_and_map(frame_node, PHYS_SPI);
+ } else {
+ frame_data = (struct gt_timer_data *)frame;
+ /*
+ * According to ARMv8 Architecture Reference Manual(ARM),
+ * the size of CNTBaseN frames of memory-mapped timer
+ * is SZ_4K(Offset 0x000 ? 0xFFF).
+ */
+ base = ioremap(frame_data->cntbase_phy, SZ_4K);
+ if (arch_timer_mem_use_virtual)
+ irq = frame_data->virtual_irq;
+ else
+ irq = frame_data->irq;
+ }
+
+ if (!base) {
+ pr_err("Can't map frame's registers\n");
+ return -ENXIO;
+ }
+ if (!irq) {
+ pr_err("Frame missing %s irq",
+ arch_timer_mem_use_virtual ? "virt" : "phys");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ arch_counter_base = base;
t = kzalloc(sizeof(*t), GFP_KERNEL);
- if (!t)
+ if (!t) {
return -ENOMEM;
+ goto out;
+ }
t->base = base;
t->evt.irq = irq;
@@ -676,11 +718,13 @@ static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
func = arch_timer_handler_phys_mem;
ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
- if (ret) {
- pr_err("Failed to request mem timer irq\n");
- kfree(t);
- }
+ if (!ret)
+ return 0;
+ pr_err("Failed to request mem timer irq\n");
+ kfree(t);
+out:
+ iounmap(base);
return ret;
}
@@ -769,7 +813,7 @@ static int __init arch_timer_init(void)
return ret;
arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI];
-
+
return 0;
}
@@ -803,21 +847,56 @@ static int __init arch_timer_of_init(struct device_node *np)
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
-static int __init arch_timer_mem_init(struct device_node *np)
+static int __init get_cnttidr(struct device_node *np,
+ struct gt_block_data *gt_block, u32 *cnttidr)
{
- struct device_node *frame, *best_frame = NULL;
- void __iomem *cntctlbase, *base;
- unsigned int irq, ret = -EINVAL;
- u32 cnttidr;
+ if (np)
+ cntctlbase = of_iomap(np, 0);
+ else
+ cntctlbase = ioremap(gt_block->cntctlbase_phy, SZ_4K);
+ /*
+ * According to ARMv8 Architecture Reference Manual(ARM),
+ * the size of CNTCTLBase frame of memory-mapped timer
+ * is SZ_4K(Offset 0x000 ? 0xFFF).
+ */
- arch_timers_present |= ARCH_MEM_TIMER;
- cntctlbase = of_iomap(np, 0);
if (!cntctlbase) {
pr_err("Can't find CNTCTLBase\n");
return -ENXIO;
}
- cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
+ *cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
+ return 0;
+}
+
+static bool __init is_best_frame(u32 cnttidr, int n)
+{
+ u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | CNTACR_RWVT |
+ CNTACR_RVOFF | CNTACR_RVCT;
+
+ /* Try enabling everything, and see what sticks */
+ writel_relaxed(cntacr, cntctlbase + CNTACR(n));
+ cntacr = readl_relaxed(cntctlbase + CNTACR(n));
+
+ if ((cnttidr & CNTTIDR_VIRT(n)) &&
+ !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT)))
+ arch_timer_mem_use_virtual = true;
+ else if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
+ return false;
+
+ return true;
+}
+
+static int __init arch_timer_mem_init(struct device_node *np)
+{
+ struct device_node *frame, *best_frame = NULL;
+ unsigned int ret = -EINVAL;
+ u32 cnttidr;
+
+ arch_timers_present |= ARCH_MEM_TIMER;
+
+ if (get_cnttidr(np, NULL, &cnttidr))
+ return -ENXIO;
/*
* Try to find a virtual capable frame. Otherwise fall back to a
@@ -825,60 +904,22 @@ static int __init arch_timer_mem_init(struct device_node *np)
*/
for_each_available_child_of_node(np, frame) {
int n;
- u32 cntacr;
-
if (of_property_read_u32(frame, "frame-number", &n)) {
- pr_err("Missing frame-number\n");
+ pr_err("Missing frame-number.\n");
of_node_put(frame);
goto out;
}
-
- /* Try enabling everything, and see what sticks */
- cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
- CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
- writel_relaxed(cntacr, cntctlbase + CNTACR(n));
- cntacr = readl_relaxed(cntctlbase + CNTACR(n));
-
- if ((cnttidr & CNTTIDR_VIRT(n)) &&
- !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
+ if (is_best_frame(cnttidr, n)) {
of_node_put(best_frame);
- best_frame = frame;
- arch_timer_mem_use_virtual = true;
- break;
+ best_frame = of_node_get(frame);
+ if (arch_timer_mem_use_virtual)
+ break;
}
-
- if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
- continue;
-
- of_node_put(best_frame);
- best_frame = of_node_get(frame);
- }
-
- ret= -ENXIO;
- base = arch_counter_base = of_iomap(best_frame, 0);
- if (!base) {
- pr_err("Can't map frame's registers\n");
- goto out;
- }
-
- if (arch_timer_mem_use_virtual)
- irq = irq_of_parse_and_map(best_frame, VIRT_SPI);
- else
- irq = irq_of_parse_and_map(best_frame, PHYS_SPI);
-
- ret = -EINVAL;
- if (!irq) {
- pr_err("Frame missing %s irq",
- arch_timer_mem_use_virtual ? "virt" : "phys");
- goto out;
}
- arch_timer_detect_rate(base, np);
- ret = arch_timer_mem_register(base, irq);
- if (ret)
- goto out;
-
- return arch_timer_common_init();
+ ret = arch_timer_mem_register(np, best_frame);
+ if (!ret)
+ ret = arch_timer_common_init();
out:
iounmap(cntctlbase);
of_node_put(best_frame);
@@ -888,7 +929,72 @@ CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
arch_timer_mem_init);
#ifdef CONFIG_ACPI_GTDT
-/* Initialize per-processor generic timer */
+static struct gt_timer_data __init *arch_timer_mem_get_timer(
+ struct gt_block_data *gt_blocks)
+{
+ struct gt_block_data *gt_block = gt_blocks;
+ struct gt_timer_data *best_frame = NULL;
+ u32 cnttidr;
+ int i;
+
+ if (get_cnttidr(NULL, gt_block, &cnttidr))
+ return NULL;
+ /*
+ * Try to find a virtual capable frame. Otherwise fall back to a
+ * physical capable frame.
+ */
+ for (i = 0; i < gt_block->timer_count; i++) {
+ if (is_best_frame(cnttidr, gt_block->timer[i].frame_nr)) {
+ best_frame = >_block->timer[i];
+ if (arch_timer_mem_use_virtual)
+ break;
+ }
+ }
+ iounmap(cntctlbase);
+
+ return best_frame;
+}
+
+static int __init arch_timer_mem_acpi_init(size_t timer_count)
+{
+ struct gt_block_data *gt_blocks;
+ struct gt_timer_data *gt_timer;
+ int ret = -EINVAL;
+
+ /*
+ * If we don't have any Platform Timer Structures, just return.
+ */
+ if (!timer_count)
+ return 0;
+
+ /*
+ * before really check all the Platform Timer Structures,
+ * we assume they are GT block, and allocate memory for them.
+ * We will free these memory once we finish the initialization.
+ */
+ gt_blocks = kcalloc(timer_count, sizeof(*gt_blocks), GFP_KERNEL);
+ if (!gt_blocks)
+ return -ENOMEM;
+
+ if (gtdt_arch_timer_mem_init(gt_blocks) > 0) {
+ gt_timer = arch_timer_mem_get_timer(gt_blocks);
+ if (!gt_timer) {
+ pr_err("Failed to get mem timer info.\n");
+ goto error;
+ }
+ ret = arch_timer_mem_register(NULL, gt_timer);
+ if (ret) {
+ pr_err("Failed to register mem timer.\n");
+ goto error;
+ }
+ }
+ arch_timers_present |= ARCH_MEM_TIMER;
+error:
+ kfree(gt_blocks);
+ return ret;
+}
+
+/* Initialize per-processor generic timer and memory-mapped timer(if present) */
static int __init arch_timer_acpi_init(struct acpi_table_header *table)
{
int timer_count;
@@ -912,8 +1018,8 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
/* Get the frequency from CNTFRQ */
arch_timer_detect_rate(NULL, NULL);
- if (timer_count < 0)
- pr_err("Failed to get platform timer info.\n");
+ if (timer_count < 0 || arch_timer_mem_acpi_init((size_t)timer_count))
+ pr_err("Failed to initialize memory-mapped timer.\n");
return arch_timer_init();
}
--
2.7.4
^ permalink raw reply related
* [PATCH v13 6/8] acpi/arm64: Add memory-mapped timer support in GTDT driver
From: fu.wei at linaro.org @ 2016-09-14 20:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473883781-9571-1-git-send-email-fu.wei@linaro.org>
From: Fu Wei <fu.wei@linaro.org>
On platforms booting with ACPI, architected memory-mapped timers'
configuration data is provided by firmware through the ACPI GTDT
static table.
The clocksource architected timer kernel driver requires a firmware
interface to collect timer configuration and configure its driver.
this infrastructure is present for device tree systems, but it is
missing on systems booting with ACPI.
Implement the kernel infrastructure required to parse the static
ACPI GTDT table so that the architected timer clocksource driver can
make use of it on systems booting with ACPI, therefore enabling
the corresponding timers configuration.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
drivers/acpi/arm64/gtdt.c | 70 ++++++++++++++++++++++++++++++++++++
include/clocksource/arm_arch_timer.h | 15 ++++++++
include/linux/acpi.h | 1 +
3 files changed, 86 insertions(+)
diff --git a/drivers/acpi/arm64/gtdt.c b/drivers/acpi/arm64/gtdt.c
index b24844d..b6021db 100644
--- a/drivers/acpi/arm64/gtdt.c
+++ b/drivers/acpi/arm64/gtdt.c
@@ -150,3 +150,73 @@ int __init acpi_gtdt_init(struct acpi_table_header *table)
return gtdt->platform_timer_count;
}
+
+static int __init gtdt_parse_gt_block(struct acpi_gtdt_timer_block *block,
+ struct gt_block_data *data)
+{
+ struct acpi_gtdt_timer_entry *frame;
+ int i;
+
+ if (!block || !data)
+ return -EINVAL;
+
+ if (!block->block_address || !block->timer_count)
+ return -EINVAL;
+
+ data->cntctlbase_phy = (phys_addr_t)block->block_address;
+ data->timer_count = block->timer_count;
+
+ frame = (void *)block + block->timer_offset;
+ if (frame + block->timer_count != (void *)block + block->header.length)
+ return -EINVAL;
+
+ /*
+ * Get the GT timer Frame data for every GT Block Timer
+ */
+ for (i = 0; i < block->timer_count; i++, frame++) {
+ if (!frame->base_address || !frame->timer_interrupt)
+ return -EINVAL;
+
+ data->timer[i].irq = map_gt_gsi(frame->timer_interrupt,
+ frame->timer_flags);
+ if (data->timer[i].irq <= 0)
+ return -EINVAL;
+
+ if (frame->virtual_timer_interrupt) {
+ data->timer[i].virtual_irq =
+ map_gt_gsi(frame->virtual_timer_interrupt,
+ frame->virtual_timer_flags);
+ if (data->timer[i].virtual_irq <= 0)
+ return -EINVAL;
+ }
+
+ data->timer[i].frame_nr = frame->frame_number;
+ data->timer[i].cntbase_phy = frame->base_address;
+ }
+
+ return 0;
+}
+
+/*
+ * Get the GT block info for memory-mapped timer from GTDT table.
+ */
+int __init gtdt_arch_timer_mem_init(struct gt_block_data *data)
+{
+ void *platform_timer;
+ int index = 0;
+ int ret;
+
+ for_each_platform_timer(platform_timer) {
+ if (!is_timer_block(platform_timer))
+ continue;
+ ret = gtdt_parse_gt_block(platform_timer, data + index);
+ if (ret)
+ return ret;
+ index++;
+ }
+
+ if (index)
+ pr_info("found %d memory-mapped timer block(s).\n", index);
+
+ return index;
+}
diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
index 16dcd10..94a5d14 100644
--- a/include/clocksource/arm_arch_timer.h
+++ b/include/clocksource/arm_arch_timer.h
@@ -56,6 +56,8 @@ enum spi_nr {
#define ARCH_TIMER_MEM_PHYS_ACCESS 2
#define ARCH_TIMER_MEM_VIRT_ACCESS 3
+#define ARCH_TIMER_MEM_MAX_FRAME 8
+
#define ARCH_TIMER_USR_PCT_ACCESS_EN (1 << 0) /* physical counter */
#define ARCH_TIMER_USR_VCT_ACCESS_EN (1 << 1) /* virtual counter */
#define ARCH_TIMER_VIRT_EVT_EN (1 << 2)
@@ -71,6 +73,19 @@ struct arch_timer_kvm_info {
int virtual_irq;
};
+struct gt_timer_data {
+ int frame_nr;
+ phys_addr_t cntbase_phy;
+ int irq;
+ int virtual_irq;
+};
+
+struct gt_block_data {
+ phys_addr_t cntctlbase_phy;
+ int timer_count;
+ struct gt_timer_data timer[ARCH_TIMER_MEM_MAX_FRAME];
+};
+
#ifdef CONFIG_ARM_ARCH_TIMER
extern u32 arch_timer_get_rate(void);
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index e2f9841..5dc0b85 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -571,6 +571,7 @@ int acpi_reconfig_notifier_unregister(struct notifier_block *nb);
int acpi_gtdt_init(struct acpi_table_header *table);
int acpi_gtdt_map_ppi(int type);
bool acpi_gtdt_c3stop(void);
+int gtdt_arch_timer_mem_init(struct gt_block_data *data);
#endif
#else /* !CONFIG_ACPI */
--
2.7.4
^ permalink raw reply related
* [PATCH v13 5/8] clocksource/drivers/arm_arch_timer: Simplify ACPI support code.
From: fu.wei at linaro.org @ 2016-09-14 20:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473883781-9571-1-git-send-email-fu.wei@linaro.org>
From: Fu Wei <fu.wei@linaro.org>
The patch update arm_arch_timer driver to use the function
provided by the new GTDT driver of ACPI.
By this way, arm_arch_timer.c can be simplified, and separate
all the ACPI GTDT knowledge from this timer driver.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
drivers/clocksource/Kconfig | 1 +
drivers/clocksource/arm_arch_timer.c | 50 +++++++++---------------------------
2 files changed, 13 insertions(+), 38 deletions(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index b58d259..a63bf12 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -8,6 +8,7 @@ config CLKSRC_OF
config CLKSRC_ACPI
bool
select CLKSRC_PROBE
+ select ACPI_GTDT if ARM64
config CLKSRC_PROBE
bool
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 7d48349..0197ef9 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -887,61 +887,35 @@ out:
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
arch_timer_mem_init);
-#ifdef CONFIG_ACPI
-static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags)
-{
- int trigger, polarity;
-
- if (!interrupt)
- return 0;
-
- trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE
- : ACPI_LEVEL_SENSITIVE;
-
- polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW
- : ACPI_ACTIVE_HIGH;
-
- return acpi_register_gsi(NULL, interrupt, trigger, polarity);
-}
-
+#ifdef CONFIG_ACPI_GTDT
/* Initialize per-processor generic timer */
static int __init arch_timer_acpi_init(struct acpi_table_header *table)
{
- struct acpi_table_gtdt *gtdt;
+ int timer_count;
if (arch_timers_present & ARCH_CP15_TIMER) {
pr_warn("already initialized, skipping\n");
return -EINVAL;
}
- gtdt = container_of(table, struct acpi_table_gtdt, header);
-
arch_timers_present |= ARCH_CP15_TIMER;
- arch_timer_ppi[PHYS_SECURE_PPI] =
- map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
- gtdt->secure_el1_flags);
-
- arch_timer_ppi[PHYS_NONSECURE_PPI] =
- map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
- gtdt->non_secure_el1_flags);
+ timer_count = acpi_gtdt_init(table);
- arch_timer_ppi[VIRT_PPI] =
- map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
- gtdt->virtual_timer_flags);
-
- arch_timer_ppi[HYP_PPI] =
- map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
- gtdt->non_secure_el2_flags);
+ arch_timer_ppi[PHYS_SECURE_PPI] = acpi_gtdt_map_ppi(PHYS_SECURE_PPI);
+ arch_timer_ppi[PHYS_NONSECURE_PPI] = acpi_gtdt_map_ppi(PHYS_NONSECURE_PPI);
+ arch_timer_ppi[VIRT_PPI] = acpi_gtdt_map_ppi(VIRT_PPI);
+ arch_timer_ppi[HYP_PPI] = acpi_gtdt_map_ppi(HYP_PPI);
+ /* Always-on capability */
+ arch_timer_c3stop = acpi_gtdt_c3stop();
/* Get the frequency from CNTFRQ */
arch_timer_detect_rate(NULL, NULL);
- /* Always-on capability */
- arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
+ if (timer_count < 0)
+ pr_err("Failed to get platform timer info.\n");
- arch_timer_init();
- return 0;
+ return arch_timer_init();
}
CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v13 4/8] acpi/arm64: Add GTDT table parse driver
From: fu.wei at linaro.org @ 2016-09-14 20:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473883781-9571-1-git-send-email-fu.wei@linaro.org>
From: Fu Wei <fu.wei@linaro.org>
This patch adds support for parsing arch timer in GTDT,
provides some kernel APIs to parse all the PPIs and
always-on info in GTDT and export them.
By this driver, we can simplify arm_arch_timer drivers, and
separate the ACPI GTDT knowledge from it.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
arch/arm64/Kconfig | 1 +
drivers/acpi/arm64/Kconfig | 3 +
drivers/acpi/arm64/Makefile | 1 +
drivers/acpi/arm64/gtdt.c | 152 ++++++++++++++++++++++++++++++++++++++++++++
drivers/clocksource/Kconfig | 1 -
include/linux/acpi.h | 6 ++
6 files changed, 163 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index bc3f00f..0607728 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -2,6 +2,7 @@ config ARM64
def_bool y
select ACPI_CCA_REQUIRED if ACPI
select ACPI_GENERIC_GSI if ACPI
+ select ACPI_GTDT if ACPI
select ACPI_REDUCED_HARDWARE_ONLY if ACPI
select ACPI_MCFG if ACPI
select ARCH_HAS_DEVMEM_IS_ALLOWED
diff --git a/drivers/acpi/arm64/Kconfig b/drivers/acpi/arm64/Kconfig
index 4616da4..5a6f80f 100644
--- a/drivers/acpi/arm64/Kconfig
+++ b/drivers/acpi/arm64/Kconfig
@@ -4,3 +4,6 @@
config ACPI_IORT
bool
+
+config ACPI_GTDT
+ bool
diff --git a/drivers/acpi/arm64/Makefile b/drivers/acpi/arm64/Makefile
index 72331f2..1017def 100644
--- a/drivers/acpi/arm64/Makefile
+++ b/drivers/acpi/arm64/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_ACPI_IORT) += iort.o
+obj-$(CONFIG_ACPI_GTDT) += gtdt.o
diff --git a/drivers/acpi/arm64/gtdt.c b/drivers/acpi/arm64/gtdt.c
new file mode 100644
index 0000000..b24844d
--- /dev/null
+++ b/drivers/acpi/arm64/gtdt.c
@@ -0,0 +1,152 @@
+/*
+ * ARM Specific GTDT table Support
+ *
+ * Copyright (C) 2016, Linaro Ltd.
+ * Author: Daniel Lezcano <daniel.lezcano@linaro.org>
+ * Fu Wei <fu.wei@linaro.org>
+ * Hanjun Guo <hanjun.guo@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/acpi.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <clocksource/arm_arch_timer.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "ACPI GTDT: " fmt
+
+struct acpi_gtdt_descriptor {
+ struct acpi_table_gtdt *gtdt;
+ void *platform_timer_start;
+ void *gtdt_end;
+};
+
+static struct acpi_gtdt_descriptor acpi_gtdt_desc __initdata;
+
+static inline void *next_platform_timer(void *platform_timer)
+{
+ struct acpi_gtdt_header *gh = platform_timer;
+
+ platform_timer += gh->length;
+ if (platform_timer < acpi_gtdt_desc.gtdt_end)
+ return platform_timer;
+
+ return NULL;
+}
+
+#define for_each_platform_timer(_g) \
+ for (_g = acpi_gtdt_desc.platform_timer_start; _g; \
+ _g = next_platform_timer(_g))
+
+static inline bool is_timer_block(void *platform_timer)
+{
+ struct acpi_gtdt_header *gh = platform_timer;
+
+ return gh->type == ACPI_GTDT_TYPE_TIMER_BLOCK;
+}
+
+static inline bool is_watchdog(void *platform_timer)
+{
+ struct acpi_gtdt_header *gh = platform_timer;
+
+ return gh->type == ACPI_GTDT_TYPE_WATCHDOG;
+}
+
+static int __init map_gt_gsi(u32 interrupt, u32 flags)
+{
+ int trigger, polarity;
+
+ if (!interrupt)
+ return 0;
+
+ trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE
+ : ACPI_LEVEL_SENSITIVE;
+
+ polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW
+ : ACPI_ACTIVE_HIGH;
+
+ return acpi_register_gsi(NULL, interrupt, trigger, polarity);
+}
+
+/*
+ * Map the PPIs of per-cpu arch_timer.
+ * @type: the type of PPI
+ * Returns 0 if error.
+ */
+int __init acpi_gtdt_map_ppi(int type)
+{
+ struct acpi_table_gtdt *gtdt = acpi_gtdt_desc.gtdt;
+
+ switch (type) {
+ case PHYS_SECURE_PPI:
+ return map_gt_gsi(gtdt->secure_el1_interrupt,
+ gtdt->secure_el1_flags);
+ case PHYS_NONSECURE_PPI:
+ return map_gt_gsi(gtdt->non_secure_el1_interrupt,
+ gtdt->non_secure_el1_flags);
+ case VIRT_PPI:
+ return map_gt_gsi(gtdt->virtual_timer_interrupt,
+ gtdt->virtual_timer_flags);
+
+ case HYP_PPI:
+ return map_gt_gsi(gtdt->non_secure_el2_interrupt,
+ gtdt->non_secure_el2_flags);
+ default:
+ pr_err("Failed to map timer interrupt: invalid type.\n");
+ }
+
+ return 0;
+}
+
+/*
+ * acpi_gtdt_c3stop - got c3stop info from GTDT
+ *
+ * Returns 1 if the timer is powered in deep idle state, 0 otherwise.
+ */
+bool __init acpi_gtdt_c3stop(void)
+{
+ struct acpi_table_gtdt *gtdt = acpi_gtdt_desc.gtdt;
+
+ return !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
+}
+
+/*
+ * Get some basic info from GTDT table, and init the global variables above
+ * for all timers initialization of Generic Timer.
+ * This function does some validation on GTDT table.
+ */
+int __init acpi_gtdt_init(struct acpi_table_header *table)
+{
+ void *start;
+ struct acpi_table_gtdt *gtdt;
+
+ gtdt = container_of(table, struct acpi_table_gtdt, header);
+
+ acpi_gtdt_desc.gtdt = gtdt;
+ acpi_gtdt_desc.gtdt_end = (void *)table + table->length;
+
+ if (table->revision < 2) {
+ pr_debug("Revision:%d doesn't support Platform Timers.\n",
+ table->revision);
+ return 0;
+ }
+
+ if (!gtdt->platform_timer_count) {
+ pr_debug("No Platform Timer.\n");
+ return 0;
+ }
+
+ start = (void *)gtdt + gtdt->platform_timer_offset;
+ if (start < (void *)table + sizeof(struct acpi_table_gtdt)) {
+ pr_err(FW_BUG "Failed to retrieve timer info from firmware: invalid data.\n");
+ return -EINVAL;
+ }
+ acpi_gtdt_desc.platform_timer_start = start;
+
+ return gtdt->platform_timer_count;
+}
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 5677886..b58d259 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -285,7 +285,6 @@ config CLKSRC_MPS2
config ARM_ARCH_TIMER
bool
select CLKSRC_OF if OF
- select CLKSRC_ACPI if ACPI
config ARM_ARCH_TIMER_EVTSTREAM
bool "Enable ARM architected timer event stream generation by default"
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index c5eaf2f..e2f9841 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -567,6 +567,12 @@ enum acpi_reconfig_event {
int acpi_reconfig_notifier_register(struct notifier_block *nb);
int acpi_reconfig_notifier_unregister(struct notifier_block *nb);
+#ifdef CONFIG_ACPI_GTDT
+int acpi_gtdt_init(struct acpi_table_header *table);
+int acpi_gtdt_map_ppi(int type);
+bool acpi_gtdt_c3stop(void);
+#endif
+
#else /* !CONFIG_ACPI */
#define acpi_disabled 1
--
2.7.4
^ permalink raw reply related
* [PATCH v13 3/8] clocksource/drivers/arm_arch_timer: Improve printk relevant code
From: fu.wei at linaro.org @ 2016-09-14 20:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473883781-9571-1-git-send-email-fu.wei@linaro.org>
From: Fu Wei <fu.wei@linaro.org>
This patch defines pr_fmt(fmt) for all pr_* functions,
then the pr_* doesn't need to add "arch_timer:" everytime.
Also delete some Blank Spaces in arch_timer_banner,
according to the suggestion from checkpatch.pl.
No functional change.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
---
drivers/clocksource/arm_arch_timer.c | 53 ++++++++++++++++++------------------
1 file changed, 27 insertions(+), 26 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 059f7fb..7d48349 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -32,6 +32,9 @@
#include <clocksource/arm_arch_timer.h>
+#undef pr_fmt
+#define pr_fmt(fmt) "arch_timer: " fmt
+
#define CNTTIDR 0x08
#define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
@@ -418,24 +421,24 @@ arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
/* Check the timer frequency. */
if (arch_timer_rate == 0)
- pr_warn("Architected timer frequency not available\n");
+ pr_warn("frequency not available\n");
}
static void arch_timer_banner(unsigned type)
{
- pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
- type & ARCH_CP15_TIMER ? "cp15" : "",
- type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
- type & ARCH_MEM_TIMER ? "mmio" : "",
- (unsigned long)arch_timer_rate / 1000000,
- (unsigned long)(arch_timer_rate / 10000) % 100,
- type & ARCH_CP15_TIMER ?
- (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
- "",
- type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
- type & ARCH_MEM_TIMER ?
- arch_timer_mem_use_virtual ? "virt" : "phys" :
- "");
+ pr_info("%s%s%s timer(s) running@%lu.%02luMHz (%s%s%s).\n",
+ type & ARCH_CP15_TIMER ? "cp15" : "",
+ type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
+ type & ARCH_MEM_TIMER ? "mmio" : "",
+ (unsigned long)arch_timer_rate / 1000000,
+ (unsigned long)(arch_timer_rate / 10000) % 100,
+ type & ARCH_CP15_TIMER ?
+ (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
+ "",
+ type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
+ type & ARCH_MEM_TIMER ?
+ arch_timer_mem_use_virtual ? "virt" : "phys" :
+ "");
}
u32 arch_timer_get_rate(void)
@@ -528,8 +531,7 @@ static void __init arch_counter_register(unsigned type)
static void arch_timer_stop(struct clock_event_device *clk)
{
- pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
- clk->irq, smp_processor_id());
+ pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
if (arch_timer_has_nonsecure_ppi())
@@ -622,8 +624,7 @@ static int __init arch_timer_register(void)
}
if (err) {
- pr_err("arch_timer: can't register interrupt %d (%d)\n",
- ppi, err);
+ pr_err("can't register interrupt %d (%d)\n", ppi, err);
goto out_free;
}
@@ -676,7 +677,7 @@ static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
if (ret) {
- pr_err("arch_timer: Failed to request mem timer irq\n");
+ pr_err("Failed to request mem timer irq\n");
kfree(t);
}
@@ -754,7 +755,7 @@ static int __init arch_timer_init(void)
}
if (!has_ppi) {
- pr_warn("arch_timer: No interrupt available, giving up\n");
+ pr_warn("No interrupt available, giving up\n");
return -EINVAL;
}
}
@@ -777,7 +778,7 @@ static int __init arch_timer_of_init(struct device_node *np)
int i;
if (arch_timers_present & ARCH_CP15_TIMER) {
- pr_warn("arch_timer: multiple nodes in dt, skipping\n");
+ pr_warn("multiple nodes in dt, skipping\n");
return 0;
}
@@ -812,7 +813,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
arch_timers_present |= ARCH_MEM_TIMER;
cntctlbase = of_iomap(np, 0);
if (!cntctlbase) {
- pr_err("arch_timer: Can't find CNTCTLBase\n");
+ pr_err("Can't find CNTCTLBase\n");
return -ENXIO;
}
@@ -827,7 +828,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
u32 cntacr;
if (of_property_read_u32(frame, "frame-number", &n)) {
- pr_err("arch_timer: Missing frame-number\n");
+ pr_err("Missing frame-number\n");
of_node_put(frame);
goto out;
}
@@ -856,7 +857,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
ret= -ENXIO;
base = arch_counter_base = of_iomap(best_frame, 0);
if (!base) {
- pr_err("arch_timer: Can't map frame's registers\n");
+ pr_err("Can't map frame's registers\n");
goto out;
}
@@ -867,7 +868,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
ret = -EINVAL;
if (!irq) {
- pr_err("arch_timer: Frame missing %s irq",
+ pr_err("Frame missing %s irq",
arch_timer_mem_use_virtual ? "virt" : "phys");
goto out;
}
@@ -909,7 +910,7 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
struct acpi_table_gtdt *gtdt;
if (arch_timers_present & ARCH_CP15_TIMER) {
- pr_warn("arch_timer: already initialized, skipping\n");
+ pr_warn("already initialized, skipping\n");
return -EINVAL;
}
--
2.7.4
^ permalink raw reply related
* [PATCH v13 2/8] clocksource/drivers/arm_arch_timer: Add a new enum for spi type
From: fu.wei at linaro.org @ 2016-09-14 20:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473883781-9571-1-git-send-email-fu.wei@linaro.org>
From: Fu Wei <fu.wei@linaro.org>
This patch add a new enum "spi_nr" and use it in the driver.
Just for code's readability, no functional change.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
---
drivers/clocksource/arm_arch_timer.c | 4 ++--
include/clocksource/arm_arch_timer.h | 6 ++++++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index aea6c10..059f7fb 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -861,9 +861,9 @@ static int __init arch_timer_mem_init(struct device_node *np)
}
if (arch_timer_mem_use_virtual)
- irq = irq_of_parse_and_map(best_frame, 1);
+ irq = irq_of_parse_and_map(best_frame, VIRT_SPI);
else
- irq = irq_of_parse_and_map(best_frame, 0);
+ irq = irq_of_parse_and_map(best_frame, PHYS_SPI);
ret = -EINVAL;
if (!irq) {
diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
index 6f06481..16dcd10 100644
--- a/include/clocksource/arm_arch_timer.h
+++ b/include/clocksource/arm_arch_timer.h
@@ -45,6 +45,12 @@ enum ppi_nr {
MAX_TIMER_PPI
};
+enum spi_nr {
+ PHYS_SPI,
+ VIRT_SPI,
+ MAX_TIMER_SPI
+};
+
#define ARCH_TIMER_PHYS_ACCESS 0
#define ARCH_TIMER_VIRT_ACCESS 1
#define ARCH_TIMER_MEM_PHYS_ACCESS 2
--
2.7.4
^ permalink raw reply related
* [PATCH v13 1/8] clocksource/drivers/arm_arch_timer: Move enums and defines to header file
From: fu.wei at linaro.org @ 2016-09-14 20:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473883781-9571-1-git-send-email-fu.wei@linaro.org>
From: Fu Wei <fu.wei@linaro.org>
To support the arm_arch_timer via ACPI we need to share defines and enums
between the driver and the ACPI parser code.
Split out the relevant defines and enums into arm_arch_timer.h.
No functional change.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
---
drivers/clocksource/arm_arch_timer.c | 11 -----------
include/clocksource/arm_arch_timer.h | 11 +++++++++++
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 5770054..aea6c10 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -51,8 +51,6 @@
#define CNTV_TVAL 0x38
#define CNTV_CTL 0x3c
-#define ARCH_CP15_TIMER BIT(0)
-#define ARCH_MEM_TIMER BIT(1)
static unsigned arch_timers_present __initdata;
static void __iomem *arch_counter_base;
@@ -65,15 +63,6 @@ struct arch_timer {
#define to_arch_timer(e) container_of(e, struct arch_timer, evt)
static u32 arch_timer_rate;
-
-enum ppi_nr {
- PHYS_SECURE_PPI,
- PHYS_NONSECURE_PPI,
- VIRT_PPI,
- HYP_PPI,
- MAX_TIMER_PPI
-};
-
static int arch_timer_ppi[MAX_TIMER_PPI];
static struct clock_event_device __percpu *arch_timer_evt;
diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
index caedb74..6f06481 100644
--- a/include/clocksource/arm_arch_timer.h
+++ b/include/clocksource/arm_arch_timer.h
@@ -19,6 +19,9 @@
#include <linux/timecounter.h>
#include <linux/types.h>
+#define ARCH_CP15_TIMER BIT(0)
+#define ARCH_MEM_TIMER BIT(1)
+
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
@@ -34,6 +37,14 @@ enum arch_timer_reg {
ARCH_TIMER_REG_TVAL,
};
+enum ppi_nr {
+ PHYS_SECURE_PPI,
+ PHYS_NONSECURE_PPI,
+ VIRT_PPI,
+ HYP_PPI,
+ MAX_TIMER_PPI
+};
+
#define ARCH_TIMER_PHYS_ACCESS 0
#define ARCH_TIMER_VIRT_ACCESS 1
#define ARCH_TIMER_MEM_PHYS_ACCESS 2
--
2.7.4
^ permalink raw reply related
* [PATCH v13 0/8] acpi, clocksource: add GTDT driver and GTDT support in arm_arch_timer
From: fu.wei at linaro.org @ 2016-09-14 20:09 UTC (permalink / raw)
To: linux-arm-kernel
From: Fu Wei <fu.wei@linaro.org>
This patchset:
(1)Preparation for adding GTDT support in arm_arch_timer:
1. Move some enums and marcos to header file;
2. Add a new enum for spi type;
3. Improve printk relevant code.
(2)Introduce ACPI GTDT parser: drivers/acpi/arm64/acpi_gtdt.c
Parse all kinds of timer in GTDT table of ACPI:arch timer,
memory-mapped timer and SBSA Generic Watchdog timer.
This driver can help to simplify all the relevant timer drivers,
and separate all the ACPI GTDT knowledge from them.
(3)Simplify ACPI code for arm_arch_timer
(4)Add GTDT support for ARM memory-mapped timer, also refactor
original memory-mapped timer dt support for reusing some common
code.
This patchset depends on the following patchset:
[UPDATE PATCH V11 1/8] ACPI: I/O Remapping Table (IORT) initial support
https://lkml.org/lkml/2016/9/12/949
This patchset has been tested on the following platforms:
(1)ARM Foundation v8 model
Changelog:
v13: https://lkml.org/lkml/2016/9/15/
Improve arm_arch_timer code for memory-mapped
timer GTDT support, refactor original memory-mapped timer
dt support for reusing some common code.
v12: https://lkml.org/lkml/2016/9/13/250
Rebase to latest Linux 4.8-rc6
Delete the confusing "skipping" in the error message.
V11: https://lkml.org/lkml/2016/9/6/354
Rebase to latest Linux 4.8-rc5
Delete typedef (suggested by checkpatch.pl)
V10: https://lkml.org/lkml/2016/7/26/215
Drop the "readq" patch.
Rebase to latest Linux 4.7.
V9: https://lkml.org/lkml/2016/7/25/345
Improve pr_err message in acpi gtdt driver.
Update Commit message for 7/9
shorten the irq mapping function name
Improve GTDT driver for memory-mapped timer
v8: https://lkml.org/lkml/2016/7/19/660
Improve "pr_fmt(fmt)" definition: add "ACPI" in front of "GTDT",
and also improve printk message.
Simplify is_timer_block and is_watchdog.
Merge acpi_gtdt_desc_init and gtdt_arch_timer_init into acpi_gtdt_init();
Delete __init in include/linux/acpi.h for GTDT API
Make ARM64 select GTDT.
Delete "#include <linux/module.h>" from acpi_gtdt.c
Simplify GT block parse code.
v7: https://lkml.org/lkml/2016/7/13/769
Move the GTDT driver to drivers/acpi/arm64
Add add the ARM64-specific ACPI Support maintainers in MAINTAINERS
Merge 3 patches of GTDT parser driver.
Fix the for_each_platform_timer bug.
v6: https://lkml.org/lkml/2016/6/29/580
split the GTDT driver to 4 parts: basic, arch_timer, memory-mapped timer,
and SBSA Generic Watchdog timer
Improve driver by suggestions and example code from Daniel Lezcano
v5: https://lkml.org/lkml/2016/5/24/356
Sorting out all patches, simplify the API of GTDT driver:
GTDT driver just fills the data struct for arm_arch_timer driver.
v4: https://lists.linaro.org/pipermail/linaro-acpi/2016-March/006667.html
Delete the kvm relevant patches
Separate two patches for sorting out the code for arm_arch_timer.
Improve irq info export code to allow missing irq info in GTDT table.
v3: https://lkml.org/lkml/2016/2/1/658
Improve GTDT driver code:
(1)improve pr_* by defining pr_fmt(fmt)
(2)simplify gtdt_sbsa_gwdt_init
(3)improve gtdt_arch_timer_data_init, if table is NULL, it will try
to get GTDT table.
Move enum ppi_nr to arm_arch_timer.h, and add enum spi_nr.
Add arm_arch_timer get ppi from DT and GTDT support for kvm.
v2: https://lkml.org/lkml/2015/12/2/10
Rebase to latest kernel version(4.4-rc3).
Fix the bug about the config problem,
use CONFIG_ACPI_GTDT instead of CONFIG_ACPI in arm_arch_timer.c
v1: The first upstreaming version: https://lkml.org/lkml/2015/10/28/553
Fu Wei (8):
clocksource/drivers/arm_arch_timer: Move enums and defines to header
file
clocksource/drivers/arm_arch_timer: Add a new enum for spi type
clocksource/drivers/arm_arch_timer: Improve printk relevant code
acpi/arm64: Add GTDT table parse driver
clocksource/drivers/arm_arch_timer: Simplify ACPI support code.
acpi/arm64: Add memory-mapped timer support in GTDT driver
clocksource/drivers/arm_arch_timer: Add GTDT support for memory-mapped
timer
acpi/arm64: Add SBSA Generic Watchdog support in GTDT driver
arch/arm64/Kconfig | 1 +
drivers/acpi/arm64/Kconfig | 3 +
drivers/acpi/arm64/Makefile | 1 +
drivers/acpi/arm64/gtdt.c | 309 +++++++++++++++++++++++++++++++++
drivers/clocksource/Kconfig | 2 +-
drivers/clocksource/arm_arch_timer.c | 324 +++++++++++++++++++++--------------
drivers/watchdog/Kconfig | 1 +
include/clocksource/arm_arch_timer.h | 32 ++++
include/linux/acpi.h | 7 +
9 files changed, 552 insertions(+), 128 deletions(-)
create mode 100644 drivers/acpi/arm64/gtdt.c
--
2.7.4
^ permalink raw reply
* [PATCH v2 3/3] ARM64: dts: amlogic: Add basic support for Amlogic S905D
From: Neil Armstrong @ 2016-09-14 20:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914200858.7799-1-narmstrong@baylibre.com>
This patch introduces the basic support for the Amlogic S905D (MesonGXL)
and for the Amlogic evaluation boards P230 and P231.
No documentation has been released yet for this SoC, so for now only the
bare minimum has been added in the DT.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/arm/amlogic.txt | 4 ++
arch/arm64/boot/dts/amlogic/Makefile | 2 +
.../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 51 +++++++++++++++++
.../boot/dts/amlogic/meson-gxl-s905d-p231.dts | 51 +++++++++++++++++
.../boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 64 ++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi | 48 ++++++++++++++++
6 files changed, 220 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
index 7edb635..fffc179 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -21,6 +21,10 @@ Boards with the Amlogic Meson GXL S905X SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905x", "amlogic,meson-gxl";
+Boards with the Amlogic Meson GXL S905D SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,s905d", "amlogic,meson-gxl";
+
Board compatible values:
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 1f78b07..57e0ae0 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -5,6 +5,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
new file mode 100644
index 0000000..3dfaa37
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905d-p23x.dtsi"
+
+/ {
+ compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
+ model = "Amlogic Meson GXL (S905D) P230 Development Board";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
new file mode 100644
index 0000000..ade8d29
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905d-p23x.dtsi"
+
+/ {
+ compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl";
+ model = "Amlogic Meson GXL (S905D) P231 Development Board";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
new file mode 100644
index 0000000..1602719
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-gxl-s905d.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&uart_AO {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
new file mode 100644
index 0000000..615308e
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-gxl.dtsi"
+
+/ {
+ compatible = "amlogic,s905d", "amlogic,meson-gxl";
+};
--
2.7.0
^ permalink raw reply related
* [PATCH v2 2/3] ARM64: dts: amlogic: Add basic support for Amlogic S905X
From: Neil Armstrong @ 2016-09-14 20:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914200858.7799-1-narmstrong@baylibre.com>
From: Carlo Caione <carlo@endlessm.com>
This patch introduces the basic support for the Amlogic S905X (Meson
GXL) and for the Amlogic evaluation board P212.
No documentation has been released yet for this SoC, so for now only the
bare minimum has been added in the DT.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Andreas F?rber <afaerber@suse.de>
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/arm/amlogic.txt | 7 +++
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../boot/dts/amlogic/meson-gxl-s905x-p212.dts | 69 ++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 48 +++++++++++++++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 48 +++++++++++++++
5 files changed, 173 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
index fcc6f6c..7edb635 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -17,6 +17,10 @@ Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson-gxbb";
+Boards with the Amlogic Meson GXL S905X SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,s905x", "amlogic,meson-gxl";
+
Board compatible values:
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
@@ -28,3 +32,6 @@ Board compatible values:
- "hardkernel,odroid-c2" (Meson gxbb)
- "amlogic,p200" (Meson gxbb)
- "amlogic,p201" (Meson gxbb)
+ - "amlogic,p212" (Meson gxl s905x)
+ - "amlogic,p230" (Meson gxl s905d)
+ - "amlogic,p231" (Meson gxl s905d)
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 47ec703..1f78b07 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
new file mode 100644
index 0000000..9639f01
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905x.dtsi"
+
+/ {
+ compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl";
+ model = "Amlogic Meson GXL (S905X) P212 Development Board";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
new file mode 100644
index 0000000..07f0e0b
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-gxl.dtsi"
+
+/ {
+ compatible = "amlogic,s905x", "amlogic,meson-gxl";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
new file mode 100644
index 0000000..13b10ee
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-gx.dtsi"
+
+/ {
+ compatible = "amlogic,meson-gxl";
+};
--
2.7.0
^ permalink raw reply related
* [PATCH v2 1/3] ARM64: dts: amlogic: Add Meson GX dtsi from GXBB
From: Neil Armstrong @ 2016-09-14 20:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914200858.7799-1-narmstrong@baylibre.com>
Move all non-gxbb specific nodes to a common GX dtsi.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 200 +++++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 895 ++++++++++++----------------
2 files changed, 579 insertions(+), 516 deletions(-)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gx.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
new file mode 100644
index 0000000..a739d6a
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * Copyright (c) 2016 Andreas F?rber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cbus: cbus at c1100000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc1100000 0x0 0x100000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
+
+ uart_A: serial at 84c0 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x84c0 0x0 0x14>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+ };
+
+ gic: interrupt-controller at c4301000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xc4301000 0 0x1000>,
+ <0x0 0xc4302000 0 0x2000>,
+ <0x0 0xc4304000 0 0x2000>,
+ <0x0 0xc4306000 0 0x2000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ };
+
+ aobus: aobus at c8100000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc8100000 0x0 0x100000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
+
+ uart_AO: serial at 4c0 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x004c0 0x0 0x14>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+ };
+
+ periphs: periphs at c8834000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc8834000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
+ };
+
+
+ hiubus: hiubus at c883c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc883c000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
+ };
+
+ apb: apb at d0000000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xd0000000 0x0 0x200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 4e9cd01..443811b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -40,9 +40,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "meson-gx.dtsi"
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
#include <dt-bindings/clock/gxbb-clkc.h>
@@ -51,56 +49,6 @@
/ {
compatible = "amlogic,meson-gxbb";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
-
- cpu0: cpu at 0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x0>;
- enable-method = "psci";
- };
-
- cpu1: cpu at 1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x1>;
- enable-method = "psci";
- };
-
- cpu2: cpu at 2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x2>;
- enable-method = "psci";
- };
-
- cpu3: cpu at 3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x3>;
- enable-method = "psci";
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
firmware {
sm: secure-monitor {
@@ -126,31 +74,7 @@
};
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
- };
-
- xtal: xtal-clk {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xtal";
- #clock-cells = <0>;
- };
-
soc {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
usb0_phy: phy at c0000000 {
compatible = "amlogic,meson-gxbb-usb2-phy";
#phy-cells = <0>;
@@ -170,500 +94,439 @@
status = "disabled";
};
- cbus: cbus at c1100000 {
- compatible = "simple-bus";
- reg = <0x0 0xc1100000 0x0 0x100000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
+ usb0: usb at c9000000 {
+ compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
+ reg = <0x0 0xc9000000 0x0 0x40000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+ clock-names = "otg";
+ phys = <&usb0_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "host";
+ status = "disabled";
+ };
- reset: reset-controller at 4404 {
- compatible = "amlogic,meson-gxbb-reset";
- reg = <0x0 0x04404 0x0 0x20>;
- #reset-cells = <1>;
- };
+ usb1: usb at c9100000 {
+ compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
+ reg = <0x0 0xc9100000 0x0 0x40000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+ clock-names = "otg";
+ phys = <&usb1_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "host";
+ status = "disabled";
+ };
- uart_A: serial at 84c0 {
- compatible = "amlogic,meson-uart";
- reg = <0x0 0x84c0 0x0 0x14>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>;
- status = "disabled";
- };
+ ethmac: ethernet at c9410000 {
+ compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+ reg = <0x0 0xc9410000 0x0 0x10000
+ 0x0 0xc8834540 0x0 0x4>;
+ interrupts = <0 8 1>;
+ interrupt-names = "macirq";
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+ phy-mode = "rgmii";
+ status = "disabled";
+ };
+ };
+};
+
+&cbus {
+ reset: reset-controller at 4404 {
+ compatible = "amlogic,meson-gxbb-reset";
+ reg = <0x0 0x04404 0x0 0x20>;
+ #reset-cells = <1>;
+ };
+
+ uart_B: serial at 84dc {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x84dc 0x0 0x14>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ pwm_ab: pwm at 8550 {
+ compatible = "amlogic,meson-gxbb-pwm";
+ reg = <0x0 0x08550 0x0 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_cd: pwm at 8650 {
+ compatible = "amlogic,meson-gxbb-pwm";
+ reg = <0x0 0x08650 0x0 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ef: pwm at 86c0 {
+ compatible = "amlogic,meson-gxbb-pwm";
+ reg = <0x0 0x086c0 0x0 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ uart_C: serial at 8700 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x8700 0x0 0x14>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ watchdog at 98d0 {
+ compatible = "amlogic,meson-gxbb-wdt";
+ reg = <0x0 0x098d0 0x0 0x10>;
+ clocks = <&xtal>;
+ };
+
+ spifc: spi at 8c80 {
+ compatible = "amlogic,meson-gxbb-spifc";
+ reg = <0x0 0x08c80 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_SPI>;
+ status = "disabled";
+ };
+
+ i2c_A: i2c at 8500 {
+ compatible = "amlogic,meson-gxbb-i2c";
+ reg = <0x0 0x08500 0x0 0x20>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc CLKID_I2C>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c_B: i2c at 87c0 {
+ compatible = "amlogic,meson-gxbb-i2c";
+ reg = <0x0 0x087c0 0x0 0x20>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc CLKID_I2C>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c_C: i2c at 87e0 {
+ compatible = "amlogic,meson-gxbb-i2c";
+ reg = <0x0 0x087e0 0x0 0x20>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc CLKID_I2C>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+};
+
+&aobus {
+ pinctrl_aobus: pinctrl at 14 {
+ compatible = "amlogic,meson-gxbb-aobus-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
- uart_B: serial at 84dc {
- compatible = "amlogic,meson-uart";
- reg = <0x0 0x84dc 0x0 0x14>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>;
- status = "disabled";
+ gpio_ao: bank at 14 {
+ reg = <0x0 0x00014 0x0 0x8>,
+ <0x0 0x0002c 0x0 0x4>,
+ <0x0 0x00024 0x0 0x8>;
+ reg-names = "mux", "pull", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ uart_ao_a_pins: uart_ao_a {
+ mux {
+ groups = "uart_tx_ao_a", "uart_rx_ao_a";
+ function = "uart_ao";
};
+ };
- pwm_ab: pwm at 8550 {
- compatible = "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x08550 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
+ remote_input_ao_pins: remote_input_ao {
+ mux {
+ groups = "remote_input_ao";
+ function = "remote_input_ao";
};
+ };
- pwm_cd: pwm at 8650 {
- compatible = "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x08650 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
+ i2c_ao_pins: i2c_ao {
+ mux {
+ groups = "i2c_sck_ao",
+ "i2c_sda_ao";
+ function = "i2c_ao";
};
+ };
- pwm_ef: pwm at 86c0 {
- compatible = "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x086c0 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
+ pwm_ao_a_3_pins: pwm_ao_a_3 {
+ mux {
+ groups = "pwm_ao_a_3";
+ function = "pwm_ao_a_3";
};
+ };
- uart_C: serial at 8700 {
- compatible = "amlogic,meson-uart";
- reg = <0x0 0x8700 0x0 0x14>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>;
- status = "disabled";
+ pwm_ao_a_6_pins: pwm_ao_a_6 {
+ mux {
+ groups = "pwm_ao_a_6";
+ function = "pwm_ao_a_6";
};
+ };
- watchdog at 98d0 {
- compatible = "amlogic,meson-gxbb-wdt";
- reg = <0x0 0x098d0 0x0 0x10>;
- clocks = <&xtal>;
+ pwm_ao_a_12_pins: pwm_ao_a_12 {
+ mux {
+ groups = "pwm_ao_a_12";
+ function = "pwm_ao_a_12";
};
+ };
- spifc: spi at 8c80 {
- compatible = "amlogic,meson-gxbb-spifc";
- reg = <0x0 0x08c80 0x0 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc CLKID_SPI>;
- status = "disabled";
+ pwm_ao_b_pins: pwm_ao_b {
+ mux {
+ groups = "pwm_ao_b";
+ function = "pwm_ao_b";
};
+ };
+ };
+
+ clkc_AO: clock-controller at 040 {
+ compatible = "amlogic,gxbb-aoclkc";
+ reg = <0x0 0x00040 0x0 0x4>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ ir: ir at 580 {
+ compatible = "amlogic,meson-gxbb-ir";
+ reg = <0x0 0x00580 0x0 0x40>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ pwm_ab_AO: pwm at 550 {
+ compatible = "amlogic,meson-gxbb-pwm";
+ reg = <0x0 0x0550 0x0 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ i2c_AO: i2c at 500 {
+ compatible = "amlogic,meson-gxbb-i2c";
+ reg = <0x0 0x500 0x0 0x20>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc CLKID_AO_I2C>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+};
+
+&periphs {
+ rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x0 0x0 0x4>;
+ };
+
+ pinctrl_periphs: pinctrl at 4b0 {
+ compatible = "amlogic,meson-gxbb-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank at 4b0 {
+ reg = <0x0 0x004b0 0x0 0x28>,
+ <0x0 0x004e8 0x0 0x14>,
+ <0x0 0x00120 0x0 0x14>,
+ <0x0 0x00430 0x0 0x40>;
+ reg-names = "mux", "pull", "pull-enable", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
- i2c_A: i2c at 8500 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x08500 0x0 0x20>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ emmc_pins: emmc {
+ mux {
+ groups = "emmc_nand_d07",
+ "emmc_cmd",
+ "emmc_clk";
+ function = "emmc";
};
+ };
- i2c_B: i2c at 87c0 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x087c0 0x0 0x20>;
- interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ nor_pins: nor {
+ mux {
+ groups = "nor_d",
+ "nor_q",
+ "nor_c",
+ "nor_cs";
+ function = "nor";
};
+ };
- i2c_C: i2c at 87e0 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x087e0 0x0 0x20>;
- interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ sdcard_pins: sdcard {
+ mux {
+ groups = "sdcard_d0",
+ "sdcard_d1",
+ "sdcard_d2",
+ "sdcard_d3",
+ "sdcard_cmd",
+ "sdcard_clk";
+ function = "sdcard";
};
};
- gic: interrupt-controller at c4301000 {
- compatible = "arm,gic-400";
- reg = <0x0 0xc4301000 0 0x1000>,
- <0x0 0xc4302000 0 0x2000>,
- <0x0 0xc4304000 0 0x2000>,
- <0x0 0xc4306000 0 0x2000>;
- interrupt-controller;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- #interrupt-cells = <3>;
- #address-cells = <0>;
- };
-
- aobus: aobus at c8100000 {
- compatible = "simple-bus";
- reg = <0x0 0xc8100000 0x0 0x100000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
-
- pinctrl_aobus: pinctrl at 14 {
- compatible = "amlogic,meson-gxbb-aobus-pinctrl";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio_ao: bank at 14 {
- reg = <0x0 0x00014 0x0 0x8>,
- <0x0 0x0002c 0x0 0x4>,
- <0x0 0x00024 0x0 0x8>;
- reg-names = "mux", "pull", "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- uart_ao_a_pins: uart_ao_a {
- mux {
- groups = "uart_tx_ao_a", "uart_rx_ao_a";
- function = "uart_ao";
- };
- };
-
- remote_input_ao_pins: remote_input_ao {
- mux {
- groups = "remote_input_ao";
- function = "remote_input_ao";
- };
- };
-
- i2c_ao_pins: i2c_ao {
- mux {
- groups = "i2c_sck_ao",
- "i2c_sda_ao";
- function = "i2c_ao";
- };
- };
-
- pwm_ao_a_3_pins: pwm_ao_a_3 {
- mux {
- groups = "pwm_ao_a_3";
- function = "pwm_ao_a_3";
- };
- };
-
- pwm_ao_a_6_pins: pwm_ao_a_6 {
- mux {
- groups = "pwm_ao_a_6";
- function = "pwm_ao_a_6";
- };
- };
-
- pwm_ao_a_12_pins: pwm_ao_a_12 {
- mux {
- groups = "pwm_ao_a_12";
- function = "pwm_ao_a_12";
- };
- };
-
- pwm_ao_b_pins: pwm_ao_b {
- mux {
- groups = "pwm_ao_b";
- function = "pwm_ao_b";
- };
- };
+ sdio_pins: sdio {
+ mux {
+ groups = "sdio_d0",
+ "sdio_d1",
+ "sdio_d2",
+ "sdio_d3",
+ "sdio_cmd",
+ "sdio_clk";
+ function = "sdio";
};
+ };
- clkc_AO: clock-controller at 040 {
- compatible = "amlogic,gxbb-aoclkc";
- reg = <0x0 0x00040 0x0 0x4>;
- #clock-cells = <1>;
- #reset-cells = <1>;
+ sdio_irq_pins: sdio_irq {
+ mux {
+ groups = "sdio_irq";
+ function = "sdio";
};
+ };
- uart_AO: serial at 4c0 {
- compatible = "amlogic,meson-uart";
- reg = <0x0 0x004c0 0x0 0x14>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>;
- status = "disabled";
+ uart_a_pins: uart_a {
+ mux {
+ groups = "uart_tx_a",
+ "uart_rx_a";
+ function = "uart_a";
};
+ };
- ir: ir at 580 {
- compatible = "amlogic,meson-gxbb-ir";
- reg = <0x0 0x00580 0x0 0x40>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
+ uart_b_pins: uart_b {
+ mux {
+ groups = "uart_tx_b",
+ "uart_rx_b";
+ function = "uart_b";
};
+ };
- pwm_ab_AO: pwm at 550 {
- compatible = "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x0550 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
+ uart_c_pins: uart_c {
+ mux {
+ groups = "uart_tx_c",
+ "uart_rx_c";
+ function = "uart_c";
};
+ };
- i2c_AO: i2c at 500 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x500 0x0 0x20>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_AO_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ i2c_a_pins: i2c_a {
+ mux {
+ groups = "i2c_sck_a",
+ "i2c_sda_a";
+ function = "i2c_a";
};
};
- periphs: periphs at c8834000 {
- compatible = "simple-bus";
- reg = <0x0 0xc8834000 0x0 0x2000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
+ i2c_b_pins: i2c_b {
+ mux {
+ groups = "i2c_sck_b",
+ "i2c_sda_b";
+ function = "i2c_b";
+ };
+ };
- rng {
- compatible = "amlogic,meson-rng";
- reg = <0x0 0x0 0x0 0x4>;
+ i2c_c_pins: i2c_c {
+ mux {
+ groups = "i2c_sck_c",
+ "i2c_sda_c";
+ function = "i2c_c";
};
+ };
- pinctrl_periphs: pinctrl at 4b0 {
- compatible = "amlogic,meson-gxbb-periphs-pinctrl";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio: bank at 4b0 {
- reg = <0x0 0x004b0 0x0 0x28>,
- <0x0 0x004e8 0x0 0x14>,
- <0x0 0x00120 0x0 0x14>,
- <0x0 0x00430 0x0 0x40>;
- reg-names = "mux", "pull", "pull-enable", "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- emmc_pins: emmc {
- mux {
- groups = "emmc_nand_d07",
- "emmc_cmd",
- "emmc_clk";
- function = "emmc";
- };
- };
-
- nor_pins: nor {
- mux {
- groups = "nor_d",
- "nor_q",
- "nor_c",
- "nor_cs";
- function = "nor";
- };
- };
-
- sdcard_pins: sdcard {
- mux {
- groups = "sdcard_d0",
- "sdcard_d1",
- "sdcard_d2",
- "sdcard_d3",
- "sdcard_cmd",
- "sdcard_clk";
- function = "sdcard";
- };
- };
-
- sdio_pins: sdio {
- mux {
- groups = "sdio_d0",
- "sdio_d1",
- "sdio_d2",
- "sdio_d3",
- "sdio_cmd",
- "sdio_clk";
- function = "sdio";
- };
- };
-
- sdio_irq_pins: sdio_irq {
- mux {
- groups = "sdio_irq";
- function = "sdio";
- };
- };
-
- uart_a_pins: uart_a {
- mux {
- groups = "uart_tx_a",
- "uart_rx_a";
- function = "uart_a";
- };
- };
-
- uart_b_pins: uart_b {
- mux {
- groups = "uart_tx_b",
- "uart_rx_b";
- function = "uart_b";
- };
- };
-
- uart_c_pins: uart_c {
- mux {
- groups = "uart_tx_c",
- "uart_rx_c";
- function = "uart_c";
- };
- };
-
- i2c_a_pins: i2c_a {
- mux {
- groups = "i2c_sck_a",
- "i2c_sda_a";
- function = "i2c_a";
- };
- };
-
- i2c_b_pins: i2c_b {
- mux {
- groups = "i2c_sck_b",
- "i2c_sda_b";
- function = "i2c_b";
- };
- };
-
- i2c_c_pins: i2c_c {
- mux {
- groups = "i2c_sck_c",
- "i2c_sda_c";
- function = "i2c_c";
- };
- };
-
- eth_pins: eth_c {
- mux {
- groups = "eth_mdio",
- "eth_mdc",
- "eth_clk_rx_clk",
- "eth_rx_dv",
- "eth_rxd0",
- "eth_rxd1",
- "eth_rxd2",
- "eth_rxd3",
- "eth_rgmii_tx_clk",
- "eth_tx_en",
- "eth_txd0",
- "eth_txd1",
- "eth_txd2",
- "eth_txd3";
- function = "eth";
- };
- };
-
- pwm_a_x_pins: pwm_a_x {
- mux {
- groups = "pwm_a_x";
- function = "pwm_a_x";
- };
- };
-
- pwm_a_y_pins: pwm_a_y {
- mux {
- groups = "pwm_a_y";
- function = "pwm_a_y";
- };
- };
-
- pwm_b_pins: pwm_b {
- mux {
- groups = "pwm_b";
- function = "pwm_b";
- };
- };
-
- pwm_d_pins: pwm_d {
- mux {
- groups = "pwm_d";
- function = "pwm_d";
- };
- };
-
- pwm_e_pins: pwm_e {
- mux {
- groups = "pwm_e";
- function = "pwm_e";
- };
- };
-
- pwm_f_x_pins: pwm_f_x {
- mux {
- groups = "pwm_f_x";
- function = "pwm_f_x";
- };
- };
-
- pwm_f_y_pins: pwm_f_y {
- mux {
- groups = "pwm_f_y";
- function = "pwm_f_y";
- };
- };
+ eth_pins: eth_c {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_clk_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_rxd2",
+ "eth_rxd3",
+ "eth_rgmii_tx_clk",
+ "eth_tx_en",
+ "eth_txd0",
+ "eth_txd1",
+ "eth_txd2",
+ "eth_txd3";
+ function = "eth";
};
};
- hiubus: hiubus at c883c000 {
- compatible = "simple-bus";
- reg = <0x0 0xc883c000 0x0 0x2000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
+ pwm_a_x_pins: pwm_a_x {
+ mux {
+ groups = "pwm_a_x";
+ function = "pwm_a_x";
+ };
+ };
- clkc: clock-controller at 0 {
- compatible = "amlogic,gxbb-clkc";
- #clock-cells = <1>;
- reg = <0x0 0x0 0x0 0x3db>;
+ pwm_a_y_pins: pwm_a_y {
+ mux {
+ groups = "pwm_a_y";
+ function = "pwm_a_y";
};
+ };
- mailbox: mailbox at 404 {
- compatible = "amlogic,meson-gxbb-mhu";
- reg = <0 0x404 0 0x4c>;
- interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
- <0 209 IRQ_TYPE_EDGE_RISING>,
- <0 210 IRQ_TYPE_EDGE_RISING>;
- #mbox-cells = <1>;
+ pwm_b_pins: pwm_b {
+ mux {
+ groups = "pwm_b";
+ function = "pwm_b";
};
};
- apb: apb at d0000000 {
- compatible = "simple-bus";
- reg = <0x0 0xd0000000 0x0 0x200000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
+ pwm_d_pins: pwm_d {
+ mux {
+ groups = "pwm_d";
+ function = "pwm_d";
+ };
};
- usb0: usb at c9000000 {
- compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
- reg = <0x0 0xc9000000 0x0 0x40000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
- clock-names = "otg";
- phys = <&usb0_phy>;
- phy-names = "usb2-phy";
- dr_mode = "host";
- status = "disabled";
+ pwm_e_pins: pwm_e {
+ mux {
+ groups = "pwm_e";
+ function = "pwm_e";
+ };
};
- usb1: usb at c9100000 {
- compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
- reg = <0x0 0xc9100000 0x0 0x40000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
- clock-names = "otg";
- phys = <&usb1_phy>;
- phy-names = "usb2-phy";
- dr_mode = "host";
- status = "disabled";
+ pwm_f_x_pins: pwm_f_x {
+ mux {
+ groups = "pwm_f_x";
+ function = "pwm_f_x";
+ };
};
- ethmac: ethernet at c9410000 {
- compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
- reg = <0x0 0xc9410000 0x0 0x10000
- 0x0 0xc8834540 0x0 0x4>;
- interrupts = <0 8 1>;
- interrupt-names = "macirq";
- clocks = <&clkc CLKID_ETH>,
- <&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
- phy-mode = "rgmii";
- status = "disabled";
+ pwm_f_y_pins: pwm_f_y {
+ mux {
+ groups = "pwm_f_y";
+ function = "pwm_f_y";
+ };
};
};
};
+
+&hiubus {
+ clkc: clock-controller at 0 {
+ compatible = "amlogic,gxbb-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0x0 0x0 0x3db>;
+ };
+
+ mailbox: mailbox at 404 {
+ compatible = "amlogic,meson-gxbb-mhu";
+ reg = <0 0x404 0 0x4c>;
+ interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
+ <0 209 IRQ_TYPE_EDGE_RISING>,
+ <0 210 IRQ_TYPE_EDGE_RISING>;
+ #mbox-cells = <1>;
+ };
+};
--
2.7.0
^ permalink raw reply related
* [PATCH v2 0/3] ARM64: amlogic: Add support for GXL SoC Family
From: Neil Armstrong @ 2016-09-14 20:08 UTC (permalink / raw)
To: linux-arm-kernel
The new Amlogic GXL SoCs (S905X and S905D) are part of the Meson GX family and
share some common features that can be described in a common GX dtsi file used
by the Meson GXBB and Meson GXL Family dtsi.
This patchset introduces the common GX dtsi and switches the GXBB to use
the common GX dtsi.
Then it introduces the GXL S905X SoC with the GXL common dtsi, then the S905D
dtsi and the p212 board dts.
Finally the GXL S905D SoC is introduced with a S905D dtsi using the GXL common
and the p23x Board dtsi for the p231 and p230 development boards.
Changes since v1 at http://lkml.kernel.org/r/20160903082227.30559-1-narmstrong at baylibre.com :
- Add missing copyrigh in gx dtsi
- Rename gxl SoCs compatibles to amlogic,s905x and amlogic,s905d
Changes since RFC v1:
- Merge GX common and GXBB changes in a single patch
- Integrate GXL S905X patch
- Add support for S905D and the p23x boards
Note: This patchset integrates the patch "ARM64: dts: amlogic: Add basic support for Amlogic S905X" [1]
from Carlo Caione.
[1] http://lkml.kernel.org/r/1472382113-10754-1-git-send-email-carlo at caione.org
Carlo Caione (1):
ARM64: dts: amlogic: Add basic support for Amlogic S905X
Neil Armstrong (2):
ARM64: dts: amlogic: Add Meson GX dtsi from GXBB
ARM64: dts: amlogic: Add basic support for Amlogic S905D
Documentation/devicetree/bindings/arm/amlogic.txt | 11 +
arch/arm64/boot/dts/amlogic/Makefile | 3 +
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 200 +++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 895 +++++++++------------
.../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 51 ++
.../boot/dts/amlogic/meson-gxl-s905d-p231.dts | 51 ++
.../boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 64 ++
arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi | 48 ++
.../boot/dts/amlogic/meson-gxl-s905x-p212.dts | 69 ++
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 48 ++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 48 ++
11 files changed, 972 insertions(+), 516 deletions(-)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gx.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
--
2.7.0
^ permalink raw reply
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