* [RFC PATCH v2 1/5] ARM: hisi: Make 3620 explicit, remove wildcards
From: Arnd Bergmann @ 2016-09-16 7:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915210505.21878-2-netz.kernel@gmail.com>
On Thursday, September 15, 2016 4:05:01 PM CEST Marty Plummer wrote:
> --- a/arch/arm/mach-hisi/Kconfig
> +++ b/arch/arm/mach-hisi/Kconfig
> @@ -12,8 +12,8 @@ if ARCH_HISI
>
> menu "Hisilicon platform type"
>
> -config ARCH_HI3xxx
> - bool "Hisilicon Hi36xx family"
> +config ARCH_HI3620
> + bool "Hisilicon Hi3620 family"
> depends on ARCH_MULTI_V7
> select CACHE_L2X0
> select HAVE_ARM_SCU if SMP
>
This breaks bisection by removing the ARCH_HI3xxx symbol that
the other drivers still rely on until the entire series is
applied.
I'd suggest introducing a hidden ARCH_HI3xxx symbol like
config ARCH_HI3xxx
bool
config ARCH_HI3620
bool "Hisilicon Hi3620 family"
select ARCH_HI3xxx
...
Arnd
^ permalink raw reply
* [GIT PULL] arm64: X-Gene platforms DTS changes queued for 4.9 - part1
From: Arnd Bergmann @ 2016-09-16 7:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915112440.GD6718@leverpostej>
On Thursday, September 15, 2016 12:24:40 PM CEST Mark Rutland wrote:
> On Thu, Sep 15, 2016 at 11:15:35AM +0100, Will Deacon wrote:
> > From 436d3a7ad25517433fc8f563f44fdab3c4801666 Mon Sep 17 00:00:00 2001
> > From: Will Deacon <will.deacon@arm.com>
> > Date: Thu, 15 Sep 2016 10:14:41 +0100
> > Subject: [PATCH] MAINTAINERS: Update ARM PMU PROFILING AND DEBUGGING entry
> >
> > There are an increasing number of ARM SoC PMU drivers appearing for
> > things like interconnects, memory controllers and cache controllers.
> > Rather than have these handled on an ad-hoc basis, where SoC maintainers
> > each send their PMU drivers directly to arm-soc, let's take these into
> > drivers/perf/ and send a single pull request to arm-soc instead, much
> > like other subsystems.
> >
> > This patch amends the ARM PMU MAINTAINERS entry to include all of
> > drivers/perf/ (currently just the ARM CPU PMU), changes Mark Rutland
> > from Reviewer to Maintainer, so that he can help with the new tree and
> > adds the device-tree binding to the list of maintained files.
> >
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Signed-off-by: Will Deacon <will.deacon@arm.com>
>
> FWIW:
>
> Acked-by: Mark Rutland <mark.rutland@arm.com>
>
Acked-by: Arnd Bergmann <arnd@arndb.de>
^ permalink raw reply
* [RESEND PATCH] arm64: kgdb: fix single stepping
From: Will Deacon @ 2016-09-16 7:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916043218.GA30248@linaro.org>
A Jason appeared!
On Fri, Sep 16, 2016 at 01:32:19PM +0900, AKASHI Takahiro wrote:
> On Thu, Sep 15, 2016 at 08:04:57AM -0500, Jason Wessel wrote:
> > I added the patch to kgdb-next after fixing up the context since it no
> > longer applied to the mainline (
> > https://git.kernel.org/cgit/linux/kernel/git/jwessel/kgdb.git/log/?h=kgdb-next).
> > If there is further discussion on the point above, another patch can be
> > added, but it I am assuming this is the way you desire it to work as
> > there are some other architectures that use the same behaviour. I do
> > not presently have any ARM64 hardware to validate this particular
> > change.
> >
> > I also added to the patch a "Cc: linux-stable <stable@vger.kernel.org>"
> > so we can have this appear on some of the older kernels.
>
> Since Will asked me to split this patch into a few, I need some reworks
> to clarify which hunks in the patch are necessary for which version of kernel.
Yes, splitting the patch would be much better for sorting out the stable
backports too. Jason, please can you drop the patch for now? I don't mind
whether the end result goes via arm64 or kgdb, but we should at least both
agree on it first :)
Will
^ permalink raw reply
* [PATCH v3] clk: let clk_disable() return immediately if clk is NULL
From: Masahiro Yamada @ 2016-09-16 7:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <194aebe5-38dd-f43d-fb4d-16ce592a68e8@gmail.com>
Hi Stephen, Michael,
2016-08-26 0:27 GMT+09:00 Florian Fainelli <f.fainelli@gmail.com>:
> On 08/24/2016 10:26 AM, Masahiro Yamada wrote:
>> Many of clk_disable() implementations just return for NULL pointer,
>> but this check is missing from some. Let's make it tree-wide
>> consistent. It will allow clock consumers to call clk_disable()
>> without NULL pointer check.
>>
>> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
>> Acked-by: Greg Ungerer <gerg@uclinux.org>
>> Acked-by: Wan Zongshun <mcuos.com@gmail.com>
>> ---
>>
>> I came back after a long pause.
>> You can see the discussion about the previous version:
>> https://www.linux-mips.org/archives/linux-mips/2016-04/msg00063.html
>>
>>
>> Changes in v3:
>> - Return only when clk is NULL. Do not take care of error pointer.
>>
>> Changes in v2:
>> - Rebase on Linux 4.6-rc1
>>
>> arch/arm/mach-mmp/clock.c | 3 +++
>> arch/arm/mach-w90x900/clock.c | 3 +++
>> arch/blackfin/mach-bf609/clock.c | 3 +++
>> arch/m68k/coldfire/clk.c | 4 ++++
>> arch/mips/bcm63xx/clk.c | 3 +++
>
Gentle ping...
If you are not keen on this,
shall I split it per-arch and send to each arch subsystem?
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [PATCH v6 1/2] clk: uniphier: add core support code for UniPhier clock driver
From: Masahiro Yamada @ 2016-09-16 7:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160907003258.GP12510@codeaurora.org>
Hi Stephen,
2016-09-07 9:32 GMT+09:00 Stephen Boyd <sboyd@codeaurora.org>:
> On 09/05, Masahiro Yamada wrote:
>> 2016-08-30 3:22 GMT+09:00 Stephen Boyd <sboyd@codeaurora.org>:
>> > On 08/29, Masahiro Yamada wrote:
>> >> I tried this, but it did not work.
>> >>
>> >> To make dev_get_regmap() work,
>> >> the parent device needs to call dev_regmap_init_mmio() beforehand.
>> >>
>> >>
>> >> Since commit bdb0066df96e74a4002125467ebe459feff1ebef
>> >> (mfd: syscon: Decouple syscon interface from platform devices),
>> >> syscon_probe() is not called for platform devices,
>> >> so that never happens.
>> >>
>> >
>> > Ok. Is the syscon also a simple-mfd?
>> >
>> > It sounds like there's a device for the parent, but we've failed
>> > to attach a regmap to it. Maybe the core DT code should assign
>> > the regmap to the parent device when it creates it so that child
>> > devices don't need to know this detail? It could look for
>> > simple-mfd devices with compatible = "syscon" and then create the
>> > regmap? Here's a totally untested patch for that.
>> >
>>
>>
>> I was not quire sure about this,
>> but maybe worth submitting to DT subsystem?
>>
>> Anyway, I will go with syscon_node_to_regmap() for v7.
>> Of course, I am happy to replace it with dev_get_regmap()
>> when the issue is solved in the mainline.
>>
>
> Ok that's fine. Did my patch fix dev_get_regmap() for you though?
> That would be useful to know so that this patch can be merged in
> parallel to yours.
Sorry for my late reply.
Yup, your patch worked fine!
And, I've posted v7 for my SoC clk driver.
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [PATCH v7 2/2] clk: uniphier: add clock data for UniPhier SoCs
From: Masahiro Yamada @ 2016-09-16 7:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474011604-12577-1-git-send-email-yamada.masahiro@socionext.com>
Add clock data arrays for all UniPhier SoCs with a binding document.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/clock/uniphier-clock.txt | 134 ++++++++++++++++++
drivers/clk/uniphier/Makefile | 3 +
drivers/clk/uniphier/clk-uniphier-core.c | 91 +++++++++++++
drivers/clk/uniphier/clk-uniphier-mio.c | 101 ++++++++++++++
drivers/clk/uniphier/clk-uniphier-peri.c | 57 ++++++++
drivers/clk/uniphier/clk-uniphier-sys.c | 151 +++++++++++++++++++++
drivers/clk/uniphier/clk-uniphier.h | 13 ++
7 files changed, 550 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/uniphier-clock.txt
create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-sys.c
diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
new file mode 100644
index 0000000..c7179d3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
@@ -0,0 +1,134 @@
+UniPhier clock controller
+
+
+System clock
+------------
+
+Required properties:
+- compatible: should be one of the following:
+ "socionext,uniphier-sld3-clock" - for sLD3 SoC.
+ "socionext,uniphier-ld4-clock" - for LD4 SoC.
+ "socionext,uniphier-pro4-clock" - for Pro4 SoC.
+ "socionext,uniphier-sld8-clock" - for sLD8 SoC.
+ "socionext,uniphier-pro5-clock" - for Pro5 SoC.
+ "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
+ "socionext,uniphier-ld11-clock" - for LD11 SoC.
+ "socionext,uniphier-ld20-clock" - for LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+ sysctrl at 61840000 {
+ compatible = "socionext,uniphier-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x4000>;
+
+ clock {
+ compatible = "socionext,uniphier-ld20-clock";
+ #clock-cells = <1>;
+ };
+
+ other nodes ...
+ };
+
+Provided clocks:
+
+ 8: ST DMAC
+12: GIO (Giga bit stream I/O)
+14: USB3 ch0 host
+15: USB3 ch1 host
+16: USB3 ch0 PHY0
+17: USB3 ch0 PHY1
+20: USB3 ch1 PHY0
+21: USB3 ch1 PHY1
+
+
+Media I/O (MIO) clock
+---------------------
+
+Required properties:
+- compatible: should be one of the following:
+ "socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
+ "socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
+ "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
+ "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
+ "socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.
+ "socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.
+ "socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
+ "socionext,uniphier-ld20-mio-clock" - for LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+ mioctrl at 59810000 {
+ compatible = "socionext,uniphier-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+
+ clock {
+ compatible = "socionext,uniphier-ld20-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ other nodes ...
+ };
+
+Provided clocks:
+
+ 0: SD ch0 host
+ 1: eMMC host
+ 2: SD ch1 host
+ 7: MIO DMAC
+ 8: USB2 ch0 host
+ 9: USB2 ch1 host
+10: USB2 ch2 host
+11: USB2 ch3 host
+12: USB2 ch0 PHY
+13: USB2 ch1 PHY
+14: USB2 ch2 PHY
+15: USB2 ch3 PHY
+
+
+Peripheral clock
+----------------
+
+Required properties:
+- compatible: should be one of the following:
+ "socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
+ "socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
+ "socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
+ "socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
+ "socionext,uniphier-pro5-peri-clock" - for Pro5 SoC.
+ "socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
+ "socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
+ "socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+ perictrl at 59820000 {
+ compatible = "socionext,uniphier-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ clock {
+ compatible = "socionext,uniphier-ld20-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ other nodes ...
+ };
+
+Provided clocks:
+
+ 0: UART ch0
+ 1: UART ch1
+ 2: UART ch2
+ 3: UART ch3
+ 4: I2C ch0
+ 5: I2C ch1
+ 6: I2C ch2
+ 7: I2C ch3
+ 8: I2C ch4
+ 9: I2C ch5
+10: I2C ch6
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index 88a28ca..f27b3603 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -3,3 +3,6 @@ obj-y += clk-uniphier-fixed-factor.o
obj-y += clk-uniphier-fixed-rate.o
obj-y += clk-uniphier-gate.o
obj-y += clk-uniphier-mux.o
+obj-y += clk-uniphier-sys.o
+obj-y += clk-uniphier-mio.o
+obj-y += clk-uniphier-peri.o
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index a6e2a94..5ffb898 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -109,6 +109,97 @@ static int uniphier_clk_remove(struct platform_device *pdev)
}
static const struct of_device_id uniphier_clk_match[] = {
+ /* System clock */
+ {
+ .compatible = "socionext,uniphier-ld4-clock",
+ .data = uniphier_ld4_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-clock",
+ .data = uniphier_pro4_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-clock",
+ .data = uniphier_sld8_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-clock",
+ .data = uniphier_pro5_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-clock",
+ .data = uniphier_pxs2_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-clock",
+ .data = uniphier_ld11_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-clock",
+ .data = uniphier_ld20_sys_clk_data,
+ },
+ /* Media I/O clock */
+ {
+ .compatible = "socionext,uniphier-sld3-mio-clock",
+ .data = uniphier_sld3_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld4-mio-clock",
+ .data = uniphier_sld3_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-mio-clock",
+ .data = uniphier_sld3_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-mio-clock",
+ .data = uniphier_sld3_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-mio-clock",
+ .data = uniphier_pro5_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-mio-clock",
+ .data = uniphier_pro5_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-mio-clock",
+ .data = uniphier_sld3_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-mio-clock",
+ .data = uniphier_pro5_mio_clk_data,
+ },
+ /* Peripheral clock */
+ {
+ .compatible = "socionext,uniphier-ld4-peri-clock",
+ .data = uniphier_ld4_peri_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-peri-clock",
+ .data = uniphier_pro4_peri_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-peri-clock",
+ .data = uniphier_ld4_peri_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-peri-clock",
+ .data = uniphier_pro4_peri_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-peri-clock",
+ .data = uniphier_pro4_peri_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-peri-clock",
+ .data = uniphier_pro4_peri_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-peri-clock",
+ .data = uniphier_pro4_peri_clk_data,
+ },
{ /* sentinel */ }
};
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
new file mode 100644
index 0000000..6aa7ec7
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "clk-uniphier.h"
+
+#define UNIPHIER_MIO_CLK_SD_FIXED \
+ UNIPHIER_CLK_FACTOR("sd-44m", -1, "sd-133m", 1, 3), \
+ UNIPHIER_CLK_FACTOR("sd-33m", -1, "sd-200m", 1, 6), \
+ UNIPHIER_CLK_FACTOR("sd-50m", -1, "sd-200m", 1, 4), \
+ UNIPHIER_CLK_FACTOR("sd-67m", -1, "sd-200m", 1, 3), \
+ UNIPHIER_CLK_FACTOR("sd-100m", -1, "sd-200m", 1, 2), \
+ UNIPHIER_CLK_FACTOR("sd-40m", -1, "sd-200m", 1, 5), \
+ UNIPHIER_CLK_FACTOR("sd-25m", -1, "sd-200m", 1, 8), \
+ UNIPHIER_CLK_FACTOR("sd-22m", -1, "sd-133m", 1, 6)
+
+#define UNIPHIER_MIO_CLK_SD(_idx, ch) \
+ { \
+ .name = "sd" #ch "-sel", \
+ .type = UNIPHIER_CLK_TYPE_MUX, \
+ .idx = -1, \
+ .data.mux = { \
+ .parent_names = { \
+ "sd-44m", \
+ "sd-33m", \
+ "sd-50m", \
+ "sd-67m", \
+ "sd-100m", \
+ "sd-40m", \
+ "sd-25m", \
+ "sd-22m", \
+ }, \
+ .num_parents = 8, \
+ .reg = 0x30 + 0x200 * (ch), \
+ .masks = { \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00001300, \
+ 0x00001300, \
+ 0x00001300, \
+ 0x00001300, \
+ }, \
+ .vals = { \
+ 0x00000000, \
+ 0x00010000, \
+ 0x00020000, \
+ 0x00030000, \
+ 0x00001000, \
+ 0x00001100, \
+ 0x00001200, \
+ 0x00001300, \
+ }, \
+ }, \
+ }, \
+ UNIPHIER_CLK_GATE("sd" #ch, (_idx), "sd" #ch "-sel", 0x20 + 0x200 * (ch), 8)
+
+#define UNIPHIER_MIO_CLK_USB2(idx, ch) \
+ UNIPHIER_CLK_GATE("usb2" #ch, (idx), "usb2", 0x20 + 0x200 * (ch), 28)
+
+#define UNIPHIER_MIO_CLK_USB2_PHY(idx, ch) \
+ UNIPHIER_CLK_GATE("usb2" #ch "-phy", (idx), "usb2", 0x20 + 0x200 * (ch), 29)
+
+#define UNIPHIER_MIO_CLK_DMAC(idx) \
+ UNIPHIER_CLK_GATE("miodmac", (idx), "stdmac", 0x20, 25)
+
+const struct uniphier_clk_data uniphier_sld3_mio_clk_data[] = {
+ UNIPHIER_MIO_CLK_SD_FIXED,
+ UNIPHIER_MIO_CLK_SD(0, 0),
+ UNIPHIER_MIO_CLK_SD(1, 1),
+ UNIPHIER_MIO_CLK_SD(2, 2),
+ UNIPHIER_MIO_CLK_DMAC(7),
+ UNIPHIER_MIO_CLK_USB2(8, 0),
+ UNIPHIER_MIO_CLK_USB2(9, 1),
+ UNIPHIER_MIO_CLK_USB2(10, 2),
+ UNIPHIER_MIO_CLK_USB2(11, 3),
+ UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
+ UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
+ UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
+ UNIPHIER_MIO_CLK_USB2_PHY(15, 3),
+ { /* sentinel */ }
+};
+
+const struct uniphier_clk_data uniphier_pro5_mio_clk_data[] = {
+ UNIPHIER_MIO_CLK_SD_FIXED,
+ UNIPHIER_MIO_CLK_SD(0, 0),
+ UNIPHIER_MIO_CLK_SD(1, 1),
+ { /* sentinel */ }
+};
diff --git a/drivers/clk/uniphier/clk-uniphier-peri.c b/drivers/clk/uniphier/clk-uniphier-peri.c
new file mode 100644
index 0000000..521c80e
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-peri.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "clk-uniphier.h"
+
+#define UNIPHIER_PERI_CLK_UART(idx, ch) \
+ UNIPHIER_CLK_GATE("uart" #ch, (idx), "uart", 0x24, 19 + (ch))
+
+#define UNIPHIER_PERI_CLK_I2C_COMMON \
+ UNIPHIER_CLK_GATE("i2c-common", -1, "i2c", 0x20, 1)
+
+#define UNIPHIER_PERI_CLK_I2C(idx, ch) \
+ UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c-common", 0x24, 5 + (ch))
+
+#define UNIPHIER_PERI_CLK_FI2C(idx, ch) \
+ UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
+
+const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
+ UNIPHIER_PERI_CLK_UART(0, 0),
+ UNIPHIER_PERI_CLK_UART(1, 1),
+ UNIPHIER_PERI_CLK_UART(2, 2),
+ UNIPHIER_PERI_CLK_UART(3, 3),
+ UNIPHIER_PERI_CLK_I2C_COMMON,
+ UNIPHIER_PERI_CLK_I2C(4, 0),
+ UNIPHIER_PERI_CLK_I2C(5, 1),
+ UNIPHIER_PERI_CLK_I2C(6, 2),
+ UNIPHIER_PERI_CLK_I2C(7, 3),
+ UNIPHIER_PERI_CLK_I2C(8, 4),
+ { /* sentinel */ }
+};
+
+const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
+ UNIPHIER_PERI_CLK_UART(0, 0),
+ UNIPHIER_PERI_CLK_UART(1, 1),
+ UNIPHIER_PERI_CLK_UART(2, 2),
+ UNIPHIER_PERI_CLK_UART(3, 3),
+ UNIPHIER_PERI_CLK_FI2C(4, 0),
+ UNIPHIER_PERI_CLK_FI2C(5, 1),
+ UNIPHIER_PERI_CLK_FI2C(6, 2),
+ UNIPHIER_PERI_CLK_FI2C(7, 3),
+ UNIPHIER_PERI_CLK_FI2C(8, 4),
+ UNIPHIER_PERI_CLK_FI2C(9, 5),
+ UNIPHIER_PERI_CLK_FI2C(10, 6),
+ { /* sentinel */ }
+};
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
new file mode 100644
index 0000000..5d02999
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/stddef.h>
+
+#include "clk-uniphier.h"
+
+#define UNIPHIER_SLD3_SYS_CLK_SD \
+ UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
+ UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
+
+#define UNIPHIER_PRO5_SYS_CLK_SD \
+ UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
+ UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
+
+#define UNIPHIER_LD20_SYS_CLK_SD \
+ UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
+ UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
+
+#define UNIPHIER_SLD3_SYS_CLK_STDMAC(idx) \
+ UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
+
+#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
+ UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
+
+#define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
+ UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
+
+#define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
+ UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
+
+const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = {
+ UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
+ UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
+ UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
+ UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
+ UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
+ UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
+ UNIPHIER_SLD3_SYS_CLK_SD,
+ UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
+ UNIPHIER_SLD3_SYS_CLK_STDMAC(8),
+ { /* sentinel */ }
+};
+
+const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
+ UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
+ UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
+ UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
+ UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
+ UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
+ UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
+ UNIPHIER_SLD3_SYS_CLK_SD,
+ UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
+ UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
+ { /* sentinel */ }
+};
+
+const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
+ UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
+ UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
+ UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
+ UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
+ UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
+ UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
+ UNIPHIER_SLD3_SYS_CLK_SD,
+ UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
+ UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
+ UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
+ UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
+ UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
+ { /* sentinel */ }
+};
+
+const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
+ UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
+ UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
+ UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
+ UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
+ UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
+ UNIPHIER_SLD3_SYS_CLK_SD,
+ UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
+ UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
+ { /* sentinel */ }
+};
+
+const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
+ UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
+ UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
+ UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */
+ UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
+ UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
+ UNIPHIER_PRO5_SYS_CLK_SD,
+ UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC */
+ UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
+ UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
+ UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
+ { /* sentinel */ }
+};
+
+const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
+ UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
+ UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
+ UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
+ UNIPHIER_PRO5_SYS_CLK_SD,
+ UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, RLE */
+ /* GIO is always clock-enabled: no function for 0x2104 bit6 */
+ UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
+ UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
+ /* The document mentions 0x2104 bit 18, but not functional */
+ UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
+ UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
+ { /* sentinel */ }
+};
+
+const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
+ UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
+ UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
+ UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
+ UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
+ UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
+ { /* sentinel */ }
+};
+
+const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
+ UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
+ UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
+ UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
+ UNIPHIER_LD20_SYS_CLK_SD,
+ UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */
+ /* GIO is always clock-enabled: no function for 0x210c bit5 */
+ /*
+ * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
+ * We do not use bit 15 here.
+ */
+ UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
+ UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
+ UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
+ { /* sentinel */ }
+};
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
index 3e354e9..3ae1840 100644
--- a/drivers/clk/uniphier/clk-uniphier.h
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -106,4 +106,17 @@ struct clk_hw *uniphier_clk_register_mux(struct device *dev,
const char *name,
const struct uniphier_clk_mux_data *data);
+extern const struct uniphier_clk_data uniphier_sld3_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_ld4_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_pro4_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_sld8_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
+extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
+extern const struct uniphier_clk_data uniphier_pro5_mio_clk_data[];
+extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
+extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
+
#endif /* __CLK_UNIPHIER_H__ */
--
1.9.1
^ permalink raw reply related
* [PATCH v7 1/2] clk: uniphier: add core support code for UniPhier clock driver
From: Masahiro Yamada @ 2016-09-16 7:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474011604-12577-1-git-send-email-yamada.masahiro@socionext.com>
This includes UniPhier clock driver code, except SoC-specific
data arrays.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
MAINTAINERS | 1 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/uniphier/Kconfig | 9 ++
drivers/clk/uniphier/Makefile | 5 +
drivers/clk/uniphier/clk-uniphier-core.c | 123 +++++++++++++++++++++++
drivers/clk/uniphier/clk-uniphier-fixed-factor.c | 48 +++++++++
drivers/clk/uniphier/clk-uniphier-fixed-rate.c | 47 +++++++++
drivers/clk/uniphier/clk-uniphier-gate.c | 97 ++++++++++++++++++
drivers/clk/uniphier/clk-uniphier-mux.c | 95 +++++++++++++++++
drivers/clk/uniphier/clk-uniphier.h | 109 ++++++++++++++++++++
11 files changed, 536 insertions(+)
create mode 100644 drivers/clk/uniphier/Kconfig
create mode 100644 drivers/clk/uniphier/Makefile
create mode 100644 drivers/clk/uniphier/clk-uniphier-core.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-fixed-factor.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-fixed-rate.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-gate.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-mux.c
create mode 100644 drivers/clk/uniphier/clk-uniphier.h
diff --git a/MAINTAINERS b/MAINTAINERS
index ef47152..c205e1a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1839,6 +1839,7 @@ F: arch/arm/mach-uniphier/
F: arch/arm/mm/cache-uniphier.c
F: arch/arm64/boot/dts/socionext/
F: drivers/bus/uniphier-system-bus.c
+F: drivers/clk/uniphier/
F: drivers/i2c/busses/i2c-uniphier*
F: drivers/pinctrl/uniphier/
F: drivers/reset/reset-uniphier.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index e2d9bd7..584c10d 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -218,5 +218,6 @@ source "drivers/clk/samsung/Kconfig"
source "drivers/clk/sunxi-ng/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
+source "drivers/clk/uniphier/Kconfig"
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3b6f9cf..7d66cef 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -86,6 +86,7 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_SUNXI) += sunxi-ng/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
+obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
obj-$(CONFIG_X86) += x86/
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
new file mode 100644
index 0000000..5512377
--- /dev/null
+++ b/drivers/clk/uniphier/Kconfig
@@ -0,0 +1,9 @@
+config CLK_UNIPHIER
+ bool "Clock driver for UniPhier SoCs"
+ depends on ARCH_UNIPHIER || COMPILE_TEST
+ depends on OF && MFD_SYSCON
+ default ARCH_UNIPHIER
+ help
+ Support for clock controllers on UniPhier SoCs.
+ Say Y if you want to control clocks provided by System Control
+ block, Media I/O block, Peripheral Block.
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
new file mode 100644
index 0000000..88a28ca
--- /dev/null
+++ b/drivers/clk/uniphier/Makefile
@@ -0,0 +1,5 @@
+obj-y += clk-uniphier-core.o
+obj-y += clk-uniphier-fixed-factor.o
+obj-y += clk-uniphier-fixed-rate.o
+obj-y += clk-uniphier-gate.o
+obj-y += clk-uniphier-mux.o
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
new file mode 100644
index 0000000..a6e2a94
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-uniphier.h"
+
+static struct clk_hw *uniphier_clk_register(struct device *dev,
+ struct regmap *regmap,
+ const struct uniphier_clk_data *data)
+{
+ switch (data->type) {
+ case UNIPHIER_CLK_TYPE_FIXED_FACTOR:
+ return uniphier_clk_register_fixed_factor(dev, data->name,
+ &data->data.factor);
+ case UNIPHIER_CLK_TYPE_FIXED_RATE:
+ return uniphier_clk_register_fixed_rate(dev, data->name,
+ &data->data.rate);
+ case UNIPHIER_CLK_TYPE_GATE:
+ return uniphier_clk_register_gate(dev, regmap, data->name,
+ &data->data.gate);
+ case UNIPHIER_CLK_TYPE_MUX:
+ return uniphier_clk_register_mux(dev, regmap, data->name,
+ &data->data.mux);
+ default:
+ dev_err(dev, "unsupported clock type\n");
+ return ERR_PTR(-EINVAL);
+ }
+}
+
+static int uniphier_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct clk_hw_onecell_data *hw_data;
+ const struct uniphier_clk_data *p, *data;
+ struct regmap *regmap;
+ struct device_node *parent;
+ int clk_num = 0;
+
+ data = of_device_get_match_data(dev);
+ if (WARN_ON(!data))
+ return -EINVAL;
+
+ parent = of_get_parent(dev->of_node); /* parent should be syscon node */
+ regmap = syscon_node_to_regmap(parent);
+ of_node_put(parent);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "failed to get regmap (error %ld)\n",
+ PTR_ERR(regmap));
+ return PTR_ERR(regmap);
+ }
+
+ for (p = data; p->name; p++)
+ clk_num = max(clk_num, p->idx + 1);
+
+ hw_data = devm_kzalloc(dev,
+ sizeof(*hw_data) + clk_num * sizeof(struct clk_hw *),
+ GFP_KERNEL);
+ if (!hw_data)
+ return -ENOMEM;
+
+ hw_data->num = clk_num;
+
+ /* avoid returning NULL for unused idx */
+ for (; clk_num >= 0; clk_num--)
+ hw_data->hws[clk_num] = ERR_PTR(-EINVAL);
+
+ for (p = data; p->name; p++) {
+ struct clk_hw *hw;
+
+ dev_dbg(dev, "register %s (index=%d)\n", p->name, p->idx);
+ hw = uniphier_clk_register(dev, regmap, p);
+ if (IS_ERR(hw)) {
+ dev_err(dev, "failed to register %s (error %ld)\n",
+ p->name, PTR_ERR(hw));
+ return PTR_ERR(hw);
+ }
+
+ if (p->idx >= 0)
+ hw_data->hws[p->idx] = hw;
+ }
+
+ return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+ hw_data);
+}
+
+static int uniphier_clk_remove(struct platform_device *pdev)
+{
+ of_clk_del_provider(pdev->dev.of_node);
+
+ return 0;
+}
+
+static const struct of_device_id uniphier_clk_match[] = {
+ { /* sentinel */ }
+};
+
+static struct platform_driver uniphier_clk_driver = {
+ .probe = uniphier_clk_probe,
+ .remove = uniphier_clk_remove,
+ .driver = {
+ .name = "uniphier-clk",
+ .of_match_table = uniphier_clk_match,
+ },
+};
+builtin_platform_driver(uniphier_clk_driver);
diff --git a/drivers/clk/uniphier/clk-uniphier-fixed-factor.c b/drivers/clk/uniphier/clk-uniphier-fixed-factor.c
new file mode 100644
index 0000000..da2d9f4
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-fixed-factor.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+
+#include "clk-uniphier.h"
+
+struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
+ const char *name,
+ const struct uniphier_clk_fixed_factor_data *data)
+{
+ struct clk_fixed_factor *fix;
+ struct clk_init_data init;
+ int ret;
+
+ fix = devm_kzalloc(dev, sizeof(*fix), GFP_KERNEL);
+ if (!fix)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &clk_fixed_factor_ops;
+ init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
+ init.parent_names = data->parent_name ? &data->parent_name : NULL;
+ init.num_parents = data->parent_name ? 1 : 0;
+
+ fix->mult = data->mult;
+ fix->div = data->div;
+ fix->hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &fix->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &fix->hw;
+}
diff --git a/drivers/clk/uniphier/clk-uniphier-fixed-rate.c b/drivers/clk/uniphier/clk-uniphier-fixed-rate.c
new file mode 100644
index 0000000..0ad0d46
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-fixed-rate.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+
+#include "clk-uniphier.h"
+
+struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
+ const char *name,
+ const struct uniphier_clk_fixed_rate_data *data)
+{
+ struct clk_fixed_rate *fixed;
+ struct clk_init_data init;
+ int ret;
+
+ /* allocate fixed-rate clock */
+ fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
+ if (!fixed)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &clk_fixed_rate_ops;
+ init.parent_names = NULL;
+ init.num_parents = 0;
+
+ fixed->fixed_rate = data->fixed_rate;
+ fixed->hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &fixed->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &fixed->hw;
+}
diff --git a/drivers/clk/uniphier/clk-uniphier-gate.c b/drivers/clk/uniphier/clk-uniphier-gate.c
new file mode 100644
index 0000000..49142d4
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-gate.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+
+#include "clk-uniphier.h"
+
+struct uniphier_clk_gate {
+ struct clk_hw hw;
+ struct regmap *regmap;
+ unsigned int reg;
+ unsigned int bit;
+};
+
+#define to_uniphier_clk_gate(_hw) \
+ container_of(_hw, struct uniphier_clk_gate, hw)
+
+static int uniphier_clk_gate_endisable(struct clk_hw *hw, int enable)
+{
+ struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
+
+ return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit),
+ enable ? BIT(gate->bit) : 0);
+}
+
+static int uniphier_clk_gate_enable(struct clk_hw *hw)
+{
+ return uniphier_clk_gate_endisable(hw, 1);
+}
+
+static void uniphier_clk_gate_disable(struct clk_hw *hw)
+{
+ if (uniphier_clk_gate_endisable(hw, 0) < 0)
+ pr_warn("failed to disable clk\n");
+}
+
+static int uniphier_clk_gate_is_enabled(struct clk_hw *hw)
+{
+ struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
+ unsigned int val;
+
+ if (regmap_read(gate->regmap, gate->reg, &val) < 0)
+ pr_warn("is_enabled() may return wrong result\n");
+
+ return !!(val & BIT(gate->bit));
+}
+
+static const struct clk_ops uniphier_clk_gate_ops = {
+ .enable = uniphier_clk_gate_enable,
+ .disable = uniphier_clk_gate_disable,
+ .is_enabled = uniphier_clk_gate_is_enabled,
+};
+
+struct clk_hw *uniphier_clk_register_gate(struct device *dev,
+ struct regmap *regmap,
+ const char *name,
+ const struct uniphier_clk_gate_data *data)
+{
+ struct uniphier_clk_gate *gate;
+ struct clk_init_data init;
+ int ret;
+
+ gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &uniphier_clk_gate_ops;
+ init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
+ init.parent_names = data->parent_name ? &data->parent_name : NULL;
+ init.num_parents = data->parent_name ? 1 : 0;
+
+ gate->regmap = regmap;
+ gate->reg = data->reg;
+ gate->bit = data->bit;
+ gate->hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &gate->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &gate->hw;
+}
diff --git a/drivers/clk/uniphier/clk-uniphier-mux.c b/drivers/clk/uniphier/clk-uniphier-mux.c
new file mode 100644
index 0000000..15a2f2c
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-mux.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+
+#include "clk-uniphier.h"
+
+struct uniphier_clk_mux {
+ struct clk_hw hw;
+ struct regmap *regmap;
+ unsigned int reg;
+ const unsigned int *masks;
+ const unsigned int *vals;
+};
+
+#define to_uniphier_clk_mux(_hw) container_of(_hw, struct uniphier_clk_mux, hw)
+
+static int uniphier_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
+
+ return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index],
+ mux->vals[index]);
+}
+
+static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
+ int num_parents = clk_hw_get_num_parents(hw);
+ int ret;
+ u32 val;
+ u8 i;
+
+ ret = regmap_read(mux->regmap, mux->reg, &val);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < num_parents; i++)
+ if ((mux->masks[i] & val) == mux->vals[i])
+ return i;
+
+ return -EINVAL;
+}
+
+static const struct clk_ops uniphier_clk_mux_ops = {
+ .determine_rate = __clk_mux_determine_rate,
+ .set_parent = uniphier_clk_mux_set_parent,
+ .get_parent = uniphier_clk_mux_get_parent,
+};
+
+struct clk_hw *uniphier_clk_register_mux(struct device *dev,
+ struct regmap *regmap,
+ const char *name,
+ const struct uniphier_clk_mux_data *data)
+{
+ struct uniphier_clk_mux *mux;
+ struct clk_init_data init;
+ int ret;
+
+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &uniphier_clk_mux_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+ init.parent_names = data->parent_names;
+ init.num_parents = data->num_parents,
+
+ mux->regmap = regmap;
+ mux->reg = data->reg;
+ mux->masks = data->masks;
+ mux->vals = data->vals;
+ mux->hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &mux->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &mux->hw;
+}
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
new file mode 100644
index 0000000..3e354e9
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CLK_UNIPHIER_H__
+#define __CLK_UNIPHIER_H__
+
+struct clk_hw;
+struct device;
+struct regmap;
+
+#define UNIPHIER_CLK_MUX_MAX_PARENTS 8
+
+enum uniphier_clk_type {
+ UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ UNIPHIER_CLK_TYPE_FIXED_RATE,
+ UNIPHIER_CLK_TYPE_GATE,
+ UNIPHIER_CLK_TYPE_MUX,
+};
+
+struct uniphier_clk_fixed_factor_data {
+ const char *parent_name;
+ unsigned int mult;
+ unsigned int div;
+};
+
+struct uniphier_clk_fixed_rate_data {
+ unsigned long fixed_rate;
+};
+
+struct uniphier_clk_gate_data {
+ const char *parent_name;
+ unsigned int reg;
+ unsigned int bit;
+};
+
+struct uniphier_clk_mux_data {
+ const char *parent_names[UNIPHIER_CLK_MUX_MAX_PARENTS];
+ unsigned int num_parents;
+ unsigned int reg;
+ unsigned int masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
+ unsigned int vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
+};
+
+struct uniphier_clk_data {
+ const char *name;
+ enum uniphier_clk_type type;
+ int idx;
+ union {
+ struct uniphier_clk_fixed_factor_data factor;
+ struct uniphier_clk_fixed_rate_data rate;
+ struct uniphier_clk_gate_data gate;
+ struct uniphier_clk_mux_data mux;
+ } data;
+};
+
+#define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div) \
+ { \
+ .name = (_name), \
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR, \
+ .idx = (_idx), \
+ .data.factor = { \
+ .parent_name = (_parent), \
+ .mult = (_mult), \
+ .div = (_div), \
+ }, \
+ }
+
+
+#define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \
+ { \
+ .name = (_name), \
+ .type = UNIPHIER_CLK_TYPE_GATE, \
+ .idx = (_idx), \
+ .data.gate = { \
+ .parent_name = (_parent), \
+ .reg = (_reg), \
+ .bit = (_bit), \
+ }, \
+ }
+
+
+struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
+ const char *name,
+ const struct uniphier_clk_fixed_factor_data *data);
+struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
+ const char *name,
+ const struct uniphier_clk_fixed_rate_data *data);
+struct clk_hw *uniphier_clk_register_gate(struct device *dev,
+ struct regmap *regmap,
+ const char *name,
+ const struct uniphier_clk_gate_data *data);
+struct clk_hw *uniphier_clk_register_mux(struct device *dev,
+ struct regmap *regmap,
+ const char *name,
+ const struct uniphier_clk_mux_data *data);
+
+#endif /* __CLK_UNIPHIER_H__ */
--
1.9.1
^ permalink raw reply related
* [PATCH v7 0/2] clk: uniphier: add clock drivers for UniPhier SoCs
From: Masahiro Yamada @ 2016-09-16 7:40 UTC (permalink / raw)
To: linux-arm-kernel
I split into two patches to make review easier.
1/2: core support code
2/2: data arrays
Changes in v7:
- Add static to probe/remove callbacks
- Fill unused idx of clk array with ERR_PTR(-EINVAL)
- Use of_device_get_match_data() instead of of_match_node()
- Remove CLK_IS_BASIC flag
- Make drivers built-in only
- Remove bogus #include <linux/bitops.h>
Changes in v6:
- Fix provided clock description a bit
Changes in v5:
- Assign each gating register bit with a separate clk
- Fix examples in binding document to add specific compatible
- Document provided clocks for system clock
Changes in v4:
- Unify module_platform_driver() boilerplate into a single place
- Add binding document
- Add USB3 clocks
Changes in v3:
- Change to platform drivers instead of OF_CLK_DECLARE
- Split into a core part + SoC drivers
SoC drivers just consist of tables of SoC-specific data.
This allows reviewer to concentrate on the core-part
- Hard-code parent clock names for cascading
Changes in v2:
- split emmc_hw_reset
- make SD clock rate-controllable
- add CLK_SET_RATE_PARENT flag to mux, gate, fixed-factor clocks
Masahiro Yamada (2):
clk: uniphier: add core support code for UniPhier clock driver
clk: uniphier: add clock data for UniPhier SoCs
.../devicetree/bindings/clock/uniphier-clock.txt | 134 +++++++++++++
MAINTAINERS | 1 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/uniphier/Kconfig | 9 +
drivers/clk/uniphier/Makefile | 8 +
drivers/clk/uniphier/clk-uniphier-core.c | 214 +++++++++++++++++++++
drivers/clk/uniphier/clk-uniphier-fixed-factor.c | 48 +++++
drivers/clk/uniphier/clk-uniphier-fixed-rate.c | 47 +++++
drivers/clk/uniphier/clk-uniphier-gate.c | 97 ++++++++++
drivers/clk/uniphier/clk-uniphier-mio.c | 101 ++++++++++
drivers/clk/uniphier/clk-uniphier-mux.c | 95 +++++++++
drivers/clk/uniphier/clk-uniphier-peri.c | 57 ++++++
drivers/clk/uniphier/clk-uniphier-sys.c | 151 +++++++++++++++
drivers/clk/uniphier/clk-uniphier.h | 122 ++++++++++++
15 files changed, 1086 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/uniphier-clock.txt
create mode 100644 drivers/clk/uniphier/Kconfig
create mode 100644 drivers/clk/uniphier/Makefile
create mode 100644 drivers/clk/uniphier/clk-uniphier-core.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-fixed-factor.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-fixed-rate.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-gate.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-mux.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-sys.c
create mode 100644 drivers/clk/uniphier/clk-uniphier.h
--
1.9.1
^ permalink raw reply
* [PATCH v6 2/3] ARM: dts: add TOPEET itop elite based board
From: Krzysztof Kozlowski @ 2016-09-16 7:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473285535-21996-3-git-send-email-ayaka@soulik.info>
On 09/07/2016 11:58 PM, Randy Li wrote:
> The TOPEET itop exynos 4412 have three versions base board. The
> Elite version is the cheap one without too much peripheral devices
> on it.
>
> Currently supported are serial console, wired networking(USB),
> USB OTG in peripheral mode, USB host, SD storage, GPIO buttons,
> PWM beeper, ADC and LEDs. The WM8960 analog audio codec is also
> enabled.
>
> The FIMC is not used for camera currently, I enabled it just for a
> colorspace convertor.
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> ---
> .../bindings/arm/samsung/samsung-boards.txt | 3 +
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/exynos4412-itop-elite.dts | 239 +++++++++++++++++++++
> 3 files changed, 243 insertions(+)
> create mode 100644 arch/arm/boot/dts/exynos4412-itop-elite.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> index 0ea7f14..c7159ac 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> @@ -22,6 +22,9 @@ Required root node properties:
> * FriendlyARM
> - "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM
> TINY4412 board.
> + * TOPEET
> + - "topeet,itop4412-elite" - for Exynos4412-based TOPEET
> + Elite base board.
>
> * Google
> - "google,pi" - for Exynos5800-based Google Peach Pi
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 207f96f..0b39d00 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \
> exynos4210-smdkv310.dtb \
> exynos4210-trats.dtb \
> exynos4210-universal_c210.dtb \
> + exynos4412-itop-elite.dtb \
> exynos4412-odroidu3.dtb \
> exynos4412-odroidx.dtb \
> exynos4412-odroidx2.dtb \
> diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
> new file mode 100644
> index 0000000..dd83689
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
> @@ -0,0 +1,239 @@
> +/*
> + * TOPEET's Exynos4412 based itop board device tree source
> + *
> + * Copyright (c) 2016 SUMOMO Computer Association
> + * https://www.sumomo.mobi
> + * Randy Li <ayaka@soulik.info>
> + *
> + * Device tree source file for TOPEET iTop Exynos 4412 core board
> + * which is based on Samsung's Exynos4412 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +#include <dt-bindings/sound/samsung-i2s.h>
> +#include "exynos4412-itop-scp-core.dtsi"
> +
> +/ {
> + model = "TOPEET iTop 4412 Elite board based on Exynos4412";
> + compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4";
> +
> + chosen {
> + bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait";
> + stdout-path = "serial2:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led2 {
> + label = "red:system";
> + gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + linux,default-trigger = "heartbeat";
> + };
> +
> + led3 {
> + label = "red:user";
> + gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + home {
> + label = "GPIO Key Home";
> + linux,code = <KEY_HOME>;
> + gpios = <&gpx1 1 GPIO_ACTIVE_LOW>;
> + };
> +
> + back {
> + label = "GPIO Key Back";
> + linux,code = <KEY_BACK>;
> + gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
> + };
> +
> + sleep {
> + label = "GPIO Key Sleep";
> + linux,code = <KEY_POWER>;
> + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
> + };
> +
> + vol-up {
> + label = "GPIO Key Vol+";
> + linux,code = <KEY_UP>;
> + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
> + };
> +
> + vol-down {
> + label = "GPIO Key Vol-";
> + linux,code = <KEY_DOWN>;
> + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "wm-sound";
> +
> + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
> + <&clock_audss EXYNOS_MOUT_I2S>,
> + <&clock_audss EXYNOS_DOUT_SRP>,
> + <&clock_audss EXYNOS_DOUT_AUD_BUS>;
> + assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
> + <&clock_audss EXYNOS_MOUT_AUDSS>;
> + assigned-clock-rates = <0>,
> + <0>,
> + <112896000>,
> + <11289600>;
> +
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&link0_codec>;
> + simple-audio-card,frame-master = <&link0_codec>;
> +
> + simple-audio-card,widgets =
> + "Microphone", "Mic Jack",
> + "Line", "Line In",
> + "Line", "Line Out",
> + "Speaker", "Speaker",
> + "Headphone", "Headphone Jack";
> + simple-audio-card,routing =
> + "Headphone Jack", "HP_L",
> + "Headphone Jack", "HP_R",
> + "Speaker", "SPK_LP",
> + "Speaker", "SPK_LN",
> + "Speaker", "SPK_RP",
> + "Speaker", "SPK_RN",
> + "LINPUT1", "Mic Jack",
> + "LINPUT3", "Mic Jack",
> + "RINPUT1", "Mic Jack",
> + "RINPUT2", "Mic Jack";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&i2s0 0>;
> + };
> +
> + link0_codec: simple-audio-card,codec {
> + sound-dai = <&codec>;
> + clocks = <&i2s0 CLK_I2S_CDCLK>;
> + system-clock-frequency = <11289600>;
> + };
> + };
> +
> + beep {
> + compatible = "pwm-beeper";
> + pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>;
I have serious doubts that you run this code... if it does not even
compile. Sorry, I cannot accept code that does not compile and was not
tested.
Please, test your DTS on top of current Linux tree, which would be one of:
1. Linus' master branch: v4.8-rc6,
2. one of my branches (for-next, next/dt etc),
3. recent linux-next.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 0/2] ARM: dts: s5p: Remove skeleton.dtsi usage and fix memory node DTC warnings
From: Krzysztof Kozlowski @ 2016-09-16 7:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473348361-15784-1-git-send-email-javier@osg.samsung.com>
On 09/08/2016 05:25 PM, Javier Martinez Canillas wrote:
> Hello,
>
> This small patch series is similar to [0] that removed the skeleton.dtsi
> usage for Exynos DTS. This series do the same for S5PV210 boards DTS.
>
> [0]: http://www.spinics.net/lists/kernel/msg2333268.html
>
> Best regards,
> Javier
>
>
> Javier Martinez Canillas (2):
> ARM: dts: s5p: Remove skeleton.dtsi inclusion for S5PV210
> ARM: dts: s5p: Add missing unit name to memory nodes for S5PV210
> boards
Applied both, thanks.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v2 07/11] arm64/tracing: fix compat syscall handling
From: Marcin Nowakowski @ 2016-09-16 7:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474009887-7225-1-git-send-email-marcin.nowakowski@imgtec.com>
Add arch_syscall_addr for arm64 and define NR_compat_syscalls, as the
number of compat syscalls for arm64 exceeds the number defined by
NR_syscalls.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel at lists.infradead.org
---
arch/arm64/include/asm/ftrace.h | 12 +-----------
arch/arm64/include/asm/unistd.h | 1 +
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/ftrace.c | 16 ++++++++++++++++
4 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/ftrace.h b/arch/arm64/include/asm/ftrace.h
index caa955f..b57ff7c 100644
--- a/arch/arm64/include/asm/ftrace.h
+++ b/arch/arm64/include/asm/ftrace.h
@@ -41,17 +41,7 @@ static inline unsigned long ftrace_call_adjust(unsigned long addr)
#define ftrace_return_address(n) return_address(n)
-/*
- * Because AArch32 mode does not share the same syscall table with AArch64,
- * tracing compat syscalls may result in reporting bogus syscalls or even
- * hang-up, so just do not trace them.
- * See kernel/trace/trace_syscalls.c
- *
- * x86 code says:
- * If the user really wants these, then they should use the
- * raw syscall tracepoints with filtering.
- */
-#define ARCH_TRACE_IGNORE_COMPAT_SYSCALLS
+#define ARCH_COMPAT_SYSCALL_NUMBERS_OVERLAP 1
static inline bool arch_trace_is_compat_syscall(struct pt_regs *regs)
{
return is_compat_task();
diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h
index e78ac26..276d049 100644
--- a/arch/arm64/include/asm/unistd.h
+++ b/arch/arm64/include/asm/unistd.h
@@ -45,6 +45,7 @@
#define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE+5)
#define __NR_compat_syscalls 394
+#define NR_compat_syscalls (__NR_compat_syscalls)
#endif
#define __ARCH_WANT_SYS_CLONE
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 14f7b65..64a8c53 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -28,6 +28,7 @@ $(obj)/%.stub.o: $(obj)/%.o FORCE
arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
sys_compat.o entry32.o
arm64-obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o entry-ftrace.o
+arm64-obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o
arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o
arm64-obj-$(CONFIG_ARM64_MODULE_PLTS) += module-plts.o
arm64-obj-$(CONFIG_PERF_EVENTS) += perf_regs.o perf_callchain.o
diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c
index ebecf9a..53348d1 100644
--- a/arch/arm64/kernel/ftrace.c
+++ b/arch/arm64/kernel/ftrace.c
@@ -176,4 +176,20 @@ int ftrace_disable_ftrace_graph_caller(void)
return ftrace_modify_graph_caller(false);
}
#endif /* CONFIG_DYNAMIC_FTRACE */
+
#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
+
+#if (defined CONFIG_FTRACE_SYSCALLS) && (defined CONFIG_COMPAT)
+
+extern const void *sys_call_table[];
+extern const void *compat_sys_call_table[];
+
+unsigned long __init arch_syscall_addr(int nr, bool compat)
+{
+ if (compat)
+ return (unsigned long)compat_sys_call_table[nr];
+
+ return (unsigned long)sys_call_table[nr];
+}
+
+#endif /* CONFIG_FTRACE_SYSCALLS && CONFIG_COMPAT */
--
2.7.4
^ permalink raw reply related
* [GIT PULL] ARM: exynos: Fixes for v4.8, secound round
From: Krzysztof Kozlowski @ 2016-09-16 7:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CGME20160916071017eucas1p155978eec97e20211d9c54ef670e319eb@eucas1p1.samsung.com>
Hi,
Remaining fix for this release cycle. It waited in my tree for some time
because of travel.
Best regards,
Krzysztof
The following changes since commit 326dce0734b63c3b82b6a88e5645eab8b54c6692:
MAINTAINERS: Switch to kernel.org account for Krzysztof Kozlowski (2016-08-17 17:54:56 +0200)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-fixes-4.8-2
for you to fetch changes up to b030485220caf862c71db6fb8b8ad016ce7f7565:
ARM: EXYNOS: Clear OF_POPULATED flag from PMU node in IRQ init callback (2016-08-30 10:49:18 +0200)
----------------------------------------------------------------
1. A recent change in populating irqchip devices from Device Tree
broke Suspend to RAM on Exynos boards due to lack of probing of
PMU (Power Management Unit) driver. Multiple drivers attach to
the PMU's DT node: irqchip, clock controller and PMU platform
driver for handling suspend. The new irqchip code marked the
PMU's DT node as OF_POPULATED but we need to attach to this
node also PMU platform driver.
2. Add Javier as additional reviewer for Exynos patches.
----------------------------------------------------------------
Javier Martinez Canillas (2):
MAINTAINERS: Add myself as reviewer for Samsung Exynos support
ARM: EXYNOS: Clear OF_POPULATED flag from PMU node in IRQ init callback
MAINTAINERS | 1 +
arch/arm/mach-exynos/suspend.c | 6 ++++++
2 files changed, 7 insertions(+)
^ permalink raw reply
* [GIT PULL 2/2] arm64: X-Gene platforms DTS changes queued for 4.9
From: Duc Dang @ 2016-09-16 7:01 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Olof,
This is the DTS changes for X-Gene platforms targeted for 4.9.
The changes include:
+ X-Gene Soc PMU DTS entry from X-Gene PMU patch set of Tai Nguyen [1]
+ Follow up patch to enable DTS entry for SoC PMU on X-Gene v2
+ Correct PCIe legacy interrupt mode to level-active high
+ DTS entry for X-Gene hwmon (v4 acked by Guenter, DT binding document
and driver is in linux-next now [2])
+ DTS entries for X-Gene v2 CPU clock from X-Gene PMD clock patch set
(v3 already accepted by Stephen into clk-next [3])
Regards,
Duc Dang.
[1]: https://lkml.org/lkml/2016/7/15/563
[2]: http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/?id=893485e74c37669aeecf0b648dbfbd8e2f0471c3
[3]: https://lkml.org/lkml/2016/9/12/907
-------
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
https://github.com/AppliedMicro/xgene-next.git tags/xgene-dts-for-v4.9
for you to fetch changes up to 39936ae1ab1dee28cc1479294bd76d16f3ea7792:
arm64: dts: apm: Add DT node for APM X-Gene 2 CPU clocks (2016-09-15
11:19:39 -0700)
----------------------------------------------------------------
X-gene DTS changes queued for v4.9
This change set includes:
+ DTS entry to enable SoC PMU for X-Gene v1 SoC
+ DTS entry to enable SoC PMU for X-Gene v2 SoC
+ PCIe legacy interrupt polarity fix for X-Gene
+ X-Gene SoC hwmon DTS entry
+ DTS entries for X-Gene v2 CPU clock
----------------------------------------------------------------
Duc Dang (2):
arm64: dts: apm: Add APM X-Gene v2 SoC PMU DTS entries
arm64: dts: apm: Fix interrupt polarity for X-Gene PCIe legacy interrupts
Tai Nguyen (1):
arm64: dts: apm: Add APM X-Gene SoC PMU DTS entries
hotran (2):
arm64: dts: apm: Add X-Gene SoC hwmon to device tree
arm64: dts: apm: Add DT node for APM X-Gene 2 CPU clocks
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 135 +++++++++++++++++++++++++++--
arch/arm64/boot/dts/apm/apm-storm.dtsi | 103 +++++++++++++++++-----
2 files changed, 210 insertions(+), 28 deletions(-)
^ permalink raw reply
* [GIT PULL 1/2] arm64: X-Gene driver updates queued for 4.9
From: Duc Dang @ 2016-09-16 7:01 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Olof,
This is the driver updates for X-Gene platforms targeted for 4.9.
The change set includes:
+ X-Gene Soc PMU support patch set from Tai Nguyen (v10 reviewed by
Mark, DT binding document acked by Rob [1] and was suggested to merge
via am-soc tree by Will [2])
As we discussed, the X-Gene Soc PMU will go through arm-soc tree this
time because we don't have a dedicated tree for PMU drivers yet.
Starting from v4.10, PMU drivers will be collected by Will/Mark before
sending to arm-soc tree [3].
Regards,
Duc Dang.
[1]: https://lkml.org/lkml/2016/7/15/563
[2]: https://lkml.org/lkml/2016/7/20/224
[3]: http://www.spinics.net/lists/arm-kernel/msg532044.html
------
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
https://github.com/AppliedMicro/xgene-next.git tags/xgene-drivers-for-4.9
for you to fetch changes up to 832c927d119b5be3a01376b8e3033286eb5797e1:
perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver
(2016-09-15 11:20:55 -0700)
----------------------------------------------------------------
X-Gene driver changes queued for v4.9
This patch set includes:
+ X-Gene SoC Performance Monitoring Unit (PMU) driver
----------------------------------------------------------------
Tai Nguyen (3):
MAINTAINERS: Add entry for APM X-Gene SoC PMU driver
Documentation: Add documentation for APM X-Gene SoC PMU DTS binding
perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver
.../devicetree/bindings/perf/apm-xgene-pmu.txt | 112 ++
Documentation/perf/xgene-pmu.txt | 48 +
MAINTAINERS | 7 +
drivers/perf/Kconfig | 7 +
drivers/perf/Makefile | 1 +
drivers/perf/xgene_pmu.c | 1398 ++++++++++++++++++++
6 files changed, 1573 insertions(+)
create mode 100644 Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
create mode 100644 Documentation/perf/xgene-pmu.txt
create mode 100644 drivers/perf/xgene_pmu.c
^ permalink raw reply
* [GIT PULL 3/3] ZTE arm64 defconfig changes for 4.9
From: Shawn Guo @ 2016-09-16 6:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474008641-30859-1-git-send-email-shawnguo@kernel.org>
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/zte-defconfig64-4.9
for you to fetch changes up to ba1f4d81707ab30dd342024dfa2cf50bb8003ece:
arm64: defconfig: enable ZTE ZX related config (2016-09-16 14:28:39 +0800)
----------------------------------------------------------------
ZTE arm64 defconfig updates for 4.9:
- Enable ZTE ZX family support in arm64 defconfig
----------------------------------------------------------------
Jun Nie (1):
arm64: defconfig: enable ZTE ZX related config
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
^ permalink raw reply
* [GIT PULL 2/3] ZTE arm64 device tree changes for 4.9
From: Shawn Guo @ 2016-09-16 6:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474008641-30859-1-git-send-email-shawnguo@kernel.org>
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/zte-dt64-4.9
for you to fetch changes up to 2e673c7dc37a51f1c1cdabee22615916cbe0fc27:
arm64: dts: Add ZTE ZX296718 SoC dts and Makefile (2016-09-16 10:47:05 +0800)
----------------------------------------------------------------
ZTE arm64 device tree changes for 4.9:
- Add initial DTS support for ZTE ZX296718 SoC and ZX296718 EVB board.
----------------------------------------------------------------
Jun Nie (1):
arm64: dts: Add ZTE ZX296718 SoC dts and Makefile
Documentation/devicetree/bindings/arm/zte.txt | 24 +++
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/zte/Makefile | 5 +
arch/arm64/boot/dts/zte/zx296718-evb.dts | 64 ++++++
arch/arm64/boot/dts/zte/zx296718.dtsi | 292 ++++++++++++++++++++++++++
5 files changed, 386 insertions(+)
create mode 100644 arch/arm64/boot/dts/zte/Makefile
create mode 100644 arch/arm64/boot/dts/zte/zx296718-evb.dts
create mode 100644 arch/arm64/boot/dts/zte/zx296718.dtsi
^ permalink raw reply
* [GIT PULL 1/3] ZTE arm64 soc changes for 4.9
From: Shawn Guo @ 2016-09-16 6:50 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/zte-soc64-4.9
for you to fetch changes up to 12496aea0887fc067ad9ba0aa28798317f47a1e0:
arm64: add ZTE ZX SoC family (2016-09-16 14:30:20 +0800)
----------------------------------------------------------------
ZTE arm64 SoC changes for 4.9:
- Add a Kconfig option for ZTE ZX SoC family support
----------------------------------------------------------------
Jun Nie (1):
arm64: add ZTE ZX SoC family
arch/arm64/Kconfig.platforms | 5 +++++
1 file changed, 5 insertions(+)
^ permalink raw reply
* [PATCH v5 0/3] Add ZTE ZX296718 support
From: Shawn Guo @ 2016-09-16 6:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3220973.vrdeeLxHSS@wuerfel>
On Thu, Sep 15, 2016 at 03:24:06PM +0200, Arnd Bergmann wrote:
> On Tuesday, September 13, 2016 3:21:46 PM CEST Shawn Guo wrote:
> >
> > Reviewed-by: Shawn Guo <shawnguo@kernel.org>
> >
> > Arnd, Olof,
> >
> > If you like, I can help collect ZTE DTS patches to reduce your
> > maintenance burden, considering we have an established pull-request
> > work flow and I get ZTE platform on hands to test patches.
>
> Thanks, I think that would be a good idea. I was going to apply
> the patches manually, but I'll just wait for you to forward
> them to me.
I will send pull requests to you shortly. We will likely have more ZTE
DTS patches to come for the later releases, and doing so should ease
your life, I hope.
Shawn
^ permalink raw reply
* [PATCH v3 2/2] KVM: arm/arm64: Route vtimer events to user space
From: Alexander Graf @ 2016-09-16 6:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474007187-18673-1-git-send-email-agraf@suse.de>
We have 2 modes for dealing with interrupts in the ARM world. We can either
handle them all using hardware acceleration through the vgic or we can emulate
a gic in user space and only drive CPU IRQ pins from there.
Unfortunately, when driving IRQs from user space, we never tell user space
about timer events that may result in interrupt line state changes, so we
lose out on timer events if we run with user space gic emulation.
This patch fixes that by routing vtimer expiration events to user space.
With this patch I can successfully run edk2 and Linux with user space gic
emulation.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
v1 -> v2:
- Add back curly brace that got lost
v2 -> v3:
- Split into patch set
---
Documentation/virtual/kvm/api.txt | 24 +++++++-
arch/arm/include/asm/kvm_host.h | 3 +
arch/arm/kvm/arm.c | 22 ++++---
arch/arm64/include/asm/kvm_host.h | 3 +
include/uapi/linux/kvm.h | 14 +++++
virt/kvm/arm/arch_timer.c | 125 +++++++++++++++++++++++++++-----------
6 files changed, 149 insertions(+), 42 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
index 23937e0..dec1a78 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -3202,8 +3202,10 @@ struct kvm_run {
/* in */
__u8 request_interrupt_window;
-Request that KVM_RUN return when it becomes possible to inject external
+[x86] Request that KVM_RUN return when it becomes possible to inject external
interrupts into the guest. Useful in conjunction with KVM_INTERRUPT.
+[arm*] Bits set to 1 in here mask IRQ lines that would otherwise potentially
+trigger forever. Useful with KVM_CAP_ARM_TIMER.
__u8 padding1[7];
@@ -3519,6 +3521,16 @@ Hyper-V SynIC state change. Notification is used to remap SynIC
event/message pages and to enable/disable SynIC messages/events processing
in userspace.
+ /* KVM_EXIT_ARM_TIMER */
+ struct {
+ __u8 timesource;
+ } arm_timer;
+
+Indicates that a timer triggered that user space needs to handle and
+potentially mask with vcpu->run->request_interrupt_window to allow the
+guest to proceed. This only happens for timers that got enabled through
+KVM_CAP_ARM_TIMER.
+
/* Fix the size of the union. */
char padding[256];
};
@@ -3739,6 +3751,16 @@ Once this is done the KVM_REG_MIPS_VEC_* and KVM_REG_MIPS_MSA_* registers can be
accessed, and the Config5.MSAEn bit is accessible via the KVM API and also from
the guest.
+6.11 KVM_CAP_ARM_TIMER
+
+Architectures: arm, arm64
+Target: vcpu
+Parameters: args[0] contains a bitmap of timers to enable
+
+This capability allows to route per-core timers into user space. When it's
+enabled, the enabled timers trigger KVM_EXIT_ARM_TIMER guest exits when they
+are pending, unless masked by vcpu->run->request_interrupt_window.
+
7. Capabilities that can be enabled on VMs
------------------------------------------
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index de338d9..77d1f73 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -180,6 +180,9 @@ struct kvm_vcpu_arch {
/* Detect first run of a vcpu */
bool has_run_once;
+
+ /* User space wants timer notifications */
+ bool user_space_arm_timers;
};
struct kvm_vm_stat {
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index c84b6ad..57bdb71 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -187,6 +187,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
case KVM_CAP_ARM_PSCI_0_2:
case KVM_CAP_READONLY_MEM:
case KVM_CAP_MP_STATE:
+ case KVM_CAP_ARM_TIMER:
r = 1;
break;
case KVM_CAP_COALESCED_MMIO:
@@ -474,13 +475,7 @@ static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
return ret;
}
- /*
- * Enable the arch timers only if we have an in-kernel VGIC
- * and it has been properly initialized, since we cannot handle
- * interrupts from the virtual timer with a userspace gic.
- */
- if (irqchip_in_kernel(kvm) && vgic_initialized(kvm))
- ret = kvm_timer_enable(vcpu);
+ ret = kvm_timer_enable(vcpu);
return ret;
}
@@ -601,6 +596,13 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
run->exit_reason = KVM_EXIT_INTR;
}
+ if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu)) {
+ /* Tell user space about the pending vtimer */
+ ret = 0;
+ run->exit_reason = KVM_EXIT_ARM_TIMER;
+ run->arm_timer.timesource = KVM_ARM_TIMER_VTIMER;
+ }
+
if (ret <= 0 || need_new_vmid_gen(vcpu->kvm) ||
vcpu->arch.power_off || vcpu->arch.pause) {
local_irq_enable();
@@ -887,6 +889,12 @@ static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
return -EINVAL;
switch (cap->cap) {
+ case KVM_CAP_ARM_TIMER:
+ r = 0;
+ if (cap->args[0] != KVM_ARM_TIMER_VTIMER)
+ return -EINVAL;
+ vcpu->arch.user_space_arm_timers = true;
+ break;
default:
r = -EINVAL;
break;
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 3eda975..3d01481 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -270,6 +270,9 @@ struct kvm_vcpu_arch {
/* Detect first run of a vcpu */
bool has_run_once;
+
+ /* User space wants timer notifications */
+ bool user_space_arm_timers;
};
#define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 300ef25..00f4948 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -205,6 +205,7 @@ struct kvm_hyperv_exit {
#define KVM_EXIT_S390_STSI 25
#define KVM_EXIT_IOAPIC_EOI 26
#define KVM_EXIT_HYPERV 27
+#define KVM_EXIT_ARM_TIMER 28
/* For KVM_EXIT_INTERNAL_ERROR */
/* Emulate instruction failed. */
@@ -361,6 +362,10 @@ struct kvm_run {
} eoi;
/* KVM_EXIT_HYPERV */
struct kvm_hyperv_exit hyperv;
+ /* KVM_EXIT_ARM_TIMER */
+ struct {
+ __u8 timesource;
+ } arm_timer;
/* Fix the size of the union. */
char padding[256];
};
@@ -870,6 +875,7 @@ struct kvm_ppc_smmu_info {
#define KVM_CAP_S390_USER_INSTR0 130
#define KVM_CAP_MSI_DEVID 131
#define KVM_CAP_PPC_HTM 132
+#define KVM_CAP_ARM_TIMER 133
#ifdef KVM_CAP_IRQ_ROUTING
@@ -1327,4 +1333,12 @@ struct kvm_assigned_msix_entry {
#define KVM_X2APIC_API_USE_32BIT_IDS (1ULL << 0)
#define KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK (1ULL << 1)
+/* Available with KVM_CAP_ARM_TIMER */
+
+/* Bits for run->request_interrupt_window */
+#define KVM_IRQWINDOW_VTIMER (1 << 0)
+
+/* Bits for run->arm_timer.timesource */
+#define KVM_ARM_TIMER_VTIMER (1 << 0)
+
#endif /* __LINUX_KVM_H */
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 4309b60..cbbb50dd 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -170,16 +170,45 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level)
{
int ret;
struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+ struct kvm_run *run = vcpu->run;
- BUG_ON(!vgic_initialized(vcpu->kvm));
+ BUG_ON(irqchip_in_kernel(vcpu->kvm) && !vgic_initialized(vcpu->kvm));
timer->active_cleared_last = false;
timer->irq.level = new_level;
- trace_kvm_timer_update_irq(vcpu->vcpu_id, timer->irq.irq,
+ trace_kvm_timer_update_irq(vcpu->vcpu_id, host_vtimer_irq,
timer->irq.level);
- ret = kvm_vgic_inject_mapped_irq(vcpu->kvm, vcpu->vcpu_id,
- timer->irq.irq,
- timer->irq.level);
+
+ if (irqchip_in_kernel(vcpu->kvm) && vgic_initialized(vcpu->kvm)) {
+ /* Fire the timer in the VGIC */
+
+ ret = kvm_vgic_inject_mapped_irq(vcpu->kvm, vcpu->vcpu_id,
+ timer->irq.irq,
+ timer->irq.level);
+ } else if (!vcpu->arch.user_space_arm_timers) {
+ /* User space has not activated timer use */
+ ret = 0;
+ } else {
+ /*
+ * Set PENDING_TIMER so that user space can handle the event if
+ *
+ * 1) Level is high
+ * 2) The vtimer is not suppressed by user space
+ * 3) We are not in the timer trigger exit path
+ */
+ if (new_level &&
+ !(run->request_interrupt_window & KVM_IRQWINDOW_VTIMER) &&
+ (run->exit_reason != KVM_EXIT_ARM_TIMER)) {
+ /* KVM_REQ_PENDING_TIMER means vtimer triggered */
+ kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
+ }
+
+ /* Force a new level high check on next entry */
+ timer->irq.level = 0;
+
+ ret = 0;
+ }
+
WARN_ON(ret);
}
@@ -197,7 +226,8 @@ static int kvm_timer_update_state(struct kvm_vcpu *vcpu)
* because the guest would never see the interrupt. Instead wait
* until we call this function from kvm_timer_flush_hwstate.
*/
- if (!vgic_initialized(vcpu->kvm) || !timer->enabled)
+ if ((irqchip_in_kernel(vcpu->kvm) && !vgic_initialized(vcpu->kvm)) ||
+ !timer->enabled)
return -ENODEV;
if (kvm_timer_should_fire(vcpu) != timer->irq.level)
@@ -275,35 +305,57 @@ void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
* to ensure that hardware interrupts from the timer triggers a guest
* exit.
*/
- phys_active = timer->irq.level ||
- kvm_vgic_map_is_active(vcpu, timer->irq.irq);
-
- /*
- * We want to avoid hitting the (re)distributor as much as
- * possible, as this is a potentially expensive MMIO access
- * (not to mention locks in the irq layer), and a solution for
- * this is to cache the "active" state in memory.
- *
- * Things to consider: we cannot cache an "active set" state,
- * because the HW can change this behind our back (it becomes
- * "clear" in the HW). We must then restrict the caching to
- * the "clear" state.
- *
- * The cache is invalidated on:
- * - vcpu put, indicating that the HW cannot be trusted to be
- * in a sane state on the next vcpu load,
- * - any change in the interrupt state
- *
- * Usage conditions:
- * - cached value is "active clear"
- * - value to be programmed is "active clear"
- */
- if (timer->active_cleared_last && !phys_active)
- return;
+ if (irqchip_in_kernel(vcpu->kvm) && vgic_initialized(vcpu->kvm)) {
+ phys_active = timer->irq.level ||
+ kvm_vgic_map_is_active(vcpu, timer->irq.irq);
+
+ /*
+ * We want to avoid hitting the (re)distributor as much as
+ * possible, as this is a potentially expensive MMIO access
+ * (not to mention locks in the irq layer), and a solution for
+ * this is to cache the "active" state in memory.
+ *
+ * Things to consider: we cannot cache an "active set" state,
+ * because the HW can change this behind our back (it becomes
+ * "clear" in the HW). We must then restrict the caching to
+ * the "clear" state.
+ *
+ * The cache is invalidated on:
+ * - vcpu put, indicating that the HW cannot be trusted to be
+ * in a sane state on the next vcpu load,
+ * - any change in the interrupt state
+ *
+ * Usage conditions:
+ * - cached value is "active clear"
+ * - value to be programmed is "active clear"
+ */
+ if (timer->active_cleared_last && !phys_active)
+ return;
+
+ ret = irq_set_irqchip_state(host_vtimer_irq,
+ IRQCHIP_STATE_ACTIVE,
+ phys_active);
+ } else {
+ /* User space tells us whether the timer is in active mode */
+ phys_active = vcpu->run->request_interrupt_window &
+ KVM_IRQWINDOW_VTIMER;
+
+ /* However if the line is high, we exit anyway, so we want
+ * to keep the IRQ masked */
+ phys_active = phys_active || timer->irq.level;
+
+ /*
+ * So we can just explicitly mask or unmask the IRQ, gaining
+ * more compatibility with oddball irq controllers.
+ */
+ if (phys_active)
+ disable_percpu_irq(host_vtimer_irq);
+ else
+ enable_percpu_irq(host_vtimer_irq, 0);
+
+ ret = 0;
+ }
- ret = irq_set_irqchip_state(host_vtimer_irq,
- IRQCHIP_STATE_ACTIVE,
- phys_active);
WARN_ON(ret);
timer->active_cleared_last = !phys_active;
@@ -479,6 +531,10 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
if (timer->enabled)
return 0;
+ /* No need to route physical IRQs when we don't use the vgic */
+ if (!irqchip_in_kernel(vcpu->kvm))
+ goto no_vgic;
+
/*
* Find the physical IRQ number corresponding to the host_vtimer_irq
*/
@@ -502,6 +558,7 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
if (ret)
return ret;
+no_vgic:
/*
* There is a potential race here between VCPUs starting for the first
--
2.6.6
^ permalink raw reply related
* [PATCH v3 1/2] KVM: arm/arm64: Add vcpu ENABLE_CAP functionality
From: Alexander Graf @ 2016-09-16 6:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474007187-18673-1-git-send-email-agraf@suse.de>
In a follow-up patch we will need to enable capabilities on demand for
backwards compatibility. This patch adds the generic framework to handle
vcpu cap enablement to the arm code base.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
Documentation/virtual/kvm/api.txt | 4 +++-
arch/arm/kvm/arm.c | 25 +++++++++++++++++++++++++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
index 739db9a..23937e0 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -997,7 +997,9 @@ documentation when it pops into existence).
Capability: KVM_CAP_ENABLE_CAP, KVM_CAP_ENABLE_CAP_VM
Architectures: x86 (only KVM_CAP_ENABLE_CAP_VM),
- mips (only KVM_CAP_ENABLE_CAP), ppc, s390
+ mips (only KVM_CAP_ENABLE_CAP), ppc, s390,
+ arm (only KVM_CAP_ENABLE_CAP),
+ arm64 (only KVM_CAP_ENABLE_CAP)
Type: vcpu ioctl, vm ioctl (with KVM_CAP_ENABLE_CAP_VM)
Parameters: struct kvm_enable_cap (in)
Returns: 0 on success; -1 on error
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 75f130e..c84b6ad 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -878,6 +878,23 @@ static int kvm_arm_vcpu_has_attr(struct kvm_vcpu *vcpu,
return ret;
}
+static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
+ struct kvm_enable_cap *cap)
+{
+ int r;
+
+ if (cap->flags)
+ return -EINVAL;
+
+ switch (cap->cap) {
+ default:
+ r = -EINVAL;
+ break;
+ }
+
+ return r;
+}
+
long kvm_arch_vcpu_ioctl(struct file *filp,
unsigned int ioctl, unsigned long arg)
{
@@ -941,6 +958,14 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
return -EFAULT;
return kvm_arm_vcpu_has_attr(vcpu, &attr);
}
+ case KVM_ENABLE_CAP:
+ {
+ struct kvm_enable_cap cap;
+
+ if (copy_from_user(&cap, argp, sizeof(cap)))
+ return -EFAULT;
+ return kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
+ }
default:
return -EINVAL;
}
--
2.6.6
^ permalink raw reply related
* [PATCH v3 0/2] KVM: ARM: Enable vtimers with user space gic
From: Alexander Graf @ 2016-09-16 6:26 UTC (permalink / raw)
To: linux-arm-kernel
Some systems out there (well, one type in particular - the Raspberry Pi series)
do have virtualization capabilities in the core, but no ARM GIC interrupt
controller.
To run on these systems, the cleanest route is to just handle all
interrupt delivery in user space and only deal with IRQ pins in the core
side in KVM.
This works pretty well already, but breaks when the guest starts to use
architected timers, as these are handled straight inside kernel space today.
This patch set allows user space to receive vtimer events as well as mask
them, so that we can handle all vtimer related interrupt injection from user
space, enabling us to use architected timer with user space gic emulation.
I have successfully run edk2 as well as Linux using these patches on a
Raspberry Pi 3 system with acceptable speed.
A branch with WIP QEMU code can be found here:
https://github.com/agraf/qemu.git no-kvm-irqchip
To use the user space irqchip, just run it with
$ qemu-system-aarch64 -M virt,kernel-irqchip=off
v1 -> v2:
- Add back curly brace that got lost
v2 -> v3:
- Fix "only only" in documentation
- Split patches
- Remove kvm_emulate.h include
Alexander Graf (2):
KVM: arm/arm64: Add vcpu ENABLE_CAP functionality
KVM: arm/arm64: Route vtimer events to user space
Documentation/virtual/kvm/api.txt | 28 ++++++++-
arch/arm/include/asm/kvm_host.h | 3 +
arch/arm/kvm/arm.c | 47 +++++++++++---
arch/arm64/include/asm/kvm_host.h | 3 +
include/uapi/linux/kvm.h | 14 +++++
virt/kvm/arm/arch_timer.c | 125 +++++++++++++++++++++++++++-----------
6 files changed, 177 insertions(+), 43 deletions(-)
--
2.6.6
^ permalink raw reply
* [PATCH] soc: rockchip: power-domain: Handle errors from of_genpd_add_provider_onecell
From: Tomeu Vizoso @ 2016-09-16 5:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6250295.kzQYkblnJM@diego>
On 09/16/2016 12:31 AM, Heiko St?bner wrote:
> Am Donnerstag, 15. September 2016, 16:39:34 schrieb Heiko St?bner:
>> Am Donnerstag, 15. September 2016, 12:43:41 schrieb Tomeu Vizoso:
>>> It was a bit surprising that the device was reported to have probed just
>>> fine, but the provider hadn't been registered.
>>>
>>> So handle any errors when registering the provider and fail the probe
>>> accordingly.
>>>
>>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>>> Cc: Caesar Wang <wxt@rock-chips.com>
>>> ---
>>>
>>> drivers/soc/rockchip/pm_domains.c | 6 +++++-
>>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/soc/rockchip/pm_domains.c
>>> b/drivers/soc/rockchip/pm_domains.c index 7acd1517dd37..57e920128cb2
>>> 100644
>>> --- a/drivers/soc/rockchip/pm_domains.c
>>> +++ b/drivers/soc/rockchip/pm_domains.c
>>> @@ -627,7 +627,11 @@ static int rockchip_pm_domain_probe(struct
>>> platform_device *pdev) goto err_out;
>>>
>>> }
>>>
>>> - of_genpd_add_provider_onecell(np, &pmu->genpd_data);
>>> + error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
>>> + if (error) {
>>> + dev_err(dev, "failed to add provider: %d\n", error);
>>> + goto err_out;
>>> + }
>>>
>>> return 0;
>>
>> Looks good in itself, but seems to trigger some issue in the genpd code
>> when applied alone on top of linux-next-20160915. Looks like genpd
>> is missing counter-initialization somewhere, as I'm seeing now:
>>
>> [ 1.664744] genpd_poweroff_unused disabling (null)
>> [ 1.669553] ------------[ cut here ]------------
>> [ 1.674169] WARNING: CPU: 0 PID: 1 at ../kernel/workqueue.c:1440
>> __queue_work+0x2b8/0x3f8 [ 1.682337] Modules linked in:
>> [ 1.685401] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
>> 4.8.0-rc6-next-20160915-00001-g7432710-dirty #5 [ 1.694608] Hardware
>> name: Rockchip (Device Tree)
>> [ 1.699312] [<c0310388>] (unwind_backtrace) from [<c030ba04>]
>> (show_stack+0x10/0x14) [ 1.707050] [<c030ba04>] (show_stack) from
>> [<c0599c90>] (dump_stack+0x90/0xa4) [ 1.714267] [<c0599c90>]
>> (dump_stack) from [<c0341bc0>] (__warn+0xe8/0x100) [ 1.721221]
>> [<c0341bc0>] (__warn) from [<c0341c88>] (warn_slowpath_null+0x20/0x28) [
>> 1.728785] [<c0341c88>] (warn_slowpath_null) from [<c0355b28>]
>> (__queue_work+0x2b8/0x3f8) [ 1.737041] [<c0355b28>] (__queue_work) from
>> [<c0355ca8>] (queue_work_on+0x40/0x4c) [ 1.744692] [<c0355ca8>]
>> (queue_work_on) from [<c103e8b8>] (genpd_poweroff_unused+0x78/0x9c) [
>> 1.753123] [<c103e8b8>] (genpd_poweroff_unused) from [<c0301e78>]
>> (do_one_initcall+0x40/0x170) [ 1.761815] [<c0301e78>] (do_one_initcall)
>> from [<c1000dc8>] (kernel_init_freeable+0x15c/0x1fc) [ 1.770507]
>> [<c1000dc8>] (kernel_init_freeable) from [<c0bb7ba0>]
>> (kernel_init+0x8/0x114) [ 1.778678] [<c0bb7ba0>] (kernel_init) from
>> [<c0307df8>] (ret_from_fork+0x14/0x3c) [ 1.786240] ---[ end trace
>> b38c51ace1463add ]---
>> [ 1.790875] genpd_poweroff_unused disabling ??????
>> [ 1.795856] genpd_poweroff_unused disabling ??????
>> [ 1.800830] ------------[ cut here ]------------
>> [ 1.805443] WARNING: CPU: 0 PID: 1 at ../kernel/workqueue.c:1440
>> __queue_work+0x2b8/0x3f8 [ 1.813610] Modules linked in:
>> [ 1.816673] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W
>> 4.8.0-rc6-next-20160915-00001-g7432710-dirty #5 [ 1.827094] Hardware
>> name: Rockchip (Device Tree)
>> [ 1.831795] [<c0310388>] (unwind_backtrace) from [<c030ba04>]
>> (show_stack+0x10/0x14) [ 1.839532] [<c030ba04>] (show_stack) from
>> [<c0599c90>] (dump_stack+0x90/0xa4) [ 1.846747] [<c0599c90>]
>> (dump_stack) from [<c0341bc0>] (__warn+0xe8/0x100) [ 1.853700]
>> [<c0341bc0>] (__warn) from [<c0341c88>] (warn_slowpath_null+0x20/0x28) [
>> 1.861264] [<c0341c88>] (warn_slowpath_null) from [<c0355b28>]
>> (__queue_work+0x2b8/0x3f8) [ 1.869521] [<c0355b28>] (__queue_work) from
>> [<c0355ca8>] (queue_work_on+0x40/0x4c) [ 1.877170] [<c0355ca8>]
>> (queue_work_on) from [<c103e8b8>] (genpd_poweroff_unused+0x78/0x9c) [
>> 1.885600] [<c103e8b8>] (genpd_poweroff_unused) from [<c0301e78>]
>> (do_one_initcall+0x40/0x170) [ 1.894290] [<c0301e78>] (do_one_initcall)
>> from [<c1000dc8>] (kernel_init_freeable+0x15c/0x1fc) [ 1.902981]
>> [<c1000dc8>] (kernel_init_freeable) from [<c0bb7ba0>]
>> (kernel_init+0x8/0x114) [ 1.911152] [<c0bb7ba0>] (kernel_init) from
>> [<c0307df8>] (ret_from_fork+0x14/0x3c) [ 1.918713] ---[ end trace
>> b38c51ace1463ade ]---
>> [ 1.923338] genpd_poweroff_unused disabling ??????
>> [ 1.928325] genpd_poweroff_unused disabling ??????
>>
>> [+ millions more of those]
>
> just for completenes sake, I've included your patch in a series of my
> own [0] which adds the necessary pm_genpd_remove prequisite to prevent
> the errors shown above.
That's awesome, thanks. For some reason I hadn't noticed those.
Regards,
Tomeu
>
> Heiko
>
> [0] "[PATCH 0/2] soc: rockchip: fix probe error path in power-domain driver"
>
^ permalink raw reply
* v4.8-rc: GSM audio causes trouble
From: Sebastian Reichel @ 2016-09-16 5:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915205142.GA6747@amd>
Hi,
On Thu, Sep 15, 2016 at 10:51:42PM +0200, Pavel Machek wrote:
> > I was trying to improve GSM call quality, and hit problems in
> > v4.8-rc. Sound only worked for a while, then I tried to kill
> > cmtspeech_ofono_test, and could not, not even with -9 and could not
> > even reboot.
> >
> > I went back to v4.1 (ok, quite far, I see), and problems are gone.
> >
> > Does it work for you? Any ideas what to try... besides bisect?
>
> v4.7 is okay.
>
> v4.8 with
>
> git diff ..mini-v4.7 drivers/hsi/ | git apply
>
> Seems to work ok.
>
> Best regards,
hsi changes from 4.7 to 4.8 are basically runtime PM enablement.
Does 4.8 work for you with just 9c99e5e51988 reverted?
-- Sebastian
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160916/e6cccda1/attachment-0001.sig>
^ permalink raw reply
* [PATCH] clocksource: arm_arch_timer: Don't assume clock runs in suspend
From: Brian Norris @ 2016-09-16 5:49 UTC (permalink / raw)
To: linux-arm-kernel
Since commit 4fbcdc813fb9 ("clocksource: arm_arch_timer: Use clocksource
for suspend timekeeping"), this driver assumes that the ARM architected
timer keeps running in suspend. This is not the case for some ARM SoCs,
depending on the HW state used for system suspend. Let's not assume that
all SoCs support this, and instead only support this if the device tree
explicitly tells us it's "always on". In all other cases, just fall back
to the RTC. This should be relatively harmless.
It seems fair to key the system-suspend behavior off the same property
used for C3STOP, since if the timer doesn't keep context for CPU sleep,
it likely doesn't for system sleep either.
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
drivers/clocksource/arm_arch_timer.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 57700541f951..e28677a34f02 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -490,7 +490,7 @@ static struct clocksource clocksource_counter = {
.rating = 400,
.read = arch_counter_read,
.mask = CLOCKSOURCE_MASK(56),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static struct cyclecounter cyclecounter = {
@@ -526,6 +526,8 @@ static void __init arch_counter_register(unsigned type)
clocksource_counter.name = "arch_mem_counter";
}
+ if (!arch_timer_c3stop)
+ clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
start_count = arch_timer_read_counter();
clocksource_register_hz(&clocksource_counter, arch_timer_rate);
cyclecounter.mult = clocksource_counter.mult;
--
2.8.1.340.g018a5d0.dirty
^ permalink raw reply related
* [PATCH] KVM: arm/arm64: timer: Fix hw sync for user space irqchip path
From: Alexander Graf @ 2016-09-16 5:16 UTC (permalink / raw)
To: linux-arm-kernel
While adding the new vgic implementation, apparently nobody tested
the non-vgic path where user space controls the vgic, so two functions
slipped through the cracks that get called in generic code but don't
check whether hardware support is enabled.
This patch guards them with proper checks to ensure we only try to
use vgic data structures if they are available. Without this, I get
a stack trace:
[ 74.363037] Unable to handle kernel paging request at virtual address ffffffffffffffe8
[...]
[ 74.929654] [<ffff000008824bcc>] _raw_spin_lock+0x1c/0x58
[ 74.935133] [<ffff0000080b7f20>] kvm_vgic_flush_hwstate+0x88/0x288
[ 74.941406] [<ffff0000080ab0b4>] kvm_arch_vcpu_ioctl_run+0xfc/0x630
[ 74.947766] [<ffff0000080a15bc>] kvm_vcpu_ioctl+0x2f4/0x710
[ 74.953420] [<ffff0000082788a8>] do_vfs_ioctl+0xb0/0x728
[ 74.958807] [<ffff000008278fb4>] SyS_ioctl+0x94/0xa8
[ 74.963844] [<ffff000008083744>] el0_svc_naked+0x38/0x3c
Fixes: 0919e84c0
Cc: stable at vger.kernel.org
Signed-off-by: Alexander Graf <agraf@suse.de>
---
virt/kvm/arm/vgic/vgic.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
index e83b7fe..9f312ba 100644
--- a/virt/kvm/arm/vgic/vgic.c
+++ b/virt/kvm/arm/vgic/vgic.c
@@ -645,6 +645,9 @@ next:
/* Sync back the hardware VGIC state into our emulation after a guest's run. */
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
{
+ if (!vcpu->kvm->arch.vgic.enabled)
+ return;
+
vgic_process_maintenance_interrupt(vcpu);
vgic_fold_lr_state(vcpu);
vgic_prune_ap_list(vcpu);
@@ -653,6 +656,9 @@ void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
/* Flush our emulation state into the GIC hardware before entering the guest. */
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
{
+ if (!vcpu->kvm->arch.vgic.enabled)
+ return;
+
spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
vgic_flush_lr_state(vcpu);
spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
--
2.6.6
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox