* [PATCH v26 2/7] arm64: kdump: implement machine_crash_shutdown()
From: James Morse @ 2016-09-16 14:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915114815.GK16712@linaro.org>
On 16/09/16 04:21, AKASHI Takahiro wrote:
> On Wed, Sep 14, 2016 at 07:09:33PM +0100, James Morse wrote:
>> On 07/09/16 05:29, AKASHI Takahiro wrote:
>>> Primary kernel calls machine_crash_shutdown() to shut down non-boot cpus
>>> and save registers' status in per-cpu ELF notes before starting crash
>>> dump kernel. See kernel_kexec().
>>> Even if not all secondary cpus have shut down, we do kdump anyway.
>>>
>>> As we don't have to make non-boot(crashed) cpus offline (to preserve
>>> correct status of cpus at crash dump) before shutting down, this patch
>>> also adds a variant of smp_send_stop().
>>> diff --git a/arch/arm64/include/asm/kexec.h b/arch/arm64/include/asm/kexec.h
>>> index 04744dc..a908958 100644
>>> --- a/arch/arm64/include/asm/kexec.h
>>> +++ b/arch/arm64/include/asm/kexec.h
>>> @@ -40,7 +40,46 @@
>>> static inline void crash_setup_regs(struct pt_regs *newregs,
>>> struct pt_regs *oldregs)
>>> {
>>> - /* Empty routine needed to avoid build errors. */
>>> + if (oldregs) {
>>> + memcpy(newregs, oldregs, sizeof(*newregs));
>>> + } else {
>>> + u64 tmp1, tmp2;
>>> +
>>> + __asm__ __volatile__ (
>>> + "stp x0, x1, [%2, #16 * 0]\n"
>>> + "stp x2, x3, [%2, #16 * 1]\n"
>>> + "stp x4, x5, [%2, #16 * 2]\n"
>>> + "stp x6, x7, [%2, #16 * 3]\n"
>>> + "stp x8, x9, [%2, #16 * 4]\n"
>>> + "stp x10, x11, [%2, #16 * 5]\n"
>>> + "stp x12, x13, [%2, #16 * 6]\n"
>>> + "stp x14, x15, [%2, #16 * 7]\n"
>>> + "stp x16, x17, [%2, #16 * 8]\n"
>>> + "stp x18, x19, [%2, #16 * 9]\n"
>>> + "stp x20, x21, [%2, #16 * 10]\n"
>>> + "stp x22, x23, [%2, #16 * 11]\n"
>>> + "stp x24, x25, [%2, #16 * 12]\n"
>>> + "stp x26, x27, [%2, #16 * 13]\n"
>>> + "stp x28, x29, [%2, #16 * 14]\n"
>>> + "mov %0, sp\n"
>>> + "stp x30, %0, [%2, #16 * 15]\n"
>>> +
>>> + "/* faked current PSTATE */\n"
>>> + "mrs %0, CurrentEL\n"
>>> + "mrs %1, DAIF\n"
>>> + "orr %0, %0, %1\n"
>>> + "mrs %1, NZCV\n"
>>> + "orr %0, %0, %1\n"
>>> +
>>
>> What about SPSEL? While we don't use it, it is correctly preserved for
>> everything except a CPU that calls panic()...
>
> My comment above might be confusing, but what I want to fake
> here is "spsr" as pt_regs.pstate is normally set based on spsr_el1.
> So there is no corresponding field of SPSEL in spsr.
Here is my logic, I may have missed something obvious, see what you think:
SPSR_EL{1,2} shows the CPU mode 'M' in bits 0-4, From aarch64 bit 4 is always 0.
>From the register definitions in the ARM-ARM C5.2, likely values in 0-3 are:
0100 EL1t
0101 EL1h
1000 EL2t
1001 EL2h
I'm pretty sure this least significant bit is what SPSEL changes, so it does get
implicitly recorded in SPSR.
CurrentEL returns a value in bits 0-3, of which 0-1 are RES0, so we lose the
difference between EL?t and EL?h.
>
>>
>>> + /* pc */
>>> + "adr %1, 1f\n"
>>> + "1:\n"
>>> + "stp %1, %0, [%2, #16 * 16]\n"
>>> + : "=r" (tmp1), "=r" (tmp2), "+r" (newregs)
>>> + :
>>> + : "memory"
Do you need the memory clobber? This asm only modifies values in newregs.
>>> + );
>>> + }
>>> }
>>>
>>> #endif /* __ASSEMBLY__ */
>>> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
>>> +#ifdef CONFIG_KEXEC_CORE
>>> +void smp_send_crash_stop(void)
>>> +{
>>> + cpumask_t mask;
>>> + unsigned long timeout;
>>> +
>>> + if (num_online_cpus() == 1)
>>> + return;
>>> +
>>> + cpumask_copy(&mask, cpu_online_mask);
>>> + cpumask_clear_cpu(smp_processor_id(), &mask);
>>> +
>>> + atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1);
>>> +
>>> + pr_crit("SMP: stopping secondary CPUs\n");
>>> + smp_cross_call(&mask, IPI_CPU_CRASH_STOP);
>>> +
>>> + /* Wait up to one second for other CPUs to stop */
>>> + timeout = USEC_PER_SEC;
>>> + while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--)
>>> + udelay(1);
>>> +
>>> + if (atomic_read(&waiting_for_crash_ipi) > 0)
>>> + pr_warning("SMP: failed to stop secondary CPUs %*pbl\n",
>>> + cpumask_pr_args(cpu_online_mask));
>>> +}
>>> +#endif
>>
>> This is very similar to smp_send_stop() which also has the timeout. Is it
>> possible to merge them? You could use in_crash_kexec to choose the IPI type.
>
> Yeah, we could merge them along with ipi_cpu_(crash_)stop().
> But the resulting code would be quite noisy if each line
> is switched by "if (in_crash_kexec)."
> Otherwise, we may have one big "if" like:
> void smp_send_stop(void)
> {
> if (in_crash_kexec)
> ...
> else
> ...
> }
> It seems to me that it is not much different from the current code.
> What do you think?
Hmm, yes, its too fiddly to keep the existing behaviour of both.
The problems are ipi_cpu_stop() doesn't call cpu_die(), (I can't see a good
reason for this, but more archaeology is needed), and ipi_cpu_crash_stop()
doesn't modify the online cpu mask.
I don't suggest we do this yet, but it could be future cleanup if it's proved to
be safe:
smp_send_stop() is only called from: machine_halt(), machine_power_off(),
machine_restart() and panic(). In all those cases the CPUs are never expected to
come back, so we can probably merge the IPIs. This involves modifying the
online cpu mask during kdump, (which I think is fine as it uses the atomic
bitops so we won't get blocked on a lock), and promoting in_crash_kexec to some
atomic type.
But I think we should leave it as it is for now,
Thanks,
James
^ permalink raw reply
* [PATCH v26 3/7] arm64: kdump: add kdump support
From: James Morse @ 2016-09-16 14:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160907042908.6232-4-takahiro.akashi@linaro.org>
On 07/09/16 05:29, AKASHI Takahiro wrote:
> On crash dump kernel, all the information about primary kernel's system
> memory (core image) is available in elf core header.
> The primary kernel will set aside this header with reserve_elfcorehdr()
> at boot time and inform crash dump kernel of its location via a new
> device-tree property, "linux,elfcorehdr".
>
> Please note that all other architectures use traditional "elfcorehdr="
> kernel parameter for this purpose.
>
> Then crash dump kernel will access the primary kernel's memory with
> copy_oldmem_page(), which reads one page by ioremap'ing it since it does
> not reside in linear mapping on crash dump kernel.
>
> We also need our own elfcorehdr_read() here since the header is placed
> within crash dump kernel's usable memory.
One nit below, looks good.
Reviewed-by: James Morse <james.morse@arm.com>
Thanks,
James
> diff --git a/arch/arm64/kernel/crash_dump.c b/arch/arm64/kernel/crash_dump.c
> +/**
> + * copy_oldmem_page() - copy one page from old kernel memory
> + * @pfn: page frame number to be copied
> + * @buf: buffer where the copied page is placed
> + * @csize: number of bytes to copy
> + * @offset: offset in bytes into the page
> + * @userbuf: if set, @buf is in a user address space
> + *
> + * This function copies one page from old kernel memory into buffer pointed by
> + * @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes
> + * copied or negative error in case of failure.
> + */
> +ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
> + size_t csize, unsigned long offset,
> + int userbuf)
> +{
> + void *vaddr;
> +
> + if (!csize)
> + return 0;
> +
> + vaddr = memremap(__pfn_to_phys(pfn), PAGE_SIZE, MEMREMAP_WB);
> + if (!vaddr)
> + return -ENOMEM;
> +
> + if (userbuf) {
> + if (copy_to_user(buf, vaddr + offset, csize)) {
If you re-cast buf with (char __user *), it should stop sparse complaining:
> ../arch/arm64/kernel/crash_dump.c:45:34: warning: incorrect type in argument 1
(different address spaces)
> ../arch/arm64/kernel/crash_dump.c:45:34: expected void [noderef] <asn:1>*to
> ../arch/arm64/kernel/crash_dump.c:45:34: got char *buf
^ permalink raw reply
* next-20160915 build: 2 failures 16 warnings (next-20160915)
From: Hans de Goede @ 2016-09-16 14:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915154140.GM27974@sirena.org.uk>
Hi,
On 15-09-16 17:41, Mark Brown wrote:
> On Thu, Sep 15, 2016 at 12:43:41PM +0100, Build bot for Mark Brown wrote:
>
> Today's -next fails to build both arm and arm64 allmodconfigs due to:
>
>> arm64-allmodconfig
>> ERROR: "musb_root_disconnect" [drivers/usb/musb/sunxi.ko] undefined!
>
>> arm-allmodconfig
>> ERROR: "musb_root_disconnect" [drivers/usb/musb/sunxi.ko] undefined!
>
> due to 7cba17ec9adc8cf (musb: sunxi: Add support for platform_set_mode)
> which adds a call to that non-exported function to a module.
Thank you for catching / reporting this. One patch fixing this
coming up.
Regards,
Hans
^ permalink raw reply
* [PATCH] musb: Export musb_root_disconnect for use in modules
From: Hans de Goede @ 2016-09-16 14:59 UTC (permalink / raw)
To: linux-arm-kernel
Export musb_root_disconnect for use in modules, so that musb glue
code build as module can use it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/usb/musb/musb_virthub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
index fe08e77..61b5f1c 100644
--- a/drivers/usb/musb/musb_virthub.c
+++ b/drivers/usb/musb/musb_virthub.c
@@ -245,6 +245,7 @@ void musb_root_disconnect(struct musb *musb)
usb_otg_state_string(musb->xceiv->otg->state));
}
}
+EXPORT_SYMBOL_GPL(musb_root_disconnect);
/*---------------------------------------------------------------------*/
--
2.9.3
^ permalink raw reply related
* [RESEND PATCH v7 1/2] sdhci-of-arasan: Add device tree parameter xlnx, fails-without-test-cd bit
From: Zach Brown @ 2016-09-16 15:01 UTC (permalink / raw)
To: linux-arm-kernel
The sdhci controller on xilinx zynq devices will not function unless
the CD bit is provided. http://www.xilinx.com/support/answers/61064.html
In cases where it is impossible to provide the CD bit in hardware,
setting the controller to test mode and then setting inserted to true
will get the controller to function without the CD bit.
The device property "xlnx,fails-without-test-cd" will let the arasan
driver know the controller does not have the CD line wired and that the
controller does not function without it.
Signed-off-by: Zach Brown <zach.brown@ni.com>
---
v2:
* improved commit messages
* removed fake-cd device property
* removed fake-cd quirk
* use broken-cd device property
* documented new usage of broken-cd
v3:
* removed new usage of broken-cd
* created fails-without-test-cd device property
* created arasan controller specific quirk
v4:
* changed fails-without-test-cd to xlnx-fails-without-test-cd
* removed extra blank line
v5:
* Fixed style mistake
* Changed (1 << 0 ) to BIT(0)
v6:
* Fixed style mistakes
* Condensed unnecessarily long variable names
* Removed line wraps that were no longer necessary.
* Rebased changes off Ulf's mmc tree's next branch.
v7:
* Removed erroneous re-creation of Optional Properties section
* Changed xlnx-fails-without-test-cd to xlnx,fails-without-test-cd
* Changed of_get_property to of_property_read_bool
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 3404afa..49df630 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -36,6 +36,9 @@ Optional Properties:
- #clock-cells: If specified this should be the value <0>. With this property
in place we will export a clock representing the Card Clock. This clock
is expected to be consumed by our PHY. You must also specify
+ - xlnx,fails-without-test-cd: when present, the controller doesn't work when
+ the CD line is not connected properly, and the line is not connected
+ properly. Test mode can be used to force the controller to function.
Example:
sdhci at e0100000 {
--
2.7.4
^ permalink raw reply related
* [RESEND PATCH v7 2/2] sdhci-of-arasan: Set controller to test mode when xlnx, fails-without-test-cd is present
From: Zach Brown @ 2016-09-16 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474038102-20937-1-git-send-email-zach.brown@ni.com>
The sdhci controller on xilinx zynq devices will not function unless
the CD bit is provided. http://www.xilinx.com/support/answers/61064.html
In cases where it is impossible to provide the CD bit in hardware,
setting the controller to test mode and then setting inserted to true
will get the controller to function without the CD bit.
When the device has the property xlnx,fails-without-test-cd the driver
changes the controller to test mode and sets test inserted to true to
make the controller function.
Signed-off-by: Zach Brown <zach.brown@ni.com>
---
drivers/mmc/host/sdhci-of-arasan.c | 27 ++++++++++++++++++++++++++-
drivers/mmc/host/sdhci.h | 2 ++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 33601a8..da8e40a 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -26,6 +26,7 @@
#include <linux/phy/phy.h>
#include <linux/regmap.h>
#include "sdhci-pltfm.h"
+#include <linux/of.h>
#define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
#define SDHCI_ARASAN_VENDOR_REGISTER 0x78
@@ -98,6 +99,10 @@ struct sdhci_arasan_data {
struct regmap *soc_ctl_base;
const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
+ unsigned int quirks; /* Arasan deviations from spec */
+
+/* Controller does not have CD wired and will not function normally without */
+#define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
};
static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
@@ -245,12 +250,27 @@ static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
}
+void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
+{
+ u8 ctrl;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
+
+ sdhci_reset(host, mask);
+
+ if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+ ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ }
+}
+
static struct sdhci_ops sdhci_arasan_ops = {
.set_clock = sdhci_arasan_set_clock,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
.get_timeout_clock = sdhci_arasan_get_timeout_clock,
.set_bus_width = sdhci_set_bus_width,
- .reset = sdhci_reset,
+ .reset = sdhci_arasan_reset,
.set_uhs_signaling = sdhci_set_uhs_signaling,
};
@@ -545,6 +565,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
struct sdhci_host *host;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_arasan_data *sdhci_arasan;
+ struct device_node *np = pdev->dev.of_node;
host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata,
sizeof(*sdhci_arasan));
@@ -599,6 +620,10 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
}
sdhci_get_of_property(pdev);
+
+ if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
+ sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
+
pltfm_host->clk = clk_xin;
if (of_device_is_compatible(pdev->dev.of_node,
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index a2bc9e1..c722cd2 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -84,6 +84,8 @@
#define SDHCI_CTRL_ADMA32 0x10
#define SDHCI_CTRL_ADMA64 0x18
#define SDHCI_CTRL_8BITBUS 0x20
+#define SDHCI_CTRL_CDTEST_INS 0x40
+#define SDHCI_CTRL_CDTEST_EN 0x80
#define SDHCI_POWER_CONTROL 0x29
#define SDHCI_POWER_ON 0x01
--
2.7.4
^ permalink raw reply related
* [GIT PULL] ARM: SoC fixes for 4.8-rc7
From: Arnd Bergmann @ 2016-09-16 15:02 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 95390e3290e8bf69091116e0d91b9754c0e93a24:
Merge tag 'sunxi-fixes-for-4.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes (2016-09-07 21:25:08 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/fixes-for-linus
for you to fetch changes up to 6408649115cfd73d6807398d04b2ba564db9211e:
Merge tag 'samsung-fixes-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into fixes (2016-09-16 16:29:48 +0200)
----------------------------------------------------------------
ARM: SoC fixes
Here are a couple of bugfixes for v4.8-rc. Most of them have
actually been around for a while this time but for some reason
didn't get applied early on. The shmobile regulator fix is the
only one that isn't completely obvious.
device tree changes:
- archtimer interrupts must be level triggered (multiple platforms)
- fix for USB and MMC clocks on STiH410
- fix split DT repository in case of raspberry-pi 3
- A new use of skeleton.dtsi on arm64 has crept in after that
was removed.
defconfig updates:
- xilinx vdma has a new Kconfig symbol name
- keystone requires CONFIG_NOP_USB_XCEIV since v4.8-rc1
code fixes:
- fix regulator quirk on shmobile
- suspend-to-ram regression on EXYNOS
maintainer updates:
- Javier Martinez Canillas is now a reviewer for Samsung EXYNOS
----------------------------------------------------------------
Arnd Bergmann (4):
Merge tag 'renesas-fixes-for-v4.8' of git://git.kernel.org/.../horms/renesas into fixes
Merge tag 'sti-dt-fixes-for-v4.8-rcs' of git://git.kernel.org/.../pchotard/sti into fixes
Merge branch 'dt/irq-fix' into fixes
Merge tag 'samsung-fixes-4.8-2' of git://git.kernel.org/.../krzk/linux into fixes
Fabian Frederick (1):
ARM: multi_v7_defconfig: update XILINX_VDMA
Ian Campbell (2):
ARM: dts: Remove use of skeleton.dtsi from bcm283x.dtsi
ARM64: dts: bcm: Use a symlink to R-Pi dtsi files from arch=arm
Javier Martinez Canillas (2):
MAINTAINERS: Add myself as reviewer for Samsung Exynos support
ARM: EXYNOS: Clear OF_POPULATED flag from PMU node in IRQ init callback
Lee Jones (2):
ARM: dts: STiH410: Handle interconnect clock required by EHCI/OHCI (USB)
ARM: dts: STiH407-family: Provide interconnect clock for consumption in ST SDHCI
Marc Zyngier (1):
arm64: dts: Fix broken architected timer interrupt trigger
Roger Quadros (1):
ARM: keystone: defconfig: Fix USB configuration
Wolfram Sang (1):
ARM: shmobile: fix regulator quirk for Gen2
MAINTAINERS | 1 +
arch/arm/boot/dts/bcm2835-rpi.dtsi | 1 +
arch/arm/boot/dts/bcm283x.dtsi | 3 +-
arch/arm/boot/dts/stih407-family.dtsi | 10 ++--
arch/arm/boot/dts/stih410.dtsi | 12 +++--
arch/arm/configs/keystone_defconfig | 1 +
arch/arm/configs/multi_v7_defconfig | 2 +-
arch/arm/mach-exynos/suspend.c | 6 +++
arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c | 62 +++++++++-------------
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 +--
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 +--
arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 +--
arch/arm64/boot/dts/broadcom/bcm2835-rpi.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts | 4 +-
arch/arm64/boot/dts/broadcom/bcm2837.dtsi | 2 +-
.../boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcm283x.dtsi | 1 +
arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 +--
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 +--
arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 +--
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 +--
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 8 +--
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 +--
.../boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 +--
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 +--
25 files changed, 102 insertions(+), 93 deletions(-)
create mode 120000 arch/arm64/boot/dts/broadcom/bcm2835-rpi.dtsi
create mode 120000 arch/arm64/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi
create mode 120000 arch/arm64/boot/dts/broadcom/bcm283x.dtsi
^ permalink raw reply
* [RFC PATCH 2/8] thread_info: allow custom in-task thread_info
From: Andy Lutomirski @ 2016-09-16 15:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916103101.GA21702@leverpostej>
> On Thu, Sep 15, 2016 at 11:37:47AM -0700, Andy Lutomirski wrote:
> > On Thu, Sep 15, 2016 at 6:49 AM, Mark Rutland <mark.rutland@arm.com> wrote:
> > > Currently, task_struct is defined in <linux/sched.h>, which (indirectly)
> > > pulls in a number of low-level arch headers such as <asm/preempt.h>
> > > through a number of other headers. Thus, code and structures in these
> > > headers can't rely on the definition of task_struct. Some of these
> > > headers are necessary for the definition of task_struct, so moving
> > > task_struct into its own header is insufficient tio avoid circular
> > > includes.
> >
> > The flippant answer is to fix the headers, but I tried that myself and
> > gave up :(
>
> Agreed; likewise (though I gave up quicker, I suspect). :(
>
> Longer-term I'd still hope that we can do this.
>
> > But how about this slightly less duplicative alternative:
> >
> > struct thread_info {
> > #ifdef arch_thread_info
> > struct arch_thread_info arch_ti;
> > #endif
> > };
>
> I'm happy to have an arch_thread_info.
>
> Just to check, what do you mean to happen with the flags field? Should
> that always be in the generic thread_info? e.g.
>
> struct thread_info {
> u32 flags;
> #ifdef arch_thread_info
> struct arch_thread_info arch_ti;
> #endif
> };
Exactly. Possibly with a comment that using thread_struct should be
preferred and that arch_thread_info should be used only if some header
file requires access via current_thread_info() or task_thread_info().
--Andy
>
> Thanks,
> Mark,
^ permalink raw reply
* [PATCH v4 1/2] ARM: dts: sun8i: add pinmux for UART1 at PG
From: Icenowy Zheng @ 2016-09-16 15:16 UTC (permalink / raw)
To: linux-arm-kernel
The UART1 at PG (PG6, PG7, PG8, PG9) is, in the Allwinner's reference
tablet design of A23/33, used to connect to UART Bluetooth cards.
Add the pinmux for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
This patch is splited in v4.
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 7e05e09..c340885 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -361,6 +361,20 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ uart1_pins_a: uart1 at 0 {
+ allwinner,pins = "PG6", "PG7";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_pins_cts_rts_a: uart1-cts-rts at 0 {
+ allwinner,pins = "PG8", "PG9";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc0_pins_a: mmc0 at 0 {
allwinner,pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
--
2.9.3
^ permalink raw reply related
* [PATCH v4 2/2] ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board
From: Icenowy Zheng @ 2016-09-16 15:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916151642.27907-1-icenowy@aosc.xyz>
UART1 is connected to the bluetooth part of RTL8723BS WiFi/BT combo card
on iNet D978 Rev2 board.
Enable the UART1 to make it possible to use the modified hciattach by
Realtek to drive the BT part of RTL8723BS.
On the board no r_uart pins are found now (the onboard RX/TX pins are
wired to PF2/PF4, which is muxed with mmc0), so also disabled it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes since v4:
- Split the pinmux part into another patch.
Changes since v3:
- Change bluetooth to serial0.
Changes since v2:
- Remove stdout-path.
arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts
index 0f52cd9..fb46655 100644
--- a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts
+++ b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts
@@ -49,6 +49,15 @@
model = "INet-D978 Rev 02";
compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33";
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ /* Delete debug UART as serial0 is the UART for bluetooth */
+ /delete-property/stdout-path;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -86,3 +95,14 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
+
+&r_uart {
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_a>,
+ <&uart1_pins_cts_rts_a>;
+ status = "okay";
+};
--
2.9.3
^ permalink raw reply related
* [PATCH v4 22/22] phy: Add support for Qualcomm's USB HS phy
From: Rob Herring @ 2016-09-16 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160907213519.27340-23-stephen.boyd@linaro.org>
On Wed, Sep 07, 2016 at 02:35:19PM -0700, Stephen Boyd wrote:
> The high-speed phy on qcom SoCs is controlled via the ULPI
> viewport.
>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: <devicetree@vger.kernel.org>
> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
> ---
> .../devicetree/bindings/phy/qcom,usb-hs-phy.txt | 83 ++++++
> drivers/phy/Kconfig | 8 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-qcom-usb-hs.c | 289 +++++++++++++++++++++
> 4 files changed, 381 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt
> create mode 100644 drivers/phy/phy-qcom-usb-hs.c
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt b/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt
> new file mode 100644
> index 000000000000..d7eacd63d06b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt
> @@ -0,0 +1,83 @@
> +Qualcomm's USB HS PHY
> +
> +PROPERTIES
> +
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the
> + following:
> +
> + "qcom,usb-hs-phy-apq8064"
> + "qcom,usb-hs-phy-msm8916"
> + "qcom,usb-hs-phy-msm8974"
This is fine, but things are usually named <soc>-<ipblock>.
> +
> +- #phy-cells:
> + Usage: required
> + Value type: <u32>
> + Definition: Should contain 0
> +
> +- clocks:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: Should contain clock specifier for the reference and sleep
> + clocks
> +
> +- clock-names:
> + Usage: required
> + Value type: <stringlist>
> + Definition: Should contain "ref" and "sleep" for the reference and sleep
> + clocks respectively
> +
> +- resets:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: Should contain the phy and POR resets
> +
> +- reset-names:
> + Usage: required
> + Value type: <stringlist>
> + Definition: Should contain "phy" and "por" for the phy and POR resets
> + respectively
> +
> +- v3p3-supply:
> + Usage: required
> + Value type: <phandle>
> + Definition: Should contain a reference to the 3.3V supply
> +
> +- v1p8-supply:
> + Usage: required
> + Value type: <phandle>
> + Definition: Should contain a reference to the 1.8V supply
> +
> +- extcon:
I don't recommend using extcon binding. It needs some work to put it
nicely.
> + Usage: optional
> + Value type: <prop-encoded-array>
> + Definition: Should contain the vbus and ID extcons in the first and second
> + cells respectively
> +
> +- qcom,init-seq:
> + Usage: optional
> + Value type: <u8 array>
> + Definition: Should contain a sequence of ULPI register and address pairs to
> + program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related
> + to Device Mode Eye Diagram test.
We generally nak this type of property. For 1 register I don't care so
much. For 100, that would be another story.
Is this value per unit, per board, per SoC? Can you limit it to certain
registers?
> +
> +EXAMPLE
> +
> +otg: usb-controller {
> + ulpi {
> + phy {
> + compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy";
> + #phy-cells = <0>;
> + clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
> + clock-names = "ref", "sleep";
> + resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
> + reset-names = "phy", "por";
> + v3p3-supply = <&pm8941_l24>;
> + v1p8-supply = <&pm8941_l6>;
> + extcon = <&smbb>, <&usb_id>;
> + qcom,init-seq = /bits/ 8 <0x81 0x63>;
> + };
> + };
> +};
^ permalink raw reply
* [PATCH v6 3/3] devicetree: bindings: Add vendor prefix for Topeet.
From: Rob Herring @ 2016-09-16 15:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473285535-21996-4-git-send-email-ayaka@soulik.info>
On Thu, Sep 08, 2016 at 05:58:55AM +0800, Randy Li wrote:
> Add TOPEET, a ARM devlopment board vendor in China mainland.
>
> Signed-off-by: Randy Li <ayaka@soulik.info>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
I applied this one to avoid any merge conflicts with fixing
alphabetizing of this file this cycle.
Rob
^ permalink raw reply
* [PATCH 0/2] spi: meson: Add Amlogic GXBB compatible
From: Rob Herring @ 2016-09-16 15:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4a199a95-3ee6-a3a0-bc8a-63bd0912e7d2@suse.de>
On Thu, Sep 08, 2016 at 02:50:37PM +0200, Andreas F?rber wrote:
> Am 08.09.2016 um 14:04 schrieb Andreas F?rber:
> > Am 08.09.2016 um 09:53 schrieb Neil Armstrong:
> >> This patchset adds a specific compatible string in the Meson SPIFC driver for
> >> the Amlogic Meson GXBB SoC.
> >
> > Any particular reason? We could just reuse the meson6 one since there
> > appear to be no code changes so far.
>
> So Neil is essentially telling me they don't know whether there are any
> differences in the IP block, so a separate compatible string was chosen.
>
> No objection from my side, but a general clarification from device tree
> maintainers when and when not to would be appreciated. (+ devicetree)
New chip, always define a new compatible. If you think they are the same
or are close enough to function with the existing driver, then put both
compatible strings in the DT.
Rob
^ permalink raw reply
* [PATCH V5] perf tools: adding support for address filters
From: Mathieu Poirier @ 2016-09-16 15:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914082535.3304d51a1a6a085234f77529@kernel.org>
On 13 September 2016 at 17:25, Masami Hiramatsu <mhiramat@kernel.org> wrote:
> On Tue, 13 Sep 2016 08:18:10 -0600
> Mathieu Poirier <mathieu.poirier@linaro.org> wrote:
>
>> On 13 September 2016 at 04:01, Adrian Hunter <adrian.hunter@intel.com> wrote:
>> > On 12/09/16 20:53, Mathieu Poirier wrote:
>> >> This patch makes it possible to use the current filter
>> >> framework with address filters. That way address filters for
>> >> HW tracers such as CoreSight and IntelPT can be communicated
>> >> to the kernel drivers.
>> >>
>> >> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>> >>
>> >> ---
>> >> Changes for V5:
>> >> - Modified perf_evsel__append_filter() to take a string format
>> >> rather than an operation.
>> >
>> > Hope I'm not being a pain, but aren't there other places calling
>> > perf_evsel__append_filter() that need to be changed. Might make
>> > sense as a separate patch.
>>
>> No no, you're right - I completely overlooked that.
>>
>> But shouldn't it be in the same patch? That way a git bisect would
>> stay consistent...
>
> You're right. Caller and callee should be changed in atomic.
>
> BTW, could you add document updates how the perf command line
> will be changed, and also show the result in the patch description?
This patch does not change anything on the perf command line. It
simply allows current options to succeed (as they should) rather than
fail.
Thanks,
Mathieu
>
> Thank you,
>
>>
>> >
>> >>
>> >> Changes for V4:
>> >> - Added support for address filters over more than one
>> >> nibble.
>> >> - Removed Jiri's ack, this version is too different from
>> >> what was reviewed.
>> >>
>> >> Changes for V3:
>> >> - Added Jiri's ack.
>> >> - Rebased to v4.8-rc5.
>> >>
>> >> Changes for V2:
>> >> - Rebased to v4.8-rc4.
>> >> - Revisited error path.
>> >>
>> >>
>> >> tools/perf/util/evsel.c | 4 ++--
>> >> tools/perf/util/evsel.h | 2 +-
>> >> tools/perf/util/parse-events.c | 40 +++++++++++++++++++++++++++++++++++-----
>> >> 3 files changed, 38 insertions(+), 8 deletions(-)
>> >>
>> >> diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
>> >> index d40f852d2de2..a9bb277f221f 100644
>> >> --- a/tools/perf/util/evsel.c
>> >> +++ b/tools/perf/util/evsel.c
>> >> @@ -1047,14 +1047,14 @@ int perf_evsel__set_filter(struct perf_evsel *evsel, const char *filter)
>> >> }
>> >>
>> >> int perf_evsel__append_filter(struct perf_evsel *evsel,
>> >> - const char *op, const char *filter)
>> >> + const char *fmt, const char *filter)
>> >> {
>> >> char *new_filter;
>> >>
>> >> if (evsel->filter == NULL)
>> >> return perf_evsel__set_filter(evsel, filter);
>> >>
>> >> - if (asprintf(&new_filter,"(%s) %s (%s)", evsel->filter, op, filter) > 0) {
>> >> + if (asprintf(&new_filter, fmt, evsel->filter, filter) > 0) {
>> >> free(evsel->filter);
>> >> evsel->filter = new_filter;
>> >> return 0;
>> >> diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h
>> >> index 8ceb7ebb51f5..50595c8c7207 100644
>> >> --- a/tools/perf/util/evsel.h
>> >> +++ b/tools/perf/util/evsel.h
>> >> @@ -236,7 +236,7 @@ void perf_evsel__set_sample_id(struct perf_evsel *evsel,
>> >>
>> >> int perf_evsel__set_filter(struct perf_evsel *evsel, const char *filter);
>> >> int perf_evsel__append_filter(struct perf_evsel *evsel,
>> >> - const char *op, const char *filter);
>> >> + const char *fmt, const char *filter);
>> >> int perf_evsel__apply_filter(struct perf_evsel *evsel, int ncpus, int nthreads,
>> >> const char *filter);
>> >> int perf_evsel__apply_drv_configs(struct perf_evsel *evsel,
>> >> diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
>> >> index 2eb8b1ed4cc8..8e683979ccd8 100644
>> >> --- a/tools/perf/util/parse-events.c
>> >> +++ b/tools/perf/util/parse-events.c
>> >> @@ -1760,20 +1760,50 @@ foreach_evsel_in_last_glob(struct perf_evlist *evlist,
>> >> static int set_filter(struct perf_evsel *evsel, const void *arg)
>> >> {
>> >> const char *str = arg;
>> >> + bool found = false;
>> >> + int nr_addr_filters = 0;
>> >> + struct perf_pmu *pmu = NULL;
>> >>
>> >> - if (evsel == NULL || evsel->attr.type != PERF_TYPE_TRACEPOINT) {
>> >> - fprintf(stderr,
>> >> - "--filter option should follow a -e tracepoint option\n");
>> >> - return -1;
>> >> + if (evsel == NULL)
>> >> + goto err;
>> >> +
>> >> + if (evsel->attr.type == PERF_TYPE_TRACEPOINT) {
>> >> + if (perf_evsel__append_filter(evsel,
>> >> + "(%s) && (%s)", str) < 0) {
>> >> + fprintf(stderr,
>> >> + "not enough memory to hold filter string\n");
>> >> + return -1;
>> >> + }
>> >> +
>> >> + return 0;
>> >> }
>> >>
>> >> - if (perf_evsel__append_filter(evsel, "&&", str) < 0) {
>> >> + while ((pmu = perf_pmu__scan(pmu)) != NULL)
>> >> + if (pmu->type == evsel->attr.type) {
>> >> + found = true;
>> >> + break;
>> >> + }
>> >> +
>> >> + if (found)
>> >> + perf_pmu__scan_file(pmu, "nr_addr_filters",
>> >> + "%d", &nr_addr_filters);
>> >> +
>> >> + if (!nr_addr_filters)
>> >> + goto err;
>> >> +
>> >> + if (perf_evsel__append_filter(evsel, "%s,%s", str) < 0) {
>> >> fprintf(stderr,
>> >> "not enough memory to hold filter string\n");
>> >> return -1;
>> >> }
>> >>
>> >> return 0;
>> >> +
>> >> +err:
>> >> + fprintf(stderr,
>> >> + "--filter option should follow a -e tracepoint or HW tracer option\n");
>> >> +
>> >> + return -1;
>> >> }
>> >>
>> >> int parse_filter(const struct option *opt, const char *str,
>> >>
>> >
>
>
> --
> Masami Hiramatsu <mhiramat@kernel.org>
^ permalink raw reply
* [PATCH 1/2] dt-bindings: spi-meson: Add GXBB Compatible string
From: Rob Herring @ 2016-09-16 15:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473321206-32284-2-git-send-email-narmstrong@baylibre.com>
On Thu, Sep 08, 2016 at 09:53:25AM +0200, Neil Armstrong wrote:
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> Documentation/devicetree/bindings/spi/spi-meson.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/spi-meson.txt b/Documentation/devicetree/bindings/spi/spi-meson.txt
> index bb52a86..dc6d031 100644
> --- a/Documentation/devicetree/bindings/spi/spi-meson.txt
> +++ b/Documentation/devicetree/bindings/spi/spi-meson.txt
> @@ -7,7 +7,7 @@ NOR memories, without DMA support and a 64-byte unified transmit /
> receive buffer.
>
> Required properties:
> - - compatible: should be "amlogic,meson6-spifc"
> + - compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc"
If you are going to use both, make sure the order is clear (most
specific, best match first). Sometimes the chip names make that clear,
but not here.
> - reg: physical base address and length of the controller registers
> - clocks: phandle of the input clock for the baud rate generator
> - #address-cells: should be 1
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v4 2/2] soc: qcom: add l2 cache perf events driver
From: Neil Leeder @ 2016-09-16 15:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160901163051.GA6731@leverpostej>
Hi Mark,
Thank you for the thorough review. I will post an updated patchset which addresses
all of your comments. There is just one outstanding comment which I have a question about:
On 9/1/2016 12:30 PM, Mark Rutland wrote:
> On Tue, Aug 30, 2016 at 01:01:33PM -0400, Neil Leeder wrote:
>> +static int l2_cache__event_init(struct perf_event *event)
>> +{
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct hml2_pmu *slice;
>> + struct perf_event *sibling;
>> + struct l2cache_pmu *l2cache_pmu = to_l2cache_pmu(event->pmu);
>> +
>> + if (event->attr.type != l2cache_pmu->pmu.type)
>> + return -ENOENT;
>> +
>> + if (hwc->sample_period) {
>> + dev_warn(&l2cache_pmu->pdev->dev, "Sampling not supported\n");
>> + return -EOPNOTSUPP;
>> + }
>> +
>> + if (event->cpu < 0) {
>> + dev_warn(&l2cache_pmu->pdev->dev, "Per-task mode not supported\n");
>> + return -EOPNOTSUPP;
>> + }
>> +
>> + /* We cannot filter accurately so we just don't allow it. */
>> + if (event->attr.exclude_user || event->attr.exclude_kernel ||
>> + event->attr.exclude_hv || event->attr.exclude_idle) {
>> + dev_warn(&l2cache_pmu->pdev->dev, "Can't exclude execution levels\n");
>> + return -EOPNOTSUPP;
>> + }
>> +
>> + if (((L2_EVT_GROUP(event->attr.config) > L2_EVT_GROUP_MAX) ||
>> + (L2_EVT_PREFIX(event->attr.config) != 0) ||
>> + (L2_EVT_REG(event->attr.config) != 0)) &&
>> + (event->attr.config != L2CYCLE_CTR_RAW_CODE)) {
>> + dev_warn(&l2cache_pmu->pdev->dev, "Invalid config %llx\n",
>> + event->attr.config);
>> + return -EINVAL;
>> + }
>> +
>> + /* Don't allow groups with mixed PMUs, except for s/w events */
>> + if (event->group_leader->pmu != event->pmu &&
>> + !is_software_event(event->group_leader)) {
>> + dev_warn(&l2cache_pmu->pdev->dev,
>> + "Can't create mixed PMU group\n");
>> + return -EINVAL;
>> + }
>> +
>> + list_for_each_entry(sibling, &event->group_leader->sibling_list,
>> + group_entry)
>> + if (sibling->pmu != event->pmu &&
>> + !is_software_event(sibling)) {
>> + dev_warn(&l2cache_pmu->pdev->dev,
>> + "Can't create mixed PMU group\n");
>> + return -EINVAL;
>> + }
>> +
>> + hwc->idx = -1;
>> + hwc->config_base = event->attr.config;
>> +
>> + /*
>> + * Ensure all events are on the same cpu so all events are in the
>> + * same cpu context, to avoid races on pmu_enable etc.
>> + */
>> + slice = get_hml2_pmu(event->cpu);
>> + event->cpu = slice->on_cpu;
>
> This could put an event on a different CPU to its group siblings, which
> is broken.
This is the same logic as in arm-ccn.c:arm_ccn_pmu_event_init(), where there
is a single CPU designated as the CPU to be used for all events. All
events for this slice are forced to slice->on_cpu which is the CPU set in the
cpumask for this slice.
I'm not sure how this can put an event on a different CPU to its group siblings?
Thanks,
Neil
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH] pcie: qcom: add support to msm8996 PCIE controller
From: Srinivas Kandagatla @ 2016-09-16 15:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916141708.GA21504@rob-hp-laptop>
Thanks for the Review,
On 16/09/16 15:17, Rob Herring wrote:
> On Wed, Sep 07, 2016 at 12:06:52PM +0100, Srinivas Kandagatla wrote:
>
...
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
>> index 4059a6f..1ddfcb4 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
>> @@ -92,6 +92,18 @@
...
>> Definition: A phandle and power domain specifier pair to the
>> power domain which is responsible for collapsing
>> @@ -137,6 +156,11 @@
>> Definition: A phandle to the analog power supply for IC which generates
>> reference clock
>>
>> +- vdda_1p8-supply:
>
> Don't use '_' in property names.
Will fix it and example to match these properties in next version.
>
>> + Usage: required for msm8996/apq8096
>> + Value type: <phandle>
>> + Definition: A phandle to the analog power supply for PCIE_1P8
>> +
>> - phys:
>> Usage: required for apq8084
>> Value type: <phandle>
>> @@ -231,3 +255,65 @@
>> pinctrl-0 = <&pcie0_pins_default>;
>> pinctrl-names = "default";
>> };
>> +
>> +* Example for apq8096:
>> + pcie1: qcom,pcie at 00608000 {
>
> pcie at ...
Yep, will fix it in next version.
>
>> + compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
>> + power-domains = <&gcc PCIE1_GDSC>;
>> + bus-range = <0x00 0xff>;
>> + num-lanes = <1>;
>> +
>> + status = "disabled";
>> +
>> + reg = <0x00608000 0x2000>,
>> + <0x0d000000 0xf1d>,
>> + <0x0d000f20 0xa8>,
>> + <0x0d100000 0x100000>;
>> +
^ permalink raw reply
* [PATCH v9 07/10] arm: arm64: pmu: Assign platform PMU CPU affinity
From: Jeremy Linton @ 2016-09-16 15:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916132953.GR3380@arm.com>
Hi
Thanks for taking a look at this..
On 09/16/2016 08:29 AM, Will Deacon wrote:
> On Wed, Sep 14, 2016 at 05:32:35PM -0500, Jeremy Linton wrote:
>> On systems with multiple PMU types the PMU to CPU affinity
>> needs to be detected and set. The CPU to interrupt affinity
>> should also be set.
>>
(trimming)
>> continue;
>> ret = info->init(pmu);
>> + /*
>> + * if this pmu declaration is unspecified and we have
>> + * previously found a PMU on this platform then append
>> + * a PMU number to the pmu name. This avoids changing
>> + * the names of PMUs that are specific to a class of CPUs.
>> + * The assumption is that if we match a specific PMU in the
>> + * provided pmu_probe_info then it's unique, and another PMU
>> + * in the system will match a different entry rather than
>> + * needing the _number to assure its unique.
>> + */
>> + if ((!info->cpuid) && (duplicate_pmus)) {
>
> Hmm, the duplicate_pmus check looks a little odd here. Doesn't it mean
> that you'd end up with things like:
>
> "arm,armv8-pmuv3"
> "arm,armv8-pmuv3_1"
>
> which looks needlessly fiddly to parse. Is this intentional?
Well, IIRC, you recommend that format, or maybe I misunderstood. Anyway,
per the comment I'm trying to assure that legacy platform devices don't
accidentally get a "_X" appended to their name and break something.
Further, by itself the name itself doesn't have any meaning/ordering and
could just as well be a random string. So, I don't think anyone is going
to try and parse it except to compare it as a whole something like
"armv8_cortex_a53". Which is why the cpu affinity is required.
Additionally, doing it this way allows a tiny tweak to the pmu table in
the future to re-enable meaningful PMU names. Lastly, its big.little
exclusive, so I would rather apply pain to non-existant big.little
server machines, than uglify the common case.
^ permalink raw reply
* [PATCH v3 0/2] KVM: ARM: Enable vtimers with user space gic
From: Paolo Bonzini @ 2016-09-16 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916134619.jjiaplhxgkkl5qri@kamzik.localdomain>
On 16/09/2016 15:46, Andrew Jones wrote:
> > But I haven't even looked at the patches in detail, I was just replying
> > to the comment about testing.
>
> This may be a great time to start encouraging feature writers to submit
> kvm-unit-tests patches at the same time as the feature (Hi Alex :-) I'm
> happy to help when a test isn't easy to write due to a lack of framework,
> but don't have nearly enough bandwidth to write all the tests myself.
In this case really a kernel smoke test can just work. But yes,
architectural timer tests would be nice too.
> As for additional motivation for this series, I'll point out that it's
> good for bug isolation. When a guest fails to boot over KVM I can try
> TCG. If that works, then I've likely narrowed it to KVM. If I can
> further try kernel_irqchip=no, then I may further narrow it down to
> the vgic implementation.
(Or vice versa to the userspace GIC if you're looking at a TCG bug).
Paolo
^ permalink raw reply
* [PATCH] musb: Export musb_root_disconnect for use in modules
From: Greg Kroah-Hartman @ 2016-09-16 15:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916145936.3297-1-hdegoede@redhat.com>
On Fri, Sep 16, 2016 at 04:59:36PM +0200, Hans de Goede wrote:
> Export musb_root_disconnect for use in modules, so that musb glue
> code build as module can use it.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> drivers/usb/musb/musb_virthub.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
> index fe08e77..61b5f1c 100644
> --- a/drivers/usb/musb/musb_virthub.c
> +++ b/drivers/usb/musb/musb_virthub.c
> @@ -245,6 +245,7 @@ void musb_root_disconnect(struct musb *musb)
> usb_otg_state_string(musb->xceiv->otg->state));
> }
> }
> +EXPORT_SYMBOL_GPL(musb_root_disconnect);
>
>
> /*---------------------------------------------------------------------*/
Does this fix a build error somehow? Who reported it?
^ permalink raw reply
* [PATCH v9 07/10] arm: arm64: pmu: Assign platform PMU CPU affinity
From: Will Deacon @ 2016-09-16 15:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8d76725a-507b-4d70-8aad-993ccfa488f6@arm.com>
On Fri, Sep 16, 2016 at 10:35:32AM -0500, Jeremy Linton wrote:
> On 09/16/2016 08:29 AM, Will Deacon wrote:
> >On Wed, Sep 14, 2016 at 05:32:35PM -0500, Jeremy Linton wrote:
> >>On systems with multiple PMU types the PMU to CPU affinity
> >>needs to be detected and set. The CPU to interrupt affinity
> >>should also be set.
> >>
> (trimming)
> >> continue;
> >> ret = info->init(pmu);
> >>+ /*
> >>+ * if this pmu declaration is unspecified and we have
> >>+ * previously found a PMU on this platform then append
> >>+ * a PMU number to the pmu name. This avoids changing
> >>+ * the names of PMUs that are specific to a class of CPUs.
> >>+ * The assumption is that if we match a specific PMU in the
> >>+ * provided pmu_probe_info then it's unique, and another PMU
> >>+ * in the system will match a different entry rather than
> >>+ * needing the _number to assure its unique.
> >>+ */
> >>+ if ((!info->cpuid) && (duplicate_pmus)) {
> >
> >Hmm, the duplicate_pmus check looks a little odd here. Doesn't it mean
> >that you'd end up with things like:
> >
> >"arm,armv8-pmuv3"
> >"arm,armv8-pmuv3_1"
> >
> >which looks needlessly fiddly to parse. Is this intentional?
>
> Well, IIRC, you recommend that format, or maybe I misunderstood. Anyway, per
> the comment I'm trying to assure that legacy platform devices don't
> accidentally get a "_X" appended to their name and break something.
Ah, right, for the old 32-bit platforms that rely on probing, Gotcha.
Will
^ permalink raw reply
* [PATCH V8 0/7] perf: Driver specific configuration for PMU
From: Mathieu Poirier @ 2016-09-16 15:49 UTC (permalink / raw)
To: linux-arm-kernel
This iteration split the __get_cpuid() work in the main Makefile and
moves the driver configuration code out of file evlist.c and evsel.c so
that `perf test python` can succeed. Other than moving things around
this set is keeping the code and functionality unchanged.
Also tested with `make -C tool/perf build-test`
Thanks,
Mathieu
Original blurb:
---------------
This patchset adds the possiblity of specifying PMU driver configuration
directly from the perf command line. Anything that falls within the
event specifiers '/.../' and that is preceded by the '@' symbol is
treated as a configurable. Two formats are supported, @cfg and
@cfg=config.
For example:
perf record -e some_event/@cfg1/ ...
or
perf record -e some_event/@cfg2=config/ ...
or
perf record -e some_event/@cfg1, at cfg2=config/ ...
The above are all valid configuration and will see the strings 'cfg1'
and 'cfg2=config' sent to the PMU driver for parsing and interpretation
using the existing ioctl() mechanism.
The primary customers for this feature are the CoreSight drivers where
the selection of a sink (where trace data is accumulated) needs to be
done in a previous, and separated step, from the launching of the perf
command.
As such something that used to be a two-step process:
# echo 1 > /sys/bus/coresight/devices/20070000.etr/enable_sink
# perf record -e cs_etm//u --per-thread uname
is integrated in a single command:
# perf record -e cs_etm/@20070000.etr/u --per-thread uname
---
Changes for V8:
- Splitted what used to be 1/5 in the V7 patchset.
- Moved code around to avoid failing 'perf test pythong'.
- Tested with `make -C tool/perf build-test`.
Changes for V7:
- Got rid of a miscellaneous debug message.
- Rebased to v4.8-rc4
- Added Jiri Olsa's Acked-by.
Changes for V6:
- Using sysFS rather than an ioctl() to communicate command line
parameters to the CoreSight PMU.
Changes for V5:
- Made commit log in 5/9 more descriptive.
- Addressed missing return code in builtin-top.c.
- Overhauled the kernel portion to do parsing in the core.
Changes for V4:
- Pushing PMU driver configuration for 'perf top'.
- Rebased to the latest perf/core branch[1].
Changes for V3:
- Added comment for function drv_str() that explains the reason for
keeping the entire token intact.
- Added driver config terms to the existing list of config terms.
- Added documenation for driver specific configuration.
- Pushing PMU driver configuration for 'perf stat' as well.
- Preventing users from selecting a sink from sysFS _and_ perf.
Changes for V2:
- Rebased to [1] as per Jiri's request.
Mathieu Poirier (7):
perf tools: confining __get_cpuid() to x86 architecture
perf tools: making coresight PMU listable
perf tools: adding coresight etm PMU record capabilities
perf tools: add infrastructure for PMU specific configuration
perf tools: pushing configuration down to PMU driver
perf tools: adding PMU configuration to tools
perf tools: adding sink configuration for cs_etm PMU
MAINTAINERS | 5 +
tools/perf/Documentation/perf-record.txt | 12 +
tools/perf/Makefile.config | 11 +-
tools/perf/arch/arm/util/Build | 2 +
tools/perf/arch/arm/util/auxtrace.c | 54 +++
tools/perf/arch/arm/util/cs-etm.c | 617 +++++++++++++++++++++++++++++++
tools/perf/arch/arm/util/cs-etm.h | 26 ++
tools/perf/arch/arm/util/pmu.c | 36 ++
tools/perf/arch/arm64/util/Build | 4 +
tools/perf/builtin-record.c | 10 +
tools/perf/builtin-stat.c | 9 +
tools/perf/builtin-top.c | 13 +
tools/perf/util/Build | 1 +
tools/perf/util/auxtrace.c | 1 +
tools/perf/util/auxtrace.h | 1 +
tools/perf/util/cs-etm.h | 74 ++++
tools/perf/util/drv_configs.c | 77 ++++
tools/perf/util/drv_configs.h | 26 ++
tools/perf/util/evsel.h | 2 +
tools/perf/util/parse-events.c | 7 +-
tools/perf/util/parse-events.h | 1 +
tools/perf/util/parse-events.l | 22 ++
tools/perf/util/parse-events.y | 11 +
tools/perf/util/pmu.h | 2 +
24 files changed, 1019 insertions(+), 5 deletions(-)
create mode 100644 tools/perf/arch/arm/util/auxtrace.c
create mode 100644 tools/perf/arch/arm/util/cs-etm.c
create mode 100644 tools/perf/arch/arm/util/cs-etm.h
create mode 100644 tools/perf/arch/arm/util/pmu.c
create mode 100644 tools/perf/util/cs-etm.h
create mode 100644 tools/perf/util/drv_configs.c
create mode 100644 tools/perf/util/drv_configs.h
--
2.7.4
^ permalink raw reply
* [PATCH V8 1/7] perf tools: confining __get_cpuid() to x86 architecture
From: Mathieu Poirier @ 2016-09-16 15:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474041004-13956-1-git-send-email-mathieu.poirier@linaro.org>
The __get_cpuid() test is only valid when compiling for x86.
When compiling for other architectures like ARM/ARM64 the test
fails event if the functionality is not required.
This patch isolate the build-in feature check to x86 platform,
allowing the compilation and usage of PMUs that use the AUXTRACE
infrastructure on other architectures (i.e ARM CoreSight).
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
---
tools/perf/Makefile.config | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config
index 24803c58049a..72edf83d76b7 100644
--- a/tools/perf/Makefile.config
+++ b/tools/perf/Makefile.config
@@ -746,10 +746,13 @@ ifdef LIBBABELTRACE
endif
ifndef NO_AUXTRACE
- ifeq ($(feature-get_cpuid), 0)
- msg := $(warning Your gcc lacks the __get_cpuid() builtin, disables support for auxtrace/Intel PT, please install a newer gcc);
- NO_AUXTRACE := 1
- else
+ ifeq ($(ARCH),x86)
+ ifeq ($(feature-get_cpuid), 0)
+ msg := $(warning Your gcc lacks the __get_cpuid() builtin, disables support for auxtrace/Intel PT, please install a newer gcc);
+ NO_AUXTRACE := 1
+ endif
+ endif
+ ifndef NO_AUXTRACE
$(call detected,CONFIG_AUXTRACE)
CFLAGS += -DHAVE_AUXTRACE_SUPPORT
endif
--
2.7.4
^ permalink raw reply related
* [PATCH V8 2/7] perf tools: making coresight PMU listable
From: Mathieu Poirier @ 2016-09-16 15:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474041004-13956-1-git-send-email-mathieu.poirier@linaro.org>
Adding the required mechanic allowing 'perf list pmu' to
discover coresight ETM/PTM tracers.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
---
MAINTAINERS | 1 +
tools/perf/arch/arm/util/Build | 2 ++
tools/perf/arch/arm/util/pmu.c | 34 ++++++++++++++++++++++++++++++++++
tools/perf/arch/arm64/util/Build | 2 ++
4 files changed, 39 insertions(+)
create mode 100644 tools/perf/arch/arm/util/pmu.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 6781a3febd59..3ff44a5aa539 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1123,6 +1123,7 @@ F: drivers/hwtracing/coresight/*
F: Documentation/trace/coresight.txt
F: Documentation/devicetree/bindings/arm/coresight.txt
F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
+F: tools/perf/arch/arm/util/pmu.c
ARM/CORGI MACHINE SUPPORT
M: Richard Purdie <rpurdie@rpsys.net>
diff --git a/tools/perf/arch/arm/util/Build b/tools/perf/arch/arm/util/Build
index f98da17357c0..4093fd146f46 100644
--- a/tools/perf/arch/arm/util/Build
+++ b/tools/perf/arch/arm/util/Build
@@ -2,3 +2,5 @@ libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
libperf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
+
+libperf-$(CONFIG_AUXTRACE) += pmu.o
diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c
new file mode 100644
index 000000000000..af9fb666b44f
--- /dev/null
+++ b/tools/perf/arch/arm/util/pmu.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+#include <linux/coresight-pmu.h>
+#include <linux/perf_event.h>
+
+#include "../../util/pmu.h"
+
+struct perf_event_attr
+*perf_pmu__get_default_config(struct perf_pmu *pmu __maybe_unused)
+{
+#ifdef HAVE_AUXTRACE_SUPPORT
+ if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) {
+ /* add ETM default config here */
+ pmu->selectable = true;
+ }
+#endif
+ return NULL;
+}
diff --git a/tools/perf/arch/arm64/util/Build b/tools/perf/arch/arm64/util/Build
index 02f41dba4f4f..3876dd05bb8b 100644
--- a/tools/perf/arch/arm64/util/Build
+++ b/tools/perf/arch/arm64/util/Build
@@ -1,2 +1,4 @@
libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
+
+libperf-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o
--
2.7.4
^ permalink raw reply related
* [PATCH V8 3/7] perf tools: adding coresight etm PMU record capabilities
From: Mathieu Poirier @ 2016-09-16 15:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474041004-13956-1-git-send-email-mathieu.poirier@linaro.org>
Coresight ETMs are IP blocks used to perform HW assisted tracing
on a CPU core. This patch introduce the required auxiliary API
functions allowing the perf core to interact with a tracer.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
MAINTAINERS | 4 +
tools/perf/arch/arm/util/Build | 2 +-
tools/perf/arch/arm/util/auxtrace.c | 54 ++++
tools/perf/arch/arm/util/cs-etm.c | 559 ++++++++++++++++++++++++++++++++++++
tools/perf/arch/arm/util/cs-etm.h | 23 ++
tools/perf/arch/arm64/util/Build | 4 +-
tools/perf/util/auxtrace.c | 1 +
tools/perf/util/auxtrace.h | 1 +
tools/perf/util/cs-etm.h | 74 +++++
9 files changed, 720 insertions(+), 2 deletions(-)
create mode 100644 tools/perf/arch/arm/util/auxtrace.c
create mode 100644 tools/perf/arch/arm/util/cs-etm.c
create mode 100644 tools/perf/arch/arm/util/cs-etm.h
create mode 100644 tools/perf/util/cs-etm.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3ff44a5aa539..e8443349fb7d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1124,6 +1124,10 @@ F: Documentation/trace/coresight.txt
F: Documentation/devicetree/bindings/arm/coresight.txt
F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
F: tools/perf/arch/arm/util/pmu.c
+F: tools/perf/arch/arm/util/auxtrace.c
+F: tools/perf/arch/arm/util/cs-etm.c
+F: tools/perf/arch/arm/util/cs-etm.h
+F: tools/perf/util/cs-etm.h
ARM/CORGI MACHINE SUPPORT
M: Richard Purdie <rpurdie@rpsys.net>
diff --git a/tools/perf/arch/arm/util/Build b/tools/perf/arch/arm/util/Build
index 4093fd146f46..e64c5f216448 100644
--- a/tools/perf/arch/arm/util/Build
+++ b/tools/perf/arch/arm/util/Build
@@ -3,4 +3,4 @@ libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
libperf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
-libperf-$(CONFIG_AUXTRACE) += pmu.o
+libperf-$(CONFIG_AUXTRACE) += pmu.o auxtrace.o cs-etm.o
diff --git a/tools/perf/arch/arm/util/auxtrace.c b/tools/perf/arch/arm/util/auxtrace.c
new file mode 100644
index 000000000000..8edf2cb71564
--- /dev/null
+++ b/tools/perf/arch/arm/util/auxtrace.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdbool.h>
+#include <linux/coresight-pmu.h>
+
+#include "../../util/auxtrace.h"
+#include "../../util/evlist.h"
+#include "../../util/pmu.h"
+#include "cs-etm.h"
+
+struct auxtrace_record
+*auxtrace_record__init(struct perf_evlist *evlist, int *err)
+{
+ struct perf_pmu *cs_etm_pmu;
+ struct perf_evsel *evsel;
+ bool found_etm = false;
+
+ cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME);
+
+ if (evlist) {
+ evlist__for_each_entry(evlist, evsel) {
+ if (cs_etm_pmu &&
+ evsel->attr.type == cs_etm_pmu->type)
+ found_etm = true;
+ }
+ }
+
+ if (found_etm)
+ return cs_etm_record_init(err);
+
+ /*
+ * Clear 'err' even if we haven't found a cs_etm event - that way perf
+ * record can still be used even if tracers aren't present. The NULL
+ * return value will take care of telling the infrastructure HW tracing
+ * isn't available.
+ */
+ *err = 0;
+ return NULL;
+}
diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c
new file mode 100644
index 000000000000..829c479614f1
--- /dev/null
+++ b/tools/perf/arch/arm/util/cs-etm.c
@@ -0,0 +1,559 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <api/fs/fs.h>
+#include <linux/bitops.h>
+#include <linux/coresight-pmu.h>
+#include <linux/kernel.h>
+#include <linux/log2.h>
+#include <linux/types.h>
+
+#include "cs-etm.h"
+#include "../../perf.h"
+#include "../../util/auxtrace.h"
+#include "../../util/cpumap.h"
+#include "../../util/evlist.h"
+#include "../../util/pmu.h"
+#include "../../util/thread_map.h"
+#include "../../util/cs-etm.h"
+
+#include <stdlib.h>
+
+struct cs_etm_recording {
+ struct auxtrace_record itr;
+ struct perf_pmu *cs_etm_pmu;
+ struct perf_evlist *evlist;
+ bool snapshot_mode;
+ size_t snapshot_size;
+};
+
+static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu);
+
+static int cs_etm_parse_snapshot_options(struct auxtrace_record *itr,
+ struct record_opts *opts,
+ const char *str)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ unsigned long long snapshot_size = 0;
+ char *endptr;
+
+ if (str) {
+ snapshot_size = strtoull(str, &endptr, 0);
+ if (*endptr || snapshot_size > SIZE_MAX)
+ return -1;
+ }
+
+ opts->auxtrace_snapshot_mode = true;
+ opts->auxtrace_snapshot_size = snapshot_size;
+ ptr->snapshot_size = snapshot_size;
+
+ return 0;
+}
+
+static int cs_etm_recording_options(struct auxtrace_record *itr,
+ struct perf_evlist *evlist,
+ struct record_opts *opts)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+ struct perf_evsel *evsel, *cs_etm_evsel = NULL;
+ const struct cpu_map *cpus = evlist->cpus;
+ bool privileged = (geteuid() == 0 || perf_event_paranoid() < 0);
+
+ ptr->evlist = evlist;
+ ptr->snapshot_mode = opts->auxtrace_snapshot_mode;
+
+ evlist__for_each_entry(evlist, evsel) {
+ if (evsel->attr.type == cs_etm_pmu->type) {
+ if (cs_etm_evsel) {
+ pr_err("There may be only one %s event\n",
+ CORESIGHT_ETM_PMU_NAME);
+ return -EINVAL;
+ }
+ evsel->attr.freq = 0;
+ evsel->attr.sample_period = 1;
+ cs_etm_evsel = evsel;
+ opts->full_auxtrace = true;
+ }
+ }
+
+ /* no need to continue if at least one event of interest was found */
+ if (!cs_etm_evsel)
+ return 0;
+
+ if (opts->use_clockid) {
+ pr_err("Cannot use clockid (-k option) with %s\n",
+ CORESIGHT_ETM_PMU_NAME);
+ return -EINVAL;
+ }
+
+ /* we are in snapshot mode */
+ if (opts->auxtrace_snapshot_mode) {
+ /*
+ * No size were given to '-S' or '-m,', so go with
+ * the default
+ */
+ if (!opts->auxtrace_snapshot_size &&
+ !opts->auxtrace_mmap_pages) {
+ if (privileged) {
+ opts->auxtrace_mmap_pages = MiB(4) / page_size;
+ } else {
+ opts->auxtrace_mmap_pages =
+ KiB(128) / page_size;
+ if (opts->mmap_pages == UINT_MAX)
+ opts->mmap_pages = KiB(256) / page_size;
+ }
+ } else if (!opts->auxtrace_mmap_pages && !privileged &&
+ opts->mmap_pages == UINT_MAX) {
+ opts->mmap_pages = KiB(256) / page_size;
+ }
+
+ /*
+ * '-m,xyz' was specified but no snapshot size, so make the
+ * snapshot size as big as the auxtrace mmap area.
+ */
+ if (!opts->auxtrace_snapshot_size) {
+ opts->auxtrace_snapshot_size =
+ opts->auxtrace_mmap_pages * (size_t)page_size;
+ }
+
+ /*
+ * -Sxyz was specified but no auxtrace mmap area, so make the
+ * auxtrace mmap area big enough to fit the requested snapshot
+ * size.
+ */
+ if (!opts->auxtrace_mmap_pages) {
+ size_t sz = opts->auxtrace_snapshot_size;
+
+ sz = round_up(sz, page_size) / page_size;
+ opts->auxtrace_mmap_pages = roundup_pow_of_two(sz);
+ }
+
+ /* Snapshost size can't be bigger than the auxtrace area */
+ if (opts->auxtrace_snapshot_size >
+ opts->auxtrace_mmap_pages * (size_t)page_size) {
+ pr_err("Snapshot size %zu must not be greater than AUX area tracing mmap size %zu\n",
+ opts->auxtrace_snapshot_size,
+ opts->auxtrace_mmap_pages * (size_t)page_size);
+ return -EINVAL;
+ }
+
+ /* Something went wrong somewhere - this shouldn't happen */
+ if (!opts->auxtrace_snapshot_size ||
+ !opts->auxtrace_mmap_pages) {
+ pr_err("Failed to calculate default snapshot size and/or AUX area tracing mmap pages\n");
+ return -EINVAL;
+ }
+ }
+
+ /* We are in full trace mode but '-m,xyz' wasn't specified */
+ if (opts->full_auxtrace && !opts->auxtrace_mmap_pages) {
+ if (privileged) {
+ opts->auxtrace_mmap_pages = MiB(4) / page_size;
+ } else {
+ opts->auxtrace_mmap_pages = KiB(128) / page_size;
+ if (opts->mmap_pages == UINT_MAX)
+ opts->mmap_pages = KiB(256) / page_size;
+ }
+
+ }
+
+ /* Validate auxtrace_mmap_pages provided by user */
+ if (opts->auxtrace_mmap_pages) {
+ unsigned int max_page = (KiB(128) / page_size);
+ size_t sz = opts->auxtrace_mmap_pages * (size_t)page_size;
+
+ if (!privileged &&
+ opts->auxtrace_mmap_pages > max_page) {
+ opts->auxtrace_mmap_pages = max_page;
+ pr_err("auxtrace too big, truncating to %d\n",
+ max_page);
+ }
+
+ if (!is_power_of_2(sz)) {
+ pr_err("Invalid mmap size for %s: must be a power of 2\n",
+ CORESIGHT_ETM_PMU_NAME);
+ return -EINVAL;
+ }
+ }
+
+ if (opts->auxtrace_snapshot_mode)
+ pr_debug2("%s snapshot size: %zu\n", CORESIGHT_ETM_PMU_NAME,
+ opts->auxtrace_snapshot_size);
+
+ if (cs_etm_evsel) {
+ /*
+ * To obtain the auxtrace buffer file descriptor, the auxtrace
+ * event must come first.
+ */
+ perf_evlist__to_front(evlist, cs_etm_evsel);
+ /*
+ * In the case of per-cpu mmaps, we need the CPU on the
+ * AUX event.
+ */
+ if (!cpu_map__empty(cpus))
+ perf_evsel__set_sample_bit(cs_etm_evsel, CPU);
+ }
+
+ /* Add dummy event to keep tracking */
+ if (opts->full_auxtrace) {
+ struct perf_evsel *tracking_evsel;
+ int err;
+
+ err = parse_events(evlist, "dummy:u", NULL);
+ if (err)
+ return err;
+
+ tracking_evsel = perf_evlist__last(evlist);
+ perf_evlist__set_tracking_event(evlist, tracking_evsel);
+
+ tracking_evsel->attr.freq = 0;
+ tracking_evsel->attr.sample_period = 1;
+
+ /* In per-cpu case, always need the time of mmap events etc */
+ if (!cpu_map__empty(cpus))
+ perf_evsel__set_sample_bit(tracking_evsel, TIME);
+ }
+
+ return 0;
+}
+
+static u64 cs_etm_get_config(struct auxtrace_record *itr)
+{
+ u64 config = 0;
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+ struct perf_evlist *evlist = ptr->evlist;
+ struct perf_evsel *evsel;
+
+ evlist__for_each_entry(evlist, evsel) {
+ if (evsel->attr.type == cs_etm_pmu->type) {
+ /*
+ * Variable perf_event_attr::config is assigned to
+ * ETMv3/PTM. The bit fields have been made to match
+ * the ETMv3.5 ETRMCR register specification. See the
+ * PMU_FORMAT_ATTR() declarations in
+ * drivers/hwtracing/coresight/coresight-perf.c for
+ * details.
+ */
+ config = evsel->attr.config;
+ break;
+ }
+ }
+
+ return config;
+}
+
+static size_t
+cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
+ struct perf_evlist *evlist __maybe_unused)
+{
+ int i;
+ int etmv3 = 0, etmv4 = 0;
+ const struct cpu_map *cpus = evlist->cpus;
+
+ /* cpu map is not empty, we have specific CPUs to work with */
+ if (!cpu_map__empty(cpus)) {
+ for (i = 0; i < cpu_map__nr(cpus); i++) {
+ if (cs_etm_is_etmv4(itr, cpus->map[i]))
+ etmv4++;
+ else
+ etmv3++;
+ }
+ } else {
+ /* get configuration for all CPUs in the system */
+ for (i = 0; i < cpu__max_cpu(); i++) {
+ if (cs_etm_is_etmv4(itr, i))
+ etmv4++;
+ else
+ etmv3++;
+ }
+ }
+
+ return (CS_ETM_HEADER_SIZE +
+ (etmv4 * CS_ETMV4_PRIV_SIZE) +
+ (etmv3 * CS_ETMV3_PRIV_SIZE));
+}
+
+static const char *metadata_etmv3_ro[CS_ETM_PRIV_MAX] = {
+ [CS_ETM_ETMCCER] = "mgmt/etmccer",
+ [CS_ETM_ETMIDR] = "mgmt/etmidr",
+};
+
+static const char *metadata_etmv4_ro[CS_ETMV4_PRIV_MAX] = {
+ [CS_ETMV4_TRCIDR0] = "trcidr/trcidr0",
+ [CS_ETMV4_TRCIDR1] = "trcidr/trcidr1",
+ [CS_ETMV4_TRCIDR2] = "trcidr/trcidr2",
+ [CS_ETMV4_TRCIDR8] = "trcidr/trcidr8",
+ [CS_ETMV4_TRCAUTHSTATUS] = "mgmt/trcauthstatus",
+};
+
+static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu)
+{
+ bool ret = false;
+ char path[PATH_MAX];
+ int scan;
+ unsigned int val;
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+
+ /* Take any of the RO files for ETMv4 and see if it present */
+ snprintf(path, PATH_MAX, "cpu%d/%s",
+ cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]);
+ scan = perf_pmu__scan_file(cs_etm_pmu, path, "%x", &val);
+
+ /* The file was read successfully, we have a winner */
+ if (scan == 1)
+ ret = true;
+
+ return ret;
+}
+
+static int cs_etm_get_ro(struct perf_pmu *pmu, int cpu, const char *path)
+{
+ char pmu_path[PATH_MAX];
+ int scan;
+ unsigned int val = 0;
+
+ /* Get RO metadata from sysfs */
+ snprintf(pmu_path, PATH_MAX, "cpu%d/%s", cpu, path);
+
+ scan = perf_pmu__scan_file(pmu, pmu_path, "%x", &val);
+ if (scan != 1)
+ pr_err("%s: error reading: %s\n", __func__, pmu_path);
+
+ return val;
+}
+
+static void cs_etm_get_metadata(int cpu, u32 *offset,
+ struct auxtrace_record *itr,
+ struct auxtrace_info_event *info)
+{
+ u32 increment;
+ u64 magic;
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+
+ /* first see what kind of tracer this cpu is affined to */
+ if (cs_etm_is_etmv4(itr, cpu)) {
+ magic = __perf_cs_etmv4_magic;
+ /* Get trace configuration register */
+ info->priv[*offset + CS_ETMV4_TRCCONFIGR] =
+ cs_etm_get_config(itr);
+ /* Get traceID from the framework */
+ info->priv[*offset + CS_ETMV4_TRCTRACEIDR] =
+ coresight_get_trace_id(cpu);
+ /* Get read-only information from sysFS */
+ info->priv[*offset + CS_ETMV4_TRCIDR0] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv4_ro[CS_ETMV4_TRCIDR0]);
+ info->priv[*offset + CS_ETMV4_TRCIDR1] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv4_ro[CS_ETMV4_TRCIDR1]);
+ info->priv[*offset + CS_ETMV4_TRCIDR2] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv4_ro[CS_ETMV4_TRCIDR2]);
+ info->priv[*offset + CS_ETMV4_TRCIDR8] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv4_ro[CS_ETMV4_TRCIDR8]);
+ info->priv[*offset + CS_ETMV4_TRCAUTHSTATUS] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv4_ro
+ [CS_ETMV4_TRCAUTHSTATUS]);
+
+ /* How much space was used */
+ increment = CS_ETMV4_PRIV_MAX;
+ } else {
+ magic = __perf_cs_etmv3_magic;
+ /* Get configuration register */
+ info->priv[*offset + CS_ETM_ETMCR] = cs_etm_get_config(itr);
+ /* Get traceID from the framework */
+ info->priv[*offset + CS_ETM_ETMTRACEIDR] =
+ coresight_get_trace_id(cpu);
+ /* Get read-only information from sysFS */
+ info->priv[*offset + CS_ETM_ETMCCER] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv3_ro[CS_ETM_ETMCCER]);
+ info->priv[*offset + CS_ETM_ETMIDR] =
+ cs_etm_get_ro(cs_etm_pmu, cpu,
+ metadata_etmv3_ro[CS_ETM_ETMIDR]);
+
+ /* How much space was used */
+ increment = CS_ETM_PRIV_MAX;
+ }
+
+ /* Build generic header portion */
+ info->priv[*offset + CS_ETM_MAGIC] = magic;
+ info->priv[*offset + CS_ETM_CPU] = cpu;
+ /* Where the next CPU entry should start from */
+ *offset += increment;
+}
+
+static int cs_etm_info_fill(struct auxtrace_record *itr,
+ struct perf_session *session,
+ struct auxtrace_info_event *info,
+ size_t priv_size)
+{
+ int i;
+ u32 offset;
+ u64 nr_cpu, type;
+ const struct cpu_map *cpus = session->evlist->cpus;
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu;
+
+ if (priv_size != cs_etm_info_priv_size(itr, session->evlist))
+ return -EINVAL;
+
+ if (!session->evlist->nr_mmaps)
+ return -EINVAL;
+
+ /* If the cpu_map is empty all CPUs are involved */
+ nr_cpu = cpu_map__empty(cpus) ? cpu__max_cpu() : cpu_map__nr(cpus);
+ /* Get PMU type as dynamically assigned by the core */
+ type = cs_etm_pmu->type;
+
+ /* First fill out the session header */
+ info->type = PERF_AUXTRACE_CS_ETM;
+ info->priv[CS_HEADER_VERSION_0] = 0;
+ info->priv[CS_PMU_TYPE_CPUS] = type << 32;
+ info->priv[CS_PMU_TYPE_CPUS] |= nr_cpu;
+ info->priv[CS_ETM_SNAPSHOT] = ptr->snapshot_mode;
+
+ offset = CS_ETM_SNAPSHOT + 1;
+
+ /* cpu map is not empty, we have specific CPUs to work with */
+ if (!cpu_map__empty(cpus)) {
+ for (i = 0; i < cpu_map__nr(cpus) && offset < priv_size; i++)
+ cs_etm_get_metadata(cpus->map[i], &offset, itr, info);
+ } else {
+ /* get configuration for all CPUs in the system */
+ for (i = 0; i < cpu__max_cpu(); i++)
+ cs_etm_get_metadata(i, &offset, itr, info);
+ }
+
+ return 0;
+}
+
+static int cs_etm_find_snapshot(struct auxtrace_record *itr __maybe_unused,
+ int idx, struct auxtrace_mmap *mm,
+ unsigned char *data __maybe_unused,
+ u64 *head, u64 *old)
+{
+ pr_debug3("%s: mmap index %d old head %zu new head %zu size %zu\n",
+ __func__, idx, (size_t)*old, (size_t)*head, mm->len);
+
+ *old = *head;
+ *head += mm->len;
+
+ return 0;
+}
+
+static int cs_etm_snapshot_start(struct auxtrace_record *itr)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_evsel *evsel;
+
+ evlist__for_each_entry(ptr->evlist, evsel) {
+ if (evsel->attr.type == ptr->cs_etm_pmu->type)
+ return perf_evsel__disable(evsel);
+ }
+ return -EINVAL;
+}
+
+static int cs_etm_snapshot_finish(struct auxtrace_record *itr)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_evsel *evsel;
+
+ evlist__for_each_entry(ptr->evlist, evsel) {
+ if (evsel->attr.type == ptr->cs_etm_pmu->type)
+ return perf_evsel__enable(evsel);
+ }
+ return -EINVAL;
+}
+
+static u64 cs_etm_reference(struct auxtrace_record *itr __maybe_unused)
+{
+ return (((u64) rand() << 0) & 0x00000000FFFFFFFFull) |
+ (((u64) rand() << 32) & 0xFFFFFFFF00000000ull);
+}
+
+static void cs_etm_recording_free(struct auxtrace_record *itr)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ free(ptr);
+}
+
+static int cs_etm_read_finish(struct auxtrace_record *itr, int idx)
+{
+ struct cs_etm_recording *ptr =
+ container_of(itr, struct cs_etm_recording, itr);
+ struct perf_evsel *evsel;
+
+ evlist__for_each_entry(ptr->evlist, evsel) {
+ if (evsel->attr.type == ptr->cs_etm_pmu->type)
+ return perf_evlist__enable_event_idx(ptr->evlist,
+ evsel, idx);
+ }
+
+ return -EINVAL;
+}
+
+struct auxtrace_record *cs_etm_record_init(int *err)
+{
+ struct perf_pmu *cs_etm_pmu;
+ struct cs_etm_recording *ptr;
+
+ cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME);
+
+ if (!cs_etm_pmu) {
+ *err = -EINVAL;
+ goto out;
+ }
+
+ ptr = zalloc(sizeof(struct cs_etm_recording));
+ if (!ptr) {
+ *err = -ENOMEM;
+ goto out;
+ }
+
+ ptr->cs_etm_pmu = cs_etm_pmu;
+ ptr->itr.parse_snapshot_options = cs_etm_parse_snapshot_options;
+ ptr->itr.recording_options = cs_etm_recording_options;
+ ptr->itr.info_priv_size = cs_etm_info_priv_size;
+ ptr->itr.info_fill = cs_etm_info_fill;
+ ptr->itr.find_snapshot = cs_etm_find_snapshot;
+ ptr->itr.snapshot_start = cs_etm_snapshot_start;
+ ptr->itr.snapshot_finish = cs_etm_snapshot_finish;
+ ptr->itr.reference = cs_etm_reference;
+ ptr->itr.free = cs_etm_recording_free;
+ ptr->itr.read_finish = cs_etm_read_finish;
+
+ *err = 0;
+ return &ptr->itr;
+out:
+ return NULL;
+}
diff --git a/tools/perf/arch/arm/util/cs-etm.h b/tools/perf/arch/arm/util/cs-etm.h
new file mode 100644
index 000000000000..909f486d02d1
--- /dev/null
+++ b/tools/perf/arch/arm/util/cs-etm.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef INCLUDE__PERF_CS_ETM_H__
+#define INCLUDE__PERF_CS_ETM_H__
+
+struct auxtrace_record *cs_etm_record_init(int *err);
+
+#endif
diff --git a/tools/perf/arch/arm64/util/Build b/tools/perf/arch/arm64/util/Build
index 3876dd05bb8b..cef6fb38d17e 100644
--- a/tools/perf/arch/arm64/util/Build
+++ b/tools/perf/arch/arm64/util/Build
@@ -1,4 +1,6 @@
libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
-libperf-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o
+libperf-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o \
+ ../../arm/util/auxtrace.o \
+ ../../arm/util/cs-etm.o
diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c
index c9169011e55e..c0aba8e839aa 100644
--- a/tools/perf/util/auxtrace.c
+++ b/tools/perf/util/auxtrace.c
@@ -892,6 +892,7 @@ int perf_event__process_auxtrace_info(struct perf_tool *tool __maybe_unused,
return intel_pt_process_auxtrace_info(event, session);
case PERF_AUXTRACE_INTEL_BTS:
return intel_bts_process_auxtrace_info(event, session);
+ case PERF_AUXTRACE_CS_ETM:
case PERF_AUXTRACE_UNKNOWN:
default:
return -EINVAL;
diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h
index ac5f0d7167e6..09286f193532 100644
--- a/tools/perf/util/auxtrace.h
+++ b/tools/perf/util/auxtrace.h
@@ -41,6 +41,7 @@ enum auxtrace_type {
PERF_AUXTRACE_UNKNOWN,
PERF_AUXTRACE_INTEL_PT,
PERF_AUXTRACE_INTEL_BTS,
+ PERF_AUXTRACE_CS_ETM,
};
enum itrace_period_type {
diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h
new file mode 100644
index 000000000000..3cc6bc3263fe
--- /dev/null
+++ b/tools/perf/util/cs-etm.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright(C) 2015 Linaro Limited. All rights reserved.
+ * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
+#define INCLUDE__UTIL_PERF_CS_ETM_H__
+
+/* Versionning header in case things need tro change in the future. That way
+ * decoding of old snapshot is still possible.
+ */
+enum {
+ /* Starting with 0x0 */
+ CS_HEADER_VERSION_0,
+ /* PMU->type (32 bit), total # of CPUs (32 bit) */
+ CS_PMU_TYPE_CPUS,
+ CS_ETM_SNAPSHOT,
+ CS_HEADER_VERSION_0_MAX,
+};
+
+/* Beginning of header common to both ETMv3 and V4 */
+enum {
+ CS_ETM_MAGIC,
+ CS_ETM_CPU,
+};
+
+/* ETMv3/PTM metadata */
+enum {
+ /* Dynamic, configurable parameters */
+ CS_ETM_ETMCR = CS_ETM_CPU + 1,
+ CS_ETM_ETMTRACEIDR,
+ /* RO, taken from sysFS */
+ CS_ETM_ETMCCER,
+ CS_ETM_ETMIDR,
+ CS_ETM_PRIV_MAX,
+};
+
+/* ETMv4 metadata */
+enum {
+ /* Dynamic, configurable parameters */
+ CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1,
+ CS_ETMV4_TRCTRACEIDR,
+ /* RO, taken from sysFS */
+ CS_ETMV4_TRCIDR0,
+ CS_ETMV4_TRCIDR1,
+ CS_ETMV4_TRCIDR2,
+ CS_ETMV4_TRCIDR8,
+ CS_ETMV4_TRCAUTHSTATUS,
+ CS_ETMV4_PRIV_MAX,
+};
+
+#define KiB(x) ((x) * 1024)
+#define MiB(x) ((x) * 1024 * 1024)
+
+#define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64))
+
+static const u64 __perf_cs_etmv3_magic = 0x3030303030303030ULL;
+static const u64 __perf_cs_etmv4_magic = 0x4040404040404040ULL;
+#define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
+#define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
+
+#endif
--
2.7.4
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox