* [PATCH 07/24] ste_dma40: Use kmalloc_array() in d40_hw_detect_init()
From: SF Markus Elfring @ 2016-09-17 15:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <92810066-69b6-94e7-dcec-a28594b1328f@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Sat, 17 Sep 2016 11:44:55 +0200
A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "kmalloc_array".
This issue was detected also by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/dma/ste_dma40.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index b5d15a1..f813056 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3299,9 +3299,9 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
if (!base->lookup_log_chans)
goto failure;
- base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
- sizeof(d40_backup_regs_chan),
- GFP_KERNEL);
+ base->reg_val_backup_chan = kmalloc_array(base->num_phy_chans,
+ sizeof(d40_backup_regs_chan),
+ GFP_KERNEL);
if (!base->reg_val_backup_chan)
goto failure;
--
2.10.0
^ permalink raw reply related
* [PATCH 06/24] ste_dma40: Replace four kzalloc() calls by kcalloc() in d40_hw_detect_init()
From: SF Markus Elfring @ 2016-09-17 15:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <92810066-69b6-94e7-dcec-a28594b1328f@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Sat, 17 Sep 2016 09:56:32 +0200
* The script "checkpatch.pl" can point information out like the following.
WARNING: Prefer kcalloc over kzalloc with multiply
Thus fix the affected source code places.
* Replace the specification of data types by pointer dereferences
to make the corresponding size determination a bit safer according to
the Linux coding style convention.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/dma/ste_dma40.c | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 57d87a8..b5d15a1 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3281,19 +3281,20 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
}
- base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
+ base->phy_res = kcalloc(num_phy_chans,
+ sizeof(*base->phy_res),
GFP_KERNEL);
if (!base->phy_res)
goto failure;
- base->lookup_phy_chans = kzalloc(num_phy_chans *
- sizeof(struct d40_chan *),
+ base->lookup_phy_chans = kcalloc(num_phy_chans,
+ sizeof(*base->lookup_phy_chans),
GFP_KERNEL);
if (!base->lookup_phy_chans)
goto failure;
- base->lookup_log_chans = kzalloc(num_log_chans *
- sizeof(struct d40_chan *),
+ base->lookup_log_chans = kcalloc(num_log_chans,
+ sizeof(*base->lookup_log_chans),
GFP_KERNEL);
if (!base->lookup_log_chans)
goto failure;
@@ -3304,9 +3305,10 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
if (!base->reg_val_backup_chan)
goto failure;
- base->lcla_pool.alloc_map =
- kzalloc(num_phy_chans * sizeof(struct d40_desc *)
- * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
+ base->lcla_pool.alloc_map = kcalloc(num_phy_chans
+ * D40_LCLA_LINK_PER_EVENT_GRP,
+ sizeof(*base->lcla_pool.alloc_map),
+ GFP_KERNEL);
if (!base->lcla_pool.alloc_map)
goto failure;
--
2.10.0
^ permalink raw reply related
* [PATCH 05/24] ste_dma40: Improve a size determination in d40_of_probe()
From: SF Markus Elfring @ 2016-09-17 15:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <92810066-69b6-94e7-dcec-a28594b1328f@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Sat, 17 Sep 2016 08:28:05 +0200
Replace the specification of a data structure by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/dma/ste_dma40.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 220129e..57d87a8 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3487,9 +3487,7 @@ static int __init d40_of_probe(struct platform_device *pdev,
int num_phy = 0, num_memcpy = 0, num_disabled = 0;
const __be32 *list;
- pdata = devm_kzalloc(&pdev->dev,
- sizeof(struct stedma40_platform_data),
- GFP_KERNEL);
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
--
2.10.0
^ permalink raw reply related
* [PATCH 04/24] ste_dma40: Move an assignment in d40_lcla_allocate()
From: SF Markus Elfring @ 2016-09-17 15:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <92810066-69b6-94e7-dcec-a28594b1328f@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Sat, 17 Sep 2016 08:24:46 +0200
Move one assignment for the local variable "ret" so that its setting
will only be performed after corresponding data processing succeeded
by this function.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/dma/ste_dma40.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 76d63b6..220129e 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3402,7 +3402,7 @@ static int __init d40_lcla_allocate(struct d40_base *base)
struct d40_lcla_pool *pool = &base->lcla_pool;
unsigned long *page_list;
int i, j;
- int ret = 0;
+ int ret;
/*
* This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
@@ -3474,6 +3474,7 @@ static int __init d40_lcla_allocate(struct d40_base *base)
writel(virt_to_phys(base->lcla_pool.base),
base->virtbase + D40_DREG_LCLA);
+ ret = 0;
free_page_list:
kfree(page_list);
return ret;
--
2.10.0
^ permalink raw reply related
* [PATCH 03/24] ste_dma40: Rename a jump label in d40_lcla_allocate()
From: SF Markus Elfring @ 2016-09-17 15:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <92810066-69b6-94e7-dcec-a28594b1328f@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Sat, 17 Sep 2016 08:23:37 +0200
Adjust jump labels according to the current Linux coding style convention.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/dma/ste_dma40.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 80a199a..76d63b6 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3429,7 +3429,7 @@ static int __init d40_lcla_allocate(struct d40_base *base)
for (j = 0; j < i; j++)
free_pages(page_list[j], base->lcla_pool.pages);
- goto failure;
+ goto free_page_list;
}
if ((virt_to_phys((void *)page_list[i]) &
@@ -3456,7 +3456,7 @@ static int __init d40_lcla_allocate(struct d40_base *base)
GFP_KERNEL);
if (!base->lcla_pool.base_unaligned) {
ret = -ENOMEM;
- goto failure;
+ goto free_page_list;
}
base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
@@ -3469,12 +3469,12 @@ static int __init d40_lcla_allocate(struct d40_base *base)
if (dma_mapping_error(base->dev, pool->dma_addr)) {
pool->dma_addr = 0;
ret = -ENOMEM;
- goto failure;
+ goto free_page_list;
}
writel(virt_to_phys(base->lcla_pool.base),
base->virtbase + D40_DREG_LCLA);
-failure:
+ free_page_list:
kfree(page_list);
return ret;
}
--
2.10.0
^ permalink raw reply related
* [PATCH 02/24] ste_dma40: Return directly after a failed kmalloc_array()
From: SF Markus Elfring @ 2016-09-17 15:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <92810066-69b6-94e7-dcec-a28594b1328f@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Sat, 17 Sep 2016 08:21:30 +0200
Return directly after a memory allocation failed in this function
at the beginning.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/dma/ste_dma40.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index fbebeff..80a199a 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3412,10 +3412,8 @@ static int __init d40_lcla_allocate(struct d40_base *base)
page_list = kmalloc_array(MAX_LCLA_ALLOC_ATTEMPTS,
sizeof(*page_list),
GFP_KERNEL);
- if (!page_list) {
- ret = -ENOMEM;
- goto failure;
- }
+ if (!page_list)
+ return -ENOMEM;
/* Calculating how many pages that are required */
base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
--
2.10.0
^ permalink raw reply related
* [PATCH 01/24] ste_dma40: Use kmalloc_array() in d40_lcla_allocate()
From: SF Markus Elfring @ 2016-09-17 15:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <92810066-69b6-94e7-dcec-a28594b1328f@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Fri, 16 Sep 2016 17:56:07 +0200
* A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "kmalloc_array".
This issue was detected by using the Coccinelle software.
* Replace the specification of a data type by a pointer dereference
to make the corresponding size determination a bit safer according to
the Linux coding style convention.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/dma/ste_dma40.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 73203ac..fbebeff 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3409,9 +3409,9 @@ static int __init d40_lcla_allocate(struct d40_base *base)
* To full fill this hardware requirement without wasting 256 kb
* we allocate pages until we get an aligned one.
*/
- page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
- GFP_KERNEL);
-
+ page_list = kmalloc_array(MAX_LCLA_ALLOC_ATTEMPTS,
+ sizeof(*page_list),
+ GFP_KERNEL);
if (!page_list) {
ret = -ENOMEM;
goto failure;
--
2.10.0
^ permalink raw reply related
* [PATCH 00/24] ste_dma40: Fine-tuning for several function implementations
From: SF Markus Elfring @ 2016-09-17 15:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <566ABCD9.1060404@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Sat, 17 Sep 2016 16:56:56 +0200
Several update suggestions were taken into account
from static source code analysis.
Markus Elfring (24):
Use kmalloc_array() in d40_lcla_allocate()
Return directly after a failed kmalloc_array()
Rename a jump label in d40_lcla_allocate()
Move an assignment in d40_lcla_allocate()
Improve a size determination in d40_of_probe()
Replace four kzalloc() calls by kcalloc() in d40_hw_detect_init()
Use kmalloc_array() in d40_hw_detect_init()
Less checks in d40_hw_detect_init() after error detection
Delete unnecessary variable initialisations in d40_hw_detect_init()
Adjust the position of a jump label in d40_probe()
Rename a jump label in d40_probe()
Rename jump labels in d40_dmaengine_init()
Rename a jump label in d40_alloc_chan_resources()
One check less in d40_prep_sg() after error detection
Move two assignments in d40_prep_sg()
Rename a jump label in d40_prep_desc()
Move an assignment in d40_prep_desc()
Rename a jump label in d40_is_paused()
Rename a jump label in d40_free_dma()
Rename a jump label in d40_alloc_mask_free()
Rename jump labels in d40_alloc_mask_set()
Rename a jump label in dma_tasklet()
Rename a jump label in __d40_execute_command_phy()
Rename a jump label in d40_log_lli_to_lcxa()
drivers/dma/ste_dma40.c | 253 +++++++++++++++++++++++-------------------------
1 file changed, 122 insertions(+), 131 deletions(-)
--
2.10.0
^ permalink raw reply
* [PATCH v2 3/4] arm64: dts: add Allwinner A64 SoC .dtsi
From: Maxime Ripard @ 2016-09-17 14:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <fad78d40-b595-633c-6d43-6246ec893635@arm.com>
On Thu, Sep 15, 2016 at 01:08:45AM +0100, Andr? Przywara wrote:
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org>
> > L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> > S: Maintained
> > N: sun[x456789]i
> > +F: arch/arm64/boot/dts/allwinner/
>
> If you promise to not break it needlessly ;-)
We started doing so since 4.7, and we're already fighting needlessly
with maintainers because of that.
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu at 0 {
>
> This is probably me to blame here since I put you up to it, but you need
> "cpux" names (e.g. "cpu0: cpu at 0 {") to match the ones that the PMU node
> references below. dtc will refuse to compile it otherwise.
Gaah, yes, of course.
> > + i2c1_pins: i2c1_pins {
> > + allwinner,pins = "PH2", "PH3";
> > + allwinner,function = "i2c1";
> > + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> > + };
> > +
> > + uart0_pins_a: uart0 at 0 {
> > + allwinner,pins = "PB8", "PB9";
> > + allwinner,function = "uart0";
> > + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> > + };
>
> So did I get this right that there is a strict "no user - no pins"
> policy here?
> I don't see a reason why we shouldn't have at least the other UART pins
> described here as well - since they are a pure SoC property. That would
> make it easier for people to enable them (with a simple, scripted fdt
> one-liner command in U-Boot, for instance).
To avoid having huge DT that are longer to load and parse, especially
since every one wires it in the exact same way all the time. And the
combination is just too high.
On the A64, the UART0 can be exposed through PB9 and PF4 for TX, and
PB8 and PF2 for RX. Even though the common usage would be to use PB8
and PB9, or PF4 and PF6. But absolutely nothing prevents from using
PB8 and PF4.
You can then add CTS and RTS into the mix, and multiply that by the
number of devices in the SoC.
> I guess there will never be an official DT with more than 2 UARTs
> enabled, although we have actually five UARTs on the headers on the
> Pine64, for instance (and personally I am looking into using one as a
> terminal server).
We relaxed the rule lately however. Boards that have access to those
UARTs on their headers can put a node in their DT with the right
muxing filled already. Which brings you the simple, script fdt
one-liner in U-Boot.
> Also UART1 is connected to that WiFi/Bluetooth slot, having it enabled
> should make BT work without further ado (but I haven't tested this).
That's probably not true. You'll most likely need to enable a few
regulators to have it working.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [RFC PATCH] PCI/ACPI: xgene: Add ECAM quirk for X-Gene PCIe controller
From: Duc Dang @ 2016-09-17 14:24 UTC (permalink / raw)
To: linux-arm-kernel
PCIe controller in X-Gene SoCs is not ECAM compliant: software
needs to configure additional concontroller register to address
device at bus:dev:function.
This patch depends on "ECAM quirks handling for ARM64 platforms"
series (http://www.spinics.net/lists/arm-kernel/msg530692.html)
to address the limitation above for X-Gene PCIe controller.
The quirk will only be applied for X-Gene PCIe MCFG table with
OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs).
Signed-off-by: Duc Dang <dhdang@apm.com>
---
drivers/acpi/pci_mcfg.c | 32 +++++
drivers/pci/host/Makefile | 2 +-
drivers/pci/host/pci-xgene-ecam.c | 280 ++++++++++++++++++++++++++++++++++++++
include/linux/pci-ecam.h | 5 +
4 files changed, 318 insertions(+), 1 deletion(-)
create mode 100644 drivers/pci/host/pci-xgene-ecam.c
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index ddf338b..adce35f 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -123,6 +123,38 @@ static struct mcfg_fixup mcfg_quirks[] = {
{ "CAVIUM", "THUNDERX", 2, 13, MCFG_BUS_ANY, &pci_thunder_ecam_ops,
MCFG_RES_EMPTY},
#endif
+#ifdef CONFIG_PCI_XGENE
+ {"APM ", "XGENE ", 1, 0, MCFG_BUS_ANY,
+ &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 1, 1, MCFG_BUS_ANY,
+ &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 1, 2, MCFG_BUS_ANY,
+ &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 1, 3, MCFG_BUS_ANY,
+ &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 1, 4, MCFG_BUS_ANY,
+ &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 2, 0, MCFG_BUS_ANY,
+ &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 2, 1, MCFG_BUS_ANY,
+ &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 2, 2, MCFG_BUS_ANY,
+ &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 2, 3, MCFG_BUS_ANY,
+ &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 2, 4, MCFG_BUS_ANY,
+ &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 3, 0, MCFG_BUS_ANY,
+ &xgene_v2_1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 3, 1, MCFG_BUS_ANY,
+ &xgene_v2_1_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 4, 0, MCFG_BUS_ANY,
+ &xgene_v2_2_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 4, 1, MCFG_BUS_ANY,
+ &xgene_v2_2_pcie_ecam_ops, MCFG_RES_EMPTY},
+ {"APM ", "XGENE ", 4, 2, MCFG_BUS_ANY,
+ &xgene_v2_2_pcie_ecam_ops, MCFG_RES_EMPTY},
+#endif
};
static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 8843410..af4f505 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
-obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
+obj-$(CONFIG_PCI_XGENE) += pci-xgene.o pci-xgene-ecam.o
obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
diff --git a/drivers/pci/host/pci-xgene-ecam.c b/drivers/pci/host/pci-xgene-ecam.c
new file mode 100644
index 0000000..b66a04f
--- /dev/null
+++ b/drivers/pci/host/pci-xgene-ecam.c
@@ -0,0 +1,280 @@
+/*
+ * APM X-Gene PCIe ECAM fixup driver
+ *
+ * Copyright (c) 2016, Applied Micro Circuits Corporation
+ * Author:
+ * Duc Dang <dhdang@apm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/pci-acpi.h>
+#include <linux/platform_device.h>
+#include <linux/pci-ecam.h>
+
+#ifdef CONFIG_ACPI
+#define RTDID 0x160
+#define ROOT_CAP_AND_CTRL 0x5C
+
+/* PCIe IP version */
+#define XGENE_PCIE_IP_VER_UNKN 0
+#define XGENE_PCIE_IP_VER_1 1
+#define XGENE_PCIE_IP_VER_2 2
+
+#define XGENE_CSR_LENGTH 0x10000
+
+struct xgene_pcie_acpi_root {
+ void __iomem *csr_base;
+ u32 version;
+};
+
+static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
+{
+ struct xgene_pcie_acpi_root *xgene_root;
+ struct device *dev = cfg->parent;
+ u32 csr_base;
+
+ xgene_root = devm_kzalloc(dev, sizeof(*xgene_root), GFP_KERNEL);
+ if (!xgene_root)
+ return -ENOMEM;
+
+ switch (cfg->res.start) {
+ case 0xE0D0000000ULL:
+ csr_base = 0x1F2B0000;
+ break;
+ case 0xD0D0000000ULL:
+ csr_base = 0x1F2C0000;
+ break;
+ case 0x90D0000000ULL:
+ csr_base = 0x1F2D0000;
+ break;
+ case 0xA0D0000000ULL:
+ csr_base = 0x1F500000;
+ break;
+ case 0xC0D0000000ULL:
+ csr_base = 0x1F510000;
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ xgene_root->csr_base = ioremap(csr_base, XGENE_CSR_LENGTH);
+ if (!xgene_root->csr_base) {
+ kfree(xgene_root);
+ return -ENODEV;
+ }
+
+ xgene_root->version = XGENE_PCIE_IP_VER_1;
+
+ cfg->priv = xgene_root;
+
+ return 0;
+}
+
+static int xgene_v2_1_pcie_ecam_init(struct pci_config_window *cfg)
+{
+ struct xgene_pcie_acpi_root *xgene_root;
+ struct device *dev = cfg->parent;
+ resource_size_t csr_base;
+
+ xgene_root = devm_kzalloc(dev, sizeof(*xgene_root), GFP_KERNEL);
+ if (!xgene_root)
+ return -ENOMEM;
+
+ switch (cfg->res.start) {
+ case 0xC0D0000000ULL:
+ csr_base = 0x1F2B0000;
+ break;
+ case 0xA0D0000000ULL:
+ csr_base = 0x1F2C0000;
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ xgene_root->csr_base = ioremap(csr_base, XGENE_CSR_LENGTH);
+ if (!xgene_root->csr_base) {
+ kfree(xgene_root);
+ return -ENODEV;
+ }
+
+ xgene_root->version = XGENE_PCIE_IP_VER_2;
+
+ cfg->priv = xgene_root;
+
+ return 0;
+}
+
+static int xgene_v2_2_pcie_ecam_init(struct pci_config_window *cfg)
+{
+ struct xgene_pcie_acpi_root *xgene_root;
+ struct device *dev = cfg->parent;
+ resource_size_t csr_base;
+
+ xgene_root = devm_kzalloc(dev, sizeof(*xgene_root), GFP_KERNEL);
+ if (!xgene_root)
+ return -ENOMEM;
+
+ switch (cfg->res.start) {
+ case 0xE0D0000000ULL:
+ csr_base = 0x1F2B0000;
+ break;
+ case 0xA0D0000000ULL:
+ csr_base = 0x1F500000;
+ break;
+ case 0x90D0000000ULL:
+ csr_base = 0x1F2D0000;
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ xgene_root->csr_base = ioremap(csr_base, XGENE_CSR_LENGTH);
+ if (!xgene_root->csr_base) {
+ kfree(xgene_root);
+ return -ENODEV;
+ }
+
+ xgene_root->version = XGENE_PCIE_IP_VER_2;
+
+ cfg->priv = xgene_root;
+
+ return 0;
+}
+/*
+ * For Configuration request, RTDID register is used as Bus Number,
+ * Device Number and Function number of the header fields.
+ */
+static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
+{
+ struct pci_config_window *cfg = bus->sysdata;
+ struct xgene_pcie_acpi_root *port = cfg->priv;
+ unsigned int b, d, f;
+ u32 rtdid_val = 0;
+
+ b = bus->number;
+ d = PCI_SLOT(devfn);
+ f = PCI_FUNC(devfn);
+
+ if (!pci_is_root_bus(bus))
+ rtdid_val = (b << 8) | (d << 3) | f;
+
+ writel(rtdid_val, port->csr_base + RTDID);
+ /* read the register back to ensure flush */
+ readl(port->csr_base + RTDID);
+}
+
+/*
+ * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
+ * the translation from PCI bus to native BUS. Entire DDR region
+ * is mapped into PCIe space using these registers, so it can be
+ * reached by DMA from EP devices. The BAR0/1 of bridge should be
+ * hidden during enumeration to avoid the sizing and resource allocation
+ * by PCIe core.
+ */
+static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
+{
+ if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
+ (offset == PCI_BASE_ADDRESS_1)))
+ return true;
+
+ return false;
+}
+
+void __iomem *xgene_pcie_ecam_map_bus(struct pci_bus *bus,
+ unsigned int devfn, int where)
+{
+ struct pci_config_window *cfg = bus->sysdata;
+ unsigned int busn = bus->number;
+ void __iomem *base;
+
+ if (busn < cfg->busr.start || busn > cfg->busr.end)
+ return NULL;
+
+ if ((pci_is_root_bus(bus) && devfn != 0) ||
+ xgene_pcie_hide_rc_bars(bus, where))
+ return NULL;
+
+ xgene_pcie_set_rtdid_reg(bus, devfn);
+
+ if (busn > cfg->busr.start)
+ base = cfg->win + (1 << cfg->ops->bus_shift);
+ else
+ base = cfg->win;
+
+ return base + where;
+}
+
+static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct pci_config_window *cfg = bus->sysdata;
+ struct xgene_pcie_acpi_root *port = cfg->priv;
+
+ if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
+ PCIBIOS_SUCCESSFUL)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ /*
+ * The v1 controller has a bug in its Configuration Request
+ * Retry Status (CRS) logic: when CRS is enabled and we read the
+ * Vendor and Device ID of a non-existent device, the controller
+ * fabricates return data of 0xFFFF0001 ("device exists but is not
+ * ready") instead of 0xFFFFFFFF ("device does not exist"). This
+ * causes the PCI core to retry the read until it times out.
+ * Avoid this by not claiming to support CRS.
+ */
+ if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
+ ((where & ~0x3) == ROOT_CAP_AND_CTRL))
+ *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
+
+ if (size <= 2)
+ *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
+ .bus_shift = 16,
+ .init = xgene_v1_pcie_ecam_init,
+ .pci_ops = {
+ .map_bus = xgene_pcie_ecam_map_bus,
+ .read = xgene_pcie_config_read32,
+ .write = pci_generic_config_write,
+ }
+};
+
+struct pci_ecam_ops xgene_v2_1_pcie_ecam_ops = {
+ .bus_shift = 16,
+ .init = xgene_v2_1_pcie_ecam_init,
+ .pci_ops = {
+ .map_bus = xgene_pcie_ecam_map_bus,
+ .read = xgene_pcie_config_read32,
+ .write = pci_generic_config_write,
+ }
+};
+
+struct pci_ecam_ops xgene_v2_2_pcie_ecam_ops = {
+ .bus_shift = 16,
+ .init = xgene_v2_2_pcie_ecam_init,
+ .pci_ops = {
+ .map_bus = xgene_pcie_ecam_map_bus,
+ .read = xgene_pcie_config_read32,
+ .write = pci_generic_config_write,
+ }
+};
+#endif
diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
index 35f0e81..40da3e7 100644
--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
@@ -65,6 +65,11 @@ extern struct pci_ecam_ops pci_thunder_pem_ops;
#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
extern struct pci_ecam_ops pci_thunder_ecam_ops;
#endif
+#ifdef CONFIG_PCI_XGENE
+extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops;
+extern struct pci_ecam_ops xgene_v2_1_pcie_ecam_ops;
+extern struct pci_ecam_ops xgene_v2_2_pcie_ecam_ops;
+#endif
#ifdef CONFIG_PCI_HOST_GENERIC
/* for DT-based PCI controllers that support ECAM */
--
1.9.1
^ permalink raw reply related
* [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks
From: Maxime Ripard @ 2016-09-17 14:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914214554.GH7243@codeaurora.org>
Hi Stephen,
On Wed, Sep 14, 2016 at 02:45:54PM -0700, Stephen Boyd wrote:
> On 09/09, Maxime Ripard wrote:
> > index 106cba27c331..964f22091a10 100644
> > --- a/drivers/clk/sunxi-ng/Makefile
> > +++ b/drivers/clk/sunxi-ng/Makefile
> > @@ -22,3 +22,4 @@ obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
> > obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
> > obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
> > obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
> > +obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
>
> Maybe do alphanumeric ordering?
Yes, of course.
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > new file mode 100644
> > index 000000000000..d51ee416f515
> > --- /dev/null
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > @@ -0,0 +1,870 @@
> > +
> > +static void __init sun50i_a64_ccu_setup(struct device_node *node)
> > +{
> > + void __iomem *reg;
> > + u32 val;
> > +
> > + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> > + if (IS_ERR(reg)) {
> > + pr_err("%s: Could not map the clock registers\n",
> > + of_node_full_name(node));
> > + return;
> > + }
> > +
> > + /* Force the PLL-Audio-1x divider to 4 */
> > + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
> > + val &= ~GENMASK(19, 16);
> > + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
> > +
> > + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
> > +
> > + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc);
> > +}
> > +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu",
> > + sun50i_a64_ccu_setup);
>
> Is there a reason it can't be a platform driver?
We have timers connected to those clocks. I'm not sure we'll ever use
them, since we also have the arch timers, and we can always change
that later, I'll change that.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v2 1/4] clk: sunxi-ng: Add A64 clocks
From: Maxime Ripard @ 2016-09-17 14:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65fg_5j7RmiwHUSJfiZfR78Dmv7EOLEm9eDNtxMJ-MuFQ@mail.gmail.com>
Hi,
On Sat, Sep 10, 2016 at 11:24:48AM +0800, Chen-Yu Tsai wrote:
> > +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
> > + "osc24M", 0x028,
> > + 8, 5, /* N */
> > + 4, 2, /* K */
>
> The manual says to give preference to K >= 2. I suggest swapping N/K and
> leaving a note about it, so the actual K is in the inner loop (see ccu_nk.c)
> of the factor calculation.
It also says that we should fix that frequency (and we don't), so we
don't really care.
> > +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
> > + "pll-video0", 0x040,
> > + 8, 4, /* N */
> > + 4, 2, /* K */
>
> You need a table for K. (Manual says K >= 2).
Not really a table, but a minimum, like we have a maximum already.
> > +static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M",
> > + 0x074, 0, 2, ths_div_table, BIT(31), 0);
>
> Even though the mux has only one valid parent, I suggest you still implement it,
> in case some bogus value gets put in before the kernel loads.
Ack.
> > +static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
> > +static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
> > + 0, 4, /* M */
> > + 16, 2, /* P */
> > + 24, 2, /* mux */
>
> Manual says the mux is 4 bits wide.
Ack.
> > +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
> > + "pll-audio-2x", "pll-audio" };
> > +static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
> > + 0x0b0, 16, 2, BIT(31), 0);
> > +
> > +static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
> > + 0x0b4, 16, 2, BIT(31), 0);
> > +
> > +static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
> > + 0x0b8, 16, 2, BIT(31), 0);
> > +
> > +static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
> > + 0x0c0, 0, 4, BIT(31), 0);
>
> CLK_SET_PARENT_RATE for the above audio clocks?
Indeed.
> > +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
> > + 0x0cc, BIT(8), 0);
> > +static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
> > + 0x0cc, BIT(9), 0);
> > +static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
> > + 0x0cc, BIT(10), 0);
> > +static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
> > + 0x0cc, BIT(11), 0);
> > +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
> > + 0x0cc, BIT(16), 0);
> > +static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",
> > + 0x0cc, BIT(17), 0);
>
> I guess we aren't modeling the 2 OHCI 12M muxes?
To be honest, I can't even make sense of it. Which clocks are using it
is unclear to me, so yeah, I don't know. I can probably leave some ID
for it though, just in case.
> > +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
> > +static const u8 tcon1_table[] = { 0, 2, };
> > +struct ccu_div tcon1_clk = {
> > + .enable = BIT(31),
> > + .div = _SUNXI_CCU_DIV(0, 4),
> > + .mux = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table),
> > + .common = {
> > + .reg = 0x11c,
> > + .hw.init = CLK_HW_INIT_PARENTS("tcon1",
> > + tcon1_parents,
> > + &ccu_div_ops,
> > + 0),
> > + },
> > +};
>
> CLK_SET_PARENT_RATE for the TCON clocks?
Yep
> > +static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
> > + 0x140, BIT(31), 0);
> > +
> > +static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
> > + 0x140, BIT(30), 0);
>
> CLK_SET_PARENT_RATE for the above audio clocks?
Ack.
> > +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
> > + 0x144, BIT(31), 0);
> > +
> > +static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
> > +static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
> > + 0x150, 0, 4, 24, 2, BIT(31), 0);
>
> Might need CLK_SET_PARENT_RATE for hdmi?
Ack
> > +static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
> > + 0x154, BIT(31), 0);
> > +
> > +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
> > + "pll-ddr0", "pll-ddr1" };
> > +static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
> > + 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
> > +
> > +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
>
> You need a mux table = { 0, 2 } here.
Indeed
> > +static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
> > + 0x168, 0, 3, 24, 2, BIT(31), 0);
> > +
> > +static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
> > + 0x1a0, 0, 3, BIT(31), 0);
>
> CLK_SET_PARENT_RATE for the GPU clock?
Ack
> > +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
> > + "pll-video0", 1, 2, 0);
>
> CLK_SET_PARENT_RATE for pll-video0-2x.
Ack
>
> > +
> > +static struct ccu_common *sun50i_a64_ccu_clks[] = {
> > + &pll_cpux_clk.common,
> > + &pll_audio_base_clk.common,
> > + &pll_video0_clk.common,
> > + &pll_ve_clk.common,
> > + &pll_ddr0_clk.common,
> > + &pll_periph0_clk.common,
> > + &pll_periph1_clk.common,
> > + &pll_video1_clk.common,
> > + &pll_gpu_clk.common,
> > + &pll_mipi_clk.common,
> > + &pll_hsic_clk.common,
> > + &pll_de_clk.common,
> > + &pll_ddr1_clk.common,
> > + &cpux_clk.common,
> > + &axi_clk.common,
> > + &ahb1_clk.common,
> > + &apb1_clk.common,
> > + &apb2_clk.common,
> > + &ahb2_clk.common,
> > + &bus_mipi_dsi_clk.common,
> > + &bus_ce_clk.common,
> > + &bus_dma_clk.common,
> > + &bus_mmc0_clk.common,
> > + &bus_mmc1_clk.common,
> > + &bus_mmc2_clk.common,
> > + &bus_nand_clk.common,
> > + &bus_dram_clk.common,
> > + &bus_emac_clk.common,
> > + &bus_ts_clk.common,
> > + &bus_hstimer_clk.common,
> > + &bus_spi0_clk.common,
> > + &bus_spi1_clk.common,
> > + &bus_otg_clk.common,
> > + &bus_ehci0_clk.common,
> > + &bus_ehci1_clk.common,
> > + &bus_ohci0_clk.common,
> > + &bus_ohci1_clk.common,
> > + &bus_ve_clk.common,
> > + &bus_tcon0_clk.common,
> > + &bus_tcon1_clk.common,
> > + &bus_deinterlace_clk.common,
> > + &bus_csi_clk.common,
> > + &bus_hdmi_clk.common,
> > + &bus_de_clk.common,
> > + &bus_gpu_clk.common,
> > + &bus_msgbox_clk.common,
> > + &bus_spinlock_clk.common,
> > + &bus_codec_clk.common,
> > + &bus_spdif_clk.common,
> > + &bus_pio_clk.common,
> > + &bus_ths_clk.common,
> > + &bus_i2s0_clk.common,
> > + &bus_i2s1_clk.common,
> > + &bus_i2s2_clk.common,
> > + &bus_i2c0_clk.common,
> > + &bus_i2c1_clk.common,
> > + &bus_i2c2_clk.common,
> > + &bus_scr_clk.common,
> > + &bus_uart0_clk.common,
> > + &bus_uart1_clk.common,
> > + &bus_uart2_clk.common,
> > + &bus_uart3_clk.common,
> > + &bus_uart4_clk.common,
> > + &bus_dbg_clk.common,
> > + &ths_clk.common,
> > + &nand_clk.common,
> > + &mmc0_clk.common,
> > + &mmc1_clk.common,
> > + &mmc2_clk.common,
> > + &ts_clk.common,
> > + &ce_clk.common,
> > + &spi0_clk.common,
> > + &spi1_clk.common,
> > + &i2s0_clk.common,
> > + &i2s1_clk.common,
> > + &i2s2_clk.common,
> > + &spdif_clk.common,
> > + &usb_phy0_clk.common,
> > + &usb_phy1_clk.common,
> > + &usb_hsic_clk.common,
> > + &usb_hsic_12m_clk.common,
> > + &usb_ohci0_clk.common,
> > + &usb_ohci1_clk.common,
> > + &dram_clk.common,
> > + &dram_ve_clk.common,
> > + &dram_csi_clk.common,
> > + &dram_deinterlace_clk.common,
> > + &dram_ts_clk.common,
> > + &de_clk.common,
> > + &tcon0_clk.common,
> > + &tcon1_clk.common,
> > + &deinterlace_clk.common,
> > + &csi_misc_clk.common,
> > + &csi_sclk_clk.common,
> > + &csi_mclk_clk.common,
> > + &ve_clk.common,
> > + &ac_dig_clk.common,
> > + &ac_dig_4x_clk.common,
> > + &avs_clk.common,
> > + &hdmi_clk.common,
> > + &hdmi_ddc_clk.common,
> > + &mbus_clk.common,
> > + &dsi_dphy_clk.common,
> > + &gpu_clk.common,
> > +};
> > +
> > +static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
> > + .hws = {
> > + [CLK_OSC_12M] = &osc12M_clk.hw,
> > + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
> > + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
> > + [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
> > + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
> > + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
> > + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
> > + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
> > + [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
> > + [CLK_PLL_VE] = &pll_ve_clk.common.hw,
> > + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
> > + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
> > + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
> > + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
> > + [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
> > + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
> > + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
> > + [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
> > + [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
> > + [CLK_PLL_DE] = &pll_de_clk.common.hw,
> > + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
> > + [CLK_CPUX] = &cpux_clk.common.hw,
> > + [CLK_AXI] = &axi_clk.common.hw,
> > + [CLK_AHB1] = &ahb1_clk.common.hw,
> > + [CLK_APB1] = &apb1_clk.common.hw,
> > + [CLK_APB2] = &apb2_clk.common.hw,
> > + [CLK_AHB2] = &ahb2_clk.common.hw,
> > + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
> > + [CLK_BUS_CE] = &bus_ce_clk.common.hw,
> > + [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
> > + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
> > + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
> > + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
> > + [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
> > + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
> > + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
> > + [CLK_BUS_TS] = &bus_ts_clk.common.hw,
> > + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
> > + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
> > + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
> > + [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
> > + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
> > + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
> > + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
> > + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
> > + [CLK_BUS_VE] = &bus_ve_clk.common.hw,
> > + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
> > + [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
> > + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
> > + [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
> > + [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
> > + [CLK_BUS_DE] = &bus_de_clk.common.hw,
> > + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
> > + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
> > + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
> > + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
> > + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
> > + [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
> > + [CLK_BUS_THS] = &bus_ths_clk.common.hw,
> > + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
> > + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
> > + [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
> > + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
> > + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
> > + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
> > + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
> > + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
> > + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
> > + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
> > + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
> > + [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
> > + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
> > + [CLK_THS] = &ths_clk.common.hw,
> > + [CLK_NAND] = &nand_clk.common.hw,
> > + [CLK_MMC0] = &mmc0_clk.common.hw,
> > + [CLK_MMC1] = &mmc1_clk.common.hw,
> > + [CLK_MMC2] = &mmc2_clk.common.hw,
> > + [CLK_TS] = &ts_clk.common.hw,
> > + [CLK_CE] = &ce_clk.common.hw,
> > + [CLK_SPI0] = &spi0_clk.common.hw,
> > + [CLK_SPI1] = &spi1_clk.common.hw,
> > + [CLK_I2S0] = &i2s0_clk.common.hw,
> > + [CLK_I2S1] = &i2s1_clk.common.hw,
> > + [CLK_I2S2] = &i2s2_clk.common.hw,
> > + [CLK_SPDIF] = &spdif_clk.common.hw,
> > + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
> > + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
> > + [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
> > + [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
> > + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
> > + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
> > + [CLK_DRAM] = &dram_clk.common.hw,
> > + [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
> > + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
> > + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
> > + [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
> > + [CLK_DE] = &de_clk.common.hw,
> > + [CLK_TCON0] = &tcon0_clk.common.hw,
> > + [CLK_TCON1] = &tcon1_clk.common.hw,
> > + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
> > + [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
> > + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
> > + [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
> > + [CLK_VE] = &ve_clk.common.hw,
> > + [CLK_AC_DIG] = &ac_dig_clk.common.hw,
> > + [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
> > + [CLK_AVS] = &avs_clk.common.hw,
> > + [CLK_HDMI] = &hdmi_clk.common.hw,
> > + [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
> > + [CLK_MBUS] = &mbus_clk.common.hw,
> > + [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
> > + [CLK_GPU] = &gpu_clk.common.hw,
> > + },
> > + .num = CLK_NUMBER,
> > +};
> > +
> > +static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
> > + [RST_USB_PHY0] = { 0x0cc, BIT(0) },
> > + [RST_USB_PHY1] = { 0x0cc, BIT(1) },
> > + [RST_USB_HSIC] = { 0x0cc, BIT(2) },
> > +
> > +
> > + [RST_MBUS] = { 0x0fc, BIT(31) },
> > +
> > + [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
> > + [RST_BUS_CE] = { 0x2c0, BIT(5) },
> > + [RST_BUS_DMA] = { 0x2c0, BIT(6) },
> > + [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
> > + [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
> > + [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
> > + [RST_BUS_NAND] = { 0x2c0, BIT(13) },
> > + [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
> > + [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
> > + [RST_BUS_TS] = { 0x2c0, BIT(18) },
> > + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
> > + [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
> > + [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
> > + [RST_BUS_OTG] = { 0x2c0, BIT(23) },
> > + [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
> > + [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
> > + [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
> > + [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
> > +
> > + [RST_BUS_VE] = { 0x2c4, BIT(0) },
> > + [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
> > + [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
> > + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
> > + [RST_BUS_CSI] = { 0x2c4, BIT(8) },
> > + [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
> > + [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
> > + [RST_BUS_DE] = { 0x2c4, BIT(12) },
> > + [RST_BUS_GPU] = { 0x2c4, BIT(20) },
> > + [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
> > + [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
> > + [RST_BUS_DBG] = { 0x2c4, BIT(31) },
> > +
> > + [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
> > +
> > + [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
> > + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
> > + [RST_BUS_THS] = { 0x2d0, BIT(8) },
> > + [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
> > + [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
> > + [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
> > +
> > + [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
> > + [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
> > + [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
> > + [RST_BUS_SCR] = { 0x2d8, BIT(5) },
> > + [RST_BUS_UART0] = { 0x2d8, BIT(16) },
> > + [RST_BUS_UART1] = { 0x2d8, BIT(17) },
> > + [RST_BUS_UART2] = { 0x2d8, BIT(18) },
> > + [RST_BUS_UART3] = { 0x2d8, BIT(19) },
> > + [RST_BUS_UART4] = { 0x2d8, BIT(20) },
> > +};
> > +
> > +static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
> > + .ccu_clks = sun50i_a64_ccu_clks,
> > + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks),
> > +
> > + .hw_clks = &sun50i_a64_hw_clks,
> > +
> > + .resets = sun50i_a64_ccu_resets,
> > + .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
> > +};
> > +
> > +static void __init sun50i_a64_ccu_setup(struct device_node *node)
> > +{
> > + void __iomem *reg;
> > + u32 val;
> > +
> > + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> > + if (IS_ERR(reg)) {
> > + pr_err("%s: Could not map the clock registers\n",
> > + of_node_full_name(node));
> > + return;
> > + }
> > +
> > + /* Force the PLL-Audio-1x divider to 4 */
> > + val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
> > + val &= ~GENMASK(19, 16);
> > + writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
> > +
> > + writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
> > +
> > + sunxi_ccu_probe(node, reg, &sun50i_a64_ccu_desc);
> > +}
> > +CLK_OF_DECLARE(sun50i_a64_ccu, "allwinner,sun50i-a64-ccu",
> > + sun50i_a64_ccu_setup);
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
> > new file mode 100644
> > index 000000000000..e3c77d92af1c
> > --- /dev/null
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
> > @@ -0,0 +1,68 @@
> > +/*
> > + * Copyright 2016 Maxime Ripard
> > + *
> > + * Maxime Ripard <maxime.ripard@free-electrons.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef _CCU_SUN50I_A64_H_
> > +#define _CCU_SUN50I_A64_H_
> > +
> > +#include <dt-bindings/clock/sun50i-a64-ccu.h>
> > +#include <dt-bindings/reset/sun50i-a64-ccu.h>
> > +
> > +#define CLK_OSC_12M 0
> > +#define CLK_PLL_CPUX 1
> > +#define CLK_PLL_AUDIO_BASE 2
> > +#define CLK_PLL_AUDIO 3
> > +#define CLK_PLL_AUDIO_2X 4
> > +#define CLK_PLL_AUDIO_4X 5
> > +#define CLK_PLL_AUDIO_8X 6
> > +#define CLK_PLL_VIDEO0 7
> > +#define CLK_PLL_VIDEO0_2X 8
> > +#define CLK_PLL_VE 9
> > +#define CLK_PLL_DDR0 10
> > +#define CLK_PLL_PERIPH0 11
> > +#define CLK_PLL_PERIPH0_2X 12
> > +#define CLK_PLL_PERIPH1 13
> > +#define CLK_PLL_PERIPH1_2X 14
> > +#define CLK_PLL_VIDEO1 15
> > +#define CLK_PLL_GPU 16
> > +#define CLK_PLL_MIPI 17
> > +#define CLK_PLL_HSIC 18
> > +#define CLK_PLL_DE 19
> > +#define CLK_PLL_DDR1 20
> > +#define CLK_CPUX 21
> > +#define CLK_AXI 22
> > +#define CLK_APB 23
>
> This is listed but never implemented.
Yes, on purpose. If we ever need to implement it, we won't have an
headache.
> > +#define RST_USB_PHY0 0
> > +#define RST_USB_PHY1 1
> > +#define RST_USB_HSIC 2
>
> There's also a DRAM reset in 0xf4 (DRAM configuration)
Ack.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [RFC PATCH 9/9] ethernet: sun8i-emac: add pm_runtime support
From: Maxime Ripard @ 2016-09-17 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914140304.GA27639@Red>
On Wed, Sep 14, 2016 at 04:03:04PM +0200, LABBE Corentin wrote:
> > > +static int __maybe_unused sun8i_emac_suspend(struct platform_device *pdev, pm_message_t state)
> > > +{
> > > + struct net_device *ndev = platform_get_drvdata(pdev);
> > > + struct sun8i_emac_priv *priv = netdev_priv(ndev);
> > > +
> > > + napi_disable(&priv->napi);
> > > +
> > > + if (netif_running(ndev))
> > > + netif_device_detach(ndev);
> > > +
> > > + sun8i_emac_stop_tx(ndev);
> > > + sun8i_emac_stop_rx(ndev);
> > > +
> > > + sun8i_emac_rx_clean(ndev);
> > > + sun8i_emac_tx_clean(ndev);
> > > +
> > > + phy_stop(ndev->phydev);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int __maybe_unused sun8i_emac_resume(struct platform_device *pdev)
> > > +{
> > > + struct net_device *ndev = platform_get_drvdata(pdev);
> > > + struct sun8i_emac_priv *priv = netdev_priv(ndev);
> > > +
> > > + phy_start(ndev->phydev);
> > > +
> > > + sun8i_emac_start_tx(ndev);
> > > + sun8i_emac_start_rx(ndev);
> > > +
> > > + if (netif_running(ndev))
> > > + netif_device_attach(ndev);
> > > +
> > > + netif_start_queue(ndev);
> > > +
> > > + napi_enable(&priv->napi);
> > > +
> > > + return 0;
> > > +}
> >
> > The main idea behind the runtime PM hooks is that they bring the
> > device to a working state and shuts it down when it's not needed
> > anymore.
Indeed.
> I expect that the first part (all pm_runtime_xxx) of the patch bring that.
> When the interface is not opened:
> cat /sys/devices/platform/soc/1c30000.ethernet/power/runtime_status
> suspended
>
> > However, they shouldn't be called when the device is still in used, so
> > all the mangling with NAPI, the phy and so on is irrelevant here, but
> > the clocks, resets, for example, are.
> >
>
> I do the same as other ethernet driver for suspend/resume.
suspend / resume are used when you put the whole system into suspend,
and bring it back.
runtime_pm is only when the device is not used anymore. It makes sense
when you suspend to do whatever you're doing here. It doesn't make any
when the system is not suspended, but the device is.
> > > static const struct of_device_id sun8i_emac_of_match_table[] = {
> > > { .compatible = "allwinner,sun8i-a83t-emac",
> > > .data = &emac_variant_a83t },
> > > @@ -2246,6 +2302,8 @@ static struct platform_driver sun8i_emac_driver = {
> > > .name = "sun8i-emac",
> > > .of_match_table = sun8i_emac_of_match_table,
> > > },
> > > + .suspend = sun8i_emac_suspend,
> > > + .resume = sun8i_emac_resume,
> >
> > These are not the runtime PM hooks. How did you test that?
> >
>
> Anyway I didnt test suspend/resume so I will remove it until I
> successfully found how to hibernate my board.
So you submit code you never tested? That's usually a recipe for
disaster.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH V5] perf tools: adding support for address filters
From: Masami Hiramatsu @ 2016-09-17 13:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANLsYkwRUps0Mtc_yQfNOW+qsmOXT8yaGrDj4566LPPTrLsUxg@mail.gmail.com>
On Fri, 16 Sep 2016 09:32:43 -0600
Mathieu Poirier <mathieu.poirier@linaro.org> wrote:
> On 13 September 2016 at 17:25, Masami Hiramatsu <mhiramat@kernel.org> wrote:
> > On Tue, 13 Sep 2016 08:18:10 -0600
> > Mathieu Poirier <mathieu.poirier@linaro.org> wrote:
> >
> >> On 13 September 2016 at 04:01, Adrian Hunter <adrian.hunter@intel.com> wrote:
> >> > On 12/09/16 20:53, Mathieu Poirier wrote:
> >> >> This patch makes it possible to use the current filter
> >> >> framework with address filters. That way address filters for
> >> >> HW tracers such as CoreSight and IntelPT can be communicated
> >> >> to the kernel drivers.
> >> >>
> >> >> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> >> >>
> >> >> ---
> >> >> Changes for V5:
> >> >> - Modified perf_evsel__append_filter() to take a string format
> >> >> rather than an operation.
> >> >
> >> > Hope I'm not being a pain, but aren't there other places calling
> >> > perf_evsel__append_filter() that need to be changed. Might make
> >> > sense as a separate patch.
> >>
> >> No no, you're right - I completely overlooked that.
> >>
> >> But shouldn't it be in the same patch? That way a git bisect would
> >> stay consistent...
> >
> > You're right. Caller and callee should be changed in atomic.
> >
> > BTW, could you add document updates how the perf command line
> > will be changed, and also show the result in the patch description?
>
> This patch does not change anything on the perf command line. It
> simply allows current options to succeed (as they should) rather than
> fail.
Yes, and it will make perf acceptable to pass --filter to CoreSight or
Intel PT events, or am I misunderstand?
If it is correct, could you give us an example how to pass it, since
tools/perf/Documentation/perf-record.txt says it is only for tracepoints?
Thank you,
>
> Thanks,
> Mathieu
>
> >
> > Thank you,
> >
> >>
> >> >
> >> >>
> >> >> Changes for V4:
> >> >> - Added support for address filters over more than one
> >> >> nibble.
> >> >> - Removed Jiri's ack, this version is too different from
> >> >> what was reviewed.
> >> >>
> >> >> Changes for V3:
> >> >> - Added Jiri's ack.
> >> >> - Rebased to v4.8-rc5.
> >> >>
> >> >> Changes for V2:
> >> >> - Rebased to v4.8-rc4.
> >> >> - Revisited error path.
> >> >>
> >> >>
> >> >> tools/perf/util/evsel.c | 4 ++--
> >> >> tools/perf/util/evsel.h | 2 +-
> >> >> tools/perf/util/parse-events.c | 40 +++++++++++++++++++++++++++++++++++-----
> >> >> 3 files changed, 38 insertions(+), 8 deletions(-)
> >> >>
> >> >> diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
> >> >> index d40f852d2de2..a9bb277f221f 100644
> >> >> --- a/tools/perf/util/evsel.c
> >> >> +++ b/tools/perf/util/evsel.c
> >> >> @@ -1047,14 +1047,14 @@ int perf_evsel__set_filter(struct perf_evsel *evsel, const char *filter)
> >> >> }
> >> >>
> >> >> int perf_evsel__append_filter(struct perf_evsel *evsel,
> >> >> - const char *op, const char *filter)
> >> >> + const char *fmt, const char *filter)
> >> >> {
> >> >> char *new_filter;
> >> >>
> >> >> if (evsel->filter == NULL)
> >> >> return perf_evsel__set_filter(evsel, filter);
> >> >>
> >> >> - if (asprintf(&new_filter,"(%s) %s (%s)", evsel->filter, op, filter) > 0) {
> >> >> + if (asprintf(&new_filter, fmt, evsel->filter, filter) > 0) {
> >> >> free(evsel->filter);
> >> >> evsel->filter = new_filter;
> >> >> return 0;
> >> >> diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h
> >> >> index 8ceb7ebb51f5..50595c8c7207 100644
> >> >> --- a/tools/perf/util/evsel.h
> >> >> +++ b/tools/perf/util/evsel.h
> >> >> @@ -236,7 +236,7 @@ void perf_evsel__set_sample_id(struct perf_evsel *evsel,
> >> >>
> >> >> int perf_evsel__set_filter(struct perf_evsel *evsel, const char *filter);
> >> >> int perf_evsel__append_filter(struct perf_evsel *evsel,
> >> >> - const char *op, const char *filter);
> >> >> + const char *fmt, const char *filter);
> >> >> int perf_evsel__apply_filter(struct perf_evsel *evsel, int ncpus, int nthreads,
> >> >> const char *filter);
> >> >> int perf_evsel__apply_drv_configs(struct perf_evsel *evsel,
> >> >> diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
> >> >> index 2eb8b1ed4cc8..8e683979ccd8 100644
> >> >> --- a/tools/perf/util/parse-events.c
> >> >> +++ b/tools/perf/util/parse-events.c
> >> >> @@ -1760,20 +1760,50 @@ foreach_evsel_in_last_glob(struct perf_evlist *evlist,
> >> >> static int set_filter(struct perf_evsel *evsel, const void *arg)
> >> >> {
> >> >> const char *str = arg;
> >> >> + bool found = false;
> >> >> + int nr_addr_filters = 0;
> >> >> + struct perf_pmu *pmu = NULL;
> >> >>
> >> >> - if (evsel == NULL || evsel->attr.type != PERF_TYPE_TRACEPOINT) {
> >> >> - fprintf(stderr,
> >> >> - "--filter option should follow a -e tracepoint option\n");
> >> >> - return -1;
> >> >> + if (evsel == NULL)
> >> >> + goto err;
> >> >> +
> >> >> + if (evsel->attr.type == PERF_TYPE_TRACEPOINT) {
> >> >> + if (perf_evsel__append_filter(evsel,
> >> >> + "(%s) && (%s)", str) < 0) {
> >> >> + fprintf(stderr,
> >> >> + "not enough memory to hold filter string\n");
> >> >> + return -1;
> >> >> + }
> >> >> +
> >> >> + return 0;
> >> >> }
> >> >>
> >> >> - if (perf_evsel__append_filter(evsel, "&&", str) < 0) {
> >> >> + while ((pmu = perf_pmu__scan(pmu)) != NULL)
> >> >> + if (pmu->type == evsel->attr.type) {
> >> >> + found = true;
> >> >> + break;
> >> >> + }
> >> >> +
> >> >> + if (found)
> >> >> + perf_pmu__scan_file(pmu, "nr_addr_filters",
> >> >> + "%d", &nr_addr_filters);
> >> >> +
> >> >> + if (!nr_addr_filters)
> >> >> + goto err;
> >> >> +
> >> >> + if (perf_evsel__append_filter(evsel, "%s,%s", str) < 0) {
> >> >> fprintf(stderr,
> >> >> "not enough memory to hold filter string\n");
> >> >> return -1;
> >> >> }
> >> >>
> >> >> return 0;
> >> >> +
> >> >> +err:
> >> >> + fprintf(stderr,
> >> >> + "--filter option should follow a -e tracepoint or HW tracer option\n");
> >> >> +
> >> >> + return -1;
> >> >> }
> >> >>
> >> >> int parse_filter(const struct option *opt, const char *str,
> >> >>
> >> >
> >
> >
> > --
> > Masami Hiramatsu <mhiramat@kernel.org>
--
Masami Hiramatsu <mhiramat@kernel.org>
^ permalink raw reply
* [PATCH v2] input: touchscreen: Add support for Elan eKTF2127 touchscreen controller
From: Hans de Goede @ 2016-09-17 12:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916185654.GA14732@dtor-ws>
Hi,
On 16-09-16 20:56, Dmitry Torokhov wrote:
> On Fri, Sep 02, 2016 at 09:09:35AM -0500, Rob Herring wrote:
>> On Sun, Aug 28, 2016 at 06:00:05PM +0200, Hans de Goede wrote:
>>> From: Siebren Vroegindeweij <siebren.vroegindeweij@hotmail.com>
>>>
>>> This adds a driver for the Elan eKTF2127 touchscreen controller,
>>> which speaks an i2c protocol which is distinctly different from
>>> the already supported eKTH controllers.
>>>
>>> Signed-off-by: Michel Verlaan <michel.verl@gmail.com>
>>> Signed-off-by: Siebren Vroegindeweij <siebren.vroegindeweij@hotmail.com>
>>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>>> ---
>>> Changes in v2:
>>> -Improve devicetree bindings document
>>> -Use touchscreen_parse_properties and touchscreen_report_pos instead of DIY
>>> -Remove a bunch of unused defines (copy and paste leftover from chipone driver)
>>> -Some other minor cleanups and review comments addressed
>>> -Add defines for some command / address hex-values
>>> -Check packet header in interrupt handler
>>> ---
>>> .../bindings/input/touchscreen/ektf2127.txt | 27 ++
>>
>> Acked-by: Rob Herring <robh@kernel.org>
>
> I'd like to merge the version below (factored out querying dimensions
> and parsing/reporting touch), can you please give it a spin?
Just tested it, works as advertised. Nice cleanup, esp. the
refactoring of the dimension querying, I should have tought of
that myself.
Regards,
Hans
^ permalink raw reply
* [PATCH 5/6] arm/arm64: vgic-new: Implement VGICv3 CPU interface access
From: Marc Zyngier @ 2016-09-17 11:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CALicx6ucEH3w58Rhb8Urk0V5kRcqtUdwDYDtSLXrkas-Jatv=A@mail.gmail.com>
On Sat, 17 Sep 2016 11:58:48 +0530
Vijay Kilari <vijay.kilari@gmail.com> wrote:
> On Fri, Sep 16, 2016 at 10:37 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> > On 16/09/16 17:57, Vijay Kilari wrote:
> >> On Fri, Sep 16, 2016 at 8:06 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> >>> On 16/09/16 13:20, vijay.kilari at gmail.com wrote:
> >>>> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> >>>>
> >>>> VGICv3 CPU interface registers are accessed using
> >>>> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
> >>>> as 64-bit. The cpu MPIDR value is passed along with register id.
> >>>> is used to identify the cpu for registers access.
> >>>>
> >>>> The version of VGIC v3 specification is define here
> >>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
> >>>>
> >>>> Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
> >>>> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> >>>> ---
> >>>> arch/arm64/include/uapi/asm/kvm.h | 3 +
> >>>> arch/arm64/kvm/Makefile | 1 +
> >>>> include/linux/irqchip/arm-gic-v3.h | 30 ++++
> >>>> virt/kvm/arm/vgic/vgic-kvm-device.c | 27 ++++
> >>>> virt/kvm/arm/vgic/vgic-mmio-v3.c | 18 +++
> >>>> virt/kvm/arm/vgic/vgic-sys-reg-v3.c | 296 ++++++++++++++++++++++++++++++++++++
> >>>> virt/kvm/arm/vgic/vgic.h | 10 ++
> >>>> 7 files changed, 385 insertions(+)
> >
> > [...]
> >
> >>>> diff --git a/virt/kvm/arm/vgic/vgic-sys-reg-v3.c b/virt/kvm/arm/vgic/vgic-sys-reg-v3.c
> >>>> new file mode 100644
> >>>> index 0000000..8e4f403
> >>>> --- /dev/null
> >>>> +++ b/virt/kvm/arm/vgic/vgic-sys-reg-v3.c
> >>>> @@ -0,0 +1,296 @@
> >>>> +#include <linux/irqchip/arm-gic-v3.h>
> >>>> +#include <linux/kvm.h>
> >>>> +#include <linux/kvm_host.h>
> >>>> +#include <kvm/iodev.h>
> >>>> +#include <kvm/arm_vgic.h>
> >>>> +#include <asm/kvm_emulate.h>
> >>>> +#include <asm/kvm_arm.h>
> >>>> +#include <asm/kvm_mmu.h>
> >>>> +
> >>>> +#include "vgic.h"
> >>>> +#include "vgic-mmio.h"
> >>>> +#include "sys_regs.h"
> >>>> +
> >>>> +static bool access_gic_ctlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> >>>> + const struct sys_reg_desc *r)
> >>>> +{
> >>>> + struct vgic_vmcr vmcr;
> >>>> + u64 val;
> >>>> + u32 ich_vtr;
> >>>> +
> >>>> + vgic_get_vmcr(vcpu, &vmcr);
> >>>> + if (p->is_write) {
> >>>> + val = p->regval;
> >>>> + vmcr.ctlr &= ~(ICH_VMCR_CBPR_MASK | ICH_VMCR_EOIM_MASK);
> >>>> + vmcr.ctlr |= ((val & ICC_CTLR_EL1_CBPR_MASK) >>
> >>>> + ICC_CTLR_EL1_CBPR_SHIFT) << ICH_VMCR_CBPR_SHIFT;
> >>>> + vmcr.ctlr |= ((val & ICC_CTLR_EL1_EOImode_MASK) >>
> >>>> + ICC_CTLR_EL1_EOImode_SHIFT) << ICH_VMCR_EOIM_SHIFT;
> >>>> + vgic_set_vmcr(vcpu, &vmcr);
> >>>
> >>> You've ignored my comments again: "What if userspace writes something
> >>> that is incompatible with the current configuration? Wrong number of ID
> >>> bits, or number of priorities?"
> >>
> >> IMO, In case of incompatibility,
> >> If ID bits and PRI bits are less than HW supported, it is ok.
> >
> > Yes. But you also need to track of what the guest has programmed in
> > order to be able to migrate it back to its original configuration.
>
> You mean the vgic has to track/store the ID and PRI bits that guest
> has programmed
> and return the same when guest reads back instead of
> returning HW supported value for ICC_CTLR_EL1 reg access?.
If you have two hosts (A and B), A having 5 bits of priority and B
having 7 bits, you should be able to migrate from A to B, and then from
B to A. Which means you have to preserve what the guest knows to be its
configuration, even if you run on a more capable system. Otherwise,
you're a bit stuck.
You probably won't be able to hide the discrepancy from inside the
guest though (the guest will be able to observe the change), but this
is better than nothing.
Thanks,
M.
--
Jazz is not dead. It just smells funny.
^ permalink raw reply
* [RFT] arm64 dts: exynos: Fix invalid GIC interrupt flags in exynos7
From: Alim Akhtar @ 2016-09-17 11:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474056073-8071-1-git-send-email-krzk@kernel.org>
Hi Krzysztof,
On 09/17/2016 01:31 AM, Krzysztof Kozlowski wrote:
> Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
> generates an error:
> genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
>
> The GIC requires shared interrupts to be edge rising or level high.
> Platform declares support for both. Choose level high everywhere.
>
> Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
This patch does resolve the error reported in commit.
Have booted on exynos7 board, things looks fine (have not done a
extensive testing though).
With the _Typo_ fixed as pointed by you, feel free to add
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
On another note, please cc me if case you want to check/verify something
on exynos7 platform. I almost missed this patch.
Thanks.
> arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 20 +++++--
> arch/arm64/boot/dts/exynos/exynos7.dtsi | 69 +++++++++++++------------
> 2 files changed, 51 insertions(+), 38 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> index f77ddaf21d04..983c63ba38c8 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
> @@ -20,8 +20,14 @@
> interrupt-controller;
> interrupt-parent = <&gic>;
> #interrupt-cells = <2>;
> - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
> - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
> + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
> + <0 1 IRQ_TYPE_LEVEL_HIGH>,
> + <0 2 IRQ_TYPE_LEVEL_HIGH>,
> + <0 3 IRQ_TYPE_LEVEL_HIGH>,
> + <0 4 IRQ_TYPE_LEVEL_HIGH>,
> + <0 5 IRQ_TYPE_LEVEL_HIGH>,
> + <0 6 IRQ_TYPE_LEVEL_HIGH>,
> + <0 7 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> gpa1: gpa1 {
> @@ -31,8 +37,14 @@
> interrupt-controller;
> interrupt-parent = <&gic>;
> #interrupt-cells = <2>;
> - interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
> - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
> + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
> + <0 9 IRQ_TYPE_LEVEL_HIGH>
> + <0 10 IRQ_TYPE_LEVEL_HIGH>,
> + <0 11 IRQ_TYPE_LEVEL_HIGH>,
> + <0 12 IRQ_TYPE_LEVEL_HIGH>,
> + <0 13 IRQ_TYPE_LEVEL_HIGH>,
> + <0 14 IRQ_TYPE_LEVEL_HIGH>,
> + <0 15 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> gpa2: gpa2 {
> diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> index 6328a66ed97e..0a80dabfbe95 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
> @@ -106,7 +106,7 @@
> pdma0: pdma at 10E10000 {
> compatible = "arm,pl330", "arm,primecell";
> reg = <0x10E10000 0x1000>;
> - interrupts = <0 225 0>;
> + interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clock_fsys0 ACLK_PDMA0>;
> clock-names = "apb_pclk";
> #dma-cells = <1>;
> @@ -117,7 +117,7 @@
> pdma1: pdma at 10EB0000 {
> compatible = "arm,pl330", "arm,primecell";
> reg = <0x10EB0000 0x1000>;
> - interrupts = <0 226 0>;
> + interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clock_fsys0 ACLK_PDMA1>;
> clock-names = "apb_pclk";
> #dma-cells = <1>;
> @@ -220,7 +220,7 @@
> serial_0: serial at 13630000 {
> compatible = "samsung,exynos4210-uart";
> reg = <0x13630000 0x100>;
> - interrupts = <0 440 0>;
> + interrupts = <0 440 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clock_peric0 PCLK_UART0>,
> <&clock_peric0 SCLK_UART0>;
> clock-names = "uart", "clk_uart_baud0";
> @@ -230,7 +230,7 @@
> serial_1: serial at 14c20000 {
> compatible = "samsung,exynos4210-uart";
> reg = <0x14c20000 0x100>;
> - interrupts = <0 456 0>;
> + interrupts = <0 456 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clock_peric1 PCLK_UART1>,
> <&clock_peric1 SCLK_UART1>;
> clock-names = "uart", "clk_uart_baud0";
> @@ -240,7 +240,7 @@
> serial_2: serial at 14c30000 {
> compatible = "samsung,exynos4210-uart";
> reg = <0x14c30000 0x100>;
> - interrupts = <0 457 0>;
> + interrupts = <0 457 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clock_peric1 PCLK_UART2>,
> <&clock_peric1 SCLK_UART2>;
> clock-names = "uart", "clk_uart_baud0";
> @@ -250,7 +250,7 @@
> serial_3: serial at 14c40000 {
> compatible = "samsung,exynos4210-uart";
> reg = <0x14c40000 0x100>;
> - interrupts = <0 458 0>;
> + interrupts = <0 458 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clock_peric1 PCLK_UART3>,
> <&clock_peric1 SCLK_UART3>;
> clock-names = "uart", "clk_uart_baud0";
> @@ -264,62 +264,62 @@
> wakeup-interrupt-controller {
> compatible = "samsung,exynos7-wakeup-eint";
> interrupt-parent = <&gic>;
> - interrupts = <0 16 0>;
> + interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
> };
> };
>
> pinctrl_bus0: pinctrl at 13470000 {
> compatible = "samsung,exynos7-pinctrl";
> reg = <0x13470000 0x1000>;
> - interrupts = <0 383 0>;
> + interrupts = <0 383 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> pinctrl_nfc: pinctrl at 14cd0000 {
> compatible = "samsung,exynos7-pinctrl";
> reg = <0x14cd0000 0x1000>;
> - interrupts = <0 473 0>;
> + interrupts = <0 473 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> pinctrl_touch: pinctrl at 14ce0000 {
> compatible = "samsung,exynos7-pinctrl";
> reg = <0x14ce0000 0x1000>;
> - interrupts = <0 474 0>;
> + interrupts = <0 474 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> pinctrl_ff: pinctrl at 14c90000 {
> compatible = "samsung,exynos7-pinctrl";
> reg = <0x14c90000 0x1000>;
> - interrupts = <0 475 0>;
> + interrupts = <0 475 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> pinctrl_ese: pinctrl at 14ca0000 {
> compatible = "samsung,exynos7-pinctrl";
> reg = <0x14ca0000 0x1000>;
> - interrupts = <0 476 0>;
> + interrupts = <0 476 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> pinctrl_fsys0: pinctrl at 10e60000 {
> compatible = "samsung,exynos7-pinctrl";
> reg = <0x10e60000 0x1000>;
> - interrupts = <0 221 0>;
> + interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> pinctrl_fsys1: pinctrl at 15690000 {
> compatible = "samsung,exynos7-pinctrl";
> reg = <0x15690000 0x1000>;
> - interrupts = <0 203 0>;
> + interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> pinctrl_bus1: pinctrl at 14870000 {
> compatible = "samsung,exynos7-pinctrl";
> reg = <0x14870000 0x1000>;
> - interrupts = <0 384 0>;
> + interrupts = <0 384 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> hsi2c_0: hsi2c at 13640000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x13640000 0x1000>;
> - interrupts = <0 441 0>;
> + interrupts = <0 441 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -332,7 +332,7 @@
> hsi2c_1: hsi2c at 13650000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x13650000 0x1000>;
> - interrupts = <0 442 0>;
> + interrupts = <0 442 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -345,7 +345,7 @@
> hsi2c_2: hsi2c at 14e60000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x14e60000 0x1000>;
> - interrupts = <0 459 0>;
> + interrupts = <0 459 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -358,7 +358,7 @@
> hsi2c_3: hsi2c at 14e70000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x14e70000 0x1000>;
> - interrupts = <0 460 0>;
> + interrupts = <0 460 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -371,7 +371,7 @@
> hsi2c_4: hsi2c at 13660000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x13660000 0x1000>;
> - interrupts = <0 443 0>;
> + interrupts = <0 443 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -384,7 +384,7 @@
> hsi2c_5: hsi2c at 13670000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x13670000 0x1000>;
> - interrupts = <0 444 0>;
> + interrupts = <0 444 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -397,7 +397,7 @@
> hsi2c_6: hsi2c at 14e00000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x14e00000 0x1000>;
> - interrupts = <0 461 0>;
> + interrupts = <0 461 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -410,7 +410,7 @@
> hsi2c_7: hsi2c at 13e10000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x13e10000 0x1000>;
> - interrupts = <0 462 0>;
> + interrupts = <0 462 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -423,7 +423,7 @@
> hsi2c_8: hsi2c at 14e20000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x14e20000 0x1000>;
> - interrupts = <0 463 0>;
> + interrupts = <0 463 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -436,7 +436,7 @@
> hsi2c_9: hsi2c at 13680000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x13680000 0x1000>;
> - interrupts = <0 445 0>;
> + interrupts = <0 445 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -449,7 +449,7 @@
> hsi2c_10: hsi2c at 13690000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x13690000 0x1000>;
> - interrupts = <0 446 0>;
> + interrupts = <0 446 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -462,7 +462,7 @@
> hsi2c_11: hsi2c at 136a0000 {
> compatible = "samsung,exynos7-hsi2c";
> reg = <0x136a0000 0x1000>;
> - interrupts = <0 447 0>;
> + interrupts = <0 447 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> pinctrl-names = "default";
> @@ -499,7 +499,8 @@
> rtc: rtc at 10590000 {
> compatible = "samsung,s3c6410-rtc";
> reg = <0x10590000 0x100>;
> - interrupts = <0 355 0>, <0 356 0>;
> + interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>,
> + <0 356 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clock_ccore PCLK_RTC>;
> clock-names = "rtc";
> status = "disabled";
> @@ -508,7 +509,7 @@
> watchdog: watchdog at 101d0000 {
> compatible = "samsung,exynos7-wdt";
> reg = <0x101d0000 0x100>;
> - interrupts = <0 110 0>;
> + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clock_peris PCLK_WDT>;
> clock-names = "watchdog";
> samsung,syscon-phandle = <&pmu_system_controller>;
> @@ -517,7 +518,7 @@
>
> mmc_0: mmc at 15740000 {
> compatible = "samsung,exynos7-dw-mshc-smu";
> - interrupts = <0 201 0>;
> + interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x15740000 0x2000>;
> @@ -530,7 +531,7 @@
>
> mmc_1: mmc at 15750000 {
> compatible = "samsung,exynos7-dw-mshc";
> - interrupts = <0 202 0>;
> + interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x15750000 0x2000>;
> @@ -543,7 +544,7 @@
>
> mmc_2: mmc at 15560000 {
> compatible = "samsung,exynos7-dw-mshc-smu";
> - interrupts = <0 216 0>;
> + interrupts = <0 216 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x15560000 0x2000>;
> @@ -557,7 +558,7 @@
> adc: adc at 13620000 {
> compatible = "samsung,exynos7-adc";
> reg = <0x13620000 0x100>;
> - interrupts = <0 448 0>;
> + interrupts = <0 448 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clock_peric0 PCLK_ADCIF>;
> clock-names = "adc";
> #io-channel-cells = <1>;
> @@ -577,7 +578,7 @@
> tmuctrl_0: tmu at 10060000 {
> compatible = "samsung,exynos7-tmu";
> reg = <0x10060000 0x200>;
> - interrupts = <0 108 0>;
> + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clock_peris PCLK_TMU>,
> <&clock_peris SCLK_TMU>;
> clock-names = "tmu_apbif", "tmu_sclk";
>
^ permalink raw reply
* [PATCH] musb: Export musb_root_disconnect for use in modules
From: Greg Kroah-Hartman @ 2016-09-17 10:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9e474920-2ebd-8d38-7c7b-d8e894dc2568@redhat.com>
On Sat, Sep 17, 2016 at 12:12:04PM +0200, Hans de Goede wrote:
> Hi,
>
> On 16-09-16 17:56, Greg Kroah-Hartman wrote:
> > On Fri, Sep 16, 2016 at 04:53:17PM +0100, Mark Brown wrote:
> > > On Fri, Sep 16, 2016 at 05:47:01PM +0200, Greg Kroah-Hartman wrote:
> > > > On Fri, Sep 16, 2016 at 04:59:36PM +0200, Hans de Goede wrote:
> > >
> > > > > +EXPORT_SYMBOL_GPL(musb_root_disconnect);
> > >
> > > > Does this fix a build error somehow? Who reported it?
> > >
> > > Yes, the sunxi driver uses this symbol and the build bots reported it
> > > yesterday.
> >
> > then all of that should have been in this patch :(
> >
> > So much for me trying to be subtle...
>
> Sorry, you're right, I'll add a Fixes tag, and I'll mention
> this fixes a buildbot reported error too.
>
> I'll do a v2 with this right away.
>
> For the next time, is there any official format to
> mention the buildbot report or some such ?
like normal:
"Reported-by: ...."
^ permalink raw reply
* [PATCH] musb: Export musb_root_disconnect for use in modules
From: Hans de Goede @ 2016-09-17 10:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916155608.GA31257@kroah.com>
Hi,
On 16-09-16 17:56, Greg Kroah-Hartman wrote:
> On Fri, Sep 16, 2016 at 04:53:17PM +0100, Mark Brown wrote:
>> On Fri, Sep 16, 2016 at 05:47:01PM +0200, Greg Kroah-Hartman wrote:
>>> On Fri, Sep 16, 2016 at 04:59:36PM +0200, Hans de Goede wrote:
>>
>>>> +EXPORT_SYMBOL_GPL(musb_root_disconnect);
>>
>>> Does this fix a build error somehow? Who reported it?
>>
>> Yes, the sunxi driver uses this symbol and the build bots reported it
>> yesterday.
>
> then all of that should have been in this patch :(
>
> So much for me trying to be subtle...
Sorry, you're right, I'll add a Fixes tag, and I'll mention
this fixes a buildbot reported error too.
I'll do a v2 with this right away.
For the next time, is there any official format to
mention the buildbot report or some such ?
Regards,
Hans
^ permalink raw reply
* [PATCH v2] musb: Export musb_root_disconnect for use in modules
From: Hans de Goede @ 2016-09-17 10:08 UTC (permalink / raw)
To: linux-arm-kernel
Export musb_root_disconnect for use in modules, so that musb glue
code build as module can use it.
This fixes the buildbot errors for -next in arm64-allmodconfig
and arm-allmodconfig.
Fixes: 7cba17ec9adc8cf ("musb: sunxi: Add support for platform_set_mode")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v2:
-Add Fixes tag and buildbot reference to the commit msg
---
drivers/usb/musb/musb_virthub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
index fe08e77..61b5f1c 100644
--- a/drivers/usb/musb/musb_virthub.c
+++ b/drivers/usb/musb/musb_virthub.c
@@ -245,6 +245,7 @@ void musb_root_disconnect(struct musb *musb)
usb_otg_state_string(musb->xceiv->otg->state));
}
}
+EXPORT_SYMBOL_GPL(musb_root_disconnect);
/*---------------------------------------------------------------------*/
--
2.9.3
^ permalink raw reply related
* [PATCH 2/5] mmc: bcm2835-sdhost: Add new driver for the internal SD controller.
From: Ulf Hansson @ 2016-09-17 10:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <877falaq1q.fsf@eliezer.anholt.net>
On 9 September 2016 at 20:25, Eric Anholt <eric@anholt.net> wrote:
> Gerd Hoffmann <kraxel@redhat.com> writes:
>
>> On Mi, 2016-08-31 at 14:58 +0200, Ulf Hansson wrote:
>>> On 22 June 2016 at 13:42, Gerd Hoffmann <kraxel@redhat.com> wrote:
>>> > From: Eric Anholt <eric@anholt.net>
>>> >
>>> > The 2835 has two SD controllers: The Arasan SDHCI controller that we
>>> > currently use, and a custom SD controller. The custom one runs faster
>>> >
>>> > The code was originally written by Phil Elwell in the downstream
>>> > Rasbperry Pi tree, and I did a major cleanup on it (+319, -707 lines
>>> > out of the original 2055) for inclusion.
>>> >
>>> > Signed-off-by: Eric Anholt <eric@anholt.net>
>>>
>>> Apologize for the delay!
>>
>> No problem, I was on summer vacation anyway ...
>>
>>> Could you start by providing some more information about the driver
>>> and the controller in change in the change log please.
>>
>> Eric? I don't know much more than what the commit message above says.
>>
>> Beside the speedup mentioned above driving the sdcard with the custom sd
>> controller allows to use the sdhci (handled by sdhci-iproc) to be used
>> for the wifi on the rpi3.
>
> Maybe just add that we need both controllers in order to do both wifi
> and SD card? I don't know exactly what Ulf wants to see here.
Some toplevel description of the controller. Like what speed modes it
supports, can it do SD/SDIO/eMMC and so forth.
>
>>> > +static void bcm2835_sdhost_set_power(struct bcm2835_host *host, bool on)
>>> > +{
>>> > + bcm2835_sdhost_write(host, on ? 1 : 0, SDVDD);
>>>
>>> What exactly does this power on/off?
>>
>> Dunno. Eric?
>
> Note: I don't know much about SD, so I'm just trying to play oracle for
> you all here.
>
> VDD bit 0 (POWER_ON) starts the power-on setup cycle by the sdhost once
> power is already supplied to the card by some other means. In the
> SDHOST docs they assume you're going to use GPIO to control SD card
> power, but for Raspberry Pi they just have the SD Card's VDD always on.
> It's unclear to me what's controlling power to the Pi3 wifi/BT's SD
> client, but I don't have specs to it.
Very useful information, could we fold something like this in as
comment in the code!?
>
> Note that after you've set POWER_ON to 0, you can also set bit 1
> (CLOCK_OFF) to 1 to turn off the clock to the power-on FSM.
Ditto.
>
>>> > + /* Need to send CMD12 if -
>>> > + * a) open-ended multiblock transfer (no CMD23)
>>> > + * b) error in multiblock transfer
>>> > + */
>>> > + if (host->mrq->stop && (data->error || !host->use_sbc)) {
>>> > + if (bcm2835_sdhost_send_command(host, host->mrq->stop)) {
>>> > + /* No busy, so poll for completion */
>>> > + if (!host->use_busy)
>>>
>>> This looks a bit weird. Can you explain why this is needed?
>>
>> Eric, any clue? Some hardware bug workaround?
>> Have a pointer to hardware specs?
>
> Would no-CMD23 transfers mean that data->blocks was 0 to mean
> indefinite? That's the only mention of CMD12 in the spec -- when you've
> set HBLC to 0, you need to CMD12 or CMD52 when you're done with the
> transfer.
Perhaps you are right, although the comments above is weird.
The driver should check if it's a request with R1B response, as to
find out when to care about busy detection. I have feeling that there
might be some odd things going on in this driver related to this. I
could be wrong through.
I advised Gerd to have a look how MMC_CAP_WAIT_WHILE_BUSY is working,
so perhaps Gerd can figure this out when he understands that part
better!?
>
>>> > +static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>>> > +{
>>>
>>> I don't find any place where you control power to the card here. Don't
>>> you need to do that?
>>
>> Eric?
>
> It looks like the card is always powered. Do you mean something else by
> power (like bringing up the FSM)? Is there something else needed in
> set_ios()?
As you told me above, you are using an external regulator to power the
card (VDD). And it seems like in this particular case this is always
powered on.
Still, my recommendation is to model this as a regulator, as it would
prevent you from hard-coding the so called mmc->ocr_mask_avail.
Instead that mask can be fetched by checking the supported voltage
levels from the regulators.
Please have a look at mmc_regulator_get_supply() and
mmc_regulator_set_ocr(), those helpers are really convenient to use.
You should be using the "vmmc" regulator for this purpose.
Kind regards
Uffe
^ permalink raw reply
* [PATCH v3 1/3] tty: amba-pl011: define flag register bits for ZTE device
From: Russell King - ARM Linux @ 2016-09-17 9:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160917053753.GG7398@tiger>
On Sat, Sep 17, 2016 at 01:37:53PM +0800, Shawn Guo wrote:
> I still think that's a bad idea. ZTE is not the first one making such
> small customization on PL011, and likely won't be the last one. We
> don't want to clone PL011 driver every time there is a such vendor
> hardware coming out, do we? Having PL011 driver being able to handle
> different register layout is very helpful to handle such vendor
> variants, IMHO.
Well, it's turning out that handling ZTE in PL011 is turning into a
bad idea as well - we keep getting these breakages each time we try.
I think ZTE is sufficiently different from PL011 with the different
register layout _and_ the different bits, _and_ the pain that this
is causing, that it should have been a separate driver.
The only way I can think of dealing with the console issue is to
replicate the console code, once for the PL011 variant and then
again for the ZTE variant. We can't _both_ give them the same names
_and_ register them together - we either have to give them different
names, which makes it confusing because one name won't match the
userspace name for the UART, or we need the driver to detect the
port type early. That's made much more difficult because ZTE didn't
bother with the ID registers, unlike every other vendor.
Serial drivers are not that complex anymore, compared to how they
were back before serial_core happened, so having it as a separate
driver isn't that big a deal.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH 3/3] arm: dts: imx6qdl-wandboard-revb: Fix "ERROR: trailing whitespace"
From: Jagan Teki @ 2016-09-17 7:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474098926-5236-1-git-send-email-jagan@amarulasolutions.com>
From: Jagan Teki <jteki@openedev.com>
Fixed error in trailing whitespace in wandboard-rev1 dtsi.
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
index ef7fa62..a320891 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
@@ -28,7 +28,7 @@
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */
- MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */
+ MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */
>;
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/3] arm: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible"
From: Jagan Teki @ 2016-09-17 7:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474098926-5236-1-git-send-email-jagan@amarulasolutions.com>
From: Jagan Teki <jteki@openedev.com>
Fixed code indent tabs in respetcive imx6qdl dtsi files.
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 6 +++---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 4 ++--
arch/arm/boot/dts/imx6qdl.dtsi | 6 +++---
8 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index a7100f9..54aca3a 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -153,9 +153,9 @@
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi3 {
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 8953eba..88e5cb3 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -154,9 +154,9 @@
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 6ac41c7..1753ab7 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -144,9 +144,9 @@
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index 805e236..ee83161 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -291,7 +291,7 @@
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
- };
+ };
pinctrl_wdog: wdoggrp {
fsl,pins = <
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index e0280cac2..e9801a2 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -427,10 +427,10 @@
};
&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3
&pinctrl_usdhc3_cdwp>;
cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- status = "disabled";
+ status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index e000e6f..8006467 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -283,7 +283,7 @@
VD-supply = <®_audio>;
VLS-supply = <®_audio>;
VLC-supply = <®_audio>;
- };
+ };
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 8e9e0d9..55ef535 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -129,8 +129,8 @@
pinctrl-0 = <&pinctrl_gpio_leds>;
red {
- gpios = <&gpio1 2 0>;
- default-state = "on";
+ gpios = <&gpio1 2 0>;
+ default-state = "on";
};
};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index b13b0b2..1bbd36f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -204,9 +204,9 @@
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
<&clks IMX6QDL_CLK_LVDS1_GATE>,
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
--
2.7.4
^ permalink raw reply related
* [PATCH 1/3] arm: dts: imx6qdl: Fix "WARNING: please, no space before tabs"
From: Jagan Teki @ 2016-09-17 7:55 UTC (permalink / raw)
To: linux-arm-kernel
From: Jagan Teki <jteki@openedev.com>
Fixed no space before tabs warnings in respetcive imx6qdl dtsi files.
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
arch/arm/boot/dts/imx6qdl-apf6dev.dtsi | 14 +++++++-------
arch/arm/boot/dts/imx6qdl-tx6.dtsi | 32 ++++++++++++++++----------------
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 4 ++--
3 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
index edbce22..5e7792d 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
@@ -347,13 +347,13 @@
fsl,pins = <
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index ac9529f..2bf2e62 100644
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -429,8 +429,8 @@
pinctrl_edt_ft5x06: edt-ft5x06grp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
+ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
>;
};
@@ -481,21 +481,21 @@
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 2b9c2be..82dc5744 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -129,8 +129,8 @@
pinctrl_i2c1: i2c1grp {
fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
--
2.7.4
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