* [PATCH] arm: dts: fix rk3066a based boards vdd_log voltage initialization
From: Andy Yan @ 2016-09-19 8:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474274639-27768-1-git-send-email-andy.yan@rock-chips.com>
The current rk3066a based boards(Rayeager, Bqcurie2, Marsboard) use
pwm modulate vdd_logic voltage, but the pwm is default disabled and
the pwm pin acts as a gpio before pwm regulator probed, so the pwm
regulator driver will get a zero dutycycle at probe time, so change
the initial dutycycle to zero to match pwm_regulator_init_state check.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/boot/dts/rk3066a-bqcurie2.dts | 2 +-
arch/arm/boot/dts/rk3066a-marsboard.dts | 2 +-
arch/arm/boot/dts/rk3066a-rayeager.dts | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index bc674ee..618450d 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -61,7 +61,7 @@
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
- voltage-table = <1000000 100>,
+ voltage-table = <1000000 0>,
<1200000 42>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
index a2b763e..ddc680b 100644
--- a/arch/arm/boot/dts/rk3066a-marsboard.dts
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -59,7 +59,7 @@
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
- voltage-table = <1000000 100>,
+ voltage-table = <1000000 0>,
<1200000 42>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index 2536b3a..30aee99 100644
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -84,7 +84,7 @@
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
- voltage-table = <1000000 100>,
+ voltage-table = <1000000 0>,
<1200000 42>;
status = "okay";
};
--
2.7.4
^ permalink raw reply related
* [PATCH 0/1] fix rk3066a based boards boot issue on linux-4.8
From: Andy Yan @ 2016-09-19 8:43 UTC (permalink / raw)
To: linux-arm-kernel
Hi, heiko:
I found my Rayeager board couldn't boot up on linux 4.8. After some
dig, I found the pwm-regulator for vdd_log register failed and found
some change in Boris's patch: commit 87248991a1de(regulator: pwm: Properly
initialize the ->state field).
I send this patch to make the pwm-regulator can register success on
this change.
Andy Yan (1):
arm: dts: fix rk3066a based boards vdd_log voltage initialization
arch/arm/boot/dts/rk3066a-bqcurie2.dts | 2 +-
arch/arm/boot/dts/rk3066a-marsboard.dts | 2 +-
arch/arm/boot/dts/rk3066a-rayeager.dts | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v4 7/7] ARM: dts: bcm283x: drop alt3 from &gpio
From: Gerd Hoffmann @ 2016-09-19 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474274603-24215-1-git-send-email-kraxel@redhat.com>
As the alt3 group has no pins left drop it from &gpio.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-a.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-b.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-zero.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi.dtsi | 5 -----
arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 2 +-
8 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
index f7f9db3..21507c9 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
@@ -22,7 +22,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts
index 8be102f..5afba09 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts
@@ -15,7 +15,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
i2s_alt2: i2s_alt2 {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
index 35cde65..38f66aa 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -23,7 +23,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
index 84df85e..75e045a 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
@@ -16,7 +16,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */
i2s_alt2: i2s_alt2 {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 8e626a8..76a254b 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -16,7 +16,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0>;
};
&hdmi {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
index 60e359f..7c1c180 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
@@ -26,7 +26,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 3f0ce61..a46fa41 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -41,11 +41,6 @@
brcm,pins = <4 5 7 8 9 10 11>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
-
- alt3: alt3 {
- brcm,pins = <>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
};
&i2c0 {
diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
index 39dccf6..bf19e8c 100644
--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
@@ -27,7 +27,7 @@
};
&gpio {
- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+ pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
--
1.8.3.1
^ permalink raw reply related
* [PATCH v4 6/7] ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio
From: Gerd Hoffmann @ 2016-09-19 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474274603-24215-1-git-send-email-kraxel@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 8688204..3f0ce61 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -43,7 +43,7 @@
};
alt3: alt3 {
- brcm,pins = <48 49 50 51 52 53>;
+ brcm,pins = <>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
};
@@ -67,6 +67,8 @@
};
&sdhci {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio48>;
status = "okay";
bus-width = <4>;
};
--
1.8.3.1
^ permalink raw reply related
* [PATCH v4 5/7] ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio
From: Gerd Hoffmann @ 2016-09-19 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474274603-24215-1-git-send-email-kraxel@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index b936978..8688204 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -38,7 +38,7 @@
};
alt0: alt0 {
- brcm,pins = <2 3 4 5 7 8 9 10 11>;
+ brcm,pins = <4 5 7 8 9 10 11>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
@@ -56,6 +56,8 @@
};
&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_gpio2>;
status = "okay";
clock-frequency = <100000>;
};
--
1.8.3.1
^ permalink raw reply related
* [PATCH v4 4/7] ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio
From: Gerd Hoffmann @ 2016-09-19 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474274603-24215-1-git-send-email-kraxel@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index ff62236..b936978 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -38,7 +38,7 @@
};
alt0: alt0 {
- brcm,pins = <0 1 2 3 4 5 7 8 9 10 11>;
+ brcm,pins = <2 3 4 5 7 8 9 10 11>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
@@ -49,6 +49,8 @@
};
&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_gpio0>;
status = "okay";
clock-frequency = <100000>;
};
--
1.8.3.1
^ permalink raw reply related
* [PATCH v4 3/7] ARM: dts: bcm283x: add pinctrl group to &pwm, drop pins from &gpio
From: Gerd Hoffmann @ 2016-09-19 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474274603-24215-1-git-send-email-kraxel@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 88bcd0c..ff62236 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -38,7 +38,7 @@
};
alt0: alt0 {
- brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 40 45>;
+ brcm,pins = <0 1 2 3 4 5 7 8 9 10 11>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
@@ -68,6 +68,8 @@
};
&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
status = "okay";
};
--
1.8.3.1
^ permalink raw reply related
* [PATCH v4 2/7] ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.
From: Gerd Hoffmann @ 2016-09-19 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474274603-24215-1-git-send-email-kraxel@redhat.com>
From: Eric Anholt <eric@anholt.net>
The BCM2835-ARM-Peripherals.pdf documentation specifies what the
function selects do for the pins, and there are a bunch of obvious
groupings to be made. With these created, we'll be able to replace
bcm2835-rpi.dtsi's main "set all of these pins to alt0" with
references to specific groups we want enabled.
Also add pinctrl groups for emmc and sdhost.
Based on patches by Eric Anholt <eric@anholt.net>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
arch/arm/boot/dts/bcm283x.dtsi | 203 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 203 insertions(+)
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 4d9f3ab..68d559e 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -131,6 +131,209 @@
interrupt-controller;
#interrupt-cells = <2>;
+
+ /* Defines pin muxing groups according to
+ * BCM2835-ARM-Peripherals.pdf page 102.
+ *
+ * While each pin can have its mux selected
+ * for various functions individually, some
+ * groups only make sense to switch to a
+ * particular function together.
+ */
+ dpi_gpio0: dpi_gpio0 {
+ brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
+ 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+ emmc_gpio22: emmc_gpio22 {
+ brcm,pins = <22 23 24 25 26 27>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+ emmc_gpio34: emmc_gpio34 {
+ brcm,pins = <34 35 36 37 38 39>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ brcm,pull = <BCM2835_PUD_OFF
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP
+ BCM2835_PUD_UP>;
+ };
+ emmc_gpio48: emmc_gpio48 {
+ brcm,pins = <48 49 50 51 52 53>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ gpclk0_gpio4: gpclk0_gpio4 {
+ brcm,pins = <4>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk1_gpio5: gpclk1_gpio5 {
+ brcm,pins = <5>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk1_gpio42: gpclk1_gpio42 {
+ brcm,pins = <42>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk1_gpio44: gpclk1_gpio44 {
+ brcm,pins = <44>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk2_gpio6: gpclk2_gpio6 {
+ brcm,pins = <6>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ gpclk2_gpio43: gpclk2_gpio43 {
+ brcm,pins = <43>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+
+ i2c0_gpio0: i2c0_gpio0 {
+ brcm,pins = <0 1>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ i2c0_gpio32: i2c0_gpio32 {
+ brcm,pins = <32 34>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ i2c0_gpio44: i2c0_gpio44 {
+ brcm,pins = <44 45>;
+ brcm,function = <BCM2835_FSEL_ALT1>;
+ };
+ i2c1_gpio2: i2c1_gpio2 {
+ brcm,pins = <2 3>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ i2c1_gpio44: i2c1_gpio44 {
+ brcm,pins = <44 45>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+ i2c_slave_gpio18: i2c_slave_gpio18 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ jtag_gpio4: jtag_gpio4 {
+ brcm,pins = <4 5 6 12 13>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+ jtag_gpio22: jtag_gpio22 {
+ brcm,pins = <22 23 24 25 26 27>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+
+ pcm_gpio18: pcm_gpio18 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pcm_gpio28: pcm_gpio28 {
+ brcm,pins = <28 29 30 31>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+
+ pwm0_gpio12: pwm0_gpio12 {
+ brcm,pins = <12>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm0_gpio18: pwm0_gpio18 {
+ brcm,pins = <18>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm0_gpio40: pwm0_gpio40 {
+ brcm,pins = <40>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio13: pwm1_gpio13 {
+ brcm,pins = <13>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio19: pwm1_gpio19 {
+ brcm,pins = <19>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm1_gpio41: pwm1_gpio41 {
+ brcm,pins = <41>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio45: pwm1_gpio45 {
+ brcm,pins = <45>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+
+ sdhost_gpio48: sdhost_gpio48 {
+ brcm,pins = <48 49 50 51 52 53>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+
+ spi0_gpio7: spi0_gpio7 {
+ brcm,pins = <7 8 9 10 11>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ spi0_gpio35: spi0_gpio35 {
+ brcm,pins = <35 36 37 38 39>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ spi1_gpio16: spi1_gpio16 {
+ brcm,pins = <16 17 18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+ spi2_gpio40: spi2_gpio40 {
+ brcm,pins = <40 41 42 43 44 45>;
+ brcm,function = <BCM2835_FSEL_ALT4>;
+ };
+
+ uart0_gpio14: uart0_gpio14 {
+ brcm,pins = <14 15>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ /* Separate from the uart0_gpio14 group
+ * because it conflicts with spi1_gpio16, and
+ * people often run uart0 on the two pins
+ * without flow contrl.
+ */
+ uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
+ brcm,pins = <16 17>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+ uart0_gpio30: uart0_gpio30 {
+ brcm,pins = <30 31>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+ uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
+ brcm,pins = <32 33>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ uart1_gpio14: uart1_gpio14 {
+ brcm,pins = <14 15>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
+ brcm,pins = <16 17>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_gpio32: uart1_gpio32 {
+ brcm,pins = <32 33>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
+ brcm,pins = <30 31>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_gpio36: uart1_gpio36 {
+ brcm,pins = <36 37 38 39>;
+ brcm,function = <BCM2835_FSEL_ALT2>;
+ };
+ uart1_gpio40: uart1_gpio40 {
+ brcm,pins = <40 41>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
+ brcm,pins = <42 43>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
};
uart0: serial at 7e201000 {
--
1.8.3.1
^ permalink raw reply related
* [PATCH v4 1/7] pinctrl: bcm2835: add pull defines to dt bindings
From: Gerd Hoffmann @ 2016-09-19 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474274603-24215-1-git-send-email-kraxel@redhat.com>
Also delete (unused) private enum from driver.
The pull defines can be used instead if needed.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 6 ------
include/dt-bindings/pinctrl/bcm2835.h | 5 +++++
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index fa77165..4cf612b 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -76,12 +76,6 @@ enum bcm2835_pinconf_param {
BCM2835_PINCONF_PARAM_PULL,
};
-enum bcm2835_pinconf_pull {
- BCM2835_PINCONFIG_PULL_NONE,
- BCM2835_PINCONFIG_PULL_DOWN,
- BCM2835_PINCONFIG_PULL_UP,
-};
-
#define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
#define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
#define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
diff --git a/include/dt-bindings/pinctrl/bcm2835.h b/include/dt-bindings/pinctrl/bcm2835.h
index 6f0bc37..e4e4fdf 100644
--- a/include/dt-bindings/pinctrl/bcm2835.h
+++ b/include/dt-bindings/pinctrl/bcm2835.h
@@ -24,4 +24,9 @@
#define BCM2835_FSEL_ALT2 6
#define BCM2835_FSEL_ALT3 7
+/* brcm,pull property */
+#define BCM2835_PUD_OFF 0
+#define BCM2835_PUD_DOWN 1
+#define BCM2835_PUD_UP 2
+
#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */
--
1.8.3.1
^ permalink raw reply related
* [PATCH v4 0/7] ARM: dts: bcm283x: add and use pinctrl groups
From: Gerd Hoffmann @ 2016-09-19 8:43 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
New in v4: Patch #6 has been splitted into two: Patch 6 just moves
pinctrl from &gpio to &sdhci. Removing the empty now alt3 group
-- including all references as pointed out by Stefan Wahren in review --
is done by the new patch 7. Patches 1-5 are unchanged.
cheers,
Gerd
Eric Anholt (1):
ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.
Gerd Hoffmann (6):
pinctrl: bcm2835: add pull defines to dt bindings
ARM: dts: bcm283x: add pinctrl group to &pwm, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio
ARM: dts: bcm283x: drop alt3 from &gpio
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-a.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-b.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi-zero.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi.dtsi | 15 ++-
arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 2 +-
arch/arm/boot/dts/bcm283x.dtsi | 203 +++++++++++++++++++++++++++++++
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 6 -
include/dt-bindings/pinctrl/bcm2835.h | 5 +
11 files changed, 224 insertions(+), 19 deletions(-)
--
1.8.3.1
^ permalink raw reply
* [PATCH RFC 8/8] ARM: dts: sk-rzg1m: initial device tree
From: Geert Uytterhoeven @ 2016-09-19 8:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2097453.1xPZsJcFmC@wasted.cogentembedded.com>
On Fri, Sep 16, 2016 at 3:38 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the initial device tree for the R8A7743 SoC based SK-RZG1M board.
> The board has one debug serial port (SCIF0); include support for it, so
> that the serial console can work.
>
> Based on the original (and large) patch by Dmitry Shifrin
> <dmitry.shifrin@cogentembedded.com>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- /dev/null
> +++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
> @@ -0,0 +1,44 @@
> + compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
To be documented in Documentation/devicetree/bindings/arm/shmobile.txt
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] ASoC: samsung: make audio interface/controller explicitly
From: Mark Brown @ 2016-09-19 8:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474207751-9804-2-git-send-email-ayaka@soulik.info>
On Sun, Sep 18, 2016 at 10:09:11PM +0800, Randy Li wrote:
> It is simple sound card time, we could assign different codec
> to a interface without making a specific driver for it.
> config SND_SAMSUNG_AC97
> - tristate
> + tristate "Samsung AC97 controller support"
> select SND_SOC_AC97_BUS
Are you *sure* simple-card works for AC'97?
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^ permalink raw reply
* [PATCH] make samsung interface entries explicitly
From: Mark Brown @ 2016-09-19 8:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474207751-9804-1-git-send-email-ayaka@soulik.info>
On Sun, Sep 18, 2016 at 10:09:10PM +0800, Randy Li wrote:
> I found those modules should be selected directly, as I
> only use the simple sound card.
Please don't send cover letters for single patches, if there is anything
that needs saying put it in the changelog of the patch or after the ---
if it's administrative stuff. This reduces mail volume and ensures that
any important information is recorded in the changelog rather than being
lost.
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^ permalink raw reply
* [PATCH RFC 7/8] ARM: dts: r8a7743: add [H]SCIF support
From: Geert Uytterhoeven @ 2016-09-19 8:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2338956.oSVFAsJyhK@wasted.cogentembedded.com>
Hi Sergei,
On Fri, Sep 16, 2016 at 3:37 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe [H]SCIFs in the R8A7743 device tree.
>
> Based on the original (and large) patch by Dmitry Shifrin
> <dmitry.shifrin@cogentembedded.com>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
> +++ renesas/arch/arm/boot/dts/r8a7743.dtsi
> @@ -154,6 +154,268 @@
> dma-channels = <15>;
> };
>
> + scifa0: serial at e6c40000 {
> + compatible = "renesas,scifa-r8a7743",
To be documented...
> + "renesas,rcar-gen2-scifa", "renesas,scifa";
> + reg = <0 0xe6c40000 0 64>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&mstp2_clks R8A7743_CLK_SCIFA0>;
> + clock-names = "fck";
> + dmas = <&dmac0 0x21>, <&dmac0 0x22>,
> + <&dmac1 0x21>, <&dmac1 0x22>;
> + dma-names = "tx", "rx", "tx", "rx";
> + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
> + status = "disabled";
> + };
[...]
> + scifb0: serial at e6c20000 {
> + compatible = "renesas,scifb-r8a7743",
To be documented...
> + "renesas,rcar-gen2-scifb", "renesas,scifb";
> + reg = <0 0xe6c20000 0 64>;
This does not cover the whole register block (aha, also on existing Gen2).
"reg = <0 0xe6c20000 0 256>;"?
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&mstp2_clks R8A7743_CLK_SCIFB0>;
> + clock-names = "fck";
> + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
> + <&dmac1 0x3d>, <&dmac1 0x3e>;
> + dma-names = "tx", "rx", "tx", "rx";
> + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
> + status = "disabled";
> + };
[...]
> + scif0: serial at e6e60000 {
> + compatible = "renesas,scif-r8a7743",
To be documented...
> + "renesas,rcar-gen2-scif", "renesas,scif";
> + reg = <0 0xe6e60000 0 64>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&mstp7_clks R8A7743_CLK_SCIF0>, <&zs_clk>,
> + <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
> + <&dmac1 0x29>, <&dmac1 0x2a>;
> + dma-names = "tx", "rx", "tx", "rx";
> + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
> + status = "disabled";
> + };
> +
> + scif1: serial at e6e68000 {
> + compatible = "renesas,scif-r8a7743",
> + "renesas,rcar-gen2-scif", "renesas,scif";
> + reg = <0 0xe6e68000 0 64>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&mstp7_clks R8A7743_CLK_SCIF1>, <&zs_clk>,
> + <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
> + <&dmac1 0x2d>, <&dmac1 0x2e>;
> + dma-names = "tx", "rx", "tx", "rx";
> + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
> + status = "disabled";
> + };
[...]
> + hscif0: serial at e62c0000 {
> + compatible = "renesas,hscif-r8a7743",
To be documented...
> + "renesas,rcar-gen2-hscif", "renesas,hscif";
> + reg = <0 0xe62c0000 0 96>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&mstp7_clks R8A7743_CLK_HSCIF0>, <&zs_clk>,
> + <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
> + <&dmac1 0x39>, <&dmac1 0x3a>;
> + dma-names = "tx", "rx", "tx", "rx";
> + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
> + status = "disabled";
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] dmaengine: sun6i: Add support for Allwinner A83T (sun8i) variant
From: Maxime Ripard @ 2016-09-19 8:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160918080103.ADDBE110E@mail.free-electrons.com>
On Sun, Sep 18, 2016 at 09:59:50AM +0200, Jean-Francois Moine wrote:
> The A83T SoC has the same dma engine as the A31 (sun6i), with a reduced
> amount of endpoints and physical channels.
>
> Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH] pinctrl: nomadik: don't default-flag IRQs as falling
From: Linus Walleij @ 2016-09-19 8:22 UTC (permalink / raw)
To: linux-arm-kernel
There is no point in adding any default trigger for these
GPIO interrupts: the device tree should contain all trigger
information and the platforms using the driver boots
exclusively from device tree.
Also the boot log is nagging me to fix this:
[ 0.771057] ------------[ cut here ]------------
[ 0.775695] WARNING: CPU: 0 PID: 1 at
../drivers/gpio/gpiolib.c:1622 _gpiochip_irqchip_add+0x138/0x160
[ 0.785034] /soc/gpio at 8012e000: Ignoring 2 default trigger
(...)
[ 0.942962] gpio 8012e000.gpio: at address e08f8000
(etc ad nauseam)
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/nomadik/pinctrl-nomadik.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
index 205fb399268a..d318ca055489 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
@@ -1177,7 +1177,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
irqchip,
0,
handle_edge_irq,
- IRQ_TYPE_EDGE_FALLING);
+ IRQ_TYPE_NONE);
if (ret) {
dev_err(&dev->dev, "could not add irqchip\n");
gpiochip_remove(&nmk_chip->chip);
--
2.7.4
^ permalink raw reply related
* [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support
From: Geert Uytterhoeven @ 2016-09-19 8:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1815255.1arMxK7TDL@wasted.cogentembedded.com>
On Fri, Sep 16, 2016 at 3:36 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
> +++ renesas/arch/arm/boot/dts/r8a7743.dtsi
> @@ -90,6 +90,70 @@
> #power-domain-cells = <1>;
> };
>
> + dmac0: dma-controller at e6700000 {
> + compatible = "renesas,dmac-r8a7743",
To be documented.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v4 2/2] ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board
From: Maxime Ripard @ 2016-09-19 8:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916151642.27907-2-icenowy@aosc.xyz>
On Fri, Sep 16, 2016 at 11:16:42PM +0800, Icenowy Zheng wrote:
> UART1 is connected to the bluetooth part of RTL8723BS WiFi/BT combo card
> on iNet D978 Rev2 board.
>
> Enable the UART1 to make it possible to use the modified hciattach by
> Realtek to drive the BT part of RTL8723BS.
>
> On the board no r_uart pins are found now (the onboard RX/TX pins are
> wired to PF2/PF4, which is muxed with mmc0), so also disabled it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support
From: Geert Uytterhoeven @ 2016-09-19 8:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1815255.1arMxK7TDL@wasted.cogentembedded.com>
On Fri, Sep 16, 2016 at 3:36 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe SYS-DMAC0/1 in the R8A7743 device tree.
>
> Based on the original (and large) patch by Dmitry Shifrin
> <dmitry.shifrin@cogentembedded.com>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
(but the clocks properties will have to be changed due to CPG/MSSR)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v4 1/2] ARM: dts: sun8i: add pinmux for UART1 at PG
From: Maxime Ripard @ 2016-09-19 8:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916151642.27907-1-icenowy@aosc.xyz>
Hi,
On Fri, Sep 16, 2016 at 11:16:41PM +0800, Icenowy Zheng wrote:
> The UART1 at PG (PG6, PG7, PG8, PG9) is, in the Allwinner's reference
> tablet design of A23/33, used to connect to UART Bluetooth cards.
>
> Add the pinmux for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> This patch is splited in v4.
>
> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> index 7e05e09..c340885 100644
> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> @@ -361,6 +361,20 @@
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> };
>
> + uart1_pins_a: uart1 at 0 {
> + allwinner,pins = "PG6", "PG7";
> + allwinner,function = "uart1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart1_pins_cts_rts_a: uart1-cts-rts at 0 {
> + allwinner,pins = "PG8", "PG9";
> + allwinner,function = "uart1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
It turns out the allwinner,drive and allwinner,pull properties are
optionnal. I removed them, and applied that patch.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v6 0/8] power: add power sequence library
From: Vaibhav Hiremath @ 2016-09-19 8:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160919074637.GA10289@b29397-desktop>
On Monday 19 September 2016 01:16 PM, Peter Chen wrote:
> On Mon, Sep 19, 2016 at 01:09:10PM +0530, Vaibhav Hiremath wrote:
>>
>> On Friday 09 September 2016 02:17 PM, Ulf Hansson wrote:
>>> [...]
>>>
>>>>>>> We had an agreement that keep mmc's pwrseq framework unchanging.
>>>>>>> Unless Ulf and rob both agree to change.
>>>>>> Why 2 separate approach for same problem ?
>>>>>> And I see this as possible duplication of code/functionality :)
>>>>> How the new kernel compatibles old dts? If we do not need to
>>>>> consider this problem, the mmc can try to use power sequence library
>>>>> too in future.
>>>> I think we should attempt to get both MMC and USB power seq
>>>> come on one agreement, so that it can be reused.
>>> That would be nice. Although, to do that you would have to allow some
>>> DT bindings to be deprecated in the new generic power seq bindings, as
>>> otherwise you would break existing DTBs.
>>>
>>> I guess that is what Rob was objecting to!?
>> yeah, thats right.
>>
>> So lets adopt similar implementation for USB as well instead of
>> library, but keeping MMC untouched as of now.
>>
>> What I am trying to propose here is,
>>
>> Lets have power-sequence framework (similar to V1 of this series),
>> with,
>>
>> pwrseq: Core framework for power sequence.
>> pwrseq_generic/simple: for all generic control, like reset and clock
>> pwrseq_emmc: probably duplication of existing code - the idea
>> here is, all future code should be using this new
>> binding, so that we can deprecate the
>> drivers/mmc/core/pwrseq
>> pwrseq_arche: The usecase which I am dealing with today, which is more
>> complex in nature.
>>
>> Then the respective drivers can add their drivers (if needed) based on
>> complexity.
>>
>> comments ??
> The key point here is DT maintainer (Rob) doesn't agree with adding new node
> for power sequence at dts.
>
Hmmm.
We haven't heard from Rob lately especially after introduction of complex
usecases. I hope he would revisit on above proposal.
Thanks,
Vaibhav
^ permalink raw reply
* [PATCH RFC 5/8] ARM: dts: r8a7743: initial SoC device tree
From: Geert Uytterhoeven @ 2016-09-19 8:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1679762.ECpvSkQAyM@wasted.cogentembedded.com>
Hi Sergei,
On Fri, Sep 16, 2016 at 3:35 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> The initial R8A7743 SoC device tree including CPU cores, GIC, timer, SYSC,
> and the required clock descriptions.
>
> Based on the original (and large) patch by Dmitry Shifrin
> <dmitry.shifrin@cogentembedded.com>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> --- /dev/null/
> +++ renesas/arch/arm/boot/dts/r8a7743.dtsi
> @@ -0,0 +1,210 @@
> +/ {
> + soc {
=
> + /* Special CPG clocks */
> + cpg_clocks: cpg_clocks at e6150000 {
> + compatible = "renesas,r8a7743-cpg-clocks",
> + "renesas,rcar-gen2-cpg-clocks";
For a new SoC family, I would strongly suggest using a renesas,cpg-mssr
based binding instead:
- No more mstp*_clocks nodes with array triplets to keep in sync,
- Support for MSSR reset can be added later,
- No need to add all those fixed-factor clocks to DT,
- Less DT churn when adding support for new devices.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] ARM: dts: Add power button support for igepv5
From: Pau Pajuel @ 2016-09-19 8:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <31409234-3185-5348-2d37-effb7769c92a@osg.samsung.com>
Hello Tony,
2016-09-14 3:26 GMT+02:00 Javier Martinez Canillas <javier@osg.samsung.com>:
> Hello Tony,
>
> On 09/09/2016 05:07 PM, Tony Lindgren wrote:
>> Add power button support for igepv5.
>>
>> Cc: Agust? Fontquerni i Gorchs <afontquerni@iseebcn.com>
>> Cc: Enric Balletbo Serra <eballetbo@gmail.com>
>> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
>> Cc: Pau Pajuel <ppajuel@gmail.com>
>> Signed-off-by: Tony Lindgren <tony@atomide.com>
>> ---
>
> I don't have a schematics for this board, but the patch looks good to me.
Patch has an errata. Power button is GPIO_ACTIVE_LOW instead GPIO_ACTIVE_HIGH.
>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
>
> Best regards,
> --
> Javier Martinez Canillas
> Open Source Group
> Samsung Research America
Best regards
^ permalink raw reply
* [PATCH soc/next] ARM: BCM53573: Add custom init_time with arch timer workaroud
From: Marc Zyngier @ 2016-09-19 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160918193238.21339-1-zajec5@gmail.com>
Rafa?,
On 18/09/16 20:32, Rafa? Mi?ecki wrote:
> From: Rafa? Mi?ecki <rafal@milecki.pl>
>
> BCM53573 uses ARM architected timer but CFE (bootloader) is bugged and
> doesn't setup hardware properly. As the architecture requirement clock
> should be enabled and CNTFRQ should be set before starting Linux.
>
> Unfortunately it's impossible to have CFE fixed and updated on all
> released devices. There are plenty of them on the market and updating
> bootloader isn't a standard procedure. We also don't have CFE sources
> for BCM53573 devices and no replacement bootloader.
>
> We can't modify arch timer to simply accept specifying clock. Quoting
> Mark: "The clock-frequency property is at best a dodgy workaround, and
> this is even worse.". Marc also noted that other subsystems may rely on
> CNTFRQ as well.
>
> The only sane workaround seems to be fixing this CFE bug in BCM53573
> arch code. It doesn't require modifying other drivers and should allow
> all subsystems to work correctly.
>
> Signed-off-by: Rafa? Mi?ecki <rafal@milecki.pl>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> ---
> MAINTAINERS | 1 +
> arch/arm/mach-bcm/Makefile | 3 +++
> arch/arm/mach-bcm/bcm_53573.c | 62 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 66 insertions(+)
> create mode 100644 arch/arm/mach-bcm/bcm_53573.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a91bca7..0bb0c4b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2568,6 +2568,7 @@ BROADCOM BCM53573 ARM ARCHITECTURE
> M: Rafa? Mi?ecki <rafal@milecki.pl>
> L: linux-arm-kernel at lists.infradead.org
> S: Maintained
> +F: arch/arm/mach-bcm/bcm_53573.c
> F: arch/arm/boot/dts/bcm53573*
> F: arch/arm/boot/dts/bcm47189*
>
> diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
> index 980f585..0d64778 100644
> --- a/arch/arm/mach-bcm/Makefile
> +++ b/arch/arm/mach-bcm/Makefile
> @@ -50,6 +50,9 @@ ifeq ($(CONFIG_ARCH_BCM_5301X),y)
> obj-$(CONFIG_SMP) += platsmp.o
> endif
>
> +# BCM53573
> +obj-$(CONFIG_ARCH_BCM_53573) += bcm_53573.o
> +
> # BCM63XXx
> ifeq ($(CONFIG_ARCH_BCM_63XX),y)
> obj-y += bcm63xx.o
> diff --git a/arch/arm/mach-bcm/bcm_53573.c b/arch/arm/mach-bcm/bcm_53573.c
> new file mode 100644
> index 0000000..540a247
> --- /dev/null
> +++ b/arch/arm/mach-bcm/bcm_53573.c
> @@ -0,0 +1,62 @@
> +/*
> + * Copyright (C) 2016 Rafa? Mi?ecki <rafal@milecki.pl>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <asm/mach/arch.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clocksource.h>
> +#include <linux/clk.h>
> +
> +static inline void arch_timer_set_cntfrq(u32 cntfrq)
> +{
> + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (cntfrq));
> +}
This is wrong for a number of reasons: This register only writeable from
the secure side. Boot this kernel in non-secure mode, and the kernel
will explode. Also, you're only setting it from the boot CPU, while it
should be set on all of them.
So in effect, this is not any better than advertising the timer
frequency in the device tree.
> +
> +/*
> + * CFE bootloader doesn't meet arch requirements. It doesn't enable ILP clock
> + * which is required for arch timer and doesn't set CNTFRQ.
> + * Fix is up here.
> + */
> +static void __init bcm_53573_setup_arch_timer(void)
> +{
> + struct of_phandle_args out_args = { };
> + struct clk *clk;
> +
> + out_args.np = of_find_compatible_node(NULL, NULL, "brcm,bcm53573-ilp");
> + if (!out_args.np) {
> + pr_warn("Failed to find ILP node\n");
> + return;
> + }
> +
> + clk = of_clk_get_from_provider(&out_args);
> + if (!IS_ERR(clk)) {
> + if (!clk_prepare_enable(clk))
> + arch_timer_set_cntfrq(clk_get_rate(clk));
> + }
> +
> + of_node_put(out_args.np);
> +}
> +
> +/* A copy of ARM's time_init with workaround inserted */
> +static void __init bcm_53573_init_time(void)
> +{
> +#ifdef CONFIG_COMMON_CLK
> + of_clk_init(NULL);
> +#endif
> + bcm_53573_setup_arch_timer();
> + clocksource_probe();
> +}
> +
> +static const char *const bcm_53573_dt_compat[] __initconst = {
> + "brcm,bcm53573",
> + NULL,
> +};
> +
> +DT_MACHINE_START(BCM5301X, "BCM53573")
> + .init_time = bcm_53573_init_time,
> + .dt_compat = bcm_53573_dt_compat,
> +MACHINE_END
>
My advise would be to move this to a shim outside of the kernel, which
could configure the clocks and set CNTFRQ on all CPUs. As it stands,
this patch doesn't really improve the situation.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v2 1/3] ipmi: add an Aspeed BT IPMI BMC driver
From: Cédric Le Goater @ 2016-09-19 8:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <08e9b30f-6c35-8418-a8b0-0b63639dd36d@acm.org>
On 09/16/2016 09:41 PM, Corey Minyard wrote:
> On 09/16/2016 05:39 AM, C?dric Le Goater wrote:
>> From: Alistair Popple <alistair@popple.id.au>
>>
>> This patch adds a simple device driver to expose the iBT interface on
>> Aspeed SOCs (AST2400 and AST2500) as a character device. Such SOCs are
>> commonly used as BMCs (BaseBoard Management Controllers) and this
>> driver implements the BMC side of the BT interface.
>>
>> The BT (Block Transfer) interface is used to perform in-band IPMI
>> communication between a host and its BMC. Entire messages are buffered
>> before sending a notification to the other end, host or BMC, that
>> there is data to be read. Usually, the host emits requests and the BMC
>> responses but the specification provides a mean for the BMC to send
>> SMS Attention (BMC-to-Host attention or System Management Software
>> attention) messages.
>>
>> For this purpose, the driver introduces a specific ioctl on the
>> device: 'BT_BMC_IOCTL_SMS_ATN' that can be used by the system running
>> on the BMC to signal the host of such an event.
>>
>> The device name defaults to '/dev/ipmi-bt-host'
>
> Others have reviewed this for style and such, and I have looked
> at it from a protocol point of view. it looks to be sound for the
> most part. I have some higher level concerns:
>
> There appears to be no handling for multiple simultaneous users.
> This interface can only be used by one task at a time, so you should
> probably only allow one opener. Well, I guess the BMC could be split
> into a reader and a writer task, so I'm not really sure about that, but
> I would think in most situations having more than one opener is a
> bug. You do call clr_b_busy() on open, for instance, which might be
> an issue for multiple openers. Maybe a module parameter for
> maximum number of openers? Just want to make sure this was
> thought about, at least.
yes but not implemented ... The open_count in the bt_bmc structure
is unused. In v3, I will replace it with a global atomic_t tracked
in the open and release operations.
> There is also no mutex protecting reading or writing. If multiple
> threads call read or write at the same time, it probably wouldn't
> work correctly. I think you need a read and a write mutex on the
> interface to protect against this.
yes. I will add a mutex also in v3.
> The spec says:
>
> The BMC must not return a given response once the corresponding
> Request-to-Response interval has passed. The BMC can ensure this
> by maintaining its own internal list of outstanding requests through
> the interface. The BMC could age and expire the entries in the list
> by expiring the entries at an interval that is somewhat shorter than
> the specified Request-to-Response interval....
This is clearly not handled in the driver.
For this purpose, we could maintain a request expiry list using the seq
field of the BT message. Update the list in the read and write operations
and arm a timer to garbage collect any left overs. As for the errno in
the write when a response had timeout'ed, may be ETIMEDOUT ?
For configuration of the maximum response time, a sysfs file would do
I think.
Do you want that in v3 also ? I have some experimental patches for it,
that I can send as follow ups.
Thanks,
C.
> On the write side, though, there doesn't seem to be a way to handle a
> situation where the host side doesn't respond for a while and the
> pending message would need to be discarded.
>
> The spec doesn't mention much about error recovery on this interface,
> but the way this is written should be fine, I think.
>
> I'm copying Rocky Craig, who wrote the host side driver for Linux, in
> case he wants to comment on this.
>
> This is easy to read and understand, so I think v3 should be good.
>
> Thanks,
>
> -corey
>
>> Signed-off-by: Alistair Popple <alistair@popple.id.au>
>> Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>> [clg: - checkpatch fixes
>> - added a devicetree binding documentation
>> - replace 'bt_host' by 'bt_bmc' to reflect that the driver is
>> the BMC side of the IPMI BT interface
>> - renamed the device to 'ipmi-bt-host'
>> - introduced a temporary buffer to copy_{to,from}_user
>> - used platform_get_irq()
>> - moved the driver under drivers/char/ipmi/ but kept it as a misc
>> device
>> - changed the compatible cell to "aspeed,ast2400-bt-bmc"
>> ]
>> Signed-off-by: C?dric Le Goater <clg@kaod.org>
>> ---
>>
>> Changes since v1:
>>
>> - replace 'bt_host' by 'bt_bmc' to reflect that the driver is
>> the BMC side of the IPMI BT interface
>> - renamed the device to 'ipmi-bt-host'
>> - introduced a temporary buffer to copy_{to,from}_user
>> - used platform_get_irq()
>> - moved the driver under drivers/char/ipmi/ but kept it as a misc
>> device
>> - changed the compatible cell to "aspeed,ast2400-bt-bmc"
>>
>> .../bindings/char/ipmi/aspeed,ast2400-bt-bmc.txt | 23 +
>> drivers/Makefile | 2 +-
>> drivers/char/ipmi/Kconfig | 7 +
>> drivers/char/ipmi/Makefile | 1 +
>> drivers/char/ipmi/bt-bmc.c | 486 +++++++++++++++++++++
>> include/uapi/linux/Kbuild | 1 +
>> include/uapi/linux/bt-bmc.h | 18 +
>> 7 files changed, 537 insertions(+), 1 deletion(-)
>> create mode 100644 Documentation/devicetree/bindings/char/ipmi/aspeed,ast2400-bt-bmc.txt
>> create mode 100644 drivers/char/ipmi/bt-bmc.c
>> create mode 100644 include/uapi/linux/bt-bmc.h
>>
>> diff --git a/Documentation/devicetree/bindings/char/ipmi/aspeed,ast2400-bt-bmc.txt b/Documentation/devicetree/bindings/char/ipmi/aspeed,ast2400-bt-bmc.txt
>> new file mode 100644
>> index 000000000000..fbbacd958240
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/char/ipmi/aspeed,ast2400-bt-bmc.txt
>> @@ -0,0 +1,23 @@
>> +* Aspeed BT (Block Transfer) IPMI interface
>> +
>> +The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
>> +(BaseBoard Management Controllers) and the BT interface can be used to
>> +perform in-band IPMI communication with their host.
>> +
>> +Required properties:
>> +
>> +- compatible : should be "aspeed,ast2400-bt-bmc"
>> +- reg: physical address and size of the registers
>> +
>> +Optional properties:
>> +
>> +- interrupts: interrupt generated by the BT interface. without an
>> + interrupt, the driver will operate in poll mode.
>> +
>> +Example:
>> +
>> + ibt at 1e789140 {
>> + compatible = "aspeed,ast2400-bt-bmc";
>> + reg = <0x1e789140 0x18>;
>> + interrupts = <8>;
>> + };
>> diff --git a/drivers/Makefile b/drivers/Makefile
>> index 53abb4a5f736..5a9e7b6b7928 100644
>> --- a/drivers/Makefile
>> +++ b/drivers/Makefile
>> @@ -21,7 +21,7 @@ obj-y += video/
>> obj-y += idle/
>> # IPMI must come before ACPI in order to provide IPMI opregion support
>> -obj-$(CONFIG_IPMI_HANDLER) += char/ipmi/
>> +obj-y += char/ipmi/
>> obj-$(CONFIG_ACPI) += acpi/
>> obj-$(CONFIG_SFI) += sfi/
>> diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
>> index 5a9350b1069a..2c234e3e7513 100644
>> --- a/drivers/char/ipmi/Kconfig
>> +++ b/drivers/char/ipmi/Kconfig
>> @@ -76,3 +76,10 @@ config IPMI_POWEROFF
>> the IPMI management controller is capable of this.
>> endif # IPMI_HANDLER
>> +
>> +config ASPEED_BT_IPMI_BMC
>> + tristate "BT IPMI bmc driver"
>> + help
>> + Provides a driver for the BT (Block Transfer) IPMI interface
>> + found on Aspeed SOCs (AST2400 and AST2500). The driver
>> + implements the BMC side of the BT interface.
>> diff --git a/drivers/char/ipmi/Makefile b/drivers/char/ipmi/Makefile
>> index f3ffde1f5f1f..0d98cd91def1 100644
>> --- a/drivers/char/ipmi/Makefile
>> +++ b/drivers/char/ipmi/Makefile
>> @@ -11,3 +11,4 @@ obj-$(CONFIG_IPMI_SSIF) += ipmi_ssif.o
>> obj-$(CONFIG_IPMI_POWERNV) += ipmi_powernv.o
>> obj-$(CONFIG_IPMI_WATCHDOG) += ipmi_watchdog.o
>> obj-$(CONFIG_IPMI_POWEROFF) += ipmi_poweroff.o
>> +obj-$(CONFIG_ASPEED_BT_IPMI_BMC) += bt-bmc.o
>> diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
>> new file mode 100644
>> index 000000000000..b96cb421e1c2
>> --- /dev/null
>> +++ b/drivers/char/ipmi/bt-bmc.c
>> @@ -0,0 +1,486 @@
>> +/*
>> + * Copyright (c) 2015-2016, IBM Corporation.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation; either version
>> + * 2 of the License, or (at your option) any later version.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/moduleparam.h>
>> +#include <linux/errno.h>
>> +#include <linux/poll.h>
>> +#include <linux/sched.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/slab.h>
>> +#include <linux/init.h>
>> +#include <linux/device.h>
>> +#include <linux/of.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/io.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/delay.h>
>> +#include <linux/miscdevice.h>
>> +#include <linux/timer.h>
>> +#include <linux/jiffies.h>
>> +#include <linux/bt-bmc.h>
>> +
>> +/*
>> + * This is a BMC device used to communicate to the host
>> + */
>> +#define DEVICE_NAME "ipmi-bt-host"
>> +
>> +#define BT_IO_BASE 0xe4
>> +#define BT_IRQ 10
>> +
>> +#define BT_CR0 0x0
>> +#define BT_CR0_IO_BASE 16
>> +#define BT_CR0_IRQ 12
>> +#define BT_CR0_EN_CLR_SLV_RDP 0x8
>> +#define BT_CR0_EN_CLR_SLV_WRP 0x4
>> +#define BT_CR0_ENABLE_IBT 0x1
>> +#define BT_CR1 0x4
>> +#define BT_CR1_IRQ_H2B 0x01
>> +#define BT_CR1_IRQ_HBUSY 0x40
>> +#define BT_CR2 0x8
>> +#define BT_CR2_IRQ_H2B 0x01
>> +#define BT_CR2_IRQ_HBUSY 0x40
>> +#define BT_CR3 0xc
>> +#define BT_CTRL 0x10
>> +#define BT_CTRL_B_BUSY 0x80
>> +#define BT_CTRL_H_BUSY 0x40
>> +#define BT_CTRL_OEM0 0x20
>> +#define BT_CTRL_SMS_ATN 0x10
>> +#define BT_CTRL_B2H_ATN 0x08
>> +#define BT_CTRL_H2B_ATN 0x04
>> +#define BT_CTRL_CLR_RD_PTR 0x02
>> +#define BT_CTRL_CLR_WR_PTR 0x01
>> +#define BT_BMC2HOST 0x14
>> +#define BT_INTMASK 0x18
>> +#define BT_INTMASK_B2H_IRQEN 0x01
>> +#define BT_INTMASK_B2H_IRQ 0x02
>> +#define BT_INTMASK_BMC_HWRST 0x80
>> +
>> +struct bt_bmc {
>> + struct device dev;
>> + struct miscdevice miscdev;
>> + void __iomem *base;
>> + int open_count;
>> + int irq;
>> + wait_queue_head_t queue;
>> + struct timer_list poll_timer;
>> +};
>> +
>> +static u8 bt_inb(struct bt_bmc *bt_bmc, int reg)
>> +{
>> + return ioread8(bt_bmc->base + reg);
>> +}
>> +
>> +static void bt_outb(struct bt_bmc *bt_bmc, u8 data, int reg)
>> +{
>> + iowrite8(data, bt_bmc->base + reg);
>> +}
>> +
>> +static void clr_rd_ptr(struct bt_bmc *bt_bmc)
>> +{
>> + bt_outb(bt_bmc, BT_CTRL_CLR_RD_PTR, BT_CTRL);
>> +}
>> +
>> +static void clr_wr_ptr(struct bt_bmc *bt_bmc)
>> +{
>> + bt_outb(bt_bmc, BT_CTRL_CLR_WR_PTR, BT_CTRL);
>> +}
>> +
>> +static void clr_h2b_atn(struct bt_bmc *bt_bmc)
>> +{
>> + bt_outb(bt_bmc, BT_CTRL_H2B_ATN, BT_CTRL);
>> +}
>> +
>> +static void set_b_busy(struct bt_bmc *bt_bmc)
>> +{
>> + if (!(bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_B_BUSY))
>> + bt_outb(bt_bmc, BT_CTRL_B_BUSY, BT_CTRL);
>> +}
>> +
>> +static void clr_b_busy(struct bt_bmc *bt_bmc)
>> +{
>> + if (bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_B_BUSY)
>> + bt_outb(bt_bmc, BT_CTRL_B_BUSY, BT_CTRL);
>> +}
>> +
>> +static void set_b2h_atn(struct bt_bmc *bt_bmc)
>> +{
>> + bt_outb(bt_bmc, BT_CTRL_B2H_ATN, BT_CTRL);
>> +}
>> +
>> +static u8 bt_read(struct bt_bmc *bt_bmc)
>> +{
>> + return bt_inb(bt_bmc, BT_BMC2HOST);
>> +}
>> +
>> +static ssize_t bt_readn(struct bt_bmc *bt_bmc, u8 *buf, size_t n)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < n; i++)
>> + buf[i] = bt_read(bt_bmc);
>> + return n;
>> +}
>> +
>> +static void bt_write(struct bt_bmc *bt_bmc, u8 c)
>> +{
>> + bt_outb(bt_bmc, c, BT_BMC2HOST);
>> +}
>> +
>> +static ssize_t bt_writen(struct bt_bmc *bt_bmc, u8 *buf, size_t n)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < n; i++)
>> + bt_write(bt_bmc, buf[i]);
>> + return n;
>> +}
>> +
>> +static void set_sms_atn(struct bt_bmc *bt_bmc)
>> +{
>> + bt_outb(bt_bmc, BT_CTRL_SMS_ATN, BT_CTRL);
>> +}
>> +
>> +static struct bt_bmc *file_bt_bmc(struct file *file)
>> +{
>> + return container_of(file->private_data, struct bt_bmc, miscdev);
>> +}
>> +
>> +static int bt_bmc_open(struct inode *inode, struct file *file)
>> +{
>> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
>> +
>> + clr_b_busy(bt_bmc);
>> +
>> + return 0;
>> +}
>> +
>> +#define BT_BMC_BUFFER_SIZE 256
>> +
>> +/*
>> + * The BT (Block Transfer) interface means that entire messages are
>> + * buffered by the host before a notification is sent to the BMC that
>> + * there is data to be read. The first byte is the length and the
>> + * message data follows. The read operation just tries to capture the
>> + * whole before returning it to userspace.
>> + */
>> +static ssize_t bt_bmc_read(struct file *file, char __user *buf,
>> + size_t count, loff_t *ppos)
>> +{
>> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
>> + u8 len;
>> + int len_byte = 1;
>> + u8 kbuffer[BT_BMC_BUFFER_SIZE];
>> + ssize_t ret = 0;
>> + ssize_t nread;
>> +
>> + if (!access_ok(VERIFY_WRITE, buf, count))
>> + return -EFAULT;
>> +
>> + WARN_ON(*ppos);
>> +
>> + if (wait_event_interruptible(bt_bmc->queue,
>> + bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_H2B_ATN))
>> + return -ERESTARTSYS;
>> +
>> + set_b_busy(bt_bmc);
>> + clr_h2b_atn(bt_bmc);
>> + clr_rd_ptr(bt_bmc);
>> +
>> + /*
>> + * The BT frames start with the message length, which does not
>> + * include the length byte.
>> + */
>> + kbuffer[0] = bt_read(bt_bmc);
>> + len = kbuffer[0];
>> +
>> + /* We pass the length back to userspace as well */
>> + if (len + 1 > count)
>> + len = count - 1;
>> +
>> + while (len) {
>> + nread = min_t(ssize_t, len, sizeof(kbuffer) - len_byte);
>> +
>> + bt_readn(bt_bmc, kbuffer + len_byte, nread);
>> +
>> + if (copy_to_user(buf, kbuffer, nread + len_byte)) {
>> + ret = -EFAULT;
>> + break;
>> + }
>> + len -= nread;
>> + buf += nread + len_byte;
>> + ret += nread + len_byte;
>> + len_byte = 0;
>> + }
>> +
>> + clr_b_busy(bt_bmc);
>> +
>> + return ret;
>> +}
>> +
>> +static ssize_t bt_bmc_write(struct file *file, const char __user *buf,
>> + size_t count, loff_t *ppos)
>> +{
>> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
>> + u8 kbuffer[BT_BMC_BUFFER_SIZE];
>> + ssize_t ret = 0;
>> + ssize_t nwritten;
>> +
>> + if (!access_ok(VERIFY_READ, buf, count))
>> + return -EFAULT;
>> +
>> + WARN_ON(*ppos);
>> +
>> + /* There's no interrupt for clearing bmc busy so we have to
>> + * poll
>> + */
>> + if (wait_event_interruptible(bt_bmc->queue,
>> + !(bt_inb(bt_bmc, BT_CTRL) &
>> + (BT_CTRL_H_BUSY | BT_CTRL_B2H_ATN))))
>> + return -ERESTARTSYS;
>> +
>> + clr_wr_ptr(bt_bmc);
>> +
>> + while (count) {
>> + nwritten = min_t(ssize_t, count, sizeof(kbuffer));
>> + if (copy_from_user(&kbuffer, buf, nwritten)) {
>> + ret = -EFAULT;
>> + break;
>> + }
>> +
>> + bt_writen(bt_bmc, kbuffer, nwritten);
>> +
>> + count -= nwritten;
>> + buf += nwritten;
>> + ret += nwritten;
>> + }
>> +
>> + set_b2h_atn(bt_bmc);
>> +
>> + return ret;
>> +}
>> +
>> +static long bt_bmc_ioctl(struct file *file, unsigned int cmd,
>> + unsigned long param)
>> +{
>> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
>> +
>> + switch (cmd) {
>> + case BT_BMC_IOCTL_SMS_ATN:
>> + set_sms_atn(bt_bmc);
>> + return 0;
>> + }
>> + return -EINVAL;
>> +}
>> +
>> +static int bt_bmc_release(struct inode *inode, struct file *file)
>> +{
>> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
>> +
>> + set_b_busy(bt_bmc);
>> + return 0;
>> +}
>> +
>> +static unsigned int bt_bmc_poll(struct file *file, poll_table *wait)
>> +{
>> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
>> + unsigned int mask = 0;
>> + uint8_t ctrl;
>> +
>> + poll_wait(file, &bt_bmc->queue, wait);
>> +
>> + ctrl = bt_inb(bt_bmc, BT_CTRL);
>> +
>> + if (ctrl & BT_CTRL_H2B_ATN)
>> + mask |= POLLIN;
>> +
>> + if (!(ctrl & (BT_CTRL_H_BUSY | BT_CTRL_B2H_ATN)))
>> + mask |= POLLOUT;
>> +
>> + return mask;
>> +}
>> +
>> +static const struct file_operations bt_bmc_fops = {
>> + .owner = THIS_MODULE,
>> + .open = bt_bmc_open,
>> + .read = bt_bmc_read,
>> + .write = bt_bmc_write,
>> + .release = bt_bmc_release,
>> + .poll = bt_bmc_poll,
>> + .unlocked_ioctl = bt_bmc_ioctl,
>> +};
>> +
>> +static void poll_timer(unsigned long data)
>> +{
>> + struct bt_bmc *bt_bmc = (void *)data;
>> +
>> + bt_bmc->poll_timer.expires += msecs_to_jiffies(500);
>> + wake_up(&bt_bmc->queue);
>> + add_timer(&bt_bmc->poll_timer);
>> +}
>> +
>> +static irqreturn_t bt_bmc_irq(int irq, void *arg)
>> +{
>> + struct bt_bmc *bt_bmc = arg;
>> + uint32_t reg;
>> +
>> + reg = ioread32(bt_bmc->base + BT_CR2);
>> + reg &= BT_CR2_IRQ_H2B | BT_CR2_IRQ_HBUSY;
>> + if (!reg)
>> + return IRQ_NONE;
>> +
>> + /* ack pending IRQs */
>> + iowrite32(reg, bt_bmc->base + BT_CR2);
>> +
>> + wake_up(&bt_bmc->queue);
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
>> + struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + uint32_t reg;
>> + int rc;
>> +
>> + bt_bmc->irq = platform_get_irq(pdev, 0);
>> + if (!bt_bmc->irq)
>> + return -ENODEV;
>> +
>> + rc = devm_request_irq(dev, bt_bmc->irq, bt_bmc_irq, IRQF_SHARED,
>> + DEVICE_NAME, bt_bmc);
>> + if (rc < 0) {
>> + dev_warn(dev, "Unable to request IRQ %d\n", bt_bmc->irq);
>> + bt_bmc->irq = 0;
>> + return rc;
>> + }
>> +
>> + /* Configure IRQs on the bmc clearing the H2B and HBUSY bits;
>> + * H2B will be asserted when the bmc has data for us; HBUSY
>> + * will be cleared (along with B2H) when we can write the next
>> + * message to the BT buffer
>> + */
>> + reg = ioread32(bt_bmc->base + BT_CR1);
>> + reg |= BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY;
>> + iowrite32(reg, bt_bmc->base + BT_CR1);
>> +
>> + return 0;
>> +}
>> +
>> +static int bt_bmc_probe(struct platform_device *pdev)
>> +{
>> + struct bt_bmc *bt_bmc;
>> + struct device *dev;
>> + struct resource *res;
>> + int rc;
>> +
>> + if (!pdev || !pdev->dev.of_node)
>> + return -ENODEV;
>> +
>> + dev = &pdev->dev;
>> + dev_info(dev, "Found bt bmc device\n");
>> +
>> + bt_bmc = devm_kzalloc(dev, sizeof(*bt_bmc), GFP_KERNEL);
>> + if (!bt_bmc)
>> + return -ENOMEM;
>> +
>> + dev_set_drvdata(&pdev->dev, bt_bmc);
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res) {
>> + dev_err(dev, "Unable to find resources\n");
>> + rc = -ENXIO;
>> + goto out_free;
>> + }
>> +
>> + bt_bmc->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (!bt_bmc->base) {
>> + rc = -ENOMEM;
>> + goto out_free;
>> + }
>> +
>> + init_waitqueue_head(&bt_bmc->queue);
>> +
>> + bt_bmc->miscdev.minor = MISC_DYNAMIC_MINOR,
>> + bt_bmc->miscdev.name = DEVICE_NAME,
>> + bt_bmc->miscdev.fops = &bt_bmc_fops,
>> + bt_bmc->miscdev.parent = dev;
>> + rc = misc_register(&bt_bmc->miscdev);
>> + if (rc) {
>> + dev_err(dev, "Unable to register device\n");
>> + goto out_unmap;
>> + }
>> +
>> + bt_bmc_config_irq(bt_bmc, pdev);
>> +
>> + if (bt_bmc->irq) {
>> + dev_info(dev, "Using IRQ %d\n", bt_bmc->irq);
>> + } else {
>> + dev_info(dev, "No IRQ; using timer\n");
>> + setup_timer(&bt_bmc->poll_timer, poll_timer,
>> + (unsigned long)bt_bmc);
>> + bt_bmc->poll_timer.expires = jiffies + msecs_to_jiffies(10);
>> + add_timer(&bt_bmc->poll_timer);
>> + }
>> +
>> + iowrite32((BT_IO_BASE << BT_CR0_IO_BASE) |
>> + (BT_IRQ << BT_CR0_IRQ) |
>> + BT_CR0_EN_CLR_SLV_RDP |
>> + BT_CR0_EN_CLR_SLV_WRP |
>> + BT_CR0_ENABLE_IBT,
>> + bt_bmc->base + BT_CR0);
>> +
>> + clr_b_busy(bt_bmc);
>> +
>> + return 0;
>> +
>> +out_unmap:
>> + devm_iounmap(&pdev->dev, bt_bmc->base);
>> +
>> +out_free:
>> + devm_kfree(dev, bt_bmc);
>> + return rc;
>> +
>> +}
>> +
>> +static int bt_bmc_remove(struct platform_device *pdev)
>> +{
>> + struct bt_bmc *bt_bmc = dev_get_drvdata(&pdev->dev);
>> +
>> + misc_deregister(&bt_bmc->miscdev);
>> + if (!bt_bmc->irq)
>> + del_timer_sync(&bt_bmc->poll_timer);
>> + devm_iounmap(&pdev->dev, bt_bmc->base);
>> + devm_kfree(&pdev->dev, bt_bmc);
>> + bt_bmc = NULL;
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id bt_bmc_match[] = {
>> + { .compatible = "aspeed,ast2400-bt-bmc" },
>> + { },
>> +};
>> +
>> +static struct platform_driver bt_bmc_driver = {
>> + .driver = {
>> + .name = DEVICE_NAME,
>> + .of_match_table = bt_bmc_match,
>> + },
>> + .probe = bt_bmc_probe,
>> + .remove = bt_bmc_remove,
>> +};
>> +
>> +module_platform_driver(bt_bmc_driver);
>> +
>> +MODULE_DEVICE_TABLE(of, bt_bmc_match);
>> +MODULE_LICENSE("GPL");
>> +MODULE_AUTHOR("Alistair Popple <alistair@popple.id.au>");
>> +MODULE_DESCRIPTION("Linux device interface to the BT interface");
>> diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild
>> index 185f8ea2702f..17b12942c67d 100644
>> --- a/include/uapi/linux/Kbuild
>> +++ b/include/uapi/linux/Kbuild
>> @@ -74,6 +74,7 @@ header-y += bpf_common.h
>> header-y += bpf.h
>> header-y += bpqether.h
>> header-y += bsg.h
>> +header-y += bt-bmc.h
>> header-y += btrfs.h
>> header-y += can.h
>> header-y += capability.h
>> diff --git a/include/uapi/linux/bt-bmc.h b/include/uapi/linux/bt-bmc.h
>> new file mode 100644
>> index 000000000000..d9ec766a63d0
>> --- /dev/null
>> +++ b/include/uapi/linux/bt-bmc.h
>> @@ -0,0 +1,18 @@
>> +/*
>> + * Copyright (c) 2015-2016, IBM Corporation.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation; either version
>> + * 2 of the License, or (at your option) any later version.
>> + */
>> +
>> +#ifndef _UAPI_LINUX_BT_BMC_H
>> +#define _UAPI_LINUX_BT_BMC_H
>> +
>> +#include <linux/ioctl.h>
>> +
>> +#define __BT_BMC_IOCTL_MAGIC 0xb1
>> +#define BT_BMC_IOCTL_SMS_ATN _IO(__BT_BMC_IOCTL_MAGIC, 0x00)
>> +
>> +#endif /* _UAPI_LINUX_BT_BMC_H */
>
>
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