* [PATCH v26 0/7] arm64: add kdump support
From: Ard Biesheuvel @ 2016-09-19 16:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57E00CDC.70403@arm.com>
On 19 September 2016 at 17:05, James Morse <james.morse@arm.com> wrote:
> On 16/09/16 21:17, Ard Biesheuvel wrote:
>> On 16 September 2016 at 17:04, James Morse <james.morse@arm.com> wrote:
>>> Mark, Ard, how does/will reserved-memory work on an APCI only system?
>>
>> It works by accident, at the moment. We used to ignore both
>> /memreserve/s and the /reserved-memory node, but due to some unrelated
>> refactoring, we ended up honouring the reserved-memory node when
>> booting via UEFI
>
> Okay, so kdump probably shouldn't rely on this behaviour...
>
No, but I would still like to keep /reserved-memory node support for
dynamic ranges, since they are guaranteed not to contain anything
'magic' left behind by the firmware. So if we keep /that/, keeping
static allocation support (with validation, as I proposed in the
series I quoted) is only a small step.
--
Ard.
> For an acpi-only system, we could get reserve_crashkernel() to copy the uefi
> memory map into the reserved region, changing the region types for existing
> kernel memory to EfiReservedMemoryType (for example) and fixing up the reserved
> region boundaries.
>
> This second memory map could then be added alongside the real one in the
> DT/chosen, and used in preference the second time we go through uefi_init() in
> the crash kernel.
>
> kexec-tools would still need to keep the '/reserved-memory' node for non-uefi
> systems.
>
> Doing this doesn't depend on userspace, and means the uefi memory map is still
> the one and only true source of memory layout information. If fixing it like
> this is valid I don't think it should block kdump.
>
> ... I will think about this some more before trying to put it together.
>
>
>
> Thanks,
>
> James
^ permalink raw reply
* [PATCH v26 0/7] arm64: add kdump support
From: James Morse @ 2016-09-19 16:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKv+Gu_UvFnPtFHggaO6Z_ePuArdchEK1qYWPkkwpcgLus3Epw@mail.gmail.com>
On 16/09/16 21:17, Ard Biesheuvel wrote:
> On 16 September 2016 at 17:04, James Morse <james.morse@arm.com> wrote:
>> Mark, Ard, how does/will reserved-memory work on an APCI only system?
>
> It works by accident, at the moment. We used to ignore both
> /memreserve/s and the /reserved-memory node, but due to some unrelated
> refactoring, we ended up honouring the reserved-memory node when
> booting via UEFI
Okay, so kdump probably shouldn't rely on this behaviour...
For an acpi-only system, we could get reserve_crashkernel() to copy the uefi
memory map into the reserved region, changing the region types for existing
kernel memory to EfiReservedMemoryType (for example) and fixing up the reserved
region boundaries.
This second memory map could then be added alongside the real one in the
DT/chosen, and used in preference the second time we go through uefi_init() in
the crash kernel.
kexec-tools would still need to keep the '/reserved-memory' node for non-uefi
systems.
Doing this doesn't depend on userspace, and means the uefi memory map is still
the one and only true source of memory layout information. If fixing it like
this is valid I don't think it should block kdump.
... I will think about this some more before trying to put it together.
Thanks,
James
^ permalink raw reply
* [GIT PULL] Amlogic 64-bit DT updates for v4.9, round 2 (for next/late)
From: Arnd Bergmann @ 2016-09-19 15:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7h37l0kbv9.fsf@baylibre.com>
On Thursday, September 15, 2016 3:59:54 PM CEST Kevin Hilman wrote:
> Here is round 2 of the 64-bit DT changes for v4.9.
>
> Based on my drivers pull (round 2), this is targetted at next/late also
> since the DT patches here are using clock IDs that come from my 2nd
> drivers pull (which itself has merged an immtable branch from the clock
> tree.)
>
Pulled into next/late, thanks!
Arnd
^ permalink raw reply
* [GIT PULL 1/3] ARM: soc: exynos: Drivers for v4.9
From: Krzysztof Kozlowski @ 2016-09-19 15:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2663426.T8oUku18qe@wuerfel>
On Mon, Sep 19, 2016 at 05:02:40PM +0200, Arnd Bergmann wrote:
> On Sunday, September 18, 2016 6:39:46 PM CEST Krzysztof Kozlowski wrote:
> > Samsung drivers/soc update for v4.9:
> > 1. Allow compile testing of exynos-mct clocksource driver on ARM64.
> > 2. Document Exynos5433 PMU compatible (already used by clkout driver and more
> > will be coming soon).
>
> Pulled into next/drivers, thanks
>
> Just for my understanding: why do we need the exynos-mct driver on ARM64
> but not the delay-timer portion of it?
I think we want all of it but Doug's optimization 3252a646aa2c
("clocksource: exynos_mct: Only use 32-bits where possible") is not
ARM64 friendly. One way of dealing with it would be to prepare two
versions of exynos4_read_current_timer(). One reading only lower 32-bit
value for ARMv7 and second (slow) reading lower and upper for ARMv8.
>
> Is there an advantage in using MCT over the architected timer on these
> chips? If so, should we also have a way to use it as the delay timer?
No, there is no real advantage... except that the SoC has some
interesting "characteristics"... The timers are tightly coupled. Very
tightly. I spent a lot of time and failed to boot my ARMv8 board without
some MCT magic.
Best regards,
Krzysztof
^ permalink raw reply
* [GIT PULL] Amlogic driver updates for v4.9, 2nd round
From: Arnd Bergmann @ 2016-09-19 15:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7hoa3ql2y7.fsf@baylibre.com>
On Wednesday, September 14, 2016 12:02:40 PM CEST Kevin Hilman wrote:
> Amlogic driver updates for v4.9, 2nd round
> - media: update IR support for newer SoCs
> - firmware: add secure monitor driver
> - net: new stmmac glue driver
> - usb: udd DWC2 support for meson-gxbb
> - clocks: expose more clock IDs for use by DT
> - DT binding updates
>
Pulled into next/late. I think in a case like this, separate
branches would have been a bit nicer, as this branch mixes some things
that are not really related.
> ----------------------------------------------------------------
> Alexander M?ller (6):
> clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention
> meson: clk: Move register definitions to meson8b.h
> meson: clk: Rename register names according to Amlogic datasheet
> clk: meson: Copy meson8b CLKID defines to private header file
> gxbb: clk: Adjust MESON_GATE macro to be shared with meson8b
> meson: clk: Add support for clock gates
I also note that some of the subject lines are inconsistent regarding
the "clk: meson:" vs "gxbb: clk:" part.
Arnd
^ permalink raw reply
* [PATCH] ASoC: samsung: make audio interface/controller explicitly
From: Randy Li @ 2016-09-19 15:51 UTC (permalink / raw)
To: linux-arm-kernel
It is simple sound card time, we could assign different codec
to a interface without making a specific driver for it. The SPDIF
and I2S interface for Samsung would be possible used by simple-sound-card,
but not sure about the PCM.
Signed-off-by: Randy Li <ayaka@soulik.info>
---
sound/soc/samsung/Kconfig | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index 7b722b0..210ce38 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -1,3 +1,7 @@
+menu "SoC Audio for Samsung CPUs"
+
+comment "Common SoC Audio options for Samsung CPUs:"
+
config SND_SOC_SAMSUNG
tristate "ASoC support for Samsung"
depends on (PLAT_SAMSUNG || ARCH_EXYNOS)
@@ -18,18 +22,22 @@ config SND_S3C2412_SOC_I2S
select SND_S3C_I2SV2_SOC
config SND_SAMSUNG_PCM
- tristate
+ tristate "Samsung PCM interface support"
+ depends on SND_SOC_SAMSUNG
config SND_SAMSUNG_AC97
tristate
select SND_SOC_AC97_BUS
+ depends on SND_SOC_SAMSUNG
config SND_SAMSUNG_SPDIF
- tristate
+ tristate "Samsung SPDIF transmitter support"
+ depends on SND_SOC_SAMSUNG
select SND_SOC_SPDIF
config SND_SAMSUNG_I2S
- tristate
+ tristate "Samsung I2S interface support"
+ depends on I2C && SND_SOC_SAMSUNG
config SND_SOC_SAMSUNG_NEO1973_WM8753
tristate "Audio support for Openmoko Neo1973 Smartphones (GTA02)"
@@ -229,3 +237,5 @@ config SND_SOC_ARNDALE_RT5631_ALC5631
depends on SND_SOC_SAMSUNG && I2C
select SND_SAMSUNG_I2S
select SND_SOC_RT5631
+
+endmenu
--
2.7.4
^ permalink raw reply related
* [PATCH v3 4/8] scpi: Add support for Legacy match table for Amlogic GXBB SoC
From: Sudeep Holla @ 2016-09-19 15:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6698b7b9-6ffc-d120-be9c-851ea0be2bf2@arm.com>
On 19/09/16 16:50, Sudeep Holla wrote:
>
>
> On 07/09/16 16:34, Neil Armstrong wrote:
>> Add new DT match table to setup the is_legacy boolean value across
>> the scpi functions.
>> Add the Amlogic GXBB SoC compatible for platform and as legacy match
>> entry.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>> drivers/firmware/arm_scpi.c | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
>> index 6a16100..60a76e63 100644
>> --- a/drivers/firmware/arm_scpi.c
>> +++ b/drivers/firmware/arm_scpi.c
>> @@ -979,6 +979,11 @@ static int scpi_alloc_xfer_list(struct device
>> *dev, struct scpi_chan *ch)
>> return 0;
>> }
>>
>> +static const struct of_device_id legacy_scpi_of_match[] = {
>> + {.compatible = "amlogic,meson-gxbb-scpi"},
>> + {},
>> +};
>
> This needs to be documented.
>
Ignore that I see you have done that in the later patch.
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH v2] ARM: mvebu: Select corediv clk for all mvebu v7 SoC
From: Uwe Kleine-König @ 2016-09-19 15:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160919154824.22919-1-gregory.clement@free-electrons.com>
On Mon, Sep 19, 2016 at 05:48:24PM +0200, Gregory CLEMENT wrote:
> Since the commit bd3677ff31a3 ("clk: mvebu: Remove corediv clock from
> Armada XP"), the corediv clk is no more selected for Armada XP, however
> this clock is used for Armada XP using the compatible
> armada-370-corediv-clock.
>
> While since commit 1594d568c6e3 ("clk: mvebu: Move corediv config to
> mvebu config") Armada 38x and Armada 375 got corediv support again, not
> only Armada XP was missed but also Armada 39x.
>
> Actually all the SoC selecting MVEBU_V7 config need this clock:
> git grep "\-corediv-clock" arch/arm/boot/dts
> arch/arm/boot/dts/armada-370-xp.dtsi: compatible = "marvell,armada-370-corediv-clock";
> arch/arm/boot/dts/armada-375.dtsi: compatible = "marvell,armada-375-corediv-clock";
> arch/arm/boot/dts/armada-38x.dtsi: compatible = "marvell,armada-380-corediv-clock";
> arch/arm/boot/dts/armada-39x.dtsi: compatible = "marvell,armada-390-corediv-clock"
>
> This commit now fixes this behavior by letting MVEBU_V7 select
> MVEBU_CLK_COREDIV.
>
> Fixes: bd3677ff31a3 ("clk: mvebu: Remove corediv clock from Armada XP")
> Cc: stable at vger.kernel.org
> Reported-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
Acked-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Thanks
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH v3 4/8] scpi: Add support for Legacy match table for Amlogic GXBB SoC
From: Sudeep Holla @ 2016-09-19 15:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473262477-18045-5-git-send-email-narmstrong@baylibre.com>
On 07/09/16 16:34, Neil Armstrong wrote:
> Add new DT match table to setup the is_legacy boolean value across
> the scpi functions.
> Add the Amlogic GXBB SoC compatible for platform and as legacy match entry.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> drivers/firmware/arm_scpi.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
> index 6a16100..60a76e63 100644
> --- a/drivers/firmware/arm_scpi.c
> +++ b/drivers/firmware/arm_scpi.c
> @@ -979,6 +979,11 @@ static int scpi_alloc_xfer_list(struct device *dev, struct scpi_chan *ch)
> return 0;
> }
>
> +static const struct of_device_id legacy_scpi_of_match[] = {
> + {.compatible = "amlogic,meson-gxbb-scpi"},
> + {},
> +};
This needs to be documented.
> +
> static int scpi_probe(struct platform_device *pdev)
> {
> int count, idx, ret;
> @@ -991,6 +996,9 @@ static int scpi_probe(struct platform_device *pdev)
> if (!scpi_info)
> return -ENOMEM;
>
> + if (of_match_device(legacy_scpi_of_match, &pdev->dev))
> + scpi_info->is_legacy = true;
> +
> count = of_count_phandle_with_args(np, "mboxes", "#mbox-cells");
> if (count < 0) {
> dev_err(dev, "no mboxes property in '%s'\n", np->full_name);
> @@ -1097,6 +1105,7 @@ err:
>
> static const struct of_device_id scpi_of_match[] = {
> {.compatible = "arm,scpi"},
> + {.compatible = "amlogic,meson-gxbb-scpi"},
I also prefer adding "arm,legacy-scpi". So far AMLogic has followed the
legacy specification except the capabilities. You could use
"amlogic,meson-gxbb-scpi" for that and "arm,legacy-scpi" for the probe
part or we can add the use of "amlogic,meson-gxbb-scpi" later but just
document it now.
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH v2] ARM: mvebu: Select corediv clk for all mvebu v7 SoC
From: Gregory CLEMENT @ 2016-09-19 15:48 UTC (permalink / raw)
To: linux-arm-kernel
Since the commit bd3677ff31a3 ("clk: mvebu: Remove corediv clock from
Armada XP"), the corediv clk is no more selected for Armada XP, however
this clock is used for Armada XP using the compatible
armada-370-corediv-clock.
While since commit 1594d568c6e3 ("clk: mvebu: Move corediv config to
mvebu config") Armada 38x and Armada 375 got corediv support again, not
only Armada XP was missed but also Armada 39x.
Actually all the SoC selecting MVEBU_V7 config need this clock:
git grep "\-corediv-clock" arch/arm/boot/dts
arch/arm/boot/dts/armada-370-xp.dtsi: compatible = "marvell,armada-370-corediv-clock";
arch/arm/boot/dts/armada-375.dtsi: compatible = "marvell,armada-375-corediv-clock";
arch/arm/boot/dts/armada-38x.dtsi: compatible = "marvell,armada-380-corediv-clock";
arch/arm/boot/dts/armada-39x.dtsi: compatible = "marvell,armada-390-corediv-clock"
This commit now fixes this behavior by letting MVEBU_V7 select
MVEBU_CLK_COREDIV.
Fixes: bd3677ff31a3 ("clk: mvebu: Remove corediv clock from Armada XP")
Cc: stable at vger.kernel.org
Reported-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
Changelog:
v1 -> v2
- Improve commit log as suggested by Uwe
arch/arm/mach-mvebu/Kconfig | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index f9b6bd306cfe..541647f57192 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -23,6 +23,7 @@ config MACH_MVEBU_V7
select CACHE_L2X0
select ARM_CPU_SUSPEND
select MACH_MVEBU_ANY
+ select MVEBU_CLK_COREDIV
config MACH_ARMADA_370
bool "Marvell Armada 370 boards"
@@ -32,7 +33,6 @@ config MACH_ARMADA_370
select CPU_PJ4B
select MACH_MVEBU_V7
select PINCTRL_ARMADA_370
- select MVEBU_CLK_COREDIV
help
Say 'Y' here if you want your kernel to support boards based
on the Marvell Armada 370 SoC with device tree.
@@ -50,7 +50,6 @@ config MACH_ARMADA_375
select HAVE_SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_375
- select MVEBU_CLK_COREDIV
help
Say 'Y' here if you want your kernel to support boards based
on the Marvell Armada 375 SoC with device tree.
@@ -68,7 +67,6 @@ config MACH_ARMADA_38X
select HAVE_SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_38X
- select MVEBU_CLK_COREDIV
help
Say 'Y' here if you want your kernel to support boards based
on the Marvell Armada 380/385 SoC with device tree.
--
2.9.3
^ permalink raw reply related
* [PATCH v8 2/2] ARM: dts: add TOPEET itop elite based board
From: Randy Li @ 2016-09-19 15:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474300103-26659-1-git-send-email-ayaka@soulik.info>
The TOPEET itop exynos 4412 have three versions base board. The
Elite version is the cheap one without too much peripheral devices
on it.
Currently supported are serial console, wired networking(USB),
USB OTG in peripheral mode, USB host, SD storage, GPIO buttons,
PWM beeper, ADC and LEDs. The WM8960 analog audio codec is also
enabled.
The FIMC is not used for camera currently, I enabled it just for a
colorspace convertor.
Signed-off-by: Randy Li <ayaka@soulik.info>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../bindings/arm/samsung/samsung-boards.txt | 3 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos4412-itop-elite.dts | 240 +++++++++++++++++++++
3 files changed, 244 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos4412-itop-elite.dts
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index 0ea7f14..5160fa5 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -22,6 +22,9 @@ Required root node properties:
* FriendlyARM
- "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM
TINY4412 board.
+ * TOPEET
+ - "topeet,itop4412-elite" - for Exynos4412-based TOPEET
+ Elite base board.
* Google
- "google,pi" - for Exynos5800-based Google Peach Pi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index befcd26..d709f74 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
exynos4210-universal_c210.dtb \
+ exynos4412-itop-elite.dtb \
exynos4412-odroidu3.dtb \
exynos4412-odroidx.dtb \
exynos4412-odroidx2.dtb \
diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
new file mode 100644
index 0000000..b08705e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
@@ -0,0 +1,240 @@
+/*
+ * TOPEET's Exynos4412 based itop board device tree source
+ *
+ * Copyright (c) 2016 SUMOMO Computer Association
+ * https://www.sumomo.mobi
+ * Randy Li <ayaka@soulik.info>
+ *
+ * Device tree source file for TOPEET iTop Exynos 4412 core board
+ * which is based on Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/sound/samsung-i2s.h>
+#include "exynos4412-itop-scp-core.dtsi"
+
+/ {
+ model = "TOPEET iTop 4412 Elite board based on Exynos4412";
+ compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4";
+
+ chosen {
+ bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait";
+ stdout-path = "serial2:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led2 {
+ label = "red:system";
+ gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led3 {
+ label = "red:user";
+ gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ home {
+ label = "GPIO Key Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpx1 1 GPIO_ACTIVE_LOW>;
+ };
+
+ back {
+ label = "GPIO Key Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ sleep {
+ label = "GPIO Key Sleep";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
+ };
+
+ vol-up {
+ label = "GPIO Key Vol+";
+ linux,code = <KEY_UP>;
+ gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ vol-down {
+ label = "GPIO Key Vol-";
+ linux,code = <KEY_DOWN>;
+ gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm-sound";
+
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_MOUT_I2S>,
+ <&clock_audss EXYNOS_DOUT_SRP>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>;
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>;
+ assigned-clock-rates = <0>,
+ <0>,
+ <112896000>,
+ <11289600>;
+
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&link0_codec>;
+ simple-audio-card,frame-master = <&link0_codec>;
+
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Speaker", "Speaker",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Speaker", "SPK_LP",
+ "Speaker", "SPK_LN",
+ "Speaker", "SPK_RP",
+ "Speaker", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "LINPUT3", "Mic Jack",
+ "RINPUT1", "Mic Jack",
+ "RINPUT2", "Mic Jack";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0 0>;
+ };
+
+ link0_codec: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ clocks = <&i2s0 CLK_I2S_CDCLK>;
+ system-clock-frequency = <11289600>;
+ };
+ };
+
+ beep {
+ compatible = "pwm-beeper";
+ pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>;
+ };
+
+ camera: camera {
+ pinctrl-0 = <&cam_port_a_clk_active>;
+ pinctrl-names = "default";
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_CAM0>;
+ assigned-clock-parents = <&clock CLK_XUSBXTI>;
+ };
+};
+
+&adc {
+ vdd-supply = <&ldo3_reg>;
+ status = "okay";
+};
+
+&ehci {
+ status = "okay";
+ /* In order to reset USB ethernet */
+ samsung,vbus-gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;
+
+ port at 0 {
+ status = "okay";
+ };
+
+ port at 2 {
+ status = "okay";
+ };
+};
+
+&exynos_usbphy {
+ status = "okay";
+};
+
+&fimc_0 {
+ status = "okay";
+ assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+ <&clock CLK_SCLK_FIMC0>;
+ assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+ assigned-clock-rates = <0>, <176000000>;
+};
+
+&hsotg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&i2c_4 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ pinctrl-0 = <&i2c4_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ codec: wm8960 at 1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&pmu_system_controller 0>;
+ clock-names = "MCLK1";
+ wlf,shared-lrclk;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&i2s0 {
+ pinctrl-0 = <&i2s0_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+ clocks = <&clock_audss EXYNOS_I2S_BUS>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+};
+
+&pinctrl_1 {
+ ether-reset {
+ samsung,pins = "gpc0-1";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&pwm {
+ status = "okay";
+ pinctrl-0 = <&pwm0_out>;
+ pinctrl-names = "default";
+ samsung,pwm-outputs = <0>;
+};
+
+&sdhci_2 {
+ bus-width = <4>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
+ pinctrl-names = "default";
+ cd-gpio = <&gpx0 7 GPIO_ACTIVE_LOW>;
+ cap-sd-highspeed;
+ vmmc-supply = <&ldo23_reg>;
+ vqmmc-supply = <&ldo17_reg>;
+ status = "okay";
+};
+
+&serial_1 {
+ status = "okay";
+};
+
+&serial_2 {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v8 1/2] ARM: dts: Add TOPEET itop core board SCP package version
From: Randy Li @ 2016-09-19 15:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474300103-26659-1-git-send-email-ayaka@soulik.info>
The TOPEET itop is a samsung exnynos 4412 core board, which have
two package versions. This patch add the support for SCP version.
Currently supported are USB3503A HSIC, USB OTG, eMMC, rtc and
PMIC. The future features are in the based board. Also MFC and
watchdog have been enabled.
Signed-off-by: Randy Li <ayaka@soulik.info>
---
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 501 ++++++++++++++++++++++++
1 file changed, 501 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
new file mode 100644
index 0000000..8fe191b
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
@@ -0,0 +1,501 @@
+/*
+ * TOPEET's Exynos4412 based itop board device tree source
+ *
+ * Copyright (c) 2016 SUMOMO Computer Association
+ * https://www.sumomo.mobi
+ * Randy Li <ayaka@soulik.info>
+ *
+ * Device tree source file for TOPEET iTop Exynos 4412 SCP package core
+ * board which is based on Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "exynos4412.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
+#include "exynos-mfc-reserved-memory.dtsi"
+
+/ {
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x40000000>;
+ };
+
+ firmware at 0203F000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0203F000 0x1000>;
+ };
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 7 7>;
+ };
+ map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 13 13>;
+ };
+ };
+ };
+ };
+
+ usb-hub {
+ compatible = "smsc,usb3503a";
+ reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>;
+ connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>;
+ intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsic_reset>;
+ };
+};
+
+&bus_dmc {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-supply = <&buck1_reg>;
+ status = "okay";
+};
+
+&bus_acp {
+ devfreq = <&bus_dmc>;
+ status = "okay";
+};
+
+&bus_c2c {
+ devfreq = <&bus_dmc>;
+ status = "okay";
+};
+
+&bus_leftbus {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-supply = <&buck3_reg>;
+ status = "okay";
+};
+
+&bus_rightbus {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_fsys {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_peri {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&bus_mfc {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu0-supply = <&buck2_reg>;
+};
+
+&hsotg {
+ vusb_d-supply = <&ldo15_reg>;
+ vusb_a-supply = <&ldo12_reg>;
+};
+
+&i2c_1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-max-bus-freq = <400000>;
+ pinctrl-0 = <&i2c1_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ s5m8767: s5m8767-pmic at 66 {
+ compatible = "samsung,s5m8767-pmic";
+ reg = <0x66>;
+
+ s5m8767,pmic-buck-default-dvs-idx = <3>;
+
+ s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>,
+ <&gpb 6 GPIO_ACTIVE_HIGH>,
+ <&gpb 7 GPIO_ACTIVE_HIGH>;
+
+ s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>,
+ <&gpm3 6 GPIO_ACTIVE_HIGH>,
+ <&gpm3 7 GPIO_ACTIVE_HIGH>;
+
+ /* VDD_ARM */
+ s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>,
+ <1243750>, <1118750>,
+ <1068750>, <1012500>,
+ <956250>, <900000>;
+ /* VDD_INT */
+ s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>,
+ <925000>, <925000>,
+ <887500>, <887500>,
+ <850000>, <850000>;
+ /* VDD_G3D */
+ s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>,
+ <1025000>, <950000>,
+ <918750>, <900000>,
+ <875000>, <831250>;
+
+ regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "VDD_ALIVE";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ /* SCP uses 1.5v, POP uses 1.2v */
+ ldo2_reg: LDO2 {
+ regulator-name = "VDDQ_M12";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "VDDIOAP_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "VDDQ_PRE";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "VDD_LDO5";
+ op_mode = <0>; /* Always off Mode */
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "VDD10_MPLL";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "VDD10_XPLL";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "VDD10_MIPI";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "VDD33_LCD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VDD18_MIPI";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "VDD18_ABB1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "VDD33_UOTG";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VDDIOPERI_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VDD18_ABB02";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VDD10_USH";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VDD18_HSIC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "VDDIOAP_MMC012_28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ /* Used by HSIC */
+ ldo18_reg: LDO18 {
+ regulator-name = "VDDIOPERI_28";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-name = "VDD_LDO19";
+ op_mode = <0>; /* Always off Mode */
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VDD28_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "VDD28_AF";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "VDDA28_2M";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-name = "VDD28_TF";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-name = "VDD33_A31";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-name = "VDD18_CAM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-name = "VDD18_A31";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo27_reg: LDO27 {
+ regulator-name = "GPS_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ ldo28_reg: LDO28 {
+ regulator-name = "DVDD12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1456250>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <875000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "vdd_m12";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "vdd12_5m";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "pvdd_buck7";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "pvdd_buck8";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ op_mode = <1>; /* Normal Mode */
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-name = "vddf28_emmc";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3000000>;
+ op_mode = <1>; /* Normal Mode */
+ };
+ };
+
+ s5m8767_osc: clocks {
+ #clock-cells = <1>;
+ clock-output-names = "s5m8767_ap",
+ "s5m8767_cp", "s5m8767_bt";
+ };
+
+ };
+};
+
+&mfc {
+ status = "okay";
+};
+
+&mshc_0 {
+ pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+ pinctrl-names = "default";
+ status = "okay";
+ vmmc-supply = <&buck9_reg>;
+ num-slots = <1>;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+};
+
+&pinctrl_1 {
+ hsic_reset: hsic-reset {
+ samsung,pins = "gpm2-4";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+};
+
+&rtc {
+ status = "okay";
+ clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
+};
+
+&tmu {
+ vtmu-supply = <&ldo16_reg>;
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v8 0/2] Add a new board TOPEET iTOP for Exynos 4412
From: Randy Li @ 2016-09-19 15:48 UTC (permalink / raw)
To: linux-arm-kernel
Changelog:
- v8:
- add the missing LDOs for PMIC, the pins for LDOs are not avaiabled in core
board.
- re-order the header files in core board.
- skip the vendor prefix file
- v7:
- add a missing header file
- add a rootdelay to bootargs or it can't mount root filesystem
- fix the memory node
- v6:
- move pwms pinctrl to pwms node
- fix the order of the dtb file in Makefile
- v5:
- correct the mail format
- v4:
- re-order some nodes in alphabetical order
- fix some minor bugs
- add a entry in vendor list
- v3:
- fixing the rtc clock, using clock source from PMIC
- enable the tmu
- enable the fimc for elite board
- suuport the audio codec at elite board, but the audio sound a little
distortion
- fixing minor bugs in the last commit
- v2:
- removing rtc node
the clock source driver is not done yet.
- adding exynos-bus
- fixing the MFC
Randy Li (2):
ARM: dts: Add TOPEET itop core board SCP package version
ARM: dts: add TOPEET itop elite based board
.../bindings/arm/samsung/samsung-boards.txt | 3 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos4412-itop-elite.dts | 240 ++++++++++
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 501 +++++++++++++++++++++
4 files changed, 745 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos4412-itop-elite.dts
create mode 100644 arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
--
2.7.4
^ permalink raw reply
* [GIT PULL 3/3] ARM: dts: exynos: pinctrl cleanup for v4.9
From: Arnd Bergmann @ 2016-09-19 15:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474216788-17282-4-git-send-email-krzk@kernel.org>
On Sunday, September 18, 2016 6:39:48 PM CEST Krzysztof Kozlowski wrote:
> Topic branch for Samsung DeviceTree cleanup for 4.9.
>
> Replace in DT sources hard-coded values for pinctrl configuration like pull
> up/down, drive strength and function. This makes the DTS easier to read,
> especially that some drive strengths values are quite non-obvious.
>
>
Pulled into next/dt, thanks!
Arnd
^ permalink raw reply
* [GIT PULL 2/3] ARM: dts: exynos: DT for v4.9, second round
From: Arnd Bergmann @ 2016-09-19 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474216788-17282-3-git-send-email-krzk@kernel.org>
On Sunday, September 18, 2016 6:39:47 PM CEST Krzysztof Kozlowski wrote:
> Samsung DeviceTree update for v4.9, second round:
> 1. Enable HDMI on Arndale Octa board.
> 2. Update list of clocks for FIMC-IS block on Exynos4x12.
> 3. Remove skeleton.dtsi thus fixing DT compiler warning:
> "Node /memory has a reg or ranges property, but no unit name"
> This is a tree-wide effort by various people. Javier Martinez Canillas did
> it for Exynos and S5PV210.
>
Pulled into next/dt, thanks!
Arnd
^ permalink raw reply
* [PATCH V6 4/5] PCI: thunder: Enable ACPI PCI controller for ThunderX pass2.x silicon version
From: Bjorn Helgaas @ 2016-09-19 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473449047-10499-5-git-send-email-tn@semihalf.com>
On Fri, Sep 09, 2016 at 09:24:06PM +0200, Tomasz Nowicki wrote:
> ThunderX PCIe controller to off-chip devices (so-called PEM) is not fully
> compliant with ECAM standard. It uses non-standard configuration space
> accessors (see pci_thunder_pem_ops) and custom configuration space granulation
> (see bus_shift = 24). In order to access configuration space and
> probe PEM as ACPI based PCI host controller we need to add MCFG quirk
> infrastructure. This involves:
> 1. Export PEM pci_thunder_pem_ops structure so it is visible to MCFG quirk
> code.
> 2. New quirk entries for each PEM segment. Each contains platform IDs,
> mentioned pci_thunder_pem_ops and CFG resources.
>
> Quirk is considered for ThunderX silicon pass2.x only which is identified
> via MCFG revision 1.
Is it really the case that silicon pass2.x has MCFG revision 1, and
silicon pass1.x has MCFG revision 2? That just seems backwards.
> Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
> ---
> drivers/acpi/pci_mcfg.c | 27 +++++++++++++++++++++++++++
> drivers/pci/host/pci-thunder-pem.c | 2 +-
> include/linux/pci-ecam.h | 4 ++++
> 3 files changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> index 2b8acc7..1f73d7b 100644
> --- a/drivers/acpi/pci_mcfg.c
> +++ b/drivers/acpi/pci_mcfg.c
> @@ -51,6 +51,33 @@ struct mcfg_fixup {
>
> static struct mcfg_fixup mcfg_quirks[] = {
> /* { OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
> +#ifdef CONFIG_PCI_HOST_THUNDER_PEM
> + /* SoC pass2.x */
> + { "CAVIUM", "THUNDERX", 1, 4, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x88001f000000UL, 0x39 * SZ_16M) },
> + { "CAVIUM", "THUNDERX", 1, 5, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x884057000000UL, 0x39 * SZ_16M) },
> + { "CAVIUM", "THUNDERX", 1, 6, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x88808f000000UL, 0x39 * SZ_16M) },
> + { "CAVIUM", "THUNDERX", 1, 7, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x89001f000000UL, 0x39 * SZ_16M) },
> + { "CAVIUM", "THUNDERX", 1, 8, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x894057000000UL, 0x39 * SZ_16M) },
> + { "CAVIUM", "THUNDERX", 1, 9, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x89808f000000UL, 0x39 * SZ_16M) },
> + { "CAVIUM", "THUNDERX", 1, 14, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x98001f000000UL, 0x39 * SZ_16M) },
> + { "CAVIUM", "THUNDERX", 1, 15, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x984057000000UL, 0x39 * SZ_16M) },
> + { "CAVIUM", "THUNDERX", 1, 16, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x98808f000000UL, 0x39 * SZ_16M) },
> + { "CAVIUM", "THUNDERX", 1, 17, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x99001f000000UL, 0x39 * SZ_16M) },
> + { "CAVIUM", "THUNDERX", 1, 18, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x994057000000UL, 0x39 * SZ_16M) },
> + { "CAVIUM", "THUNDERX", 1, 19, MCFG_BUS_ANY, &pci_thunder_pem_ops,
> + DEFINE_RES_MEM(0x99808f000000UL, 0x39 * SZ_16M) },
> +#endif
> };
>
> static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
> diff --git a/drivers/pci/host/pci-thunder-pem.c b/drivers/pci/host/pci-thunder-pem.c
> index b048761..d7c10cc 100644
> --- a/drivers/pci/host/pci-thunder-pem.c
> +++ b/drivers/pci/host/pci-thunder-pem.c
> @@ -367,7 +367,7 @@ static int thunder_pem_init(struct pci_config_window *cfg)
> return 0;
> }
>
> -static struct pci_ecam_ops pci_thunder_pem_ops = {
> +struct pci_ecam_ops pci_thunder_pem_ops = {
> .bus_shift = 24,
> .init = thunder_pem_init,
> .pci_ops = {
> diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
> index 7adad20..65505ea 100644
> --- a/include/linux/pci-ecam.h
> +++ b/include/linux/pci-ecam.h
> @@ -58,6 +58,10 @@ void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
> int where);
> /* default ECAM ops */
> extern struct pci_ecam_ops pci_generic_ecam_ops;
> +/* ECAM ops for known quirks */
> +#ifdef CONFIG_PCI_HOST_THUNDER_PEM
> +extern struct pci_ecam_ops pci_thunder_pem_ops;
> +#endif
>
> #ifdef CONFIG_PCI_HOST_GENERIC
> /* for DT-based PCI controllers that support ECAM */
> --
> 1.9.1
>
^ permalink raw reply
* [GIT PULL] omap dts updates for v4.9 merge window, part 2
From: Arnd Bergmann @ 2016-09-19 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160915172021.6u2zam4yd6vruub4@atomide.com>
On Thursday, September 15, 2016 10:20:22 AM CEST Tony Lindgren wrote:
> Part two of device tree changes for omaps for v4.9 merge window. This
> is mostly usability and non-critical fixes except for the addition of
> beagleboard-x15 rev B1 support:
>
> - Fix omap4 pandaboard SDIO WLAN latencies in idle mode by enabling wakeirq
>
> - Usability fixes for WLAN, USB, LEDs and power button on omap5 boards
>
> - Remove am57xx beagleboard-x15 pinmux configuration as the processor requires
> that it's done in IO isolation in bootloader except for MMC and DCAN
>
> - Add support for beagleboard-x15 rev B1 by moving most of the
> configuration to am57xx-beagle-x15-common.dtsi
>
> - Enable support for more than 2GB of memory for omap5 with LPAE with
> #address-cells
>
> - Fix omap3-gta04 backlight PWM frequency until the PWM driver
>
> - Revert am335x dts changes related to cpufreq as the driver changes
> still have not merged and the dts changes broke cpufreq
Pulled into next/dt, thanks!
Arnd
^ permalink raw reply
* [GIT PULL] DaVinci DTS updates for v4.9 (part 2)
From: Arnd Bergmann @ 2016-09-19 15:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d231c316-a14b-1534-2bcd-29f0898b0b1c@ti.com>
On Thursday, September 15, 2016 8:14:22 PM CEST Sekhar Nori wrote:
> This pull request adds NAND support to
> DA850 based LCDK board.
>
>
Pulled into next/dt, thanks!
Arnd
^ permalink raw reply
* [GIT PULL] STi DT update for v4.9, round 3
From: Arnd Bergmann @ 2016-09-19 15:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e51819f2-a354-7153-3b86-a92e99b85213@st.com>
On Friday, September 16, 2016 9:55:01 AM CEST Patrice Chotard wrote:
> Clock improvement for video playback
>
> This serie allows to increase video resolutions and make audio
> adjustment during a video playback for STiH407 family socs.
>
Pulled into next/dt, thanks!
Arnd
^ permalink raw reply
* [PATCH 4/4] drm/sun4i: dotclock: Round to closest clock rate
From: Chen-Yu Tsai @ 2016-09-19 15:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160918191648.GJ17518@lukather>
On Mon, Sep 19, 2016 at 3:16 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Thu, Sep 15, 2016 at 11:14:02PM +0800, Chen-Yu Tsai wrote:
>> With display pixel clocks we want to have the closest possible clock
>> rate, to minimize timing and refresh rate skews. Whether the actual
>> clock rate is higher or lower than the requested rate is less important.
>>
>> Also check candidates against the requested rate, rather than the
>> ideal parent rate, the varying dividers also influence the difference
>> between the requested rate and the rounded rate.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>> drivers/gpu/drm/sun4i/sun4i_dotclock.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
>> index 3eb99784f371..d401156490f3 100644
>> --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
>> +++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
>> @@ -90,7 +90,8 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
>> goto out;
>> }
>>
>> - if ((rounded < ideal) && (rounded > best_parent)) {
>> + if (abs(rate - rounded / i) <
>> + abs(rate - best_parent / best_div)) {
>
> I'm not sure what you're trying to do here. Why is the divider involved?
Say you want the dotclock at X, so you try Y = 6 ~ 127 for the divider.
Now you're asking the CCF to round (X*Y).
In the original code, you were comparing the result of rounding (X * Y).
if ((rounded < ideal) && (rounded > best_parent)) {
best_parent = rounded;
best_div = i;
}
where ideal = X * Y (i in the code). Given the divider increases in
the loop, you are actually not closing in on the best divider, but the
highest divider that doesn't give a higher rate than the ideal rate.
Including the divider makes it compare the actual dot clock frequency
if a given divider was used.
Does this makes sense? Explaining this kind of makes my head spin...
Regards
ChenYu
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
^ permalink raw reply
* [GIT PULL] STi DT update for v4.9
From: Arnd Bergmann @ 2016-09-19 15:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ede2d2b6-7e0c-f31e-72bd-06aae5838327@st.com>
On Wednesday, September 14, 2016 3:15:22 PM CEST Patrice Chotard wrote:
> STi dts update:
>
> Update gpio-cells and gpio specifier for STiH415/416
> Add PWM capture support for STiH416 and STiH407 family
> Add USB3 support for B2260
> Add HVA support for STiH410
> Add clk_ignore_unused in bootargs of B2260
> Add Flexible Direct Memory Access (FDMA) support for STiH407 family
> Add internal audio codec IP spport for STiH407 family
> Add uniperif player/reader IP blocks for STiH407 family
>
>
Pulled into next/dt, thanks!
Arnd
^ permalink raw reply
* [GIT PULL] Amlogic DT updates for v4.9
From: Arnd Bergmann @ 2016-09-19 15:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7h1t0mmk3o.fsf@baylibre.com>
On Wednesday, September 14, 2016 11:06:51 AM CEST Kevin Hilman wrote:
> Amlogic DT updates for v4.9
> - add PWM support
>
Pulled into next/dt, thanks!
Arnd
^ permalink raw reply
* next-20160914 build: 2 failures 3 warnings (next-20160914)
From: Grygorii Strashko @ 2016-09-19 15:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474883226.Je8NqnULCh@wuerfel>
On 09/19/2016 02:30 PM, Arnd Bergmann wrote:
> On Monday, September 19, 2016 11:54:29 AM CEST Mark Brown wrote:
>> On Mon, Sep 19, 2016 at 12:31:04PM +0200, Arnd Bergmann wrote:
>>
>>> My guess is that this is indeed the correct fix, but I don't understand
>>> at all what the function does, and Marcin Niestroj said the same thing,
>>> he just copied the code from a driver that is always built-in.
>>
>> Yes, most of the code is copied from regmap-irq. Setting the parent is
>> needed for edge triggered interrupts that don't latch state when
>> disabled but isn't needed in the general case.
>
> I found this in the tps65217 data sheet:
>
> 9.3.7 Interrupt Pin (nINT)
> The interrupt pin is used to signal any event or fault
> condition to the host processor. Whenever a fault or event
> occurs in the IC the corresponding interrupt bit is set in
> the INT register, and the open-drain output is pulled low.
> The nINT pin is released (returns to Hi-Z state) and fault
> bits are cleared when the INT register is read by the
> host. However, if a failure persists, the corresponding
> INT bit remains set and the nINT pin is pulled low again
> after a maximum of 32 ?s.
>
> Interrupt events include pushbutton pressed/released, USB
> and AC voltage status change.
> The MASK bits in the INT register are used to mask events
> from generating interrupts. The MASK settings affect the
> nINT pin only and have no impact on protection and
> monitor circuits themselves. Note that persisting event
> conditions such as ISINK enabled shutdown can cause the
> nINT pin to be pulled low for an extended period of
> time which can keep the host in a loop trying to resolve
> the interrupt. If this behavior is not desired, set the
> corresponding mask bit after receiving the interrupt and
> keep polling the INT register to see when the event
> condition has disappeared. Then unmask the interrupt bit
> again.
>
> Does this tell us if it's needed or not?
>
The irq_set_parent() is required for proper supporting of lazy irq disabling
for threaded nested irqs and allow them to be re-triggered in the following case:
driverX:
disable(nested_irq);
...
parent irq triggered
|- handle_nested_irq()
|- mark nested_irq with IRQS_PENDING
...
driverX:
enable(nested_irq);
|- if IRQS_PENDING -> resend parent_irq [*], because nested threaded irq can't
be resend by itself
[*] if parent_irq is not set the IRQS_PENDING status will be ignored and irq might be lost.
Also, it was "mandatory" to be done before commit 75a06189fc5
"genirq: Prevent resend to interrupts marked IRQ_NESTED_THREAD"
which made setting of parent_irq optional.
So, if is it required or not depends not only on HW, but, rather, on MFD drivers implementation
(Interrupt controller and MFD cell drivers).
--
regards,
-grygorii
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt for v4.9 (#2)
From: Arnd Bergmann @ 2016-09-19 15:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87eg4mbiqn.fsf@free-electrons.com>
On Wednesday, September 14, 2016 5:31:44 PM CEST Gregory CLEMENT wrote:
> mvebu dt for 4.9 (part 2)
>
> - convert orion5x based SoC Netgear WNR854T to devicetree
> - remove obsolete orion-gpio binding description
>
>
Pulled into next/dt, thanks!
Arnd
^ permalink raw reply
* [GIT PULL] ARM: at91: dt for 4.9
From: Arnd Bergmann @ 2016-09-19 15:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160914082812.tmlrrqwkeudcybui@piout.net>
On Wednesday, September 14, 2016 10:28:12 AM CEST Alexandre Belloni wrote:
> DT Changes for 4.9:
> - add ETM and ETB nodes on sama5d2
>
Pulled into next/dt, thanks!
Arnd
^ permalink raw reply
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