* [PATCH 4/4] ARM: sa11x0/pxa: get rid of get_clock_tick_rate
From: Daniel Lezcano @ 2016-09-19 19:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474312335-20997-5-git-send-email-robert.jarzmik@free.fr>
On 19/09/2016 21:12, Robert Jarzmik wrote:
> The last user of this function is gone, so remove it. The clock API
> should now be used to get clock rates.
>
> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
> ---
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [RFC PATCH] PCI/ACPI: xgene: Add ECAM quirk for X-Gene PCIe controller
From: Bjorn Helgaas @ 2016-09-19 20:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474122278-32525-1-git-send-email-dhdang@apm.com>
Hi Duc,
On Sat, Sep 17, 2016 at 07:24:38AM -0700, Duc Dang wrote:
> PCIe controller in X-Gene SoCs is not ECAM compliant: software
> needs to configure additional concontroller register to address
> device at bus:dev:function.
>
> This patch depends on "ECAM quirks handling for ARM64 platforms"
> series (http://www.spinics.net/lists/arm-kernel/msg530692.html)
> to address the limitation above for X-Gene PCIe controller.
>
> The quirk will only be applied for X-Gene PCIe MCFG table with
> OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs).
>
> Signed-off-by: Duc Dang <dhdang@apm.com>
> ---
> drivers/acpi/pci_mcfg.c | 32 +++++
> drivers/pci/host/Makefile | 2 +-
> drivers/pci/host/pci-xgene-ecam.c | 280 ++++++++++++++++++++++++++++++++++++++
> include/linux/pci-ecam.h | 5 +
> 4 files changed, 318 insertions(+), 1 deletion(-)
> create mode 100644 drivers/pci/host/pci-xgene-ecam.c
This adds a bunch of stuff, but doesn't remove anything. So I assume
it's adding new functionality that didn't exist before. What is it?
I sort of expected this to also remove, for example, the seemingly
identical xgene_pcie_config_read32() in drivers/pci/host/pci-xgene.c.
Actually, a bunch of this code seems to be duplicated from there. It
doesn't seem like we should end up with all this duplicated code.
I'd really like it better if all this could get folded into
pci-xgene.c so we don't end up with more files.
> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> index ddf338b..adce35f 100644
> --- a/drivers/acpi/pci_mcfg.c
> +++ b/drivers/acpi/pci_mcfg.c
> @@ -123,6 +123,38 @@ static struct mcfg_fixup mcfg_quirks[] = {
> { "CAVIUM", "THUNDERX", 2, 13, MCFG_BUS_ANY, &pci_thunder_ecam_ops,
> MCFG_RES_EMPTY},
> #endif
> +#ifdef CONFIG_PCI_XGENE
> + {"APM ", "XGENE ", 1, 0, MCFG_BUS_ANY,
> + &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 1, 1, MCFG_BUS_ANY,
> + &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 1, 2, MCFG_BUS_ANY,
> + &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 1, 3, MCFG_BUS_ANY,
> + &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 1, 4, MCFG_BUS_ANY,
> + &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 2, 0, MCFG_BUS_ANY,
> + &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 2, 1, MCFG_BUS_ANY,
> + &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 2, 2, MCFG_BUS_ANY,
> + &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 2, 3, MCFG_BUS_ANY,
> + &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 2, 4, MCFG_BUS_ANY,
> + &xgene_v1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 3, 0, MCFG_BUS_ANY,
> + &xgene_v2_1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 3, 1, MCFG_BUS_ANY,
> + &xgene_v2_1_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 4, 0, MCFG_BUS_ANY,
> + &xgene_v2_2_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 4, 1, MCFG_BUS_ANY,
> + &xgene_v2_2_pcie_ecam_ops, MCFG_RES_EMPTY},
> + {"APM ", "XGENE ", 4, 2, MCFG_BUS_ANY,
> + &xgene_v2_2_pcie_ecam_ops, MCFG_RES_EMPTY},
Most of these are the same. Let's add a macro that fills in the
boilerplate so each entry only contains the variable parts. I'm going
to propose the same for the ThunderX quirks.
> +#endif
> };
>
> static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index 8843410..af4f505 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -15,7 +15,7 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
> obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
> obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
> obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
> -obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
> +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o pci-xgene-ecam.o
> obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
> obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
> diff --git a/drivers/pci/host/pci-xgene-ecam.c b/drivers/pci/host/pci-xgene-ecam.c
> new file mode 100644
> index 0000000..b66a04f
> --- /dev/null
> +++ b/drivers/pci/host/pci-xgene-ecam.c
> @@ -0,0 +1,280 @@
> +/*
> + * APM X-Gene PCIe ECAM fixup driver
> + *
> + * Copyright (c) 2016, Applied Micro Circuits Corporation
> + * Author:
> + * Duc Dang <dhdang@apm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_pci.h>
> +#include <linux/pci-acpi.h>
> +#include <linux/platform_device.h>
> +#include <linux/pci-ecam.h>
> +
> +#ifdef CONFIG_ACPI
> +#define RTDID 0x160
> +#define ROOT_CAP_AND_CTRL 0x5C
> +
> +/* PCIe IP version */
> +#define XGENE_PCIE_IP_VER_UNKN 0
> +#define XGENE_PCIE_IP_VER_1 1
> +#define XGENE_PCIE_IP_VER_2 2
We only use XGENE_PCIE_IP_VER_1, so I think the others should be
removed. I think it would be nicer to have a "crs_broken:1" bit set
by the probe path, and get rid of the version field altogether.
> +#define XGENE_CSR_LENGTH 0x10000
> +
> +struct xgene_pcie_acpi_root {
> + void __iomem *csr_base;
> + u32 version;
> +};
I think this should be folded into struct xgene_pcie_port so we don't
have to allocate and manage it separately.
> +static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
> +{
> + struct xgene_pcie_acpi_root *xgene_root;
> + struct device *dev = cfg->parent;
> + u32 csr_base;
> +
> + xgene_root = devm_kzalloc(dev, sizeof(*xgene_root), GFP_KERNEL);
> + if (!xgene_root)
> + return -ENOMEM;
> +
> + switch (cfg->res.start) {
> + case 0xE0D0000000ULL:
> + csr_base = 0x1F2B0000;
> + break;
> + case 0xD0D0000000ULL:
> + csr_base = 0x1F2C0000;
> + break;
> + case 0x90D0000000ULL:
> + csr_base = 0x1F2D0000;
> + break;
> + case 0xA0D0000000ULL:
> + csr_base = 0x1F500000;
> + break;
> + case 0xC0D0000000ULL:
> + csr_base = 0x1F510000;
> + break;
Ugh. What in the world is going on here? Apparently we're testing a
host bridge resource against this hard-coded list of random values,
and based on that, we know about this *other* list of hard-coded CSR
ranges? This is not the way resource discovery normally works ;)
> + default:
> + return -ENODEV;
> + }
> +
> + xgene_root->csr_base = ioremap(csr_base, XGENE_CSR_LENGTH);
There should be a request_region() somewhere, too. Ideal would be to
use devm_ioremap_resource(), but I don't know where this apparent
resource is coming from.
> + if (!xgene_root->csr_base) {
> + kfree(xgene_root);
> + return -ENODEV;
> + }
> +
> + xgene_root->version = XGENE_PCIE_IP_VER_1;
> +
> + cfg->priv = xgene_root;
> +
> + return 0;
> +}
> +
> +static int xgene_v2_1_pcie_ecam_init(struct pci_config_window *cfg)
> +{
> + struct xgene_pcie_acpi_root *xgene_root;
> + struct device *dev = cfg->parent;
> + resource_size_t csr_base;
> +
> + xgene_root = devm_kzalloc(dev, sizeof(*xgene_root), GFP_KERNEL);
> + if (!xgene_root)
> + return -ENOMEM;
> +
> + switch (cfg->res.start) {
> + case 0xC0D0000000ULL:
> + csr_base = 0x1F2B0000;
> + break;
> + case 0xA0D0000000ULL:
> + csr_base = 0x1F2C0000;
> + break;
> + default:
> + return -ENODEV;
> + }
> +
> + xgene_root->csr_base = ioremap(csr_base, XGENE_CSR_LENGTH);
> + if (!xgene_root->csr_base) {
> + kfree(xgene_root);
> + return -ENODEV;
> + }
> +
> + xgene_root->version = XGENE_PCIE_IP_VER_2;
> +
> + cfg->priv = xgene_root;
> +
> + return 0;
> +}
> +
> +static int xgene_v2_2_pcie_ecam_init(struct pci_config_window *cfg)
> +{
> + struct xgene_pcie_acpi_root *xgene_root;
> + struct device *dev = cfg->parent;
> + resource_size_t csr_base;
> +
> + xgene_root = devm_kzalloc(dev, sizeof(*xgene_root), GFP_KERNEL);
> + if (!xgene_root)
> + return -ENOMEM;
> +
> + switch (cfg->res.start) {
> + case 0xE0D0000000ULL:
> + csr_base = 0x1F2B0000;
> + break;
> + case 0xA0D0000000ULL:
> + csr_base = 0x1F500000;
> + break;
> + case 0x90D0000000ULL:
> + csr_base = 0x1F2D0000;
> + break;
> + default:
> + return -ENODEV;
> + }
> +
> + xgene_root->csr_base = ioremap(csr_base, XGENE_CSR_LENGTH);
> + if (!xgene_root->csr_base) {
> + kfree(xgene_root);
> + return -ENODEV;
> + }
> +
> + xgene_root->version = XGENE_PCIE_IP_VER_2;
> +
> + cfg->priv = xgene_root;
> +
> + return 0;
> +}
> +/*
> + * For Configuration request, RTDID register is used as Bus Number,
> + * Device Number and Function number of the header fields.
> + */
> +static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
> +{
> + struct pci_config_window *cfg = bus->sysdata;
> + struct xgene_pcie_acpi_root *port = cfg->priv;
> + unsigned int b, d, f;
> + u32 rtdid_val = 0;
> +
> + b = bus->number;
> + d = PCI_SLOT(devfn);
> + f = PCI_FUNC(devfn);
> +
> + if (!pci_is_root_bus(bus))
> + rtdid_val = (b << 8) | (d << 3) | f;
> +
> + writel(rtdid_val, port->csr_base + RTDID);
> + /* read the register back to ensure flush */
> + readl(port->csr_base + RTDID);
> +}
> +
> +/*
> + * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
> + * the translation from PCI bus to native BUS. Entire DDR region
> + * is mapped into PCIe space using these registers, so it can be
> + * reached by DMA from EP devices. The BAR0/1 of bridge should be
> + * hidden during enumeration to avoid the sizing and resource allocation
> + * by PCIe core.
> + */
> +static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
> +{
> + if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
> + (offset == PCI_BASE_ADDRESS_1)))
> + return true;
> +
> + return false;
> +}
> +
> +void __iomem *xgene_pcie_ecam_map_bus(struct pci_bus *bus,
> + unsigned int devfn, int where)
> +{
> + struct pci_config_window *cfg = bus->sysdata;
> + unsigned int busn = bus->number;
> + void __iomem *base;
> +
> + if (busn < cfg->busr.start || busn > cfg->busr.end)
> + return NULL;
> +
> + if ((pci_is_root_bus(bus) && devfn != 0) ||
> + xgene_pcie_hide_rc_bars(bus, where))
> + return NULL;
> +
> + xgene_pcie_set_rtdid_reg(bus, devfn);
> +
> + if (busn > cfg->busr.start)
> + base = cfg->win + (1 << cfg->ops->bus_shift);
> + else
> + base = cfg->win;
> +
> + return base + where;
> +}
> +
> +static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
> + int where, int size, u32 *val)
> +{
> + struct pci_config_window *cfg = bus->sysdata;
> + struct xgene_pcie_acpi_root *port = cfg->priv;
> +
> + if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
> + PCIBIOS_SUCCESSFUL)
> + return PCIBIOS_DEVICE_NOT_FOUND;
> +
> + /*
> + * The v1 controller has a bug in its Configuration Request
> + * Retry Status (CRS) logic: when CRS is enabled and we read the
> + * Vendor and Device ID of a non-existent device, the controller
> + * fabricates return data of 0xFFFF0001 ("device exists but is not
> + * ready") instead of 0xFFFFFFFF ("device does not exist"). This
> + * causes the PCI core to retry the read until it times out.
> + * Avoid this by not claiming to support CRS.
> + */
> + if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
> + ((where & ~0x3) == ROOT_CAP_AND_CTRL))
> + *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
> +
> + if (size <= 2)
> + *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> +struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
> + .bus_shift = 16,
> + .init = xgene_v1_pcie_ecam_init,
> + .pci_ops = {
> + .map_bus = xgene_pcie_ecam_map_bus,
> + .read = xgene_pcie_config_read32,
> + .write = pci_generic_config_write,
> + }
> +};
> +
> +struct pci_ecam_ops xgene_v2_1_pcie_ecam_ops = {
> + .bus_shift = 16,
> + .init = xgene_v2_1_pcie_ecam_init,
> + .pci_ops = {
> + .map_bus = xgene_pcie_ecam_map_bus,
> + .read = xgene_pcie_config_read32,
> + .write = pci_generic_config_write,
> + }
> +};
> +
> +struct pci_ecam_ops xgene_v2_2_pcie_ecam_ops = {
> + .bus_shift = 16,
> + .init = xgene_v2_2_pcie_ecam_init,
> + .pci_ops = {
> + .map_bus = xgene_pcie_ecam_map_bus,
> + .read = xgene_pcie_config_read32,
> + .write = pci_generic_config_write,
> + }
> +};
> +#endif
> diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
> index 35f0e81..40da3e7 100644
> --- a/include/linux/pci-ecam.h
> +++ b/include/linux/pci-ecam.h
> @@ -65,6 +65,11 @@ extern struct pci_ecam_ops pci_thunder_pem_ops;
> #ifdef CONFIG_PCI_HOST_THUNDER_ECAM
> extern struct pci_ecam_ops pci_thunder_ecam_ops;
> #endif
> +#ifdef CONFIG_PCI_XGENE
> +extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops;
> +extern struct pci_ecam_ops xgene_v2_1_pcie_ecam_ops;
> +extern struct pci_ecam_ops xgene_v2_2_pcie_ecam_ops;
> +#endif
>
> #ifdef CONFIG_PCI_HOST_GENERIC
> /* for DT-based PCI controllers that support ECAM */
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH 3/4] watchdog: sa11x0/pxa: get rid of get_clock_tick_rate
From: Guenter Roeck @ 2016-09-19 20:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474312335-20997-4-git-send-email-robert.jarzmik@free.fr>
On Mon, Sep 19, 2016 at 09:12:14PM +0200, Robert Jarzmik wrote:
> The OS timer rate used for the watchdog can now be fetched from the
> standard clock API. This will remove the last user of
> get_clock_tick_rate() in both pxa and sa11x0 architectures.
>
> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Did you test this ? Potential problem, if built into the kernel, could be that
the clocks might not be ready by the time the driver is instantiated. Unless
this is converted to a platform driver, it won't be able to handle a
-EPROBE_DEFER from the clock subsystem.
Guenter
> ---
> drivers/watchdog/sa1100_wdt.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c
> index e1d39a1e9628..8965e3f536c3 100644
> --- a/drivers/watchdog/sa1100_wdt.c
> +++ b/drivers/watchdog/sa1100_wdt.c
> @@ -22,6 +22,7 @@
>
> #include <linux/module.h>
> #include <linux/moduleparam.h>
> +#include <linux/clk.h>
> #include <linux/types.h>
> #include <linux/kernel.h>
> #include <linux/fs.h>
> @@ -155,12 +156,27 @@ static struct miscdevice sa1100dog_miscdev = {
> };
>
> static int margin __initdata = 60; /* (secs) Default is 1 minute */
> +static struct clk *clk;
>
> static int __init sa1100dog_init(void)
> {
> int ret;
>
> - oscr_freq = get_clock_tick_rate();
> + clk = clk_get(NULL, "OSTIMER0");
> + if (IS_ERR(clk)) {
> + pr_err("SA1100/PXA2xx Watchdog Timer: clock not found: %d\n",
> + (int) PTR_ERR(clk));
> + return PTR_ERR(clk);
> + }
> +
> + ret = clk_prepare_enable(clk);
> + if (ret) {
> + pr_err("SA1100/PXA2xx Watchdog Timer: clock failed to prepare+enable: %d\n",
> + ret);
> + goto err;
> + }
> +
> + oscr_freq = clk_get_rate(clk);
>
> /*
> * Read the reset status, and save it for later. If
> @@ -176,11 +192,17 @@ static int __init sa1100dog_init(void)
> pr_info("SA1100/PXA2xx Watchdog Timer: timer margin %d sec\n",
> margin);
> return ret;
> +err:
> + clk_disable_unprepare(clk);
> + clk_put(clk);
> + return ret;
> }
>
> static void __exit sa1100dog_exit(void)
> {
> misc_deregister(&sa1100dog_miscdev);
> + clk_disable_unprepare(clk);
> + clk_put(clk);
> }
>
> module_init(sa1100dog_init);
> --
> 2.1.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt64 for v4.9 (#2)
From: Arnd Bergmann @ 2016-09-19 20:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87d1k6bio7.fsf@free-electrons.com>
On Wednesday, September 14, 2016 5:33:12 PM CEST Gregory CLEMENT wrote:
> mvebu dt64 for 4.9 (part 2)
>
> - enable MSI for PCIe on Armada 7K/8K
>
Pulled into next/dt64, thanks!
Arnd
^ permalink raw reply
* [GIT PULL 2/2] arm64: X-Gene platforms DTS changes queued for 4.9
From: Arnd Bergmann @ 2016-09-19 20:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CADaLNDk7uP8Gv+YB6oJfLqyRgjVVY82jQoPrQMk6y8xXGokyUQ@mail.gmail.com>
On Friday, September 16, 2016 12:01:28 AM CEST Duc Dang wrote:
> This is the DTS changes for X-Gene platforms targeted for 4.9.
>
> The changes include:
> + X-Gene Soc PMU DTS entry from X-Gene PMU patch set of Tai Nguyen [1]
> + Follow up patch to enable DTS entry for SoC PMU on X-Gene v2
> + Correct PCIe legacy interrupt mode to level-active high
> + DTS entry for X-Gene hwmon (v4 acked by Guenter, DT binding document
> and driver is in linux-next now [2])
> + DTS entries for X-Gene v2 CPU clock from X-Gene PMD clock patch set
> (v3 already accepted by Stephen into clk-next [3])
>
>
Pulled into next/dt64, thanks!
Arnd
^ permalink raw reply
* [GIT PULL 2/3] ZTE arm64 device tree changes for 4.9
From: Arnd Bergmann @ 2016-09-19 20:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474008641-30859-2-git-send-email-shawnguo@kernel.org>
On Friday, September 16, 2016 2:50:40 PM CEST Shawn Guo wrote:
> ZTE arm64 device tree changes for 4.9:
> - Add initial DTS support for ZTE ZX296718 SoC and ZX296718 EVB board.
>
>
Pulled into next/dt64, thanks!
Arnd
^ permalink raw reply
* [GIT PULL 1/3] ZTE arm64 soc changes for 4.9
From: Arnd Bergmann @ 2016-09-19 20:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474008641-30859-1-git-send-email-shawnguo@kernel.org>
On Friday, September 16, 2016 2:50:39 PM CEST Shawn Guo wrote:
> ZTE arm64 SoC changes for 4.9:
> - Add a Kconfig option for ZTE ZX SoC family support
>
Pulled into next/arm64, thanks!
Arnd
^ permalink raw reply
* [GIT PULL 3/3] ZTE arm64 defconfig changes for 4.9
From: Arnd Bergmann @ 2016-09-19 20:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474008641-30859-3-git-send-email-shawnguo@kernel.org>
On Friday, September 16, 2016 2:50:41 PM CEST Shawn Guo wrote:
> ZTE arm64 defconfig updates for 4.9:
> - Enable ZTE ZX family support in arm64 defconfig
>
Pulled into next/arm64, thanks!
Arnd
^ permalink raw reply
* [PATCH] cpufreq: ti: Use generic platdev driver
From: Dave Gerlach @ 2016-09-19 20:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4712275.44limO7TAi@vostro.rjw.lan>
On 09/16/2016 04:59 PM, Rafael J. Wysocki wrote:
> On Friday, September 16, 2016 04:29:04 PM Dave Gerlach wrote:
>> Hi,
>> On 09/15/2016 01:25 AM, Viresh Kumar wrote:
>>> On 14-09-16, 15:41, Dave Gerlach wrote:
>>>> Now that the cpufreq-dt-platdev is used to create the cpufreq-dt platform
>>>> device for all OMAP platforms and the platform code that did it
>>>> before has been removed, add ti,am33xx and ti,dra7xx to the machine list
>>>> in cpufreq-dt-platdev which had relied on the removed platform code to do
>>>> this previously.
>>>>
>>>> Fixes: 7694ca6e1d6f ("cpufreq: omap: Use generic platdev driver")
>>>> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
>>>
>>> Any stable trees you want this to be added to ?
>>
>> I suppose it'll go for 4.7-stable as the change happened in v4.6.
>
> The commit in the fixes tag went in during the 4.7 cycle, so the fix should
> go into 4.7.y, but I'm not going to push it as urgent material for 4.8.
>
Yes, that is fine, thanks a lot!
Regards,
Dave
> Thanks,
> Rafael
>
^ permalink raw reply
* [PATCH] arm: dts: fix rk3066a based boards vdd_log voltage initialization
From: Boris Brezillon @ 2016-09-19 20:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAD=FV=U_BQez2eCqm7mX9kj0dcEsnBKiFWcLAhXXJD+yTZhACw@mail.gmail.com>
On Mon, 19 Sep 2016 11:12:12 -0700
Doug Anderson <dianders@chromium.org> wrote:
> Hi,
>
> On Mon, Sep 19, 2016 at 11:06 AM, Boris Brezillon
> <boris.brezillon@free-electrons.com> wrote:
> > On Mon, 19 Sep 2016 10:52:51 -0700
> > Doug Anderson <dianders@chromium.org> wrote:
> >
> >> Hi,
> >>
> >> On Mon, Sep 19, 2016 at 10:48 AM, Boris Brezillon
> >> <boris.brezillon@free-electrons.com> wrote:
> >> > The PWM chip has always claimed the pins and muxed them to the PWM IP.
> >> > So, this means it's broken from the beginning, and my patch is only
> >> > uncovering the problem (unless the pins stay configured as input until
> >> > the PWM is enabled, which I'm not sure is the case).
> >>
> >> Such a solution is achievable with the pinctrl APIs pretty easily.
> >> You might not be able to use the automatic "init" state but you can do
> >> something similar and switch to an "active" state once the PWM is
> >> actually turned on the first time.
> >
> > But is it really the case here (I don't see any code requesting a
> > specific pinmux depending on the PWM state)?
>
> It is not happening right now as far as I know. ...but that's a bug.
>
> > Anyway, we really need to handle this case, we should define the
> > typical voltage when the PWM is disabled. Same as what you suggested
> > with voltage-when-input, but with a different naming (since the concept
> > of pinmux is PWM hardware/driver specific).
> >
> > voltage-when-pwm-disabled = <...>;
>
> Voltage when disabled and voltage when input are two different states.
> A disabled PWM will typically either drive high or low (depending on
> where it was when you turned it off). Not all "disabled" states will
> mean that the pin is configured as an input.
Okay, after reading again your first answer, I think I understand why
you want to differentiate the when-disabled and when-input cases. You
want to use the "init" and "default" pinctrl states. The "init" state
(applied at probe time) would keep the PWM pin in gpio+input mode and
the "default" state (applied when the PWM device is enabled for the
first time) would mux the pin to the PWM device.
Your solution requires that the pwm-regulator device knows in which
state the pin attached to the PWM is, which IMO is breaking the
layering we have right now: a PWM-regulator is assigned a PWM device
which is assigned a pin and a pinmux config.
Another solution would be to expose an additional information in the
pwm_state: whether the PWM is in the INIT state (probed, but not yet
configured by its user) or DEFAULT state (probed and already
configured by its user). But again, by doing that we also expose
internal PWM details to its user, which I'm not sure will help keep
the PWM API simple.
Actually, I had something slightly different in mind. I thought about
having two new pinctrl states ("enabled" and "disabled"). The "enabled"
state (pin muxed to the PWM device) would be applied each time the PWM
is enabled, and "disabled" state (gpio+input mode) would be applied each
time the PWM is disabled.
This way we can guarantee that even when the PWM is disabled, the
PWM-driven regulator is configured to output a non-destructive voltage.
Hence my suggestion to name the property 'voltage-when-pwm-disabled'.
^ permalink raw reply
* [PATCH v4 22/22] phy: Add support for Qualcomm's USB HS phy
From: Rob Herring @ 2016-09-19 21:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <147407072439.8245.12292695359399379462@sboyd-linaro>
On Fri, Sep 16, 2016 at 7:05 PM, Stephen Boyd <stephen.boyd@linaro.org> wrote:
> Quoting Rob Herring (2016-09-16 08:19:51)
>> On Wed, Sep 07, 2016 at 02:35:19PM -0700, Stephen Boyd wrote:
>> > The high-speed phy on qcom SoCs is controlled via the ULPI
>> > viewport.
>> >
[...]
>> > +- qcom,init-seq:
>> > + Usage: optional
>> > + Value type: <u8 array>
>> > + Definition: Should contain a sequence of ULPI register and address pairs to
>> > + program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related
>> > + to Device Mode Eye Diagram test.
>>
>> We generally nak this type of property. For 1 register I don't care so
>> much. For 100, that would be another story.
>>
>> Is this value per unit, per board, per SoC? Can you limit it to certain
>> registers?
>
> I'm told that this can be per board, depending on how it's wired from
> the phy pins to the usb port. Typically it's the same though for the
> boards I have, mostly because those boards are similar designs with
> respect to how USB is wired. The set of registers is not that many, 4 or
> 5 at most. My understanding is these are tuning registers. Right now the
> register part in the binding is the full register offset, and not an
> offset from ULPI_EXT_VENDOR_SPECIFIC (0x80). I could change this to be
> an offset from that area if you like so that this can't be abused to
> write into standard ULPI registers (there really isn't any way to
> enforce this in software though).
Okay, that sounds fine to me.
Rob
^ permalink raw reply
* [PATCH v2 1/2] Documentation: dt: add bindings for ti-cpufreq
From: Rob Herring @ 2016-09-19 21:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160901025328.376-2-d-gerlach@ti.com>
On Wed, Aug 31, 2016 at 09:53:27PM -0500, Dave Gerlach wrote:
> Add the device tree bindings document for the TI CPUFreq/OPP driver
> on AM33xx, AM43xx, DRA7, and AM57 SoCs. The operating-points-v2 binding
> allows us to provide an opp-supported-hw property for each OPP to define
> when it is available. This driver is responsible for reading and parsing
> registers to determine which OPPs can be selectively enabled based
> on the specific SoC in use by matching against the opp-supported-hw
> data.
Sorry, for the delay. Missed this somehow.
>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> ---
> v1->v2:
> - Dropped all driver/linux specific documentation
> - Fixed some typos
> - Add new compatibles for each SoC family to match against
> - Switched to use am335x example to better demonstrate field one of
> opp-supported-hw.
>
> .../devicetree/bindings/cpufreq/ti-cpufreq.txt | 130 +++++++++++++++++++++
> 1 file changed, 130 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
>
> diff --git a/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
> new file mode 100644
> index 000000000000..6276ae494121
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
> @@ -0,0 +1,130 @@
> +TI CPUFreq and OPP bindings
> +================================
> +
> +Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx
> +families support different OPPs depending on the silicon variant in use.
> +The ti_cpufreq driver can use revision and an efuse value from the SoC to
> +provide the OPP framework with supported hardware information. This is
> +used to determine which OPPs from the operating-points-v2 table get enabled
> +when it is parsed by the OPP framework.
> +
> +Required properties:
> +--------------------
> +In 'cpus' nodes:
> +- operating-points-v2: Phandle to the operating-points-v2 table to use.
> +- ti,syscon-efuse: Syscon phandle, offset to efuse register, efuse register
> + mask, and efuse register shift to get the relevant bits
> + that describe OPP availability.
> +- ti,syscon-rev: Syscon and offset used to look up revision value on SoC.
These have nothing to do with a cpu, so they don't belong here. Maybe
the first is a property of an OPP table, but the second certainly is
not.
> +
> +In 'operating-points-v2' table:
> +- compatible: Should be
> + - 'operating-points-v2-ti-am3352-cpu' for am335x SoCs
> + - 'operating-points-v2-ti-am4372-cpu' for am43xx SoCs
> + - 'operating-points-v2-ti-dra7-cpu' for dra7xx/am57xx SoCs
> +
> +- opp-supported-hw: Two bitfields indicating:
> + 1. Which revision of the SoC the OPP is supported by
> + 2. Which eFuse bits indicate this OPP is available
I tend to think you should handle this with kernel code (bootloader
really) fixing up the OPP table as necessary rather than putting in DT.
Rob
^ permalink raw reply
* [PATCH] coresight: tmc: implementing TMC-ETR AUX space API
From: Mathieu Poirier @ 2016-09-19 21:14 UTC (permalink / raw)
To: linux-arm-kernel
This patch implements the AUX area interfaces required to
use the TMC-ETR (configured to work in scatter-gather mode)
from the Perf sub-system.
Some of this work was inspired from the original implementation
done by Pratik Patel at CodeAurora.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 629 +++++++++++++++++++++++-
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
2 files changed, 621 insertions(+), 9 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 6d7de0309e94..581d6393bb5d 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -17,10 +17,60 @@
#include <linux/coresight.h>
#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+
#include "coresight-priv.h"
#include "coresight-tmc.h"
-void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
+/**
+ * struct etr_page - DMA'able and virtual address representation for a page
+ * @daddr: DMA'able page address returned by dma_map_page()
+ * @vaddr: Virtual address returned by page_address()
+ */
+struct etr_page {
+ dma_addr_t daddr;
+ u64 vaddr;
+};
+
+/**
+ * struct cs_etr_buffer - keep track of a recording session' specifics
+ * @dev: device reference to be used with the DMA API
+ * @tmc: generic portion of the TMC buffers
+ * @etr_nr_pages: number of memory pages for the ETR-SG trace storage
+ * @pt_vaddr: the virtual address of the first page table entry
+ * @page_addr: quick access to all the pages held in the page table
+ */
+struct cs_etr_buffers {
+ struct device *dev;
+ struct cs_buffers tmc;
+ unsigned int etr_nr_pages;
+ void __iomem *pt_vaddr;
+ struct etr_page page_addr[0];
+};
+
+#define TMC_ETR_ENTRIES_PER_PT (PAGE_SIZE / sizeof(u32))
+
+/*
+ * Helpers for scatter-gather descriptors. Descriptors are defined as follow:
+ *
+ * ---Bit31------------Bit4-------Bit1-----Bit0--
+ * | Address[39:12] | SBZ | Entry Type |
+ * ----------------------------------------------
+ *
+ * Address: Bits [39:12] of a physical page address. Bits [11:0] are
+ * always zero.
+ *
+ * Entry type: b10 - Normal entry
+ * b11 - Last entry in a page table
+ * b01 - Last entry
+ */
+#define TMC_ETR_SG_LST_ENT(phys_pte) (((phys_pte >> PAGE_SHIFT) << 4) | 0x1)
+#define TMC_ETR_SG_ENT(phys_pte) (((phys_pte >> PAGE_SHIFT) << 4) | 0x2)
+#define TMC_ETR_SG_NXT_TBL(phys_pte) (((phys_pte >> PAGE_SHIFT) << 4) | 0x3)
+
+#define TMC_ETR_SG_ENT_TO_PG(entry) ((entry >> 4) << PAGE_SHIFT)
+
+void tmc_etr_enable_hw_cnt_mem(struct tmc_drvdata *drvdata)
{
u32 axictl;
@@ -57,7 +107,47 @@ void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
-static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
+void tmc_etr_enable_hw_sg_mem(struct tmc_drvdata *drvdata)
+{
+ u32 axictl;
+
+ CS_UNLOCK(drvdata->base);
+
+ /* Wait for TMCSReady bit to be set */
+ tmc_wait_for_tmcready(drvdata);
+
+ writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
+
+ axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
+ /* half the write buffer depth */
+ axictl |= TMC_AXICTL_WR_BURST_08;
+ /* enable scatter-gather mode */
+ axictl |= TMC_AXICTL_SCT_GAT_MODE;
+ /* enable non-secure, priviledged access */
+ axictl |= (TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1);
+
+ writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
+
+ writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
+
+ /*
+ * DBAHI Holds the upper eight bits of the 40-bit address used to
+ * locate the trace buffer in system memory.
+ */
+ writel_relaxed((drvdata->paddr >> 32) & 0xFF,
+ drvdata->base + TMC_DBAHI);
+
+ writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
+ TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
+ TMC_FFCR_TRIGON_TRIGIN,
+ drvdata->base + TMC_FFCR);
+ writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
+ tmc_enable_hw(drvdata);
+
+ CS_LOCK(drvdata->base);
+}
+
+static void tmc_etr_dump_hw_cnt_mem(struct tmc_drvdata *drvdata)
{
u32 rwp, val;
@@ -87,7 +177,8 @@ static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
* read before the TMC is disabled.
*/
if (local_read(&drvdata->mode) == CS_MODE_SYSFS)
- tmc_etr_dump_hw(drvdata);
+ tmc_etr_dump_hw_cnt_mem(drvdata);
+
tmc_disable_hw(drvdata);
CS_LOCK(drvdata->base);
@@ -157,7 +248,7 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev, u32 mode)
memset(drvdata->vaddr, 0, drvdata->size);
- tmc_etr_enable_hw(drvdata);
+ tmc_etr_enable_hw_cnt_mem(drvdata);
out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
@@ -199,7 +290,7 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, u32 mode)
goto out;
}
- tmc_etr_enable_hw(drvdata);
+ tmc_etr_enable_hw_sg_mem(drvdata);
out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
@@ -241,9 +332,528 @@ static void tmc_disable_etr_sink(struct coresight_device *csdev)
dev_info(drvdata->dev, "TMC-ETR disabled\n");
}
+/*
+ * The default perf ring buffer size is 32 and 1024 pages for user and kernel
+ * space respectively. The size of the intermediate SG list is allowed
+ * to match the size of the perf ring buffer but cap it to the default
+ * kernel size.
+ */
+#define DEFAULT_NR_KERNEL_PAGES 1024
+static int tmc_get_etr_pages(int nr_pages)
+{
+ if (nr_pages <= DEFAULT_NR_KERNEL_PAGES)
+ return nr_pages;
+
+ return DEFAULT_NR_KERNEL_PAGES;
+}
+
+/*
+ * Go through all the pages in the SG list and check if @phys_addr
+ * falls within one of those. If so record the information in
+ * @page and @offset.
+ */
+static int
+tmc_get_sg_page_index(struct cs_etr_buffers *etr_buffer,
+ u64 phys_addr, u32 *page, u32 *offset)
+{
+ int i = 0, pte = 0, nr_pages = etr_buffer->etr_nr_pages;
+ u32 *page_table_itr = etr_buffer->pt_vaddr;
+ phys_addr_t phys_page_addr;
+
+ /* Circle through all the pages in the SG list */
+ while (pte < nr_pages) {
+ phys_page_addr = TMC_ETR_SG_ENT_TO_PG((u64)*page_table_itr);
+
+ /* Does @phys_addr falls within this page? */
+ if (phys_addr >= phys_page_addr &&
+ phys_addr < (phys_page_addr + PAGE_SIZE)) {
+ *page = pte;
+ *offset = phys_addr - phys_page_addr;
+ return 0;
+ }
+
+ if (pte == nr_pages - 1) {
+ /* The last page in the SG list */
+ pte++;
+ } else if (i == TMC_ETR_ENTRIES_PER_PT - 1) {
+ /*
+ * The last entry in this page table - get a reference
+ * on the next page table and do _not_ increment @pte
+ */
+ page_table_itr = phys_to_virt(phys_page_addr);
+ i = 0;
+ } else {
+ /* A normal page in the SG list */
+ page_table_itr++;
+ pte++;
+ i++;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static void tmc_sg_page_sync(struct cs_etr_buffers *etr_buffer,
+ int start_page, u64 to_sync)
+{
+ int i, index;
+ int pages_to_sync = DIV_ROUND_UP_ULL(to_sync, PAGE_SIZE);
+ dma_addr_t daddr;
+ struct device *dev = etr_buffer->dev;
+
+ for (i = start_page; i < (start_page + pages_to_sync); i++) {
+ /* Wrap around the etr page list if need be */
+ index = i % etr_buffer->etr_nr_pages;
+ daddr = etr_buffer->page_addr[index].daddr;
+ dma_sync_single_for_cpu(dev, daddr, PAGE_SIZE, DMA_FROM_DEVICE);
+ }
+}
+
+static void tmc_free_sg_buffer(struct cs_etr_buffers *etr_buffer, int nr_pages)
+{
+ int i = 0, pte = 0;
+ u32 *page_addr, *page_table_itr;
+ u32 *page_table_addr = etr_buffer->pt_vaddr;
+ phys_addr_t phys_page_addr;
+ dma_addr_t daddr;
+ struct device *dev = etr_buffer->dev;
+
+ if (!page_table_addr)
+ return;
+
+ page_table_itr = page_table_addr;
+ while (pte < nr_pages) {
+ phys_page_addr = TMC_ETR_SG_ENT_TO_PG((u64)*page_table_itr);
+ page_addr = phys_to_virt(phys_page_addr);
+
+ if (pte == nr_pages - 1) {
+ /* The last page in the SG list */
+ daddr = etr_buffer->page_addr[pte].daddr;
+ page_addr = (u32 *)etr_buffer->page_addr[pte].vaddr;
+
+ dma_unmap_page(dev, daddr, PAGE_SIZE,
+ DMA_FROM_DEVICE);
+
+ /* Free the current page */
+ free_page((unsigned long)page_addr);
+ /* Free the current page table */
+ free_page((unsigned long)page_table_addr);
+
+ pte++;
+ } else if (i == TMC_ETR_ENTRIES_PER_PT - 1) {
+ /* The last entry in this page table */
+ page_addr = phys_to_virt(phys_page_addr);
+
+ /* Free the current page table */
+ free_page((unsigned long)page_table_addr);
+ /* Move along to the next one */
+ page_table_addr = page_addr;
+ page_table_itr = page_table_addr;
+
+ i = 0;
+ } else {
+ /* A normal page in the SG list */
+ daddr = etr_buffer->page_addr[pte].daddr;
+ page_addr = (u32 *)etr_buffer->page_addr[pte].vaddr;
+
+ dma_unmap_page(dev, daddr, PAGE_SIZE,
+ DMA_FROM_DEVICE);
+
+ /* Free the current page */
+ free_page((unsigned long)page_addr);
+
+ page_table_itr++;
+ pte++;
+ i++;
+ }
+ }
+}
+
+static dma_addr_t tmc_setup_dma_page(struct device *dev, struct page *page)
+{
+ dma_addr_t daddr;
+
+ /*
+ * No data is communicated to the device, as such there is no point
+ * in setting the direction to DMA_BIDIRECTIONAL. See
+ * Documentation/DMA-API-HOWTO.txt for details.
+ */
+ daddr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
+ if (dma_mapping_error(dev, daddr)) {
+ __free_page(page);
+ return -EINVAL;
+ }
+
+ return daddr;
+}
+
+static int
+tmc_alloc_sg_buffer(struct cs_etr_buffers *etr_buffer, int cpu, int nr_pages)
+{
+ int i = 0, node, pte = 0, ret = 0;
+ dma_addr_t dma_page_addr;
+ u32 *page_table_addr, *page_addr;
+ struct page *page;
+ struct device *dev = etr_buffer->dev;
+
+ if (cpu == -1)
+ cpu = smp_processor_id();
+ node = cpu_to_node(cpu);
+
+ /* Allocate the first page table */
+ page = alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 0);
+ if (!page)
+ return -ENOMEM;
+
+ page_table_addr = page_address(page);
+ /*
+ * Keep track of the first page table, the rest will be chained
+ * in the last page table entry.
+ */
+ etr_buffer->pt_vaddr = page_table_addr;
+
+ while (pte < nr_pages) {
+ page = alloc_pages_node(node,
+ GFP_KERNEL | __GFP_ZERO, 0);
+ if (!page) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ page_addr = page_address(page);
+
+ if (pte == nr_pages - 1) {
+ /* The last page in the list */
+ dma_page_addr = tmc_setup_dma_page(dev, page);
+ if (dma_page_addr == -EINVAL) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ *page_table_addr = TMC_ETR_SG_LST_ENT(dma_page_addr);
+
+ etr_buffer->page_addr[pte].vaddr = (u64)page_addr;
+ etr_buffer->page_addr[pte].daddr = dma_page_addr;
+
+ pte++;
+ } else if (i == TMC_ETR_ENTRIES_PER_PT - 1) {
+ /* The last entry in this page table */
+ *page_table_addr =
+ TMC_ETR_SG_NXT_TBL(virt_to_phys(page_addr));
+ /* Move on to the next page table */
+ page_table_addr = page_addr;
+
+ i = 0;
+ } else {
+ /* A normal page in the SG list */
+ dma_page_addr = tmc_setup_dma_page(dev, page);
+ if (dma_page_addr == -EINVAL) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ *page_table_addr = TMC_ETR_SG_ENT(dma_page_addr);
+
+ etr_buffer->page_addr[pte].vaddr = (u64)page_addr;
+ etr_buffer->page_addr[pte].daddr = dma_page_addr;
+
+ page_table_addr++;
+ pte++;
+ i++;
+ }
+ }
+
+ return 0;
+
+err:
+ tmc_free_sg_buffer(etr_buffer, pte);
+ etr_buffer->pt_vaddr = NULL;
+ return ret;
+}
+
+static void *tmc_alloc_etr_buffer(struct coresight_device *csdev, int cpu,
+ void **pages, int nr_pages, bool overwrite)
+{
+ int etr_pages, node;
+ struct device *dev = csdev->dev.parent;
+ struct cs_etr_buffers *buf;
+
+ if (cpu == -1)
+ cpu = smp_processor_id();
+ node = cpu_to_node(cpu);
+
+ /* Register DBALO and DBAHI form a 40-bit address range */
+ if (dma_set_mask(dev, DMA_BIT_MASK(40)))
+ return NULL;
+
+ /*
+ * The HW can't start collecting data in the middle of the SG list,
+ * it must start at the beginning. As such we can't use the ring
+ * buffer provided by perf as entries into the page tables since
+ * it is not guaranteed that user space will have the chance to
+ * consume the data before the next trace run begins.
+ *
+ * To work around this reserve a set of pages that will be used as
+ * and intermediate (SG) buffer. This isn't optimal but the best we
+ * can do with the current HW revision.
+ */
+ etr_pages = tmc_get_etr_pages(nr_pages);
+
+ /* Allocate memory structure for interaction with Perf */
+ buf = kzalloc_node(offsetof(struct cs_etr_buffers,
+ page_addr[etr_pages]),
+ GFP_KERNEL, node);
+ if (!buf)
+ return NULL;
+
+ buf->dev = dev;
+
+ if (tmc_alloc_sg_buffer(buf, cpu, etr_pages)) {
+ kfree(buf);
+ return NULL;
+ }
+
+ buf->etr_nr_pages = etr_pages;
+ buf->tmc.snapshot = overwrite;
+ buf->tmc.nr_pages = nr_pages;
+ buf->tmc.data_pages = pages;
+
+ return buf;
+}
+
+static void tmc_free_etr_buffer(void *config)
+{
+ struct cs_etr_buffers *buf = config;
+
+ tmc_free_sg_buffer(buf, buf->etr_nr_pages);
+ kfree(buf);
+}
+
+static int tmc_set_etr_buffer(struct coresight_device *csdev,
+ struct perf_output_handle *handle,
+ void *sink_config)
+{
+ unsigned long head;
+ struct cs_etr_buffers *buf = sink_config;
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ /* wrap head around to the amount of space we have */
+ head = handle->head & ((buf->tmc.nr_pages << PAGE_SHIFT) - 1);
+
+ /* find the page to write to */
+ buf->tmc.cur = head / PAGE_SIZE;
+
+ /* and offset within that page */
+ buf->tmc.offset = head % PAGE_SIZE;
+
+ local_set(&buf->tmc.data_size, 0);
+
+ /* Keep track of how big the internal SG list is */
+ drvdata->size = buf->etr_nr_pages << PAGE_SHIFT;
+
+ /* Tell the HW where to put the trace data */
+ drvdata->paddr = virt_to_phys(buf->pt_vaddr);
+
+ return 0;
+}
+
+static unsigned long tmc_reset_etr_buffer(struct coresight_device *csdev,
+ struct perf_output_handle *handle,
+ void *sink_config, bool *lost)
+{
+ long size = 0;
+ struct cs_etr_buffers *buf = sink_config;
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ if (buf) {
+ /*
+ * In snapshot mode ->data_size holds the new address of the
+ * ring buffer's head. The size itself is the whole address
+ * range since we want the latest information.
+ */
+ if (buf->tmc.snapshot) {
+ size = buf->tmc.nr_pages << PAGE_SHIFT;
+ handle->head = local_xchg(&buf->tmc.data_size, size);
+ }
+
+ /*
+ * Tell the tracer PMU how much we got in this run and if
+ * something went wrong along the way. Nobody else can use
+ * this cs_etr_buffers instance until we are done. As such
+ * resetting parameters here and squaring off with the ring
+ * buffer API in the tracer PMU is fine.
+ */
+ *lost = !!local_xchg(&buf->tmc.lost, 0);
+ size = local_xchg(&buf->tmc.data_size, 0);
+ }
+
+ /* Get ready for another run */
+ drvdata->vaddr = NULL;
+ drvdata->paddr = 0;
+
+ return size;
+}
+
+static void tmc_update_etr_buffer(struct coresight_device *csdev,
+ struct perf_output_handle *handle,
+ void *sink_config)
+{
+ bool full;
+ int i, rb_index, sg_index = 0;
+ u32 rwplo, rwphi, rb_offset, sg_offset = 0;
+ u32 stop_index, stop_offset, to_copy, sg_size;
+ u32 *rb_ptr, *sg_ptr;
+ u64 rwp, to_read;
+ struct cs_etr_buffers *etr_buf = sink_config;
+ struct cs_buffers *cs_buf = &etr_buf->tmc;
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ if (!etr_buf)
+ return;
+
+ /* This shouldn't happen */
+ if (WARN_ON_ONCE(local_read(&drvdata->mode) != CS_MODE_PERF))
+ return;
+
+ CS_UNLOCK(drvdata->base);
+
+ tmc_flush_and_stop(drvdata);
+
+ rwplo = readl_relaxed(drvdata->base + TMC_RWP);
+ rwphi = readl_relaxed(drvdata->base + TMC_RWPHI);
+ full = (readl_relaxed(drvdata->base + TMC_STS) & TMC_STS_FULL);
+
+ /* Combine the high and low part of the rwp to make a full address */
+ rwp = (u64)rwphi << 32;
+ rwp |= rwplo;
+
+ /* Convert the stop address in RAM to a page and an offset */
+ if (tmc_get_sg_page_index(etr_buf, rwp, &stop_index, &stop_offset))
+ goto out;
+
+ if (full) {
+ /*
+ * The buffer head has wrapped around. As such the size
+ * is the entire buffer length and the index and offset in
+ * the scatter-gather list are moved forward.
+ */
+ local_inc(&cs_buf->lost);
+ to_read = drvdata->size;
+ sg_index = stop_index;
+ sg_offset = stop_offset;
+ } else {
+ to_read = (stop_index * PAGE_SIZE) + stop_offset;
+ }
+
+ /*
+ * The TMC RAM buffer may be bigger than the space available in the
+ * perf ring buffer (handle->size). If so advance the RRP so that we
+ * get the latest trace data.
+ */
+ if (to_read > handle->size) {
+ u64 rrp;
+
+ /*
+ * Compute where we should start reading from
+ * relative to rwp.
+ */
+ rrp = rwp + drvdata->size;
+ /* Go back just enough */
+ rrp -= handle->size;
+ /* Make sure we are still within our limits */
+ rrp %= drvdata->size;
+
+ /* Get a new index and offset based on rrp */
+ if (tmc_get_sg_page_index(etr_buf, rrp,
+ &stop_index, &stop_offset))
+ goto out;
+
+ /* Tell user space we lost data */
+ local_inc(&cs_buf->lost);
+ to_read = handle->size;
+ /* Adjust start index and offset */
+ sg_index = stop_index;
+ sg_offset = stop_offset;
+ }
+
+ /* Get a handle on where the Perf ring buffer is */
+ rb_index = cs_buf->cur;
+ rb_offset = cs_buf->offset;
+
+ /* Refresh the SG list */
+ tmc_sg_page_sync(etr_buf, sg_index, to_read);
+
+ for (i = to_read; i > 0; ) {
+ /* Get current location of the perf ring buffer */
+ rb_ptr = cs_buf->data_pages[rb_index] + rb_offset;
+ /* Get current location in the ETR SG list */
+ sg_ptr = (u32 *)(etr_buf->page_addr[sg_index].vaddr +
+ sg_offset);
+
+ /*
+ * First figure out the maximum amount of data we can get out
+ * of the ETR SG list.
+ */
+ if (i < PAGE_SIZE)
+ sg_size = i;
+ else
+ sg_size = PAGE_SIZE - sg_offset;
+
+ /*
+ * We have two page table buffer, one is the Perf ring
+ * buffer while the other one is the internal ETR SG list.
+ * Get the maximum amount of information we can copy from the
+ * ETR SG list to the Perf ring buffer, which happens to be
+ * the minimum space available in the current pages
+ * (both of them).
+ */
+ to_copy = min((u32)(PAGE_SIZE - rb_offset), sg_size);
+
+ /* Transfer trace data from ETR SG list to Perf ring buffer */
+ memcpy(rb_ptr, sg_ptr, to_copy);
+
+ rb_offset += to_copy;
+ sg_offset += to_copy;
+ i -= to_copy;
+
+ /* If a page is full, move to the next one */
+ if (rb_offset == PAGE_SIZE) {
+ rb_offset = 0;
+ rb_index++;
+ rb_index %= cs_buf->nr_pages;
+ }
+
+ if (sg_offset == PAGE_SIZE) {
+ sg_offset = 0;
+ sg_index++;
+ sg_index %= etr_buf->etr_nr_pages;
+ }
+ }
+
+ /*
+ * In snapshot mode all we have to do is communicate to
+ * perf_aux_output_end() the address of the current head. In full
+ * trace mode the same function expects a size to move rb->aux_head
+ * forward.
+ */
+ if (etr_buf->tmc.snapshot)
+ local_set(&etr_buf->tmc.data_size,
+ stop_index * PAGE_SIZE + stop_offset);
+ else
+ local_add(to_read, &etr_buf->tmc.data_size);
+
+out:
+ CS_LOCK(drvdata->base);
+}
+
static const struct coresight_ops_sink tmc_etr_sink_ops = {
.enable = tmc_enable_etr_sink,
.disable = tmc_disable_etr_sink,
+ .alloc_buffer = tmc_alloc_etr_buffer,
+ .free_buffer = tmc_free_etr_buffer,
+ .set_buffer = tmc_set_etr_buffer,
+ .reset_buffer = tmc_reset_etr_buffer,
+ .update_buffer = tmc_update_etr_buffer,
};
const struct coresight_ops tmc_etr_cs_ops = {
@@ -306,11 +916,12 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
/*
* The trace run will continue with the same allocated trace
- * buffer. The trace buffer is cleared in tmc_etr_enable_hw(),
- * so we don't have to explicitly clear it. Also, since the
- * tracer is still enabled drvdata::buf can't be NULL.
+ * buffer. The trace buffer is cleared in
+ * tmc_etr_enable_hw_cnt_mem(), so we don't have to explicitly
+ * clear it. Also, since the tracer is still enabled
+ * drvdata::buf can't be NULL.
*/
- tmc_etr_enable_hw(drvdata);
+ tmc_etr_enable_hw_cnt_mem(drvdata);
} else {
/*
* The ETR is not tracing and the buffer was just read.
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 44b3ae346118..05dc00d79732 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -59,6 +59,7 @@
#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
#define TMC_AXICTL_SCT_GAT_MODE BIT(7)
#define TMC_AXICTL_WR_BURST_16 0xF00
+#define TMC_AXICTL_WR_BURST_08 0x700
/* TMC_FFCR - 0x304 */
#define TMC_FFCR_FLUSHMAN_BIT 6
#define TMC_FFCR_EN_FMT BIT(0)
--
2.7.4
^ permalink raw reply related
* [PATCH] arm: dts: fix rk3066a based boards vdd_log voltage initialization
From: Doug Anderson @ 2016-09-19 21:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160919224352.3b84b6c0@bbrezillon>
Hi,
On Mon, Sep 19, 2016 at 1:43 PM, Boris Brezillon
<boris.brezillon@free-electrons.com> wrote:
> On Mon, 19 Sep 2016 11:12:12 -0700
> Doug Anderson <dianders@chromium.org> wrote:
>
>> Hi,
>>
>> On Mon, Sep 19, 2016 at 11:06 AM, Boris Brezillon
>> <boris.brezillon@free-electrons.com> wrote:
>> > On Mon, 19 Sep 2016 10:52:51 -0700
>> > Doug Anderson <dianders@chromium.org> wrote:
>> >
>> >> Hi,
>> >>
>> >> On Mon, Sep 19, 2016 at 10:48 AM, Boris Brezillon
>> >> <boris.brezillon@free-electrons.com> wrote:
>> >> > The PWM chip has always claimed the pins and muxed them to the PWM IP.
>> >> > So, this means it's broken from the beginning, and my patch is only
>> >> > uncovering the problem (unless the pins stay configured as input until
>> >> > the PWM is enabled, which I'm not sure is the case).
>> >>
>> >> Such a solution is achievable with the pinctrl APIs pretty easily.
>> >> You might not be able to use the automatic "init" state but you can do
>> >> something similar and switch to an "active" state once the PWM is
>> >> actually turned on the first time.
>> >
>> > But is it really the case here (I don't see any code requesting a
>> > specific pinmux depending on the PWM state)?
>>
>> It is not happening right now as far as I know. ...but that's a bug.
>>
>> > Anyway, we really need to handle this case, we should define the
>> > typical voltage when the PWM is disabled. Same as what you suggested
>> > with voltage-when-input, but with a different naming (since the concept
>> > of pinmux is PWM hardware/driver specific).
>> >
>> > voltage-when-pwm-disabled = <...>;
>>
>> Voltage when disabled and voltage when input are two different states.
>> A disabled PWM will typically either drive high or low (depending on
>> where it was when you turned it off). Not all "disabled" states will
>> mean that the pin is configured as an input.
>
> Okay, after reading again your first answer, I think I understand why
> you want to differentiate the when-disabled and when-input cases. You
> want to use the "init" and "default" pinctrl states. The "init" state
> (applied at probe time) would keep the PWM pin in gpio+input mode and
> the "default" state (applied when the PWM device is enabled for the
> first time) would mux the pin to the PWM device.
> Your solution requires that the pwm-regulator device knows in which
> state the pin attached to the PWM is, which IMO is breaking the
> layering we have right now: a PWM-regulator is assigned a PWM device
> which is assigned a pin and a pinmux config.
> Another solution would be to expose an additional information in the
> pwm_state: whether the PWM is in the INIT state (probed, but not yet
> configured by its user) or DEFAULT state (probed and already
> configured by its user). But again, by doing that we also expose
> internal PWM details to its user, which I'm not sure will help keep
> the PWM API simple.
One note is that probably using the "init" state would not be a good
idea because it would make assumptions about what state the firmware
left things. Possibly a firmware update could cause a change from a
PWM being left as "input" to the PWM actually being initted.
...really we should be able to detect if the PWM was left on at
bootup.
> Actually, I had something slightly different in mind. I thought about
> having two new pinctrl states ("enabled" and "disabled"). The "enabled"
> state (pin muxed to the PWM device) would be applied each time the PWM
> is enabled, and "disabled" state (gpio+input mode) would be applied each
> time the PWM is disabled.
Adding "enabled" and "disabled" state is sane IMHO. At the moment the
PWM regulator never actually puts things in "disabled" state, but I
suppose it could in the future.
> This way we can guarantee that even when the PWM is disabled, the
> PWM-driven regulator is configured to output a non-destructive voltage.
> Hence my suggestion to name the property 'voltage-when-pwm-disabled'.
That's fine with me, as long as the PWM starts up as "enabled" if the
pinctrl happened to be left initted by the BIOS.
-Doug
^ permalink raw reply
* [PATCH 3/3] dt-bindings: reset: oxnas: Update for OX820
From: Rob Herring @ 2016-09-19 21:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473428153.3023.34.camel@pengutronix.de>
On Fri, Sep 09, 2016 at 03:35:53PM +0200, Philipp Zabel wrote:
> Hi Neil,
>
> Am Freitag, den 09.09.2016, 15:19 +0200 schrieb Neil Armstrong:
> > Add new compatible string for reset and sys-ctrl for the Oxford
> > Semiconductor OX820 Support.
> > Drop the OX810SE indices since they moved in a dedicated include file.
>
> Not sure if the OX820 reset controller should be considered "compatible"
> to OX810SE. The register layout and usage is the same, but the reset
> indices are different. Does this warrant a new compatible string, or
> should this be
> compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset"?
Correct. Different connections are fine since the connections are
described in the DT. However you could have some connections not
described, so a new compatible may still be needed for that purpose (in
addition to other reasons you do a new compatible for new SoCs).
Rob
^ permalink raw reply
* [PATCH v5 1/9] Documentation: dt-bindings: Document STM32 EXTI controller bindings
From: Rob Herring @ 2016-09-19 21:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473432124-6784-2-git-send-email-alexandre.torgue@st.com>
On Fri, Sep 09, 2016 at 04:41:56PM +0200, Alexandre TORGUE wrote:
> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v15 5/5] ASoC: rockchip: Add DP dai-links to the rk3399-gru machine driver
From: Rob Herring @ 2016-09-19 21:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473473748-22331-6-git-send-email-zyw@rock-chips.com>
On Fri, Sep 09, 2016 at 07:15:48PM -0700, Chris Zhong wrote:
> This patch adds DP audio output support to the rk3399-gru machine
> driver.
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> ---
>
> Changes in v15: None
> Changes in v14: None
> Changes in v13: None
> Changes in v12: None
> Changes in v11: None
> Changes in v10: None
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3:
> - change spdif to i2s2
>
> Changes in v2:
> - correct the commit message
>
> Changes in v1: None
>
> .../bindings/sound/rockchip,rk3399-gru-sound.txt | 11 +--
> sound/soc/rockchip/rk3399_gru_sound.c | 93 ++++++++++++++++++++++
> 2 files changed, 99 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
> index f19b6c8..83af540 100644
> --- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
> +++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
> @@ -1,15 +1,16 @@
> -ROCKCHIP with MAX98357A/RT5514/DA7219 codecs on GRU boards
> +ROCKCHIP with MAX98357A/RT5514/DA7219 codecs and DP via spdif on GRU boards
>
> Required properties:
> - compatible: "rockchip,rk3399-gru-sound"
> -- rockchip,cpu: The phandle of the Rockchip I2S controller that's
> +- rockchip,cpu: The phandle of the Rockchip I2S controller controller that's
Huh?
^ permalink raw reply
* [PATCH] of: Add vendor prefix for Aries Embedded GmbH
From: Marek Vasut @ 2016-09-19 21:38 UTC (permalink / raw)
To: linux-arm-kernel
Add vendor prefix for Aries Embedded GmbH
http://www.aries-embedded.de/
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 69caf14..522dd65 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -27,6 +27,7 @@ analogix Analogix Semiconductor, Inc.
apm Applied Micro Circuits Corporation (APM)
aptina Aptina Imaging
arasan Arasan Chip Systems
+aries Aries Embedded GmbH
arm ARM Ltd.
armadeus ARMadeus Systems SARL
arrow Arrow Electronics
--
2.9.3
^ permalink raw reply related
* [PATCH] arm: migrate exception table users off module.h and onto extable.h
From: Paul Gortmaker @ 2016-09-19 21:38 UTC (permalink / raw)
To: linux-arm-kernel
These files were only including module.h for exception table
related functions. We've now separated that content out into its
own file "extable.h" so now move over to that and avoid all the
extra header content in module.h that we don't really need to compile
these files.
Cc: Russell King <linux@armlinux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
[see: https://lkml.org/lkml/2016/7/24/224 for additional context if needed]
arch/arm/mm/extable.c | 2 +-
arch/arm/mm/fault.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mm/extable.c b/arch/arm/mm/extable.c
index 312e15e6d00b..f436f7439e46 100644
--- a/arch/arm/mm/extable.c
+++ b/arch/arm/mm/extable.c
@@ -1,7 +1,7 @@
/*
* linux/arch/arm/mm/extable.c
*/
-#include <linux/module.h>
+#include <linux/extable.h>
#include <linux/uaccess.h>
int fixup_exception(struct pt_regs *regs)
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 3a2e678b8d30..94de590db99e 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -8,7 +8,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#include <linux/module.h>
+#include <linux/extable.h>
#include <linux/signal.h>
#include <linux/mm.h>
#include <linux/hardirq.h>
--
2.8.4
^ permalink raw reply related
* [PATCH] arm64: migrate exception table users off module.h and onto extable.h
From: Paul Gortmaker @ 2016-09-19 21:38 UTC (permalink / raw)
To: linux-arm-kernel
These files were only including module.h for exception table
related functions. We've now separated that content out into its
own file "extable.h" so now move over to that and avoid all the
extra header content in module.h that we don't really need to compile
these files.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
[see: https://lkml.org/lkml/2016/7/24/224 for additional context if needed]
arch/arm64/kernel/probes/kprobes.c | 2 +-
arch/arm64/mm/extable.c | 2 +-
arch/arm64/mm/fault.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
index bf9768588288..9c1866ef3271 100644
--- a/arch/arm64/kernel/probes/kprobes.c
+++ b/arch/arm64/kernel/probes/kprobes.c
@@ -19,7 +19,7 @@
#include <linux/kasan.h>
#include <linux/kernel.h>
#include <linux/kprobes.h>
-#include <linux/module.h>
+#include <linux/extable.h>
#include <linux/slab.h>
#include <linux/stop_machine.h>
#include <linux/stringify.h>
diff --git a/arch/arm64/mm/extable.c b/arch/arm64/mm/extable.c
index 81acd4706878..c9f118cd812b 100644
--- a/arch/arm64/mm/extable.c
+++ b/arch/arm64/mm/extable.c
@@ -2,7 +2,7 @@
* Based on arch/arm/mm/extable.c
*/
-#include <linux/module.h>
+#include <linux/extable.h>
#include <linux/uaccess.h>
int fixup_exception(struct pt_regs *regs)
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index c8beaa0da7df..427f2fd49463 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -18,7 +18,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include <linux/module.h>
+#include <linux/extable.h>
#include <linux/signal.h>
#include <linux/mm.h>
#include <linux/hardirq.h>
--
2.8.4
^ permalink raw reply related
* [PATCH 1/4] ARM: dts: mxs: Add new M28EVK manufacturer compat
From: Marek Vasut @ 2016-09-19 21:40 UTC (permalink / raw)
To: linux-arm-kernel
The board is now manufactured by Aries Embedded GmbH, update compat string.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx28-m28.dtsi | 4 ++--
arch/arm/boot/dts/imx28-m28evk.dts | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi
index 214bb15..a69856e 100644
--- a/arch/arm/boot/dts/imx28-m28.dtsi
+++ b/arch/arm/boot/dts/imx28-m28.dtsi
@@ -12,8 +12,8 @@
#include "imx28.dtsi"
/ {
- model = "DENX M28";
- compatible = "denx,m28", "fsl,imx28";
+ model = "Aries/DENX M28";
+ compatible = "aries,m28", "denx,m28", "fsl,imx28";
memory {
reg = <0x40000000 0x08000000>;
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 8d04e57..dbfb8aa 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -13,8 +13,8 @@
#include "imx28-m28.dtsi"
/ {
- model = "DENX M28EVK";
- compatible = "denx,m28evk", "fsl,imx28";
+ model = "Aries/DENX M28EVK";
+ compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28";
apb at 80000000 {
apbh at 80000000 {
--
2.9.3
^ permalink raw reply related
* [PATCH 2/4] ARM: dts: mx5: Add new M53EVK manufacturer compat
From: Marek Vasut @ 2016-09-19 21:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160919214044.9615-1-marex@denx.de>
The board is now manufactured by Aries Embedded GmbH, update compat string.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx53-m53.dtsi | 4 ++--
arch/arm/boot/dts/imx53-m53evk.dts | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi
index d259f57..ec390aa5 100644
--- a/arch/arm/boot/dts/imx53-m53.dtsi
+++ b/arch/arm/boot/dts/imx53-m53.dtsi
@@ -12,8 +12,8 @@
#include "imx53.dtsi"
/ {
- model = "DENX M53";
- compatible = "denx,imx53-m53", "fsl,imx53";
+ model = "Aries/DENX M53";
+ compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53";
memory {
reg = <0x70000000 0x20000000>,
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index dcee1e0f..4347a32 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -13,8 +13,8 @@
#include "imx53-m53.dtsi"
/ {
- model = "DENX M53EVK";
- compatible = "denx,imx53-m53evk", "fsl,imx53";
+ model = "Aries/DENX M53EVK";
+ compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53";
display1: display at di1 {
compatible = "fsl,imx-parallel-display";
--
2.9.3
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: socfpga: Add new MCVEVK manufacturer compat
From: Marek Vasut @ 2016-09-19 21:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160919214044.9615-1-marex@denx.de>
The board is now manufactured by Aries Embedded GmbH, update compat string.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
index f86f9c0..6ad3b1e 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
@@ -18,7 +18,7 @@
#include "socfpga_cyclone5.dtsi"
/ {
- model = "DENX MCV";
+ model = "Aries/DENX MCV";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
memory {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
index caa40cf..8882314 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
@@ -18,7 +18,7 @@
#include "socfpga_cyclone5_mcv.dtsi"
/ {
- model = "DENX MCV EVK";
+ model = "Aries/DENX MCV EVK";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
aliases {
--
2.9.3
^ permalink raw reply related
* [PATCH 4/4] ARM: at91/dt: sama5d4: Add new MA5D4EVK manufacturer compat
From: Marek Vasut @ 2016-09-19 21:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160919214044.9615-1-marex@denx.de>
The board is now manufactured by Aries Embedded GmbH, update compat string.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi | 4 ++--
arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
index 7c75872..b40dd9f 100644
--- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
@@ -12,8 +12,8 @@
#include "sama5d4.dtsi"
/ {
- model = "DENX MA5D4";
- compatible = "denx,ma5d4", "atmel,sama5d4", "atmel,sama5";
+ model = "Aries/DENX MA5D4";
+ compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5";
memory {
reg = <0x20000000 0x10000000>;
diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
index a52f520..d4ebd90 100644
--- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
+++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
@@ -13,8 +13,8 @@
#include "at91-sama5d4_ma5d4.dtsi"
/ {
- model = "DENX MA5D4EVK";
- compatible = "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5";
+ model = "Aries/DENX MA5D4EVK";
+ compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5";
chosen {
stdout-path = "serial3:115200n8";
--
2.9.3
^ permalink raw reply related
* [GIT PULL] ARM: mvebu: soc for v4.9 (#1)
From: Arnd Bergmann @ 2016-09-19 21:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87bmzqbilu.fsf@free-electrons.com>
On Wednesday, September 14, 2016 5:34:37 PM CEST Gregory CLEMENT wrote:
> mvebu soc for 4.9 (part 1)
>
> - irq cleanup for old mvebu SoC
> - Convert orion5x based SoC Netgear WNR854T to devicetree
>
Pulled into next/soc, thanks!
Arnd
^ permalink raw reply
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