* [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
From: Po Liu @ 2016-09-21 6:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160920204725.GA10804@localhost>
Hi Bjorn,
> -----Original Message-----
> From: Bjorn Helgaas [mailto:helgaas at kernel.org]
> Sent: Wednesday, September 21, 2016 4:47 AM
> To: Po Liu
> Cc: Roy Zang; Arnd Bergmann; devicetree at vger.kernel.org; Marc Zyngier;
> linux-pci at vger.kernel.org; linux-kernel at vger.kernel.org; Stuart Yoder;
> M.H. Lian; Murali Karicheri; Mingkai Hu; Bjorn Helgaas; Leo Li; Shawn
> Guo; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
>
> On Mon, Aug 22, 2016 at 10:09:18AM +0000, Po Liu wrote:
> > Hi Bjorn,
> >
> > Sorry for late reply.
> >
> > I checked the updated kernel with Dongdong mentioned ACPI patch which
> was truly affected my quirk patch uploaded. So I suppose the quirk patch
> is not qualify to fix the bug.
>
> I don't understand what you're saying here.
>
> The quirk worked on your machine. It apparently didn't work on
> Dongdong's machine because of_irq_parse_and_map_pci() is run after the
> quirk in this path:
>
> pci_device_probe
> pcibios_alloc_irq # arm64
> dev->irq = of_irq_parse_and_map_pci
>
> and of_irq_parse_and_map_pci() returned zero, probably because
> of_irq_parse_pci() failed. My guess is that the reason it works on your
> machine but not Dongdong's is that your DTs are different such that
> of_irq_parse_pci() works for you but not for Dongdong.
>
> I think the idea of of_irq_parse_and_map_pci() is to set up a device's
> INTx line. But that doesn't quite apply here because your device
> doesn't actually *use* INTx. So I don't know why of_irq_parse_pci()
> works for you. Maybe that's a symptom of a problem in your DT.
>
> Or maybe you're saying that the quirk *didn't* work on your machine when
> you tested it in a kernel that included d8ed75d59332 ("ARM64:
> PCI: ACPI support for legacy IRQs parsing and consolidation with DT
> code").
Yes, this point is what I mean. After this patch my quirk patch would not work.
Since I discussed with Dongdong, the patches d8ed75d59332 ACPI related were not be merged yet.
> But that doesn't make sense either, because prior to
> d8ed75d59332, we *always* set
>
> dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
>
> and after the patch we only do it if "acpi_disabled". I guess I just
> don't understand what you're saying.
Before the patch merged. pcibios_add_device()(which run the ->irq = of_irq_parse_and_map_pci(dev, 0, 0);) was loaded before the pci_fixup_device(pci_fixup_final).
But after the patch d8ed75d59332("ARM64: PCI: ACPI support for legacy IRQs parsing and consolidation with DT code") merged, the pci_fixup_device(pci_fixup_final) run BEFORE the pcibios_alloc_irq()(which run the ->irq = of_irq_parse_and_map_pci(dev, 0, 0);). So the dev->irq were overwhelm by the pcibios_alloc_irq().
When I test, the acpi_disabled is '1' although my kernel config default is CONFIG_ACPI=y. And no setting in the uboot with apci=xxx. But this is another issue, I didn't deep to check it.
>
> > I were keep thinking what your "explicitly checking for a root port
> device" meaning. Do you mean I should upload again the first version
> patch which fix it in the portdrv_core.c ? I would upload again if yes.
>
> No, I did not mean you should go back to the first version of the patch.
> If we *can* do this in a quirk, I think that would be much better than
> doing it in the PCIe port driver. I meant that Dongdong's suggestion of
> adding this:
>
> if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
> return;
>
> to your quirk made sense to me.
If the quirk patch could make workaround. It should be the better way.
Po Liu
>
> > > -----Original Message-----
> > > From: Bjorn Helgaas [mailto:helgaas at kernel.org]
> > > Sent: Saturday, July 30, 2016 6:42 AM
> > > To: Po Liu
> > > Cc: linux-pci at vger.kernel.org;
> > > linux-arm-kernel at lists.infradead.org;
> > > linux-kernel at vger.kernel.org; devicetree at vger.kernel.org; Roy Zang;
> > > Arnd Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan
> > > Lian; Murali Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
> > > Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
> > >
> > > On Tue, Jun 14, 2016 at 04:24:05PM +0800, Po Liu wrote:
> > > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC
> mode.
> > > > When chip support the aer interrupt with none MSI/MSI-X/INTx
> > > mode, > maybe there is interrupt line for aer pme etc. Search the
> > > interrupt > number in the fdt file. Then fixup the dev->irq with it.
> > > >
> > > > Signed-off-by: Po Liu <po.liu@nxp.com>
> > >
> > > I'm not sure where we're at with this. Dongdong had some issue
> > > (possibly with a version of the quirk on a different platform?), and
> > > I think the suggestion of explicitly checking for a root port
> > > device was a good one.
> > >
> > > So please update and repost this for next cycle.
> > >
> > > > ---
> > > > changes for V3:
> > > > - Move to quirk;
> > > > - Only correct the irq in RC mode;
> > > >
> > > > drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++ > 1
> > > file changed, 29 insertions(+) > > diff --git
> > > a/drivers/pci/quirks.c b/drivers/pci/quirks.c index >
> > > ee72ebe..8b39cce 100644 > --- a/drivers/pci/quirks.c > +++
> > > b/drivers/pci/quirks.c > @@ -25,6 +25,7 @@ > #include
> > > <linux/sched.h> > #include <linux/ktime.h> > #include
> > > <linux/mm.h> > +#include <linux/of_irq.h>
> > > > #include <asm/dma.h> /* isa_dma_bridge_buggy */
> > > > #include "pci.h"
> > > >
> > > > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
> > > pci_dev *pdev)
> > > > }
> > > > }
> > > > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, >
> > > quirk_intel_qat_vf_cap); > + > +/* If root port doesn't support
> > > MSI/MSI-X/INTx in RC mode, > + * but use standalone irq. Read the
> > > device tree for the aer > + * interrupt number.
> > > > + */
> > > > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > > > + int ret;
> > > > + u8 header_type;
> > > > + struct device_node *np = NULL;
> > > > +
> > > > + /* Only for the RC mode device */
> > > > + pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
> > > > + if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> > > > + return;
> > > > +
> > > > + if (dev->bus->dev.of_node)
> > > > + np = dev->bus->dev.of_node;
> > > > +
> > > > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > > > + ret = of_irq_get_byname(np, "aer");
> > > > + if (ret > 0) {
> > > > + dev->no_msi = 1;
> > > > + dev->irq = ret;
> > > > + }
> > > > + }
> > > > +}
> > > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, >
> > > +quirk_aer_interrupt); > -- > 2.1.0.27.g96db324 > > >
> > > _______________________________________________
> > > > linux-arm-kernel mailing list
> > > > linux-arm-kernel at lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* iomux-mx3.h: possible macro precedence issue
From: Uwe Kleine-König @ 2016-09-21 6:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474438379.15981.1.camel@perches.com>
Hello Joe,
On Tue, Sep 20, 2016 at 11:12:59PM -0700, Joe Perches wrote:
> > > -#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
> > > +#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, (IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE))
> > > [...]
> > > -#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
> > > +#define IOMUX_MODE(pin, mode) ((pin) | ((mode) << IOMUX_MODE_SHIFT))
> >
> > Joe, do you create a proper patch?
>
> I just don't have the hardware and don't know what was intended
> by the existing code. It does appear to be a defect though.
I don't have that hardware either, but fixing this with just checking
the hardware manual is good enough.
The current definition makes MX31_PIN_DTR_DTE1__DTR_DTE2:
MX31_PIN_DTR_DTE1__DTR_DTE2
= IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
= (MX31_PIN_DTR_DTE1 | IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE << IOMUX_MODE_SHIFT)
= (IOMUX_PIN(44, 109) | (4 << 4) | 0 << 17)
= (0x586d | 0x40)
= 0x586d
while the expected value is
(MX31_PIN_DTR_DTE1 | (IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE) << IOMUX_MODE_SHIFT)
= (IOMUX_PIN(44, 109) | ((4 << 4) | 0) << 17)
= (0x586d | 0x800000)
= 0x80586d
The effect is that the input is routed nowhere (which is the case also
with the issue fixed) and output is controlled by the GPIO module
instead of the UART and so the pin doesn't operate as handshaking
signal. (Assuming I interpreted everything correctly which I'm not sure
given that I didn't touch i.MX31 for long and it's different that the
other i.MX SoCs.)
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [GIT PULL] i.MX legacy board changes for 4.9
From: Shawn Guo @ 2016-09-21 6:16 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Olof,
I know this is late for 4.9 merge window, but the patch series fixes a
regression for i.MX legacy board support on linux-next [1]. So please
pull it for 4.9 merge window. Otherwise, we will need to get them in
during 4.9-rc cycles.
Thanks,
Shawn
[1] http://www.gossamer-threads.com/lists/linux/kernel/2529845
The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-legacy-4.9
for you to fetch changes up to 23fe1fd01c1e065907fdcd5cbfd35c02e5a418a2:
ARM: imx legacy: pca100: move peripheral initialization to .init_late (2016-09-20 22:39:07 +0800)
----------------------------------------------------------------
i.MX legacy board file changes for 4.9:
It includes a patch series that moves registrations and initializations
of all peripherals which are GPIO line consumers for all legacy boards
from .init_machine to .init_late init level. This is needed to
proactively prevent boot time issues on the legacy boards due to the
deprioritized init level of the GPIO controller driver (set lower than
IOMUX controller driver init level), which is shared among all i.MX
SoCs.
----------------------------------------------------------------
Vladimir Zapolskiy (17):
ARM: imx legacy: kzm: move peripheral initialization to .init_late
ARM: imx legacy: mx31lite: move peripheral initialization to .init_late
ARM: imx legacy: mx31ads: move peripheral initialization to .init_late
ARM: imx legacy: mx31lilly: move peripheral initialization to .init_late
ARM: imx legacy: pcm037: move peripheral initialization to .init_late
ARM: imx legacy: mx31-3ds: move peripheral initialization to .init_late
ARM: imx legacy: qong: move peripheral initialization to .init_late
ARM: imx legacy: armadillo5x0: move peripheral initialization to .init_late
ARM: imx legacy: mx31moboard: move peripheral initialization to .init_late
ARM: imx legacy: vpr200: move peripheral initialization to .init_late
ARM: imx legacy: imx27-visstrim-m10: move peripheral initialization to .init_late
ARM: imx legacy: mx27-3ds: move peripheral initialization to .init_late
ARM: imx legacy: mx35-3ds: move peripheral initialization to .init_late
ARM: imx legacy: pcm043: move peripheral initialization to .init_late
ARM: imx legacy: mx21ads: move peripheral initialization to .init_late
ARM: imx legacy: mx27ads: move peripheral initialization to .init_late
ARM: imx legacy: pca100: move peripheral initialization to .init_late
arch/arm/mach-imx/mach-armadillo5x0.c | 39 ++++++++++-------
arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 24 +++++++---
arch/arm/mach-imx/mach-kzm_arm11_01.c | 9 +++-
arch/arm/mach-imx/mach-mx21ads.c | 13 ++++--
arch/arm/mach-imx/mach-mx27_3ds.c | 30 ++++++++-----
arch/arm/mach-imx/mach-mx27ads.c | 13 ++++--
arch/arm/mach-imx/mach-mx31_3ds.c | 39 ++++++++++-------
arch/arm/mach-imx/mach-mx31ads.c | 18 ++++----
arch/arm/mach-imx/mach-mx31lilly.c | 50 +++++++++++++++------
arch/arm/mach-imx/mach-mx31lite.c | 68 ++++++++++++++++++++---------
arch/arm/mach-imx/mach-mx31moboard.c | 23 ++++++----
arch/arm/mach-imx/mach-mx35_3ds.c | 15 ++++---
arch/arm/mach-imx/mach-pca100.c | 26 ++++++-----
arch/arm/mach-imx/mach-pcm037.c | 67 ++++++++++++++--------------
arch/arm/mach-imx/mach-pcm043.c | 10 ++++-
arch/arm/mach-imx/mach-qong.c | 2 +-
arch/arm/mach-imx/mach-vpr200.c | 29 +++++++-----
arch/arm/mach-imx/mx31lilly-db.c | 20 ---------
arch/arm/mach-imx/mx31lite-db.c | 33 --------------
19 files changed, 301 insertions(+), 227 deletions(-)
^ permalink raw reply
* iomux-mx3.h: possible macro precedence issue
From: Joe Perches @ 2016-09-21 6:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921060609.5efuaa2sdsti2j5g@pengutronix.de>
On Wed, 2016-09-21 at 08:06 +0200, Uwe Kleine-K?nig wrote:\
> On Tue, Sep 20, 2016 at 01:02:24PM -0700, Joe Perches wrote:
> > Julia Lawall wrote a script
> >
> > Link:?http://lkml.kernel.org/r/alpine.DEB.2.10.1609201503260.2914 at hadrien
> >
> > that found a possible issue with macro argument precedence.
> >
> >
> > diff -u -p a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
> > --- a/arch/arm/mach-imx/iomux-mx3.h
> > +++ b/arch/arm/mach-imx/iomux-mx3.h
> > @@ -529,7 +529,7 @@ enum iomux_pins {
> > ?#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1)
> > ?#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1)
> > ?#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1)
> > -#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
> > +#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, (IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE))
> > ?#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
> > ?#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
> > ?#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
>
>
> I assume this is the only problematic definition?
yes..
> If so, there is a
> single affected platform: arch/arm/mach-imx/mach-kzm_arm11_01.c
> ?
> > this may be intentional, but perhaps a solution
> > would be to use parentheses in the #define IOMUX_MODE?
> >
> > ---
> >
> > diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
> > index 368667b..3f9ede2 100644
> > --- a/arch/arm/mach-imx/iomux-mx3.h
> > +++ b/arch/arm/mach-imx/iomux-mx3.h
> > @@ -156,7 +156,7 @@ void mxc_iomux_mode(unsigned int pin_mode);
> > > > ? (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
> > > > ? (padnum & IOMUX_PADNUM_MASK))
> > ?
> > -#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
> > +#define IOMUX_MODE(pin, mode) ((pin) | ((mode) << IOMUX_MODE_SHIFT))
> > ?
> > ?#define IOMUX_TO_GPIO(iomux_pin) \
> > ? ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
>
>
> My preference is to fix IOMUX_MODE instead of adding the parents to
> MX31_PIN_DTR_DTE1__DTR_DTE2.
Mine too.
> Joe, do you create a proper patch?
I just don't have the hardware and don't know what was intended
by the existing code. It does appear to be a defect though.
^ permalink raw reply
* iomux-mx3.h: possible macro precedence issue
From: Uwe Kleine-König @ 2016-09-21 6:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474401744.1954.55.camel@perches.com>
Cc += Shawn
Hello,
On Tue, Sep 20, 2016 at 01:02:24PM -0700, Joe Perches wrote:
> Julia Lawall wrote a script
>
> Link:?http://lkml.kernel.org/r/alpine.DEB.2.10.1609201503260.2914 at hadrien
>
> that found a possible issue with macro argument precedence.
>
>
> diff -u -p a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
> --- a/arch/arm/mach-imx/iomux-mx3.h
> +++ b/arch/arm/mach-imx/iomux-mx3.h
> @@ -529,7 +529,7 @@ enum iomux_pins {
> #define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1)
> #define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1)
> #define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1)
> -#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
> +#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, (IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE))
> #define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
> #define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
> #define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
I assume this is the only problematic definition? If so, there is a
single affected platform: arch/arm/mach-imx/mach-kzm_arm11_01.c
> this may be intentional, but perhaps a solution
> would be to use parentheses in the #define IOMUX_MODE
>
> ---
>
> diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
> index 368667b..3f9ede2 100644
> --- a/arch/arm/mach-imx/iomux-mx3.h
> +++ b/arch/arm/mach-imx/iomux-mx3.h
> @@ -156,7 +156,7 @@ void mxc_iomux_mode(unsigned int pin_mode);
> (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
> (padnum & IOMUX_PADNUM_MASK))
>
> -#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
> +#define IOMUX_MODE(pin, mode) ((pin) | ((mode) << IOMUX_MODE_SHIFT))
>
> #define IOMUX_TO_GPIO(iomux_pin) \
> ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
My preference is to fix IOMUX_MODE instead of adding the parents to
MX31_PIN_DTR_DTE1__DTR_DTE2.
Joe, do you create a proper patch?
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [RESEND PATCH v6, 5/5] arm64: dts: mediatek: add USB3 DRD driver
From: Chunfeng Yun @ 2016-09-21 5:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474437277-27201-1-git-send-email-chunfeng.yun@mediatek.com>
USB3 DRD driver is added for MT8173-EVB, and xHCI driver
becomes its subnode
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 46 +++++++++++++++++++++++++--
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 29 +++++++++++++----
2 files changed, 66 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 7453a47..682dfd7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -34,6 +34,11 @@
chosen { };
+ extcon_usb: extcon_iddig {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
+ };
+
usb_p1_vbus: regulator at 0 {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
@@ -42,6 +47,16 @@
gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ usb_p0_vbus: regulator at 1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
};
&i2c1 {
@@ -205,6 +220,20 @@
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
+
+ usb_id_pins_float: usb_iddig_pull_up {
+ pins_iddig {
+ pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>;
+ bias-pull-up;
+ };
+ };
+
+ usb_id_pins_ground: usb_iddig_pull_down {
+ pins_iddig {
+ pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>;
+ bias-pull-down;
+ };
+ };
};
&pwm0 {
@@ -431,12 +460,25 @@
status = "okay";
};
+&ssusb {
+ vusb33-supply = <&mt6397_vusb_reg>;
+ vbus-supply = <&usb_p0_vbus>;
+ extcon = <&extcon_usb>;
+ dr_mode = "otg";
+ mediatek,enable-wakeup;
+ pinctrl-names = "default", "id_float", "id_ground";
+ pinctrl-0 = <&usb_id_pins_float>;
+ pinctrl-1 = <&usb_id_pins_float>;
+ pinctrl-2 = <&usb_id_pins_ground>;
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
-&usb30 {
+&usb_host {
vusb33-supply = <&mt6397_vusb_reg>;
vbus-supply = <&usb_p1_vbus>;
- mediatek,wakeup-src = <1>;
+ status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 10f638f..925948a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -668,11 +668,14 @@
status = "disabled";
};
- usb30: usb at 11270000 {
- compatible = "mediatek,mt8173-xhci";
- reg = <0 0x11270000 0 0x1000>,
+ ssusb: usb at 11271000 {
+ compatible = "mediatek,mt8173-mtu3";
+ reg = <0 0x11271000 0 0x3000>,
<0 0x11280700 0 0x0100>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&phy_port0 PHY_TYPE_USB3>,
+ <&phy_port1 PHY_TYPE_USB2>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>,
<&pericfg CLK_PERI_USB0>,
@@ -680,10 +683,22 @@
clock-names = "sys_ck",
"wakeup_deb_p0",
"wakeup_deb_p1";
- phys = <&phy_port0 PHY_TYPE_USB3>,
- <&phy_port1 PHY_TYPE_USB2>;
mediatek,syscon-wakeup = <&pericfg>;
- status = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: xhci at 11270000 {
+ compatible = "mediatek,mt8173-xhci";
+ reg = <0 0x11270000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>;
+ clock-names = "sys_ck";
+ status = "disabled";
+ };
};
u3phy: usb-phy at 11290000 {
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH v6, 3/5] usb: xhci-mtk: make IPPC register optional
From: Chunfeng Yun @ 2016-09-21 5:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474437277-27201-1-git-send-email-chunfeng.yun@mediatek.com>
Make IPPC register optional to support host side of dual-role mode,
due to it is moved into common glue layer for simplification.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/usb/host/xhci-mtk.c | 36 +++++++++++++++++++++++++++++-------
1 file changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 79959f1..4bf99b9 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -94,6 +94,9 @@ static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
int ret;
int i;
+ if (ippc == NULL)
+ return 0;
+
/* power on host ip */
value = readl(&ippc->ip_pw_ctr1);
value &= ~CTRL1_IP_HOST_PDN;
@@ -139,6 +142,9 @@ static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
int ret;
int i;
+ if (ippc == NULL)
+ return 0;
+
/* power down all u3 ports */
for (i = 0; i < mtk->num_u3_ports; i++) {
value = readl(&ippc->u3_ctrl_p[i]);
@@ -173,6 +179,9 @@ static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
u32 value;
+ if (ippc == NULL)
+ return 0;
+
/* reset whole ip */
value = readl(&ippc->ip_pw_ctr0);
value |= CTRL0_IP_SW_RST;
@@ -475,6 +484,7 @@ static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
/* called during probe() after chip reset completes */
static int xhci_mtk_setup(struct usb_hcd *hcd)
{
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
int ret;
@@ -482,12 +492,21 @@ static int xhci_mtk_setup(struct usb_hcd *hcd)
ret = xhci_mtk_ssusb_config(mtk);
if (ret)
return ret;
+ }
+
+ ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
+ if (ret)
+ return ret;
+
+ if (usb_hcd_is_primary_hcd(hcd)) {
+ mtk->num_u3_ports = xhci->num_usb3_ports;
+ mtk->num_u2_ports = xhci->num_usb2_ports;
ret = xhci_mtk_sch_init(mtk);
if (ret)
return ret;
}
- return xhci_gen_setup(hcd, xhci_mtk_quirks);
+ return ret;
}
static int xhci_mtk_probe(struct platform_device *pdev)
@@ -586,7 +605,7 @@ static int xhci_mtk_probe(struct platform_device *pdev)
mtk->hcd = platform_get_drvdata(pdev);
platform_set_drvdata(pdev, mtk);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
hcd->regs = devm_ioremap_resource(dev, res);
if (IS_ERR(hcd->regs)) {
ret = PTR_ERR(hcd->regs);
@@ -595,11 +614,14 @@ static int xhci_mtk_probe(struct platform_device *pdev)
hcd->rsrc_start = res->start;
hcd->rsrc_len = resource_size(res);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- mtk->ippc_regs = devm_ioremap_resource(dev, res);
- if (IS_ERR(mtk->ippc_regs)) {
- ret = PTR_ERR(mtk->ippc_regs);
- goto put_usb2_hcd;
+ mtk->ippc_regs = NULL;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
+ if (res) { /* ippc register is optional */
+ mtk->ippc_regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(mtk->ippc_regs)) {
+ ret = PTR_ERR(mtk->ippc_regs);
+ goto put_usb2_hcd;
+ }
}
for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) {
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH v6, 2/5] dt-bindings: mt8173-mtu3: add devicetree bindings
From: Chunfeng Yun @ 2016-09-21 5:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474437277-27201-1-git-send-email-chunfeng.yun@mediatek.com>
add a DT binding doc for MediaTek USB3 DRD driver
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/usb/mt8173-mtu3.txt | 87 ++++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
diff --git a/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
new file mode 100644
index 0000000..e049d19
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
@@ -0,0 +1,87 @@
+The device node for Mediatek USB3.0 DRD controller
+
+Required properties:
+ - compatible : should be "mediatek,mt8173-mtu3"
+ - reg : specifies physical base address and size of the registers
+ - reg-names: should be "mac" for device IP and "ippc" for IP port control
+ - interrupts : interrupt used by the device IP
+ - power-domains : a phandle to USB power domain node to control USB's
+ mtcmos
+ - vusb33-supply : regulator of USB avdd3.3v
+ - clocks : a list of phandle + clock-specifier pairs, one for each
+ entry in clock-names
+ - clock-names : must contain "sys_ck" for clock of controller;
+ "wakeup_deb_p0" and "wakeup_deb_p1" are optional, they are
+ depends on "mediatek,enable-wakeup"
+ - phys : a list of phandle + phy specifier pairs
+ - dr_mode : should be one of "host", "peripheral" or "otg",
+ refer to usb/generic.txt
+
+Optional properties:
+ - #address-cells, #size-cells : should be '2' if the device has sub-nodes
+ with 'reg' property
+ - ranges : allows valid 1:1 translation between child's address space and
+ parent's address space
+ - extcon : external connector for vbus and idpin changes detection, needed
+ when supports dual-role mode.
+ - vbus-supply : reference to the VBUS regulator, needed when supports
+ dual-role mode.
+ - pinctl-names : a pinctrl state named "default" must be defined,
+ "id_float" and "id_ground" are optinal which depends on
+ "mediatek,enable-manual-drd"
+ - pinctrl-0 : pin control group
+ See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+
+ - maximum-speed : valid arguments are "super-speed", "high-speed" and
+ "full-speed"; refer to usb/generic.txt
+ - enable-manual-drd : supports manual dual-role switch via debugfs; usually
+ used when receptacle is TYPE-A and also wants to support dual-role
+ mode.
+ - mediatek,enable-wakeup : supports ip sleep wakeup used by host mode
+ - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup
+ control register, it depends on "mediatek,enable-wakeup".
+
+Sub-nodes:
+The xhci should be added as subnode to mtu3 as shown in the following example
+if host mode is enabled. The DT binding details of xhci can be found in:
+Documentation/devicetree/bindings/usb/mt8173-xhci.txt
+
+Example:
+ssusb: usb at 11271000 {
+ compatible = "mediatek,mt8173-mtu3";
+ reg = <0 0x11271000 0 0x3000>,
+ <0 0x11280700 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&phy_port0 PHY_TYPE_USB3>,
+ <&phy_port1 PHY_TYPE_USB2>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>,
+ <&pericfg CLK_PERI_USB0>,
+ <&pericfg CLK_PERI_USB1>;
+ clock-names = "sys_ck",
+ "wakeup_deb_p0",
+ "wakeup_deb_p1";
+ vusb33-supply = <&mt6397_vusb_reg>;
+ vbus-supply = <&usb_p0_vbus>;
+ extcon = <&extcon_usb>;
+ dr_mode = "otg";
+ mediatek,enable-wakeup;
+ mediatek,syscon-wakeup = <&pericfg>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: xhci at 11270000 {
+ compatible = "mediatek,mt8173-xhci";
+ reg = <0 0x11270000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>;
+ clock-names = "sys_ck";
+ vusb33-supply = <&mt6397_vusb_reg>;
+ status = "disabled";
+ };
+};
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH v6, 1/5] dt-bindings: mt8173-xhci: support host side of dual-role mode
From: Chunfeng Yun @ 2016-09-21 5:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474437277-27201-1-git-send-email-chunfeng.yun@mediatek.com>
Some resources, such as IPPC register etc, shared with device
driver are moved into common glue layer when xHCI driver is the
host side of dual-role mode and they should be changed as optional
properties if they are required ones before. For clarity, add
a new part of binding to support host side of dual-role mode.
Additionally add optional properties of pinctrl for host only mode
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/usb/mt8173-xhci.txt | 54 +++++++++++++++++++-
1 file changed, 52 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
index b3a7ffa..2a930bd 100644
--- a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
@@ -2,10 +2,18 @@ MT8173 xHCI
The device node for Mediatek SOC USB3.0 host controller
+There are two scenarios: the first one only supports xHCI driver;
+the second one supports dual-role mode, and the host is based on xHCI
+driver. Take account of backward compatibility, we divide bindings
+into two parts.
+
+1st: only supports xHCI driver
+------------------------------------------------------------------------
+
Required properties:
- compatible : should contain "mediatek,mt8173-xhci"
- - reg : specifies physical base address and size of the registers,
- the first one for MAC, the second for IPPC
+ - reg : specifies physical base address and size of the registers
+ - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
- interrupts : interrupt used by the controller
- power-domains : a phandle to USB power domain node to control USB's
mtcmos
@@ -27,12 +35,16 @@ Optional properties:
control register, it depends on "mediatek,wakeup-src".
- vbus-supply : reference to the VBUS regulator;
- usb3-lpm-capable : supports USB3.0 LPM
+ - pinctrl-names : a pinctrl state named "default" must be defined
+ - pinctrl-0 : pin control group
+ See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
Example:
usb30: usb at 11270000 {
compatible = "mediatek,mt8173-xhci";
reg = <0 0x11270000 0 0x1000>,
<0 0x11280700 0 0x0100>;
+ reg-names = "mac", "ippc";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>,
@@ -49,3 +61,41 @@ usb30: usb at 11270000 {
mediatek,syscon-wakeup = <&pericfg>;
mediatek,wakeup-src = <1>;
};
+
+2nd: dual-role mode with xHCI driver
+------------------------------------------------------------------------
+
+In the case, xhci is added as subnode to mtu3. An example and the DT binding
+details of mtu3 can be found in:
+Documentation/devicetree/bindings/usb/mtu3.txt
+
+Required properties:
+ - compatible : should contain "mediatek,mt8173-xhci"
+ - reg : specifies physical base address and size of the registers
+ - reg-names: should be "mac" for xHCI MAC
+ - interrupts : interrupt used by the host controller
+ - power-domains : a phandle to USB power domain node to control USB's
+ mtcmos
+ - vusb33-supply : regulator of USB avdd3.3v
+
+ - clocks : a list of phandle + clock-specifier pairs, one for each
+ entry in clock-names
+ - clock-names : must be
+ "sys_ck": for clock of xHCI MAC
+
+Optional properties:
+ - vbus-supply : reference to the VBUS regulator;
+ - usb3-lpm-capable : supports USB3.0 LPM
+
+Example:
+usb30: usb at 11270000 {
+ compatible = "mediatek,mt8173-xhci";
+ reg = <0 0x11270000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+ clocks = <&topckgen CLK_TOP_USB30_SEL>;
+ clock-names = "sys_ck";
+ vusb33-supply = <&mt6397_vusb_reg>;
+ usb3-lpm-capable;
+};
--
1.7.9.5
^ permalink raw reply related
* [RESEND PATCH v6, 0/5] Add MediaTek USB3 DRD Driver
From: Chunfeng Yun @ 2016-09-21 5:54 UTC (permalink / raw)
To: linux-arm-kernel
>From 99e428a1808c8ca91ff473d487b52ca5d355d875 Mon Sep 17 00:00:00 2001
From: Chunfeng Yun <chunfeng.yun@mediatek.com>
Date: Mon, 5 Sep 2016 10:27:07 +0800
Subject: [PATCH v6, 0/5] Add MediaTek USB3 DRD Driver
These patches introduce the MediaTek USB3 dual-role controller
driver.
The driver can be configured as Dual-Role Device (DRD),
Peripheral Only and Host Only (xHCI) modes. It works well
with Mass Storage, RNDIS and g_zero on FS/HS and SS. And it is
tested on MT8173 platform which only contains USB2.0 device IP,
and on MT6290 platform which contains USB3.0 device IP.
Change in v6:
1. handle endianness of GPD and SETUP data
2. remove dummy error log and return suitable error number
3. cancel delay work when deregiseter driver
Change in v5:
1. modify some comments
2. rename some unsuitable variables
3. add reg-names property for host node
4. add USB_MTU3_DEBUG to control debug messages
Change in v4:
1. fix build errors on non-mediatek platforms
2. provide manual dual-role switch via debugfs instead of sysfs
Change in v3:
1. fix some typo error
2. rename mtu3.txt to mt8173-mtu3.txt
Change in v2:
1. modify binding docs according to suggestions
2. modify some comments and remove some dummy blank lines
3. fix memory leakage
Chunfeng Yun (5):
dt-bindings: mt8173-xhci: support host side of dual-role mode
dt-bindings: mt8173-mtu3: add devicetree bindings
usb: xhci-mtk: make IPPC register optional
usb: Add MediaTek USB3 DRD Driver
arm64: dts: mediatek: add USB3 DRD driver
.../devicetree/bindings/usb/mt8173-mtu3.txt | 87 ++
.../devicetree/bindings/usb/mt8173-xhci.txt | 54 +-
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 46 +-
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 29 +-
drivers/usb/Kconfig | 2 +
drivers/usb/Makefile | 1 +
drivers/usb/host/xhci-mtk.c | 36 +-
drivers/usb/mtu3/Kconfig | 54 ++
drivers/usb/mtu3/Makefile | 19 +
drivers/usb/mtu3/mtu3.h | 422 ++++++++++
drivers/usb/mtu3/mtu3_core.c | 871 +++++++++++++++++++
drivers/usb/mtu3/mtu3_dr.c | 379 +++++++++
drivers/usb/mtu3/mtu3_dr.h | 108 +++
drivers/usb/mtu3/mtu3_gadget.c | 731 ++++++++++++++++
drivers/usb/mtu3/mtu3_gadget_ep0.c | 883 ++++++++++++++++++++
drivers/usb/mtu3/mtu3_host.c | 294 +++++++
drivers/usb/mtu3/mtu3_hw_regs.h | 473 +++++++++++
drivers/usb/mtu3/mtu3_plat.c | 490 +++++++++++
drivers/usb/mtu3/mtu3_qmu.c | 599 +++++++++++++
drivers/usb/mtu3/mtu3_qmu.h | 43 +
20 files changed, 5603 insertions(+), 18 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
create mode 100644 drivers/usb/mtu3/Kconfig
create mode 100644 drivers/usb/mtu3/Makefile
create mode 100644 drivers/usb/mtu3/mtu3.h
create mode 100644 drivers/usb/mtu3/mtu3_core.c
create mode 100644 drivers/usb/mtu3/mtu3_dr.c
create mode 100644 drivers/usb/mtu3/mtu3_dr.h
create mode 100644 drivers/usb/mtu3/mtu3_gadget.c
create mode 100644 drivers/usb/mtu3/mtu3_gadget_ep0.c
create mode 100644 drivers/usb/mtu3/mtu3_host.c
create mode 100644 drivers/usb/mtu3/mtu3_hw_regs.h
create mode 100644 drivers/usb/mtu3/mtu3_plat.c
create mode 100644 drivers/usb/mtu3/mtu3_qmu.c
create mode 100644 drivers/usb/mtu3/mtu3_qmu.h
--
1.7.9.5
^ permalink raw reply
* [PATCH] iommu/io-pgtable-arm: Using for_each_set_bit to simplify the code
From: Kefeng Wang @ 2016-09-21 5:41 UTC (permalink / raw)
To: linux-arm-kernel
Using for_each_set_bit() to simplify the code.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 5 +----
drivers/iommu/io-pgtable-arm.c | 5 +----
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index def8ca1..f23821b 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -789,8 +789,7 @@ static int __init arm_v7s_do_selftests(void)
* Distinct mappings of different granule sizes.
*/
iova = 0;
- i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG);
- while (i != BITS_PER_LONG) {
+ for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) {
size = 1UL << i;
if (ops->map(ops, iova, iova, size, IOMMU_READ |
IOMMU_WRITE |
@@ -807,8 +806,6 @@ static int __init arm_v7s_do_selftests(void)
return __FAIL(ops);
iova += SZ_16M;
- i++;
- i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i);
loopnr++;
}
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index f5c90e1..8c3dfb7 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -980,8 +980,7 @@ static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
* Distinct mappings of different granule sizes.
*/
iova = 0;
- j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG);
- while (j != BITS_PER_LONG) {
+ for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
size = 1UL << j;
if (ops->map(ops, iova, iova, size, IOMMU_READ |
@@ -999,8 +998,6 @@ static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
return __FAIL(ops, i);
iova += SZ_1G;
- j++;
- j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j);
}
/* Partial unmap */
--
1.7.12.4
^ permalink raw reply related
* [PATCH 5/9] dmaengine/ARM: omap-dma: Fix the DMAengine compile test on non OMAP configs
From: Vinod Koul @ 2016-09-21 3:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921035131.GD2609@localhost>
On Wed, Sep 21, 2016 at 09:21:32AM +0530, Vinod Koul wrote:
> On Fri, Sep 16, 2016 at 11:33:20AM +0300, Peter Ujfalusi wrote:
> > The DMAengine driver for omap-dma use three function calls from the
> > plat-omap legacy driver. When the DMAengine driver is built when ARCH_OMAP
> > is not set, the compilation will fail due to missing symbols.
> > Add empty inline functions to allow the DMAengine driver to be compiled
> > with COMPILE_TEST.
>
> Peter,
>
> This should be before you enable COMPILE_TEST otherwise build will break!
Ah never mind, you have three drivers in this series so I think this is fine
before the omap one :)
--
~Vinod
^ permalink raw reply
* [PATCH 8/9] dmaengine: ti-dma-crossbar: Use enum for crossbar type
From: Vinod Koul @ 2016-09-21 3:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916083324.29133-9-peter.ujfalusi@ti.com>
On Fri, Sep 16, 2016 at 11:33:23AM +0300, Peter Ujfalusi wrote:
> Fixes compiler warning on 64bit architectures.
Would be good to give the warning message here
>
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---
> drivers/dma/ti-dma-crossbar.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/dma/ti-dma-crossbar.c b/drivers/dma/ti-dma-crossbar.c
> index e4f3bd1ae264..876e4ccaf033 100644
> --- a/drivers/dma/ti-dma-crossbar.c
> +++ b/drivers/dma/ti-dma-crossbar.c
> @@ -16,8 +16,10 @@
> #include <linux/of_device.h>
> #include <linux/of_dma.h>
>
> -#define TI_XBAR_DRA7 0
> -#define TI_XBAR_AM335X 1
> +enum ti_xbar_type {
> + TI_XBAR_DRA7 = 0,
> + TI_XBAR_AM335X,
> +};
>
> static const struct of_device_id ti_dma_xbar_match[] = {
> {
> @@ -395,7 +397,7 @@ static int ti_dra7_xbar_probe(struct platform_device *pdev)
>
> xbar->dmarouter.dev = &pdev->dev;
> xbar->dmarouter.route_free = ti_dra7_xbar_free;
> - xbar->dma_offset = (u32)match->data;
> + xbar->dma_offset = (enum ti_xbar_type)match->data;
>
> mutex_init(&xbar->mutex);
> platform_set_drvdata(pdev, xbar);
> @@ -428,7 +430,7 @@ static int ti_dma_xbar_probe(struct platform_device *pdev)
> if (unlikely(!match))
> return -EINVAL;
>
> - switch ((u32)match->data) {
> + switch ((enum ti_xbar_type)match->data) {
> case TI_XBAR_DRA7:
> ret = ti_dra7_xbar_probe(pdev);
> break;
> --
> 2.10.0
>
--
~Vinod
^ permalink raw reply
* [PATCH 5/9] dmaengine/ARM: omap-dma: Fix the DMAengine compile test on non OMAP configs
From: Vinod Koul @ 2016-09-21 3:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916083324.29133-6-peter.ujfalusi@ti.com>
On Fri, Sep 16, 2016 at 11:33:20AM +0300, Peter Ujfalusi wrote:
> The DMAengine driver for omap-dma use three function calls from the
> plat-omap legacy driver. When the DMAengine driver is built when ARCH_OMAP
> is not set, the compilation will fail due to missing symbols.
> Add empty inline functions to allow the DMAengine driver to be compiled
> with COMPILE_TEST.
Peter,
This should be before you enable COMPILE_TEST otherwise build will break!
>
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---
> include/linux/omap-dma.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
> index 1d99b61adc65..290081620b3e 100644
> --- a/include/linux/omap-dma.h
> +++ b/include/linux/omap-dma.h
> @@ -297,6 +297,7 @@ struct omap_system_dma_plat_info {
> #define dma_omap15xx() __dma_omap15xx(d)
> #define dma_omap16xx() __dma_omap16xx(d)
>
> +#if defined(CONFIG_ARCH_OMAP)
> extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
>
> extern void omap_set_dma_priority(int lch, int dst_port, int priority);
> @@ -355,4 +356,22 @@ static inline int omap_lcd_dma_running(void)
> }
> #endif
>
> +#else /* CONFIG_ARCH_OMAP */
> +
> +static inline struct omap_system_dma_plat_info *omap_get_plat_info(void)
> +{
> + return NULL;
> +}
> +
> +static inline int omap_request_dma(int dev_id, const char *dev_name,
> + void (*callback)(int lch, u16 ch_status, void *data),
> + void *data, int *dma_ch)
> +{
> + return -ENODEV;
> +}
> +
> +static inline void omap_free_dma(int ch) { }
> +
> +#endif /* CONFIG_ARCH_OMAP */
> +
> #endif /* __LINUX_OMAP_DMA_H */
> --
> 2.10.0
>
--
~Vinod
^ permalink raw reply
* [PATCH] clk: mediatek: clk-mt8173: Unmap region obtained by of_iomap
From: James Liao @ 2016-09-21 3:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474360242-15126-1-git-send-email-arvind.yadav.cs@gmail.com>
On Tue, 2016-09-20 at 14:00 +0530, Arvind Yadav wrote:
> From: Arvind Yadav <arvind.yadav.cs@gmail.com>
>
> Free memory mapping, if init is not successful.
>
> Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
> ---
> drivers/clk/mediatek/clk-mt8173.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
> index 10c9860..0ac3aee 100644
> --- a/drivers/clk/mediatek/clk-mt8173.c
> +++ b/drivers/clk/mediatek/clk-mt8173.c
> @@ -1074,8 +1074,10 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
> }
>
> mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> - if (!clk_data)
> + if (!clk_data) {
> + iounmap(base);
> return;
> + }
>
> mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
>
^ permalink raw reply
* s3c2416 use two usb host?
From: jiangyanpin77 @ 2016-09-21 2:39 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
I am working on samsung s3c2416 ARM based Soc on
linux 3.1.18 kernel. By default, the Soc has one
USB host and one USB device/host. My USB host is
working fine. Since I need to use two USB host on my system,
I need to enable the USB device/host as a USB host.
I am using ARM9 based s3c2416 processor. The SoC has one USB host
controller and one USB host/device controller. What are the
register settings that should be done to enable both USB
interfaces as USB host controller. ? There is a register PHYCTRL
with address 0x4C00_0080. Its bit[0] says something on USB host
mode and USB device mode. Is it this register which I should
work on or any more register configurations are required ?
The following are the changes I have made for the same:
Register Address value
-----------------------------
PHYPWR 0x4C00_0084 0x0
PWRCFG 0x4C00_0060 (1<<4)
URSTCON 0x4C00_0088 (0<<2)|(1<<1)|(1<<0)
URSTCON 0x4C00_0088 (0<<2)|(0<<1)|(0<<0)
PHYCTRL 0x4C00_0080 (0<<3)|(0<<2)|(1<<1)|(1<<0)
UCLKCON 0x4C00_008C 0<<31)|(0<<2)|(1<<1)|(1<<0)
Once I try to plug in a USB mass storage device (whose driver is present in
kernel), I get the following error:
usb 1-2: new full speed USB device using s3c2410-ohci and address 10
usb 1-2: device descriptor read/64, error -62
usb 1-2: device descriptor read/64, error -62
usb 1-2: new full speed USB device using s3c2410-ohci and address 11
usb 1-2: device descriptor read/64, error -62
usb 1-2: device descriptor read/64, error -62
usb 1-2: new full speed USB device using s3c2410-ohci and address 12
usb 1-2: device not accepting address 12, error -62
usb 1-2: new full speed USB device using s3c2410-ohci and address 13
usb 1-2: device not accepting address 13, error -62
Why is it throwing this error ? Is there any driver for USB hub missing in
2.6.21 kernel, or do I need to modify more on register settings.
Please help.
Thank You
YanpinJiang
^ permalink raw reply
* [PATCH] ARM: *: mm: Implement get_user_pages_fast()
From: Yuriy Romanenko @ 2016-09-21 2:00 UTC (permalink / raw)
To: linux-arm-kernel
>From 6be781314e78ad43d797915189145a0aae41f639 Mon Sep 17 00:00:00 2001
From: Yuriy Romanenko <yromanenko@carrietech.com>
Date: Tue, 20 Sep 2016 18:50:16 -0700
Subject: [PATCH] ARM: *: mm: Implement get_user_pages_fast()
Will do an unlocked walk of the page table, if that provides everything
necessary, it will succeed and return, otherwise it will call the old
slow path on the remainder
Signed-off-by: Yuriy Romanenko <yromanenko@carrietech.com>
---
arch/arm/mm/Makefile | 2 +-
arch/arm/mm/gup.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 91 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mm/gup.c
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 7f76d96..096cfcb 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -6,7 +6,7 @@ obj-y := dma-mapping.o extable.o fault.o init.o \
iomap.o
obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \
- mmap.o pgd.o mmu.o pageattr.o
+ mmap.o pgd.o mmu.o pageattr.o gup.o
ifneq ($(CONFIG_MMU),y)
obj-y += nommu.o
diff --git a/arch/arm/mm/gup.c b/arch/arm/mm/gup.c
new file mode 100644
index 0000000..6e57bc9
--- /dev/null
+++ b/arch/arm/mm/gup.c
@@ -0,0 +1,90 @@
+/*
+ * Lockless get_user_pages_fast for ARM
+ *
+ * Copyright (C) 2014 Lytro, Inc.
+ */
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/vmstat.h>
+#include <linux/highmem.h>
+#include <linux/swap.h>
+
+#include <asm/pgtable.h>
+
+struct gup_private_data {
+ int nr;
+ struct page **pages;
+ int write;
+};
+
+static int gup_pte_entry(pte_t *ptep, unsigned long start,
+ unsigned long end, struct mm_walk *walk)
+{
+ struct gup_private_data *private_data =
+ (struct gup_private_data *)walk->private;
+ struct page * page;
+ pte_t pte = *ptep;
+ if (!pte_present(pte) ||
+ pte_special(pte) ||
+ (private_data->write && !pte_write(pte)))
+ {
+ return private_data->nr;
+ }
+ page = pte_page(pte);
+ get_page(page);
+ private_data->pages[private_data->nr++] = page;
+ return 0;
+}
+
+static int gup_pte_hole_entry(unsigned long start, unsigned long end,
+ struct mm_walk *walk)
+{
+ struct gup_private_data *private_data =
+ (struct gup_private_data *)walk->private;
+ return private_data->nr;
+}
+
+
+int get_user_pages_fast(unsigned long start, int nr_pages, int write,
+ struct page **pages)
+{
+ struct mm_struct *mm = current->mm;
+ int ret;
+ unsigned long page_addr = (start & PAGE_MASK);
+ int nr = 0;
+
+ struct gup_private_data private_data = {
+ .nr = 0,
+ .pages = pages,
+ .write = write
+ };
+
+ struct mm_walk gup_walk = {
+ .pte_entry = gup_pte_entry,
+ .pte_hole = gup_pte_hole_entry,
+ .mm = mm,
+ .private = (void *)&private_data
+ };
+
+ ret = walk_page_range(page_addr,
+ page_addr + nr_pages * PAGE_SIZE,
+ &gup_walk);
+ nr = ret ? ret : nr_pages;
+
+ if (nr == nr_pages)
+ {
+ return nr;
+ }
+ else
+ {
+ page_addr += (nr << PAGE_SHIFT);
+ }
+
+ down_read(&mm->mmap_sem);
+ ret = get_user_pages(current, mm, page_addr,
+ nr_pages - nr, write, 0, pages + nr, NULL);
+ up_read(&mm->mmap_sem);
+
+ return (ret < 0) ? nr : (ret + nr);
+}
\ No newline@end of file
--
2.7.4
^ permalink raw reply related
* [RFC PATCH 0/8] arm64: move thread_info off of the task stack
From: Laura Abbott @ 2016-09-21 1:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473947349-14521-1-git-send-email-mark.rutland@arm.com>
On 09/15/2016 06:49 AM, Mark Rutland wrote:
> Building atop of Andy's work on x86 and generic code, these patches move
> arm64's thread_info off of the stack and into task_struct. This protects
> thread_info from corruption in the face of stack overflow, and serves as
> a step towards fully robust stack overflow handling will be addressed by
> subsequent patches.
>
> In contrast to x86, we can't place some critical data such as
> preempt_count in percpu variables, and we must store these in some
> per-task location. This, compounded with the way headers are organised
> conspires to require us to still define our own thread_info. I
> understand that the longer term plan is to kill off thread_info
> entirely, hence I'm sending this as an RFC so we can figure out if/how
> we can achieve that.
>
> These patches are based on Andy's x86/vmap_stack branch [1,2], and I've
> pushed a copy to me arm64/ti-stack-split branch [3,4]. The result of
> these patches boots happily on platforms within reach of my desk, but
> has not seen much stressing so far.
>
FWIW, I used your ti-stack-split branch while running some kernel builds
and it seems to work well enough. You can take that as a Tested-by or I
can re-test with a non-RFC version.
> Thanks,
> Mark.
>
> [1] git://git.kernel.org/pub/scm/linux/kernel/git/luto/linux.git x86/vmap_stack
> [2] https://git.kernel.org/cgit/linux/kernel/git/luto/linux.git/log/?h=x86/vmap_stack
> [3] git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git arm64/ti-stack-split
> [4] https://git.kernel.org/cgit/linux/kernel/git/mark/linux.git/log/?h=arm64/ti-stack-split
>
> Mark Rutland (8):
> thread_info: include <current.h> for THREAD_INFO_IN_TASK
> thread_info: allow custom in-task thread_info
> arm64: thread_info remove stale items
> arm64: asm-offsets: remove unused definitions
> arm64: assembler: introduce ldr_this_cpu
> arm64: traps: use task_struct instead of thread_info
> arm64: move sp_el0 and tpidr_el1 into cpu_suspend_ctx
> arm64: split thread_info from task stack
>
> arch/arm64/Kconfig | 2 ++
> arch/arm64/include/asm/Kbuild | 1 -
> arch/arm64/include/asm/assembler.h | 19 +++++++++++++++----
> arch/arm64/include/asm/current.h | 22 ++++++++++++++++++++++
> arch/arm64/include/asm/smp.h | 1 +
> arch/arm64/include/asm/suspend.h | 2 +-
> arch/arm64/include/asm/thread_info.h | 21 ---------------------
> arch/arm64/kernel/asm-offsets.c | 3 +--
> arch/arm64/kernel/entry.S | 6 +++---
> arch/arm64/kernel/head.S | 11 +++++------
> arch/arm64/kernel/process.c | 31 ++++++++++++++++++++++++++-----
> arch/arm64/kernel/sleep.S | 3 ---
> arch/arm64/kernel/smp.c | 2 ++
> arch/arm64/kernel/stacktrace.c | 5 +++++
> arch/arm64/kernel/suspend.c | 6 ------
> arch/arm64/kernel/traps.c | 12 ++++++------
> arch/arm64/mm/proc.S | 6 ++++++
> include/linux/thread_info.h | 4 +++-
> init/Kconfig | 3 +++
> 19 files changed, 101 insertions(+), 59 deletions(-)
> create mode 100644 arch/arm64/include/asm/current.h
>
^ permalink raw reply
* [PATCH V6 0/5] ECAM quirks handling for ARM64 platforms
From: cov at codeaurora.org @ 2016-09-21 1:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160920192636.GB4941@localhost>
Hi Bjorn, Thomasz,
On 2016-09-20 15:26, Bjorn Helgaas wrote:
> On Fri, Sep 09, 2016 at 09:24:02PM +0200, Tomasz Nowicki wrote:
>> Quirk handling relies on an idea of simple static array which contains
>> quirk enties. Each entry consists of identification information (IDs
>> from
>> standard header of MCFG table) along with custom pci_ecam_ops
>> structure and
>> configuration space resource structure. This way it is possible find
>> corresponding quirk entries and override pci_ecam_ops and PCI
>> configuration
>> space regions.
>>
>> As an example, the last 3 patches present quirk handling mechanism
>> usage for
>> ThunderX.
>>
>> v5 -> v6
>> - rebase against v4.8-rc5
>> - drop patch 1 form previous series
>> - keep pci_acpi_setup_ecam_mapping() in ARM64 arch directory
>> - move quirk code to pci_mcfg.c
>> - restrict quirk to override pci_ecam_ops and CFG resource structure
>> only, no init call any more
>> - split ThunderX quirks into the smaller chunks
>> - add ThunderX pass1.x silicon revision support
>>
>> v4 -> v5
>> - rebase against v4.8-rc1
>> - rework to exact MCFG OEM ID, TABLE ID, rev match
>> - use memcmp instead of strncmp
>> - no substring match
>> - fix typos and dmesg message
>>
>> Tomasz Nowicki (5):
>> PCI/ACPI: Extend pci_mcfg_lookup() responsibilities
>> PCI/ACPI: Check platform specific ECAM quirks
>> PCI: thunder-pem: Allow to probe PEM-specific register range for
>> ACPI
>> case
>> PCI: thunder: Enable ACPI PCI controller for ThunderX pass2.x
>> silicon
>> version
>> PCI: thunder: Enable ACPI PCI controller for ThunderX pass1.x
>> silicon
>> version
>>
>> arch/arm64/kernel/pci.c | 17 ++--
>> drivers/acpi/pci_mcfg.c | 168
>> +++++++++++++++++++++++++++++++++++-
>> drivers/pci/host/pci-thunder-ecam.c | 2 +-
>> drivers/pci/host/pci-thunder-pem.c | 63 +++++++++++---
>> include/linux/pci-acpi.h | 4 +-
>> include/linux/pci-ecam.h | 7 ++
>> 6 files changed, 230 insertions(+), 31 deletions(-)
>
> I'm not quite ready to merge these because we haven't resolved the
> question of how to expose the resources used by the memory-mapped
> config space. I'm fine with the first two patches (I did make a
> couple trivial changes, see below), but there's no point in merging
> them until we merge a user for them.
>
> I pushed the series to pci/ecam-v6 for build testing and discussion.
> The diff (the changes I made locally) from v6 as posted by Tomasz is
> below.
Rebasing the following simple quirks framework user onto this branch,
I have some questions.
https://source.codeaurora.org/quic/server/kernel/commit/?h=cov/4.8-rc2-testing&id=83b766cafef11c107b10177d0626db311f382299
> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> index eb14f74..bb3b8ad 100644
> --- a/drivers/acpi/pci_mcfg.c
> +++ b/drivers/acpi/pci_mcfg.c
> @@ -42,86 +42,59 @@ struct mcfg_fixup {
> struct resource cfgres;
> };
>
> -#define MCFG_DOM_ANY (-1)
Did you delete this because there were no current users, because you'd
prefer users just use "-1", or for some other reason?
> #define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
> ((end) - (start) + 1), \
> NULL, IORESOURCE_BUS)
> -#define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
> -#define MCFG_RES_EMPTY DEFINE_RES_NAMED(0, 0, NULL, 0)
> +#define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
>
> static struct mcfg_fixup mcfg_quirks[] = {
> -/* { OEM_ID, OEM_TABLE_ID, REV, DOMAIN, BUS_RANGE, cfgres, ops }, */
> +/* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, cfgres, ops }, */
This comment appears to have the order of cfgres and ops reversed.
Am I correct in reading that if a user of the framework does not wish to
override cfgres they must place a struct resource with .start = 0 at the
end of their mcfg_quirks entry? If so, I guess I have the same questions
about removing MCFG_RES_EMPTY as I do about removing MCFG_DOM_ANY.
Thanks,
Cov
^ permalink raw reply
* [RFC 3/4] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
From: Andy Gross @ 2016-09-21 1:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1467938467-21607-4-git-send-email-jmcnicol@redhat.com>
On Thu, Jul 07, 2016 at 05:41:06PM -0700, Jeremy McNicoll wrote:
> From: Bastian K?cher <mail@kchr.de>
>
> Initial device tree support for Qualcomm MSM8994 SoC and
> Huawei Angler / Google Nexus 6P support.
>
> The device tree and the angler_defconfig are based on the
> device tree from the Google 3.10 kernel tree.
>
> The device can be booted into the initrd with only one CPU running.
>
> Signed-off-by: Bastian K?cher <mail@kchr.de>
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> arch/arm64/Kconfig.platforms | 13 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/huawei/Makefile | 5 +
> .../boot/dts/huawei/msm8994-angler-rev-101.dts | 41 ++
There is nothing to warrant having huawei have their own directory unless they
are making their own SOC.
> arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 ++
> arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi | 31 +
> arch/arm64/boot/dts/qcom/msm8994.dtsi | 237 ++++++++
> arch/arm64/configs/angler_defconfig | 666 +++++++++++++++++++++
We don't need to add defconfigs. We just need to turn on the options in the
main defconfig.
Also, when you do have defconfigs, please separate those changes into a separate
patch.
> 8 files changed, 1032 insertions(+)
> create mode 100644 arch/arm64/boot/dts/huawei/Makefile
> create mode 100644 arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
> create mode 100644 arch/arm64/configs/angler_defconfig
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 515e669..f253f60d 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -98,6 +98,19 @@ config MACH_LGE
> help
> This enables support for the LGE Nexus 5X - BullHead MSM8992.
>
> +config ARCH_MSM8994
> + bool "Qualcomm MSM8994"
> + depends on ARCH_QCOM
> + select ARCH_REQUIRE_GPIOLIB
> + help
> + This enables support for the Qualcomm MSM8994
> +
> +config MACH_HUAWEI
> + bool "Huawei Angler (MSM8994)"
> + depends on ARCH_QCOM
> + help
> + This enables support for the Huawei Nexus 6P - Angler MSM8994.
Remove both of these. We aren't adding more ARCHs or machs.
> +
> config ARCH_ROCKCHIP
> bool "Rockchip Platforms"
> select ARCH_HAS_RESET_CONTROLLER
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index bde90fb..d199f8b 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ dts-dirs += cavium
> dts-dirs += exynos
> dts-dirs += freescale
> dts-dirs += hisilicon
> +dts-dirs += huawei
> dts-dirs += marvell
> dts-dirs += mediatek
> dts-dirs += nvidia
> diff --git a/arch/arm64/boot/dts/huawei/Makefile b/arch/arm64/boot/dts/huawei/Makefile
> new file mode 100644
> index 0000000..4b31ff4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/huawei/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_MACH_HUAWEI) += msm8994-angler-rev-101.dtb
> +
> +always := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> new file mode 100644
> index 0000000..07a71d6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/huawei/msm8994-angler-rev-101.dts
> @@ -0,0 +1,41 @@
> +/* Copyright (c) 2015, Huawei Inc. All rights reserved.
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +#include "../qcom/msm8994-v2.0.dtsi"
> +
> +/ {
> + model = "HUAWEI MSM8994 ANGLER rev-1.01";
> + compatible = "qcom,msm8994";
> + qcom,board-id= <8026 0>;
> +};
> +
> +/ {
> + aliases {
> + serial0 = &blsp1_uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0";
> + };
> +
> + soc {
> + serial at f991e000 {
> + status = "okay";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp1_uart2_default>;
> + pinctrl-1 = <&blsp1_uart2_sleep>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> new file mode 100644
> index 0000000..0e4eea0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +&msmgpio {
> + blsp1_uart2_default: blsp1_uart2_default {
> + pinmux {
> + function = "blsp_uart2";
> + pins = "gpio4", "gpio5";
> + };
> + pinconf {
> + pins = "gpio4", "gpio5";
> + drive-strength = <16>;
> + bias-disable;
> + };
> + };
> +
> + blsp1_uart2_sleep: blsp1_uart2_sleep {
> + pinmux {
> + function = "gpio";
> + pins = "gpio4", "gpio5";
> + };
> + pinconf {
> + pins = "gpio4", "gpio5";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> new file mode 100644
> index 0000000..8fc4c41f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> @@ -0,0 +1,31 @@
> +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/*
> + * As a general rule, only version-specific property overrides should be placed
> + * inside this file. Device definitions should be placed inside the msm8994.dtsi
> + * file.
> + */
> +
> +#include "msm8994.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8994v2.0";
> + compatible = "qcom,msm8994";
> + qcom,msm-id = <207 0x20000>;
Drop the msm-id
> +
> +};
> +
> +/* Clock driver overrides */
> +&clock_gcc {
> + compatible = "qcom,gcc-8994v2";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> new file mode 100644
> index 0000000..c95cb73
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> @@ -0,0 +1,237 @@
> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/memreserve/ 0x00000000 0x00001000;
> +/memreserve/ 0xac1c0000 0x00001000;
So the 0x00000000 is totally bogus. And the 0xac1c0000 needs to move to a
reserved area lower in the dts.
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. MSM 8994";
> + compatible = "qcom,msm8994";
> + qcom,msm-id = <207 0x0>;
> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
kill the ids
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> + };
> + };
> +
> + CPU0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0>;
> + next-level-cache = <&L2_0>;
> + // The currents(uA) correspond to the frequencies in the
> + // frequency table.
> + current = < 24140 //384000 kHZ
> + 27200 //460800 kHZ
> + 32300 //600000 kHZ
> + 36940 //672000 kHz
> + 41570 //768000 kHZ
> + 49870 //864000 kHZ
> + 57840 //960000 kHZ
> + 79800 //1248000 kHZ
> + 88810 //1344000 kHZ
> + 102400 //1478400 kHZ
> + 110900>; //1555200 kHZ
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> + };
> +
> + soc: soc { };
> +
> + memory {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the reg */
> + reg = <0 0 0 0>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
Move that reserve down here and make it no-map.
> +
> + smem_mem: smem_region at 0x6a00000 {
> + reg = <0x0 0x6a00000 0x0 0x200000>;
> + no-map;
> + };
> + };
> +};
> +
> +&soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> + compatible = "simple-bus";
> +
> + intc: interrupt-controller at f9000000 {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0xf9000000 0x1000>,
> + <0xf9002000 0x1000>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <1 2 0xff08>,
> + <1 3 0xff08>,
> + <1 4 0xff08>,
> + <1 1 0xff08>;
> + clock-frequency = <19200000>;
> + };
> +
> + timer at f9020000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0xf9020000 0x1000>;
> + clock-frequency = <19200000>;
> +
> + frame at f9021000 {
> + frame-number = <0>;
> + interrupts = <0 9 0x4>,
> + <0 8 0x4>;
> + reg = <0xf9021000 0x1000>,
> + <0xf9022000 0x1000>;
> + };
> +
> + frame at f9023000 {
> + frame-number = <1>;
> + interrupts = <0 10 0x4>;
> + reg = <0xf9023000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame at f9024000 {
> + frame-number = <2>;
> + interrupts = <0 11 0x4>;
> + reg = <0xf9024000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame at f9025000 {
> + frame-number = <3>;
> + interrupts = <0 12 0x4>;
> + reg = <0xf9025000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame at f9026000 {
> + frame-number = <4>;
> + interrupts = <0 13 0x4>;
> + reg = <0xf9026000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame at f9027000 {
> + frame-number = <5>;
> + interrupts = <0 14 0x4>;
> + reg = <0xf9027000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame at f9028000 {
> + frame-number = <6>;
> + interrupts = <0 15 0x4>;
> + reg = <0xf9028000 0x1000>;
> + status = "disabled";
> + };
> + };
> +
> + restart at fc4ab000 {
> + compatible = "qcom,pshold";
> + reg = <0xfc4ab000 0x4>;
> + };
> +
> + msmgpio: pinctrl at fd510000 {
> + compatible = "qcom,msm8994-pinctrl", "qcom,msm8974-pinctrl";
> + reg = <0xfd510000 0x4000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + blsp1_uart2: serial at f991e000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0xf991e000 0x1000>;
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + clock-names = "core", "iface";
> + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
> + <&clock_gcc GCC_BLSP1_AHB_CLK>;
> + };
> +
> + clocks {
> + xo_board: xo_board {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <19200000>;
> + };
> +
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> + };
> +
> + tcsr_mutex_regs: syscon at fd484000 {
> + compatible = "syscon";
> + reg = <0xfd484000 0x2000>;
> + };
> +
> + tcsr_mutex: hwlock {
> + compatible = "qcom,tcsr-mutex";
> + syscon = <&tcsr_mutex_regs 0 0x80>;
> + #hwlock-cells = <1>;
> + };
> +
> + qcom,smem at 6a00000 {
> + compatible = "qcom,smem";
> +
> + memory-region = <&smem_mem>;
> +
> + hwlocks = <&tcsr_mutex 3>;
> + };
> +
> + clock_gcc: qcom,gcc at fc400000 {
> + compatible = "qcom,gcc-8994";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + reg = <0xfc400000 0x2000>;
> + };
> +
> +};
> +
> +#include "msm8994-pins.dtsi"
> diff --git a/arch/arm64/configs/angler_defconfig b/arch/arm64/configs/angler_defconfig
> new file mode 100644
> index 0000000..00cf192
> --- /dev/null
> +++ b/arch/arm64/configs/angler_defconfig
> @@ -0,0 +1,666 @@
> +CONFIG_AUDIT=y
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_IRQ_TIME_ACCOUNTING=y
> +CONFIG_RCU_FAST_NO_HZ=y
> +CONFIG_LOG_BUF_SHIFT=20
> +CONFIG_CGROUPS=y
> +CONFIG_CGROUP_DEBUG=y
> +CONFIG_CGROUP_FREEZER=y
> +CONFIG_CPUSETS=y
> +CONFIG_CGROUP_CPUACCT=y
> +CONFIG_RESOURCE_COUNTERS=y
> +CONFIG_CGROUP_SCHED=y
> +CONFIG_CFS_BANDWIDTH=y
> +CONFIG_RT_GROUP_SCHED=y
> +CONFIG_SCHED_HMP=y
> +CONFIG_NAMESPACES=y
> +# CONFIG_UTS_NS is not set
> +# CONFIG_PID_NS is not set
> +CONFIG_BLK_DEV_INITRD=y
> +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> +CONFIG_PANIC_TIMEOUT=5
> +CONFIG_KALLSYMS_ALL=y
> +# CONFIG_PCI_QUIRKS is not set
> +CONFIG_EMBEDDED=y
> +# CONFIG_SLUB_DEBUG is not set
> +CONFIG_PROFILING=y
> +CONFIG_PARTITION_ADVANCED=y
> +CONFIG_ARCH_MSM=y
> +CONFIG_ARCH_MSM8994=y
> +CONFIG_ARCH_MSM8994_V1_TLBI_WA=y
> +CONFIG_PCI_MSM=y
> +CONFIG_ARM64_A57_ERRATA_832075=y
> +CONFIG_SMP=y
> +CONFIG_SCHED_MC=y
> +CONFIG_ARCH_WANTS_CTXSW_LOGGING=y
> +CONFIG_PREEMPT=y
> +CONFIG_ARMV7_COMPAT=y
> +CONFIG_BALANCE_ANON_FILE_RECLAIM=y
> +CONFIG_ZSMALLOC=y
> +CONFIG_SECCOMP=y
> +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
> +# CONFIG_COREDUMP is not set
> +CONFIG_COMPAT=y
> +CONFIG_PM_AUTOSLEEP=y
> +CONFIG_PM_WAKELOCKS=y
> +CONFIG_PM_WAKELOCKS_LIMIT=0
> +CONFIG_PM_RUNTIME=y
> +CONFIG_SUSPEND_TIME=y
> +CONFIG_CPU_FREQ=y
> +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
> +CONFIG_CPU_FREQ_GOV_USERSPACE=y
> +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
> +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
> +CONFIG_CPU_BOOST=y
> +CONFIG_CPU_IDLE=y
> +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
> +# CONFIG_CPU_IDLE_GOV_LADDER is not set
> +# CONFIG_CPU_IDLE_GOV_MENU is not set
> +CONFIG_NET=y
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_XFRM_USER=y
> +CONFIG_XFRM_STATISTICS=y
> +CONFIG_NET_KEY=y
> +CONFIG_INET=y
> +CONFIG_IP_ADVANCED_ROUTER=y
> +CONFIG_IP_MULTIPLE_TABLES=y
> +CONFIG_IP_ROUTE_VERBOSE=y
> +CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_INET_AH=y
> +CONFIG_INET_ESP=y
> +CONFIG_INET_IPCOMP=y
> +# CONFIG_INET_XFRM_MODE_BEET is not set
> +# CONFIG_INET_LRO is not set
> +CONFIG_IPV6_PRIVACY=y
> +CONFIG_IPV6_ROUTER_PREF=y
> +CONFIG_IPV6_ROUTE_INFO=y
> +CONFIG_IPV6_OPTIMISTIC_DAD=y
> +CONFIG_INET6_AH=y
> +CONFIG_INET6_ESP=y
> +CONFIG_INET6_IPCOMP=y
> +CONFIG_IPV6_MIP6=y
> +CONFIG_IPV6_MULTIPLE_TABLES=y
> +CONFIG_IPV6_SUBTREES=y
> +CONFIG_NETFILTER=y
> +CONFIG_NF_CONNTRACK=y
> +CONFIG_NF_CONNTRACK_EVENTS=y
> +CONFIG_NF_CT_PROTO_DCCP=y
> +CONFIG_NF_CT_PROTO_SCTP=y
> +CONFIG_NF_CT_PROTO_UDPLITE=y
> +CONFIG_NF_CONNTRACK_AMANDA=y
> +CONFIG_NF_CONNTRACK_FTP=y
> +CONFIG_NF_CONNTRACK_H323=y
> +CONFIG_NF_CONNTRACK_IRC=y
> +CONFIG_NF_CONNTRACK_NETBIOS_NS=y
> +CONFIG_NF_CONNTRACK_PPTP=y
> +CONFIG_NF_CONNTRACK_SANE=y
> +CONFIG_NF_CONNTRACK_SIP=y
> +CONFIG_NF_CONNTRACK_TFTP=y
> +CONFIG_NF_CT_NETLINK=y
> +CONFIG_NETFILTER_TPROXY=y
> +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
> +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
> +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
> +CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y
> +CONFIG_NETFILTER_XT_TARGET_LOG=y
> +CONFIG_NETFILTER_XT_TARGET_MARK=y
> +CONFIG_NETFILTER_XT_TARGET_NFLOG=y
> +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
> +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
> +CONFIG_NETFILTER_XT_TARGET_TEE=y
> +CONFIG_NETFILTER_XT_TARGET_TPROXY=y
> +CONFIG_NETFILTER_XT_TARGET_TRACE=y
> +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
> +CONFIG_NETFILTER_XT_MATCH_COMMENT=y
> +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
> +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
> +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
> +CONFIG_NETFILTER_XT_MATCH_DSCP=y
> +CONFIG_NETFILTER_XT_MATCH_ESP=y
> +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
> +CONFIG_NETFILTER_XT_MATCH_HELPER=y
> +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
> +CONFIG_NETFILTER_XT_MATCH_LENGTH=y
> +CONFIG_NETFILTER_XT_MATCH_LIMIT=y
> +CONFIG_NETFILTER_XT_MATCH_MAC=y
> +CONFIG_NETFILTER_XT_MATCH_MARK=y
> +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
> +CONFIG_NETFILTER_XT_MATCH_POLICY=y
> +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
> +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
> +CONFIG_NETFILTER_XT_MATCH_QUOTA=y
> +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
> +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
> +CONFIG_NETFILTER_XT_MATCH_SOCKET=y
> +CONFIG_NETFILTER_XT_MATCH_STATE=y
> +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
> +CONFIG_NETFILTER_XT_MATCH_STRING=y
> +CONFIG_NETFILTER_XT_MATCH_TIME=y
> +CONFIG_NETFILTER_XT_MATCH_U32=y
> +CONFIG_NF_CONNTRACK_IPV4=y
> +CONFIG_IP_NF_IPTABLES=y
> +CONFIG_IP_NF_MATCH_AH=y
> +CONFIG_IP_NF_MATCH_ECN=y
> +CONFIG_IP_NF_MATCH_TTL=y
> +CONFIG_IP_NF_FILTER=y
> +CONFIG_IP_NF_TARGET_REJECT=y
> +CONFIG_IP_NF_TARGET_REJECT_SKERR=y
> +CONFIG_NF_NAT_IPV4=y
> +CONFIG_IP_NF_TARGET_MASQUERADE=y
> +CONFIG_IP_NF_TARGET_NETMAP=y
> +CONFIG_IP_NF_TARGET_REDIRECT=y
> +CONFIG_IP_NF_MANGLE=y
> +CONFIG_IP_NF_RAW=y
> +CONFIG_IP_NF_SECURITY=y
> +CONFIG_IP_NF_ARPTABLES=y
> +CONFIG_IP_NF_ARPFILTER=y
> +CONFIG_IP_NF_ARP_MANGLE=y
> +CONFIG_NF_CONNTRACK_IPV6=y
> +CONFIG_IP6_NF_IPTABLES=y
> +CONFIG_IP6_NF_FILTER=y
> +CONFIG_IP6_NF_TARGET_REJECT=y
> +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
> +CONFIG_IP6_NF_MANGLE=y
> +CONFIG_IP6_NF_RAW=y
> +CONFIG_BRIDGE_NF_EBTABLES=y
> +CONFIG_BRIDGE_EBT_BROUTE=y
> +CONFIG_L2TP=y
> +CONFIG_L2TP_DEBUGFS=y
> +CONFIG_L2TP_V3=y
> +CONFIG_L2TP_IP=y
> +CONFIG_L2TP_ETH=y
> +CONFIG_BRIDGE=y
> +CONFIG_NET_SCHED=y
> +CONFIG_NET_SCH_HTB=y
> +CONFIG_NET_SCH_PRIO=y
> +CONFIG_NET_CLS_FW=y
> +CONFIG_NET_CLS_U32=y
> +CONFIG_CLS_U32_MARK=y
> +CONFIG_NET_CLS_FLOW=y
> +CONFIG_NET_EMATCH=y
> +CONFIG_NET_EMATCH_CMP=y
> +CONFIG_NET_EMATCH_NBYTE=y
> +CONFIG_NET_EMATCH_U32=y
> +CONFIG_NET_EMATCH_META=y
> +CONFIG_NET_EMATCH_TEXT=y
> +CONFIG_NET_CLS_ACT=y
> +CONFIG_RMNET_DATA=y
> +CONFIG_RMNET_DATA_FC=y
> +CONFIG_RMNET_DATA_DEBUG_PKT=y
> +CONFIG_SOCKEV_NLMCAST=y
> +CONFIG_BT=y
> +CONFIG_BT_RFCOMM=y
> +CONFIG_BT_RFCOMM_TTY=y
> +CONFIG_BT_BNEP=y
> +CONFIG_BT_BNEP_MC_FILTER=y
> +CONFIG_BT_BNEP_PROTO_FILTER=y
> +CONFIG_BT_HIDP=y
> +CONFIG_MSM_BT_BLUESLEEP=y
> +CONFIG_CFG80211=y
> +CONFIG_CFG80211_INTERNAL_REGDB=y
> +CONFIG_RFKILL=y
> +CONFIG_NFC=y
> +CONFIG_NFC_PN548=y
> +CONFIG_IPC_ROUTER=y
> +CONFIG_IPC_ROUTER_SECURITY=y
> +CONFIG_CMA=y
> +CONFIG_CMA_SIZE_MBYTES=32
> +CONFIG_ARM_CCI=y
> +CONFIG_ZRAM=y
> +CONFIG_ZRAM_LZ4_COMPRESS=y
> +CONFIG_BLK_DEV_LOOP=y
> +CONFIG_BLK_DEV_RAM=y
> +CONFIG_UID_STAT=y
> +CONFIG_QSEECOM=y
> +CONFIG_TI_DRV2667=y
> +CONFIG_UID_CPUTIME=y
> +CONFIG_WIFI_SAR=y
> +CONFIG_SCSI=y
> +CONFIG_SCSI_TGT=y
> +CONFIG_BLK_DEV_SD=y
> +CONFIG_CHR_DEV_SG=y
> +CONFIG_SCSI_MULTI_LUN=y
> +CONFIG_SCSI_CONSTANTS=y
> +CONFIG_SCSI_LOGGING=y
> +CONFIG_SCSI_SCAN_ASYNC=y
> +# CONFIG_SCSI_LOWLEVEL is not set
> +CONFIG_MD=y
> +CONFIG_BLK_DEV_DM=y
> +CONFIG_DM_CRYPT=y
> +CONFIG_DM_REQ_CRYPT=y
> +CONFIG_DM_VERITY=y
> +CONFIG_NETDEVICES=y
> +CONFIG_DUMMY=y
> +CONFIG_TUN=y
> +# CONFIG_ETHERNET is not set
> +CONFIG_PPP=y
> +CONFIG_PPP_BSDCOMP=y
> +CONFIG_PPP_DEFLATE=y
> +CONFIG_PPP_FILTER=y
> +CONFIG_PPP_MPPE=y
> +CONFIG_PPP_MULTILINK=y
> +CONFIG_PPPOE=y
> +CONFIG_PPPOL2TP=y
> +CONFIG_PPPOLAC=y
> +CONFIG_PPPOPNS=y
> +CONFIG_PPP_ASYNC=y
> +CONFIG_PPP_SYNC_TTY=y
> +CONFIG_USB_KAWETH=y
> +CONFIG_USB_PEGASUS=y
> +CONFIG_USB_RTL8150=y
> +CONFIG_USB_RTL8152=y
> +CONFIG_USB_USBNET=y
> +# CONFIG_USB_NET_CDC_NCM is not set
> +# CONFIG_USB_NET_NET1080 is not set
> +# CONFIG_USB_NET_CDC_SUBSET is not set
> +# CONFIG_USB_NET_ZAURUS is not set
> +CONFIG_CLD_LL_CORE=y
> +CONFIG_BCMDHD=y
> +CONFIG_BCMDHD_PCIE=y
> +CONFIG_BCM4358=y
> +CONFIG_BCMDHD_FW_PATH="/vendor/firmware/fw_bcmdhd.bin"
> +CONFIG_DHD_USE_STATIC_BUF=y
> +CONFIG_DHD_USE_SCHED_SCAN=y
> +CONFIG_DHD_OF_SUPPORT=y
> +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> +CONFIG_INPUT_EVDEV=y
> +# CONFIG_KEYBOARD_ATKBD is not set
> +CONFIG_KEYBOARD_GPIO=y
> +# CONFIG_INPUT_MOUSE is not set
> +CONFIG_INPUT_JOYSTICK=y
> +CONFIG_JOYSTICK_XPAD=y
> +CONFIG_JOYSTICK_XPAD_FF=y
> +CONFIG_JOYSTICK_XPAD_LEDS=y
> +CONFIG_INPUT_TABLET=y
> +CONFIG_TABLET_USB_ACECAD=y
> +CONFIG_TABLET_USB_AIPTEK=y
> +CONFIG_TABLET_USB_GTCO=y
> +CONFIG_TABLET_USB_HANWANG=y
> +CONFIG_TABLET_USB_KBTAB=y
> +CONFIG_TABLET_USB_WACOM=y
> +CONFIG_INPUT_TOUCHSCREEN=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEVICETREE_SUPPORT=y
> +# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_PROXIMITY is not set
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_BINARY_FW_UPGRADE=y
> +CONFIG_TOUCHSCREEN_HUAWEI_CYTTSP4_RECOVERY_FW_UPDATE=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_MANUAL_TTCONFIG_UPGRADE=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_USE_FW_BIN_FILE=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEVICE_ACCESS=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_LOADER=y
> +CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP4_DEBUG_MODULE=y
> +CONFIG_TOUCHSCREEN_GEN_VKEYS=y
> +CONFIG_SECURE_TOUCH=y
> +CONFIG_TOUCHSCREEN_HUAWEI_SYNAPTICS_DSX_v25=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_CORE=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_RMI_DEV=y
> +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX25_FW_UPDATE=y
> +CONFIG_INPUT_MISC=y
> +CONFIG_INPUT_KEYCHORD=y
> +CONFIG_INPUT_UINPUT=y
> +CONFIG_INPUT_GPIO=y
> +CONFIG_LASER_STMVL6180=y
> +CONFIG_RF_DETECT=y
> +# CONFIG_SERIO is not set
> +CONFIG_FINGERPRINT_FPC=y
> +# CONFIG_VT is not set
> +# CONFIG_LEGACY_PTYS is not set
> +# CONFIG_DEVMEM is not set
> +# CONFIG_DEVKMEM is not set
> +CONFIG_SERIAL_MSM_HS=y
> +CONFIG_SERIAL_MSM_HSL=y
> +CONFIG_SERIAL_MSM_HSL_CONSOLE=y
> +CONFIG_SERIAL_MSM_SMD=y
> +CONFIG_HW_RANDOM_MSM=y
> +CONFIG_MSM_SMD_PKT=y
> +CONFIG_MSM_ADSPRPC=y
> +CONFIG_I2C_CHARDEV=y
> +CONFIG_I2C_MSM_V2=y
> +CONFIG_SLIMBUS_MSM_NGD=y
> +CONFIG_SPI=y
> +CONFIG_SPI_CONTEXTHUB=y
> +CONFIG_SPI_QUP=y
> +CONFIG_SPMI=y
> +CONFIG_SPMI_MSM_PMIC_ARB=y
> +CONFIG_MSM_QPNP_INT=y
> +CONFIG_USE_PINCTRL_IRQ=y
> +CONFIG_GPIO_SYSFS=y
> +CONFIG_GPIO_QPNP_PIN=y
> +CONFIG_SMB349_DUAL_CHARGER=y
> +CONFIG_SMB1351_USB_CHARGER=y
> +CONFIG_QPNP_SMBCHARGER=y
> +CONFIG_QPNP_FG=y
> +CONFIG_BATTERY_BCL=y
> +CONFIG_MSM_BCL_CTL=y
> +CONFIG_MSM_BCL_PERIPHERAL_CTL=y
> +CONFIG_POWER_RESET_MSM=y
> +CONFIG_MSM_DLOAD_MODE=y
> +CONFIG_MSM_PM=y
> +CONFIG_APSS_CORE_EA=y
> +CONFIG_SENSORS_EPM_ADC=y
> +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
> +CONFIG_THERMAL=y
> +CONFIG_THERMAL_TSENS8974=y
> +CONFIG_LIMITS_MONITOR=y
> +CONFIG_LIMITS_LITE_HW=y
> +CONFIG_THERMAL_MONITOR=y
> +CONFIG_THERMAL_QPNP=y
> +CONFIG_THERMAL_QPNP_ADC_TM=y
> +CONFIG_WCD9330_CODEC=y
> +CONFIG_REGULATOR=y
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> +CONFIG_REGULATOR_PROXY_CONSUMER=y
> +CONFIG_REGULATOR_MEM_ACC=y
> +CONFIG_REGULATOR_TPS65132=y
> +CONFIG_REGULATOR_STUB=y
> +CONFIG_REGULATOR_RPM_SMD=y
> +CONFIG_REGULATOR_QPNP=y
> +CONFIG_REGULATOR_QPNP_LABIBB=y
> +CONFIG_REGULATOR_SPM=y
> +CONFIG_REGULATOR_CPR=y
> +CONFIG_MEDIA_SUPPORT=y
> +CONFIG_MEDIA_CAMERA_SUPPORT=y
> +CONFIG_MEDIA_RADIO_SUPPORT=y
> +CONFIG_MEDIA_CONTROLLER=y
> +CONFIG_VIDEO_V4L2_SUBDEV_API=y
> +CONFIG_VIDEOBUF2_MSM_MEM=y
> +CONFIG_MEDIA_USB_SUPPORT=y
> +CONFIG_USB_VIDEO_CLASS=y
> +# CONFIG_USB_GSPCA is not set
> +CONFIG_V4L_PLATFORM_DRIVERS=y
> +CONFIG_MSMB_CAMERA=y
> +CONFIG_MSM_CAMERA_SENSOR=y
> +CONFIG_MSM_CPP=y
> +CONFIG_MSM_CCI=y
> +CONFIG_MSM_CSI30_HEADER=y
> +CONFIG_MSM_CSIPHY=y
> +CONFIG_MSM_CSID=y
> +CONFIG_MSM_EEPROM=y
> +CONFIG_MSM_ISPIF=y
> +CONFIG_HI256=y
> +CONFIG_MT9M114=y
> +CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
> +CONFIG_MSMB_JPEG=y
> +CONFIG_MSM_FD=y
> +CONFIG_MSM_VIDC_V4L2=y
> +CONFIG_TSPP=y
> +# CONFIG_RADIO_ADAPTERS is not set
> +# CONFIG_VGA_ARB is not set
> +CONFIG_MSM_KGSL=y
> +CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
> +CONFIG_FB=y
> +CONFIG_FB_MSM=y
> +CONFIG_FB_MSM_MDSS=y
> +CONFIG_FB_MSM_MDSS_WRITEBACK=y
> +CONFIG_SOUND=y
> +CONFIG_SND=y
> +CONFIG_SND_MPU401=y
> +# CONFIG_SND_PCI is not set
> +# CONFIG_SND_SPI is not set
> +CONFIG_SND_USB_AUDIO=y
> +CONFIG_SND_SOC=y
> +CONFIG_SND_SOC_MSM8994=y
> +CONFIG_SND_SOC_MAX98925=y
> +CONFIG_HID_BATTERY_STRENGTH=y
> +CONFIG_HIDRAW=y
> +CONFIG_UHID=y
> +CONFIG_HID_A4TECH=y
> +CONFIG_HID_APPLE=y
> +CONFIG_HID_BELKIN=y
> +CONFIG_HID_CHERRY=y
> +CONFIG_HID_CHICONY=y
> +CONFIG_HID_PRODIKEYS=y
> +CONFIG_HID_CYPRESS=y
> +CONFIG_HID_ELECOM=y
> +CONFIG_HID_EZKEY=y
> +CONFIG_HID_HOLTEK=y
> +CONFIG_HOLTEK_FF=y
> +CONFIG_HID_KEYTOUCH=y
> +CONFIG_HID_KYE=y
> +CONFIG_HID_UCLOGIC=y
> +CONFIG_HID_WALTOP=y
> +CONFIG_HID_GYRATION=y
> +CONFIG_HID_ICADE=y
> +CONFIG_HID_KENSINGTON=y
> +CONFIG_HID_LCPOWER=y
> +CONFIG_HID_LENOVO_TPKBD=y
> +CONFIG_HID_LOGITECH=y
> +CONFIG_HID_LOGITECH_DJ=y
> +CONFIG_LOGITECH_FF=y
> +CONFIG_LOGIRUMBLEPAD2_FF=y
> +CONFIG_LOGIG940_FF=y
> +CONFIG_HID_MAGICMOUSE=y
> +CONFIG_HID_MICROSOFT=y
> +CONFIG_HID_MONTEREY=y
> +CONFIG_HID_MULTITOUCH=y
> +CONFIG_HID_NTRIG=y
> +CONFIG_HID_ORTEK=y
> +CONFIG_HID_PANTHERLORD=y
> +CONFIG_PANTHERLORD_FF=y
> +CONFIG_HID_PRIMAX=y
> +CONFIG_HID_PS3REMOTE=y
> +CONFIG_HID_ROCCAT=y
> +CONFIG_HID_SAITEK=y
> +CONFIG_HID_SAMSUNG=y
> +CONFIG_HID_SONY=y
> +CONFIG_HID_SPEEDLINK=y
> +CONFIG_HID_STEELSERIES=y
> +CONFIG_HID_SUNPLUS=y
> +CONFIG_HID_SMARTJOYPLUS=y
> +CONFIG_SMARTJOYPLUS_FF=y
> +CONFIG_HID_TOPSEED=y
> +CONFIG_HID_THINGM=y
> +CONFIG_HID_THRUSTMASTER=y
> +CONFIG_THRUSTMASTER_FF=y
> +CONFIG_HID_WACOM=y
> +CONFIG_HID_WIIMOTE=y
> +CONFIG_HID_ZEROPLUS=y
> +CONFIG_ZEROPLUS_FF=y
> +CONFIG_HID_SENSOR_HUB=y
> +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_EHSET=y
> +CONFIG_USB_EHCI_MSM=y
> +CONFIG_USB_ACM=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_SERIAL=y
> +CONFIG_USB_SERIAL_GENERIC=y
> +CONFIG_USB_SERIAL_FTDI_SIO=y
> +CONFIG_USB_SERIAL_PL2303=y
> +CONFIG_USB_EMI62=y
> +CONFIG_USB_EMI26=y
> +CONFIG_USB_EHSET_TEST_FIXTURE=y
> +CONFIG_USB_PHY=y
> +CONFIG_USB_MSM_SSPHY_QMP=y
> +CONFIG_MSM_QUSB_PHY=y
> +CONFIG_DUAL_ROLE_USB_INTF=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_DEBUG_FILES=y
> +CONFIG_USB_GADGET_DEBUG_FS=y
> +CONFIG_USB_CI13XXX_MSM=y
> +CONFIG_USB_DWC3_MSM=y
> +CONFIG_USB_G_ANDROID=y
> +CONFIG_TYPEC=y
> +CONFIG_TUSB320_TYPEC=y
> +CONFIG_MMC=y
> +CONFIG_MMC_PERF_PROFILING=y
> +CONFIG_MMC_UNSAFE_RESUME=y
> +CONFIG_MMC_CLKGATE=y
> +CONFIG_MMC_PARANOID_SD_INIT=y
> +CONFIG_MMC_BLOCK_MINORS=32
> +CONFIG_MMC_TEST=y
> +CONFIG_MMC_BLOCK_TEST=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_MSM=y
> +CONFIG_LEDS_QPNP=y
> +CONFIG_LEDS_QPNP_FLASH=y
> +CONFIG_LEDS_QPNP_WLED=y
> +CONFIG_LEDS_TRIGGERS=y
> +CONFIG_LEDS_TRIGGER_BACKLIGHT=y
> +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> +CONFIG_SWITCH=y
> +CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_QPNP=y
> +CONFIG_DMADEVICES=y
> +CONFIG_QCOM_SPS_DMA=y
> +CONFIG_UIO=y
> +CONFIG_UIO_MSM_SHAREDMEM=y
> +CONFIG_STAGING=y
> +CONFIG_ANDROID=y
> +CONFIG_ANDROID_BINDER_IPC=y
> +CONFIG_ASHMEM=y
> +CONFIG_ANDROID_LOGGER=y
> +CONFIG_ANDROID_LOW_MEMORY_KILLER=y
> +CONFIG_ANDROID_INTF_ALARM_DEV=y
> +CONFIG_ONESHOT_SYNC=y
> +CONFIG_ION=y
> +CONFIG_ION_MSM=y
> +CONFIG_ALLOC_BUFFERS_IN_4K_CHUNKS=y
> +# CONFIG_NET_VENDOR_SILICOM is not set
> +CONFIG_SPS=y
> +CONFIG_USB_BAM=y
> +CONFIG_SPS_SUPPORT_NDP_BAM=y
> +CONFIG_QPNP_POWER_ON=y
> +CONFIG_QPNP_REVID=y
> +CONFIG_QPNP_COINCELL=y
> +CONFIG_QPNP_USB_DETECT=y
> +CONFIG_IPA=y
> +CONFIG_RMNET_IPA=y
> +CONFIG_MSM_AVTIMER=y
> +CONFIG_PFT=y
> +CONFIG_MSM_BUS_SCALING=y
> +CONFIG_MSM_BUSPM_DEV=y
> +CONFIG_BUS_TOPOLOGY_ADHOC=y
> +CONFIG_DEBUG_BUS_VOTER=y
> +CONFIG_QPNP_HAPTIC=y
> +CONFIG_MSM_MDSS_PLL=y
> +CONFIG_REMOTE_SPINLOCK_MSM=y
> +CONFIG_MSM_IOMMU_V1=y
> +CONFIG_MSM_IOMMU_VBIF_CHECK=y
> +CONFIG_IOMMU_FORCE_4K_MAPPINGS=y
> +CONFIG_DEVFREQ_SPDM=y
> +CONFIG_PWM=y
> +CONFIG_PWM_QPNP=y
> +CONFIG_SENSORS_SSC=y
> +CONFIG_GENERIC_PHY=y
> +CONFIG_CP_ACCESS64=y
> +CONFIG_MSM_EVENT_TIMER=y
> +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
> +CONFIG_MSM_QMI_INTERFACE=y
> +CONFIG_MSM_SMD_DEBUG=y
> +CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y
> +CONFIG_MSM_RPM_LOG=y
> +CONFIG_MSM_RPM_STATS_LOG=y
> +CONFIG_MSM_RUN_QUEUE_STATS=y
> +CONFIG_MSM_SMEM_LOGGING=y
> +CONFIG_MSM_SMP2P=y
> +CONFIG_MSM_SMP2P_TEST=y
> +CONFIG_MSM_SPM=y
> +CONFIG_MSM_L2_SPM=y
> +CONFIG_MSM_ADSP_LOADER=y
> +CONFIG_MSM_MEMORY_DUMP_V2=y
> +CONFIG_MSM_DEBUG_LAR_UNLOCK=y
> +CONFIG_MSM_DDR_HEALTH=y
> +CONFIG_MSM_COMMON_LOG=y
> +CONFIG_MSM_WATCHDOG_V2=y
> +CONFIG_MSM_FORCE_WDOG_BITE_ON_PANIC=y
> +CONFIG_MSM_HVC=y
> +CONFIG_MSM_SUBSYSTEM_RESTART=y
> +CONFIG_MSM_SYSMON_COMM=y
> +CONFIG_MSM_PIL=y
> +CONFIG_MSM_PIL_SSR_GENERIC=y
> +CONFIG_MSM_PIL_MSS_QDSP6V5=y
> +CONFIG_MSM_OCMEM=y
> +CONFIG_MSM_OCMEM_LOCAL_POWER_CTRL=y
> +CONFIG_MSM_OCMEM_DEBUG=y
> +CONFIG_MSM_BOOT_STATS=y
> +CONFIG_MSM_SCM=y
> +CONFIG_MSM_XPU_ERR_FATAL=y
> +CONFIG_MSM_CPUSS_DUMP=y
> +CONFIG_MSM_SHARED_HEAP_ACCESS=y
> +CONFIG_MSM_SYSTEM_HEALTH_MONITOR=y
> +CONFIG_QCOM_EARLY_RANDOM=y
> +CONFIG_MSM_PERFORMANCE=y
> +CONFIG_QCOM_NPA_DUMP=y
> +CONFIG_MSM_TZ_LOG=y
> +CONFIG_EXT4_FS=y
> +CONFIG_EXT4_FS_SECURITY=y
> +CONFIG_EXT4_FS_ENCRYPTION=y
> +CONFIG_FUSE_FS=y
> +CONFIG_VFAT_FS=y
> +CONFIG_TMPFS=y
> +CONFIG_TMPFS_POSIX_ACL=y
> +CONFIG_PSTORE=y
> +CONFIG_PSTORE_CONSOLE=y
> +CONFIG_PSTORE_PMSG=y
> +CONFIG_PSTORE_RAM=y
> +# CONFIG_NETWORK_FILESYSTEMS is not set
> +CONFIG_NLS_CODEPAGE_437=y
> +CONFIG_NLS_ASCII=y
> +CONFIG_NLS_ISO8859_1=y
> +CONFIG_NLS_UTF8=y
> +CONFIG_PRINTK_TIME=y
> +CONFIG_MAGIC_SYSRQ=y
> +CONFIG_PAGE_OWNER=y
> +# CONFIG_SYSRQ_SCHED_DEBUG is not set
> +CONFIG_SCHEDSTATS=y
> +CONFIG_TIMER_STATS=y
> +CONFIG_DEBUG_INFO=y
> +CONFIG_RCU_CPU_STALL_INFO=y
> +CONFIG_RCU_TRACE=y
> +CONFIG_IPC_LOGGING=y
> +CONFIG_BLK_DEV_IO_TRACE=y
> +CONFIG_DYNAMIC_DEBUG=y
> +CONFIG_OOPS_LOG_BUFFER=y
> +CONFIG_LOG_BUF_MAGIC=y
> +CONFIG_OOPS_LOG_BUF_SHIFT=17
> +CONFIG_PANIC_ON_DATA_CORRUPTION=y
> +CONFIG_ARM64_PTDUMP=y
> +CONFIG_PID_IN_CONTEXTIDR=y
> +CONFIG_SECURITY=y
> +CONFIG_SECURITY_NETWORK=y
> +CONFIG_LSM_MMAP_MIN_ADDR=4096
> +CONFIG_SECURITY_SELINUX=y
> +CONFIG_CRYPTO_NULL=y
> +CONFIG_CRYPTO_XCBC=y
> +CONFIG_CRYPTO_MD4=y
> +CONFIG_CRYPTO_TWOFISH=y
> +CONFIG_CRYPTO_DEV_QCRYPTO=y
> +CONFIG_CRYPTO_DEV_QCE=y
> +CONFIG_CRYPTO_DEV_QCEDEV=y
> +CONFIG_CRYPTO_DEV_QCOM_ICE=y
> +CONFIG_ASYMMETRIC_KEY_TYPE=y
> +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
> +CONFIG_PUBLIC_KEY_ALGO_RSA=y
> +CONFIG_X509_CERTIFICATE_PARSER=y
> +CONFIG_ARM64_CRYPTO=y
> +CONFIG_CRYPTO_SHA1_ARM64_CE=y
> +CONFIG_CRYPTO_SHA2_ARM64_CE=y
> +CONFIG_CRYPTO_GHASH_ARM64_CE=y
> +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
> +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
> +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
> +CONFIG_QMI_ENCDEC=y
> +CONFIG_STRICT_MEMORY_RWX=y
> +CONFIG_ARM_APPENDED_DTB=y
> +CONFIG_ARM_ATAG_DTB_COMPAT=y
> +CONFIG_ARCH_QCOM=y
> +CONFIG_QCOM_SMD_RPM=y
> +CONFIG_QCOM_SMEM=y
> +CONFIG_QCOM_SMD=y
> +CONFIG_HWSPINLOCK_QCOM=y
> +CONFIG_QCOM_PM=y
> +CONFIG_SERIAL_MSM=y
> +CONFIG_SERIAL_MSM_CONSOLE=y
> +CONFIG_PINCTRL_MSM8X74=y
> +CONFIG_COMMON_CLK_QCOM=y
> +CONFIG_MSM_GCC_8994=y
> +CONFIG_MACH_HUAWEI=y
> +CONFIG_DEVTMPFS=y
> +CONFIG_DMA_CMA=y
> --
> 2.6.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
From: Jeremy McNicoll @ 2016-09-21 0:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160708174125.GC7896@hector.attlocal.net>
On 2016-07-08 10:41 AM, Andy Gross wrote:
> On Thu, Jul 07, 2016 at 05:41:04PM -0700, Jeremy McNicoll wrote:
>> Initial device tree support for Qualcomm MSM8992 SoC and
>> LG Bullhead / Google Nexus 5X support.
>>
Hopefully that was enough time for people to enjoy their summer
vacations and welcome new additions to the family.
>> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
>> ---
>> arch/arm64/Kconfig.platforms | 12 +
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/lge/Makefile | 5 +
>> .../boot/dts/lge/msm8992-bullhead-rev-101.dts | 41 +++
>> arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 +++
>> arch/arm64/boot/dts/qcom/msm8992.dtsi | 221 ++++++++++++
>> arch/arm64/configs/bullhead_defconfig | 377 +++++++++++++++++++++
>> arch/arm64/configs/msm8992_defconfig | 5 +
>> 8 files changed, 700 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/lge/Makefile
>> create mode 100644 arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi
>> create mode 100644 arch/arm64/configs/bullhead_defconfig
>> create mode 100644 arch/arm64/configs/msm8992_defconfig
>>
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 7ef1d05..515e669 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -86,6 +86,18 @@ config ARCH_QCOM
>> help
>> This enables support for the ARMv8 based Qualcomm chipsets.
>>
>> +config ARCH_MSM8992
>> + bool "Qualcomm MSM8992"
>> + depends on ARCH_QCOM
>> + help
>> + This enables support for the Qualcomm MSM8992 SoC.
>> +
>> +config MACH_LGE
>> + bool "LGE BullHead (MSM8992)"
>> + depends on ARCH_QCOM
>> + help
>> + This enables support for the LGE Nexus 5X - BullHead MSM8992.
>
> We don't add config options for End users. Only for Soc Companies or people
> actually producing the silicon.
>
removed.
>> +
>> config ARCH_ROCKCHIP
>> bool "Rockchip Platforms"
>> select ARCH_HAS_RESET_CONTROLLER
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index 6e199c9..bde90fb 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -13,6 +13,7 @@ dts-dirs += marvell
>> dts-dirs += mediatek
>> dts-dirs += nvidia
>> dts-dirs += qcom
>> +dts-dirs += lge
>
> No, please add the files to the qcom directory.
>
ok, done
>> dts-dirs += renesas
>> dts-dirs += rockchip
>> dts-dirs += socionext
>> diff --git a/arch/arm64/boot/dts/lge/Makefile b/arch/arm64/boot/dts/lge/Makefile
>> new file mode 100644
>> index 0000000..f4e7860
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/lge/Makefile
>> @@ -0,0 +1,5 @@
>> +dtb-$(CONFIG_MACH_LGE) += msm8992-bullhead-rev-101.dtb
>> +
>> +always := $(dtb-y)
>> +subdir-y := $(dts-dirs)
>> +clean-files := *.dtb
>> diff --git a/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
>> new file mode 100644
>> index 0000000..860cded
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/lge/msm8992-bullhead-rev-101.dts
>> @@ -0,0 +1,41 @@
>> +/* Copyright (c) 2015, LGE Inc. All rights reserved.
>> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "../qcom/msm8992.dtsi"
>> +
>> +/ {
>> + model = "LGE MSM8992 BULLHEAD rev-1.01";
>> + compatible = "qcom,msm8992";
>> + qcom,board-id = <0xb64 0>;
>
> Please work with sboyd to add the board-id to the dtbTool. We don't put
> board-ids in the dts file. We post-process the dtb file and add them then.
>
sboyd has all the info he needs for this, I believe its just with legal
now. Will remove for V2.
It would be nice if we could get this dtbTool to automagically run as
part of the build system.
>
>> +};
>> +
>> +/ {
>> + aliases {
>> + serial0 = &blsp1_uart2;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0";
>> + };
>> +
>> + soc {
>> + serial at f991e000 {
>> + status = "okay";
>> + pinctrl-names = "default", "sleep";
>> + pinctrl-0 = <&blsp1_uart2_default>;
>> + pinctrl-1 = <&blsp1_uart2_sleep>;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
>
> <snip>
>
>> diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
>> new file mode 100644
>> index 0000000..fa92a1a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
>> @@ -0,0 +1,221 @@
>> +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/memreserve/ 0x00000000 0x00001000;
>
> Please use reserved-memory{}. And why are they setting aside 4k at the
> beginning? Trying to cover up corruption issues?
>
I only have the existing kernel (3.10) and no insight as to why this is
needed. Something very interesting and/or unexpected was that I needed
memreserve when using earlycon combined with
CONFIG_DEBUG_DRIVER && CONFIG_DEBUG_DEVRES
in order for the target / phone to boot. It have very well booted its
just I cant tell given the serial debug is the way I currently have to
gain visibility into the status of the phone.
But when I turned off the a fore mentioned config options and continued
to use earlycon it booted fine.
Removing memreserve.
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. MSM 8992";
>> + compatible = "qcom,msm8992";
>> + qcom,msm-id = <251 0>, <252 0>;
This is needed or else the LK provides the following error
[5380] qcom,msm-id entry not found
and refuses to boot.
>> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
>
> See above comment on ids.
removal of this (pmic-id) seems to be ok.
>
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen { };
>> +
>
> <snip>
>
>> +#include "msm8992-pins.dtsi"
>> diff --git a/arch/arm64/configs/bullhead_defconfig b/arch/arm64/configs/bullhead_defconfig
>
> Please add whatever config options you have to the default defconfig. we don't
> define board specific configs for ARM64 platforms. Or I should say, they won't
> be accepted into the kernel.
>
> Also, please separate defconfig changes into separate patches.
>
Will keep the changes to the absolute minimum.
Looks like I am going to need these 3
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
as this unit doent have all the bits'N pieces working currently and is
_ONLY_ able to boot a ramdisk.
-jeremy
> <snip>
>
>> diff --git a/arch/arm64/configs/msm8992_defconfig b/arch/arm64/configs/msm8992_defconfig
>> new file mode 100644
>> index 0000000..f673a27
>> --- /dev/null
>> +++ b/arch/arm64/configs/msm8992_defconfig
>
> See above comment.
>> @@ -0,0 +1,5 @@
>> +CONFIG_NO_HZ=y
>> +CONFIG_HIGH_RES_TIMERS=y
>> +CONFIG_SCHED_HMP=y
>> +CONFIG_NAMESPACES=y
>> +# CONFIG_CORESIGHT is not set
>> --
>> 2.6.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v3 3/5] clk: at91: sckc: optimize boot time
From: Stephen Boyd @ 2016-09-21 0:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160920205833.19638-4-alexandre.belloni@free-electrons.com>
On 09/20, Alexandre Belloni wrote:
> Assume that if the oscillator is enabled (OSC32EN bit is present), the
> delay has already elapsed as the bootloader probably waited for the
> oscillator to settle. This could waste up to 1.2s.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 2/5] clk: at91: Add sama5d4 sckc support
From: Stephen Boyd @ 2016-09-21 0:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160920205833.19638-3-alexandre.belloni@free-electrons.com>
On 09/20, Alexandre Belloni wrote:
> Starting with sama5d4, the crystal oscillator is always enabled at startup
> and the SCKC doesn't have an OSC32EN bit anymore.
>
> Add support for that new controller.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 1/5] clk: at91: move slow clock controller clocks to sckc.c
From: Stephen Boyd @ 2016-09-21 0:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160920205833.19638-2-alexandre.belloni@free-electrons.com>
On 09/20, Alexandre Belloni wrote:
> Move all clocks related to the slow clock controller to sckc.c. This avoids
> extern definitions and allows to remove sckc.h
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
Applied to clk-next
drivers/clk/at91/sckc.c:146:13:
warning: symbol 'of_at91sam9x5_clk_slow_osc_setup' was not
declared. Should it be static?
drivers/clk/at91/sckc.c:260:13:
warning: symbol 'of_at91sam9x5_clk_slow_rc_osc_setup' was not
declared. Should it be static?
drivers/clk/at91/sckc.c:359:13:
warning: symbol 'of_at91sam9x5_clk_slow_setup' was not declared.
Should it be static?
----8<----
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index f6ed711af738..311956abf4aa 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -143,8 +143,8 @@ at91_clk_register_slow_osc(void __iomem *sckcr,
return hw;
}
-void __init of_at91sam9x5_clk_slow_osc_setup(struct device_node *np,
- void __iomem *sckcr)
+static void __init
+of_at91sam9x5_clk_slow_osc_setup(struct device_node *np, void __iomem *sckcr)
{
struct clk_hw *hw;
const char *parent_name;
@@ -257,8 +257,8 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr,
return hw;
}
-void __init of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np,
- void __iomem *sckcr)
+static void __init
+of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np, void __iomem *sckcr)
{
struct clk_hw *hw;
u32 frequency = 0;
@@ -356,8 +356,8 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
return hw;
}
-void __init of_at91sam9x5_clk_slow_setup(struct device_node *np,
- void __iomem *sckcr)
+static void __init
+of_at91sam9x5_clk_slow_setup(struct device_node *np, void __iomem *sckcr)
{
struct clk_hw *hw;
const char *parent_names[2];
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH 2/2] clk: imx6: initialize GPU clocks
From: Stephen Boyd @ 2016-09-20 23:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474017371-28966-2-git-send-email-l.stach@pengutronix.de>
On 09/16, Lucas Stach wrote:
> Initialize the GPU clock muxes to sane inputs. Until now they have
> not been changed from their default values, which means that both
> GPU3D shader and GPU2D core were fed by clock inputs whose rates
> exceed the maximium allowed frequency of the cores by as much as
> 200MHz.
>
> This fixes a severe GPU stability issue on i.MX6DL.
>
> Cc: stable at vger.kernel.org
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
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