* [PATCH 5/5] arm64: Add uprobe support
From: Pratyush Anand @ 2016-09-22 3:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921170403.GE12180@e104818-lin.cambridge.arm.com>
On 21/09/2016:06:04:04 PM, Catalin Marinas wrote:
> On Wed, Sep 21, 2016 at 04:30:47PM +0530, Pratyush Anand wrote:
> > On 20/09/2016:05:59:46 PM, Catalin Marinas wrote:
> > > > +int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
> > > > + unsigned long addr)
> > > > +{
> > > > + probe_opcode_t insn;
> > > > +
> > > > + /* TODO: Currently we do not support AARCH32 instruction probing */
> > >
> > > Is there a way to check (not necessarily in this file) that we don't
> > > probe 32-bit tasks?
> >
> > - Well, I do not have complete idea about it that, how it can be done. I think
> > we can not check that just by looking a single bit in an instruction.
> > My understanding is that, we can only know about it when we are executing the
> > instruction, by reading pstate, but that would not be useful for uprobe
> > instruction analysis.
> >
> > I hope, instruction encoding for aarch32 and aarch64 are different, and by
> > analyzing for all types of aarch32 instructions, we will be able to decide
> > that whether instruction is 32 bit trace-able or not. Accordingly, we can use
> > either BRK or BKPT instruction for breakpoint generation.
>
> We may have some unrelated instruction encoding overlapping but I
> haven't checked. I was more thinking about whether we know which task is
> being probed and check is_compat_task() or maybe using
> compat_user_mode(regs).
I had thought of this, but problem is that we might not have task in existence
when we enable uprobes. For example: Lets say we are inserting a trace probe at
offset 0x690 in a executable binary.
echo "p test:0x690" > /sys/kernel/debug/tracing/uprobe_events
echo 1 > /sys/kernel/debug/tracing/events/uprobes/enable
In the 'enable' step, it is decided that whether instruction is traceable or
not.
(1) But at this point 'test' executable might not be running.
(2) Even if it is running, is_compat_task() or compat_user_mode() might not be
usable, as they work with 'current' task.
What I was thinking that, let it go with 'TODO' as of now.
Later on, we propose some changes in core layer, so that we can read the elf
headers of executable binary. ELFCLASS will be able to tell us, whether its a 32
bit or 64 bit executable. I think, moving "struct uprobe" from
kernel/events/uprobes.c to a include/linux header file will do the job. "struct
arch_uprobe" is part of "struct uprobe". "struct arch_uprobe" is passed in
arch_uprobe_analyze_insn(). So, we can access struct uprobe's "inode" element
with this change.
~Pratyush
^ permalink raw reply
* [PATCH] arm64: Call numa_store_cpu_info() earlier.
From: Yisheng Xie @ 2016-09-22 3:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474397195-16520-1-git-send-email-ddaney.cavm@gmail.com>
On 2016/9/21 2:46, David Daney wrote:
> From: David Daney <david.daney@cavium.com>
>
> Fix by moving call to numa_store_cpu_info() for all CPUs into
> smp_prepare_cpus(), which happens before wq_numa_init(). Since
> smp_store_cpu_info() now contains only a single function call,
> simplify by removing the function and out-lining its contents.
>
> Suggested-by: Robert Richter <rric@kernel.org>
> fixes: 1a2db300348b ("arm64, numa: Add NUMA support for arm64 platforms.")
> Cc: <stable@vger.kernel.org> # 4.7.x-
> Signed-off-by: David Daney <david.daney@cavium.com>
> ---
Tested-by: Yisheng Xie <xieyisheng1@huawei.com>
Thanks.
> arch/arm64/kernel/smp.c | 14 ++++++--------
> 1 file changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
> index d93d433..3ff173e 100644
> --- a/arch/arm64/kernel/smp.c
> +++ b/arch/arm64/kernel/smp.c
> @@ -201,12 +201,6 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
> return ret;
> }
>
> -static void smp_store_cpu_info(unsigned int cpuid)
> -{
> - store_cpu_topology(cpuid);
> - numa_store_cpu_info(cpuid);
> -}
> -
> /*
> * This is the secondary CPU boot entry. We're using this CPUs
> * idle thread stack, but a set of temporary page tables.
> @@ -254,7 +248,7 @@ asmlinkage void secondary_start_kernel(void)
> */
> notify_cpu_starting(cpu);
>
> - smp_store_cpu_info(cpu);
> + store_cpu_topology(cpu);
>
> /*
> * OK, now it's safe to let the boot CPU continue. Wait for
> @@ -689,10 +683,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
> {
> int err;
> unsigned int cpu;
> + unsigned int this_cpu;
>
> init_cpu_topology();
>
> - smp_store_cpu_info(smp_processor_id());
> + this_cpu = smp_processor_id();
> + store_cpu_topology(this_cpu);
> + numa_store_cpu_info(this_cpu);
>
> /*
> * If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set
> @@ -719,6 +716,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
> continue;
>
> set_cpu_present(cpu, true);
> + numa_store_cpu_info(cpu);
> }
> }
>
>
^ permalink raw reply
* [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
From: Po Liu @ 2016-09-22 2:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921223741.GG20006@localhost>
Hi Bjorn,
> -----Original Message-----
> From: Bjorn Helgaas [mailto:helgaas at kernel.org]
> Sent: Thursday, September 22, 2016 6:38 AM
> To: Po Liu
> Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> linux-kernel at vger.kernel.org; devicetree at vger.kernel.org; Roy Zang; Arnd
> Bergmann; Marc Zyngier; Stuart Yoder; Leo Li; M.H. Lian; Murali
> Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
> Subject: Re: [PATCH v5 3/3] pci:aer: add support aer interrupt with none
> MSI/MSI-X/INTx mode
>
> On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
> > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> > When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> > maybe there is interrupt line for aer pme etc. Search the interrupt
> > number in the fdt file. Then fixup the dev->irq with it.
> >
> > Signed-off-by: Po Liu <po.liu@nxp.com>
> > ---
> > changes for v5:
> > - Add clear 'aer' interrup-names description
> >
> > .../devicetree/bindings/pci/layerscape-pci.txt | 11 +++++---
> > drivers/pci/pcie/portdrv_core.c | 31
> +++++++++++++++++++---
> > 2 files changed, 35 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index 41e9f55..101d0a7 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -18,8 +18,10 @@ Required properties:
> > - reg: base addresses and lengths of the PCIe controller
> > - interrupts: A list of interrupt outputs of the controller. Must
> contain an
> > entry for each entry in the interrupt-names property.
> > -- interrupt-names: Must include the following entries:
> > - "intr": The interrupt that is asserted for controller interrupts
> > +- interrupt-names: It may be include the following entries:
> > + "aer": The interrupt that is asserted for aer interrupt
> > + "pme": The interrupt that is asserted for pme interrupt
> > + ......
> > - fsl,pcie-scfg: Must include two entries.
> > The first entry must be a link to the SCFG device node
> > The second entry must be '0' or '1' based on physical PCIe
> controller index.
> > @@ -35,8 +37,9 @@ Example:
> > reg = <0x00 0x03400000 0x0 0x00010000 /* controller
> registers */
> > 0x40 0x00000000 0x0 0x00002000>; /* configuration
> space */
> > reg-names = "regs", "config";
> > - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /*
> controller interrupt */
> > - interrupt-names = "intr";
> > + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer
> interrupt */
> > + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
> > + interrupt-names = "aer", "pme";
> > fsl,pcie-scfg = <&scfg 0>;
> > #address-cells = <3>;
> > #size-cells = <2>;
> > diff --git a/drivers/pci/pcie/portdrv_core.c
> > b/drivers/pci/pcie/portdrv_core.c index e9270b4..7c4943d 100644
> > --- a/drivers/pci/pcie/portdrv_core.c
> > +++ b/drivers/pci/pcie/portdrv_core.c
> > @@ -16,6 +16,7 @@
> > #include <linux/slab.h>
> > #include <linux/pcieport_if.h>
> > #include <linux/aer.h>
> > +#include <linux/of_irq.h>
> >
> > #include "../pci.h"
> > #include "portdrv.h"
> > @@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev
> > *dev, int *vectors, int mask) static int init_service_irqs(struct
> > pci_dev *dev, int *irqs, int mask) {
> > int i, irq = -1;
> > + int ret;
> > + struct device_node *np = NULL;
> > +
> > + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> > + irqs[i] = 0;
> > +
> > + if (dev->bus->dev.of_node)
> > + np = dev->bus->dev.of_node;
> > +
> > + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> > + * request irq for aer
> > + */
> > + if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> > + (mask & PCIE_PORT_SERVICE_PME)) {
> > + ret = of_irq_get_byname(np, "aer");
> > + if (ret > 0) {
> > + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
> > + if (dev->irq)
> > + irq = dev->irq;
> > + goto no_msi;
> > + }
> > + }
>
> We definitely need to solve this somehow. But this approach doesn't
> feel quite right because it's hard to map this code back to anything in
> the spec, and it uses a completely platform-dependent name ("interrupt-
> names aer") in code that is supposedly generic.
Very agree.
>
> What if we added some sort of hook that would return the IRQ? Maybe a
> pcibios_*() hook right now, with the idea of making it a pci_host_bridge
> function pointer someday?
Good idea. I'll try one version patch soon.
>
> I know the body of the hook would look a lot like what you have here,
> but at least it would be more obvious that it's platform-specific code.
>
Not agree more.
> I think your platform supports PME interrupts as well as AER, and
> they're different IRQs. So you'd probably have to do something similar
> to the pcie_port_enable_msix() interface, so you can fill in both IRQs.
>
Ok, understand.
Po
> > /*
> > * If MSI cannot be used for PCIe PME or hotplug, we have to use
> @@
> > -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev,
> int *irqs, int mask)
> > irq = dev->irq;
> >
> > no_msi:
> > - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> > - irqs[i] = irq;
> > + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
> > + if (!irqs[i])
> > + irqs[i] = irq;
> > + }
> > irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
> >
> > - if (irq < 0)
> > + if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
> > return -ENODEV;
> > return 0;
> > }
> > --
> > 2.1.0.27.g96db324
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 2/2] musb: sunxi: Force session end on babble errors in host-mode
From: Bin Liu @ 2016-09-22 2:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160918165018.24547-2-hdegoede@redhat.com>
Hi,
On Sun, Sep 18, 2016 at 06:50:18PM +0200, Hans de Goede wrote:
> The sunxi musb has a bug where sometimes it will generate a babble
> error on device disconnect instead of a disconnect irq. When this
> happens the musb-controller switches from host mode to device mode
> (it clears MUSB_DEVCTL_SESSION and sets MUSB_DEVCTL_BDEVICE) and
> gets stuck in this state.
>
> Clearing this requires reporting Vbus low for 200 or more ms, but
> on some devices Vbus is simply always high (host-only mode, no Vbus
> control).
>
> This commit calls sun4i_usb_phy_force_session_end() on babble errors
> in host-mode, fixing the musb controller being stuck in this state
> on systems without Vbus control; and also fixes the need to unplug
> the usb-b -> usb-a cable to get out of this state on systems with
> Vbus control.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> drivers/usb/musb/sunxi.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
> index 1408245..5079d90 100644
> --- a/drivers/usb/musb/sunxi.c
> +++ b/drivers/usb/musb/sunxi.c
> @@ -192,8 +192,18 @@ static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
> * normally babble never happens treat it as disconnect.
> */
> if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) {
musb_interrupt() handle BABBLE in host mode, and has a glue hook
musb_platform_recover() in musb_recover_from_babble().
Maybe you can use it?
> + struct sunxi_glue *glue =
> + dev_get_drvdata(musb->controller->parent);
> +
> + dev_warn(musb->controller->parent, "babble, treating as disconnect\n");
> +
> musb->int_usb &= ~MUSB_INTR_BABBLE;
> musb->int_usb |= MUSB_INTR_DISCONNECT;
> + /*
> + * Fix the musb controller sometimes getting stuck in
> + * bdevice state after a babble error.
> + */
> + sun4i_usb_phy_force_session_end(glue->phy);
As I commented in PATCH 1/2, can you somehow reuse
sun4i_usb_phy_set_mode() instead?
> }
>
> if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
> --
> 2.9.3
Regards,
-Bin.
^ permalink raw reply
* [PATCH 1/2] phy-sun4i-usb: Add sun4i_usb_phy_force_session_end() function
From: Bin Liu @ 2016-09-22 2:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <54119844-ce99-bf8c-fc6e-09bcc7523e4d@redhat.com>
Hi,
On Wed, Sep 21, 2016 at 11:05:33AM +0300, Hans de Goede wrote:
> Hi,
>
> On 09/20/2016 07:45 AM, Kishon Vijay Abraham I wrote:
> >Hi,
> >
> >On Sunday 18 September 2016 10:20 PM, Hans de Goede wrote:
> >>The sunxi musb has a bug where sometimes it will generate a babble
> >>error on device disconnect instead of a disconnect irq. When this
> >>happens the musb-controller switches from host mode to device mode
> >>(it clears MUSB_DEVCTL_SESSION and sets MUSB_DEVCTL_BDEVICE) and
> >>gets stuck in this state.
> >>
> >>Clearing this requires reporting Vbus low for 200 or more ms, but
> >>on some devices Vbus is simply always high (host-only mode, no Vbus
> >>control). The phy-sun4i-usb code already has code to force a session
> >>end for devices without Vbus control.
> >>
> >>This commit adds a sun4i_usb_phy_force_session_end() function exporting
> >>this functionality to the sunxi-musb glue, so that it can force a session
> >>end to fixup the stuck state after a babble error.
> >>
> >>Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> >>---
> >> drivers/phy/phy-sun4i-usb.c | 11 +++++++++++
> >> include/linux/phy/phy-sun4i-usb.h | 7 +++++++
> >> 2 files changed, 18 insertions(+)
> >>
> >>diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> >>index 43c0d98..06f4e11a 100644
> >>--- a/drivers/phy/phy-sun4i-usb.c
> >>+++ b/drivers/phy/phy-sun4i-usb.c
> >>@@ -470,6 +470,17 @@ void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled)
> >> }
> >> EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
> >>
> >>+void sun4i_usb_phy_force_session_end(struct phy *_phy)
> >>+{
> >>+ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
> >>+ struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
> >>+
> >>+ data->id_det = -1;
> >>+ data->force_session_end = true;
> >>+ queue_delayed_work(system_wq, &data->detect, 0);
> >>+}
> >>+EXPORT_SYMBOL_GPL(sun4i_usb_phy_force_session_end);
> >
> >Er.. one more export symbol :-(
>
> Yes unfortunately we need one more to work around sunxi musb / phy bugs.
Instead, can you somehow reuse sun4i_usb_phy_set_mode()?
Regards,
-Bin.
>
> >>+
> >> static const struct phy_ops sun4i_usb_phy_ops = {
> >> .init = sun4i_usb_phy_init,
> >> .exit = sun4i_usb_phy_exit,
> >>diff --git a/include/linux/phy/phy-sun4i-usb.h b/include/linux/phy/phy-sun4i-usb.h
> >>index 50aed92..3bb773f 100644
> >>--- a/include/linux/phy/phy-sun4i-usb.h
> >>+++ b/include/linux/phy/phy-sun4i-usb.h
> >>@@ -23,4 +23,11 @@
> >> */
> >> void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled);
> >>
> >>+/**
> >>+ * sun4i_usb_force_session_end() - Force the current session to end
> >>+ * by reporting VBus low for 200+ ms
> >>+ * @phy: reference to a sun4i usb phy
> >>+ */
> >>+void sun4i_usb_phy_force_session_end(struct phy *phy);
> >
> >Should we include a static inline function if sun4i phy is not defined?
>
> No, we're also not doing that for the already exported
> sun4i_usb_phy_set_squelch_detect()
>
> And it is not necessary since the only caller is drivers/usb/musb/sunxi.c,
> and drivers/usb/musb/Kconfig has:
>
> config USB_MUSB_SUNXI
> tristate "Allwinner (sunxi)"
> depends on PHY_SUN4I_USB
>
> Regards,
>
> Hans
^ permalink raw reply
* [PATCHv2] arm64: Correctly bounds check virt_addr_valid
From: Kees Cook @ 2016-09-21 23:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474496704-30541-1-git-send-email-labbott@redhat.com>
On Wed, Sep 21, 2016 at 3:25 PM, Laura Abbott <labbott@redhat.com> wrote:
>
> virt_addr_valid is supposed to return true if and only if virt_to_page
> returns a valid page structure. The current macro does math on whatever
> address is given and passes that to pfn_valid to verify. vmalloc and
> module addresses can happen to generate a pfn that 'happens' to be
> valid. Fix this by only performing the pfn_valid check on addresses that
> have the potential to be valid.
>
> Acked-by: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Laura Abbott <labbott@redhat.com>
> ---
> v2: Properly parenthesize macro arguments. Re-factor to common macro.
>
> Also in case it wasn't clear, there's no need to try and squeeze this
> into 4.8. Hardened usercopy should have all the checks, this is just for
> full correctness.
After this lands for 4.9, I should likely drop the checks that are in
hardened usercopy? That'll speed things up ever so slightly, and will
let us catch other architectures that have a weird
virt_addr_valid()...
-Kees
--
Kees Cook
Nexus Security
^ permalink raw reply
* [GIT PULL] few minor fixes for omap dts files for v4.9 merge window
From: Tony Lindgren @ 2016-09-21 22:49 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit a2a2b8215621536a7620e31f36bede81bb86680b:
Merge branch 'am335x-cpufreq-regression' into omap-for-v4.9/dt-v2 (2016-09-14 16:27:28 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v4.9/dt-pt3-signed
for you to fetch changes up to ce385a5e7a85c023af2e013101d4fe2240beec21:
ARM: dts: omap5-igep0050.dts: Use tabs for indentation (2016-09-20 11:37:50 -0700)
----------------------------------------------------------------
Few fixes for omap dts files for v4.9 merge window. Let's also add
the tilcdc quirks:
- Fix typo with recent beagleboard-x15 changes for mmc2_pins_default
- Add am335x blue-and-red-wiring quirk as specified in the binding in
Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt. Also
fix up the whitespace formatting for am335x-evmsk.
- Fix for recent igepv5 power button for GPIO_ACTIVE_LOW. Also fix
up the whitespace formatting for the button
----------------------------------------------------------------
Jyri Sarha (3):
ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node
ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes
ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node
Ladislav Michl (1):
ARM: dts: omap5-igep0050.dts: Use tabs for indentation
Nishanth Menon (1):
ARM: dts: am57xx-beagle-x15-common: Fix wrong pinctrl selection for mmc2
Tony Lindgren (1):
ARM: dts: Fix igepv5 power button GPIO direction
arch/arm/boot/dts/am335x-evm.dts | 2 ++
arch/arm/boot/dts/am335x-evmsk.dts | 42 +++++++++++++------------
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 2 +-
arch/arm/boot/dts/omap5-igep0050.dts | 4 +--
4 files changed, 27 insertions(+), 23 deletions(-)
^ permalink raw reply
* [PATCH V6 0/5] ECAM quirks handling for ARM64 platforms
From: Christopher Covington @ 2016-09-21 22:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921131107.GB10804@localhost>
Hi Bjorn,
On 09/21/2016 09:11 AM, Bjorn Helgaas wrote:
> On Tue, Sep 20, 2016 at 09:15:14PM -0400, cov at codeaurora.org wrote:
>>> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
>>> index eb14f74..bb3b8ad 100644
>>> --- a/drivers/acpi/pci_mcfg.c
>>> +++ b/drivers/acpi/pci_mcfg.c
>>> @@ -42,86 +42,59 @@ struct mcfg_fixup {
>>> struct resource cfgres;
>>> };
>>>
>>> -#define MCFG_DOM_ANY (-1)
>>
>> Did you delete this because there were no current users, because you'd
>> prefer users just use "-1", or for some other reason?
>
> I removed it because there were no users of it and, more importantly,
> the code doesn't implement support for it.
It looks like a stale "First match against PCI topology <domain:bus>..."
comment remains.
Thanks,
Cov
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code
Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCHv2] PCI: QDF2432 32 bit config space accessors
From: Christopher Covington @ 2016-09-21 22:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921173129.GA20006@localhost>
The Qualcomm Technologies QDF2432 SoC does not support accesses smaller
than 32 bits to the PCI configuration space. Register the appropriate
quirk.
Signed-off-by: Christopher Covington <cov@codeaurora.org>
---
drivers/acpi/pci_mcfg.c | 8 ++++++++
drivers/pci/ecam.c | 10 ++++++++++
include/linux/pci-ecam.h | 1 +
3 files changed, 19 insertions(+)
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index 245b79f..212334f 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -96,6 +96,14 @@ static struct mcfg_fixup mcfg_quirks[] = {
THUNDER_ECAM_MCFG(2, 12),
THUNDER_ECAM_MCFG(2, 13),
#endif
+ { "QCOM ", "QDF2432 ", 1, 0, MCFG_BUS_ANY, &pci_32b_ops },
+ { "QCOM ", "QDF2432 ", 1, 1, MCFG_BUS_ANY, &pci_32b_ops },
+ { "QCOM ", "QDF2432 ", 1, 2, MCFG_BUS_ANY, &pci_32b_ops },
+ { "QCOM ", "QDF2432 ", 1, 3, MCFG_BUS_ANY, &pci_32b_ops },
+ { "QCOM ", "QDF2432 ", 1, 4, MCFG_BUS_ANY, &pci_32b_ops },
+ { "QCOM ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, &pci_32b_ops },
+ { "QCOM ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, &pci_32b_ops },
+ { "QCOM ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, &pci_32b_ops },
};
static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c
index 43ed08d..c3b3063 100644
--- a/drivers/pci/ecam.c
+++ b/drivers/pci/ecam.c
@@ -162,3 +162,13 @@ struct pci_ecam_ops pci_generic_ecam_ops = {
.write = pci_generic_config_write,
}
};
+
+/* ops for 32 bit config space access quirk */
+struct pci_ecam_ops pci_32b_ops = {
+ .bus_shift = 20,
+ .pci_ops = {
+ .map_bus = pci_ecam_map_bus,
+ .read = pci_generic_config_read32,
+ .write = pci_generic_config_write32,
+ }
+};
diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
index 35f0e81..a6cffb8 100644
--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
@@ -65,6 +65,7 @@ extern struct pci_ecam_ops pci_thunder_pem_ops;
#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
extern struct pci_ecam_ops pci_thunder_ecam_ops;
#endif
+extern struct pci_ecam_ops pci_32b_ops;
#ifdef CONFIG_PCI_HOST_GENERIC
/* for DT-based PCI controllers that support ECAM */
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related
* [PATCH v5 3/3] pci:aer: add support aer interrupt with none MSI/MSI-X/INTx mode
From: Bjorn Helgaas @ 2016-09-21 22:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473741659-17618-3-git-send-email-po.liu@nxp.com>
On Tue, Sep 13, 2016 at 12:40:59PM +0800, Po Liu wrote:
> On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
> When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
> maybe there is interrupt line for aer pme etc. Search the interrupt
> number in the fdt file. Then fixup the dev->irq with it.
>
> Signed-off-by: Po Liu <po.liu@nxp.com>
> ---
> changes for v5:
> - Add clear 'aer' interrup-names description
>
> .../devicetree/bindings/pci/layerscape-pci.txt | 11 +++++---
> drivers/pci/pcie/portdrv_core.c | 31 +++++++++++++++++++---
> 2 files changed, 35 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 41e9f55..101d0a7 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -18,8 +18,10 @@ Required properties:
> - reg: base addresses and lengths of the PCIe controller
> - interrupts: A list of interrupt outputs of the controller. Must contain an
> entry for each entry in the interrupt-names property.
> -- interrupt-names: Must include the following entries:
> - "intr": The interrupt that is asserted for controller interrupts
> +- interrupt-names: It may be include the following entries:
> + "aer": The interrupt that is asserted for aer interrupt
> + "pme": The interrupt that is asserted for pme interrupt
> + ......
> - fsl,pcie-scfg: Must include two entries.
> The first entry must be a link to the SCFG device node
> The second entry must be '0' or '1' based on physical PCIe controller index.
> @@ -35,8 +37,9 @@ Example:
> reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
> 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
> reg-names = "regs", "config";
> - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> - interrupt-names = "intr";
> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */
> + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
> + interrupt-names = "aer", "pme";
> fsl,pcie-scfg = <&scfg 0>;
> #address-cells = <3>;
> #size-cells = <2>;
> diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
> index e9270b4..7c4943d 100644
> --- a/drivers/pci/pcie/portdrv_core.c
> +++ b/drivers/pci/pcie/portdrv_core.c
> @@ -16,6 +16,7 @@
> #include <linux/slab.h>
> #include <linux/pcieport_if.h>
> #include <linux/aer.h>
> +#include <linux/of_irq.h>
>
> #include "../pci.h"
> #include "portdrv.h"
> @@ -200,6 +201,28 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
> static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
> {
> int i, irq = -1;
> + int ret;
> + struct device_node *np = NULL;
> +
> + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> + irqs[i] = 0;
> +
> + if (dev->bus->dev.of_node)
> + np = dev->bus->dev.of_node;
> +
> + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
> + * request irq for aer
> + */
> + if (IS_ENABLED(CONFIG_OF_IRQ) && np &&
> + (mask & PCIE_PORT_SERVICE_PME)) {
> + ret = of_irq_get_byname(np, "aer");
> + if (ret > 0) {
> + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
> + if (dev->irq)
> + irq = dev->irq;
> + goto no_msi;
> + }
> + }
We definitely need to solve this somehow. But this approach doesn't
feel quite right because it's hard to map this code back to anything
in the spec, and it uses a completely platform-dependent name
("interrupt-names aer") in code that is supposedly generic.
What if we added some sort of hook that would return the IRQ? Maybe a
pcibios_*() hook right now, with the idea of making it a
pci_host_bridge function pointer someday?
I know the body of the hook would look a lot like what you have here,
but at least it would be more obvious that it's platform-specific
code.
I think your platform supports PME interrupts as well as AER, and
they're different IRQs. So you'd probably have to do something
similar to the pcie_port_enable_msix() interface, so you can fill in
both IRQs.
> /*
> * If MSI cannot be used for PCIe PME or hotplug, we have to use
> @@ -225,11 +248,13 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
> irq = dev->irq;
>
> no_msi:
> - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
> - irqs[i] = irq;
> + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
> + if (!irqs[i])
> + irqs[i] = irq;
> + }
> irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
>
> - if (irq < 0)
> + if (irq < 0 && irqs[PCIE_PORT_SERVICE_AER_SHIFT] < 0)
> return -ENODEV;
> return 0;
> }
> --
> 2.1.0.27.g96db324
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCHv2] arm64: Correctly bounds check virt_addr_valid
From: Laura Abbott @ 2016-09-21 22:25 UTC (permalink / raw)
To: linux-arm-kernel
virt_addr_valid is supposed to return true if and only if virt_to_page
returns a valid page structure. The current macro does math on whatever
address is given and passes that to pfn_valid to verify. vmalloc and
module addresses can happen to generate a pfn that 'happens' to be
valid. Fix this by only performing the pfn_valid check on addresses that
have the potential to be valid.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Laura Abbott <labbott@redhat.com>
---
v2: Properly parenthesize macro arguments. Re-factor to common macro.
Also in case it wasn't clear, there's no need to try and squeeze this
into 4.8. Hardened usercopy should have all the checks, this is just for
full correctness.
---
arch/arm64/include/asm/memory.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 31b7322..ba62df8 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -214,7 +214,7 @@ static inline void *phys_to_virt(phys_addr_t x)
#ifndef CONFIG_SPARSEMEM_VMEMMAP
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+#define _virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
#else
#define __virt_to_pgoff(kaddr) (((u64)(kaddr) & ~PAGE_OFFSET) / PAGE_SIZE * sizeof(struct page))
#define __page_to_voff(kaddr) (((u64)(page) & ~VMEMMAP_START) * PAGE_SIZE / sizeof(struct page))
@@ -222,11 +222,15 @@ static inline void *phys_to_virt(phys_addr_t x)
#define page_to_virt(page) ((void *)((__page_to_voff(page)) | PAGE_OFFSET))
#define virt_to_page(vaddr) ((struct page *)((__virt_to_pgoff(vaddr)) | VMEMMAP_START))
-#define virt_addr_valid(kaddr) pfn_valid((((u64)(kaddr) & ~PAGE_OFFSET) \
+#define _virt_addr_valid(kaddr) pfn_valid((((u64)(kaddr) & ~PAGE_OFFSET) \
+ PHYS_OFFSET) >> PAGE_SHIFT)
#endif
#endif
+#define _virt_addr_is_linear(kaddr) (((u64)(kaddr)) >= PAGE_OFFSET)
+#define virt_addr_valid(kaddr) (_virt_addr_is_linear(kaddr) && \
+ _virt_addr_valid(kaddr))
+
#include <asm-generic/memory_model.h>
#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v2 5/6] misc: sram: add Atmel securam support
From: Alexandre Belloni @ 2016-09-21 22:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921220939.27924-6-alexandre.belloni@free-electrons.com>
Greg,
As a reminder, I think we agreed that this one could go through the at91
tree because of the dependency on patch 2/6.
I'd like to get your ack though.
On 22/09/2016 at 00:09:38 +0200, Alexandre Belloni wrote :
> The Atmel secure SRAM is connected to a security module and may be erased
> automatically under certain conditions. For that reason, it is necessary to
> wait for the security module to flag that SRAM accesses are allowed before
> accessing it.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Philipp Zabel <p.zabel@pengutronix.de>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>
> drivers/misc/sram.c | 42 +++++++++++++++++++++++++++++++++++-------
> 1 file changed, 35 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/misc/sram.c b/drivers/misc/sram.c
> index f84b53d6ce50..b0d4dd9b0586 100644
> --- a/drivers/misc/sram.c
> +++ b/drivers/misc/sram.c
> @@ -19,12 +19,17 @@
> */
>
> #include <linux/clk.h>
> +#include <linux/delay.h>
> #include <linux/genalloc.h>
> #include <linux/io.h>
> #include <linux/list_sort.h>
> #include <linux/of_address.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> +#include <linux/regmap.h>
> #include <linux/slab.h>
> +#include <linux/mfd/syscon.h>
> +#include <soc/at91/atmel-secumod.h>
>
> #define SRAM_GRANULARITY 32
>
> @@ -334,12 +339,35 @@ static int sram_reserve_regions(struct sram_dev *sram, struct resource *res)
> return ret;
> }
>
> +static int atmel_securam_wait(void)
> +{
> + struct regmap *regmap;
> + u32 val;
> +
> + regmap = syscon_regmap_lookup_by_compatible("atmel,sama5d2-secumod");
> + if (IS_ERR(regmap))
> + return -ENODEV;
> +
> + return regmap_read_poll_timeout(regmap, AT91_SECUMOD_RAMRDY, val,
> + val & AT91_SECUMOD_RAMRDY_READY,
> + 10000, 500000);
> +}
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id sram_dt_ids[] = {
> + { .compatible = "mmio-sram" },
> + { .compatible = "atmel,sama5d2-securam", .data = atmel_securam_wait },
> + {}
> +};
> +#endif
> +
> static int sram_probe(struct platform_device *pdev)
> {
> struct sram_dev *sram;
> struct resource *res;
> size_t size;
> int ret;
> + int (*init_func)(void);
>
> sram = devm_kzalloc(&pdev->dev, sizeof(*sram), GFP_KERNEL);
> if (!sram)
> @@ -384,6 +412,13 @@ static int sram_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, sram);
>
> + init_func = of_device_get_match_data(&pdev->dev);
> + if (init_func) {
> + ret = init_func();
> + if (ret)
> + return ret;
> + }
> +
> dev_dbg(sram->dev, "SRAM pool: %zu KiB @ 0x%p\n",
> gen_pool_size(sram->pool) / 1024, sram->virt_base);
>
> @@ -405,13 +440,6 @@ static int sram_remove(struct platform_device *pdev)
> return 0;
> }
>
> -#ifdef CONFIG_OF
> -static const struct of_device_id sram_dt_ids[] = {
> - { .compatible = "mmio-sram" },
> - {}
> -};
> -#endif
> -
> static struct platform_driver sram_driver = {
> .driver = {
> .name = "sram",
> --
> 2.9.3
>
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2 6/6] ARM: dts: at91: sama5d2: Add securam node
From: Alexandre Belloni @ 2016-09-21 22:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921220939.27924-1-alexandre.belloni@free-electrons.com>
The sama5d2 has some static RAM that can be erased by the security module,
add its node
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/sama5d2.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 0b62bff86f49..a3653751a7d6 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -706,6 +706,11 @@
atmel,clk-output-range = <0 83000000>;
};
+ securam_clk: securam_clk {
+ #clock-cells = <0>;
+ reg = <51>;
+ };
+
i2s0_clk: i2s0_clk {
#clock-cells = <0>;
reg = <54>;
@@ -1029,6 +1034,15 @@
status = "disabled";
};
+ securam: sram at f8044000 {
+ compatible = "atmel,sama5d2-securam", "mmio-sram";
+ reg = <0xf8044000 0x1420>;
+ clocks = <&securam_clk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xf8044000 0x1420>;
+ };
+
rstc at f8048000 {
compatible = "atmel,sama5d3-rstc";
reg = <0xf8048000 0x10>;
--
2.9.3
^ permalink raw reply related
* [PATCH v2 5/6] misc: sram: add Atmel securam support
From: Alexandre Belloni @ 2016-09-21 22:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921220939.27924-1-alexandre.belloni@free-electrons.com>
The Atmel secure SRAM is connected to a security module and may be erased
automatically under certain conditions. For that reason, it is necessary to
wait for the security module to flag that SRAM accesses are allowed before
accessing it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/misc/sram.c | 42 +++++++++++++++++++++++++++++++++++-------
1 file changed, 35 insertions(+), 7 deletions(-)
diff --git a/drivers/misc/sram.c b/drivers/misc/sram.c
index f84b53d6ce50..b0d4dd9b0586 100644
--- a/drivers/misc/sram.c
+++ b/drivers/misc/sram.c
@@ -19,12 +19,17 @@
*/
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/genalloc.h>
#include <linux/io.h>
#include <linux/list_sort.h>
#include <linux/of_address.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/slab.h>
+#include <linux/mfd/syscon.h>
+#include <soc/at91/atmel-secumod.h>
#define SRAM_GRANULARITY 32
@@ -334,12 +339,35 @@ static int sram_reserve_regions(struct sram_dev *sram, struct resource *res)
return ret;
}
+static int atmel_securam_wait(void)
+{
+ struct regmap *regmap;
+ u32 val;
+
+ regmap = syscon_regmap_lookup_by_compatible("atmel,sama5d2-secumod");
+ if (IS_ERR(regmap))
+ return -ENODEV;
+
+ return regmap_read_poll_timeout(regmap, AT91_SECUMOD_RAMRDY, val,
+ val & AT91_SECUMOD_RAMRDY_READY,
+ 10000, 500000);
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id sram_dt_ids[] = {
+ { .compatible = "mmio-sram" },
+ { .compatible = "atmel,sama5d2-securam", .data = atmel_securam_wait },
+ {}
+};
+#endif
+
static int sram_probe(struct platform_device *pdev)
{
struct sram_dev *sram;
struct resource *res;
size_t size;
int ret;
+ int (*init_func)(void);
sram = devm_kzalloc(&pdev->dev, sizeof(*sram), GFP_KERNEL);
if (!sram)
@@ -384,6 +412,13 @@ static int sram_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, sram);
+ init_func = of_device_get_match_data(&pdev->dev);
+ if (init_func) {
+ ret = init_func();
+ if (ret)
+ return ret;
+ }
+
dev_dbg(sram->dev, "SRAM pool: %zu KiB @ 0x%p\n",
gen_pool_size(sram->pool) / 1024, sram->virt_base);
@@ -405,13 +440,6 @@ static int sram_remove(struct platform_device *pdev)
return 0;
}
-#ifdef CONFIG_OF
-static const struct of_device_id sram_dt_ids[] = {
- { .compatible = "mmio-sram" },
- {}
-};
-#endif
-
static struct platform_driver sram_driver = {
.driver = {
.name = "sram",
--
2.9.3
^ permalink raw reply related
* [PATCH v2 4/6] misc: sram: document new compatible
From: Alexandre Belloni @ 2016-09-21 22:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921220939.27924-1-alexandre.belloni@free-electrons.com>
Add atmel,sama5d2-securam to the compatible list.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/sram/sram.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sram/sram.txt b/Documentation/devicetree/bindings/sram/sram.txt
index add48f09015e..068c2c03c38f 100644
--- a/Documentation/devicetree/bindings/sram/sram.txt
+++ b/Documentation/devicetree/bindings/sram/sram.txt
@@ -4,7 +4,7 @@ Simple IO memory regions to be managed by the genalloc API.
Required properties:
-- compatible : mmio-sram
+- compatible : mmio-sram or atmel,sama5d2-securam
- reg : SRAM iomem address range
--
2.9.3
^ permalink raw reply related
* [PATCH v2 3/6] ARM: dts: at91: sama5d2: Add secumod node
From: Alexandre Belloni @ 2016-09-21 22:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921220939.27924-1-alexandre.belloni@free-electrons.com>
The sama5d2 has a security module, add its node.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/sama5d2.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 353d0e5ec83b..0b62bff86f49 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -1231,6 +1231,11 @@
clocks = <&pioA_clk>;
};
+ secumod at fc040000 {
+ compatible = "atmel,sama5d2-secumod", "syscon";
+ reg = <0xfc040000 0x100>;
+ };
+
tdes at fc044000 {
compatible = "atmel,at91sam9g46-tdes";
reg = <0xfc044000 0x100>;
--
2.9.3
^ permalink raw reply related
* [PATCH v2 2/6] ARM: at91: add secumod register definitions
From: Alexandre Belloni @ 2016-09-21 22:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921220939.27924-1-alexandre.belloni@free-electrons.com>
Add registers and bits definitions for the security module found on
sama5d2.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
include/soc/at91/atmel-secumod.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 include/soc/at91/atmel-secumod.h
diff --git a/include/soc/at91/atmel-secumod.h b/include/soc/at91/atmel-secumod.h
new file mode 100644
index 000000000000..7139e8eb1aca
--- /dev/null
+++ b/include/soc/at91/atmel-secumod.h
@@ -0,0 +1,20 @@
+/*
+ * Atmel Security Module register offsets and bit definitions.
+ *
+ * Copyright (C) 2016 Atmel
+ *
+ * Author: Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _LINUX_SOC_AT91_ATMEL_SECUMOD_H
+#define _LINUX_SOC_AT91_ATMEL_SECUMOD_H
+
+#define AT91_SECUMOD_RAMRDY 0x14
+#define AT91_SECUMOD_RAMRDY_READY BIT(0)
+
+#endif /* _LINUX_SOC_AT91_ATMEL_SECUMOD_H */
+
--
2.9.3
^ permalink raw reply related
* [PATCH v2 1/6] Documentation: dt: atmel-at91: Document secumod bindings
From: Alexandre Belloni @ 2016-09-21 22:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921220939.27924-1-alexandre.belloni@free-electrons.com>
A security module is available starting with sama5d2, add its bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/atmel-at91.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index e1f5ad855f14..eea1f44d5666 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -225,3 +225,20 @@ required properties:
compatible = "atmel,sama5d3-sfr", "syscon";
reg = <0xf0038000 0x60>;
};
+
+Security Module (SECUMOD)
+
+The Security Module macrocell provides all necessary secure functions to avoid
+voltage, temperature, frequency and mechanical attacks on the chip. It also
+embeds secure memories that can be scrambled
+
+required properties:
+- compatible: Should be "atmel,<chip>-secumod", "syscon".
+ <chip> can be "sama5d2".
+- reg: Should contain registers location and length
+
+ secumod at fc040000 {
+ compatible = "atmel,sama5d2-secumod", "syscon";
+ reg = <0xfc040000 0x100>;
+ };
+
--
2.9.3
^ permalink raw reply related
* [PATCH v2 0/6] Atmel sama5d2 security module support
From: Alexandre Belloni @ 2016-09-21 22:09 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
There has already been multiple tentatives trying to add support for the
Sama5d2 security module and in particular, access to its SRAM.
After multiple discussions, I believe adding support in the sram
driver/framework is probably the best because it allows exporting the
SRAM to the kernel, to userspace and also to run code from it.
As the support for the sama5d2 securam is fairly small, I've included it
directly in the mmio-sram driver.
Changes in v2:
- Fixed an issued in the sama5d2 dtsi
- Use regmap_read_poll_timeout and of_device_get_match_data as suggested by
Philipp
- Shrink the timeout to 500ms
- Added Rob's acks
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Alexandre Belloni (6):
Documentation: dt: atmel-at91: Document secumod bindings
ARM: at91: add secumod register definitions
ARM: dts: at91: sama5d2: Add secumod node
misc: sram: document new compatible
misc: sram: add Atmel securam support
ARM: dts: at91: sama5d2: Add securam node
.../devicetree/bindings/arm/atmel-at91.txt | 17 +++++++++
Documentation/devicetree/bindings/sram/sram.txt | 2 +-
arch/arm/boot/dts/sama5d2.dtsi | 19 ++++++++++
drivers/misc/sram.c | 42 ++++++++++++++++++----
include/soc/at91/atmel-secumod.h | 20 +++++++++++
5 files changed, 92 insertions(+), 8 deletions(-)
create mode 100644 include/soc/at91/atmel-secumod.h
--
2.9.3
^ permalink raw reply
* [PATCH] drm/sun4i: rgb: Enable panel after controller
From: Jonathan Liu @ 2016-09-21 22:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921210340.GI8719@lukather>
Hi Maxime,
On 22 September 2016 at 07:03, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Wed, Sep 21, 2016 at 11:03:04PM +1000, Jonathan Liu wrote:
>> The panel should be enabled after the controller so that the panel
>> prepare/enable delays are properly taken into account. Similarly, the
>> panel should be disabled before the controller so that the panel
>> unprepare/disable delays are properly taken into account.
>>
>> This is useful for avoiding visual glitches.
>
> This is not really taking any delays into account, especially since
> drm_panel_enable and prepare are suppose to block until their
> operation is complete.
drm_panel_prepare turns on power to the LCD using enable-gpios
property of the panel and then blocks for prepare delay. The prepare
delay for panel can be set to how long it takes between the time the
panel is powered to when it is ready to receive images. If backlight
property is specified the backlight will be off while the panel is
powered on.
drm_panel_enable blocks for enable delay and then turns on the
backlight. The enable delay can be set to how long it takes for panel
to start making the image visible after receiving the first valid
frame. For example if the panel starts off as white and the TFT takes
some time to initialize to black before it shows the image being
received.
Refer to drivers/gpu/drm/panel-panel.simple.c for details.
Regards,
Jonathan
^ permalink raw reply
* [GIT PULL 4/5] Freescale arm64 device tree updates for 4.9
From: Stuart Yoder @ 2016-09-21 21:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CALRxmdDLRPLr3yD_wGW+3=thr8eZwX4DVGzMad0Gh7n-ERi+og@mail.gmail.com>
> -----Original Message-----
> From: Arnd Bergmann <arnd@arndb.de>
> Date: Fri, Sep 16, 2016 at 8:42 AM
> Subject: Re: [GIT PULL 4/5] Freescale arm64 device tree updates for 4.9
> To: Shawn Guo <shawnguo@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>, arm at kernel.org,
> kernel at pengutronix.de, linux-arm-kernel at lists.infradead.org
>
>
> On Friday, September 16, 2016 9:47:03 AM CEST Shawn Guo wrote:
> > On Wed, Sep 14, 2016 at 05:30:49PM +0200, Arnd Bergmann wrote:
> > > On Monday, September 12, 2016 5:02:27 PM CEST Shawn Guo wrote:
> > > > i.MX arm64 device tree changes for 4.9:
> > > > - Add property dma-coherent for ls2080a PCI device to save software
> > > > cache maintenance.
> > > > - Update serial aliases and use stdout-path to sepecify console for
> > > > ls2080a and ls1043a boards.
> > > > - Add DDR memory controller device node for ls2080a and ls1043a SoCs.
> > > >
> > >
> > > Pulled into next/dt64, thanks!
> > >
> > > The "dma-coherent" change sounds like a bugfix, should that be backported
> > > to stable kernels? Usually if you lack that property on a device that
> > > is actually coherent, you can get silent data corruption by treating it as
> > > non-coherent.
> >
> > My impression is that those cache maintenance enforced for non-coherent
> > device will hurt performance on coherent device. I don't know it will
> > cause data corruption.
>
> The problem is that the device in this case is accessing data from
> the cache, while the CPU bypasses the cache for coherent mappings.
> The cache might have a stale cache line as the device reads data, or
> it could be in a writeback configuration, where the data written
> from the device to the cache has not made it into RAM at the time it
> is accessed by the CPU.
>
> For streaming mappings, the CPU will invalidate cache lines
> before reading the data, so again if the device has written data
> into the cache but not yet into memory, we will see stale data
> after dma_unmap_single().
I'm not following the potential data corruption issue. In this case
at least, DMA cohrerent devices are not directly reading or writing
any L1/L2 cache. If the device is writing a physical address, the write goes to
memory, and snoops invalidate any corresponding cache lines in L1/L2 caches.
If the device is reading a physical address, snoop transactions ensure that
dirty L1/L2 cache lines are written to memory and the device gets the right data.
The device is already sending the needed snoop transactions. The problem
is that because of the missing dma-coherent property the kernel doesn't know it
and unnecessarily does invalidates/flushes.
Thanks,
Stuart
^ permalink raw reply
* [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
From: Bjorn Helgaas @ 2016-09-21 21:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <VI1PR0401MB170983489310BF383C8C7E5B92F60@VI1PR0401MB1709.eurprd04.prod.outlook.com>
On Wed, Sep 21, 2016 at 06:51:55AM +0000, Po Liu wrote:
> Hi Bjorn,
>
> > -----Original Message-----
> > From: Bjorn Helgaas [mailto:helgaas at kernel.org]
> > Sent: Wednesday, September 21, 2016 4:47 AM
> > To: Po Liu
> > Cc: Roy Zang; Arnd Bergmann; devicetree at vger.kernel.org; Marc Zyngier;
> > linux-pci at vger.kernel.org; linux-kernel at vger.kernel.org; Stuart Yoder;
> > M.H. Lian; Murali Karicheri; Mingkai Hu; Bjorn Helgaas; Leo Li; Shawn
> > Guo; linux-arm-kernel at lists.infradead.org
> > Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
> >
> > On Mon, Aug 22, 2016 at 10:09:18AM +0000, Po Liu wrote:
> > > Hi Bjorn,
> > >
> > > Sorry for late reply.
> > >
> > > I checked the updated kernel with Dongdong mentioned ACPI patch which
> > was truly affected my quirk patch uploaded. So I suppose the quirk patch
> > is not qualify to fix the bug.
> >
> > I don't understand what you're saying here.
> >
> > The quirk worked on your machine. It apparently didn't work on
> > Dongdong's machine because of_irq_parse_and_map_pci() is run after the
> > quirk in this path:
> >
> > pci_device_probe
> > pcibios_alloc_irq # arm64
> > dev->irq = of_irq_parse_and_map_pci
> >
> > and of_irq_parse_and_map_pci() returned zero, probably because
> > of_irq_parse_pci() failed. My guess is that the reason it works on your
> > machine but not Dongdong's is that your DTs are different such that
> > of_irq_parse_pci() works for you but not for Dongdong.
> >
> > I think the idea of of_irq_parse_and_map_pci() is to set up a device's
> > INTx line. But that doesn't quite apply here because your device
> > doesn't actually *use* INTx. So I don't know why of_irq_parse_pci()
> > works for you. Maybe that's a symptom of a problem in your DT.
> >
> > Or maybe you're saying that the quirk *didn't* work on your machine when
> > you tested it in a kernel that included d8ed75d59332 ("ARM64:
> > PCI: ACPI support for legacy IRQs parsing and consolidation with DT
> > code").
>
> Yes, this point is what I mean. After this patch my quirk patch would not work.
> Since I discussed with Dongdong, the patches d8ed75d59332 ACPI related were not be merged yet.
>
>
> > But that doesn't make sense either, because prior to
> > d8ed75d59332, we *always* set
> >
> > dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> >
> > and after the patch we only do it if "acpi_disabled". I guess I just
> > don't understand what you're saying.
>
> Before the patch merged. pcibios_add_device()(which run the ->irq =
> of_irq_parse_and_map_pci(dev, 0, 0);) was loaded before the
> pci_fixup_device(pci_fixup_final). But after the patch
> d8ed75d59332("ARM64: PCI: ACPI support for legacy IRQs parsing and
> consolidation with DT code") merged, the
> pci_fixup_device(pci_fixup_final) run BEFORE the
> pcibios_alloc_irq()(which run the ->irq =
> of_irq_parse_and_map_pci(dev, 0, 0);). So the dev->irq were
> overwhelm by the pcibios_alloc_irq().
OK. Prior to d8ed75d59332, arm64 overrode the default empty
pcibios_add_device() implementation, and called
of_irq_parse_and_map_pci() there. d8ed75d59332 changed that function
to pcibios_alloc_irq(), which is called later, in the driver probe
path.
> When I test, the acpi_disabled is '1' although my kernel config
> default is CONFIG_ACPI=y. And no setting in the uboot with apci=xxx.
> But this is another issue, I didn't deep to check it.
Likely your platform just doesn't have ACPI or something's wrong in
the initial ACPI setup.
> > > I were keep thinking what your "explicitly checking for a root port
> > device" meaning. Do you mean I should upload again the first version
> > patch which fix it in the portdrv_core.c ? I would upload again if yes.
> >
> > No, I did not mean you should go back to the first version of the patch.
> > If we *can* do this in a quirk, I think that would be much better than
> > doing it in the PCIe port driver. I meant that Dongdong's suggestion of
> > adding this:
> >
> > if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
> > return;
> >
> > to your quirk made sense to me.
>
> If the quirk patch could make workaround. It should be the better way.
It doesn't sound like a quirk is going to work because all the quirks
run too early. I'll respond to the patch itself with more ideas.
> > > > -----Original Message-----
> > > > From: Bjorn Helgaas [mailto:helgaas at kernel.org]
> > > > Sent: Saturday, July 30, 2016 6:42 AM
> > > > To: Po Liu
> > > > Cc: linux-pci at vger.kernel.org;
> > > > linux-arm-kernel at lists.infradead.org;
> > > > linux-kernel at vger.kernel.org; devicetree at vger.kernel.org; Roy Zang;
> > > > Arnd Bergmann; Marc Zyngier; Stuart Yoder; Yang-Leo Li; Minghuan
> > > > Lian; Murali Karicheri; Bjorn Helgaas; Shawn Guo; Mingkai Hu
> > > > Subject: Re: [PATCH v3 2/2] pci/aer: interrupt fixup in the quirk
> > > >
> > > > On Tue, Jun 14, 2016 at 04:24:05PM +0800, Po Liu wrote:
> > > > > On some platforms, root port doesn't support MSI/MSI-X/INTx in RC
> > mode.
> > > > > When chip support the aer interrupt with none MSI/MSI-X/INTx
> > > > mode, > maybe there is interrupt line for aer pme etc. Search the
> > > > interrupt > number in the fdt file. Then fixup the dev->irq with it.
> > > > >
> > > > > Signed-off-by: Po Liu <po.liu@nxp.com>
> > > >
> > > > I'm not sure where we're at with this. Dongdong had some issue
> > > > (possibly with a version of the quirk on a different platform?), and
> > > > I think the suggestion of explicitly checking for a root port
> > > > device was a good one.
> > > >
> > > > So please update and repost this for next cycle.
> > > >
> > > > > ---
> > > > > changes for V3:
> > > > > - Move to quirk;
> > > > > - Only correct the irq in RC mode;
> > > > >
> > > > > drivers/pci/quirks.c | 29 +++++++++++++++++++++++++++++ > 1
> > > > file changed, 29 insertions(+) > > diff --git
> > > > a/drivers/pci/quirks.c b/drivers/pci/quirks.c index >
> > > > ee72ebe..8b39cce 100644 > --- a/drivers/pci/quirks.c > +++
> > > > b/drivers/pci/quirks.c > @@ -25,6 +25,7 @@ > #include
> > > > <linux/sched.h> > #include <linux/ktime.h> > #include
> > > > <linux/mm.h> > +#include <linux/of_irq.h>
> > > > > #include <asm/dma.h> /* isa_dma_bridge_buggy */
> > > > > #include "pci.h"
> > > > >
> > > > > @@ -4419,3 +4420,31 @@ static void quirk_intel_qat_vf_cap(struct
> > > > pci_dev *pdev)
> > > > > }
> > > > > }
> > > > > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, >
> > > > quirk_intel_qat_vf_cap); > + > +/* If root port doesn't support
> > > > MSI/MSI-X/INTx in RC mode, > + * but use standalone irq. Read the
> > > > device tree for the aer > + * interrupt number.
> > > > > + */
> > > > > +static void quirk_aer_interrupt(struct pci_dev *dev) {
> > > > > + int ret;
> > > > > + u8 header_type;
> > > > > + struct device_node *np = NULL;
> > > > > +
> > > > > + /* Only for the RC mode device */
> > > > > + pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
> > > > > + if ((header_type & 0x7F) != PCI_HEADER_TYPE_BRIDGE)
> > > > > + return;
> > > > > +
> > > > > + if (dev->bus->dev.of_node)
> > > > > + np = dev->bus->dev.of_node;
> > > > > +
> > > > > + if (IS_ENABLED(CONFIG_OF_IRQ) && np) {
> > > > > + ret = of_irq_get_byname(np, "aer");
> > > > > + if (ret > 0) {
> > > > > + dev->no_msi = 1;
> > > > > + dev->irq = ret;
> > > > > + }
> > > > > + }
> > > > > +}
> > > > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, >
> > > > +quirk_aer_interrupt); > -- > 2.1.0.27.g96db324 > > >
> > > > _______________________________________________
> > > > > linux-arm-kernel mailing list
> > > > > linux-arm-kernel at lists.infradead.org
> > > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > > _______________________________________________
> > > linux-arm-kernel mailing list
> > > linux-arm-kernel at lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] clk: nxp: clk-lpc32xx: Unmap region obtained by of_iomap
From: Stephen Boyd @ 2016-09-21 21:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474368846-15916-1-git-send-email-arvind.yadav.cs@gmail.com>
On 09/20, Arvind Yadav wrote:
> From: Arvind Yadav <arvind.yadav.cs@gmail.com>
>
> Free memory mapping, if lpc32xx_clk_init is not successful.
>
> Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [RFC PATCH] PCI/ACPI: xgene: Add ECAM quirk for X-Gene PCIe controller
From: Bjorn Helgaas @ 2016-09-21 21:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CADaLNDmYoYAiufYFrwhWjPBj29XPBSx1FydoM67v0c03D8N7vQ@mail.gmail.com>
On Mon, Sep 19, 2016 at 06:07:37PM -0700, Duc Dang wrote:
> On Mon, Sep 19, 2016 at 1:06 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> > On Sat, Sep 17, 2016 at 07:24:38AM -0700, Duc Dang wrote:
> This patch only adds the ability for X-Gene PCIe controller to be
> probable in ACPI boot mode. All the 'quirk' code added is for ECAM to
> work with X-Gene.
>
> > I sort of expected this to also remove, for example, the seemingly
> > identical xgene_pcie_config_read32() in drivers/pci/host/pci-xgene.c.
> > Actually, a bunch of this code seems to be duplicated from there. It
> > doesn't seem like we should end up with all this duplicated code.
> >
> > I'd really like it better if all this could get folded into
> > pci-xgene.c so we don't end up with more files.
>
> I am still debating whether to put this X-Gene ECAM quirk code into
> drivers/acpi or keep it here in drivers/pci/host. But given the
> direction of other quirk patches for ThunderX and HiSi, seem like the
> quirk will stay in drivers/pci/host. I can definitely fold the new
> quirk code into pci-xgene.c as you suggested and eliminate the
> identical one.
I like Tomasz's patches, where the MCFG quirk itself is in
acpi/pci_mcfg.c, and it uses config accessors exported from
drivers/pci/host.
I do not want to end up with duplicate accessors. The mapping
functions and accessors should be the same whether we're booting with
DT or ACPI.
I think a patch to add ACPI support should only contain:
- acpi/pci_mcfg.c quirks to fix incorrect ACPI MCFG resources or use
special accessors,
- pnp/quirks.c quirks to compensate for missing ACPI _CRS for the
ECAM regions, and
- pci-xgene.c code to derive the csr_base and cfg_base. Today we
get that from DT, but the _CRS producer/consumer mess means we
don't have a good way to get it from ACPI, so you'll need some
sort of quirk for this.
> >> +struct xgene_pcie_acpi_root {
> >> + void __iomem *csr_base;
> >> + u32 version;
> >> +};
> >
> > I think this should be folded into struct xgene_pcie_port so we don't
> > have to allocate and manage it separately.
>
> I will need to look into this more. When booting with ACPI mode, the
> code in pci-xgene.c is not used (except the cfg read/write functions
> that are shared with ECAM quirk code), so puting these into
> xgene_pcie_port will force ECAM quirk code to allocate this structure
> as well.
This information is needed whether booting with DT or ACPI, so we
should use the existing xgene_pcie_port.csr_base and initialize it
differently depending on which we're using.
> >> + default:
> >> + return -ENODEV;
> >> + }
> >> +
> >> + xgene_root->csr_base = ioremap(csr_base, XGENE_CSR_LENGTH);
> >
> > There should be a request_region() somewhere, too. Ideal would be to
> > use devm_ioremap_resource(), but I don't know where this apparent
> > resource is coming from.
>
> Yes, I will use request_region/devm_ioremap_resource here.
We're not *adding* any new resources that need ioremapping; all we're
doing is changing the *source* of the resource, so we should use the
same devm_ioremap_resource() you already have in xgene_pcie_map_reg().
You might have to refactor that slightly so we can lookup the resource
via either DT or ACPI (you'll probably actually use a quirk since ACPI
doesn't have a good mechanism for this), and then use the same call to
devm_ioremap_resource().
Bjorn
^ permalink raw reply
* [PATCH v6] soc: qcom: add l2 cache perf events driver
From: Neil Leeder @ 2016-09-21 21:12 UTC (permalink / raw)
To: linux-arm-kernel
Adds perf events support for L2 cache PMU.
The L2 cache PMU driver is named 'l2cache_0' and can be used
with perf events to profile L2 events such as cache hits
and misses.
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
---
v6: restore accidentally dropped Kconfig dependencies
v5:
Fold the header and l2-accessors into .c file
Use multi-instance framework for hotplug
Change terminology from slice to cluster for clarity
Remove unnecessary rmw sequence for enable registers
Use prev_count in hwc rather than in slice
Enforce all events in same group on same CPU
Add comments, rename variables for clarity
v4:
Replace notifier with hotplug statemachine
Allocate PMU struct dynamically
v3:
Remove exports from l2-accessors
Change l2-accessors Kconfig to make it not user-selectable
Reorder and remove unnecessary includes
v2:
Add the l2-accessors patch to this patchset, previously posted separately.
Remove sampling and per-task functionality for this uncore PMU.
Use cpumask to replace code which filtered events to one cpu per slice.
Replace manual event filtering with filter_match callback.
Use a separate used_mask for event groups.
Add hotplug notifier for CPU and irq migration.
Remove extraneous synchronisation instructions.
Other miscellaneous cleanup.
drivers/soc/qcom/Kconfig | 9 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/perf_event_l2.c | 948 +++++++++++++++++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
4 files changed, 959 insertions(+)
create mode 100644 drivers/soc/qcom/perf_event_l2.c
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 461b387..3fa27a8 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -10,6 +10,15 @@ config QCOM_GSBI
functions for connecting the underlying serial UART, SPI, and I2C
devices to the output pins.
+config QCOM_PERF_EVENTS_L2
+ bool "Qualcomm Technologies L2-cache perf events"
+ depends on ARCH_QCOM && ARM64 && HW_PERF_EVENTS && ACPI
+ help
+ Provides support for the L2 cache performance monitor unit (PMU)
+ in Qualcomm Technologies processors.
+ Adds the L2 cache PMU into the perf events subsystem for
+ monitoring L2 cache events.
+
config QCOM_PM
bool "Qualcomm Power Management"
depends on ARCH_QCOM && !ARM64
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index fdd664e..4c9df3b 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
+obj-$(CONFIG_QCOM_PERF_EVENTS_L2) += perf_event_l2.o
obj-$(CONFIG_QCOM_PM) += spm.o
obj-$(CONFIG_QCOM_SMD) += smd.o
obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o
diff --git a/drivers/soc/qcom/perf_event_l2.c b/drivers/soc/qcom/perf_event_l2.c
new file mode 100644
index 0000000..bbf47c9
--- /dev/null
+++ b/drivers/soc/qcom/perf_event_l2.c
@@ -0,0 +1,948 @@
+/* Copyright (c) 2015,2016 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/acpi.h>
+#include <linux/interrupt.h>
+#include <linux/perf_event.h>
+#include <linux/platform_device.h>
+
+#define MAX_L2_CTRS 9
+
+#define L2PMCR_NUM_EV_SHIFT 11
+#define L2PMCR_NUM_EV_MASK 0x1F
+
+#define L2PMCR 0x400
+#define L2PMCNTENCLR 0x403
+#define L2PMCNTENSET 0x404
+#define L2PMINTENCLR 0x405
+#define L2PMINTENSET 0x406
+#define L2PMOVSCLR 0x407
+#define L2PMOVSSET 0x408
+#define L2PMCCNTCR 0x409
+#define L2PMCCNTR 0x40A
+#define L2PMCCNTSR 0x40C
+#define L2PMRESR 0x410
+#define IA_L2PMXEVCNTCR_BASE 0x420
+#define IA_L2PMXEVCNTR_BASE 0x421
+#define IA_L2PMXEVFILTER_BASE 0x423
+#define IA_L2PMXEVTYPER_BASE 0x424
+
+#define IA_L2_REG_OFFSET 0x10
+
+#define L2PMXEVFILTER_SUFILTER_ALL 0x000E0000
+#define L2PMXEVFILTER_ORGFILTER_IDINDEP 0x00000004
+#define L2PMXEVFILTER_ORGFILTER_ALL 0x00000003
+
+#define L2PM_CC_ENABLE 0x80000000
+
+#define L2EVTYPER_REG_SHIFT 3
+
+#define L2PMRESR_GROUP_BITS 8
+#define L2PMRESR_GROUP_MASK GENMASK(7, 0)
+
+#define L2CYCLE_CTR_BIT 31
+#define L2CYCLE_CTR_RAW_CODE 0xFE
+
+#define L2PMCR_RESET_ALL 0x6
+#define L2PMCR_COUNTERS_ENABLE 0x1
+#define L2PMCR_COUNTERS_DISABLE 0x0
+
+#define L2PMRESR_EN ((u64)1 << 63)
+
+#define L2_EVT_MASK 0x00000FFF
+#define L2_EVT_CODE_MASK 0x00000FF0
+#define L2_EVT_GRP_MASK 0x0000000F
+#define L2_EVT_CODE_SHIFT 4
+#define L2_EVT_GRP_SHIFT 0
+
+#define L2_EVT_CODE(event) (((event) & L2_EVT_CODE_MASK) >> L2_EVT_CODE_SHIFT)
+#define L2_EVT_GROUP(event) (((event) & L2_EVT_GRP_MASK) >> L2_EVT_GRP_SHIFT)
+
+#define L2_EVT_GROUP_MAX 7
+
+#define L2_MAX_PERIOD U32_MAX
+#define L2_CNT_PERIOD (U32_MAX - GENMASK(26, 0))
+
+#define L2CPUSRSELR_EL1 S3_3_c15_c0_6
+#define L2CPUSRDR_EL1 S3_3_c15_c0_7
+
+static DEFINE_RAW_SPINLOCK(l2_access_lock);
+
+/**
+ * set_l2_indirect_reg: write value to an L2 register
+ * @reg: Address of L2 register.
+ * @value: Value to be written to register.
+ *
+ * Use architecturally required barriers for ordering between system register
+ * accesses
+ */
+static void set_l2_indirect_reg(u64 reg, u64 val)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&l2_access_lock, flags);
+ write_sysreg(reg, L2CPUSRSELR_EL1);
+ isb();
+ write_sysreg(val, L2CPUSRDR_EL1);
+ isb();
+ raw_spin_unlock_irqrestore(&l2_access_lock, flags);
+}
+
+/**
+ * get_l2_indirect_reg: read an L2 register value
+ * @reg: Address of L2 register.
+ *
+ * Use architecturally required barriers for ordering between system register
+ * accesses
+ */
+static u64 get_l2_indirect_reg(u64 reg)
+{
+ u64 val;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&l2_access_lock, flags);
+ write_sysreg(reg, L2CPUSRSELR_EL1);
+ isb();
+ val = read_sysreg(L2CPUSRDR_EL1);
+ raw_spin_unlock_irqrestore(&l2_access_lock, flags);
+
+ return val;
+}
+
+/*
+ * Aggregate PMU. Implements the core pmu functions and manages
+ * the hardware PMUs.
+ */
+struct l2cache_pmu {
+ struct hlist_node node;
+ u32 num_pmus;
+ struct pmu pmu;
+ int num_counters;
+ cpumask_t cpumask;
+ struct platform_device *pdev;
+};
+
+/*
+ * The cache is made up of one or more clusters, each cluster has its own PMU.
+ * Each cluster is associated with one or more CPUs.
+ * This structure represents one of the hardware PMUs.
+ *
+ * Events can be envisioned as a 2-dimensional array. Each column represents
+ * a group of events. There are 8 groups. Only one entry from each
+ * group can be in use at a time. When an event is assigned a counter
+ * by *_event_add(), the counter index is assigned to group_to_counter[group].
+ * This allows *filter_match() to detect and reject conflicting events in
+ * the same group.
+ * Events are specified as 0xCCG, where CC is 2 hex digits specifying
+ * the code (array row) and G specifies the group (column).
+ *
+ * In addition there is a cycle counter event specified by L2CYCLE_CTR_RAW_CODE
+ * which is outside the above scheme.
+ */
+struct hml2_pmu {
+ struct perf_event *events[MAX_L2_CTRS];
+ struct l2cache_pmu *l2cache_pmu;
+ DECLARE_BITMAP(used_counters, MAX_L2_CTRS);
+ DECLARE_BITMAP(used_groups, L2_EVT_GROUP_MAX + 1);
+ int group_to_counter[L2_EVT_GROUP_MAX + 1];
+ int irq;
+ /* The CPU that is used for collecting events on this cluster */
+ int on_cpu;
+ /* All the CPUs associated with this cluster */
+ cpumask_t cluster_cpus;
+ spinlock_t pmu_lock;
+};
+
+#define to_l2cache_pmu(p) (container_of(p, struct l2cache_pmu, pmu))
+
+static DEFINE_PER_CPU(struct hml2_pmu *, pmu_cluster);
+static u32 l2_cycle_ctr_idx;
+static u32 l2_counter_present_mask;
+
+static inline u32 idx_to_reg_bit(u32 idx)
+{
+ if (idx == l2_cycle_ctr_idx)
+ return BIT(L2CYCLE_CTR_BIT);
+
+ return BIT(idx);
+}
+
+static inline struct hml2_pmu *get_hml2_pmu(int cpu)
+{
+ return per_cpu(pmu_cluster, cpu);
+}
+
+static void hml2_pmu__reset_on_cluster(void *x)
+{
+ /* Reset all ctrs */
+ set_l2_indirect_reg(L2PMCR, L2PMCR_RESET_ALL);
+ set_l2_indirect_reg(L2PMCNTENCLR, l2_counter_present_mask);
+ set_l2_indirect_reg(L2PMINTENCLR, l2_counter_present_mask);
+ set_l2_indirect_reg(L2PMOVSCLR, l2_counter_present_mask);
+}
+
+static inline void hml2_pmu__reset(struct hml2_pmu *cluster)
+{
+ cpumask_t *mask = &cluster->cluster_cpus;
+
+ if (smp_call_function_any(mask, hml2_pmu__reset_on_cluster, NULL, 1))
+ dev_err(&cluster->l2cache_pmu->pdev->dev,
+ "Failed to reset on cluster with cpu %d\n",
+ cpumask_first(&cluster->cluster_cpus));
+}
+
+static inline void hml2_pmu__enable(void)
+{
+ set_l2_indirect_reg(L2PMCR, L2PMCR_COUNTERS_ENABLE);
+}
+
+static inline void hml2_pmu__disable(void)
+{
+ set_l2_indirect_reg(L2PMCR, L2PMCR_COUNTERS_DISABLE);
+}
+
+static inline void hml2_pmu__counter_set_value(u32 idx, u64 value)
+{
+ u32 counter_reg;
+
+ if (idx == l2_cycle_ctr_idx) {
+ set_l2_indirect_reg(L2PMCCNTR, value);
+ } else {
+ counter_reg = (idx * IA_L2_REG_OFFSET) + IA_L2PMXEVCNTR_BASE;
+ set_l2_indirect_reg(counter_reg, value & GENMASK(31, 0));
+ }
+}
+
+static inline u64 hml2_pmu__counter_get_value(u32 idx)
+{
+ u64 value;
+ u32 counter_reg;
+
+ if (idx == l2_cycle_ctr_idx) {
+ value = get_l2_indirect_reg(L2PMCCNTR);
+ } else {
+ counter_reg = (idx * IA_L2_REG_OFFSET) + IA_L2PMXEVCNTR_BASE;
+ value = get_l2_indirect_reg(counter_reg);
+ }
+
+ return value;
+}
+
+static inline void hml2_pmu__counter_enable(u32 idx)
+{
+ set_l2_indirect_reg(L2PMCNTENSET, idx_to_reg_bit(idx));
+}
+
+static inline void hml2_pmu__counter_disable(u32 idx)
+{
+ set_l2_indirect_reg(L2PMCNTENCLR, idx_to_reg_bit(idx));
+}
+
+static inline void hml2_pmu__counter_enable_interrupt(u32 idx)
+{
+ set_l2_indirect_reg(L2PMINTENSET, idx_to_reg_bit(idx));
+}
+
+static inline void hml2_pmu__counter_disable_interrupt(u32 idx)
+{
+ set_l2_indirect_reg(L2PMINTENCLR, idx_to_reg_bit(idx));
+}
+
+static inline void hml2_pmu__set_evccntcr(u32 val)
+{
+ set_l2_indirect_reg(L2PMCCNTCR, val);
+}
+
+static inline void hml2_pmu__set_evcntcr(u32 ctr, u32 val)
+{
+ u32 evtcr_reg = (ctr * IA_L2_REG_OFFSET) + IA_L2PMXEVCNTCR_BASE;
+
+ set_l2_indirect_reg(evtcr_reg, val);
+}
+
+static inline void hml2_pmu__set_evtyper(u32 ctr, u32 val)
+{
+ u32 evtype_reg = (ctr * IA_L2_REG_OFFSET) + IA_L2PMXEVTYPER_BASE;
+
+ set_l2_indirect_reg(evtype_reg, val);
+}
+
+static void hml2_pmu__set_resr(struct hml2_pmu *cluster,
+ u32 event_group, u32 event_cc)
+{
+ u64 field;
+ u64 resr_val;
+ u32 shift;
+ unsigned long flags;
+
+ shift = L2PMRESR_GROUP_BITS * event_group;
+ field = ((u64)(event_cc & L2PMRESR_GROUP_MASK) << shift) | L2PMRESR_EN;
+
+ spin_lock_irqsave(&cluster->pmu_lock, flags);
+
+ resr_val = get_l2_indirect_reg(L2PMRESR);
+ resr_val &= ~(L2PMRESR_GROUP_MASK << shift);
+ resr_val |= field;
+ set_l2_indirect_reg(L2PMRESR, resr_val);
+
+ spin_unlock_irqrestore(&cluster->pmu_lock, flags);
+}
+
+/*
+ * Hardware allows filtering of events based on the originating
+ * CPU. Turn this off by setting filter bits to allow events from
+ * all CPUS, subunits and ID independent events in this cluster.
+ */
+static inline void hml2_pmu__set_evfilter_sys_mode(u32 ctr)
+{
+ u32 reg = (ctr * IA_L2_REG_OFFSET) + IA_L2PMXEVFILTER_BASE;
+ u32 val = L2PMXEVFILTER_SUFILTER_ALL |
+ L2PMXEVFILTER_ORGFILTER_IDINDEP |
+ L2PMXEVFILTER_ORGFILTER_ALL;
+
+ set_l2_indirect_reg(reg, val);
+}
+
+static inline u32 hml2_pmu__getreset_ovsr(void)
+{
+ u32 result = get_l2_indirect_reg(L2PMOVSSET);
+
+ set_l2_indirect_reg(L2PMOVSCLR, result);
+ return result;
+}
+
+static inline bool hml2_pmu__has_overflowed(u32 ovsr)
+{
+ return !!(ovsr & l2_counter_present_mask);
+}
+
+static inline bool hml2_pmu__counter_has_overflowed(u32 ovsr, u32 idx)
+{
+ return !!(ovsr & idx_to_reg_bit(idx));
+}
+
+static void l2_cache__event_update_from_cluster(struct perf_event *event,
+ struct hml2_pmu *cluster)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ u64 delta64, prev, now;
+ u32 delta;
+ u32 idx = hwc->idx;
+
+ do {
+ prev = local64_read(&hwc->prev_count);
+ now = hml2_pmu__counter_get_value(idx);
+ } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev);
+
+ if (idx == l2_cycle_ctr_idx) {
+ /*
+ * The cycle counter is 64-bit so needs separate handling
+ * of 64-bit delta.
+ */
+ delta64 = now - prev;
+ local64_add(delta64, &event->count);
+ } else {
+ /*
+ * 32-bit counters need the unsigned 32-bit math to handle
+ * overflow and now < prev
+ */
+ delta = now - prev;
+ local64_add(delta, &event->count);
+ }
+}
+
+static void l2_cache__cluster_set_period(struct hml2_pmu *cluster,
+ struct hw_perf_event *hwc)
+{
+ u64 base = L2_MAX_PERIOD - (L2_CNT_PERIOD - 1);
+ u32 idx = hwc->idx;
+ u64 prev = local64_read(&hwc->prev_count);
+ u64 value;
+
+ /*
+ * Limit the maximum period to prevent the counter value
+ * from overtaking the one we are about to program.
+ * Use a starting value which is high enough that after
+ * an overflow, interrupt latency will not cause the count
+ * to reach the base value. If the previous value
+ * is below the base, increase it to be above the base
+ * and update prev_count accordingly. Otherwise if
+ * the previous value is already above the base
+ * nothing needs to be done to prev_count.
+ */
+ if (prev < base) {
+ value = base + prev;
+ local64_set(&hwc->prev_count, value);
+ } else {
+ value = prev;
+ }
+
+ hml2_pmu__counter_set_value(idx, value);
+}
+
+static int l2_cache__get_event_idx(struct hml2_pmu *cluster,
+ struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ int idx;
+
+ if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) {
+ if (test_and_set_bit(l2_cycle_ctr_idx, cluster->used_counters))
+ return -EAGAIN;
+
+ return l2_cycle_ctr_idx;
+ }
+
+ for (idx = 0; idx < cluster->l2cache_pmu->num_counters - 1; idx++) {
+ if (!test_and_set_bit(idx, cluster->used_counters)) {
+ set_bit(L2_EVT_GROUP(hwc->config_base),
+ cluster->used_groups);
+ return idx;
+ }
+ }
+
+ /* The counters are all in use. */
+ return -EAGAIN;
+}
+
+static void l2_cache__clear_event_idx(struct hml2_pmu *cluster,
+ struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+
+ clear_bit(idx, cluster->used_counters);
+ if (hwc->config_base != L2CYCLE_CTR_RAW_CODE)
+ clear_bit(L2_EVT_GROUP(hwc->config_base), cluster->used_groups);
+}
+
+static irqreturn_t l2_cache__handle_irq(int irq_num, void *data)
+{
+ struct hml2_pmu *cluster = data;
+ int num_counters = cluster->l2cache_pmu->num_counters;
+ u32 ovsr;
+ int idx;
+
+ ovsr = hml2_pmu__getreset_ovsr();
+ if (!hml2_pmu__has_overflowed(ovsr))
+ return IRQ_NONE;
+
+ for_each_set_bit(idx, cluster->used_counters, num_counters) {
+ struct perf_event *event = cluster->events[idx];
+ struct hw_perf_event *hwc;
+
+ if (!hml2_pmu__counter_has_overflowed(ovsr, idx))
+ continue;
+
+ l2_cache__event_update_from_cluster(event, cluster);
+ hwc = &event->hw;
+
+ l2_cache__cluster_set_period(cluster, hwc);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * Implementation of abstract pmu functionality required by
+ * the core perf events code.
+ */
+
+static void l2_cache__pmu_enable(struct pmu *pmu)
+{
+ /*
+ * Although there is only one PMU (per socket) controlling multiple
+ * physical PMUs (per cluster), because we do not support per-task mode
+ * each event is associated with a CPU. Each event has pmu_enable
+ * called on its CPU, so here it is only necessary to enable the
+ * counters for the current CPU.
+ */
+
+ hml2_pmu__enable();
+}
+
+static void l2_cache__pmu_disable(struct pmu *pmu)
+{
+ hml2_pmu__disable();
+}
+
+static int l2_cache__event_init(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hml2_pmu *cluster;
+ struct perf_event *sibling;
+ struct l2cache_pmu *l2cache_pmu;
+
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ l2cache_pmu = to_l2cache_pmu(event->pmu);
+
+ if (hwc->sample_period) {
+ dev_warn(&l2cache_pmu->pdev->dev, "Sampling not supported\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (event->cpu < 0) {
+ dev_warn(&l2cache_pmu->pdev->dev, "Per-task mode not supported\n");
+ return -EOPNOTSUPP;
+ }
+
+ /* We cannot filter accurately so we just don't allow it. */
+ if (event->attr.exclude_user || event->attr.exclude_kernel ||
+ event->attr.exclude_hv || event->attr.exclude_idle) {
+ dev_warn(&l2cache_pmu->pdev->dev, "Can't exclude execution levels\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (((L2_EVT_GROUP(event->attr.config) > L2_EVT_GROUP_MAX) ||
+ ((event->attr.config & ~L2_EVT_MASK) != 0)) &&
+ (event->attr.config != L2CYCLE_CTR_RAW_CODE)) {
+ dev_warn(&l2cache_pmu->pdev->dev, "Invalid config %llx\n",
+ event->attr.config);
+ return -EINVAL;
+ }
+
+ /* Don't allow groups with mixed PMUs, except for s/w events */
+ if (event->group_leader->pmu != event->pmu &&
+ !is_software_event(event->group_leader)) {
+ dev_warn(&l2cache_pmu->pdev->dev,
+ "Can't create mixed PMU group\n");
+ return -EINVAL;
+ }
+
+ list_for_each_entry(sibling, &event->group_leader->sibling_list,
+ group_entry)
+ if (sibling->pmu != event->pmu &&
+ !is_software_event(sibling)) {
+ dev_warn(&l2cache_pmu->pdev->dev,
+ "Can't create mixed PMU group\n");
+ return -EINVAL;
+ }
+
+ /* Ensure all events in a group are on the same cpu */
+ cluster = get_hml2_pmu(event->cpu);
+ if ((event->group_leader != event) &&
+ (cluster->on_cpu != event->group_leader->cpu)) {
+ dev_warn(&l2cache_pmu->pdev->dev,
+ "Can't create group on CPUs %d and %d",
+ event->cpu, event->group_leader->cpu);
+ return -EINVAL;
+ }
+
+ hwc->idx = -1;
+ hwc->config_base = event->attr.config;
+
+ /*
+ * Ensure all events are on the same cpu so all events are in the
+ * same cpu context, to avoid races on pmu_enable etc.
+ */
+ event->cpu = cluster->on_cpu;
+
+ return 0;
+}
+
+static void l2_cache__event_start(struct perf_event *event, int flags)
+{
+ struct hml2_pmu *cluster;
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+ u32 config;
+ u32 event_cc, event_group;
+
+ hwc->state = 0;
+
+ cluster = get_hml2_pmu(event->cpu);
+ l2_cache__cluster_set_period(cluster, hwc);
+
+ if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) {
+ hml2_pmu__set_evccntcr(0x0);
+ } else {
+ config = hwc->config_base;
+ event_cc = L2_EVT_CODE(config);
+ event_group = L2_EVT_GROUP(config);
+
+ hml2_pmu__set_evcntcr(idx, 0x0);
+ hml2_pmu__set_evtyper(idx, event_group);
+ hml2_pmu__set_resr(cluster, event_group, event_cc);
+ hml2_pmu__set_evfilter_sys_mode(idx);
+ }
+
+ hml2_pmu__counter_enable_interrupt(idx);
+ hml2_pmu__counter_enable(idx);
+}
+
+static void l2_cache__event_stop(struct perf_event *event, int flags)
+{
+ struct hml2_pmu *cluster;
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+
+ if (!(hwc->state & PERF_HES_STOPPED)) {
+ cluster = get_hml2_pmu(event->cpu);
+ hml2_pmu__counter_disable_interrupt(idx);
+ hml2_pmu__counter_disable(idx);
+
+ if (flags & PERF_EF_UPDATE)
+ l2_cache__event_update_from_cluster(event, cluster);
+ hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
+ }
+}
+
+static int l2_cache__event_add(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ int idx;
+ int err = 0;
+ struct hml2_pmu *cluster;
+
+ cluster = get_hml2_pmu(event->cpu);
+
+ idx = l2_cache__get_event_idx(cluster, event);
+ if (idx < 0) {
+ err = idx;
+ return err;
+ }
+
+ hwc->idx = idx;
+ hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
+ cluster->events[idx] = event;
+ cluster->group_to_counter[L2_EVT_GROUP(hwc->config_base)] = idx;
+ local64_set(&hwc->prev_count, 0ULL);
+
+ if (flags & PERF_EF_START)
+ l2_cache__event_start(event, flags);
+
+ /* Propagate changes to the userspace mapping. */
+ perf_event_update_userpage(event);
+
+ return err;
+}
+
+static void l2_cache__event_del(struct perf_event *event, int flags)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hml2_pmu *cluster;
+ int idx = hwc->idx;
+
+ cluster = get_hml2_pmu(event->cpu);
+ l2_cache__event_stop(event, flags | PERF_EF_UPDATE);
+ cluster->events[idx] = NULL;
+ l2_cache__clear_event_idx(cluster, event);
+
+ perf_event_update_userpage(event);
+}
+
+static void l2_cache__event_read(struct perf_event *event)
+{
+ l2_cache__event_update_from_cluster(event, get_hml2_pmu(event->cpu));
+}
+
+static int l2_cache_filter_match(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ struct hml2_pmu *cluster = get_hml2_pmu(event->cpu);
+ unsigned int group = L2_EVT_GROUP(hwc->config_base);
+
+ /* check for column exclusion: group already in use by another event */
+ if (test_bit(group, cluster->used_groups) &&
+ cluster->events[cluster->group_to_counter[group]] != event)
+ return 0;
+
+ return 1;
+}
+
+static ssize_t l2_cache_pmu_cpumask_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct l2cache_pmu *l2cache_pmu = to_l2cache_pmu(dev_get_drvdata(dev));
+
+ return cpumap_print_to_pagebuf(true, buf, &l2cache_pmu->cpumask);
+}
+
+static struct device_attribute l2_cache_pmu_cpumask_attr =
+ __ATTR(cpumask, S_IRUGO, l2_cache_pmu_cpumask_show, NULL);
+
+static struct attribute *l2_cache_pmu_cpumask_attrs[] = {
+ &l2_cache_pmu_cpumask_attr.attr,
+ NULL,
+};
+
+static struct attribute_group l2_cache_pmu_cpumask_group = {
+ .attrs = l2_cache_pmu_cpumask_attrs,
+};
+
+/* CCG format for perf RAW codes. */
+PMU_FORMAT_ATTR(l2_code, "config:4-11");
+PMU_FORMAT_ATTR(l2_group, "config:0-3");
+static struct attribute *l2_cache_pmu_formats[] = {
+ &format_attr_l2_code.attr,
+ &format_attr_l2_group.attr,
+ NULL,
+};
+
+static struct attribute_group l2_cache_pmu_format_group = {
+ .name = "format",
+ .attrs = l2_cache_pmu_formats,
+};
+
+static const struct attribute_group *l2_cache_pmu_attr_grps[] = {
+ &l2_cache_pmu_format_group,
+ &l2_cache_pmu_cpumask_group,
+ NULL,
+};
+
+/*
+ * Generic device handlers
+ */
+
+static const struct acpi_device_id l2_cache_pmu_acpi_match[] = {
+ { "QCOM8130", },
+ { }
+};
+
+static int get_num_counters(void)
+{
+ int val;
+
+ val = get_l2_indirect_reg(L2PMCR);
+
+ /*
+ * Read number of counters from L2PMCR and add 1
+ * for the cycle counter.
+ */
+ return ((val >> L2PMCR_NUM_EV_SHIFT) & L2PMCR_NUM_EV_MASK) + 1;
+}
+
+static int l2cache_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct hml2_pmu *cluster;
+ cpumask_t cluster_online_cpus;
+ struct l2cache_pmu *l2cache_pmu;
+
+ l2cache_pmu = hlist_entry_safe(node, struct l2cache_pmu, node);
+ cluster = get_hml2_pmu(cpu);
+ cpumask_and(&cluster_online_cpus, &cluster->cluster_cpus,
+ cpu_online_mask);
+
+ if (cpumask_weight(&cluster_online_cpus) == 1) {
+ /* all CPUs on this cluster were down, use this one */
+ cluster->on_cpu = cpu;
+ cpumask_set_cpu(cpu, &l2cache_pmu->cpumask);
+ WARN_ON(irq_set_affinity(cluster->irq, cpumask_of(cpu)));
+ }
+
+ return 0;
+}
+
+static int l2cache_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct hml2_pmu *cluster;
+ struct l2cache_pmu *l2cache_pmu;
+ cpumask_t cluster_online_cpus;
+ unsigned int target;
+
+ l2cache_pmu = hlist_entry_safe(node, struct l2cache_pmu, node);
+
+ if (!cpumask_test_and_clear_cpu(cpu, &l2cache_pmu->cpumask))
+ return 0;
+ cluster = get_hml2_pmu(cpu);
+ cpumask_and(&cluster_online_cpus, &cluster->cluster_cpus,
+ cpu_online_mask);
+
+ /* Any other CPU for this cluster which is still online */
+ target = cpumask_any_but(&cluster_online_cpus, cpu);
+ if (target >= nr_cpu_ids)
+ return 0;
+
+ perf_pmu_migrate_context(&l2cache_pmu->pmu, cpu, target);
+ cluster->on_cpu = target;
+ cpumask_set_cpu(target, &l2cache_pmu->cpumask);
+ WARN_ON(irq_set_affinity(cluster->irq, cpumask_of(target)));
+
+ return 0;
+}
+
+static int l2_cache_pmu_probe_cluster(struct device *dev, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev->parent);
+ struct platform_device *sdev = to_platform_device(dev);
+ struct l2cache_pmu *l2cache_pmu = data;
+ struct hml2_pmu *cluster;
+ struct acpi_device *device;
+ unsigned long fw_cluster_id;
+ int cpu;
+ int err;
+ int irq;
+
+ if (acpi_bus_get_device(ACPI_HANDLE(dev), &device))
+ return -ENODEV;
+
+ if (kstrtol(device->pnp.unique_id, 10, &fw_cluster_id) < 0) {
+ dev_err(&pdev->dev, "unable to read ACPI uid\n");
+ return -ENODEV;
+ }
+
+ irq = platform_get_irq(sdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev,
+ "Failed to get valid irq for cluster %ld\n",
+ fw_cluster_id);
+ return irq;
+ }
+
+ cluster = devm_kzalloc(&pdev->dev, sizeof(*cluster), GFP_KERNEL);
+ if (!cluster)
+ return -ENOMEM;
+
+ cluster->l2cache_pmu = l2cache_pmu;
+ for_each_present_cpu(cpu) {
+ if (topology_physical_package_id(cpu) == fw_cluster_id) {
+ cpumask_set_cpu(cpu, &cluster->cluster_cpus);
+ per_cpu(pmu_cluster, cpu) = cluster;
+ }
+ }
+ cluster->irq = irq;
+
+ if (cpumask_empty(&cluster->cluster_cpus)) {
+ dev_err(&pdev->dev, "No CPUs found for L2 cache instance %ld\n",
+ fw_cluster_id);
+ return -ENODEV;
+ }
+
+ /* Pick one CPU to be the preferred one to use in the cluster */
+ cluster->on_cpu = cpumask_first(&cluster->cluster_cpus);
+
+ if (irq_set_affinity(irq, cpumask_of(cluster->on_cpu))) {
+ dev_err(&pdev->dev,
+ "Unable to set irq affinity (irq=%d, cpu=%d)\n",
+ irq, cluster->on_cpu);
+ return -ENODEV;
+ }
+
+ err = devm_request_irq(&pdev->dev, irq, l2_cache__handle_irq,
+ IRQF_NOBALANCING, "l2-cache-pmu", cluster);
+ if (err) {
+ dev_err(&pdev->dev,
+ "Unable to request IRQ%d for L2 PMU counters\n", irq);
+ return err;
+ }
+
+ dev_info(&pdev->dev,
+ "Registered L2 cache PMU instance %ld with %d CPUs\n",
+ fw_cluster_id, cpumask_weight(&cluster->cluster_cpus));
+
+ cluster->pmu_lock = __SPIN_LOCK_UNLOCKED(cluster->pmu_lock);
+ cpumask_set_cpu(cluster->on_cpu, &l2cache_pmu->cpumask);
+
+ hml2_pmu__reset(cluster);
+ l2cache_pmu->num_pmus++;
+
+ return 0;
+}
+
+static int l2_cache_pmu_probe(struct platform_device *pdev)
+{
+ int err;
+ struct l2cache_pmu *l2cache_pmu;
+
+ l2cache_pmu =
+ devm_kzalloc(&pdev->dev, sizeof(*l2cache_pmu), GFP_KERNEL);
+ if (!l2cache_pmu)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, l2cache_pmu);
+ l2cache_pmu->pmu = (struct pmu) {
+ /* suffix is instance id for future use with multiple sockets */
+ .name = "l2cache_0",
+ .task_ctx_nr = perf_invalid_context,
+ .pmu_enable = l2_cache__pmu_enable,
+ .pmu_disable = l2_cache__pmu_disable,
+ .event_init = l2_cache__event_init,
+ .add = l2_cache__event_add,
+ .del = l2_cache__event_del,
+ .start = l2_cache__event_start,
+ .stop = l2_cache__event_stop,
+ .read = l2_cache__event_read,
+ .attr_groups = l2_cache_pmu_attr_grps,
+ .filter_match = l2_cache_filter_match,
+ };
+
+ l2cache_pmu->num_counters = get_num_counters();
+ l2cache_pmu->pdev = pdev;
+ l2_cycle_ctr_idx = l2cache_pmu->num_counters - 1;
+ l2_counter_present_mask = GENMASK(l2cache_pmu->num_counters - 2, 0) |
+ L2PM_CC_ENABLE;
+
+ cpumask_clear(&l2cache_pmu->cpumask);
+
+ /* Read cluster info and initialize each cluster */
+ err = device_for_each_child(&pdev->dev, l2cache_pmu,
+ l2_cache_pmu_probe_cluster);
+ if (err < 0)
+ return err;
+
+ if (l2cache_pmu->num_pmus == 0) {
+ dev_err(&pdev->dev, "No hardware L2 cache PMUs found\n");
+ return -ENODEV;
+ }
+
+ err = perf_pmu_register(&l2cache_pmu->pmu, l2cache_pmu->pmu.name, -1);
+ if (err < 0) {
+ dev_err(&pdev->dev, "Error %d registering L2 cache PMU\n", err);
+ return err;
+ }
+
+ dev_info(&pdev->dev, "Registered L2 cache PMU using %d HW PMUs\n",
+ l2cache_pmu->num_pmus);
+
+ err = cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
+ &l2cache_pmu->node);
+
+ return err;
+}
+
+static int l2_cache_pmu_remove(struct platform_device *pdev)
+{
+ struct l2cache_pmu *l2cache_pmu =
+ to_l2cache_pmu(platform_get_drvdata(pdev));
+
+ cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
+ &l2cache_pmu->node);
+ perf_pmu_unregister(&l2cache_pmu->pmu);
+ return 0;
+}
+
+static struct platform_driver l2_cache_pmu_driver = {
+ .driver = {
+ .name = "qcom-l2cache-pmu",
+ .owner = THIS_MODULE,
+ .acpi_match_table = ACPI_PTR(l2_cache_pmu_acpi_match),
+ },
+ .probe = l2_cache_pmu_probe,
+ .remove = l2_cache_pmu_remove,
+};
+
+static int __init register_l2_cache_pmu_driver(void)
+{
+ int err;
+
+ err = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
+ "AP_PERF_ARM_QCOM_L2_ONLINE",
+ l2cache_pmu_online_cpu,
+ l2cache_pmu_offline_cpu);
+ if (err)
+ return err;
+
+ return platform_driver_register(&l2_cache_pmu_driver);
+}
+device_initcall(register_l2_cache_pmu_driver);
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 45a4287..f342842 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -113,6 +113,7 @@ enum cpuhp_state {
CPUHP_AP_PERF_ARM_CCI_ONLINE,
CPUHP_AP_PERF_ARM_CCN_ONLINE,
CPUHP_AP_PERF_ARM_L2X0_ONLINE,
+ CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
CPUHP_AP_WORKQUEUE_ONLINE,
CPUHP_AP_RCUTREE_ONLINE,
CPUHP_AP_NOTIFY_ONLINE,
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.
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