* [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06
From: zhichang.yuan @ 2016-09-22 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <EE11001F9E5DDD47B7634E2F8A612F2E1F882BB3@lhreml507-mbx>
On 09/22/2016 11:20 PM, Gabriele Paoloni wrote:
>
>> -----Original Message-----
>> From: Arnd Bergmann [mailto:arnd at arndb.de]
>> Sent: 22 September 2016 15:59
>> To: Gabriele Paoloni
>> Cc: zhichang; linux-arm-kernel at lists.infradead.org;
>> devicetree at vger.kernel.org; lorenzo.pieralisi at arm.com; minyard at acm.org;
>> linux-pci at vger.kernel.org; gregkh at linuxfoundation.org; John Garry;
>> will.deacon at arm.com; linux-kernel at vger.kernel.org; Yuanzhichang;
>> Linuxarm; xuwei (O); linux-serial at vger.kernel.org;
>> benh at kernel.crashing.org; zourongrong at gmail.com; liviu.dudau at arm.com;
>> kantyzc at 163.com
>> Subject: Re: [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on
>> Hip06
>>
>> On Thursday, September 22, 2016 2:47:14 PM CEST Gabriele Paoloni wrote:
>>>>> static int of_empty_ranges_quirk(struct device_node *np)
>>>>> {
>>>>> if (IS_ENABLED(CONFIG_PPC)) {
>>>>> @@ -503,7 +512,7 @@ static int of_translate_one(struct
>> device_node
>>>> *parent, struct of_bus *bus,
>>>>> * This code is only enabled on powerpc. --gcl
>>>>> */
>>>>> ranges = of_get_property(parent, rprop, &rlen);
>>>>> - if (ranges == NULL && !of_empty_ranges_quirk(parent)) {
>>>>> + if (ranges == NULL && !of_empty_ranges_quirk(parent) &&
>>>> !of_isa_indirect_io(parent)) {
>>>>> pr_debug("OF: no ranges; cannot translate\n");
>>>>> return 1;
>>>>> }
>>>> I don't see what effect that would have. What do you want to
>>>> achieve with this?
>>> If I read the code correctly adding the function above would end
>>> up in a 1:1 mapping:
>>> http://lxr.free-electrons.com/source/drivers/of/address.c#L513
>>>
>>> so taddr will be assigned with the cpu address space specified
>>> in the children nodes of LPC and we are not using a quirk function
>>> (we are just checking that we have the indirect io assigned and
>>> that we are on a ISA bus). Now probably there is a nit in my
>>> code sketch where of_isa_indirect_io should be probably an
>> architecture
>>> specific function...
>> But the point is that it would then return an incorrect address,
>> which in the worst case could be the same as another I/O space
>> if that happens to be at CPU address zero.
> If we do not touch __of_address_to_resource after taddr is returned
> by of_translate_address we will check for (flags & IORESOURCE_IO),
> then we call pci_address_to_pio to retrieve the unique token (remember
> that LPC driver will register the LPC io range to pci io_range_list).
>
> I do not think that we can have any conflict with any other I/O space
> as pci_register_io_range will guarantee that the LPC range does not
> overlap with any other I/O range...
If we don't bypass the calling of pci_address_to_pio after
of_translate_address,
there should no conflict between LPC logical IO range and other logical
IO ranges
of other devices.
I guess Arnd want to skip all the translation for our LPC IO address.
But if we do it
like that, it seems we can't avoid the possible conflict with the
logical IO ranges of
PCI host bridges without any changes on the pci_register_io_range and
pci_address_to_pio.
Because two completely separate I/O spaces are created without
synchronization.
Best,
Zhichang
>>>> I think all we need from this function is to return '1' if
>>>> we hit an ISA I/O window, and that should happen for the two
>>>> interesting cases, either no 'ranges' at all, or no translation
>>>> for the range in question, so that __of_translate_address can
>>>> return OF_BAD_ADDR, and we can enter the special case
>>>> handling in the caller, that handles it like
>>>>
>>> I don't think this is very right as you may fail for different
>>> reasons other than a missing range property, e.g:
>>> http://lxr.free-electrons.com/source/drivers/of/address.c#L575
>>>
>>> And even if the only failure case was a missing range if in the
>>> future __of_translate_address had to be reworked we would again
>>> make a wrong assumption...you get my point?
>> The newly introduced function would clearly have to make
>> some sanity checks. The idea is that treat the case of
>> not being able to translate a bus specific I/O address
>> into a CPU address literally and fall back to another method
>> of translating that address.
>>
>> This matches my mental model of how we find the resource:
>>
>> - start with the bus address
>> - try to translate that into a CPU address
>> - if we arrive at a CPU physical address for IORESOURCE_MEM, use that
>> - if we arrive at a CPU physical address for IORESOURCE_IO, translate
>> that into a Linux IORESOURCE_IO token
>> - if there is no valid CPU physical address, try to translate
>> the address into an IORESOURCE_IO using the ISA accessor
>> - if that fails too, give up.
>>
>> If you try to fake a CPU physical address inbetween, it just
>> gets more confusing.
>>
>> Arnd
^ permalink raw reply
* [GIT PULL] iommu/arm-smmu: Updates for 4.9
From: Joerg Roedel @ 2016-09-22 15:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160920102534.GC17978@arm.com>
On Tue, Sep 20, 2016 at 11:25:34AM +0100, Will Deacon wrote:
> Hi Joerg,
>
> Please pull these significant arm-smmu updates for 4.9. The vast majority
> of the code here is Robin's series to move the drivers over to the
> generic DT bindings, which finally hooks up the DMA API and MSI mapping
> for host machines. This has been stewing for a while and is now at the
> point where I feel it's much better in mainline than languishing outside.
>
> A consequence of that is that there are some non-trivial changes outside
> of the drivers, but these are all acked by the relevant subsystem
> maintainers.
>
> Other stuff here includes some non-critical fixes to the queue handling
> on SMMUv3 and a small devm cleanup that missed the boat last time around.
>
> Cheers,
>
> Will
>
> --->8
>
> The following changes since commit 3eab887a55424fc2c27553b7bfe32330df83f7b8:
>
> Linux 4.8-rc4 (2016-08-28 15:04:33 -0700)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git for-joerg/arm-smmu/updates
Pulled, thanks Will.
^ permalink raw reply
* [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06
From: Gabriele Paoloni @ 2016-09-22 15:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1669038.JevuM4F83e@wuerfel>
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: 22 September 2016 15:59
> To: Gabriele Paoloni
> Cc: zhichang; linux-arm-kernel at lists.infradead.org;
> devicetree at vger.kernel.org; lorenzo.pieralisi at arm.com; minyard at acm.org;
> linux-pci at vger.kernel.org; gregkh at linuxfoundation.org; John Garry;
> will.deacon at arm.com; linux-kernel at vger.kernel.org; Yuanzhichang;
> Linuxarm; xuwei (O); linux-serial at vger.kernel.org;
> benh at kernel.crashing.org; zourongrong at gmail.com; liviu.dudau at arm.com;
> kantyzc at 163.com
> Subject: Re: [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on
> Hip06
>
> On Thursday, September 22, 2016 2:47:14 PM CEST Gabriele Paoloni wrote:
> > > > static int of_empty_ranges_quirk(struct device_node *np)
> > > > {
> > > > if (IS_ENABLED(CONFIG_PPC)) {
> > > > @@ -503,7 +512,7 @@ static int of_translate_one(struct
> device_node
> > > *parent, struct of_bus *bus,
> > > > * This code is only enabled on powerpc. --gcl
> > > > */
> > > > ranges = of_get_property(parent, rprop, &rlen);
> > > > - if (ranges == NULL && !of_empty_ranges_quirk(parent)) {
> > > > + if (ranges == NULL && !of_empty_ranges_quirk(parent) &&
> > > !of_isa_indirect_io(parent)) {
> > > > pr_debug("OF: no ranges; cannot translate\n");
> > > > return 1;
> > > > }
> > >
> > > I don't see what effect that would have. What do you want to
> > > achieve with this?
> >
> > If I read the code correctly adding the function above would end
> > up in a 1:1 mapping:
> > http://lxr.free-electrons.com/source/drivers/of/address.c#L513
> >
> > so taddr will be assigned with the cpu address space specified
> > in the children nodes of LPC and we are not using a quirk function
> > (we are just checking that we have the indirect io assigned and
> > that we are on a ISA bus). Now probably there is a nit in my
> > code sketch where of_isa_indirect_io should be probably an
> architecture
> > specific function...
>
> But the point is that it would then return an incorrect address,
> which in the worst case could be the same as another I/O space
> if that happens to be at CPU address zero.
If we do not touch __of_address_to_resource after taddr is returned
by of_translate_address we will check for (flags & IORESOURCE_IO),
then we call pci_address_to_pio to retrieve the unique token (remember
that LPC driver will register the LPC io range to pci io_range_list).
I do not think that we can have any conflict with any other I/O space
as pci_register_io_range will guarantee that the LPC range does not
overlap with any other I/O range...
>
> > > I think all we need from this function is to return '1' if
> > > we hit an ISA I/O window, and that should happen for the two
> > > interesting cases, either no 'ranges' at all, or no translation
> > > for the range in question, so that __of_translate_address can
> > > return OF_BAD_ADDR, and we can enter the special case
> > > handling in the caller, that handles it like
> > >
> >
> > I don't think this is very right as you may fail for different
> > reasons other than a missing range property, e.g:
> > http://lxr.free-electrons.com/source/drivers/of/address.c#L575
> >
> > And even if the only failure case was a missing range if in the
> > future __of_translate_address had to be reworked we would again
> > make a wrong assumption...you get my point?
>
> The newly introduced function would clearly have to make
> some sanity checks. The idea is that treat the case of
> not being able to translate a bus specific I/O address
> into a CPU address literally and fall back to another method
> of translating that address.
>
> This matches my mental model of how we find the resource:
>
> - start with the bus address
> - try to translate that into a CPU address
> - if we arrive at a CPU physical address for IORESOURCE_MEM, use that
> - if we arrive at a CPU physical address for IORESOURCE_IO, translate
> that into a Linux IORESOURCE_IO token
> - if there is no valid CPU physical address, try to translate
> the address into an IORESOURCE_IO using the ISA accessor
> - if that fails too, give up.
>
> If you try to fake a CPU physical address inbetween, it just
> gets more confusing.
>
> Arnd
^ permalink raw reply
* [PATCH] arm: dts: fix rk3066a based boards vdd_log voltage initialization
From: Boris Brezillon @ 2016-09-22 15:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAD=FV=W=ZiaLu1=zcnDyUqvK6f=E-0AWH9URHE3cgAKWWa+aJA@mail.gmail.com>
+Mark
I realize Mark has been out of the discussion, and what started as a DT
problem actually turned into a PWM regulator discussion.
Maybe we should start a new thread.
On Mon, 19 Sep 2016 14:15:06 -0700
Doug Anderson <dianders@chromium.org> wrote:
> Hi,
>
> On Mon, Sep 19, 2016 at 1:43 PM, Boris Brezillon
> <boris.brezillon@free-electrons.com> wrote:
> > On Mon, 19 Sep 2016 11:12:12 -0700
> > Doug Anderson <dianders@chromium.org> wrote:
> >
> >> Hi,
> >>
> >> On Mon, Sep 19, 2016 at 11:06 AM, Boris Brezillon
> >> <boris.brezillon@free-electrons.com> wrote:
> >> > On Mon, 19 Sep 2016 10:52:51 -0700
> >> > Doug Anderson <dianders@chromium.org> wrote:
> >> >
> >> >> Hi,
> >> >>
> >> >> On Mon, Sep 19, 2016 at 10:48 AM, Boris Brezillon
> >> >> <boris.brezillon@free-electrons.com> wrote:
> >> >> > The PWM chip has always claimed the pins and muxed them to the PWM IP.
> >> >> > So, this means it's broken from the beginning, and my patch is only
> >> >> > uncovering the problem (unless the pins stay configured as input until
> >> >> > the PWM is enabled, which I'm not sure is the case).
> >> >>
> >> >> Such a solution is achievable with the pinctrl APIs pretty easily.
> >> >> You might not be able to use the automatic "init" state but you can do
> >> >> something similar and switch to an "active" state once the PWM is
> >> >> actually turned on the first time.
> >> >
> >> > But is it really the case here (I don't see any code requesting a
> >> > specific pinmux depending on the PWM state)?
> >>
> >> It is not happening right now as far as I know. ...but that's a bug.
> >>
> >> > Anyway, we really need to handle this case, we should define the
> >> > typical voltage when the PWM is disabled. Same as what you suggested
> >> > with voltage-when-input, but with a different naming (since the concept
> >> > of pinmux is PWM hardware/driver specific).
> >> >
> >> > voltage-when-pwm-disabled = <...>;
> >>
> >> Voltage when disabled and voltage when input are two different states.
> >> A disabled PWM will typically either drive high or low (depending on
> >> where it was when you turned it off). Not all "disabled" states will
> >> mean that the pin is configured as an input.
> >
> > Okay, after reading again your first answer, I think I understand why
> > you want to differentiate the when-disabled and when-input cases. You
> > want to use the "init" and "default" pinctrl states. The "init" state
> > (applied at probe time) would keep the PWM pin in gpio+input mode and
> > the "default" state (applied when the PWM device is enabled for the
> > first time) would mux the pin to the PWM device.
> > Your solution requires that the pwm-regulator device knows in which
> > state the pin attached to the PWM is, which IMO is breaking the
> > layering we have right now: a PWM-regulator is assigned a PWM device
> > which is assigned a pin and a pinmux config.
> > Another solution would be to expose an additional information in the
> > pwm_state: whether the PWM is in the INIT state (probed, but not yet
> > configured by its user) or DEFAULT state (probed and already
> > configured by its user). But again, by doing that we also expose
> > internal PWM details to its user, which I'm not sure will help keep
> > the PWM API simple.
>
> One note is that probably using the "init" state would not be a good
> idea because it would make assumptions about what state the firmware
> left things. Possibly a firmware update could cause a change from a
> PWM being left as "input" to the PWM actually being initted.
> ...really we should be able to detect if the PWM was left on at
> bootup.
Yep.
>
>
> > Actually, I had something slightly different in mind. I thought about
> > having two new pinctrl states ("enabled" and "disabled"). The "enabled"
> > state (pin muxed to the PWM device) would be applied each time the PWM
> > is enabled, and "disabled" state (gpio+input mode) would be applied each
> > time the PWM is disabled.
>
> Adding "enabled" and "disabled" state is sane IMHO. At the moment the
> PWM regulator never actually puts things in "disabled" state, but I
> suppose it could in the future.
>
> > This way we can guarantee that even when the PWM is disabled, the
> > PWM-driven regulator is configured to output a non-destructive voltage.
> > Hence my suggestion to name the property 'voltage-when-pwm-disabled'.
>
> That's fine with me, as long as the PWM starts up as "enabled" if the
> pinctrl happened to be left initted by the BIOS.
Yes, that's already the case in the pwm-rockchip driver.
Okay, I can try to implement what is described above, but, in the
meantime, I think we should find a solution for Andy's initial problem.
As I said, the problem you're describing (pins muxed to the PWM device
when it should actually stay in gpio+input mode) is not new, and the old
pwm-regulator and pwm-rockchip implementation (before my atomic PWM
changes) were behaving the same way.
What is new though, is the pwm_regulator_init_state() function [1], and
it seems it's now preventing the probe of a pwm-regulator device if the
initial PWM state is not described in the voltage-table.
The question is, what should we do?
1/ Force users to put an entry matching this state (which means
breaking DT compat)
2/ Put a valid value in drvdata->state even if it's not reflecting the
real state
3/ Patch regulator core to support an "unknown-selector" return code.
Mark, any opinion?
Thanks,
Boris
[1]https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/drivers/regulator/pwm-regulator.c?id=refs/tags/next-20160922#n60
^ permalink raw reply
* [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06
From: Arnd Bergmann @ 2016-09-22 14:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <EE11001F9E5DDD47B7634E2F8A612F2E1F882AD3@lhreml507-mbx>
On Thursday, September 22, 2016 2:47:14 PM CEST Gabriele Paoloni wrote:
> > > static int of_empty_ranges_quirk(struct device_node *np)
> > > {
> > > if (IS_ENABLED(CONFIG_PPC)) {
> > > @@ -503,7 +512,7 @@ static int of_translate_one(struct device_node
> > *parent, struct of_bus *bus,
> > > * This code is only enabled on powerpc. --gcl
> > > */
> > > ranges = of_get_property(parent, rprop, &rlen);
> > > - if (ranges == NULL && !of_empty_ranges_quirk(parent)) {
> > > + if (ranges == NULL && !of_empty_ranges_quirk(parent) &&
> > !of_isa_indirect_io(parent)) {
> > > pr_debug("OF: no ranges; cannot translate\n");
> > > return 1;
> > > }
> >
> > I don't see what effect that would have. What do you want to
> > achieve with this?
>
> If I read the code correctly adding the function above would end
> up in a 1:1 mapping:
> http://lxr.free-electrons.com/source/drivers/of/address.c#L513
>
> so taddr will be assigned with the cpu address space specified
> in the children nodes of LPC and we are not using a quirk function
> (we are just checking that we have the indirect io assigned and
> that we are on a ISA bus). Now probably there is a nit in my
> code sketch where of_isa_indirect_io should be probably an architecture
> specific function...
But the point is that it would then return an incorrect address,
which in the worst case could be the same as another I/O space
if that happens to be at CPU address zero.
> > I think all we need from this function is to return '1' if
> > we hit an ISA I/O window, and that should happen for the two
> > interesting cases, either no 'ranges' at all, or no translation
> > for the range in question, so that __of_translate_address can
> > return OF_BAD_ADDR, and we can enter the special case
> > handling in the caller, that handles it like
> >
>
> I don't think this is very right as you may fail for different
> reasons other than a missing range property, e.g:
> http://lxr.free-electrons.com/source/drivers/of/address.c#L575
>
> And even if the only failure case was a missing range if in the
> future __of_translate_address had to be reworked we would again
> make a wrong assumption...you get my point?
The newly introduced function would clearly have to make
some sanity checks. The idea is that treat the case of
not being able to translate a bus specific I/O address
into a CPU address literally and fall back to another method
of translating that address.
This matches my mental model of how we find the resource:
- start with the bus address
- try to translate that into a CPU address
- if we arrive at a CPU physical address for IORESOURCE_MEM, use that
- if we arrive at a CPU physical address for IORESOURCE_IO, translate
that into a Linux IORESOURCE_IO token
- if there is no valid CPU physical address, try to translate
the address into an IORESOURCE_IO using the ISA accessor
- if that fails too, give up.
If you try to fake a CPU physical address inbetween, it just
gets more confusing.
Arnd
^ permalink raw reply
* [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06
From: Gabriele Paoloni @ 2016-09-22 14:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9178320.n4yHmfyPA3@wuerfel>
Hi Arnd
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: 22 September 2016 13:15
> To: Gabriele Paoloni
> Cc: zhichang; linux-arm-kernel at lists.infradead.org;
> devicetree at vger.kernel.org; lorenzo.pieralisi at arm.com; minyard at acm.org;
> linux-pci at vger.kernel.org; gregkh at linuxfoundation.org; John Garry;
> will.deacon at arm.com; linux-kernel at vger.kernel.org; Yuanzhichang;
> Linuxarm; xuwei (O); linux-serial at vger.kernel.org;
> benh at kernel.crashing.org; zourongrong at gmail.com; liviu.dudau at arm.com;
> kantyzc at 163.com
> Subject: Re: [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on
> Hip06
>
> On Thursday, September 22, 2016 11:55:45 AM CEST Gabriele Paoloni
> wrote:
> > > > I think extending of_empty_ranges_quirk() may be a reasonable
> > > solution.
> > > > What do you think Arnd?
> > >
> > > I don't really like that idea, that quirk is meant to work around
> > > broken DTs, but we can just make the DT valid and implement the
> > > code properly.
> >
> > Ok I understand your point where it is not right to use
> of_empty_ranges_quirk()
> > As a quirk is used to work around broken HW or broken FW (as in this
> case)
> > rather than to fix code
> >
> > What about the following? I think adding the check you suggested next
> to
> > of_empty_ranges_quirk() is adding the case we need in the right point
> (thus
> > avoiding any duplication)
> >
> > --- a/drivers/of/address.c
> > +++ b/drivers/of/address.c
> > @@ -457,6 +457,15 @@ static struct of_bus *of_match_bus(struct
> device_node *np)
> > return NULL;
> > }
> >
> > +static inline int of_isa_indirect_io(struct device_node *np)
> > +{
> > + /*
> > + * check if the current node is an isa bus and if indirectio
> operation
> > + * are registered
> > + */
> > + return (of_bus_isa_match(np) && arm64_extio_ops);
> > +}
> > +
> > static int of_empty_ranges_quirk(struct device_node *np)
> > {
> > if (IS_ENABLED(CONFIG_PPC)) {
> > @@ -503,7 +512,7 @@ static int of_translate_one(struct device_node
> *parent, struct of_bus *bus,
> > * This code is only enabled on powerpc. --gcl
> > */
> > ranges = of_get_property(parent, rprop, &rlen);
> > - if (ranges == NULL && !of_empty_ranges_quirk(parent)) {
> > + if (ranges == NULL && !of_empty_ranges_quirk(parent) &&
> !of_isa_indirect_io(parent)) {
> > pr_debug("OF: no ranges; cannot translate\n");
> > return 1;
> > }
>
> I don't see what effect that would have. What do you want to
> achieve with this?
If I read the code correctly adding the function above would end
up in a 1:1 mapping:
http://lxr.free-electrons.com/source/drivers/of/address.c#L513
so taddr will be assigned with the cpu address space specified
in the children nodes of LPC and we are not using a quirk function
(we are just checking that we have the indirect io assigned and
that we are on a ISA bus). Now probably there is a nit in my
code sketch where of_isa_indirect_io should be probably an architecture
specific function...
>
> I think all we need from this function is to return '1' if
> we hit an ISA I/O window, and that should happen for the two
> interesting cases, either no 'ranges' at all, or no translation
> for the range in question, so that __of_translate_address can
> return OF_BAD_ADDR, and we can enter the special case
> handling in the caller, that handles it like
>
I don't think this is very right as you may fail for different
reasons other than a missing range property, e.g:
http://lxr.free-electrons.com/source/drivers/of/address.c#L575
And even if the only failure case was a missing range if in the
future __of_translate_address had to be reworked we would again
make a wrong assumption...you get my point?
Thanks
Gab
> diff --git a/drivers/of/address.c b/drivers/of/address.c
> index 02b2903fe9d2..a18d96843fae 100644
> --- a/drivers/of/address.c
> +++ b/drivers/of/address.c
> @@ -685,17 +685,24 @@ static int __of_address_to_resource(struct
> device_node *dev,
> if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
> return -EINVAL;
> taddr = of_translate_address(dev, addrp);
> - if (taddr == OF_BAD_ADDR)
> - return -EINVAL;
> memset(r, 0, sizeof(struct resource));
> +
> if (flags & IORESOURCE_IO) {
> unsigned long port;
> - port = pci_address_to_pio(taddr);
> +
> + if (taddr == OF_BAD_ADDR)
> + port = arch_of_address_to_pio(dev, addrp)
> + else
> + port = pci_address_to_pio(taddr);
> +
> if (port == (unsigned long)-1)
> return -EINVAL;
> r->start = port;
> r->end = port + size - 1;
> } else {
> + if (taddr == OF_BAD_ADDR)
> + return -EINVAL;
> +
> r->start = taddr;
> r->end = taddr + size - 1;
> }
>
>
>
> Arnd
^ permalink raw reply
* [PATCH] clocksource: timer-digicolor: Unmap region obtained by of_iomap
From: Baruch Siach @ 2016-09-22 14:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474554073-8658-1-git-send-email-arvind.yadav.cs@gmail.com>
Hi Arvind Yadav,
On Thu, Sep 22, 2016 at 07:51:13PM +0530, Arvind Yadav wrote:
> Free memory mapping, if digicolor_timer_init is not successful.
Thanks for looking into that.
Why not add a devm_of_iomap() variant of of_iomap() that calls devm_ioremap()
instead of ioremap()?
I'm not sure that cleaning up after a clocksource driver init failure makes
much sense. Something is clearly fundamentally wrong in your device tree, and
your system will most likely not boot anyway.
baruch
> Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
> ---
> drivers/clocksource/timer-digicolor.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clocksource/timer-digicolor.c b/drivers/clocksource/timer-digicolor.c
> index 10318cc..e6e5e6a 100644
> --- a/drivers/clocksource/timer-digicolor.c
> +++ b/drivers/clocksource/timer-digicolor.c
> @@ -167,12 +167,14 @@ static int __init digicolor_timer_init(struct device_node *node)
> irq = irq_of_parse_and_map(node, dc_timer_dev.timer_id);
> if (irq <= 0) {
> pr_err("Can't parse IRQ");
> + iounmap(dc_timer_dev.base);
> return -EINVAL;
> }
>
> clk = of_clk_get(node, 0);
> if (IS_ERR(clk)) {
> pr_err("Can't get timer clock");
> + iounmap(dc_timer_dev.base);
> return PTR_ERR(clk);
> }
> clk_prepare_enable(clk);
> @@ -192,6 +194,7 @@ static int __init digicolor_timer_init(struct device_node *node)
> &dc_timer_dev.ce);
> if (ret) {
> pr_warn("request of timer irq %d failed (%d)\n", irq, ret);
> + iounmap(dc_timer_dev.base);
> return ret;
> }
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
^ permalink raw reply
* [PATCH v2 2/3] musb: sunxi: Remove custom babble handling
From: Bin Liu @ 2016-09-22 14:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <39199bd7-a372-0312-6177-5b0fc2d683ac@redhat.com>
Hi,
On Thu, Sep 22, 2016 at 05:03:39PM +0300, Hans de Goede wrote:
> Hi,
>
> On 09/22/2016 04:54 PM, Bin Liu wrote:
> >Hi,
> >
> >On Thu, Sep 22, 2016 at 02:19:00PM +0300, Hans de Goede wrote:
> >>The musb-core now a days always treats babble errors in host mode
> >
> >I don't think this statement is accurate. You might want to change it to
> >"The musb core already handles babble interrupt" or something else.
>
> It is accurate if you look in the history at drivers/usb/musb
> commits around 15-03-10 you will see 2 relevant commits:
>
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drivers/usb/musb?id=b4dc38fd45b63e3da2bc98db5d283a15a637a2fa
>
> "usb: musb: core: simplify musb_recover_work()"
>
> This commits introduces calling musb_root_disconnect(musb)
> on babble errors, that was not happening before which is why
That is true, but calling musb_root_disconnect() is just one step of the
recovery in musb core, not all.
The statement of "treats babble errors in host mode as disconnects"
implies all the babble handling is just disconnect, which is not
accurate.
BTY, "babble errors in host mode" is also redundant. babble implies
host mode.
Regards,
-Bin.
> I added the custom babble error handling. to the sunxi glue.
>
> And:
>
> "usb: musb: core: always try to recover from babble"
>
> Where the title says it all.
>
> Take these together and I believe that my commit msg:
>
> "The musb-core now a days always treats babble errors in host mode
> as disconnects, so there is no need for the sunxi specific handling
> of this anymore."
>
> Is quite accurate.
>
> Regards,
>
> Hans
>
>
> >>
> >>Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> >>---
> >>Changes in v2:
> >>-This is a new patch in v2 of this patch series
> >>---
> >> drivers/usb/musb/sunxi.c | 10 ----------
> >> 1 file changed, 10 deletions(-)
> >>
> >>diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
> >>index 1408245..82eba92 100644
> >>--- a/drivers/usb/musb/sunxi.c
> >>+++ b/drivers/usb/musb/sunxi.c
> >>@@ -186,16 +186,6 @@ static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
> >> if (musb->int_usb)
> >> writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
> >>
> >>- /*
> >>- * sunxi musb often signals babble on low / full speed device
> >>- * disconnect, without ever raising MUSB_INTR_DISCONNECT, since
> >>- * normally babble never happens treat it as disconnect.
> >>- */
> >>- if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) {
> >>- musb->int_usb &= ~MUSB_INTR_BABBLE;
> >>- musb->int_usb |= MUSB_INTR_DISCONNECT;
> >>- }
> >>-
> >> if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
> >> /* ep0 FADDR must be 0 when (re)entering peripheral mode */
> >> musb_ep_select(musb->mregs, 0);
> >>--
> >>2.9.3
> >>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] clocksource/drivers/ti-32k: Prevent ftrace recursion
From: Steven Rostedt @ 2016-09-22 14:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.20.1609221555590.5599@nanos>
On Thu, 22 Sep 2016 15:58:03 +0200 (CEST)
Thomas Gleixner <tglx@linutronix.de> wrote:
> On Thu, 22 Sep 2016, Jisheng Zhang wrote:
>
> > Currently ti-32k can be used as a scheduler clock. We properly marked
> > omap_32k_read_sched_clock() as notrace but we then call another
> > function ti_32k_read_cycles() that _wasn't_ notrace.
> >
> > Having a traceable function in the sched_clock() path leads to a
> > recursion within ftrace and a kernel crash.
>
> Kernel crash? Doesn't ftrace core prevent recursion?
>
There is recursion protection, but there are some holes, as well as
calls where ftrace can't protect itself.
What triggered the bug? Just simple enabling of function tracing? And
what arch? I would like to close these holes. Although, I should add
some kind of flag to notify the user (or at least for me) that recursion
is happening, because that can really be a performance hit on tracing.
-- Steve
^ permalink raw reply
* [PATCH] clocksource: timer-digicolor: Unmap region obtained by of_iomap
From: Arvind Yadav @ 2016-09-22 14:21 UTC (permalink / raw)
To: linux-arm-kernel
Free memory mapping, if digicolor_timer_init is not successful.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
---
drivers/clocksource/timer-digicolor.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clocksource/timer-digicolor.c b/drivers/clocksource/timer-digicolor.c
index 10318cc..e6e5e6a 100644
--- a/drivers/clocksource/timer-digicolor.c
+++ b/drivers/clocksource/timer-digicolor.c
@@ -167,12 +167,14 @@ static int __init digicolor_timer_init(struct device_node *node)
irq = irq_of_parse_and_map(node, dc_timer_dev.timer_id);
if (irq <= 0) {
pr_err("Can't parse IRQ");
+ iounmap(dc_timer_dev.base);
return -EINVAL;
}
clk = of_clk_get(node, 0);
if (IS_ERR(clk)) {
pr_err("Can't get timer clock");
+ iounmap(dc_timer_dev.base);
return PTR_ERR(clk);
}
clk_prepare_enable(clk);
@@ -192,6 +194,7 @@ static int __init digicolor_timer_init(struct device_node *node)
&dc_timer_dev.ce);
if (ret) {
pr_warn("request of timer irq %d failed (%d)\n", irq, ret);
+ iounmap(dc_timer_dev.base);
return ret;
}
--
2.7.4
^ permalink raw reply related
* [PATCH V6 3/5] PCI: thunder-pem: Allow to probe PEM-specific register range for ACPI case
From: Christopher Covington @ 2016-09-22 14:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922094955.GB18637@red-moon>
On 09/22/2016 05:49 AM, Lorenzo Pieralisi wrote:
> On Wed, Sep 21, 2016 at 01:04:57PM -0500, Bjorn Helgaas wrote:
>> On Wed, Sep 21, 2016 at 03:05:49PM +0100, Lorenzo Pieralisi wrote:
>>> On Tue, Sep 20, 2016 at 02:17:44PM -0500, Bjorn Helgaas wrote:
>>>> On Tue, Sep 20, 2016 at 04:09:25PM +0100, Ard Biesheuvel wrote:
>>>
>>> [...]
>>>
>>>>> None of these platforms can be fixed entirely in software, and given
>>>>> that we will not be adding quirks for new broken hardware, we should
>>>>> ask ourselves whether having two versions of a quirk, i.e., one for
>>>>> broken hardware + currently shipping firmware, and one for the same
>>>>> broken hardware with fixed firmware is really an improvement over what
>>>>> has been proposed here.
>>>>
>>>> We're talking about two completely different types of quirks:
>>>>
>>>> 1) MCFG quirks to use memory-mapped config space that doesn't quite
>>>> conform to the ECAM model in the PCIe spec, and
>>>>
>>>> 2) Some yet-to-be-determined method to describe address space
>>>> consumed by a bridge.
>>>>
>>>> The first two patches of this series are a nice implementation for 1).
>>>> The third patch (ThunderX-specific) is one possibility for 2), but I
>>>> don't like it because there's no way for generic software like the
>>>> ACPI core to discover these resources.
>>>
>>> Ok, so basically this means that to implement (2) we need to assign
>>> some sort of _HID to these quirky PCI bridges (so that we know what
>>> device they represent and we can retrieve their _CRS). I take from
>>> this discussion that the goal is to make sure that all non-config
>>> resources have to be declared through _CRS device objects, which is
>>> fine but that requires a FW update (unless we can fabricate ACPI
>>> devices and corresponding _CRS in the kernel whenever we match a
>>> given MCFG table signature).
>>
>> All resources consumed by ACPI devices should be declared through
>> _CRS. If you want to fabricate ACPI devices or _CRS via kernel
>> quirks, that's fine with me. This could be triggered via MCFG
>> signature, DMI info, host bridge _HID, etc.
>
> I think the PNP quirk approach + PNP0c02 resource put forward by Gab
> is enough.
>
>>> We discussed this already and I think we should make a decision:
>>>
>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-March/414722.html
>>>
>>>>>> I'd like to step back and come up with some understanding of how
>>>>>> non-broken firmware *should* deal with this issue. Then, if we *do*
>>>>>> work around this particular broken firmware in the kernel, it would be
>>>>>> nice to do it in a way that fits in with that understanding.
>>>>>>
>>>>>> For example, if a companion ACPI device is the preferred solution, an
>>>>>> ACPI quirk could fabricate a device with the required resources. That
>>>>>> would address the problem closer to the source and make it more likely
>>>>>> that the rest of the system will work correctly: /proc/iomem could
>>>>>> make sense, things that look at _CRS generically would work (e.g,
>>>>>> /sys/, an admittedly hypothetical "lsacpi", etc.)
>>>>>>
>>>>>> Hard-coding stuff in drivers is a point solution that doesn't provide
>>>>>> any guidance for future platforms and makes it likely that the hack
>>>>>> will get copied into even more drivers.
>>>>>>
>>>>>
>>>>> OK, I see. But the guidance for future platforms should be 'do not
>>>>> rely on quirks', and what I am arguing here is that the more we polish
>>>>> up this code and make it clean and reusable, the more likely it is
>>>>> that will end up getting abused by new broken hardware that we set out
>>>>> to reject entirely in the first place.
>>>>>
>>>>> So of course, if the quirk involves claiming resources, let's make
>>>>> sure that this occurs in the cleanest and most compliant way possible.
>>>>> But any factoring/reuse concerns other than for the current crop of
>>>>> broken hardware should be avoided imo.
>>>>
>>>> If future hardware is completely ECAM-compliant and we don't need any
>>>> more MCFG quirks, that would be great.
>>>
>>> Yes.
>>>
>>>> But we'll still need to describe that memory-mapped config space
>>>> somewhere. If that's done with PNP0C02 or similar devices (as is done
>>>> on my x86 laptop), we'd be all set.
>>>
>>> I am not sure I understand what you mean here. Are you referring
>>> to MCFG regions reported as PNP0c02 resources through its _CRS ?
>>
>> Yes. PCI Firmware Spec r3.0, Table 4-2, note 2 says address ranges
>> reported via MCFG or _CBA should be reserved by _CRS of a PNP0C02
>> device.
>
> Ok, that's agreed. It goes without saying that since you are quoting
> the PCI spec, if FW fails to report MCFG regions in a PNP0c02 device
> _CRS I will consider that a FW bug.
>
>>> IIUC PNP0C02 is a reservation mechanism, but it does not help us
>>> associate its _CRS to a specific PCI host bridge instance, right ?
>>
>> Gab proposed a hierarchy that *would* associate a PNP0C02 device with
>> a PCI bridge:
>>
>> Device (PCI1) {
>> Name (_HID, "HISI0080") // PCI Express Root Bridge
>> Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
>> Method (_CRS, 0, Serialized) { // Root complex resources (windows) }
>> Device (RES0) {
>> Name (_HID, "HISI0081") // HiSi PCIe RC config base address
>> Name (_CID, "PNP0C02") // Motherboard reserved resource
>> Name (_CRS, ResourceTemplate () { ... }
>> }
>> }
>>
>> That's a possibility. The PCI Firmware Spec suggests putting RES0 at
>> the root (under \_SB), but I don't know why.
>>
>> Putting it at the root means we couldn't generically associate it with
>> a bridge, although I could imagine something like this:
>>
>> Device (RES1) {
>> Name (_HID, "HISI0081") // HiSi PCIe RC config base address
>> Name (_CID, "PNP0C02") // Motherboard reserved resource
>> Name (_CRS, ResourceTemplate () { ... }
>> Method (BRDG) { "PCI1" } // hand-wavy ASL
>> }
>> Device (PCI1) {
>> Name (_HID, "HISI0080") // PCI Express Root Bridge
>> Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
>> Method (_CRS, 0, Serialized) { // Root complex resources (windows) }
>> }
>>
>> Where you could search PNP0C02 devices for a cookie that matched the
>> host bridge.o
>
> Ok, I am fine with both and I think we are converging, but the way
> to solve this problem has to be uniform for all ARM partners (and
> not only ARM). Two points here:
>
> 1) Adding a device/subdevice allows people to add a _CRS reporting the
> non-window bridge resources. Fine. It also allows people to chuck in
> there all sorts of _DSD properties to describe their PCI host bridge
> as it is done with DT properties (those _DSD can contain eg clocks
> etc.), this may be tempting (so that they can reuse the same DT
> driver and do not have to update their firmware) but I want to be
> clear here: that must not happen. So, a subdevice with a _CRS to
> report resources, yes, but it will stop there.
> 2) It is unclear to me how to formalize the above. People should not
> write FW by reading the PCI mailing list, so these guidelines have to
> be written, somehow. I do not want to standardize quirks, I want
> to prevent random ACPI table content, which is different.
> Should I report this to the ACPI spec working group ? If we do
> not do that everyone will go solve this problem as they deem fit.
Could you add some checks to fwts?
Cov
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code
Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH v2 2/3] musb: sunxi: Remove custom babble handling
From: Hans de Goede @ 2016-09-22 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922135415.GB31827@uda0271908>
Hi,
On 09/22/2016 04:54 PM, Bin Liu wrote:
> Hi,
>
> On Thu, Sep 22, 2016 at 02:19:00PM +0300, Hans de Goede wrote:
>> The musb-core now a days always treats babble errors in host mode
>
> I don't think this statement is accurate. You might want to change it to
> "The musb core already handles babble interrupt" or something else.
It is accurate if you look in the history at drivers/usb/musb
commits around 15-03-10 you will see 2 relevant commits:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drivers/usb/musb?id=b4dc38fd45b63e3da2bc98db5d283a15a637a2fa
"usb: musb: core: simplify musb_recover_work()"
This commits introduces calling musb_root_disconnect(musb)
on babble errors, that was not happening before which is why
I added the custom babble error handling. to the sunxi glue.
And:
"usb: musb: core: always try to recover from babble"
Where the title says it all.
Take these together and I believe that my commit msg:
"The musb-core now a days always treats babble errors in host mode
as disconnects, so there is no need for the sunxi specific handling
of this anymore."
Is quite accurate.
Regards,
Hans
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> Changes in v2:
>> -This is a new patch in v2 of this patch series
>> ---
>> drivers/usb/musb/sunxi.c | 10 ----------
>> 1 file changed, 10 deletions(-)
>>
>> diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
>> index 1408245..82eba92 100644
>> --- a/drivers/usb/musb/sunxi.c
>> +++ b/drivers/usb/musb/sunxi.c
>> @@ -186,16 +186,6 @@ static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
>> if (musb->int_usb)
>> writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
>>
>> - /*
>> - * sunxi musb often signals babble on low / full speed device
>> - * disconnect, without ever raising MUSB_INTR_DISCONNECT, since
>> - * normally babble never happens treat it as disconnect.
>> - */
>> - if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) {
>> - musb->int_usb &= ~MUSB_INTR_BABBLE;
>> - musb->int_usb |= MUSB_INTR_DISCONNECT;
>> - }
>> -
>> if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
>> /* ep0 FADDR must be 0 when (re)entering peripheral mode */
>> musb_ep_select(musb->mregs, 0);
>> --
>> 2.9.3
>>
^ permalink raw reply
* [PATCH v6 1/7] arm/arm64: vgic-new: Implement support for userspace access
From: Vijay Kilari @ 2016-09-22 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57E3C9D8.7070906@arm.com>
On Thu, Sep 22, 2016 at 5:38 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On 20/09/16 07:12, vijay.kilari at gmail.com wrote:
>> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>>
>> Read and write of some registers like ISPENDR and ICPENDR
>> from userspace requires special handling when compared to
>> guest access for these registers.
>>
>> Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
>> for handling of ISPENDR, ICPENDR registers handling.
>>
>> Add infrastructure to support guest and userspace read
>> and write for the required registers
>> Also moved vgic_uaccess from vgic-mmio-v2.c to vgic-mmio.c
>>
>> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>> ---
>> virt/kvm/arm/vgic/vgic-mmio-v2.c | 25 ----------
>> virt/kvm/arm/vgic/vgic-mmio-v3.c | 98 ++++++++++++++++++++++++++++++++--------
>> virt/kvm/arm/vgic/vgic-mmio.c | 78 ++++++++++++++++++++++++++++----
>> virt/kvm/arm/vgic/vgic-mmio.h | 19 ++++++++
>> 4 files changed, 169 insertions(+), 51 deletions(-)
>>
>> diff --git a/virt/kvm/arm/vgic/vgic-mmio-v2.c b/virt/kvm/arm/vgic/vgic-mmio-v2.c
>> index b44b359..0b32f40 100644
>> --- a/virt/kvm/arm/vgic/vgic-mmio-v2.c
>> +++ b/virt/kvm/arm/vgic/vgic-mmio-v2.c
>> @@ -406,31 +406,6 @@ int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
>> return -ENXIO;
>> }
>>
>> -/*
>> - * When userland tries to access the VGIC register handlers, we need to
>> - * create a usable struct vgic_io_device to be passed to the handlers and we
>> - * have to set up a buffer similar to what would have happened if a guest MMIO
>> - * access occurred, including doing endian conversions on BE systems.
>> - */
>> -static int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
>> - bool is_write, int offset, u32 *val)
>> -{
>> - unsigned int len = 4;
>> - u8 buf[4];
>> - int ret;
>> -
>> - if (is_write) {
>> - vgic_data_host_to_mmio_bus(buf, len, *val);
>> - ret = kvm_io_gic_ops.write(vcpu, &dev->dev, offset, len, buf);
>> - } else {
>> - ret = kvm_io_gic_ops.read(vcpu, &dev->dev, offset, len, buf);
>> - if (!ret)
>> - *val = vgic_data_mmio_bus_to_host(buf, len);
>> - }
>> -
>> - return ret;
>> -}
>> -
>> int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
>> int offset, u32 *val)
>> {
>> diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c
>> index 0d3c76a..ce2708d 100644
>> --- a/virt/kvm/arm/vgic/vgic-mmio-v3.c
>> +++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c
>> @@ -209,6 +209,62 @@ static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
>> return 0;
>> }
>>
>> +static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
>> + gpa_t addr, unsigned int len)
>> +{
>> + u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
>> + u32 value = 0;
>> + int i;
>> +
>> + /*
>> + * A level triggerred interrupt pending state is latched in both
>> + * "soft_pending" and "line_level" variables. Userspace will save
>> + * and restore soft_pending and line_level separately.
>> + * Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
>> + * handling of ISPENDR and ICPENDR.
>> + */
>> + for (i = 0; i < len * 8; i++) {
>> + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
>> +
>> + if (irq->config == VGIC_CONFIG_LEVEL && irq->soft_pending)
>> + value |= (1U << i);
>> + if (irq->config == VGIC_CONFIG_EDGE && irq->pending)
>> + value |= (1U << i);
>> +
>> + vgic_put_irq(vcpu->kvm, irq);
>> + }
>> +
>> + return value;
>> +}
>> +
>> +static void vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
>> + gpa_t addr, unsigned int len,
>> + unsigned long val)
>> +{
>> + u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
>> + int i;
>> +
>> + for (i = 0; i < len * 8; i++) {
>> + struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
>> +
>> + spin_lock(&irq->irq_lock);
>> + if (test_bit(i, &val)) {
>> + irq->pending = true;
>> + irq->soft_pending = true;
>> + vgic_queue_irq_unlock(vcpu->kvm, irq);
>> + } else {
>> + irq->soft_pending = false;
>> + if (irq->config == VGIC_CONFIG_EDGE ||
>> + (irq->config == VGIC_CONFIG_LEVEL &&
>> + !irq->line_level))
>> + irq->pending = false;
>> + spin_unlock(&irq->irq_lock);
>> + }
>> +
>> + vgic_put_irq(vcpu->kvm, irq);
>> + }
>> +}
>> +
>> /* We want to avoid outer shareable. */
>> u64 vgic_sanitise_shareability(u64 field)
>> {
>> @@ -358,7 +414,7 @@ static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
>> * We take some special care here to fix the calculation of the register
>> * offset.
>> */
>> -#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc) \
>> +#define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
>> { \
>> .reg_offset = off, \
>> .bits_per_irq = bpi, \
>> @@ -373,6 +429,8 @@ static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
>> .access_flags = acc, \
>> .read = rd, \
>> .write = wr, \
>> + .uaccess_read = ur, \
>> + .uaccess_write = uw, \
>> }
>>
>> static const struct vgic_register_region vgic_v3_dist_registers[] = {
>> @@ -380,40 +438,42 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = {
>> vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
>> - vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
>> + vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
>> - vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
>> + vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
>> - vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
>> + vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
>> - vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
>> + vgic_mmio_read_pending, vgic_mmio_write_spending,
>> + vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
>> - vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
>> + vgic_mmio_read_pending, vgic_mmio_write_cpending,
>> + vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
>> - vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
>> + vgic_mmio_read_active, vgic_mmio_write_sactive, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
>> - vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
>> + vgic_mmio_read_active, vgic_mmio_write_cactive, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
>> - vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
>> - VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
>> + vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
>> + 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
>> - vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
>> + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
>> VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
>> - vgic_mmio_read_config, vgic_mmio_write_config, 2,
>> + vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
>> - vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
>> + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
>> - vgic_mmio_read_irouter, vgic_mmio_write_irouter, 64,
>> + vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
>> VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
>> vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
>> @@ -451,11 +511,13 @@ static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
>> REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
>> vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
>> VGIC_ACCESS_32bit),
>> - REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
>> - vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
>> + REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0,
>> + vgic_mmio_read_pending, vgic_mmio_write_spending,
>> + vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
>> VGIC_ACCESS_32bit),
>> - REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
>> - vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
>> + REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0,
>> + vgic_mmio_read_pending, vgic_mmio_write_cpending,
>> + vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
>> VGIC_ACCESS_32bit),
>> REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
>> vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
>> diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
>> index e18b30d..31f85df 100644
>> --- a/virt/kvm/arm/vgic/vgic-mmio.c
>> +++ b/virt/kvm/arm/vgic/vgic-mmio.c
>> @@ -468,6 +468,73 @@ static bool check_region(const struct vgic_register_region *region,
>> return false;
>> }
>>
>> +static const struct vgic_register_region *
>> +vgic_get_mmio_region(struct vgic_io_device *iodev, gpa_t addr, int len)
>> +{
>> + const struct vgic_register_region *region;
>> +
>> + region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
>> + addr - iodev->base_addr);
>> + if (!region || !check_region(region, addr, len))
>> + return NULL;
>> +
>> + return region;
>> +}
>> +
>> +static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
>> + gpa_t addr, u32 *val)
>> +{
>> + struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
>> + const struct vgic_register_region *region;
>> + struct kvm_vcpu *r_vcpu;
>> +
>> + region = vgic_get_mmio_region(iodev, addr, sizeof(u32));
>> + if (!region) {
>> + *val = 0;
>> + return 0;
>
> This is not the previous semantic of vgic_uaccess, and I cannot see why
> blindly ignoring an access to an undefined region would be acceptable.
> What am I missing?
AFAIK, the vgic_uaccess is not making any check on undefined region/register.
However, dispatch_mmio_read/write are returning 0 if check of region is failed
>
>> + }
>> +
>> + r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
>> + if (region->uaccess_read)
>> + *val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
>> + else
>> + *val = region->read(r_vcpu, addr, sizeof(u32));
>> +
>> + return 0;
>> +}
>> +
>> +static int vgic_uaccess_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
>> + gpa_t addr, const u32 *val)
>> +{
>> + struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
>> + const struct vgic_register_region *region;
>> + struct kvm_vcpu *r_vcpu;
>> +
>> + region = vgic_get_mmio_region(iodev, addr, sizeof(u32));
>> + if (!region)
>> + return 0;
>
> Same here.
[...]
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH] clocksource/drivers/ti-32k: Prevent ftrace recursion
From: Thomas Gleixner @ 2016-09-22 13:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922075621.3725-1-jszhang@marvell.com>
On Thu, 22 Sep 2016, Jisheng Zhang wrote:
> Currently ti-32k can be used as a scheduler clock. We properly marked
> omap_32k_read_sched_clock() as notrace but we then call another
> function ti_32k_read_cycles() that _wasn't_ notrace.
>
> Having a traceable function in the sched_clock() path leads to a
> recursion within ftrace and a kernel crash.
Kernel crash? Doesn't ftrace core prevent recursion?
Thanks,
tglx
^ permalink raw reply
* [PATCH v2 2/3] musb: sunxi: Remove custom babble handling
From: Bin Liu @ 2016-09-22 13:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922111901.15337-2-hdegoede@redhat.com>
Hi,
On Thu, Sep 22, 2016 at 02:19:00PM +0300, Hans de Goede wrote:
> The musb-core now a days always treats babble errors in host mode
I don't think this statement is accurate. You might want to change it to
"The musb core already handles babble interrupt" or something else.
Regards,
-Bin.
> as disconnects, so there is no need for the sunxi specific handling
> of this anymore.
>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> Changes in v2:
> -This is a new patch in v2 of this patch series
> ---
> drivers/usb/musb/sunxi.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
> index 1408245..82eba92 100644
> --- a/drivers/usb/musb/sunxi.c
> +++ b/drivers/usb/musb/sunxi.c
> @@ -186,16 +186,6 @@ static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
> if (musb->int_usb)
> writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
>
> - /*
> - * sunxi musb often signals babble on low / full speed device
> - * disconnect, without ever raising MUSB_INTR_DISCONNECT, since
> - * normally babble never happens treat it as disconnect.
> - */
> - if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) {
> - musb->int_usb &= ~MUSB_INTR_BABBLE;
> - musb->int_usb |= MUSB_INTR_DISCONNECT;
> - }
> -
> if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
> /* ep0 FADDR must be 0 when (re)entering peripheral mode */
> musb_ep_select(musb->mregs, 0);
> --
> 2.9.3
>
^ permalink raw reply
* [PATCH] ASoC: rk3399_gru_sound: fix recording pop at first attempt
From: Xing Zheng @ 2016-09-22 13:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160919144404.GA18734@leverpostej>
Hi Mark,
On 2016?09?19? 22:44, Mark Rutland wrote:
> On Mon, Sep 19, 2016 at 10:29:39PM +0800, Xing Zheng wrote:
>> From: Wonjoon Lee <woojoo.lee@samsung.com>
>>
>> Pop happens when mclk applied but dmic's own boot-time
>> Specify dmic delay times in dt to make sure
>> clocks are ready earlier than dmic working
>>
>> Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
>> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
>> ---
>>
>> .../bindings/sound/rockchip,rk3399-gru-sound.txt | 6 ++++++
>> sound/soc/rockchip/rk3399_gru_sound.c | 14 ++++++++++++++
>> 2 files changed, 20 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
>> index f19b6c8..b7dd3ab 100644
>> --- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
>> +++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
>> @@ -6,6 +6,12 @@ Required properties:
>> connected to the codecs
>> - rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
>>
>> +Optional properties:
>> +- dmic-delay : specify delay time for DMIC ready.
>> + If this option is specified, which means it's required dmic need
>> + delay for DMIC to ready so that rt5514 can avoid recording before
>> + DMIC send valid data
> What units is this in? Per the code it looks like ms, so if we follow
> Documentation/devicetree/bindings/property-units.txt, thous should be
> named something like dmic-enable-delay-ms.
OK, the "dmic-wakeup-delay-ms" have been done.
> That said, do we even need a property for this? Does this vary much in
> practice?
>
> If it does, can we not derive this delay from other information (e.g.
> the rates of input clocks and so on)? What exactly determines the
> necessary delay?
Yeah, the DMIC spec indicates wake-up time as 15ms max, so we need to
start recording 15ms after MCLK after testing.
@Woojoo, please correct me if I was wrong.
Thanks.
>
> Thanks,
> Mark.
>
>>
>> sound {
>> diff --git a/sound/soc/rockchip/rk3399_gru_sound.c b/sound/soc/rockchip/rk3399_gru_sound.c
>> index 164b6da..6ab838b 100644
>> --- a/sound/soc/rockchip/rk3399_gru_sound.c
>> +++ b/sound/soc/rockchip/rk3399_gru_sound.c
>> @@ -37,6 +37,8 @@
>>
>> #define SOUND_FS 256
>>
>> +unsigned int rt5514_dmic_delay;
>> +
>> static struct snd_soc_jack rockchip_sound_jack;
>>
>> static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {
>> @@ -122,6 +124,9 @@ static int rockchip_sound_rt5514_hw_params(struct snd_pcm_substream *substream,
>> return ret;
>> }
>>
>> + /* Wait for DMIC stable */
>> + msleep(rt5514_dmic_delay);
>> +
>> return 0;
>> }
>>
>> @@ -334,6 +339,15 @@ static int rockchip_sound_probe(struct platform_device *pdev)
>> return -ENODEV;
>> }
>>
>> + /* Set DMIC delay */
>> + ret = device_property_read_u32(&pdev->dev, "dmic-delay",
>> + &rt5514_dmic_delay);
>> + if (ret) {
>> + rt5514_dmic_delay = 0;
>> + dev_dbg(&pdev->dev,
>> + "no optional property 'dmic-delay' found, default: no delay\n");
>> + }
>> +
>> rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name = kstrdup_const(dev_name(dev), GFP_KERNEL);
>> rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name = kstrdup_const(dev_name(dev), GFP_KERNEL);
>> rockchip_dailinks[DAILINK_RT5514_DSP].platform_name = kstrdup_const(dev_name(dev), GFP_KERNEL);
>> --
>> 1.7.9.5
>>
>>
>
>
--
- Xing Zheng
^ permalink raw reply
* [PATCH v2] ASoC: rk3399_gru_sound: fix recording pop at first attempt
From: Xing Zheng @ 2016-09-22 13:50 UTC (permalink / raw)
To: linux-arm-kernel
From: Wonjoon Lee <woojoo.lee@samsung.com>
Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
Changes in v2:
- rename dmic-delay to dmic-wakeup-delay-ms
.../bindings/sound/rockchip,rk3399-gru-sound.txt | 7 +++++++
sound/soc/rockchip/rk3399_gru_sound.c | 14 ++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
index f19b6c8..eac91db 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -6,10 +6,17 @@ Required properties:
connected to the codecs
- rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
+Optional properties:
+- dmic-wakeup-delay-ms : specify delay time (ms) for DMIC ready.
+ If this option is specified, which means it's required dmic need
+ delay for DMIC to ready so that rt5514 can avoid recording before
+ DMIC send valid data
+
Example:
sound {
compatible = "rockchip,rk3399-gru-sound";
rockchip,cpu = <&i2s0>;
rockchip,codec = <&max98357a &rt5514 &da7219>;
+ dmic-wakeup-delay-ms = <20>;
};
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c b/sound/soc/rockchip/rk3399_gru_sound.c
index ee06489..9ed735a 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -38,6 +38,8 @@
#define SOUND_FS 256
+unsigned int rt5514_dmic_delay;
+
static struct snd_soc_jack rockchip_sound_jack;
static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {
@@ -123,6 +125,9 @@ static int rockchip_sound_rt5514_hw_params(struct snd_pcm_substream *substream,
return ret;
}
+ /* Wait for DMIC stable */
+ msleep(rt5514_dmic_delay);
+
return 0;
}
@@ -343,6 +348,15 @@ static int rockchip_sound_probe(struct platform_device *pdev)
return -ENODEV;
}
+ /* Set DMIC delay */
+ ret = device_property_read_u32(&pdev->dev, "dmic-delay",
+ &rt5514_dmic_delay);
+ if (ret) {
+ rt5514_dmic_delay = 0;
+ dev_dbg(&pdev->dev,
+ "no optional property 'dmic-delay' found, default: no delay\n");
+ }
+
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name = kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name = kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].platform_name = kstrdup_const(dev_name(dev), GFP_KERNEL);
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 0/3] efi: MMC proxy support for the UEFI varstore
From: Ard Biesheuvel @ 2016-09-22 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922125854.GC26596@leverpostej>
(adding Charles whom I failed to cc)
On 22 September 2016 at 13:58, Mark Rutland <mark.rutland@arm.com> wrote:
> Hi Ard,
>
> On Thu, Sep 22, 2016 at 12:30:03PM +0100, Ard Biesheuvel wrote:
>> ================================================================================
>> NOTE: this is a work in progress, and not fully functional yet. In particular,
>> the actual MMC host protocol methods are stubbed out at the moment, and need to
>> be wired up to the Linux device drivers.
>> ================================================================================
>>
>> On mobile and embedded systems, there is usually only a single MMC device for
>> non-volatile storage, which sits behind a controller that is owned by the OS at
>> runtime. This makes it difficult to host the UEFI variable store on MMC as well,
>> since the UEFI runtime services routines expect ownership of the underlying
>> device as well.
>>
>> This series proposes an approach to work around this. It implements the UEFI
>> MMC host protocol in the kernel, in a way that makes it possible to expose it
>> to the firmware. At the same time, the firmware needs be set up for this, i.e.,
>> it needs to expose its MMC host protocol pointer via a UEFI configuration table,
>> so that the kernel can override it if it decides to expose this functionality
>> to the firmware.
>
> At a high level, and assuming a number of details from previous
> discussions, I think the general approach of having the kernel mediate
> access to the MMC makes sense.
>
OK.
> However, I don't think that this series has enough detail for critical
> review, even at the interface level. e.g. there is no mention of how
> this caters for replay attacks and so on (which the current spec
> sidesteps). I'm under the impression that there are mechanisms which
> have been discussed for this, and I hope this is simply an oversight.
>
This series does not take UEFI Secure Boot into account at all, and so
replay protection is not currently being addressed explicitly.
However, the reason for exposing an MMC host protocol rather than some
more abstract protocol (i.e., block I/O) is to allow firmware that
uses RPMB over MMC (e.g, with an authentication component residing in
the secure world) to reuse the same interface while maintaining the
same level of security it would have if it owned the MMC fully.
> I also think that this needs to go via the USWG (and to the UEFI spec),
> before we can consider using it. I say this because:
>
> * This is critical to correct operation of variable storage as required
> for the standard boot flow. This is a major change to the way variable
> storage works today, with a number of (security) implications.
>
The primary issue there is that the variable protocols are
architectural DXE protocols defined in the PI spec, not the UEFI spec
(and the MMC host protocol I am using here is not in any spec afaik),
and so implementing this in a UEFI compliant way is not currently
possible. Exposing a UEFI protocol like block I/O is not sufficient,
since the variable protocols are depended upon earlier in the boot
sequence (in UEFI implementations based on PI).
So yes, this needs to be discussed (and it will be, but not out in the
open, unfortunately.) However, it is unclear whether it is feasible to
address this at the UEFI level, or whether we will need to go beyond
and define something based on the PI spec directly. (/me looks at
Charles)
> * There are others in this space trying to use the same class of
> hardware, e.g. FreeBSD. We don't want a Linux-specific interface, nor
> do we want a proliferation of interfaces for this purpose.
>
No, we don't.
> I have a few other general concerns:
>
> * Identification of the relevant MMC device(s).
>
> Patch 3 suggests a devicetree property. I don't think that the
> 'linux,' prefix makes sense, and it's not clear what we would do with
> ACPI.
>
> Does the MMC device not have some identifier we can query, so that we
> can match this up without requiring additional info in ACPI/DT?
>
Good question. IIRC (but I'm a little rusty here), that is the case
for SD but not for MMC? (but it probably depends on the version) In
any case, there are other concerns here, regarding how the OS knows
which slice of the MMC is in use by the firmware. So the firmware
should expose sufficient information to the OS for it to figure out
which MMC volume it should expose to the firmware. UEFI generally uses
device paths for this, but I'm not sure if that is appropriate here.
> * Lifetime guarantees
>
> When is it valid for EFI to call the MMC proxy? Can other services
> (e.g. ACPI) call this?
>
> How do we handle kexec/kdump? e.g. how do we teardown the interface
> before branching to a new kernel, how do we safely tear down a crashed
> kernel's interface, what can we call before doing so?
>
> How do we handle suspend/resume? e.g. is it necessary to re-register
> upon resume?
>
All good questions, and exactly the kind of feedback I am seeking.
Tearing down the interface could be as simple as clearing the pointer,
but some synchronization is probably in order to make sure that no
calls are in progress.
But to clarify the purpose of this series: are there any concerns
regarding exposing callbacks to the firmware in general, and for MMC
access in particular, from the Linux side? This code seems to work as
expected, but I may have missed something important (and I still need
help to actually wire it up to the MMC code)
--
Ard.
^ permalink raw reply
* [RFC PATCH 00/11] pci: support for configurable PCI endpoint
From: Arnd Bergmann @ 2016-09-22 13:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57DA5CC1.6030502@ti.com>
On Thursday, September 15, 2016 2:03:05 PM CEST Kishon Vijay Abraham I wrote:
> On Wednesday 14 September 2016 06:55 PM, Arnd Bergmann wrote:
> > On Wednesday, September 14, 2016 10:41:56 AM CEST Kishon Vijay Abraham I wrote:
> > I've added the drivers/ntb maintainers to Cc, given that there is
> > a certain degree of overlap between your work and the existing
> > code, I think they should be part of the discussion.
> >
> >> Known Limitation:
> >> *) Does not support multi-function devices
> >
> > If I understand it right, this was a problem for USB and adding
> > it later made it somewhat inconsistent. Maybe we can at least
> > try to come up with an idea of how multi-function devices
> > could be handled even if we don't implement it until someone
> > actually needs it.
>
> Actually IMO multi-function device in PCI should be much simpler than it is for
> USB. In the case of USB, all the functions in a multi-function device will
> share the same *usb configuration* . (USB device can have multiple
> configuration but only one can be enabled at a time). A multi-function USB
> device will still have a single vendor-id/product-id/class... So I think a
> separate library (composite.c) in USB makes sense.
Ok, makes sense.
> But in the case of PCI, every function can be treated independently since all
> the functions have it's own 4KB configuration space. Each function can be
> configured independently. Each can have it's own vendor-id/product-id/class..
> I'm not sure if we'll need a separate library for PCI like we have for USB.
I think it depends on whether we want to add the software multi-function
support you mention.
> Now the restriction for not allowing multi-function device is because of the
> following structure definition.
>
> struct pci_epc {
> ..
> struct pci_epf *epf;
> ..
> };
>
> EPC has a single reference to EPF and it is used *only* to notify the function
> driver when the link is up. (If this can be changed to use notification
> mechanism, multi-function devices can be supported here)
>
> One more place where this restriction arises is in designware driver
>
> struct dw_pcie_ep {
> ..
> u8 bar_to_atu[6];
> ..
> };
>
> We use single ATU window to configure a BAR (in BAR). If there are multiple
> functions, then this should also be modified since each function has 6 BARs.
>
> This can be fixed without much effort unless some other issue props up.
Ok.
> >
> > Is your hardware able to make the PCIe endpoint look like
> > a device with multiple PCI functions, or would one have to
> > do this in software inside of a single PCI function if we
> > ever need it?
>
> The hardware I have doesn't support multiple PCI functions (like having a
> separate configuration space for each function). It has a dedicated space for
> configuration space supporting only one function. [Section 24.9.7.3.2
> PCIe_SS_EP_CFG_DBICS Register Description in [1]].
>
> yeah, it has to be done in software (but that won't be multi-function device in
> PCI terms).
>
> [1] -> http://www.ti.com/lit/ug/spruhz6g/spruhz6g.pdf
Ok, so in theory there can be other hardware (and quite likely is)
that supports multiple functions, and we can extend the framework
to support them without major obstacles, but your hardware doesn't,
so you kept it simple with one hardcoded function, right?
Seems completely reasonable to me.
> >> TODO:
> >> *) access buffers in RC
> >> *) raise MSI interrupts
> >> *) Enable user space control for the RC side PCI driver
> >
> > The user space control would end up just being one of several
> > gadget drivers, right? E.g. gadget drivers for standard hardware
> > (8250 uart, ATA, NVMe, some ethernet) could be done as kernel
> > drivers while a user space driver can be used for things that
> > are more unusual and that don't need to interface to another
> > part of the kernel?
>
> Actually I didn't mean that. It was more with respect to the host side PCI test
> driver (drivers/misc/pci_endpoint_test.c). Right now it validates BAR, irq
> itself. I wanted to change this so that the user controls which tests to run.
> (Like for USB gadget zero tests, testusb.c invokes ioctls to perform various
> tests). Similarly I want to have a userspace program invoke pci_endpoint_test
> to perform various PCI tests.
Ok, I see. So what I described above would be yet another function
driver that can be implemented, but so far, you have not planned
to do that because there was not need, right?
> >
> >> *) Adapt all other users of designware to use the new design (only
> >> dra7xx has been adapted)
> >
> > I don't fully understand this part. Does every designware based
> > driver need modifications, or are the changes to the
> > generic parts of the designware driver enough to make it
> > work for the simpler platforms?
>
> I have changed the core designware driver structures (like previously the
> platform drivers will only use pcie_port, but now I introduced struct dw_pcie
> to support both host and endpoint). This will break (compilation failure) all
> the designware based drivers (except dra7xx). All these drivers should be
> adapted to the new change (even if they work only in host mode these has to be
> adapted).
Ah, so we have to do two separate modifications to each designware driver:
a) make it work with your patch (mandatory)
b) make it support endpoint mode (optional)
> >> HOW TO:
> >>
> >> ON THE EP SIDE:
> >> ***************
> >>
> >> /* EP function is configured using configfs */
> >> # mount -t configfs none /sys/kernel/config
> >>
> >> /* PCI EP core layer creates "pci_ep" entry in configfs */
> >> # cd /sys/kernel/config/pci_ep/
> >>
> >> /*
> >> * This is the 1st step in creating an endpoint function. This
> >> * creates the endpoint function device *instance*. The string
> >> * before the .<num> suffix will identify the driver this
> >> * EP function will bind to.
> >> * Just pci_epf_test is also valid. The .<num> suffix is used
> >> * if there are multiple PCI controllers and all of them wants
> >> * to use the same function.
> >> */
> >> # mkdir pci_epf_test.0
> >
> > I haven't used USB gadgets, but I assume this is modeled around
> > the same interface. If there are notable differences, please mention
> > what they are. Otherwise the general concept seems rather nice to me.
>
> Yeah, both USB gadget and PCI endpoint use configfs interface but the semantics
> are quite different.
>
> Every directory in *usb_gadget* corresponds to a gadget device, and the gadget
> device has a functions sub-directory which has the USB functions. And these
> directories have fields or attributes specific to USB.
>
> But in the case of PCI, every directory in *pci_ep* corresponds to a PCI
> function and it has fields or attributes specific to PCI function.
Ok, I see.
> The main reason for using configfs for PCI endpoint is to give the users to
> control "which function has to be bound to which controller". The same concept
> is used for USB gadget as well but there it is "which gadget device has to be
> bound to which controller".
We should still find out whether it's important that you can have
a single PCI function with a software multi-function support of some
sort. We'd still be limited to six BARs in total, and would also need
something to identify those sub-functions, so implementing that might
get quite hairy.
Possibly this could be done at a higher level, e.g. by implementing
a PCI-virtio multiplexer that can host multiple virtio based devices
inside of a single PCI function. If we think that would be a good idea,
we should make sure the configfs interface is extensible enough to
handle that.
One use case I have in mind for this is to have a PCI function that
can use virtio to provide rootfs (virtio-blk or 9pfs), network
and console to the system that implements the PCI function (note
that this is the opposite direction of what almost everyone else
uses PCI devices for).
> > Let's talk (high-level) about the DT binding. I see that the way
> > you have done it here, one will need to have a different .dtb file
> > for a machine depending on whether the PCIe is used in host or
> > endpoint mode. The advantage of this way is that it's a much
> > cleaner binding (PCIe host bindings are a mess, and adding more
> > options to it will only make it worse), the downside is that
> > you can't decide at runtime what you want to use it for. E.g.
> > connecting two identical machines over PCIe requires deciding
> > in the bootloader which one is the endpoint, or using DT
> > overlays, which may be awkward for some users. Is this a realistic
> > use case, or do you expect that all machines will only ever be
> > used in one of the two ways?
>
> It would definitely be nice to select the mode at runtime. Even for this patch
> series, I added a temporary dtsi patch to configure the pci controller in EP
> mode (which can't be merged since the same controller is also used to test RC).
I think it should be possible to have two bindings that define a
distinct set of properties, and have one node that is marked
as "compatible" with both of them in order to let the OS choose
one or the other mode.
Arnd
^ permalink raw reply
* [PATCH v2] musb: Export musb_root_disconnect for use in modules
From: Bin Liu @ 2016-09-22 13:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921205133.GC3981@uda0271908>
On Wed, Sep 21, 2016 at 03:51:33PM -0500, Bin Liu wrote:
> Hi,
>
> On Sat, Sep 17, 2016 at 12:08:10PM +0200, Hans de Goede wrote:
> > Export musb_root_disconnect for use in modules, so that musb glue
> > code build as module can use it.
> >
> > This fixes the buildbot errors for -next in arm64-allmodconfig
> > and arm-allmodconfig.
> >
> > Fixes: 7cba17ec9adc8cf ("musb: sunxi: Add support for platform_set_mode")
> > Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>
> Applied. Thanks.
Removed it from my tree, since Greg already picked it.
Regards,
-Bin.
^ permalink raw reply
* [PATCH v2] arm: dts: zynq: Add MicroZed board support
From: Jagan Teki @ 2016-09-22 13:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Jagan Teki <jteki@openedev.com>
Added basic dts support for MicroZed board.
- UART
- SDHCI
- Ethernet
Cc: Soren Brinkmann <soren.brinkmann@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
---
Changes for v2:
- Add SDHCI
- Add Ethernet
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/zynq-microzed.dts | 95 +++++++++++++++++++++++++++++++++++++
2 files changed, 96 insertions(+)
create mode 100644 arch/arm/boot/dts/zynq-microzed.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index faacd52..4d7b858 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -862,6 +862,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \
wm8750-apc8750.dtb \
wm8850-w70v2.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += \
+ zynq-microzed.dtb \
zynq-parallella.dtb \
zynq-zc702.dtb \
zynq-zc706.dtb \
diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts
new file mode 100644
index 0000000..9e64496
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-microzed.dts
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2015 Jagan Teki <jteki@openedev.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq MicroZED Development Board";
+ compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy at 0 {
+ reg = <0>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+};
+
+&pinctrl0 {
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO29", "MIO31", "MIO36";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
+ "MIO35", "MIO37", "MIO38", "MIO39";
+ bias-disable;
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCHv2 2/3] tty/serial: at91: fix hardware handshake with GPIOs
From: Uwe Kleine-König @ 2016-09-22 13:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160912094733.21501-3-richard.genoud@gmail.com>
On Mon, Sep 12, 2016 at 11:47:32AM +0200, Richard Genoud wrote:
> Commit 1cf6e8fc8341 ("tty/serial: at91: fix RTS line management when
> hardware handshake is enabled") broke the hardware handshake when GPIOs
> where used.
s/where/were/
> Hardware handshake with GPIOs used to work before this commit because
> the CRTSCTS flag (termios->c_cflag) was set, but not the
> ATMEL_US_USMODE_HWHS flag (controller register) ; so hardware handshake
> enabled, but not handled by the controller.
>
> This commit restores this behaviour.
>
> NB: -stable is not Cced because it doesn't cleanly apply on 4.1+
> and it will also need previous commit:
> "serial: mctrl_gpio: implement mctrl_gpio_use_rtscts"
>
> Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> Fixes: 1cf6e8fc8341 ("tty/serial: at91: fix RTS line management when hardware handshake is enabled")
> ---
> drivers/tty/serial/atmel_serial.c | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
> index 2eaa18ddef61..e9b4fbf88c2d 100644
> --- a/drivers/tty/serial/atmel_serial.c
> +++ b/drivers/tty/serial/atmel_serial.c
> @@ -2025,6 +2025,7 @@ static void atmel_serial_pm(struct uart_port *port, unsigned int state,
> static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
> struct ktermios *old)
> {
> + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
> unsigned long flags;
> unsigned int old_mode, mode, imr, quot, baud;
>
> @@ -2126,8 +2127,12 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
> atmel_uart_writel(port, ATMEL_US_TTGR,
> port->rs485.delay_rts_after_send);
> mode |= ATMEL_US_USMODE_RS485;
> - } else if (termios->c_cflag & CRTSCTS) {
> - /* RS232 with hardware handshake (RTS/CTS) */
> + } else if ((termios->c_cflag & CRTSCTS) &&
> + !mctrl_gpio_use_rtscts(atmel_port->gpios)) {
IMHO the behaviour of the hw controlled pins shouldn't change when
mctrl_gpio is in use (if possible). But I don't understand the issue so
I guess you need a better changelog.
> + /*
> + * RS232 with hardware handshake (RTS/CTS)
> + * handled by the controller.
> + */
> if (atmel_use_dma_rx(port) && !atmel_use_fifo(port)) {
> dev_info(port->dev, "not enabling hardware flow control because DMA is used");
> termios->c_cflag &= ~CRTSCTS;
> @@ -2135,7 +2140,7 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
> mode |= ATMEL_US_USMODE_HWHS;
> }
> } else {
> - /* RS232 without hadware handshake */
> + /* RS232 without hadware handshake or controlled by GPIOs */
When touching this line, please also do s/hadware/hardware/.
> mode |= ATMEL_US_USMODE_NORMAL;
> }
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCHv2 1/3] serial: mctrl_gpio: implement mctrl_gpio_use_rtscts
From: Uwe Kleine-König @ 2016-09-22 13:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160912094733.21501-2-richard.genoud@gmail.com>
On Mon, Sep 12, 2016 at 11:47:31AM +0200, Richard Genoud wrote:
> This function returns true if CTS and RTS are used as GPIOs.
> Some drivers (like atmel_serial) needs to know if the flow control is
> handled by the controller or by GPIOs.
>
> Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
> ---
> drivers/tty/serial/serial_mctrl_gpio.c | 8 ++++++++
> drivers/tty/serial/serial_mctrl_gpio.h | 10 ++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/tty/serial/serial_mctrl_gpio.c b/drivers/tty/serial/serial_mctrl_gpio.c
> index d2da6aa7f27d..93bed8c99796 100644
> --- a/drivers/tty/serial/serial_mctrl_gpio.c
> +++ b/drivers/tty/serial/serial_mctrl_gpio.c
> @@ -17,6 +17,7 @@
> #include <linux/err.h>
> #include <linux/device.h>
> #include <linux/irq.h>
> +#include <linux/err.h>
> #include <linux/gpio/consumer.h>
> #include <linux/termios.h>
> #include <linux/serial_core.h>
> @@ -72,6 +73,13 @@ struct gpio_desc *mctrl_gpio_to_gpiod(struct mctrl_gpios *gpios,
> }
> EXPORT_SYMBOL_GPL(mctrl_gpio_to_gpiod);
>
> +bool mctrl_gpio_use_rtscts(struct mctrl_gpios *gpios)
> +{
> + return !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) &&
> + !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_RTS));
mctrl_gpio_to_gpiod cannot return an error pointer. So this is
(surprise!) a wrong usage of IS_ERR_OR_NULL.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH 0/2] BQL support and fix for a regression issue
From: Eric Dumazet @ 2016-09-22 13:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922.082540.992436214283504080.davem@davemloft.net>
On Thu, 2016-09-22 at 08:25 -0400, David Miller wrote:
> From: sunil.kovvuri at gmail.com
> Date: Thu, 22 Sep 2016 14:35:19 +0530
>
> > From: Sunil Goutham <sgoutham@cavium.com>
> >
> > These patches add byte queue limit support and also fixes a regression
> > issue introduced by commit
> > 'net: thunderx: Use netdev's name for naming VF's interrupts'
>
> The correct way to refer to commits when you fix a bug is
> to use the "Fixes: " tag right before the signoffs and ACKs.
>
> The correct form is:
>
> Fixes: $SHA1_ID ("Commit header line.")
>
> You'll see this in many other netdev commits.
Thanks a lot David for this enforcement, it really helps bug tracking
and backports
Note that the $SHA1_ID should be truncated to 12 first chars.
Refer to Documentation/SubmittingPatches around line 191 for more
details.
^ permalink raw reply
* [RFC PATCH 0/3] efi: MMC proxy support for the UEFI varstore
From: Mark Rutland @ 2016-09-22 12:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474543806-19210-1-git-send-email-ard.biesheuvel@linaro.org>
Hi Ard,
On Thu, Sep 22, 2016 at 12:30:03PM +0100, Ard Biesheuvel wrote:
> ================================================================================
> NOTE: this is a work in progress, and not fully functional yet. In particular,
> the actual MMC host protocol methods are stubbed out at the moment, and need to
> be wired up to the Linux device drivers.
> ================================================================================
>
> On mobile and embedded systems, there is usually only a single MMC device for
> non-volatile storage, which sits behind a controller that is owned by the OS at
> runtime. This makes it difficult to host the UEFI variable store on MMC as well,
> since the UEFI runtime services routines expect ownership of the underlying
> device as well.
>
> This series proposes an approach to work around this. It implements the UEFI
> MMC host protocol in the kernel, in a way that makes it possible to expose it
> to the firmware. At the same time, the firmware needs be set up for this, i.e.,
> it needs to expose its MMC host protocol pointer via a UEFI configuration table,
> so that the kernel can override it if it decides to expose this functionality
> to the firmware.
At a high level, and assuming a number of details from previous
discussions, I think the general approach of having the kernel mediate
access to the MMC makes sense.
However, I don't think that this series has enough detail for critical
review, even at the interface level. e.g. there is no mention of how
this caters for replay attacks and so on (which the current spec
sidesteps). I'm under the impression that there are mechanisms which
have been discussed for this, and I hope this is simply an oversight.
I also think that this needs to go via the USWG (and to the UEFI spec),
before we can consider using it. I say this because:
* This is critical to correct operation of variable storage as required
for the standard boot flow. This is a major change to the way variable
storage works today, with a number of (security) implications.
* There are others in this space trying to use the same class of
hardware, e.g. FreeBSD. We don't want a Linux-specific interface, nor
do we want a proliferation of interfaces for this purpose.
I have a few other general concerns:
* Identification of the relevant MMC device(s).
Patch 3 suggests a devicetree property. I don't think that the
'linux,' prefix makes sense, and it's not clear what we would do with
ACPI.
Does the MMC device not have some identifier we can query, so that we
can match this up without requiring additional info in ACPI/DT?
* Lifetime guarantees
When is it valid for EFI to call the MMC proxy? Can other services
(e.g. ACPI) call this?
How do we handle kexec/kdump? e.g. how do we teardown the interface
before branching to a new kernel, how do we safely tear down a crashed
kernel's interface, what can we call before doing so?
How do we handle suspend/resume? e.g. is it necessary to re-register
upon resume?
Thanks,
Mark.
> Note that these patches are based on patches in the EFI tree that are queued
> for v4.9, which replace the runtime wrappers spinlock with a semaphore. This
> allows us to sleep in the firmware callbacks.
>
> Prerequisites for using these patches:
>
> * qemu-system-aarch64 built from this branch:
> https://git.linaro.org/people/ard.biesheuvel/qemu.git/shortlog/refs/heads/mach-virt-pl181
> which adds a PL181 SD/MMC controller to the mach-virt model, and exposes it
> via the device tree. It also sets the 'linux,uefi-varstore' property on this
> node.
>
> * UEFI firmware built from this branch:
> https://git.linaro.org/people/ard.biesheuvel/uefi-next.git/shortlog/refs/heads/mmc-proxy
>
> Build using the following command
> build -a AARCH64 -t GCC5 -p ArmVirtPkg/ArmVirtQemuMmcVars.dsc
>
> Run using
> qemu-system-aarch64 \
> -M virt -cpu cortex-a57 -m 2048 \
> -device virtio-blk-device,drive=boot \
> -drive if=none,id=boot,file=fat:<path-of-Image>,format=raw \
> -kernel <edk2-dir>/Build/ArmVirtQemuMmcVars-AARCH64/DEBUG_GCC5/FV/QEMU_EFI.fd \
> -sd <edk2-dir>/build/edk2/Build/ArmVirtQemuMmcVars-AARCH64/DEBUG_GCC5/FV/QEMU_VARS.fd \
> -nographic $@
>
> This will give you an UEFI environment which keeps its UEFI variables in the
> emulated MMC volume, and exposes its MMC host protocol in a way that allows
> these patches to hook into it.
>
> Patches #1 and #2 implement the arch specific hooks to preserve/restore the NEON
> registers that the firmware may expect to be preserved across function calls.
>
> Patch #3 implements the plumbing to call back into the kernel from the firmware.
>
> Please comment on whether this approach seems feasible, and in particular, how
> on earth I should wire this up to the actual MMC code.
>
> Thanks,
> Ard.
>
> Ard Biesheuvel (3):
> efi/arm64: add SIMD stash/unstash operations
> efi/arm: add SIMD stash/unstash operations
> efi: implement MMC proxy support for the UEFI variable store
>
> arch/arm/include/asm/efi.h | 11 +
> arch/arm64/include/asm/efi.h | 33 +++
> drivers/firmware/efi/Kconfig | 9 +
> drivers/firmware/efi/Makefile | 1 +
> drivers/firmware/efi/arm-init.c | 2 +
> drivers/firmware/efi/mmc-proxy.c | 222 ++++++++++++++++++++
> include/linux/efi.h | 1 +
> 7 files changed, 279 insertions(+)
> create mode 100644 drivers/firmware/efi/mmc-proxy.c
>
> --
> 2.7.4
>
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