* [PATCH 07/15] perf tools: Add PMU configuration to tools
From: Arnaldo Carvalho de Melo @ 2016-09-22 21:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474578779-14095-1-git-send-email-acme@kernel.org>
From: Mathieu Poirier <mathieu.poirier@linaro.org>
Now that the required mechanic is there to deal with PMU specific
configuration, add the functionality to the tools where events can be
selected.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-arm-kernel at lists.infradead.org
Link: http://lkml.kernel.org/r/1474041004-13956-7-git-send-email-mathieu.poirier at linaro.org
[ Fix the build on XSI-compliant systems, using str_error_r() to make sure we return a string, not an integer ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/builtin-record.c | 10 ++++++++++
tools/perf/builtin-stat.c | 9 +++++++++
tools/perf/builtin-top.c | 13 +++++++++++++
3 files changed, 32 insertions(+)
diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c
index 03251c7f14ec..2d0d69be3bf8 100644
--- a/tools/perf/builtin-record.c
+++ b/tools/perf/builtin-record.c
@@ -22,6 +22,7 @@
#include "util/evlist.h"
#include "util/evsel.h"
#include "util/debug.h"
+#include "util/drv_configs.h"
#include "util/session.h"
#include "util/tool.h"
#include "util/symbol.h"
@@ -383,6 +384,7 @@ static int record__open(struct record *rec)
struct perf_evlist *evlist = rec->evlist;
struct perf_session *session = rec->session;
struct record_opts *opts = &rec->opts;
+ struct perf_evsel_config_term *err_term;
int rc = 0;
perf_evlist__config(evlist, opts, &callchain_param);
@@ -412,6 +414,14 @@ try_again:
goto out;
}
+ if (perf_evlist__apply_drv_configs(evlist, &pos, &err_term)) {
+ error("failed to set config \"%s\" on event %s with %d (%s)\n",
+ err_term->val.drv_cfg, perf_evsel__name(pos), errno,
+ str_error_r(errno, msg, sizeof(msg)));
+ rc = -1;
+ goto out;
+ }
+
rc = record__mmap(rec);
if (rc)
goto out;
diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c
index 90882b1d6a91..688dea7cb08f 100644
--- a/tools/perf/builtin-stat.c
+++ b/tools/perf/builtin-stat.c
@@ -52,6 +52,7 @@
#include "util/evlist.h"
#include "util/evsel.h"
#include "util/debug.h"
+#include "util/drv_configs.h"
#include "util/color.h"
#include "util/stat.h"
#include "util/header.h"
@@ -540,6 +541,7 @@ static int __run_perf_stat(int argc, const char **argv)
int status = 0;
const bool forks = (argc > 0);
bool is_pipe = STAT_RECORD ? perf_stat.file.is_pipe : false;
+ struct perf_evsel_config_term *err_term;
if (interval) {
ts.tv_sec = interval / USEC_PER_MSEC;
@@ -611,6 +613,13 @@ try_again:
return -1;
}
+ if (perf_evlist__apply_drv_configs(evsel_list, &counter, &err_term)) {
+ error("failed to set config \"%s\" on event %s with %d (%s)\n",
+ err_term->val.drv_cfg, perf_evsel__name(counter), errno,
+ str_error_r(errno, msg, sizeof(msg)));
+ return -1;
+ }
+
if (STAT_RECORD) {
int err, fd = perf_data_file__fd(&perf_stat.file);
diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c
index 400785702566..fe3af9535e85 100644
--- a/tools/perf/builtin-top.c
+++ b/tools/perf/builtin-top.c
@@ -24,6 +24,7 @@
#include "util/annotate.h"
#include "util/config.h"
#include "util/color.h"
+#include "util/drv_configs.h"
#include "util/evlist.h"
#include "util/evsel.h"
#include "util/machine.h"
@@ -913,6 +914,10 @@ static int callchain_param__setup_sample_type(struct callchain_param *callchain)
static int __cmd_top(struct perf_top *top)
{
+ char msg[512];
+ struct perf_evsel *pos;
+ struct perf_evsel_config_term *err_term;
+ struct perf_evlist *evlist = top->evlist;
struct record_opts *opts = &top->record_opts;
pthread_t thread;
int ret;
@@ -947,6 +952,14 @@ static int __cmd_top(struct perf_top *top)
if (ret)
goto out_delete;
+ ret = perf_evlist__apply_drv_configs(evlist, &pos, &err_term);
+ if (ret) {
+ error("failed to set config \"%s\" on event %s with %d (%s)\n",
+ err_term->val.drv_cfg, perf_evsel__name(pos), errno,
+ str_error_r(errno, msg, sizeof(msg)));
+ goto out_delete;
+ }
+
top->session->evlist = top->evlist;
perf_session__set_id_hdr_size(top->session);
--
2.7.4
^ permalink raw reply related
* [PATCH 08/15] perf tools: Add sink configuration for cs_etm PMU
From: Arnaldo Carvalho de Melo @ 2016-09-22 21:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474578779-14095-1-git-send-email-acme@kernel.org>
From: Mathieu Poirier <mathieu.poirier@linaro.org>
Using the PMU::set_drv_config() callback to enable the CoreSight sink
that will be used for the trace session.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-arm-kernel at lists.infradead.org
Link: http://lkml.kernel.org/r/1474041004-13956-8-git-send-email-mathieu.poirier at linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/arch/arm/util/cs-etm.c | 58 +++++++++++++++++++++++++++++++++++++++
tools/perf/arch/arm/util/cs-etm.h | 3 ++
tools/perf/arch/arm/util/pmu.c | 2 ++
3 files changed, 63 insertions(+)
diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c
index 829c479614f1..47d584da5819 100644
--- a/tools/perf/arch/arm/util/cs-etm.c
+++ b/tools/perf/arch/arm/util/cs-etm.c
@@ -27,12 +27,16 @@
#include "../../util/auxtrace.h"
#include "../../util/cpumap.h"
#include "../../util/evlist.h"
+#include "../../util/evsel.h"
#include "../../util/pmu.h"
#include "../../util/thread_map.h"
#include "../../util/cs-etm.h"
#include <stdlib.h>
+#define ENABLE_SINK_MAX 128
+#define CS_BUS_DEVICE_PATH "/bus/coresight/devices/"
+
struct cs_etm_recording {
struct auxtrace_record itr;
struct perf_pmu *cs_etm_pmu;
@@ -557,3 +561,57 @@ struct auxtrace_record *cs_etm_record_init(int *err)
out:
return NULL;
}
+
+static FILE *cs_device__open_file(const char *name)
+{
+ struct stat st;
+ char path[PATH_MAX];
+ const char *sysfs;
+
+ sysfs = sysfs__mountpoint();
+ if (!sysfs)
+ return NULL;
+
+ snprintf(path, PATH_MAX,
+ "%s" CS_BUS_DEVICE_PATH "%s", sysfs, name);
+
+ printf("path: %s\n", path);
+
+ if (stat(path, &st) < 0)
+ return NULL;
+
+ return fopen(path, "w");
+
+}
+
+static __attribute__((format(printf, 2, 3)))
+int cs_device__print_file(const char *name, const char *fmt, ...)
+{
+ va_list args;
+ FILE *file;
+ int ret = -EINVAL;
+
+ va_start(args, fmt);
+ file = cs_device__open_file(name);
+ if (file) {
+ ret = vfprintf(file, fmt, args);
+ fclose(file);
+ }
+ va_end(args);
+ return ret;
+}
+
+int cs_etm_set_drv_config(struct perf_evsel_config_term *term)
+{
+ int ret;
+ char enable_sink[ENABLE_SINK_MAX];
+
+ snprintf(enable_sink, ENABLE_SINK_MAX, "%s/%s",
+ term->val.drv_cfg, "enable_sink");
+
+ ret = cs_device__print_file(enable_sink, "%d", 1);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
diff --git a/tools/perf/arch/arm/util/cs-etm.h b/tools/perf/arch/arm/util/cs-etm.h
index 909f486d02d1..5256741be549 100644
--- a/tools/perf/arch/arm/util/cs-etm.h
+++ b/tools/perf/arch/arm/util/cs-etm.h
@@ -18,6 +18,9 @@
#ifndef INCLUDE__PERF_CS_ETM_H__
#define INCLUDE__PERF_CS_ETM_H__
+#include "../../util/evsel.h"
+
struct auxtrace_record *cs_etm_record_init(int *err);
+int cs_etm_set_drv_config(struct perf_evsel_config_term *term);
#endif
diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c
index af9fb666b44f..98d67399a0d6 100644
--- a/tools/perf/arch/arm/util/pmu.c
+++ b/tools/perf/arch/arm/util/pmu.c
@@ -19,6 +19,7 @@
#include <linux/coresight-pmu.h>
#include <linux/perf_event.h>
+#include "cs-etm.h"
#include "../../util/pmu.h"
struct perf_event_attr
@@ -28,6 +29,7 @@ struct perf_event_attr
if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) {
/* add ETM default config here */
pmu->selectable = true;
+ pmu->set_drv_config = cs_etm_set_drv_config;
}
#endif
return NULL;
--
2.7.4
^ permalink raw reply related
* [PATCH 0/2] Add R8A7792 MSIOF support
From: Sergei Shtylyov @ 2016-09-22 21:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2481458.x1iQg26kO7@wasted.cogentembedded.com>
Hello.
On 09/05/2016 11:54 PM, Sergei Shtylyov wrote:
> Here's the set of 2 patches against Simon Horman's 'renesas.git' repo,
> 'renesas-devel-20160905-v4.8-rc5' tag. We're adding the R8A7792 MSIOF clocks
> and device nodes. I'm not posting the board patches because the MSIOF driver
> seems erratic ATM...
>
> [1/2] ARM: dts: r8a7792: add MSIOF clock
> [2/2] ARM: dts: r8a7792: add MSIOF support
These seem stuck for no apparent reason. Simon?
WBR, Sergei
^ permalink raw reply
* [PATCH v5] KVM: arm/arm64: Route vtimer events to user space
From: Christoffer Dall @ 2016-09-22 21:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474548769-195643-1-git-send-email-agraf@suse.de>
On Thu, Sep 22, 2016 at 02:52:49PM +0200, Alexander Graf wrote:
> We have 2 modes for dealing with interrupts in the ARM world. We can either
> handle them all using hardware acceleration through the vgic or we can emulate
> a gic in user space and only drive CPU IRQ pins from there.
>
> Unfortunately, when driving IRQs from user space, we never tell user space
> about timer events that may result in interrupt line state changes, so we
> lose out on timer events if we run with user space gic emulation.
>
> This patch fixes that by syncing user space's view of the vtimer irq line
> with the kvm view of that same line.
>
> With this patch I can successfully run edk2 and Linux with user space gic
> emulation.
>
> Signed-off-by: Alexander Graf <agraf@suse.de>
>
> ---
>
> v1 -> v2:
>
> - Add back curly brace that got lost
>
> v2 -> v3:
>
> - Split into patch set
>
> v3 -> v4:
>
> - Improve documentation
>
> v4 -> v5:
>
> - Rewrite to use pending state sync in sregs (marc)
> - Remove redundant checks of vgic_initialized()
> - qemu tree to try this out: https://github.com/agraf/u-boot.git no-kvm-irqchip-for-v5
huh, qemu=u-boot?
> ---
> Documentation/virtual/kvm/api.txt | 26 ++++++++
> arch/arm/include/uapi/asm/kvm.h | 3 +
> arch/arm/kvm/arm.c | 14 ++---
> arch/arm64/include/uapi/asm/kvm.h | 3 +
> include/kvm/arm_arch_timer.h | 2 +-
> include/uapi/linux/kvm.h | 6 ++
> virt/kvm/arm/arch_timer.c | 129 ++++++++++++++++++++++++++------------
> 7 files changed, 134 insertions(+), 49 deletions(-)
>
> diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
> index 739db9a..8049327 100644
> --- a/Documentation/virtual/kvm/api.txt
> +++ b/Documentation/virtual/kvm/api.txt
> @@ -3928,3 +3928,29 @@ In order to use SynIC, it has to be activated by setting this
> capability via KVM_ENABLE_CAP ioctl on the vcpu fd. Note that this
> will disable the use of APIC hardware virtualization even if supported
> by the CPU, as it's incompatible with SynIC auto-EOI behavior.
> +
> +8.3 KVM_CAP_ARM_TIMER
> +
> +Architectures: arm, arm64
> +This capability, if KVM_CHECK_EXTENSION indicates that it is available and no
> +in-kernel interrupt controller is in use, means that that the kernel populates
> +the vcpu's run->s.regs.kernel_timer_pending field with timers that are currently
> +considered pending by kvm.
Be careful with the word 'pending' here. I think this could be
misleading, because pending is a state in the GIC, but not really
something I can find specific to the timer. It would be more
descriptive to say that the kernel maintained generic timer's output
signal is asserted.
> +
> +If active, it also allows user space to propagate its own pending state of timer
> +interrupt lines using run->s.regs.user_timer_pending. If those two fields
> +mismatch during CPU execution, kvm will exit to user space to give it a chance
I don't quite understand the semantics here. The only entity that knows
what the level state of the output of the timer is, is the kernel, which
emulates the timer. Userspace knows interrupt controller state, but if
it has a different view of the timer state than the kernel, it's because
the kernel failed to notify userspace of a change or userspace failed to
listen?
> +to update its own interrupt pending status. This usually involves triggering
> +an interrupt line on a user space emulated interrupt controller.
To me it feels like the semantics should be that userspace can always
derive the status of the timer and the level of the output signal from
the timer by simply looking at kvm_run structure.
The remaining two problems are:
(1) when should the kernel trigger exits to userspace? Presumably on
any change in the timer's output level, because this change has to be
propagated to the userspace interrupt controller.
(2) the kernel needs to somehow mask the underlying hardware timer
interrupt signal when it's active, because otherwise the guest won't
proceed. If we simply mask the hardware signal after telling userspace
the output signal is asserted and until the output signal ever becomes
deasserted, why do we need to listen to anything userspace has to say?
> +
> +The fields run->s.regs.kernel_timer_pending and run->s.regs.user_timer_pending
> +are available independent of run->kvm_valid_regs or run->kvm_dirty_regs bits.
> +If no in-kernel interrupt controller is used and the capability exists, they
> +will always be available and used.
> +
> +Currently the following bits are defined for both bitmaps:
> +
> + KVM_ARM_TIMER_VTIMER - virtual timer
> +
> +Future versions of kvm may implement additional timer events. These will get
> +indicated by additional KVM_CAP extensions.
> diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
> index a2b3eb3..caad81d 100644
> --- a/arch/arm/include/uapi/asm/kvm.h
> +++ b/arch/arm/include/uapi/asm/kvm.h
> @@ -105,6 +105,9 @@ struct kvm_debug_exit_arch {
> };
>
> struct kvm_sync_regs {
> + /* Used with KVM_CAP_ARM_TIMER */
> + u8 kernel_timer_pending;
> + u8 user_timer_pending;
> };
>
> struct kvm_arch_memory_slot {
> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> index 75f130e..dc19221 100644
> --- a/arch/arm/kvm/arm.c
> +++ b/arch/arm/kvm/arm.c
> @@ -187,6 +187,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
> case KVM_CAP_ARM_PSCI_0_2:
> case KVM_CAP_READONLY_MEM:
> case KVM_CAP_MP_STATE:
> + case KVM_CAP_ARM_TIMER:
> r = 1;
> break;
> case KVM_CAP_COALESCED_MMIO:
> @@ -474,13 +475,7 @@ static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
> return ret;
> }
>
> - /*
> - * Enable the arch timers only if we have an in-kernel VGIC
> - * and it has been properly initialized, since we cannot handle
> - * interrupts from the virtual timer with a userspace gic.
> - */
> - if (irqchip_in_kernel(kvm) && vgic_initialized(kvm))
> - ret = kvm_timer_enable(vcpu);
> + ret = kvm_timer_enable(vcpu);
>
> return ret;
> }
> @@ -588,7 +583,10 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
> */
> preempt_disable();
> kvm_pmu_flush_hwstate(vcpu);
> - kvm_timer_flush_hwstate(vcpu);
> + if (kvm_timer_flush_hwstate(vcpu)) {
> + ret = -EINTR;
> + run->exit_reason = KVM_EXIT_INTR;
> + }
> kvm_vgic_flush_hwstate(vcpu);
>
> local_irq_disable();
> diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
> index 3051f86..9aac860 100644
> --- a/arch/arm64/include/uapi/asm/kvm.h
> +++ b/arch/arm64/include/uapi/asm/kvm.h
> @@ -143,6 +143,9 @@ struct kvm_debug_exit_arch {
> #define KVM_GUESTDBG_USE_HW (1 << 17)
>
> struct kvm_sync_regs {
> + /* Used with KVM_CAP_ARM_TIMER */
> + u8 kernel_timer_pending;
> + u8 user_timer_pending;
> };
>
> struct kvm_arch_memory_slot {
> diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
> index dda39d8..8cd7240 100644
> --- a/include/kvm/arm_arch_timer.h
> +++ b/include/kvm/arm_arch_timer.h
> @@ -63,7 +63,7 @@ void kvm_timer_init(struct kvm *kvm);
> int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu,
> const struct kvm_irq_level *irq);
> void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
> -void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
> +int kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
> void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
> void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu);
>
> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
> index 300ef25..1fc02d7 100644
> --- a/include/uapi/linux/kvm.h
> +++ b/include/uapi/linux/kvm.h
> @@ -870,6 +870,7 @@ struct kvm_ppc_smmu_info {
> #define KVM_CAP_S390_USER_INSTR0 130
> #define KVM_CAP_MSI_DEVID 131
> #define KVM_CAP_PPC_HTM 132
> +#define KVM_CAP_ARM_TIMER 133
>
> #ifdef KVM_CAP_IRQ_ROUTING
>
> @@ -1327,4 +1328,9 @@ struct kvm_assigned_msix_entry {
> #define KVM_X2APIC_API_USE_32BIT_IDS (1ULL << 0)
> #define KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK (1ULL << 1)
>
> +/* Available with KVM_CAP_ARM_TIMER */
> +
> +/* Bits for run->s.regs.{user,kernel}_timer_pending */
> +#define KVM_ARM_TIMER_VTIMER (1 << 0)
> +
> #endif /* __LINUX_KVM_H */
> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> index 4309b60..0c6fc38 100644
> --- a/virt/kvm/arm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -166,21 +166,36 @@ bool kvm_timer_should_fire(struct kvm_vcpu *vcpu)
> return cval <= now;
> }
>
> +/*
> + * Synchronize the timer IRQ state with the interrupt controller.
> + */
> static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level)
> {
> int ret;
> struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
>
> - BUG_ON(!vgic_initialized(vcpu->kvm));
> -
> timer->active_cleared_last = false;
> timer->irq.level = new_level;
> - trace_kvm_timer_update_irq(vcpu->vcpu_id, timer->irq.irq,
> + trace_kvm_timer_update_irq(vcpu->vcpu_id, host_vtimer_irq,
> timer->irq.level);
> - ret = kvm_vgic_inject_mapped_irq(vcpu->kvm, vcpu->vcpu_id,
> - timer->irq.irq,
> - timer->irq.level);
> - WARN_ON(ret);
> +
> + if (irqchip_in_kernel(vcpu->kvm)) {
> + BUG_ON(!vgic_initialized(vcpu->kvm));
> +
> + /* Fire the timer in the VGIC */
> + ret = kvm_vgic_inject_mapped_irq(vcpu->kvm, vcpu->vcpu_id,
> + timer->irq.irq,
> + timer->irq.level);
> +
> + WARN_ON(ret);
> + } else {
> + struct kvm_sync_regs *regs = &vcpu->run->s.regs;
> +
> + /* Populate the timer bitmap for user space */
> + regs->kernel_timer_pending &= ~KVM_ARM_TIMER_VTIMER;
> + if (new_level)
> + regs->kernel_timer_pending |= KVM_ARM_TIMER_VTIMER;
I think if you got here, it means you have to exit to userspace to
update it of the new state. If you don't want to propagate a return
value from here, I think you should just not do anything an then later
compare timer->irq.level with whatever was last written to
run->kernel_timer_pending (which should be named something else than
pending).
> + }
> }
>
> /*
> @@ -197,7 +212,8 @@ static int kvm_timer_update_state(struct kvm_vcpu *vcpu)
> * because the guest would never see the interrupt. Instead wait
> * until we call this function from kvm_timer_flush_hwstate.
> */
> - if (!vgic_initialized(vcpu->kvm) || !timer->enabled)
> + if ((irqchip_in_kernel(vcpu->kvm) && !vgic_initialized(vcpu->kvm)) ||
> + !timer->enabled)
> return -ENODEV;
>
> if (kvm_timer_should_fire(vcpu) != timer->irq.level)
> @@ -248,15 +264,20 @@ void kvm_timer_unschedule(struct kvm_vcpu *vcpu)
> *
> * Check if the virtual timer has expired while we were running in the host,
> * and inject an interrupt if that was the case.
> + *
> + * Returns:
> + *
> + * 0 - success
> + * 1 - need exit to user space
this is opposite to all other exit-related APIs we have. Why not just
return -EINTR?
> */
> -void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
> +int kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
> {
> struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
> bool phys_active;
> int ret;
>
> if (kvm_timer_update_state(vcpu))
> - return;
> + return 0;
>
> /*
> * If we enter the guest with the virtual input level to the VGIC
> @@ -275,38 +296,61 @@ void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
> * to ensure that hardware interrupts from the timer triggers a guest
> * exit.
> */
> - phys_active = timer->irq.level ||
> - kvm_vgic_map_is_active(vcpu, timer->irq.irq);
> -
> - /*
> - * We want to avoid hitting the (re)distributor as much as
> - * possible, as this is a potentially expensive MMIO access
> - * (not to mention locks in the irq layer), and a solution for
> - * this is to cache the "active" state in memory.
> - *
> - * Things to consider: we cannot cache an "active set" state,
> - * because the HW can change this behind our back (it becomes
> - * "clear" in the HW). We must then restrict the caching to
> - * the "clear" state.
> - *
> - * The cache is invalidated on:
> - * - vcpu put, indicating that the HW cannot be trusted to be
> - * in a sane state on the next vcpu load,
> - * - any change in the interrupt state
> - *
> - * Usage conditions:
> - * - cached value is "active clear"
> - * - value to be programmed is "active clear"
> - */
> - if (timer->active_cleared_last && !phys_active)
> - return;
> -
> - ret = irq_set_irqchip_state(host_vtimer_irq,
> - IRQCHIP_STATE_ACTIVE,
> - phys_active);
> - WARN_ON(ret);
> + if (irqchip_in_kernel(vcpu->kvm)) {
> + phys_active = timer->irq.level ||
> + kvm_vgic_map_is_active(vcpu, timer->irq.irq);
> +
> + /*
> + * We want to avoid hitting the (re)distributor as much as
> + * possible, as this is a potentially expensive MMIO access
> + * (not to mention locks in the irq layer), and a solution for
> + * this is to cache the "active" state in memory.
> + *
> + * Things to consider: we cannot cache an "active set" state,
> + * because the HW can change this behind our back (it becomes
> + * "clear" in the HW). We must then restrict the caching to
> + * the "clear" state.
> + *
> + * The cache is invalidated on:
> + * - vcpu put, indicating that the HW cannot be trusted to be
> + * in a sane state on the next vcpu load,
> + * - any change in the interrupt state
> + *
> + * Usage conditions:
> + * - cached value is "active clear"
> + * - value to be programmed is "active clear"
> + */
> + if (timer->active_cleared_last && !phys_active)
> + return 0;
> +
> + ret = irq_set_irqchip_state(host_vtimer_irq,
> + IRQCHIP_STATE_ACTIVE,
> + phys_active);
> + WARN_ON(ret);
> + } else {
> + struct kvm_sync_regs *regs = &vcpu->run->s.regs;
> +
> + /*
> + * User space handles timer events, so we need to check whether
> + * its view of the world is in sync with ours.
> + */
> + if (regs->kernel_timer_pending != regs->user_timer_pending) {
> + /* Return to user space */
> + return 1;
> + }
Maybe I'm misunderstanding and user_timer_pending is just a cached
verison of what you said last, but as I said above, I think you can just
compare timer->irq.level with the last value the kvm_run struct, and if
something changed, you have to exit.
> +
> + /*
> + * As long as user space is aware that the timer is pending,
> + * we do not need to get new host timer events.
> + */
yes, correct, but I don't think this concept was clearly reflected in
your API text above.
> + if (timer->irq.level)
> + disable_percpu_irq(host_vtimer_irq);
> + else
> + enable_percpu_irq(host_vtimer_irq, 0);
> + }
could we move these two blocks into their own functions instead? That
would also give nice names to the huge chunk of complicated
functionality, e.g. flush_timer_state_to_user() and
flush_timer_state_to_vgic().
>
> timer->active_cleared_last = !phys_active;
> + return 0;
> }
>
> /**
> @@ -479,6 +523,10 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
> if (timer->enabled)
> return 0;
>
> + /* No need to route physical IRQs when we don't use the vgic */
> + if (!irqchip_in_kernel(vcpu->kvm))
> + goto no_vgic;
> +
> /*
> * Find the physical IRQ number corresponding to the host_vtimer_irq
> */
> @@ -502,6 +550,7 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
> if (ret)
> return ret;
>
> +no_vgic:
>
> /*
> * There is a potential race here between VCPUs starting for the first
> --
> 1.8.5.6
>
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH V6 3/5] PCI: thunder-pem: Allow to probe PEM-specific register range for ACPI case
From: Bjorn Helgaas @ 2016-09-22 22:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922183101.GA14510@localhost>
On Thu, Sep 22, 2016 at 01:31:01PM -0500, Bjorn Helgaas wrote:
> On Thu, Sep 22, 2016 at 01:44:46PM +0100, Lorenzo Pieralisi wrote:
> > On Thu, Sep 22, 2016 at 11:10:13AM +0000, Gabriele Paoloni wrote:
> > > Hi Lorenzo, Bjorn
> > >
> > > > -----Original Message-----
> > > > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi at arm.com]
> > > > Sent: 22 September 2016 10:50
> > > > To: Bjorn Helgaas
> > > > Cc: Ard Biesheuvel; Tomasz Nowicki; David Daney; Will Deacon; Catalin
> > > > Marinas; Rafael Wysocki; Arnd Bergmann; Hanjun Guo; Sinan Kaya;
> > > > Jayachandran C; Christopher Covington; Duc Dang; Robert Richter; Marcin
> > > > Wojtas; Liviu Dudau; Wangyijing; Mark Salter; linux-
> > > > pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Linaro ACPI
> > > > Mailman List; Jon Masters; Andrea Gallo; Jeremy Linton; liudongdong
> > > > (C); Gabriele Paoloni; Jeff Hugo; linux-acpi at vger.kernel.org; linux-
> > > > kernel at vger.kernel.org; Rafael J. Wysocki
> > > > Subject: Re: [PATCH V6 3/5] PCI: thunder-pem: Allow to probe PEM-
> > > > specific register range for ACPI case
> > > >
> > > > On Wed, Sep 21, 2016 at 01:04:57PM -0500, Bjorn Helgaas wrote:
> > > > > On Wed, Sep 21, 2016 at 03:05:49PM +0100, Lorenzo Pieralisi wrote:
> > > > > > On Tue, Sep 20, 2016 at 02:17:44PM -0500, Bjorn Helgaas wrote:
> > > > > > > On Tue, Sep 20, 2016 at 04:09:25PM +0100, Ard Biesheuvel wrote:
> > > > > >
> > > > > > [...]
> > > > > >
> > > > > > > > None of these platforms can be fixed entirely in software, and
> > > > given
> > > > > > > > that we will not be adding quirks for new broken hardware, we
> > > > should
> > > > > > > > ask ourselves whether having two versions of a quirk, i.e., one
> > > > for
> > > > > > > > broken hardware + currently shipping firmware, and one for the
> > > > same
> > > > > > > > broken hardware with fixed firmware is really an improvement
> > > > over what
> > > > > > > > has been proposed here.
> > > > > > >
> > > > > > > We're talking about two completely different types of quirks:
> > > > > > >
> > > > > > > 1) MCFG quirks to use memory-mapped config space that doesn't
> > > > quite
> > > > > > > conform to the ECAM model in the PCIe spec, and
> > > > > > >
> > > > > > > 2) Some yet-to-be-determined method to describe address space
> > > > > > > consumed by a bridge.
> > > > > > >
> > > > > > > The first two patches of this series are a nice implementation
> > > > for 1).
> > > > > > > The third patch (ThunderX-specific) is one possibility for 2),
> > > > but I
> > > > > > > don't like it because there's no way for generic software like
> > > > the
> > > > > > > ACPI core to discover these resources.
> > > > > >
> > > > > > Ok, so basically this means that to implement (2) we need to assign
> > > > > > some sort of _HID to these quirky PCI bridges (so that we know what
> > > > > > device they represent and we can retrieve their _CRS). I take from
> > > > > > this discussion that the goal is to make sure that all non-config
> > > > > > resources have to be declared through _CRS device objects, which is
> > > > > > fine but that requires a FW update (unless we can fabricate ACPI
> > > > > > devices and corresponding _CRS in the kernel whenever we match a
> > > > > > given MCFG table signature).
> > > > >
> > > > > All resources consumed by ACPI devices should be declared through
> > > > > _CRS. If you want to fabricate ACPI devices or _CRS via kernel
> > > > > quirks, that's fine with me. This could be triggered via MCFG
> > > > > signature, DMI info, host bridge _HID, etc.
> > > >
> > > > I think the PNP quirk approach + PNP0c02 resource put forward by Gab
> > > > is enough.
> > >
> > > Great thanks as we take a final decision I will ask Dogndgong to submit
> > > another RFC based on this approach
> > >
> > > >
> > > > > > We discussed this already and I think we should make a decision:
> > > > > >
> > > > > > http://lists.infradead.org/pipermail/linux-arm-kernel/2016-
> > > > March/414722.html
> > > > > >
> > > > > > > > > I'd like to step back and come up with some understanding of
> > > > how
> > > > > > > > > non-broken firmware *should* deal with this issue. Then, if
> > > > we *do*
> > > > > > > > > work around this particular broken firmware in the kernel, it
> > > > would be
> > > > > > > > > nice to do it in a way that fits in with that understanding.
> > > > > > > > >
> > > > > > > > > For example, if a companion ACPI device is the preferred
> > > > solution, an
> > > > > > > > > ACPI quirk could fabricate a device with the required
> > > > resources. That
> > > > > > > > > would address the problem closer to the source and make it
> > > > more likely
> > > > > > > > > that the rest of the system will work correctly: /proc/iomem
> > > > could
> > > > > > > > > make sense, things that look at _CRS generically would work
> > > > (e.g,
> > > > > > > > > /sys/, an admittedly hypothetical "lsacpi", etc.)
> > > > > > > > >
> > > > > > > > > Hard-coding stuff in drivers is a point solution that doesn't
> > > > provide
> > > > > > > > > any guidance for future platforms and makes it likely that
> > > > the hack
> > > > > > > > > will get copied into even more drivers.
> > > > > > > > >
> > > > > > > >
> > > > > > > > OK, I see. But the guidance for future platforms should be 'do
> > > > not
> > > > > > > > rely on quirks', and what I am arguing here is that the more we
> > > > polish
> > > > > > > > up this code and make it clean and reusable, the more likely it
> > > > is
> > > > > > > > that will end up getting abused by new broken hardware that we
> > > > set out
> > > > > > > > to reject entirely in the first place.
> > > > > > > >
> > > > > > > > So of course, if the quirk involves claiming resources, let's
> > > > make
> > > > > > > > sure that this occurs in the cleanest and most compliant way
> > > > possible.
> > > > > > > > But any factoring/reuse concerns other than for the current
> > > > crop of
> > > > > > > > broken hardware should be avoided imo.
> > > > > > >
> > > > > > > If future hardware is completely ECAM-compliant and we don't need
> > > > any
> > > > > > > more MCFG quirks, that would be great.
> > > > > >
> > > > > > Yes.
> > > > > >
> > > > > > > But we'll still need to describe that memory-mapped config space
> > > > > > > somewhere. If that's done with PNP0C02 or similar devices (as is
> > > > done
> > > > > > > on my x86 laptop), we'd be all set.
> > > > > >
> > > > > > I am not sure I understand what you mean here. Are you referring
> > > > > > to MCFG regions reported as PNP0c02 resources through its _CRS ?
> > > > >
> > > > > Yes. PCI Firmware Spec r3.0, Table 4-2, note 2 says address ranges
> > > > > reported via MCFG or _CBA should be reserved by _CRS of a PNP0C02
> > > > > device.
> > > >
> > > > Ok, that's agreed. It goes without saying that since you are quoting
> > > > the PCI spec, if FW fails to report MCFG regions in a PNP0c02 device
> > > > _CRS I will consider that a FW bug.
> > > >
> > > > > > IIUC PNP0C02 is a reservation mechanism, but it does not help us
> > > > > > associate its _CRS to a specific PCI host bridge instance, right ?
> > > > >
> > > > > Gab proposed a hierarchy that *would* associate a PNP0C02 device with
> > > > > a PCI bridge:
> > > > >
> > > > > Device (PCI1) {
> > > > > Name (_HID, "HISI0080") // PCI Express Root Bridge
> > > > > Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
> > > > > Method (_CRS, 0, Serialized) { // Root complex resources
> > > > (windows) }
> > > > > Device (RES0) {
> > > > > Name (_HID, "HISI0081") // HiSi PCIe RC config base address
> > > > > Name (_CID, "PNP0C02") // Motherboard reserved resource
> > > > > Name (_CRS, ResourceTemplate () { ... }
> > > > > }
> > > > > }
> > > > >
> > > > > That's a possibility. The PCI Firmware Spec suggests putting RES0 at
> > > > > the root (under \_SB), but I don't know why.
> > > > >
> > > > > Putting it at the root means we couldn't generically associate it
> > > > with
> > > > > a bridge, although I could imagine something like this:
> > > > >
> > > > > Device (RES1) {
> > > > > Name (_HID, "HISI0081") // HiSi PCIe RC config base address
> > > > > Name (_CID, "PNP0C02") // Motherboard reserved resource
> > > > > Name (_CRS, ResourceTemplate () { ... }
> > > > > Method (BRDG) { "PCI1" } // hand-wavy ASL
> > > > > }
> > > > > Device (PCI1) {
> > > > > Name (_HID, "HISI0080") // PCI Express Root Bridge
> > > > > Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
> > > > > Method (_CRS, 0, Serialized) { // Root complex resources
> > > > (windows) }
> > > > > }
> > > > >
> > > > > Where you could search PNP0C02 devices for a cookie that matched the
> > > > > host bridge.o
> > > >
> > > > Ok, I am fine with both and I think we are converging, but the way
> > > > to solve this problem has to be uniform for all ARM partners (and
> > > > not only ARM). Two points here:
> > > >
> > > > 1) Adding a device/subdevice allows people to add a _CRS reporting the
> > > > non-window bridge resources. Fine. It also allows people to chuck in
> > > > there all sorts of _DSD properties to describe their PCI host bridge
> > > > as it is done with DT properties (those _DSD can contain eg clocks
> > > > etc.), this may be tempting (so that they can reuse the same DT
> > > > driver and do not have to update their firmware) but I want to be
> > > > clear here: that must not happen. So, a subdevice with a _CRS to
> > > > report resources, yes, but it will stop there.
> > > > 2) It is unclear to me how to formalize the above. People should not
> > > > write FW by reading the PCI mailing list, so these guidelines have
> > > > to
> > > > be written, somehow. I do not want to standardize quirks, I want
> > > > to prevent random ACPI table content, which is different.
> > > > Should I report this to the ACPI spec working group ? If we do
> > > > not do that everyone will go solve this problem as they deem fit.
> > > >
> > >
> > > Do we really need to formalize this?
> > >
> > > As we discussed in the Linaro call at the moment we have few vendors
> > > that need quirks and we want to avoid promoting/accepting quirks for
> > > the future.
> > >
> > > At the time of the call I think we decided to informally accept a set
> > > of quirks for the current platforms and reject any other quirk coming
> > > after a certain date/kernel version (this to be decided).
> > >
> > > I am not sure if there is a way to document/formalize a temporary
> > > exception from the rule...
> >
> > - (1) will be enforced.
>
> I'm not sure it's necessary or possible to enforce a "no future
> quirks" rule. For one thing, there's already a pretty strong
> incentive to avoid quirks: if your hardware doesn't require quirks,
> it works with OSes already in the field.
>
> MCFG quirks allow us to use the generic ACPI pci_root.c driver even if
> the hardware doesn't support ECAM quite according to the spec.
>
> PNP0C02 usage is a workaround for the failure of the Consumer/Producer
> bit. PNP0C02 quirks compensate for firmware that doesn't describe
> resource usage accurately. It's possible the ACPI spec folks could
> come up with a better Consumer/Producer workaround, if that's needed.
> Apparently x86 hasn't needed it yet.
>
> If people add _DSD methods for clocks or whatnot, the hardware won't
> work with the generic pci_root.c driver, so there's already an
> incentive for avoiding them. x86 has managed without such methods;
> arm64 should be able to do the same.
Re-reading this, I'm afraid my response sounds a little dismissive,
and I feel like I'm missing some important information. So I
apologize if I missed your whole point, Lorenzo.
Bjorn
^ permalink raw reply
* [PATCH 0/4] ARM: at91: initial samx7 support
From: Alexandre Belloni @ 2016-09-22 22:22 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This series adds initial support for Atmel armv7m SoCs.
Most of the work has been done and tested by Andr?s, thanks!
Alexandre Belloni (1):
ARM: at91: handle CONFIG_PM for armv7m configurations
Szemz? Andr?s (3):
ARM: at91: Add armv7m support
ARM: dts: at91: add samx7 dtsi
ARM: at91: debug: add samx7 support
arch/arm/Kconfig.debug | 10 +
arch/arm/boot/dts/samx7.dtsi | 1166 ++++++++++++++++++++++++++++++++++++++
arch/arm/mach-at91/Kconfig | 15 +-
arch/arm/mach-at91/Makefile | 4 +-
arch/arm/mach-at91/Makefile.boot | 3 +
arch/arm/mach-at91/samx7.c | 72 +++
arch/arm/mach-at91/soc.h | 21 +
7 files changed, 1288 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boot/dts/samx7.dtsi
create mode 100644 arch/arm/mach-at91/Makefile.boot
create mode 100644 arch/arm/mach-at91/samx7.c
--
2.9.3
^ permalink raw reply
* [PATCH 1/4] ARM: at91: Add armv7m support
From: Alexandre Belloni @ 2016-09-22 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922222208.23798-1-alexandre.belloni@free-electrons.com>
From: Szemz? Andr?s <sza@esh.hu>
Add Atmel SAME70/SAMS70/SAMV71 SoC support and detection.
Signed-off-by: Szemz? Andr?s <sza@esh.hu>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Kconfig | 9 +++++-
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/Makefile.boot | 3 ++
arch/arm/mach-at91/samx7.c | 62 ++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-at91/soc.h | 21 ++++++++++++++
5 files changed, 95 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-at91/Makefile.boot
create mode 100644 arch/arm/mach-at91/samx7.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 5204395efda8..3ca2724a6ca6 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,12 +1,19 @@
menuconfig ARCH_AT91
bool "Atmel SoCs"
- depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7
+ depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
select COMMON_CLK_AT91
select GPIOLIB
select PINCTRL
select SOC_BUS
if ARCH_AT91
+config SOC_SAMX7
+ bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
+ select COMMON_CLK_AT91
+ select PINCTRL_AT91
+ help
+ Select this if you are using one of Atmel's SAMx7 family SoC.
+
config SOC_SAMA5D2
bool "SAMA5D2 family"
depends on ARCH_MULTI_V7
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c5bbf8bb8c0f..84956a18d604 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,6 +7,7 @@ obj-y := soc.o
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
obj-$(CONFIG_SOC_SAMA5) += sama5.o
+obj-$(CONFIG_SOC_SAMX7) += samx7.o
# Power Management
obj-$(CONFIG_PM) += pm.o
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
new file mode 100644
index 000000000000..eacfc3f5c33e
--- /dev/null
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -0,0 +1,3 @@
+# Empty file waiting for deletion once Makefile.boot isn't needed any more.
+# Patch waits for application at
+# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .
diff --git a/arch/arm/mach-at91/samx7.c b/arch/arm/mach-at91/samx7.c
new file mode 100644
index 000000000000..bd33bc56278e
--- /dev/null
+++ b/arch/arm/mach-at91/samx7.c
@@ -0,0 +1,62 @@
+/*
+ * Setup code for SAMx7
+ *
+ * Copyright (C) 2013 Atmel,
+ * 2016 Andras Szemzo <szemzo.andras@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/system_misc.h>
+#include "generic.h"
+#include "soc.h"
+
+static const struct at91_soc samx7_socs[] = {
+ AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,
+ "same70q21", "samx7"),
+ AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH,
+ "same70q20", "samx7"),
+ AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH,
+ "same70q19", "samx7"),
+ AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH,
+ "sams70q21", "samx7"),
+ AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH,
+ "sams70q20", "samx7"),
+ AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH,
+ "sams70q19", "samx7"),
+ AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH,
+ "samv71q21", "samx7"),
+ AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH,
+ "samv71q20", "samx7"),
+ AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH,
+ "samv71q19", "samx7"),
+ { /* sentinel */ },
+};
+
+static void __init samx7_dt_device_init(void)
+{
+ struct soc_device *soc;
+ struct device *soc_dev = NULL;
+
+ soc = at91_soc_init(samx7_socs);
+ if (soc)
+ soc_dev = soc_device_to_device(soc);
+
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
+}
+
+static const char *const samx7_dt_board_compat[] __initconst = {
+ "atmel,samx7",
+ NULL
+};
+
+DT_MACHINE_START(samx7_dt, "Atmel SAMx7")
+ .init_machine = samx7_dt_device_init,
+ .dt_compat = samx7_dt_board_compat,
+MACHINE_END
+
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 228efded5085..0f97e9c5da7e 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -88,4 +88,25 @@ at91_soc_init(const struct at91_soc *socs);
#define SAMA5D43_EXID_MATCH 0x00000003
#define SAMA5D44_EXID_MATCH 0x00000004
+#define SAME70Q21_CIDR_MATCH 0x21020e00
+#define SAME70Q21_EXID_MATCH 0x00000002
+#define SAME70Q20_CIDR_MATCH 0x21020c00
+#define SAME70Q20_EXID_MATCH 0x00000002
+#define SAME70Q19_CIDR_MATCH 0x210d0a00
+#define SAME70Q19_EXID_MATCH 0x00000002
+
+#define SAMS70Q21_CIDR_MATCH 0x21120e00
+#define SAMS70Q21_EXID_MATCH 0x00000002
+#define SAMS70Q20_CIDR_MATCH 0x21120c00
+#define SAMS70Q20_EXID_MATCH 0x00000002
+#define SAMS70Q19_CIDR_MATCH 0x211d0a00
+#define SAMS70Q19_EXID_MATCH 0x00000002
+
+#define SAMV71Q21_CIDR_MATCH 0x21220e00
+#define SAMV71Q21_EXID_MATCH 0x00000002
+#define SAMV71Q20_CIDR_MATCH 0x21220c00
+#define SAMV71Q20_EXID_MATCH 0x00000002
+#define SAMV71Q19_CIDR_MATCH 0x212d0a00
+#define SAMV71Q19_EXID_MATCH 0x00000002
+
#endif /* __AT91_SOC_H */
--
2.9.3
^ permalink raw reply related
* [PATCH 2/4] ARM: at91: handle CONFIG_PM for armv7m configurations
From: Alexandre Belloni @ 2016-09-22 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922222208.23798-1-alexandre.belloni@free-electrons.com>
There is currently no PM support for samx7 but the symbol can still be
selected. This avoids compilation issues.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Kconfig | 6 ++++++
arch/arm/mach-at91/Makefile | 3 +--
arch/arm/mach-at91/samx7.c | 10 ++++++++++
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 3ca2724a6ca6..df3b6efa888d 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -59,6 +59,7 @@ config SOC_AT91RM9200
bool "AT91RM9200"
depends on ARCH_MULTI_V4T
select ATMEL_AIC_IRQ
+ select ATMEL_PM if PM
select ATMEL_ST
select CPU_ARM920T
select HAVE_AT91_USB_CLK
@@ -73,6 +74,7 @@ config SOC_AT91SAM9
bool "AT91SAM9"
depends on ARCH_MULTI_V5
select ATMEL_AIC_IRQ
+ select ATMEL_PM if PM
select ATMEL_SDRAMC
select CPU_ARM926T
select HAVE_AT91_SMD
@@ -131,9 +133,13 @@ config SOC_SAM_V7
config SOC_SAMA5
bool
select ATMEL_AIC5_IRQ
+ select ATMEL_PM if PM
select ATMEL_SDRAMC
select MEMORY
select SOC_SAM_V7
select SRAM if PM
+config ATMEL_PM
+ bool
+
endif
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 84956a18d604..116691714bb8 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -10,8 +10,7 @@ obj-$(CONFIG_SOC_SAMA5) += sama5.o
obj-$(CONFIG_SOC_SAMX7) += samx7.o
# Power Management
-obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_PM) += pm_suspend.o
+obj-$(CONFIG_ATMEL_PM) += pm.o pm_suspend.o
ifeq ($(CONFIG_CPU_V7),y)
AFLAGS_pm_suspend.o := -march=armv7-a
diff --git a/arch/arm/mach-at91/samx7.c b/arch/arm/mach-at91/samx7.c
index bd33bc56278e..240f8cda79ee 100644
--- a/arch/arm/mach-at91/samx7.c
+++ b/arch/arm/mach-at91/samx7.c
@@ -16,6 +16,16 @@
#include "generic.h"
#include "soc.h"
+
+#ifdef CONFIG_PM
+/* This function has to be defined for various drivers that are using it */
+int at91_suspend_entering_slow_clock(void)
+{
+ return 0;
+}
+EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
+#endif
+
static const struct at91_soc samx7_socs[] = {
AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,
"same70q21", "samx7"),
--
2.9.3
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: at91: add samx7 dtsi
From: Alexandre Belloni @ 2016-09-22 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922222208.23798-1-alexandre.belloni@free-electrons.com>
From: Szemz? Andr?s <sza@esh.hu>
Add device tree support for Atmel samx7 SoCs family.
Signed-off-by: Szemz? Andr?s <sza@esh.hu>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/samx7.dtsi | 1166 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 1166 insertions(+)
create mode 100644 arch/arm/boot/dts/samx7.dtsi
diff --git a/arch/arm/boot/dts/samx7.dtsi b/arch/arm/boot/dts/samx7.dtsi
new file mode 100644
index 000000000000..fcef47c22413
--- /dev/null
+++ b/arch/arm/boot/dts/samx7.dtsi
@@ -0,0 +1,1166 @@
+/*
+ * samx7.dtsi - Device Tree Include file for SAMx7 family SoCs
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armv7-m.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Atmel SAMx7 family SoC";
+ compatible = "atmel,samx7";
+
+ aliases {
+ serial0 = &usart0;
+ serial1 = &usart1;
+ serial2 = &usart2;
+ serial3 = &uart0;
+ serial4 = &uart1;
+ serial5 = &uart2;
+ serial6 = &uart3;
+ serial7 = &uart4;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ gpio2 = &pioC;
+ gpio3 = &pioD;
+ gpio4 = &pioE;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ tcb0 = &tcb0;
+ tcb1 = &tcb1;
+ tcb2 = &tcb2;
+ tcb3 = &tcb3;
+ pwm0 = &pwm0;
+ pwm1 = &pwm1;
+ };
+
+ clocks {
+
+ clk_slck: clk-slck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ clk_mck: clk-mck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+ };
+
+ soc {
+
+ pmc: pmc at 0x400e0600 {
+ compatible = "atmel,at91sam9x5-pmc", "syscon";
+ reg = <0x400e0600 0x200>;
+ interrupts = <5>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk_mck>;
+
+ uart0_clk: uart0_clk {
+ #clock-cells = <0>;
+ reg = <7>;
+ };
+
+ uart1_clk: uart1_clk {
+ #clock-cells = <0>;
+ reg = <8>;
+ };
+
+ smc_clk: smc_clk {
+ #clock-cells = <0>;
+ reg = <9>;
+ };
+
+ pioA_clk: pioA_clk {
+ #clock-cells = <0>;
+ reg = <10>;
+ };
+
+ pioB_clk: pioB_clk {
+ #clock-cells = <0>;
+ reg = <11>;
+ };
+
+ pioC_clk: pioC_clk {
+ #clock-cells = <0>;
+ reg = <12>;
+ };
+
+ usart0_clk: usart0_clk {
+ #clock-cells = <0>;
+ reg = <13>;
+ };
+
+ usart1_clk: usart1_clk {
+ #clock-cells = <0>;
+ reg = <14>;
+ };
+
+ usart2_clk: usart2_clk {
+ #clock-cells = <0>;
+ reg = <15>;
+ };
+
+ pioD_clk: pioD_clk {
+ #clock-cells = <0>;
+ reg = <16>;
+ };
+
+ pioE_clk: pioE_clk {
+ #clock-cells = <0>;
+ reg = <17>;
+ };
+
+ mci_clk: mci_clk {
+ #clock-cells = <0>;
+ reg = <18>;
+ };
+
+ twi0_clk: twi0_clk {
+ #clock-cells = <0>;
+ reg = <19>;
+ };
+
+ twi1_clk: twi1_clk {
+ #clock-cells = <0>;
+ reg = <20>;
+ };
+
+ spi0_clk: spi0_clk {
+ #clock-cells = <0>;
+ reg = <21>;
+ };
+
+ ssc_clk: ssc_clk {
+ #clock-cells = <0>;
+ reg = <22>;
+ };
+
+ tcb0_clk: tcb0_clk {
+ #clock-cells = <0>;
+ reg = <23>;
+ };
+
+ tcb1_clk: tcb1_clk {
+ #clock-cells = <0>;
+ reg = <24>;
+ };
+
+ tcb2_clk: tcb2_clk {
+ #clock-cells = <0>;
+ reg = <25>;
+ };
+
+ tcb3_clk: tcb3_clk {
+ #clock-cells = <0>;
+ reg = <26>;
+ };
+
+ tcb4_clk: tcb4_clk {
+ #clock-cells = <0>;
+ reg = <27>;
+ };
+
+ tcb5_clk: tcb5_clk {
+ #clock-cells = <0>;
+ reg = <28>;
+ };
+
+ afec0_clk: afec0_clk {
+ #clock-cells = <0>;
+ reg = <29>;
+ };
+
+ dacc_clk: dacc_clk {
+ #clock-cells = <0>;
+ reg = <30>;
+ };
+
+ pwm0_clk: pwm0_clk {
+ #clock-cells = <0>;
+ reg = <31>;
+ };
+
+ icm_clk: cim_clk {
+ #clock-cells = <0>;
+ reg = <32>;
+ };
+
+ acc_clk: acc_clk {
+ #clock-cells = <0>;
+ reg = <33>;
+ };
+
+ usbhs_clk: usbhs_clk {
+ #clock-cells = <0>;
+ reg = <34>;
+ };
+
+ can0_clk: can0_clk {
+ #clock-cells = <0>;
+ reg = <35>;
+ };
+
+ can1_clk: can1_clk {
+ #clock-cells = <0>;
+ reg = <37>;
+ };
+
+ macb_clk: macb_clk {
+ #clock-cells = <0>;
+ reg = <39>;
+ };
+
+ afec1_clk: afec1_clk {
+ #clock-cells = <0>;
+ reg = <40>;
+ };
+
+ twi2_clk: twi2_clk {
+ #clock-cells = <0>;
+ reg = <41>;
+ };
+
+ spi1_clk: spi1_clk {
+ #clock-cells = <0>;
+ reg = <42>;
+ };
+
+ qspi_clk: qspi_clk {
+ #clock-cells = <0>;
+ reg = <43>;
+ };
+
+ uart2_clk: uart2_clk {
+ #clock-cells = <0>;
+ reg = <44>;
+ };
+
+ uart3_clk: uart3_clk {
+ #clock-cells = <0>;
+ reg = <45>;
+ };
+
+ uart4_clk: uart4_clk {
+ #clock-cells = <0>;
+ reg = <46>;
+ };
+
+ tcb6_clk: tcb6_clk {
+ #clock-cells = <0>;
+ reg = <47>;
+ };
+
+ tcb7_clk: tcb7_clk {
+ #clock-cells = <0>;
+ reg = <48>;
+ };
+
+ tcb8_clk: tcb8_clk {
+ #clock-cells = <0>;
+ reg = <49>;
+ };
+
+ tcb9_clk: tcb9_clk {
+ #clock-cells = <0>;
+ reg = <50>;
+ };
+
+ tcb10_clk: tcb10_clk {
+ #clock-cells = <0>;
+ reg = <51>;
+ };
+
+ tcb11_clk: tcb11_clk {
+ #clock-cells = <0>;
+ reg = <52>;
+ };
+
+ aes_clk: aes_clk {
+ #clock-cells = <0>;
+ reg = <56>;
+ };
+
+ trng_clk: trng_clk {
+ #clock-cells = <0>;
+ reg = <57>;
+ };
+
+ dma_clk: dma_clk {
+ #clock-cells = <0>;
+ reg = <58>;
+ };
+
+ isi_clk: isi_clk {
+ #clock-cells = <0>;
+ reg = <59>;
+ };
+
+ pwm1_clk: pwm1_clk {
+ #clock-cells = <0>;
+ reg = <60>;
+ };
+
+ i2sc0_clk: i2sc0_clk {
+ #clock-cells = <0>;
+ reg = <69>;
+ };
+
+ i2sc1_clk: i2sc1_clk {
+ #clock-cells = <0>;
+ reg = <70>;
+ };
+ };
+ };
+
+ pinctrl at 0x400e0e00 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
+ ranges = <0x400e0e00 0x400e0e00 0xa00>;
+
+ pioA: gpio at 0x400e0e00 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0x400e0e00 0x200>;
+ interrupts = <10>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ };
+
+ pioB: gpio at 0x400e1000 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0x400e1000 0x200>;
+ interrupts = <11>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ };
+
+ pioC: gpio at 0x400e1200 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0x400e1200 0x200>;
+ interrupts = <12>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ };
+
+ pioD: gpio at 0x400e1400 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0x400e1400 0x200>;
+ interrupts = <16>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioD_clk>;
+ };
+
+ pioE: gpio at 0x400e1600 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0x400e1600 0x200>;
+ interrupts = <17>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioE_clk>;
+ };
+
+ macb {
+ pinctrl_macb_rmii: macb_rmii-0 {
+ atmel,pins =
+ <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
+ AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
+ AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A */
+ AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
+ AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
+ AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD5 periph A */
+ AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A */
+ AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A */
+ AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A */
+ AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A */
+ >;
+ };
+ };
+
+ mmc {
+ pinctrl_mmc_clk_cmd_dat0: mmc_clk_cmd_dat0 {
+ atmel,pins =
+ <AT91_PIOA 25 AT91_PERIPH_D AT91_PINCTRL_NONE /* MCI_CK */
+ AT91_PIOA 28 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI_CDA */
+ AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI_DB0 */
+ >;
+ };
+ pinctrl_mmc_dat1_3: mmc_dat1_3 {
+ atmel,pins =
+ <AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI_DB1 */
+ AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI_DB2 */
+ AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI_DB3 */
+ >;
+ };
+ };
+
+ i2c_gpio0 {
+ pinctrl_i2c_gpio0: i2c_gpio0-0 {
+ atmel,pins =
+ <AT91_PIOA 3 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA3 gpio multidrive I2C0 data */
+ AT91_PIOA 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA4 gpio multidrive I2C0 clock */
+ };
+ };
+
+ i2c_gpio1 {
+ pinctrl_i2c_gpio1: i2c_gpio1-0 {
+ atmel,pins =
+ <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C1 data */
+ AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C1 clock */
+ };
+ };
+
+ i2c_gpio2 {
+ pinctrl_i2c_gpio2: i2c_gpio2-0 {
+ atmel,pins =
+ <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PD27 gpio multidrive I2C2 data */
+ AT91_PIOD 28 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PD28 gpio multidrive I2C2 clock */
+ };
+ };
+
+ i2c0 {
+ pinctrl_i2c0: i2c0-0 {
+ atmel,pins =
+ <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A I2C0 data */
+ AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A I2C0 clock */
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1: i2c1-0 {
+ atmel,pins =
+ <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A I2C1 data */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A I2C1 clock */
+ };
+ };
+
+ i2c2 {
+ pinctrl_i2c2: i2c2-0 {
+ atmel,pins =
+ <AT91_PIOD 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD27 periph C I2C2 data */
+ AT91_PIOD 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD28 periph C I2C2 clock */
+ };
+ };
+
+ qspi {
+ pinctrl_qspi: qspi-0 {
+ atmel,pins =
+ <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A QSCK */
+ AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A QCS */
+ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A QIO0 */
+ AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A QIO1 */
+ AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A QIO2 */
+ AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD31 periph A QIO3 */
+ >;
+ };
+ };
+
+ usart0 {
+ pinctrl_usart0: usart0-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PB0 periph C RXD */
+ AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PB1 periph C TXD */
+ >;
+ };
+
+ pinctrl_usart0_rts: usart0_rts-0 {
+ atmel,pins = <AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PB3 periph C */
+ };
+
+ pinctrl_usart0_cts: usart0_cts-0 {
+ atmel,pins = <AT91_PIOB 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PB2 periph C */
+ };
+ };
+
+ usart1 {
+ pinctrl_usart1: usart1-0 {
+ atmel,pins =
+ <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A RXD */
+ AT91_PIOB 4 AT91_PERIPH_D AT91_PINCTRL_PULL_UP /* PB4 periph D TXD */
+ >;
+ };
+
+ pinctrl_usart1_rts: usart1_rts-0 {
+ atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA24 periph A */
+ };
+
+ pinctrl_usart1_cts: usart1_cts-0 {
+ atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA25 periph A */
+ };
+ };
+
+ usart2 {
+ pinctrl_usart2: usart2-0 {
+ atmel,pins =
+ <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PD15 periph B RXD */
+ AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD16 periph B TXD */
+ >;
+ };
+
+ pinctrl_usart2_rts: usart2_rts-0 {
+ atmel,pins = <AT91_PIOD 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD18 periph B */
+ };
+
+ pinctrl_usart2_cts: usart2_cts-0 {
+ atmel,pins = <AT91_PIOD 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD19 periph B */
+ };
+ };
+
+ spi0 {
+ pinctrl_spi0: spi0-0 {
+ atmel,pins =
+ <AT91_PIOD 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI0_MISO */
+ AT91_PIOD 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI0_MOSI */
+ AT91_PIOD 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI0_SPCK */
+ >;
+ };
+ };
+
+ spi1 {
+ pinctrl_spi1: spi1-0 {
+ atmel,pins =
+ <AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* SPI1_MISO */
+ AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* SPI1_MOSI */
+ AT91_PIOC 24 AT91_PERIPH_C AT91_PINCTRL_NONE /* SPI1_SPCK */
+ >;
+ };
+ };
+
+ can0 {
+ pinctrl_can0_rx_tx: can0_rx_tx {
+ atmel,pins =
+ <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A RX */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A TX */
+ };
+ };
+
+ can1 {
+ pinctrl_can1_rx_tx: can1_rx_tx {
+ atmel,pins =
+ <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C RX */
+ AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC14 periph C TX */
+ };
+ };
+
+ pwm0 {
+ pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
+ atmel,pins =
+ <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh0_2: pwm0_pwmh0-2 {
+ atmel,pins =
+ <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh0_3: pwm0_pwmh0-3 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh0_4: pwm0_pwmh0-4 {
+ atmel,pins =
+ <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh0_5: pwm0_pwmh0-5 {
+ atmel,pins =
+ <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
+ atmel,pins =
+ <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
+ atmel,pins =
+ <AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
+ atmel,pins =
+ <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh1_3: pwm0_pwmh1-3 {
+ atmel,pins =
+ <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh1_4: pwm0_pwmh1-4 {
+ atmel,pins =
+ <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
+ atmel,pins =
+ <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
+ atmel,pins =
+ <AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh2_2: pwm0_pwmh2-2 {
+ atmel,pins =
+ <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh2_3: pwm0_pwmh2-3 {
+ atmel,pins =
+ <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh2_4: pwm0_pwmh2-4 {
+ atmel,pins =
+ <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
+ atmel,pins =
+ <AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
+ atmel,pins =
+ <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh3_2: pwm0_pwmh3-2 {
+ atmel,pins =
+ <AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh3_3: pwm0_pwmh3-3 {
+ atmel,pins =
+ <AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh3_4: pwm0_pwmh3-4 {
+ atmel,pins =
+ <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm0_pwmh3_5: pwm0_pwmh3-5 {
+ atmel,pins =
+ <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ pwm1 {
+ pinctrl_pwm1_pwmh0_0: pwm1_pwmh0-0 {
+ atmel,pins =
+ <AT91_PIOA 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm1_pwmh0_1: pwm1_pwmh0-1 {
+ atmel,pins =
+ <AT91_PIOD 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm1_pwmh1_0: pwm1_pwmh1-0 {
+ atmel,pins =
+ <AT91_PIOA 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm1_pwmh1_1: pwm1_pwmh1-1 {
+ atmel,pins =
+ <AT91_PIOD 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm1_pwmh2_0: pwm1_pwmh2-0 {
+ atmel,pins =
+ <AT91_PIOA 31 AT91_PERIPH_D AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm1_pwmh2_1: pwm1_pwmh2-1 {
+ atmel,pins =
+ <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm1_pwmh3_0: pwm1_pwmh3-0 {
+ atmel,pins =
+ <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_pwm1_pwmh3_1: pwm1_pwmh3-1 {
+ atmel,pins =
+ <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ ssc {
+ pinctrl_ssc_tx: ssc_tx {
+ atmel,pins =
+ <AT91_PIOB 1 AT91_PERIPH_D AT91_PINCTRL_NONE /* PB1 periph D TK */
+ AT91_PIOB 0 AT91_PERIPH_D AT91_PINCTRL_NONE /* PB0 periph D TF */
+ AT91_PIOD 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD26 periph B TD */
+ };
+
+ pinctrl_ssc_rx: ssc_rx {
+ atmel,pins =
+ <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A RK */
+ AT91_PIOD 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PD24 periph B RF */
+ AT91_PIOA 10 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA10 periph C RD */
+ };
+ };
+ };
+
+ chipid: chipid at 0x400e0940 {
+ compatible = "atmel,sama5d2-chipid";
+ reg = <0x400e0940 0xc0>;
+ };
+
+ rstc at 400e1800 {
+ compatible = "atmel,samx7-rstc";
+ reg = <0x400e1800 0x10>;
+ clocks = <&clk_slck>;
+ };
+
+ ssc: ssc at 40004000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0x40004000 0x4000>;
+ interrupts = <22>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(32))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(33))>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc_tx &pinctrl_ssc_rx>;
+ clocks = <&ssc_clk>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ pwm0: pwm at 40020000 {
+ compatible = "atmel,sama5d3-pwm";
+ reg = <0x40020000 0x4000>;
+ interrupts = <31>;
+ #pwm-cells = <3>;
+ clocks = <&pwm0_clk>;
+ status = "disabled";
+ };
+
+ pwm1: pwm at 4005c000 {
+ compatible = "atmel,sama5d3-pwm";
+ reg = <0x4005c000 0x4000>;
+ interrupts = <60>;
+ #pwm-cells = <3>;
+ clocks = <&pwm1_clk>;
+ status = "disabled";
+ };
+
+ watchdog at 400e1850 {
+ compatible = "atmel,at91sam9260-wdt";
+ reg = <0x400e1850 0x10>;
+ interrupts = <4>;
+ clocks = <&clk_slck>;
+ atmel,watchdog-type = "hardware";
+ atmel,reset-type = "all";
+ atmel,dbg-halt;
+ status = "disabled";
+ };
+
+ tcb0: timer at 4000c000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0x4000c000 0x4000>;
+ interrupts = <23 24 25>;
+ clocks = <&tcb0_clk>, <&tcb1_clk>, <&tcb2_clk>, <&clk_slck>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ tcb1: timer at 40010000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0x40010000 0x4000>;
+ interrupts = <26 27 28>;
+ clocks = <&tcb3_clk>, <&tcb4_clk>, <&tcb5_clk>, <&clk_slck>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ tcb2: timer at 40014000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0x40014000 0x4000>;
+ interrupts = <47 48 49>;
+ clocks = <&tcb6_clk>, <&tcb7_clk>, <&tcb8_clk>, <&clk_slck>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ tcb3: timer at 40054000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0x40054000 0x4000>;
+ interrupts = <50 51 52>;
+ clocks = <&tcb9_clk>, <&tcb10_clk>, <&tcb11_clk>, <&clk_slck>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ dma: dma-controller at 40078000 {
+ compatible = "atmel,sama5d4-dma";
+ reg = <0x40078000 0x4000>;
+ interrupts = <58>;
+ #dma-cells = <1>;
+ clocks = <&dma_clk>;
+ clock-names = "dma_clk";
+ status = "disabled";
+ };
+
+ qspi: qspi at 4007c000 {
+ compatible = "atmel,sama5d2-qspi";
+ reg = <0x4007c000 0x4000>, <0x80000000 0x20000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <43>;
+ clocks = <&qspi_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "disabled";
+ };
+
+ aes at 4006c000 {
+ compatible = "atmel,at91sam9g46-aes";
+ reg = <0x4006c000 0x4000>;
+ interrupts = <56>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(37))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(38))>;
+ dma-names = "tx", "rx";
+ clocks = <&aes_clk>;
+ clock-names = "aes_clk";
+ status = "disabled";
+ };
+
+ i2c0: i2c at 40018000 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x40018000 0x4000>;
+ interrupts = <19>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(14))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(15))>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi0_clk>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 4001c000 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x4001c000 0x4000>;
+ interrupts = <20>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(16))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(17))>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi1_clk>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 40060000 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x40060000 0x4000>;
+ interrupts = <41>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(18))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(19))>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi2_clk>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "disabled";
+ };
+
+ macb: ethernet at 40050000 {
+ compatible = "atmel,samx7-gem";
+ reg = <0x40050000 0x4000>;
+ interrupts = <39 66 67>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-mode = "rmii";
+ clocks = <&macb_clk>, <&macb_clk>;
+ clock-names = "hclk", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_phy_irq>;
+ status = "disabled";
+ };
+
+ mmc0: mmc at 40000000 {
+ compatible = "atmel,hsmci";
+ reg = <0x40000000 0x4000>;
+ interrupts = <18>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+ | AT91_XDMAC_DT_PERID(0))>;
+ dma-names = "rxtx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc_clk_cmd_dat0 &pinctrl_mmc_dat1_3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mci_clk>;
+ clock-names = "mci_clk";
+ status = "disabled";
+ };
+
+ spi0: spi at 40008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x40008000 0x4000>;
+ interrupts = <21>;
+ atmel,fifo-size = <0>;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(1))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(2))>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&spi0_clk>;
+ clock-names = "spi_clk";
+ status = "disabled";
+ };
+
+ trng at 4007000 {
+ compatible = "atmel,at91sam9g45-trng";
+ reg = <0x40070000 0x4000>;
+ interrupts = <57>;
+ clocks = <&trng_clk>;
+ status = "disabled";
+ };
+
+ rtc at 400e1860 {
+ compatible = "atmel,at91rm9200-rtc";
+ reg = <0x400e1860 0x30>;
+ interrupts = <2>;
+ clocks = <&clk_slck>;
+ status = "disabled";
+ };
+
+ usart0: serial at 40024000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x40024000 0x4000>;
+ interrupts = <13>;
+ clocks = <&usart0_clk>;
+ clock-names = "usart";
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(7))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(8))>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart0>;
+ status = "disabled";
+ };
+
+ usart1: serial at 40028000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x40028000 0x4000>;
+ interrupts = <14>;
+ clocks = <&usart1_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(9))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(10))>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart1>;
+ status = "disabled";
+ };
+
+ usart2: serial at 4002c000 {
+ compatible = "atmel,same70-usart";
+ reg = <0x4002c000 0x4000>;
+ interrupts = <15>;
+ clocks = <&usart2_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(12))>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart2>;
+ status = "disabled";
+ };
+
+ uart0: serial at 400e0800 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x400e0800 0x140>;
+ interrupts = <7>;
+ clocks = <&uart0_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(20))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(21))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart1: serial at 400e0a00 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x400e0a00 0x200>;
+ interrupts = <8>;
+ clocks = <&uart1_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(22))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(23))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart2: serial at 400e1a00 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x400e1a00 0x200>;
+ interrupts = <44>;
+ clocks = <&uart2_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(24))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(25))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart3: serial at 400e1c00 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x400e1c00 0x200>;
+ interrupts = <45>;
+ clocks = <&uart3_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(26))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(27))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart4: serial at 400e1e00 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x400e1e00 0x200>;
+ interrupts = <46>;
+ clocks = <&uart4_clk>;
+ clock-names = "usart";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ dmas = <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(28))>,
+ <&dma
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(29))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+};
--
2.9.3
^ permalink raw reply related
* [PATCH 4/4] ARM: at91: debug: add samx7 support
From: Alexandre Belloni @ 2016-09-22 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922222208.23798-1-alexandre.belloni@free-electrons.com>
From: Szemz? Andr?s <sza@esh.hu>
Add support for low level debugging on Atmel samx7.
Signed-off-by: Szemz? Andr?s <sza@esh.hu>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/Kconfig.debug | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index a9693b6987a6..d209d0d78820 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -145,6 +145,15 @@ choice
Say Y here if you want kernel low-level debugging support
on the USART3 port of sama5d4.
+ config DEBUG_AT91_SAMX7_USART1
+ bool "Kernel low-level debugging via SAMX7 USART1"
+ select DEBUG_AT91_UART
+ depends on SOC_SAMX7
+ help
+ Say Y here if you want the debug print routines to direct
+ their output to the USART1 port on SAMX7 based
+ machines.
+
config DEBUG_BCM2835
bool "Kernel low-level debugging on BCM2835 PL011 UART"
depends on ARCH_BCM2835 && ARCH_MULTI_V6
@@ -1479,6 +1488,7 @@ config DEBUG_UART_PHYS
default 0x3f201000 if DEBUG_BCM2836
default 0x3e000000 if DEBUG_BCM_KONA_UART
default 0x4000e400 if DEBUG_LL_UART_EFM32
+ default 0x40028000 if DEBUG_AT91_SAMX7_USART1
default 0x40081000 if DEBUG_LPC18XX_UART0
default 0x40090000 if DEBUG_LPC32XX
default 0x40100000 if DEBUG_PXA_UART1
--
2.9.3
^ permalink raw reply related
* [RFC PATCH 2/8] thread_info: allow custom in-task thread_info
From: Andy Lutomirski @ 2016-09-22 22:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921102827.GC18176@leverpostej>
On Sep 21, 2016 12:28 AM, "Mark Rutland" <mark.rutland@arm.com> wrote:
>
> Hi Andy,
>
> On Fri, Sep 16, 2016 at 08:11:14AM -0700, Andy Lutomirski wrote:
> > > On Thu, Sep 15, 2016 at 11:37:47AM -0700, Andy Lutomirski wrote:
> > > Just to check, what do you mean to happen with the flags field? Should
> > > that always be in the generic thread_info? e.g.
> > >
> > > struct thread_info {
> > > u32 flags;
> > > #ifdef arch_thread_info
> > > struct arch_thread_info arch_ti;
> > > #endif
> > > };
> >
> > Exactly. Possibly with a comment that using thread_struct should be
> > preferred and that arch_thread_info should be used only if some header
> > file requires access via current_thread_info() or task_thread_info().
>
> While fixing up these patches, I realised that I'm somewhat concerned by
> flags becoming a u32 (where it was previously an unsigned long for
> arm64).
>
> The generic {test,set,*}_ti_thread_flag() helpers use the usual bitops,
> which perform accesses of sizeof(unsigned long) at a time, and for arm64
> these need to be naturally-aligned.
>
> We happen to get that alignment from subsequent fields in task_struct
> and/or thread_info, and for arm64 we don't seem to have a problem with
> tearing, but it feels somewhat fragile, and leaves me uneasy.
>
> Looking at the git log, it seems that x86 also use unsigned long until
> commit affa219b60a11b32 ("x86: change thread_info's flag field back to
> 32 bits"), where if I'm reading correctly, this was done to get rid of
> unnecessary padding. With THREAD_INFO_IN_STACK, thread_info::flags is
> immediately followed by a long on x86, so we save no padding.
>
> Given all that, can we make the generic thread_info::flags an unsigned
> long, matching what the thread flag helpers implicitly assume?
>
Yes. Want to send the patch or should I?
--Andy
^ permalink raw reply
* [PATCH net-next] drivers: net: xgene: Fix MSS programming
From: Iyappan Subramanian @ 2016-09-22 22:47 UTC (permalink / raw)
To: linux-arm-kernel
Current driver programs static value of MSS in hardware register for TSO
offload engine to segment the TCP payload regardless the MSS value
provided by network stack.
This patch fixes this by programming hardware registers with the
stack provided MSS value.
Since the hardware has the limitation of having only 4 MSS registers,
this patch uses reference count of mss values being used.
Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Signed-off-by: Toan Le <toanle@apm.com>
---
drivers/net/ethernet/apm/xgene/xgene_enet_hw.h | 7 ++
drivers/net/ethernet/apm/xgene/xgene_enet_main.c | 90 ++++++++++++++++++-----
drivers/net/ethernet/apm/xgene/xgene_enet_main.h | 8 +-
drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c | 18 ++++-
4 files changed, 100 insertions(+), 23 deletions(-)
diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
index 8a8d055..8456337 100644
--- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
@@ -237,6 +237,8 @@ enum xgene_enet_rm {
#define TCPHDR_LEN 6
#define IPHDR_POS 6
#define IPHDR_LEN 6
+#define MSS_POS 20
+#define MSS_LEN 2
#define EC_POS 22 /* Enable checksum */
#define EC_LEN 1
#define ET_POS 23 /* Enable TSO */
@@ -253,6 +255,11 @@ enum xgene_enet_rm {
#define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS)
+#define TSO_MSS0_POS 0
+#define TSO_MSS0_LEN 14
+#define TSO_MSS1_POS 16
+#define TSO_MSS1_LEN 14
+
struct xgene_enet_raw_desc {
__le64 m0;
__le64 m1;
diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
index 522ba92..429f18f 100644
--- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
@@ -137,6 +137,7 @@ static irqreturn_t xgene_enet_rx_irq(const int irq, void *data)
static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
struct xgene_enet_raw_desc *raw_desc)
{
+ struct xgene_enet_pdata *pdata = netdev_priv(cp_ring->ndev);
struct sk_buff *skb;
struct device *dev;
skb_frag_t *frag;
@@ -144,6 +145,7 @@ static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
u16 skb_index;
u8 status;
int i, ret = 0;
+ u8 mss_index;
skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
skb = cp_ring->cp_skb[skb_index];
@@ -160,6 +162,13 @@ static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
DMA_TO_DEVICE);
}
+ if (GET_BIT(ET, le64_to_cpu(raw_desc->m3))) {
+ mss_index = GET_VAL(MSS, le64_to_cpu(raw_desc->m3));
+ spin_lock(&pdata->mss_lock);
+ pdata->mss_refcnt[mss_index]--;
+ spin_unlock(&pdata->mss_lock);
+ }
+
/* Checking for error */
status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
if (unlikely(status > 2)) {
@@ -178,15 +187,53 @@ static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
return ret;
}
-static u64 xgene_enet_work_msg(struct sk_buff *skb)
+static int xgene_enet_setup_mss(struct net_device *ndev, u32 mss)
+{
+ struct xgene_enet_pdata *pdata = netdev_priv(ndev);
+ bool mss_index_found = false;
+ int mss_index;
+ int i;
+
+ spin_lock(&pdata->mss_lock);
+
+ /* Reuse the slot if MSS matches */
+ for (i = 0; !mss_index_found && i < NUM_MSS_REG; i++) {
+ if (pdata->mss[i] == mss) {
+ pdata->mss_refcnt[i]++;
+ mss_index = i;
+ mss_index_found = true;
+ }
+ }
+
+ /* Overwrite the slot with ref_count = 0 */
+ for (i = 0; !mss_index_found && i < NUM_MSS_REG; i++) {
+ if (!pdata->mss_refcnt[i]) {
+ pdata->mss_refcnt[i]++;
+ pdata->mac_ops->set_mss(pdata, mss, i);
+ pdata->mss[i] = mss;
+ mss_index = i;
+ mss_index_found = true;
+ }
+ }
+
+ spin_unlock(&pdata->mss_lock);
+
+ /* No slots with ref_count = 0 available, return busy */
+ if (!mss_index_found)
+ return -EBUSY;
+
+ return mss_index;
+}
+
+static int xgene_enet_work_msg(struct sk_buff *skb, u64 *hopinfo)
{
struct net_device *ndev = skb->dev;
struct iphdr *iph;
u8 l3hlen = 0, l4hlen = 0;
u8 ethhdr, proto = 0, csum_enable = 0;
- u64 hopinfo = 0;
u32 hdr_len, mss = 0;
u32 i, len, nr_frags;
+ int mss_index;
ethhdr = xgene_enet_hdr_len(skb->data);
@@ -226,7 +273,11 @@ static u64 xgene_enet_work_msg(struct sk_buff *skb)
if (!mss || ((skb->len - hdr_len) <= mss))
goto out;
- hopinfo |= SET_BIT(ET);
+ mss_index = xgene_enet_setup_mss(ndev, mss);
+ if (unlikely(mss_index < 0))
+ return -EBUSY;
+
+ *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index);
}
} else if (iph->protocol == IPPROTO_UDP) {
l4hlen = UDP_HDR_SIZE;
@@ -234,15 +285,15 @@ static u64 xgene_enet_work_msg(struct sk_buff *skb)
}
out:
l3hlen = ip_hdrlen(skb) >> 2;
- hopinfo |= SET_VAL(TCPHDR, l4hlen) |
- SET_VAL(IPHDR, l3hlen) |
- SET_VAL(ETHHDR, ethhdr) |
- SET_VAL(EC, csum_enable) |
- SET_VAL(IS, proto) |
- SET_BIT(IC) |
- SET_BIT(TYPE_ETH_WORK_MESSAGE);
-
- return hopinfo;
+ *hopinfo |= SET_VAL(TCPHDR, l4hlen) |
+ SET_VAL(IPHDR, l3hlen) |
+ SET_VAL(ETHHDR, ethhdr) |
+ SET_VAL(EC, csum_enable) |
+ SET_VAL(IS, proto) |
+ SET_BIT(IC) |
+ SET_BIT(TYPE_ETH_WORK_MESSAGE);
+
+ return 0;
}
static u16 xgene_enet_encode_len(u16 len)
@@ -282,20 +333,22 @@ static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr;
skb_frag_t *frag;
u16 tail = tx_ring->tail;
- u64 hopinfo;
+ u64 hopinfo = 0;
u32 len, hw_len;
u8 ll = 0, nv = 0, idx = 0;
bool split = false;
u32 size, offset, ell_bytes = 0;
u32 i, fidx, nr_frags, count = 1;
+ int ret;
raw_desc = &tx_ring->raw_desc[tail];
tail = (tail + 1) & (tx_ring->slots - 1);
memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc));
- hopinfo = xgene_enet_work_msg(skb);
- if (!hopinfo)
- return -EINVAL;
+ ret = xgene_enet_work_msg(skb, &hopinfo);
+ if (ret)
+ return ret;
+
raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
hopinfo);
@@ -435,6 +488,9 @@ static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb,
return NETDEV_TX_OK;
count = xgene_enet_setup_tx_desc(tx_ring, skb);
+ if (count == -EBUSY)
+ return NETDEV_TX_BUSY;
+
if (count <= 0) {
dev_kfree_skb_any(skb);
return NETDEV_TX_OK;
@@ -1669,7 +1725,7 @@ static int xgene_enet_probe(struct platform_device *pdev)
if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
ndev->features |= NETIF_F_TSO;
- pdata->mss = XGENE_ENET_MSS;
+ spin_lock_init(&pdata->mss_lock);
}
ndev->hw_features = ndev->features;
diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.h b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
index 7735371..0cda58f 100644
--- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
@@ -47,7 +47,7 @@
#define NUM_PKT_BUF 64
#define NUM_BUFPOOL 32
#define MAX_EXP_BUFFS 256
-#define XGENE_ENET_MSS 1448
+#define NUM_MSS_REG 4
#define XGENE_MIN_ENET_FRAME_SIZE 60
#define XGENE_MAX_ENET_IRQ 16
@@ -143,7 +143,7 @@ struct xgene_mac_ops {
void (*rx_disable)(struct xgene_enet_pdata *pdata);
void (*set_speed)(struct xgene_enet_pdata *pdata);
void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
- void (*set_mss)(struct xgene_enet_pdata *pdata);
+ void (*set_mss)(struct xgene_enet_pdata *pdata, u16 mss, u8 index);
void (*link_state)(struct work_struct *work);
};
@@ -212,7 +212,9 @@ struct xgene_enet_pdata {
u8 eth_bufnum;
u8 bp_bufnum;
u16 ring_num;
- u32 mss;
+ u32 mss[NUM_MSS_REG];
+ u32 mss_refcnt[NUM_MSS_REG];
+ spinlock_t mss_lock; /* mss lock */
u8 tx_delay;
u8 rx_delay;
bool mdio_driver;
diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c
index 279ee27..6475f38 100644
--- a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c
+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c
@@ -232,9 +232,22 @@ static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata)
xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1);
}
-static void xgene_xgmac_set_mss(struct xgene_enet_pdata *pdata)
+static void xgene_xgmac_set_mss(struct xgene_enet_pdata *pdata,
+ u16 mss, u8 index)
{
- xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR, pdata->mss);
+ u8 offset;
+ u32 data;
+
+ offset = (index < 2) ? 0 : 4;
+ xgene_enet_rd_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, &data);
+
+ if (!(index & 0x1))
+ data = SET_VAL(TSO_MSS1, data >> TSO_MSS1_POS) |
+ SET_VAL(TSO_MSS0, mss);
+ else
+ data = SET_VAL(TSO_MSS1, mss) | SET_VAL(TSO_MSS0, data);
+
+ xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, data);
}
static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata)
@@ -258,7 +271,6 @@ static void xgene_xgmac_init(struct xgene_enet_pdata *pdata)
xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);
xgene_xgmac_set_mac_addr(pdata);
- xgene_xgmac_set_mss(pdata);
xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);
data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
--
1.9.1
^ permalink raw reply related
* [PATCH 1/2] power/reset: at91-reset: add samx7 support
From: Alexandre Belloni @ 2016-09-22 22:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Szemz? Andr?s <sza@esh.hu>
Add samx7 support. It is lacking a few bits and needs a new reset function.
Signed-off-by: Szemz? Andr?s <sza@esh.hu>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
drivers/power/reset/at91-reset.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c
index 1b5d450586d1..563722e64d7b 100644
--- a/drivers/power/reset/at91-reset.c
+++ b/drivers/power/reset/at91-reset.c
@@ -134,6 +134,15 @@ static int sama5d3_restart(struct notifier_block *this, unsigned long mode,
return NOTIFY_DONE;
}
+static int samx7_restart(struct notifier_block *this, unsigned long mode,
+ void *cmd)
+{
+ writel(cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PROCRST),
+ at91_rstc_base);
+
+ return NOTIFY_DONE;
+}
+
static void __init at91_reset_status(struct platform_device *pdev)
{
u32 reg = readl(at91_rstc_base + AT91_RSTC_SR);
@@ -173,6 +182,7 @@ static const struct of_device_id at91_reset_of_match[] = {
{ .compatible = "atmel,at91sam9260-rstc", .data = at91sam9260_restart },
{ .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
{ .compatible = "atmel,sama5d3-rstc", .data = sama5d3_restart },
+ { .compatible = "atmel,samx7-rstc", .data = samx7_restart },
{ /* sentinel */ }
};
--
2.9.3
^ permalink raw reply related
* [PATCH 2/2] power/reset: at91-reset: remove leftover platform_device_id
From: Alexandre Belloni @ 2016-09-22 22:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922225322.31677-1-alexandre.belloni@free-electrons.com>
commit eacd8d09db7f ("power/reset: at91-reset: remove useless
at91_reset_platform_probe()") removed non DT probe support but forgot to
remove the now useless id_table. Do that now.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
drivers/power/reset/at91-reset.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c
index 563722e64d7b..b8005cc18a54 100644
--- a/drivers/power/reset/at91-reset.c
+++ b/drivers/power/reset/at91-reset.c
@@ -247,19 +247,12 @@ static int __exit at91_reset_remove(struct platform_device *pdev)
return 0;
}
-static const struct platform_device_id at91_reset_plat_match[] = {
- { "at91-sam9260-reset", (unsigned long)at91sam9260_restart },
- { "at91-sam9g45-reset", (unsigned long)at91sam9g45_restart },
- { /* sentinel */ }
-};
-
static struct platform_driver at91_reset_driver = {
.remove = __exit_p(at91_reset_remove),
.driver = {
.name = "at91-reset",
.of_match_table = at91_reset_of_match,
},
- .id_table = at91_reset_plat_match,
};
module_platform_driver_probe(at91_reset_driver, at91_reset_probe);
--
2.9.3
^ permalink raw reply related
* [PATCH V6 0/5] ECAM quirks handling for ARM64 platforms
From: Bjorn Helgaas @ 2016-09-22 23:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <304377c6-554d-60ea-30df-006e557c7279@codeaurora.org>
On Wed, Sep 21, 2016 at 06:40:47PM -0400, Christopher Covington wrote:
> Hi Bjorn,
>
> On 09/21/2016 09:11 AM, Bjorn Helgaas wrote:
> > On Tue, Sep 20, 2016 at 09:15:14PM -0400, cov at codeaurora.org wrote:
>
> >>> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> >>> index eb14f74..bb3b8ad 100644
> >>> --- a/drivers/acpi/pci_mcfg.c
> >>> +++ b/drivers/acpi/pci_mcfg.c
> >>> @@ -42,86 +42,59 @@ struct mcfg_fixup {
> >>> struct resource cfgres;
> >>> };
> >>>
> >>> -#define MCFG_DOM_ANY (-1)
> >>
> >> Did you delete this because there were no current users, because you'd
> >> prefer users just use "-1", or for some other reason?
> >
> > I removed it because there were no users of it and, more importantly,
> > the code doesn't implement support for it.
>
> It looks like a stale "First match against PCI topology <domain:bus>..."
> comment remains.
Yep. I removed the comment since it's sort of obvious from the code.
I also renamed a few things and pulled the match out into a helper
function.
I also changed the dmesg note: I think the actual resource and the
name of the pci_ecam_ops is more interesting than the table IDs (which
I think are already elsewhere in the dmesg log).
Here's the incremental diff, which I can't really test:
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index 245b79f..0b36bc5 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -36,7 +36,7 @@ struct mcfg_fixup {
char oem_id[ACPI_OEM_ID_SIZE + 1];
char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
u32 oem_revision;
- u16 seg;
+ u16 segment;
struct resource bus_range;
struct pci_ecam_ops *ops;
struct resource cfgres;
@@ -102,30 +102,37 @@ static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
static u32 mcfg_oem_revision;
-static void pci_mcfg_match_quirks(struct acpi_pci_root *root,
+static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
+ struct resource *bus_range)
+{
+ if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
+ !memcmp(f->oem_table_id, mcfg_oem_table_id,
+ ACPI_OEM_TABLE_ID_SIZE) &&
+ f->oem_revision == mcfg_oem_revision &&
+ f->segment == segment &&
+ resource_contains(&f->bus_range, bus_range))
+ return 1;
+
+ return 0;
+}
+
+static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
struct resource *cfgres,
struct pci_ecam_ops **ecam_ops)
{
+ u16 segment = root->segment;
+ struct resource *bus_range = &root->secondary;
struct mcfg_fixup *f;
int i;
- /*
- * First match against PCI topology <domain:bus> then use OEM ID, OEM
- * table ID, and OEM revision from MCFG table standard header.
- */
for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
- if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
- !memcmp(f->oem_table_id, mcfg_oem_table_id,
- ACPI_OEM_TABLE_ID_SIZE) &&
- f->oem_revision == mcfg_oem_revision &&
- f->seg == root->segment &&
- resource_contains(&f->bus_range, &root->secondary)) {
+ if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
if (f->cfgres.start)
*cfgres = f->cfgres;
if (f->ops)
*ecam_ops = f->ops;
- dev_info(&root->device->dev, "Applying PCI MCFG quirks for %s %s rev: %d\n",
- f->oem_id, f->oem_table_id, f->oem_revision);
+ dev_info(&root->device->dev, "MCFG quirk: ECAM space for %pR at %pR with %ps\n",
+ bus_range, cfgres, *ecam_ops);
return;
}
}
@@ -173,7 +180,7 @@ skip_lookup:
* MCFG does not have it. Invalid CFG start address means MCFG
* firmware bug or we need another quirk in array.
*/
- pci_mcfg_match_quirks(root, &res, &ops);
+ pci_mcfg_apply_quirks(root, &res, &ops);
if (!res.start)
return -ENXIO;
^ permalink raw reply related
* [PATCH] PCI: rockchip: fix uninitialized variable use
From: Shawn Lin @ 2016-09-23 0:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922094018.2138640-1-arnd@arndb.de>
Hi Arnd,
? 2016/9/22 17:39, Arnd Bergmann ??:
> The newly added pcie-rockchip driver fails to initialize the
> io_size variable if the DT doesn't provide ranges for the PCI
> I/O space, as found by building it with -Wmaybe-uninitialized:
>
> drivers/pci/host/pcie-rockchip.c: In function 'rockchip_pcie_probe':
> drivers/pci/host/pcie-rockchip.c:1007:6: warning: 'io_size' may be used uninitialized in this function [-Wmaybe-uninitialized]
>
Seems like we miss this when refactoring the code a bit.
Thanks for fixing it.
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
> This adds an appropriate initialization immediately in front of
> the loop, so the io_size is zero as expected afterwards for that
> case.
>
> Fixes: abe17181b16f ("PCI: rockchip: Add Rockchip PCIe controller support")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> drivers/pci/host/pcie-rockchip.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index c3593e633ccd..8bedc1e1ef80 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -1078,6 +1078,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
> goto err_vpcie;
>
> /* Get the I/O and memory ranges from DT */
> + io_size = 0;
> resource_list_for_each_entry(win, &res) {
> switch (resource_type(win->res)) {
> case IORESOURCE_IO:
>
--
Best Regards
Shawn Lin
^ permalink raw reply
* [PATCH] clk: zx296718: register driver earlier with core_initcall
From: Shawn Guo @ 2016-09-23 1:45 UTC (permalink / raw)
To: linux-arm-kernel
Clock driver should be registered with an earlier initcall than
module_init which is used by most of client device drivers. Otherwise,
probing of these client drivers will likely be deferred due to that
calls into clk API will return -EPROBE_DEFER.
Deferred probing is not a problem for most subsystems, but could bring
some side effect for particular subsystem, like display. On ZX296718
platform, we get Linux logo and boot log lost from display device, just
because the DRM/KMS driver gets -EPROBE_DEFER from devm_clk_get() call.
Let's use core_initcall (qcom and a few other clk drivers use that) for
driver registration to avoid those unnecessary -EPROBE_DEFER and get rid
of the side effect with ZX296718 display system.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/clk/zte/clk-zx296718.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index c7716c17f302..707d62956e9b 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -917,4 +917,8 @@ static int zx_clkc_probe(struct platform_device *pdev)
},
};
-builtin_platform_driver(zx_clk_driver);
+static int __init zx_clk_init(void)
+{
+ return platform_driver_register(&zx_clk_driver);
+}
+core_initcall(zx_clk_init);
--
1.9.1
^ permalink raw reply related
* [PATCH] clocksource/drivers/ti-32k: Prevent ftrace recursion
From: Jisheng Zhang @ 2016-09-23 2:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.20.1609221555590.5599@nanos>
Hi Thomas,
On Thu, 22 Sep 2016 15:58:03 +0200 Thomas Gleixner wrote:
> On Thu, 22 Sep 2016, Jisheng Zhang wrote:
>
> > Currently ti-32k can be used as a scheduler clock. We properly marked
> > omap_32k_read_sched_clock() as notrace but we then call another
> > function ti_32k_read_cycles() that _wasn't_ notrace.
> >
> > Having a traceable function in the sched_clock() path leads to a
> > recursion within ftrace and a kernel crash.
>
> Kernel crash? Doesn't ftrace core prevent recursion?
a recent similar issue:
http://www.spinics.net/lists/arm-kernel/msg533480.html
Thanks,
Jisheng
^ permalink raw reply
* [PATCH 1/2] armv8: aarch32: Execute 32-bit Linux for LayerScape platforms
From: Alison Wang @ 2016-09-23 2:19 UTC (permalink / raw)
To: linux-arm-kernel
The ARMv8 architecture supports:
1. 64-bit execution state, AArch64.
2. 32-bit execution state, AArch32, that is compatible with previous
versions of the ARM architecture.
LayerScape platforms are compliant with ARMv8 architecture. This patch
is to support running 32-bit Linux kernel for LayerScape platforms.
Verified on LayerScape LS1043ARDB, LS1012ARDB, LS1046ARDB boards.
Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
---
arch/arm/Kconfig | 9 +++++++++
arch/arm/mach-imx/Kconfig | 14 ++++++++++++++
arch/arm/mach-imx/Makefile | 4 +++-
arch/arm/mach-imx/mach-layerscape.c | 23 +++++++++++++++++++++++
4 files changed, 49 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-imx/mach-layerscape.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f0c8068..e8d470e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -294,6 +294,15 @@ config PGTABLE_LEVELS
default 3 if ARM_LPAE
default 2
+config ARCH_AARCH32_ES_SUPPORT
+ def_bool n
+ help
+ The ARMv8 architecture supports 64-bit execution state, AArch64
+ and 32-bit execution state, AArch32, that is compatible with
+ previous versions of the ARM architecture.
+
+ Enable AArch32 execution state support for ARMv8 architecture.
+
source "init/Kconfig"
source "kernel/Kconfig.freezer"
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0ac05a0..fda4f5f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -549,6 +549,20 @@ config SOC_LS1021A
help
This enables support for Freescale LS1021A processor.
+config ARCH_LAYERSCAPE_AARCH32
+ bool "Freescale Layerscape SoC AArch32 ES support"
+ select ARCH_AARCH32_ES_SUPPORT
+ select ARM_AMBA
+ select ARM_GIC
+ select ARM_ARCH_TIMER
+ select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
+ select PCI_LAYERSCAPE if PCI
+ select PCI_DOMAINS if PCI
+
+ help
+ This enables support for Freescale Layerscape SoC family in
+ in AArch32 execution state.
+
endif
comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 737450f..7ded4fa 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -69,7 +69,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
-ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A)$(CONFIG_ARCH_LAYERSCAPE_AARCH32),)
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
@@ -96,4 +96,6 @@ obj-$(CONFIG_SOC_VF610) += mach-vf610.o
obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
+obj-$(CONFIG_ARCH_LAYERSCAPE_AARCH32) += mach-layerscape.o
+
obj-y += devices/
diff --git a/arch/arm/mach-imx/mach-layerscape.c b/arch/arm/mach-imx/mach-layerscape.c
new file mode 100644
index 0000000..acfb2a2
--- /dev/null
+++ b/arch/arm/mach-imx/mach-layerscape.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const char * const layerscape_dt_compat[] __initconst = {
+ "fsl,ls1012a",
+ "fsl,ls1043a",
+ "fsl,ls1046a",
+ NULL,
+};
+
+DT_MACHINE_START(LAYERSCAPE_AARCH32, "Freescale LAYERSCAPE")
+ .dt_compat = layerscape_dt_compat,
+MACHINE_END
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 2/2] armv8: aarch32: Add SMP support for 32-bit Linux kernel
From: Alison Wang @ 2016-09-23 2:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474597146-33312-1-git-send-email-b18965@freescale.com>
The patch adds SMP support for running 32-bit Linux kernel for
Layerscape platforms. Spin-table method is used for SMP support.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
---
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/mach-layerscape.c | 1 +
arch/arm/mach-imx/platsmp.c | 49 +++++++++++++++++++++++++++++++++++++
3 files changed, 51 insertions(+)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c4436d9..6362790 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -152,5 +152,6 @@ static inline void imx_init_l2cache(void) {}
extern const struct smp_operations imx_smp_ops;
extern const struct smp_operations ls1021a_smp_ops;
+extern const struct smp_operations layerscape_smp_ops;
#endif
diff --git a/arch/arm/mach-imx/mach-layerscape.c b/arch/arm/mach-imx/mach-layerscape.c
index acfb2a2..109d488 100644
--- a/arch/arm/mach-imx/mach-layerscape.c
+++ b/arch/arm/mach-imx/mach-layerscape.c
@@ -19,5 +19,6 @@ static const char * const layerscape_dt_compat[] __initconst = {
};
DT_MACHINE_START(LAYERSCAPE_AARCH32, "Freescale LAYERSCAPE")
+ .smp = smp_ops(layerscape_smp_ops),
.dt_compat = layerscape_dt_compat,
MACHINE_END
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 711dbbd..e2fc7a2 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -14,6 +14,7 @@
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/smp.h>
+#include <linux/types.h>
#include <asm/cacheflush.h>
#include <asm/page.h>
@@ -26,6 +27,8 @@
u32 g_diag_reg;
static void __iomem *scu_base;
+static u64 cpu_release_addr[NR_CPUS];
+
static struct map_desc scu_io_desc __initdata = {
/* .virtual and .pfn are run-time assigned */
.length = SZ_4K,
@@ -127,3 +130,49 @@ const struct smp_operations ls1021a_smp_ops __initconst = {
.smp_prepare_cpus = ls1021a_smp_prepare_cpus,
.smp_boot_secondary = ls1021a_boot_secondary,
};
+
+static int layerscape_smp_boot_secondary(unsigned int cpu,
+ struct task_struct *idle)
+{
+ u32 secondary_startup_phys;
+ __le32 __iomem *release_addr;
+
+ secondary_startup_phys = virt_to_phys(secondary_startup);
+
+ release_addr = memremap((u32)cpu_release_addr[cpu], sizeof(u64),
+ MEMREMAP_WB);
+ if (!release_addr)
+ return -ENOMEM;
+
+ writel_relaxed(secondary_startup_phys, release_addr);
+ writel_relaxed(0, release_addr + 1);
+ __cpuc_flush_dcache_area((__force void *)release_addr,
+ sizeof(u64));
+
+ sev();
+
+ iounmap(release_addr);
+
+ return 0;
+}
+
+static void layerscape_smp_init_cpus(void)
+{
+ struct device_node *dnt = NULL;
+ unsigned int cpu = 0;
+
+ while ((dnt = of_find_node_by_type(dnt, "cpu"))) {
+ if (of_property_read_u64(dnt, "cpu-release-addr",
+ &cpu_release_addr[cpu])) {
+ pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
+ cpu);
+ }
+
+ cpu++;
+ }
+}
+
+const struct smp_operations layerscape_smp_ops __initconst = {
+ .smp_init_cpus = layerscape_smp_init_cpus,
+ .smp_boot_secondary = layerscape_smp_boot_secondary,
+};
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH] clocksource/drivers/ti-32k: Prevent ftrace recursion
From: Steven Rostedt @ 2016-09-23 2:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160923100431.6cf2c88f@xhacker>
On Fri, 23 Sep 2016 10:04:31 +0800
Jisheng Zhang <jszhang@marvell.com> wrote:
> Hi Thomas,
>
> On Thu, 22 Sep 2016 15:58:03 +0200 Thomas Gleixner wrote:
>
> > On Thu, 22 Sep 2016, Jisheng Zhang wrote:
> >
> > > Currently ti-32k can be used as a scheduler clock. We properly marked
> > > omap_32k_read_sched_clock() as notrace but we then call another
> > > function ti_32k_read_cycles() that _wasn't_ notrace.
> > >
> > > Having a traceable function in the sched_clock() path leads to a
> > > recursion within ftrace and a kernel crash.
> >
> > Kernel crash? Doesn't ftrace core prevent recursion?
>
> a recent similar issue:
>
> http://www.spinics.net/lists/arm-kernel/msg533480.html
Right. But Thomas brought up recursion detection. And I said that would
be the fix, but now thinking about it, I've updated the recursion
protection so that timer issues should not cause a crash.
I'd like to know more, as this appears to be mostly arm related.
-- Steve
^ permalink raw reply
* [PATCH] clocksource/drivers/ti-32k: Prevent ftrace recursion
From: Jisheng Zhang @ 2016-09-23 2:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922224514.696ae61b@gandalf.local.home>
On Thu, 22 Sep 2016 22:45:14 -0400 Steven Rostedt wrote:
> On Fri, 23 Sep 2016 10:04:31 +0800
> Jisheng Zhang <jszhang@marvell.com> wrote:
>
> > Hi Thomas,
> >
> > On Thu, 22 Sep 2016 15:58:03 +0200 Thomas Gleixner wrote:
> >
> > > On Thu, 22 Sep 2016, Jisheng Zhang wrote:
> > >
> > > > Currently ti-32k can be used as a scheduler clock. We properly marked
> > > > omap_32k_read_sched_clock() as notrace but we then call another
> > > > function ti_32k_read_cycles() that _wasn't_ notrace.
> > > >
> > > > Having a traceable function in the sched_clock() path leads to a
> > > > recursion within ftrace and a kernel crash.
> > >
> > > Kernel crash? Doesn't ftrace core prevent recursion?
> >
> > a recent similar issue:
> >
> > http://www.spinics.net/lists/arm-kernel/msg533480.html
>
> Right. But Thomas brought up recursion detection. And I said that would
> be the fix, but now thinking about it, I've updated the recursion
> protection so that timer issues should not cause a crash.
>
Got it. Thanks for the clarification
^ permalink raw reply
* [PATCH 5/5] arm64: Add uprobe support
From: Pratyush Anand @ 2016-09-23 4:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922165030.GA27704@e104818-lin.cambridge.arm.com>
On 22/09/2016:05:50:30 PM, Catalin Marinas wrote:
> On Thu, Sep 22, 2016 at 08:53:28AM +0530, Pratyush Anand wrote:
> > On 21/09/2016:06:04:04 PM, Catalin Marinas wrote:
> > > On Wed, Sep 21, 2016 at 04:30:47PM +0530, Pratyush Anand wrote:
> > > > On 20/09/2016:05:59:46 PM, Catalin Marinas wrote:
> > > > > > +int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
> > > > > > + unsigned long addr)
> > > > > > +{
> > > > > > + probe_opcode_t insn;
> > > > > > +
> > > > > > + /* TODO: Currently we do not support AARCH32 instruction probing */
> > > > >
> > > > > Is there a way to check (not necessarily in this file) that we don't
> > > > > probe 32-bit tasks?
> > > >
> > > > - Well, I do not have complete idea about it that, how it can be done. I think
> > > > we can not check that just by looking a single bit in an instruction.
> > > > My understanding is that, we can only know about it when we are executing the
> > > > instruction, by reading pstate, but that would not be useful for uprobe
> > > > instruction analysis.
> > > >
> > > > I hope, instruction encoding for aarch32 and aarch64 are different, and by
> > > > analyzing for all types of aarch32 instructions, we will be able to decide
> > > > that whether instruction is 32 bit trace-able or not. Accordingly, we can use
> > > > either BRK or BKPT instruction for breakpoint generation.
> > >
> > > We may have some unrelated instruction encoding overlapping but I
> > > haven't checked. I was more thinking about whether we know which task is
> > > being probed and check is_compat_task() or maybe using
> > > compat_user_mode(regs).
> >
> > I had thought of this, but problem is that we might not have task in existence
> > when we enable uprobes. For example: Lets say we are inserting a trace probe at
> > offset 0x690 in a executable binary.
> >
> > echo "p test:0x690" > /sys/kernel/debug/tracing/uprobe_events
> > echo 1 > /sys/kernel/debug/tracing/events/uprobes/enable
> >
> > In the 'enable' step, it is decided that whether instruction is traceable or
> > not.
> >
> > (1) But at this point 'test' executable might not be running.
Let me correct myself first here. When executable is not running, then,
arch_uprobe_analyze_insn() is not called while uprobes enabling (ie writing '1'
to 'enable'). In that case, it is called when binary is executed and task is
created.
> > (2) Even if it is running, is_compat_task() or compat_user_mode() might not be
> > usable, as they work with 'current' task.
>
> What I find strange is that uprobes allows you to insert a breakpoint
> instruction that's not even compatible with the task (so it would
> SIGILL rather than generate a debug exception).
>
> > What I was thinking that, let it go with 'TODO' as of now.
>
> Only that I don't have any guarantee that someone is going to fix it ;).
>
> As a quick workaround you could check mm->task_size > TASK_SIZE_32 in
> the arch_uprobe_analyze_insn() function.
It would be doable. TASK_SIZE_32 is defined only for COMPAT. So, may be I can
return -EINVAL when mm->task_size < TASK_SIZE_64.
Thanks for your input.
~Pratyush
^ permalink raw reply
* [PATCH v2 2/2] cpufreq: ti: Add cpufreq driver to determine available OPPs at runtime
From: Viresh Kumar @ 2016-09-23 5:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <57E2E0BE.3070206@ti.com>
On 21-09-16, 14:34, Dave Gerlach wrote:
> Viresh,
> On 09/07/2016 10:39 PM, Viresh Kumar wrote:
> >On 07-09-16, 10:04, Dave Gerlach wrote:
> >>>>+static const struct of_device_id ti_cpufreq_of_match[] = {
> >>>>+ { .compatible = "operating-points-v2-ti-am3352-cpu",
> >>>>+ .data = &am3x_soc_data, },
> >>>>+ { .compatible = "operating-points-v2-ti-am4372-cpu",
> >>>>+ .data = &am4x_soc_data, },
> >>>>+ { .compatible = "operating-points-v2-ti-dra7-cpu",
> >>>>+ .data = &dra7_soc_data },
> >>>
> >>>You should be using your SoC compatible strings here. OPP compatible
> >>>property isn't supposed to be (mis)used for this purpose.
> >>>
> >>
> >>Referring to my comments in patch 1, what if we end up changing the bindings
> >>based on DT maintainer comments? We will have these compatible strings, and
> >>at that point is it acceptable to match against them? Or is it still better
> >>to match to SoC compatibles? I think it makes sense to just probe against
> >>these.
> >
> >But even then I think these are not correct. You should have added a
> >single compatible string: operating-points-v2-ti-cpu.
> >
> >As the properties will stay the same across machines. And then you
> >need to use SoC strings here.
> >
>
> Are you opposed to moving _of_get_opp_desc_node from
> drivers/base/power/opp/opp.h to include/linux/pm_opp.h and renaming it
> appropriately?
I am not opposed to that, but ...
> If I move the ti properties out of the cpu node, as discussed in patch 1 of
> this series, and into the operating-points-v2 table, I need a way to get the
> operating-points-v2 device node and I think it makes sense to reuse this as
> it is what the opp framework uses internally to parse the phandle to the opp
> table.
I am not sure if those registers belong to the OPP bindings. What are those
registers really? What all can be read from them? Why shouldn't they be present
as a separate node in DT on the respective bus? Look at how it is done for
sti-cpufreq driver.
--
viresh
^ permalink raw reply
* [GIT PULL 00/15] perf/core improvements and fixes
From: Ingo Molnar @ 2016-09-23 5:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474578779-14095-1-git-send-email-acme@kernel.org>
* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
> From: Arnaldo Carvalho de Melo <acme@redhat.com>
>
> Hi Ingo,
>
> Please consider pulling,
>
> - Arnaldo
>
> The following changes since commit 89f1c2c59c4aef8e26edbc7db5175e6ffb0e9ec7:
>
> Merge tag 'perf-core-for-mingo-20160920' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2016-09-20 23:32:02 +0200)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-20160922
>
> for you to fetch changes up to 2d831454140f28fa643b78deede4511b9e2c9e5f:
>
> perf hists: Make hists__fprintf_headers function global (2016-09-22 13:08:59 -0300)
>
> ----------------------------------------------------------------
> perf/core improvements:
>
> New features:
>
> - Add support for interacting with Coresight PMU ETMs/PTMs, that are IP blocks
> to perform hardware assisted tracing on a ARM CPU core (Mathieu Poirier)
>
> Infrastructure:
>
> - Histogram prep work for the upcoming c2c tool (Jiri Olsa)
>
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
>
> ----------------------------------------------------------------
> Jiri Olsa (9):
> perf evsel: Remove superfluous initialization of weight
> perf hists: Use bigger buffer for stdio headers
> perf hists: Add __hist_entry__snprintf function
> perf tools: Make reset_dimensions global
> perf tools: Make output_field_add and sort_dimension__add global
> perf tools: Make several sorting functions global
> perf tools: Make several display functions global
> perf hists: Make __hist_entry__snprintf function global
> perf hists: Make hists__fprintf_headers function global
>
> Mathieu Poirier (6):
> perf tools: Confine __get_cpuid() to x86 architecture
> perf tools: Make coresight PMU listable
> perf tools: Add coresight etm PMU record capabilities
> perf pmu: Push configuration down to PMU driver
> perf tools: Add PMU configuration to tools
> perf tools: Add sink configuration for cs_etm PMU
>
> MAINTAINERS | 5 +
> tools/perf/Makefile.config | 11 +-
> tools/perf/arch/arm/util/Build | 2 +
> tools/perf/arch/arm/util/auxtrace.c | 54 ++++
> tools/perf/arch/arm/util/cs-etm.c | 617 ++++++++++++++++++++++++++++++++++++
> tools/perf/arch/arm/util/cs-etm.h | 26 ++
> tools/perf/arch/arm/util/pmu.c | 36 +++
> tools/perf/arch/arm64/util/Build | 4 +
> tools/perf/builtin-record.c | 10 +
> tools/perf/builtin-stat.c | 9 +
> tools/perf/builtin-top.c | 13 +
> tools/perf/ui/browsers/hists.c | 2 +-
> tools/perf/ui/hist.c | 2 +-
> tools/perf/ui/stdio/hist.c | 14 +-
> tools/perf/util/Build | 1 +
> tools/perf/util/auxtrace.c | 1 +
> tools/perf/util/auxtrace.h | 1 +
> tools/perf/util/cs-etm.h | 74 +++++
> tools/perf/util/drv_configs.c | 77 +++++
> tools/perf/util/drv_configs.h | 26 ++
> tools/perf/util/evsel.c | 2 -
> tools/perf/util/hist.h | 5 +
> tools/perf/util/pmu.h | 2 +
> tools/perf/util/sort.c | 16 +-
> tools/perf/util/sort.h | 11 +
> 25 files changed, 1001 insertions(+), 20 deletions(-)
> create mode 100644 tools/perf/arch/arm/util/auxtrace.c
> create mode 100644 tools/perf/arch/arm/util/cs-etm.c
> create mode 100644 tools/perf/arch/arm/util/cs-etm.h
> create mode 100644 tools/perf/arch/arm/util/pmu.c
> create mode 100644 tools/perf/util/cs-etm.h
> create mode 100644 tools/perf/util/drv_configs.c
> create mode 100644 tools/perf/util/drv_configs.h
>
> [root at zoo ~]# time dm
> 1 73.911 alpine:3.4: Ok
> 2 26.890 android-ndk:r12b-arm: Ok
> 3 77.833 archlinux:latest: Ok
> 4 40.814 centos:5: Ok
> 5 64.151 centos:6: Ok
> 6 75.720 centos:7: Ok
> 7 68.960 debian:7: Ok
> 8 75.606 debian:8: Ok
> 9 75.127 fedora:20: Ok
> 10 80.186 fedora:21: Ok
> 11 80.157 fedora:22: Ok
> 12 83.273 fedora:23: Ok
> 13 91.566 fedora:24: Ok
> 14 37.720 fedora:24-x-ARC-uClibc: Ok
> 15 98.492 fedora:rawhide: Ok
> 16 100.555 mageia:5: Ok
> 17 94.140 opensuse:13.2: Ok
> 18 95.476 opensuse:42.1: Ok
> 19 106.037 opensuse:tumbleweed: Ok
> 20 75.951 ubuntu:12.04.5: Ok
> 21 52.138 ubuntu:14.04: Ok
> 22 94.814 ubuntu:14.04.4: Ok
> 23 100.525 ubuntu:15.10: Ok
> 24 93.813 ubuntu:16.04: Ok
> 25 85.214 ubuntu:16.04-x-arm: Ok
> 26 83.487 ubuntu:16.04-x-arm64: Ok
> 27 82.918 ubuntu:16.04-x-powerpc64: Ok
> 28 84.189 ubuntu:16.04-x-powerpc64el: Ok
> 29 93.162 ubuntu:16.10: Ok
>
> real 38m13.568s
> user 0m2.379s
> sys 0m2.402s
> [root at zoo ~]#
>
> [root at jouet ~]# perf test
> 1: vmlinux symtab matches kallsyms : Ok
> 2: detect openat syscall event : Ok
> 3: detect openat syscall event on all cpus : Ok
> 4: read samples using the mmap interface : Ok
> 5: parse events tests : Ok
> 6: Validate PERF_RECORD_* events & perf_sample fields : Ok
> 7: Test perf pmu format parsing : Ok
> 8: Test dso data read : Ok
> 9: Test dso data cache : Ok
> 10: Test dso data reopen : Ok
> 11: roundtrip evsel->name check : Ok
> 12: Check parsing of sched tracepoints fields : Ok
> 13: Generate and check syscalls:sys_enter_openat event fields: Ok
> 14: struct perf_event_attr setup : Ok
> 15: Test matching and linking multiple hists : Ok
> 16: Try 'import perf' in python, checking link problems : Ok
> 17: Test breakpoint overflow signal handler : Ok
> 18: Test breakpoint overflow sampling : Ok
> 19: Test number of exit event of a simple workload : Ok
> 20: Test software clock events have valid period values : Ok
> 21: Test object code reading : Ok
> 22: Test sample parsing : Ok
> 23: Test using a dummy software event to keep tracking : Ok
> 24: Test parsing with no sample_id_all bit set : Ok
> 25: Test filtering hist entries : Ok
> 26: Test mmap thread lookup : Ok
> 27: Test thread mg sharing : Ok
> 28: Test output sorting of hist entries : Ok
> 29: Test cumulation of child hist entries : Ok
> 30: Test tracking with sched_switch : Ok
> 31: Filter fds with revents mask in a fdarray : Ok
> 32: Add fd to a fdarray, making it autogrow : Ok
> 33: Test kmod_path__parse function : Ok
> 34: Test thread map : Ok
> 35: Test LLVM searching and compiling :
> 35.1: Basic BPF llvm compiling test : Ok
> 35.2: Test kbuild searching : Ok
> 35.3: Compile source for BPF prologue generation test : Ok
> 35.4: Compile source for BPF relocation test : Ok
> 36: Test topology in session : Ok
> 37: Test BPF filter :
> 37.1: Test basic BPF filtering : Ok
> 37.2: Test BPF prologue generation : Ok
> 37.3: Test BPF relocation checker : Ok
> 38: Test thread map synthesize : Ok
> 39: Test cpu map synthesize : Ok
> 40: Test stat config synthesize : Ok
> 41: Test stat synthesize : Ok
> 42: Test stat round synthesize : Ok
> 43: Test attr update synthesize : Ok
> 44: Test events times : Ok
> 45: Test backward reading from ring buffer : Ok
> 46: Test cpu map print : Ok
> 47: Test SDT event probing : Ok
> 48: Test is_printable_array function : Ok
> 49: Test bitmap print : Ok
> 50: x86 rdpmc test : Ok
> 51: Test converting perf time to TSC : Ok
> 52: Test dwarf unwind : Ok
> 53: Test x86 instruction decoder - new instructions : Ok
> 54: Test intel cqm nmi context read : Skip
> [root at jouet ~]#
Pulled, thanks a lot Arnaldo!
Ingo
^ permalink raw reply
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