* [PATCH 0/2] i2c: meson: add gxbb compatible string
From: Wolfram Sang @ 2016-09-24 8:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqJGQ2az=eO0PbfcTrAPxUsym=UaDOOy1Rsw0-AbzMjnXg@mail.gmail.com>
> I did state some reasons previously. Consistent rules for submitters
> of DT bindings and being able to trace history beyond git. Now, I
> guess you aren't changing the rules, but you probably aren't
> requesting people to split DT bindings either? You might not be aware,
> but we also generate a DT only tree with git-filter-branch[1] for
> non-kernel projects to use bindings and dts files. For that, sure they
> will only get the DT binding part of it, but what commit text do they
> get? Finally, DT maintainer acks (which from me is a review really)
> apply to the bindings only. Sometimes I review the drivers, but not
> often. So I would like the git history of my reviews to be accurate in
> terms of what I actually reviewed.
Points taken. Will keep them seperate from now on.
Thanks,
Wolfram
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* [PATCH v3 0/4] regulator: axp20x: support AXP803/AXP813 variants
From: Chen-Yu Tsai @ 2016-09-24 8:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1474621107.git.moinejf@free.fr>
On Fri, Sep 23, 2016 at 4:58 PM, Jean-Francois Moine <moinejf@free.fr> wrote:
> This patch series adds support for the X-Powers AXP803 and AXP813 PMICs.
> It is based on the previous patch series
> regulator: axp20x: Simplify various code
>
> v3:
> - put the code of the new devices in new files instead of in the common
> axp20x file.
> - fix errors about the regulators and interrupts
> v2:
> - fix lack of support of dcdc frequency
> - notice that the AXP803 is also handled
> - send the patch to the DT maintainers
>
> Jean-Francois Moine (4):
> regulator: axp20x: move device independant parts to new files
> regulator: axp20x: duplicate the MFD axp20x-rsb code
> regulator: axp20x: add the AXP803
> regulator: axp20x: add the AXP813
NAK. Please follow the axp20x mfd and sub-device driver design we
already have.
ChenYu
> Documentation/devicetree/bindings/mfd/axp20x.txt | 29 ++-
> drivers/mfd/axp20x.c | 15 +
> drivers/regulator/Makefile | 3 +-
> drivers/regulator/axp-regulator.c | 347 +++++++++++++++++++
> drivers/regulator/axp-regulator.h | 133 ++++++++
> drivers/regulator/axp20x-regulator.c | 415 ++---------------------
> drivers/regulator/axp803.c | 225 ++++++++++++
> drivers/regulator/axp813.c | 229 +++++++++++++
> include/linux/mfd/axp20x.h | 2 +
> 9 files changed, 1012 insertions(+), 388 deletions(-)
> create mode 100644 drivers/regulator/axp-regulator.c
> create mode 100644 drivers/regulator/axp-regulator.h
> create mode 100644 drivers/regulator/axp803.c
> create mode 100644 drivers/regulator/axp813.c
>
> --
> 2.10.0
>
^ permalink raw reply
* [PATCH 3/3] regulator: axp20x: simplify device access
From: Chen-Yu Tsai @ 2016-09-24 8:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d3078ed4eefd4de48e4b5666a64f6123f8d72483.1474616699.git.moinejf@free.fr>
Hi,
On Thu, Sep 22, 2016 at 2:20 AM, Jean-Francois Moine <moinejf@free.fr> wrote:
> Use the pointer to the main regulator device instead of the pointer
> to the child platform device.
>
> Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> ---
> drivers/regulator/axp20x-regulator.c | 45 ++++++++++++++++++------------------
> 1 file changed, 23 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
> index 7405f5b..244ddc3 100644
> --- a/drivers/regulator/axp20x-regulator.c
> +++ b/drivers/regulator/axp20x-regulator.c
> @@ -347,9 +347,9 @@ static const struct regulator_desc axp809_regulators[] = {
> AXP_DESC_SW(AXP809, SW, "sw", "swin", AXP22X_PWR_OUT_CTRL2, BIT(6)),
> };
>
> -static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
> +static int axp20x_set_dcdc_freq(struct device *dev, u32 dcdcfreq)
> {
> - struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
> + struct axp20x_dev *axp20x = dev_get_drvdata(dev);
> unsigned int reg = AXP20X_DCDC_FREQ;
> u32 min, max, def, step;
>
> @@ -378,7 +378,7 @@ static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
> step = 150;
> break;
> default:
> - dev_err(&pdev->dev,
> + dev_err(dev,
> "Setting DCDC frequency for unsupported AXP variant\n");
> return -EINVAL;
> }
> @@ -388,13 +388,13 @@ static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
>
> if (dcdcfreq < min) {
> dcdcfreq = min;
> - dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
> + dev_warn(dev, "DCDC frequency too low. Set to %ukHz\n",
> min);
> }
>
> if (dcdcfreq > max) {
> dcdcfreq = max;
> - dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
> + dev_warn(dev, "DCDC frequency too high. Set to %ukHz\n",
> max);
> }
>
> @@ -404,24 +404,24 @@ static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
> AXP20X_FREQ_DCDC_MASK, dcdcfreq);
> }
>
> -static int axp20x_regulator_parse_dt(struct platform_device *pdev)
> +static int axp20x_regulator_parse_dt(struct device *dev)
> {
> struct device_node *np, *regulators;
> int ret;
> u32 dcdcfreq = 0;
>
> - np = of_node_get(pdev->dev.parent->of_node);
> + np = of_node_get(dev->of_node);
> if (!np)
> return 0;
>
> regulators = of_get_child_by_name(np, "regulators");
> if (!regulators) {
> - dev_warn(&pdev->dev, "regulators node not found\n");
> + dev_warn(dev, "regulators node not found\n");
> } else {
> of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
> - ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
> + ret = axp20x_set_dcdc_freq(dev, dcdcfreq);
> if (ret < 0) {
> - dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
> + dev_err(dev, "Error setting dcdc frequency: %d\n", ret);
> return ret;
> }
>
> @@ -499,11 +499,12 @@ static u32 axp20x_polyphase_slave(struct axp20x_dev *axp20x)
>
> static int axp20x_regulator_probe(struct platform_device *pdev)
> {
> + struct device *dev = pdev->dev.parent;
There are 2 struct device's in play in this function, 1 from the parent,
and 1 for the platform device for this regulator sub-device.
> struct regulator_dev *rdev;
> - struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
> + struct axp20x_dev *axp20x = dev_get_drvdata(dev);
> const struct regulator_desc *regulators;
> struct regulator_config config = {
> - .dev = pdev->dev.parent,
> + .dev = dev,
> .regmap = axp20x->regmap,
> .driver_data = axp20x,
> };
> @@ -532,7 +533,7 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
> dcdc5_ix = AXP22X_DCDC5;
> dc1sw_ix = AXP22X_DC1SW;
> dc5ldo_ix = AXP22X_DC5LDO;
> - drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
> + drivevbus = of_property_read_bool(dev->of_node,
> "x-powers,drive-vbus-en");
> break;
> case AXP806_ID:
> @@ -555,13 +556,13 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
> dc5ldo_ix = AXP809_DC5LDO;
> break;
> default:
> - dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
> + dev_err(dev, "Unsupported AXP variant: %ld\n",
So this one is incorrect. You should use this device's struct,
not the parent. It's possible the mfd driver supports a PMIC,
but the regulator driver is still missing.
> axp20x->variant);
> return -EINVAL;
> }
>
> /* This only sets the dcdc freq. Ignore any errors */
> - axp20x_regulator_parse_dt(pdev);
> + axp20x_regulator_parse_dt(dev);
>
> for (i = 0; i < nregulators; i++) {
> const struct regulator_desc *desc = ®ulators[i];
> @@ -580,7 +581,7 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
> * name.
> */
> if (i == dc1sw_ix && dcdc1_name) {
> - new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
> + new_desc = devm_kzalloc(dev, sizeof(*desc),
> GFP_KERNEL);
> *new_desc = regulators[i];
> new_desc->supply_name = dcdc1_name;
> @@ -588,16 +589,16 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
> }
>
> if (i == dc5ldo_ix && dcdc5_name) {
> - new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
> + new_desc = devm_kzalloc(dev, sizeof(*desc),
> GFP_KERNEL);
Same here. The devres lifetime should be bound to this driver, not the parent.
> *new_desc = regulators[i];
> new_desc->supply_name = dcdc5_name;
> desc = new_desc;
> }
>
> - rdev = devm_regulator_register(&pdev->dev, desc, &config);
> + rdev = devm_regulator_register(dev, desc, &config);
Same here.
> if (IS_ERR(rdev)) {
> - dev_err(&pdev->dev, "Failed to register %s\n",
> + dev_err(dev, "Failed to register %s\n",
Same here.
> regulators[i].name);
>
> return PTR_ERR(rdev);
> @@ -608,7 +609,7 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
> &workmode);
> if (!ret) {
> if (axp20x_set_dcdc_workmode(rdev, i, workmode))
> - dev_err(&pdev->dev, "Failed to set workmode on %s\n",
> + dev_err(dev, "Failed to set workmode on %s\n",
Same here.
> rdev->desc->name);
> }
>
> @@ -630,11 +631,11 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
> /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
> regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
> AXP22X_MISC_N_VBUSEN_FUNC, 0);
> - rdev = devm_regulator_register(&pdev->dev,
> + rdev = devm_regulator_register(dev,
Same here.
> &axp22x_drivevbus_regulator,
> &config);
> if (IS_ERR(rdev)) {
> - dev_err(&pdev->dev, "Failed to register drivevbus\n");
> + dev_err(dev, "Failed to register drivevbus\n");
Same here.
Regards
ChenYu
> return PTR_ERR(rdev);
> }
> }
> --
> 2.10.0
>
^ permalink raw reply
* [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06
From: zhichang @ 2016-09-24 8:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1849232.KJrfRPHGN6@wuerfel>
Hi, Arnd,
On 2016?09?23? 23:55, Arnd Bergmann wrote:
> On Friday, September 23, 2016 2:59:55 PM CEST Gabriele Paoloni wrote:
>>
>>>> From the perspective of the indirect IO function the input parameter
>>>> is an unsigned long addr that (now) can be either:
>>>> 1) an IO token coming from a legacy pci device
>>>> 2) a phys address that lives on the LPC bus
>>>>
>>>> These are conceptually two separate address spaces (and actually they
>>>> both start from 0).
>>>
>>> Why? Any IORESOURCE_IO address always refers to the logical I/O port
>>> range in Linux, not the physical address that is used on a bus.
>>
>> If I read the code correctly when you get an I/O token you just add it
>> to PCI_IOBASE.
>> This is enough since pci_remap_iospace set the virtual address to
>> PCI_IOBASE + the I/O token offset; so we can read/write to
>> vaddr = PCI_IOBASE + token as pci_remap_iospace has mapped it correctly
>> to the respective PCI cpu address (that is set in the I/O range property
>> of the host controller)
>>
>> In the patchset accessors LPC operates directly on the cpu addresses
>> and the input parameter of the accessors can be either an IO token or
>> a cpu address
>>
>> +static inline void outb(u8 value, unsigned long addr)
>> +{
>> +#ifdef CONFIG_ARM64_INDIRECT_PIO
>> + if (arm64_extio_ops && arm64_extio_ops->start <= addr &&
>> + addr <= arm64_extio_ops->end)
>>
>> Here below we operate on cpu address
>>
>> + extio_outb(value, addr);
>> + else
>> +#endif
>
> I missed this bug earlier, this obviously needs to be
>
> arm64_extio_ops->outb(value, addr - arm64_extio_ops->start);
>
> or possibly
>
> arm64_extio_ops->outb(arm64_extio_ops, value, addr);
>
> as the outb function won't know what the offset is, but
> that needed to be fixed regardless.
In V3, the outb is :
void outb(u8 value, unsigned long addr)
{
if (!arm64_extio_ops || arm64_extio_ops->start > addr ||
arm64_extio_ops->end < addr)
writeb(value, PCI_IOBASE + addr);
else
if (arm64_extio_ops->pfout)
arm64_extio_ops->pfout(arm64_extio_ops->devpara,
addr + arm64_extio_ops->ptoffset, &value,
sizeof(u8), 1);
}
here, arm64_extio_ops->ptoffset is the offset between the real legacy IO address
and the logical IO address, similar to the offset of primary address and
secondary address in PCI bridge.
But in V3, LPC driver call pci_address_to_pio to request the logical IO as PCI
host bridge during its probing.
cheers,
Zhichang
>
> Arnd
>
^ permalink raw reply
* [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06
From: zhichang @ 2016-09-24 8:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1760643.vMTR5o5E9g@wuerfel>
Hi, Arnd,
On 2016?09?23? 17:51, Arnd Bergmann wrote:
> On Friday, September 23, 2016 12:27:17 AM CEST zhichang.yuan wrote:
>> For this patch sketch, I have a question.
>> Do we call pci_address_to_pio in arch_of_address_to_pio to get the
>> corresponding logical IO port
>> for LPC??
>
>
> No, of course not, that would be silly:
>
> The argument to pci_address_to_pio() is a phys_addr_t, and we we don't
> have one because there is no address associated with your PIO, that
> is the entire point of your driver!
>
ok. I think I know you points. The physical addresses of LPC are only the LPC
domain addresses, not the really CPU physical addresses. That is just why you
don't support the ranges property usage in patch V3. Consequently, It is not so
reasonable to call pci_address_to_pio() with LPC address because that function
is only suitable for cpu physical address.
But just as you said in the next email reply to Gabriele, "Any IORESOURCE_IO
address always refers to the logical I/O port range in Linux, not the physical
address that is used on a bus.", Any devices which support IO accesses should
have their own unique logical IO range to drive the corresponding hardware. It
means that the drivers should know the mapping between physical port/memory
address and logical IO depend on the device specific I/O mode. At this moment,
only PCI host bridge setup a logical IO range allocation mechanism to manipulate
this logical IO range, and this way applies cpu physical address(memory) as the
input. Now, our LPC also need subrange from this common logical IO range, but
with legacy I/O port rather than CPU memory address. Ok, it break the
precondition of pci_register_io_range/pci_pio_to_address, we should not use them
directly for LPC although the calling of pci_pio_to_address is simple and less
change on the relevant code. We had done like that in V3...
So, the key issue is how to get a logical IO subrange which is not conflicted
with others, such as pci host bridges??
I list several ideas for discussion:
1. reserve a specific logical IO subrange for LPC
I describe this in "Note 1" below. Please check it.
This way seems simple without much changes, but it is not generic.
2. setup a separate logical IO subrange allocation mechanism specific for LPC/ISA
Just as your suggestion before, add the arch_of_address_to_pio() for the devices
which operate I/O with legacy I/O port address rather than memory address in
MMIO mode. That arch_of_address_to_pio() will return non-conflict logical IO
with PCI host bridge at last. But the logical IO range is global, those
functions for LPC/ISA specific logical IO subrange allocation must be
synchronized with pci_register_io_range/pci_pio_to_address to know what logical
ranges had been populated. It is not good for the implement dispersion on same
issue.
3. setup a new underlying method to control the logical IO range management
Based on the existing resource management, add a simplified logical IO range
management support which only request the logical IO ranges according the IO
range size ( similar to IORESOURCE_SIZEALIGN mode ), no matter what type the
physical address is. Then revise the current pci_register_io_range to adopt this
new method. Of-course, LPC/ISA request the logical IO with this new method too.
This is just a proposition. It is more workload compared with other solutions.
What do you think about these? Any more ideas?
> Also, we already know the mapping because this is what the inb/outb
> workaround is looking at, so there is absolutely no reason to call it
> either.
>
>> If we don't, it seems the LPC specific IO address will conflict with PCI
>> host bridges' logical IO.
>>
>> Supposed our LPC populated the IO range from 0x100 to 0x3FF( this is
>> normal for ISA similar
>> devices), after arch_of_address_to_pio(), the r->start will be set as
>> 0x100, r->end will be set as
>> 0x3FF. And if there is one PCI host bridge who request a IO window size
>> over 0x400 at the same
>> time, the corresponding r->start and r->end will be set as 0x0, 0x3FF
>> after of_address_to_resource
>> for this host bridge. Then the IO conflict happens.
>
> You would still need to reserve some space in the io_range_list
> to avoid possible conflicts, which is a bit ugly with the current
> definition of pci_register_io_range, but I'm sure can be done.
>
Note 1) Do you remember patch V2? There, I modified the pci.c like that to
reserve 0 - PCIBIOS_MIN_IO (it is 0x1000) :
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index aab9d51..ac2e569 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3221,7 +3221,7 @@ int __weak pci_register_io_range(phys_addr_t addr, resourc
#ifdef PCI_IOBASE
struct io_range *range;
- resource_size_t allocated_size = 0;
+ resource_size_t allocated_size = PCIBIOS_MIN_IO;
/* check if the range hasn't been previously recorded */
spin_lock(&io_range_lock);
@@ -3270,7 +3270,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio)
#ifdef PCI_IOBASE
struct io_range *range;
- resource_size_t allocated_size = 0;
+ resource_size_t allocated_size = PCIBIOS_MIN_IO;
if (pio > IO_SPACE_LIMIT)
return address;
@@ -3293,7 +3293,7 @@ unsigned long __weak pci_address_to_pio(phys_addr_t addres
{
#ifdef PCI_IOBASE
struct io_range *res;
- resource_size_t offset = 0;
+ resource_size_t offset = PCIBIOS_MIN_IO;
unsigned long addr = -1;
spin_lock(&io_range_lock);
Based on this, a exclusive logical IO subrange is for LPC now. Then we certainly
can add some special handling in __of_address_to_resource or
__of_translate_address --> of_translate_one to return the untranslated LPC/ISA
IO address. But to be honest, I think we don't need this special handling in
address.c anymore. We had known the LPC/ISA IO is 1:1 to logical IO, just think
any logical IO port among 0 - 0x1000 should call the LPC registered I/O hooks in
the new in/out().
Furthermore, we can make the reservation is not fixed as PCIBIOS_MIN_IO. If the
LPC/ISA probing is run before PCI host bridge probing, we can reserve a
non-fixed logcial IO subrange what LPC/ISA ask for.
This solution is based on an assumption that no any other devices have to
request the specific logical IO subrange for LPC/ISA. Probably this assumption
is ok on arm64, you known, there is no real IO space as X86. But anyway, this
reservation is not so generic, depended on some special handling.
Does this idea match your comments??
> One way I can think of would be to change pci_register_io_range()
> to just return the logical port number directly (it already
> knows it!), and pass an invalid physical address (e.g.
> #define ISA_WORKAROUND_IO_PORT_WINDOW -0x10000) into it for
> invalid translations.
>
I am not so clear know your idea here. Do you want to select an unpopulated CPU
address as the parent address in range property?? or anything else???
> Another alternative that just occurred to me would be to move
> the pci_address_to_pio() call from __of_address_to_resource()
> into of_bus_pci_translate() and then do the special handling
> for the ISA/LPC bus in of_bus_isa_translate().
As for this idea, do you mean that of_translate_address will directly return the
final logical IO start address?? It seems to extend the definition of
of_translate_address.
Thanks,
Zhichang
>
> Arnd
>
^ permalink raw reply related
* [PATCH 2/3] gpio: Add a driver for the Raspberry Pi's firmware GPIO calls.
From: Eric Anholt @ 2016-09-24 7:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbJoM-RbcuoC=7xJyrT3v7p2n9HiidRp1GUw=o43_Fkwg@mail.gmail.com>
Linus Walleij <linus.walleij@linaro.org> writes:
> On Fri, Sep 23, 2016 at 3:15 PM, Eric Anholt <eric@anholt.net> wrote:
>> Linus Walleij <linus.walleij@linaro.org> writes:
>>>> diff --git a/include/soc/bcm2835/raspberrypi-firmware.h b/include/soc/bcm2835/raspberrypi-firmware.h
>>>> index 3fb357193f09..671ccd00aea2 100644
>>>> --- a/include/soc/bcm2835/raspberrypi-firmware.h
>>>> +++ b/include/soc/bcm2835/raspberrypi-firmware.h
>>>> @@ -73,11 +73,13 @@ enum rpi_firmware_property_tag {
>>>> RPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE = 0x00030014,
>>>> RPI_FIRMWARE_GET_EDID_BLOCK = 0x00030020,
>>>> RPI_FIRMWARE_GET_DOMAIN_STATE = 0x00030030,
>>>> + RPI_FIRMWARE_GET_GPIO_STATE = 0x00030041,
>>>> RPI_FIRMWARE_SET_CLOCK_STATE = 0x00038001,
>>>> RPI_FIRMWARE_SET_CLOCK_RATE = 0x00038002,
>>>> RPI_FIRMWARE_SET_VOLTAGE = 0x00038003,
>>>> RPI_FIRMWARE_SET_TURBO = 0x00038009,
>>>> RPI_FIRMWARE_SET_DOMAIN_STATE = 0x00038030,
>>>> + RPI_FIRMWARE_SET_GPIO_STATE = 0x00038041,
>>>
>>> Can you please merge this orthogonally into the rpi tree to ARM SoC?
>>
>> This driver would appear in the rpi downstream tree once we settle the
>> driver here. Or are you asking me to delay this series until I can get
>> them to pull just a patch extending the set of packets?
>
> Sorry I am not familiar with your development model. I don't know
> about any RPI downstream tree... What I mean is that the patch to
> include/soc/bcm2835/raspberrypi-firmware.h should be merged by
> whoever is maintaining that file, it is not a GPIO file.
>
> If I get an ACK from the maintainer I can take it into the GPIO
> tree.
Oh, people often say "the rpi tree" to mean downstream (currently 4.4).
The maintainer of that file upstream is me, and I was hoping you could
merge through your tree.
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^ permalink raw reply
* [PATCH 2/2] mfd: ab8500-debugfs: remove unused function
From: Baoyou Xie @ 2016-09-24 5:36 UTC (permalink / raw)
To: linux-arm-kernel
We get 1 warning when building kernel with W=1:
drivers/mfd/ab8500-debugfs.c:1395:6: warning: no previous prototype for 'ab8500_dump_all_banks_to_mem' [-Wmissing-prototypes]
In fact, this function is called by no one and not exported,
so this patch removes it.
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
---
drivers/mfd/ab8500-debugfs.c | 54 --------------------------------------------
1 file changed, 54 deletions(-)
diff --git a/drivers/mfd/ab8500-debugfs.c b/drivers/mfd/ab8500-debugfs.c
index 0aecd7b..9f04a25 100644
--- a/drivers/mfd/ab8500-debugfs.c
+++ b/drivers/mfd/ab8500-debugfs.c
@@ -1382,60 +1382,6 @@ void ab8500_dump_all_banks(struct device *dev)
}
}
-/* Space for 500 registers. */
-#define DUMP_MAX_REGS 700
-static struct ab8500_register_dump
-{
- u8 bank;
- u8 reg;
- u8 value;
-} ab8500_complete_register_dump[DUMP_MAX_REGS];
-
-/* This shall only be called upon kernel panic! */
-void ab8500_dump_all_banks_to_mem(void)
-{
- int i, r = 0;
- u8 bank;
- int err = 0;
-
- pr_info("Saving all ABB registers for crash analysis.\n");
-
- for (bank = 0; bank < AB8500_NUM_BANKS; bank++) {
- for (i = 0; i < debug_ranges[bank].num_ranges; i++) {
- u8 reg;
-
- for (reg = debug_ranges[bank].range[i].first;
- reg <= debug_ranges[bank].range[i].last;
- reg++) {
- u8 value;
-
- err = prcmu_abb_read(bank, reg, &value, 1);
-
- if (err < 0)
- goto out;
-
- ab8500_complete_register_dump[r].bank = bank;
- ab8500_complete_register_dump[r].reg = reg;
- ab8500_complete_register_dump[r].value = value;
-
- r++;
-
- if (r >= DUMP_MAX_REGS) {
- pr_err("%s: too many register to dump!\n",
- __func__);
- err = -EINVAL;
- goto out;
- }
- }
- }
- }
-out:
- if (err >= 0)
- pr_info("Saved all ABB registers.\n");
- else
- pr_info("Failed to save all ABB registers.\n");
-}
-
static int ab8500_all_banks_open(struct inode *inode, struct file *file)
{
struct seq_file *s;
--
2.7.4
^ permalink raw reply related
* Alignment issues with freescale FEC driver
From: Andy Duan @ 2016-09-24 5:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160923.224553.1824171056324385383.davem@davemloft.net>
From: David Miller <davem@davemloft.net> Sent: Saturday, September 24, 2016 10:46 AM
> To: eric at nelint.com
> Cc: andrew at lunn.ch; edumazet at google.com; Andy Duan
> <fugang.duan@nxp.com>; otavio at ossystems.com.br;
> netdev at vger.kernel.org; troy.kisky at boundarydevices.com;
> rmk+kernel at arm.linux.org.uk; cjb.sw.nospam at gmail.com; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: Alignment issues with freescale FEC driver
>
> From: Eric Nelson <eric@nelint.com>
> Date: Fri, 23 Sep 2016 11:35:17 -0700
>
> > From the i.MX6DQ reference manual, bit 7 of ENET_RACC says this:
> >
> > "RX FIFO Shift-16
> >
> > When this field is set, the actual frame data starts at bit 16 of the
> > first word read from the RX FIFO aligning the Ethernet payload on a
> > 32-bit boundary."
> >
> > Same for the i.MX6UL.
> >
> > I'm not sure what it will take to use this, but it seems to be exactly
> > what we're looking for.
>
> +1
RACC[SHIFT16] just instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO to align
the Ethernet payload on a 32-bit boundary.
Eric's patch "net: fec: support RRACC_SHIFT16 to align IP header" works fine.
For the alignment issues, that is introduced by commit 1b7bde6d6 and c259c132a in net-next tree. Before these commits, no alignment issue.
How to fix the issue:
Solution1: to enable HW RRACC_SHIFT16 feature (test pass):
Eric's patch "net: fec: support RRACC_SHIFT16 to align IP header".
Solution2: include the correct prefetch() header (test pass):
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -59,7 +59,7 @@
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/busfreq-imx.h>
-#include <linux/prefetch.h>
+#include <asm/processor.h>
Solution3: use __netdev_alloc_skb_ip_align() instead of netdev_alloc_skb().
Or: still use the previous method before commit 1b7bde6d6:
skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
skb_reserve(skb, NET_IP_ALIGN);
Comparing these solutions:
From sw effort and performance, I think these are the similar. Enable RRACC_SHIFT16 doesn't take extra advantage.
Correct my if I am wrong. Thanks.
Regards,
Andy
^ permalink raw reply
* [PATCH] crypto: sunxi-ss: mark sun4i_hash() static
From: Baoyou Xie @ 2016-09-24 4:28 UTC (permalink / raw)
To: linux-arm-kernel
We get 1 warning when building kernel with W=1:
drivers/crypto/sunxi-ss/sun4i-ss-hash.c:168:5: warning: no previous prototype for 'sun4i_hash' [-Wmissing-prototypes]
In fact, this function is only used in the file in which it is
declared and don't need a declaration, but can be made static.
So this patch marks it 'static'.
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-hash.c b/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
index 1afeb8e..0de2f62 100644
--- a/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
+++ b/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
@@ -165,7 +165,7 @@ int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in)
* write remaining data in op->buf
* final state op->len=56
*/
-int sun4i_hash(struct ahash_request *areq)
+static int sun4i_hash(struct ahash_request *areq)
{
u32 v, ivmode = 0;
unsigned int i = 0;
--
2.7.4
^ permalink raw reply related
* Alignment issues with freescale FEC driver
From: David Miller @ 2016-09-24 2:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <bc19d934-f50b-50d6-0f4f-ecfcb8a2a1c9@nelint.com>
From: Eric Nelson <eric@nelint.com>
Date: Fri, 23 Sep 2016 11:35:17 -0700
> From the i.MX6DQ reference manual, bit 7 of ENET_RACC says this:
>
> "RX FIFO Shift-16
>
> When this field is set, the actual frame data starts at bit 16 of the first
> word read from the RX FIFO aligning the Ethernet payload on a
> 32-bit boundary."
>
> Same for the i.MX6UL.
>
> I'm not sure what it will take to use this, but it seems to be exactly
> what we're looking for.
+1
^ permalink raw reply
* Alignment issues with freescale FEC driver
From: David Miller @ 2016-09-24 2:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0fe7a310-2d2f-4fca-d698-85d66122d91c@nelint.com>
From: Eric Nelson <eric@nelint.com>
Date: Fri, 23 Sep 2016 10:33:29 -0700
> Since the hardware requires longword alignment for its' DMA transfers,
> aligning the IP header will require a memcpy, right?
I wish hardware designers didn't do this.
There is no conflict between DMA alignment and properly offseting
the packet data by two bytes.
All hardware designers have to do is allow 2 padding bytes to be
emitted by the chip before the actual packet data.
Then the longword or whatever DMA transfer alignment is met
whilst still giving the necessary flexibility for where the
packet data lands.
^ permalink raw reply
* [PATCH 0/2] i2c: meson: add gxbb compatible string
From: Rob Herring @ 2016-09-24 1:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160923232641.GB5683@katana>
On Fri, Sep 23, 2016 at 6:26 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
>
>> > I intentionally don't ask people to send me the patches squashed. So,
>> > you will have them seperate in patchwork et al. I only squash them just
>> > before commiting to my tree. That's because I found that when digging
>> > through git history, it is much more convenient to have all the
>> > information in one commit.
>>
>> If git history was the only thing that mattered, then that would be
>> fine. But it is not. Maintainers should apply what's on the list.
>> Period.
>
> Huh? If you would *ask* me to stop squashing, I am listening to reasons.
I did state some reasons previously. Consistent rules for submitters
of DT bindings and being able to trace history beyond git. Now, I
guess you aren't changing the rules, but you probably aren't
requesting people to split DT bindings either? You might not be aware,
but we also generate a DT only tree with git-filter-branch[1] for
non-kernel projects to use bindings and dts files. For that, sure they
will only get the DT binding part of it, but what commit text do they
get? Finally, DT maintainer acks (which from me is a review really)
apply to the bindings only. Sometimes I review the drivers, but not
often. So I would like the git history of my reviews to be accurate in
terms of what I actually reviewed.
> If you want to force arbitrary rules on me, I am not. There are reasons
> where squashing/modifying patches makes more sense compared to forcing
> the author to resend. DTS bindings may not be one, we can discuss that.
> But that rule without allowing exceptions seems impractical to me.
Okay, "period" was a bit much. Exceptions are perfectly fine, we all
do some minor fixups time to time. It just shouldn't be the norm IMO.
Rob
[1] https://git.kernel.org/cgit/linux/kernel/git/devicetree/devicetree-rebasing.git/
^ permalink raw reply
* [RFC 1/4] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
From: Jeremy McNicoll @ 2016-09-23 23:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <147456957514.9057.12155171248212777735@sboyd-linaro>
On 2016-09-22 11:39 AM, Stephen Boyd wrote:
> Quoting Jeremy McNicoll (2016-09-20 17:42:02)
>> On 2016-07-08 10:41 AM, Andy Gross wrote:
>>> On Thu, Jul 07, 2016 at 05:41:04PM -0700, Jeremy McNicoll wrote:
>>>> +
>>>> +#include "../qcom/msm8992.dtsi"
>>>> +
>>>> +/ {
>>>> + model = "LGE MSM8992 BULLHEAD rev-1.01";
>>>> + compatible = "qcom,msm8992";
>>>> + qcom,board-id = <0xb64 0>;
>>>
>>> Please work with sboyd to add the board-id to the dtbTool. We don't put
>>> board-ids in the dts file. We post-process the dtb file and add them then.
>>>
>>
>> sboyd has all the info he needs for this, I believe its just with legal
>> now. Will remove for V2.
>
> I've pushed out an update for dtbtool to have these msm ids.
>
>>
>>>> +
>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> +#include <dt-bindings/clock/qcom,gcc-msm8994.h>
>>>> +
>>>> +/ {
>>>> + model = "Qualcomm Technologies, Inc. MSM 8992";
>>>> + compatible = "qcom,msm8992";
>>>> + qcom,msm-id = <251 0>, <252 0>;
>>
>> This is needed or else the LK provides the following error
>>
>> [5380] qcom,msm-id entry not found
>>
>> and refuses to boot.
>>
>>
>>>> + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
>>>
>>> See above comment on ids.
>>
>> removal of this (pmic-id) seems to be ok.
>>
>
> Having the msm ids (and the pmic ids) in dtbtool isn't going to help
> here though. I believe the bootloader on these devices uses a design of
> appended dtbs where each dtb has the qcom,{msm-id,board-id,pmic-id}
> properties in them. The QCDT "header" that dtbtool generates is not
> used.
>
> To fix that problem we'll need to update dtbtool to inject these
> properties into the dtbs based on the compatible strings. Or get
> maintainers to accept that these ids are now necessary for proper
> functionality.
I will try modifying the tool to inject these values to understand
how easy and/or complicated it will be. This topic will be raised
during plumbers as most people will be there.
>
> Furthermore, the value of board-id (0xb64) is concerning. qcom only
> supports a certain set of values there for their boards, but vendors are
> free to do whatever they want with that value. This means they can reuse
> existing values that would map to qcom's concept of the "mtp" or "cdp"
> boards, or they can numbers that would alias with other vendors.
> Thankfully, msm-id and pmic-id are values that are under qcom's control,
> so those are always going to be unique and sane. Really all that could
> alias is board-id.
>
> What does this all mean? We can't support non-qcom boards in the same
> boot.img because of the possibility for the board-id property to alias
> between different dtbs. Or at least dtbtool will have to do some alias
> analysis and eject one aliasing dtbs from the blob. It also means that
> we have a lot of work to do in dtbtool to inject these properties based
> on strings, and to have custom parsers for different vendor prefixes so
> that we know what values to inject (the nightmare is growing).
>
This provides a reasonably compelling argument that can be discussed
with the device tree maintainers during Plumbers.
> I've asked the bootloader folks to fix this in future platforms so that
> we match based on the compatible string, instead of having to do any
> post processing. Basically, put dtbtool logic into the bootloader. The
> discussion is still on-going, but I'm hopeful that we don't need to keep
> doing things here with post-processing and the headache will be reduced.
> That could totally backfire though if vendors decide to leave the
> bootloader unchanged and boot the "qcom,msm8992-mtp" dtb that's been
> slightly tweaked for their design. Let's hope that doesn't happen.
>
Thank you for pushing this internally as it will definitely aid in the
mainline support going forward.
-jeremy
^ permalink raw reply
* [PATCH 0/2] i2c: meson: add gxbb compatible string
From: Wolfram Sang @ 2016-09-23 23:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqKi9Dk5-nF9xFD-89TTUinaGjMv5s1=N2b-Xyu98b+S3w@mail.gmail.com>
> > I intentionally don't ask people to send me the patches squashed. So,
> > you will have them seperate in patchwork et al. I only squash them just
> > before commiting to my tree. That's because I found that when digging
> > through git history, it is much more convenient to have all the
> > information in one commit.
>
> If git history was the only thing that mattered, then that would be
> fine. But it is not. Maintainers should apply what's on the list.
> Period.
Huh? If you would *ask* me to stop squashing, I am listening to reasons.
If you want to force arbitrary rules on me, I am not. There are reasons
where squashing/modifying patches makes more sense compared to forcing
the author to resend. DTS bindings may not be one, we can discuss that.
But that rule without allowing exceptions seems impractical to me.
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^ permalink raw reply
* [PATCH 0/2] i2c: meson: add gxbb compatible string
From: Rob Herring @ 2016-09-23 23:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160923221312.GA5683@katana>
On Fri, Sep 23, 2016 at 5:13 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
> On Fri, Sep 23, 2016 at 10:01:13AM -0500, Rob Herring wrote:
>> On Thu, Sep 15, 2016 at 2:41 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
>> > On Wed, Sep 14, 2016 at 11:49:15AM +0200, Jerome Brunet wrote:
>> >> This patchset adds a specific compatible string in the Meson I2C driver
>> >> for the Amlogic Meson gxbb SoC.
>> >>
>> >> Other patch series (pinctrl and device tree) are being sent to complete
>> >> the i2c support on meson gxbb
>> >>
>> >> Neil Armstrong (2):
>> >> i2c: meson: add gxbb compatible string
>> >> dt-bindings: i2c-meson: add gxbb compatible string
>> >
>> > Squashed both patches and applied to for-next, thanks!
>>
>> Please don't squash. We ask people to split DT bindings for a reason
>> being reviews and bindings may not go thru subsystem maintainers in
>> the future. It also makes it harder to find things in the archives or
>> patchwork (as does maintainer fixups of subject lines).
>
> I intentionally don't ask people to send me the patches squashed. So,
> you will have them seperate in patchwork et al. I only squash them just
> before commiting to my tree. That's because I found that when digging
> through git history, it is much more convenient to have all the
> information in one commit.
If git history was the only thing that mattered, then that would be
fine. But it is not. Maintainers should apply what's on the list.
Period. You wouldn't fixup pull requests to make the commit history
more to your liking, would you?
Rob
^ permalink raw reply
* [PATCH v4] devicetree: bindings: uart: Add new compatible string for ZynqMP
From: Rob Herring @ 2016-09-23 22:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474629948-9780-1-git-send-email-navam@xilinx.com>
On Fri, Sep 23, 2016 at 04:55:48PM +0530, Nava kishore Manne wrote:
> From: Nava kishore Manne <nava.manne@xilinx.com>
>
> This patch Adds the new compatible string for ZynqMP.
>
> Signed-off-by: Nava kishore Manne <navam@xilinx.com>
> ---
> Changes for v4:
> -Modified the ChangeLog comment.
> Changes for v3:
> -Added changeLog comment.
> Changes for v2:
> -None
>
> Documentation/devicetree/bindings/serial/cdns,uart.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.txt b/Documentation/devicetree/bindings/serial/cdns,uart.txt
> index a3eb154..4fe7aae 100644
> --- a/Documentation/devicetree/bindings/serial/cdns,uart.txt
> +++ b/Documentation/devicetree/bindings/serial/cdns,uart.txt
> @@ -1,7 +1,8 @@
> Binding for Cadence UART Controller
>
> Required properties:
> -- compatible : should be "cdns,uart-r1p8", or "xlnx,xuartps"
> +- compatible : should be "cdns,uart-r1p8", or "xlnx,xuartps" for Zynq and
> + "cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC uart controller.
Please format this as one valid combination per line.
xuartps is not very specific. It needs some abbreviation of "Zynq
Ultrascale+ MPSoC" in it.
> - reg: Should contain UART controller registers location and length.
> - interrupts: Should contain UART controller interrupts.
> - clocks: Must contain phandles to the UART clocks
> --
> 2.1.2
>
^ permalink raw reply
* [PATCH 1/2] dt-bindings: add bindings doc for ZTE VOU display controller
From: Rob Herring @ 2016-09-23 22:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474615449-16893-1-git-send-email-shawn.guo@linaro.org>
On Fri, Sep 23, 2016 at 03:24:08PM +0800, Shawn Guo wrote:
> It adds initial bindings doc for ZTE VOU display controller. HDMI is
> the only supported output device right now.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> .../devicetree/bindings/display/zte,vou.txt | 67 ++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/zte,vou.txt
>
> diff --git a/Documentation/devicetree/bindings/display/zte,vou.txt b/Documentation/devicetree/bindings/display/zte,vou.txt
> new file mode 100644
> index 000000000000..b7407219cfa1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/zte,vou.txt
> @@ -0,0 +1,67 @@
> +ZTE VOU Display Controller
> +
> +This is a display controller found on ZTE ZX296718 SoC. It includes multiple
> +Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks
> +handling scaling, color space conversion etc. VOU also integrates the support
> +for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD.
> +
> +* Master display-subsystem node
> +
> +It must be the parent node of all the sub-device nodes.
> +
> +Required properties:
> + - compatible: should be "zte,zx-display-subsystem"
> + - #address-cells: should be <1>
> + - #size-cells: should be <1>
> + - ranges: to allow probing of sub-devices
> +
> +* VOU controller device
> +
> +Required properties:
> + - compatible: should be "zte,zx296718-vou"
> + - reg: Physical base address and length of the whole VOU IO region
> + - interrupts: VOU interrupt number to the CPU
> + - clocks: A list of phandle + clock-specifier pairs, one for each entry
> + in 'clock-names'
> + - clock-names: A list of clock names. It should contain: "aclk", "ppu_wclk",
> + "main_wclk" and "aux_wclk".
> +
> +* HDMI output device
> +
> +Required properties:
> + - compatible: should be "zte,zx296718-hdmi"
> + - reg: Physical base address and length of the HDMI device IO region
> + - interrupts : HDMI interrupt number to the CPU
> + - clocks: A list of phandle + clock-specifier pairs, one for each entry
> + in 'clock-names'
> + - clock-names: A list of clock names. It should contain: "osc_cec", "osc_clk"
> + and "xclk".
> +
> +Example:
> +
> +display-subsystem {
> + compatible = "zte,zx-display-subsystem";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + vou: vou at 1440000 {
> + compatible = "zte,zx296718-vou";
> + reg = <0x1440000 0x10000>;
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
> + <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
> + clock-names = "aclk", "ppu_wclk",
> + "main_wclk", "aux_wclk";
> + };
> +
> + hdmi: hdmi at 144c000 {
> + compatible = "zte,zx296718-hdmi";
> + reg = <0x144c000 0x4000>;
You have overlapping regions here. I'd suggest you kill off
zte,zx-display-subsystem and make zte,zx296718-vou the top-level node
with hdmi and others as the child nodes.
> + interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&topcrm HDMI_OSC_CEC>,
> + <&topcrm HDMI_OSC_CLK>,
> + <&topcrm HDMI_XCLK>;
> + clock-names = "osc_cec", "osc_clk", "xclk";
> + };
> +};
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH v3 4/4] regulator: axp20x: add the AXP813
From: Rob Herring @ 2016-09-23 22:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <21ac1fd8ab33185ec2cdb436272f48571695ce54.1474621108.git.moinejf@free.fr>
On Fri, Sep 23, 2016 at 09:22:41AM +0200, Jean-Francois Moine wrote:
> The X-Powers AXP813 PMIC is close to the AXP803.
> It is used in some Allwinner boards as the Sinovoip BananaPi M3+.
>
> Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> ---
> Documentation/devicetree/bindings/mfd/axp20x.txt | 9 +-
> drivers/mfd/axp20x.c | 2 +
> drivers/regulator/Makefile | 2 +-
> drivers/regulator/axp813.c | 229 +++++++++++++++++++++++
> include/linux/mfd/axp20x.h | 1 +
> 5 files changed, 239 insertions(+), 4 deletions(-)
> create mode 100644 drivers/regulator/axp813.c
>
> diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt
> index 3332d02..62019fb 100644
> --- a/Documentation/devicetree/bindings/mfd/axp20x.txt
> +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
> @@ -8,11 +8,12 @@ axp221 (X-Powers)
> axp223 (X-Powers)
> axp803 (X-Powers)
> axp809 (X-Powers)
> +axp813 (X-Powers)
>
> Required properties:
> - compatible: "x-powers,axp152", "x-powers,axp202", "x-powers,axp209",
> "x-powers,axp221", "x-powers,axp223", "x-powers,axp803",
> - "x-powers,axp806", "x-powers,axp809"
> + "x-powers,axp806", "x-powers,axp809", "x-powers,axp813"
Same comment here.
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v3 3/4] regulator: axp20x: add the AXP803
From: Rob Herring @ 2016-09-23 22:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6c9e5c21df09a1feb1b00aa000c3c0f77e51eac3.1474621107.git.moinejf@free.fr>
On Fri, Sep 23, 2016 at 09:00:42AM +0200, Jean-Francois Moine wrote:
> The X-Powers AXP803 PMIC is close to the AXP809 with more outputs.
> It is used in some Allwinner boards as the Sinovoip BananaPi M64
> and the Pine A64.
>
> Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> ---
> not tested
> ---
> Documentation/devicetree/bindings/mfd/axp20x.txt | 32 +++-
> drivers/mfd/axp20x.c | 13 ++
> drivers/regulator/Makefile | 3 +-
> drivers/regulator/axp803.c | 225 +++++++++++++++++++++++
> include/linux/mfd/axp20x.h | 1 +
> 5 files changed, 271 insertions(+), 3 deletions(-)
> create mode 100644 drivers/regulator/axp803.c
>
> diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt
> index 8f3ad9a..3332d02 100644
> --- a/Documentation/devicetree/bindings/mfd/axp20x.txt
> +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
> @@ -6,12 +6,13 @@ axp202 (X-Powers)
> axp209 (X-Powers)
> axp221 (X-Powers)
> axp223 (X-Powers)
> +axp803 (X-Powers)
> axp809 (X-Powers)
>
> Required properties:
> - compatible: "x-powers,axp152", "x-powers,axp202", "x-powers,axp209",
> - "x-powers,axp221", "x-powers,axp223", "x-powers,axp806",
> - "x-powers,axp809"
> + "x-powers,axp221", "x-powers,axp223", "x-powers,axp803",
> + "x-powers,axp806", "x-powers,axp809"
If you respin this, please reformat this to one per line.
Acked-by: Rob Herring <robh@kernel.org>
> - reg: The I2C slave address or RSB hardware address for the AXP chip
> - interrupt-parent: The parent interrupt controller
> - interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
> @@ -86,6 +87,33 @@ LDO_IO1 : LDO : ips-supply : GPIO 1
> RTC_LDO : LDO : ips-supply : always on
> DRIVEVBUS : Enable output : drivevbus-supply : external regulator
>
> +AXP803 regulators, type, and corresponding input supply names:
> +
> +Regulator Type Supply Name Notes
> +--------- ---- ----------- -----
> +DCDC1 : DC-DC buck : vin1-supply
> +DCDC2 : DC-DC buck : vin2-supply
> +DCDC3 : DC-DC buck : vin3-supply
> +DCDC4 : DC-DC buck : vin4-supply
> +DCDC5 : DC-DC buck : vin5-supply
> +DCDC6 : DC-DC buck : vin6-supply
> +ALDO1 : LDO : aldoin-supply : shared supply
> +ALDO2 : LDO : aldoin-supply : shared supply
> +ALDO3 : LDO : aldoin-supply : shared supply
> +DLDO1 : LDO : dldoin-supply : shared supply
> +DLDO2 : LDO : dldoin-supply : shared supply
> +DLDO3 : LDO : dldoin-supply : shared supply
> +DLDO4 : LDO : dldoin-supply : shared supply
> +ELDO1 : LDO : eldoin-supply : shared supply
> +ELDO2 : LDO : eldoin-supply : shared supply
> +ELDO3 : LDO : eldoin-supply : shared supply
> +FLDO1 : LDO : fldoin-supply : shared supply
> +FLDO2 : LDO : fldoin-supply : shared supply
> +RTC_LDO : LDO : ips-supply : always on
> +LDO_IO0 : LDO : ips-supply : GPIO 0
> +LDO_IO1 : LDO : ips-supply : GPIO 1
> +DC1SW : On/Off Switch : : DCDC1 secondary output
> +
> AXP806 regulators, type, and corresponding input supply names:
>
> Regulator Type Supply Name Notes
^ permalink raw reply
* [PATCH 0/2] i2c: meson: add gxbb compatible string
From: Wolfram Sang @ 2016-09-23 22:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqKNFzo6RWJO5WOvsyO3e4UTo5Zn48aaDac=+uL_CQWerQ@mail.gmail.com>
On Fri, Sep 23, 2016 at 10:01:13AM -0500, Rob Herring wrote:
> On Thu, Sep 15, 2016 at 2:41 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
> > On Wed, Sep 14, 2016 at 11:49:15AM +0200, Jerome Brunet wrote:
> >> This patchset adds a specific compatible string in the Meson I2C driver
> >> for the Amlogic Meson gxbb SoC.
> >>
> >> Other patch series (pinctrl and device tree) are being sent to complete
> >> the i2c support on meson gxbb
> >>
> >> Neil Armstrong (2):
> >> i2c: meson: add gxbb compatible string
> >> dt-bindings: i2c-meson: add gxbb compatible string
> >
> > Squashed both patches and applied to for-next, thanks!
>
> Please don't squash. We ask people to split DT bindings for a reason
> being reviews and bindings may not go thru subsystem maintainers in
> the future. It also makes it harder to find things in the archives or
> patchwork (as does maintainer fixups of subject lines).
I intentionally don't ask people to send me the patches squashed. So,
you will have them seperate in patchwork et al. I only squash them just
before commiting to my tree. That's because I found that when digging
through git history, it is much more convenient to have all the
information in one commit.
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^ permalink raw reply
* [PATCH 3/3] clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK
From: Fabio Estevam @ 2016-09-23 22:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474036587-13819-3-git-send-email-fabio.estevam@nxp.com>
Hi Stephen,
On Fri, Sep 16, 2016 at 11:36 AM, Fabio Estevam <fabio.estevam@nxp.com> wrote:
> Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
> tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
> enter the ldb_di_ipu_div divider. If the divider gets locked up, no
> ldb_di[x]_clk is generated, and the LVDS display will hang when the
> ipu_di_clk is sourced from ldb_di_clk.
>
> To fix the problem, both the new and current parent of the ldb_di_clk
> should be disabled before the switch. This patch ensures that correct
> steps are followed when ldb_di_clk parent is switched in the beginning
> of boot. The glitchy muxes are then registered as read-only. The clock
> parent can be selected using the assigned-clocks and
> assigned-clock-parents properties of the ccm device tree node:
>
> &clks {
> assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
> <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
> assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>,
> <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
> };
>
> The issue is explained in detail in EB821 ("LDB Clock Switch Procedure &
> i.MX6 Asynchronous Clock Switching Guidelines") [1].
>
> [1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf
>
> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>
> Tested-by Joshua Clayton <stillcompiling@gmail.com>
> Tested-by: Charles Kang <Charles.Kang@advantech.com.tw>
> Acked-by: Shawn Guo <shawnguo@kernel.org>
Do you think this one could be applied to clk-next? It fixes an
important LVDS bug.
Thanks
^ permalink raw reply
* [PATCH v3 3/3] clk: mvebu: migrate CP110 system controller to clk_hw API and registration
From: Stephen Boyd @ 2016-09-23 22:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAPv3WKfDrtDDMPi4oBmpNN_+b4mvG6cVnZT7pNTo8tcNUyzwyA@mail.gmail.com>
On 09/24, Marcin Wojtas wrote:
> Hi Stephen,
>
> 2016-09-23 23:47 GMT+02:00 Stephen Boyd <sboyd@codeaurora.org>:
> > On 09/21, Marcin Wojtas wrote:
> >> @@ -203,80 +202,75 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
> >> if (ret)
> >> return ret;
> >>
> >> - cp110_clks = devm_kcalloc(&pdev->dev, sizeof(struct clk *),
> >> - CP110_CLK_NUM, GFP_KERNEL);
> >> - if (!cp110_clks)
> >> - return -ENOMEM;
> >> -
> >> - cp110_clk_data = devm_kzalloc(&pdev->dev,
> >> - sizeof(*cp110_clk_data),
> >> + cp110_clk_data = devm_kcalloc(&pdev->dev, sizeof(*cp110_clk_data),
> >> + sizeof(struct clk_hw *) * CP110_CLK_NUM,
> >> GFP_KERNEL);
> >
> > This doesn't look right. Why are calloc()ing clk_hw_onecell_data this
> > way?
>
> After some time, at a first sight it seems I should've used following:
> cp110_clk_data = devm_kzalloc(&pdev->dev, sizeof(*cp110_clk_data) +
> sizeof(struct
> clk_hw *) * CP110_CLK_NUM,
> GFP_KERNEL);
>
> I'll re-check, but is that what you meant?
Yes that looks better.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 3/3] clk: mvebu: migrate CP110 system controller to clk_hw API and registration
From: Marcin Wojtas @ 2016-09-23 22:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160923214730.GF21232@codeaurora.org>
Hi Stephen,
2016-09-23 23:47 GMT+02:00 Stephen Boyd <sboyd@codeaurora.org>:
> On 09/21, Marcin Wojtas wrote:
>> @@ -203,80 +202,75 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
>> if (ret)
>> return ret;
>>
>> - cp110_clks = devm_kcalloc(&pdev->dev, sizeof(struct clk *),
>> - CP110_CLK_NUM, GFP_KERNEL);
>> - if (!cp110_clks)
>> - return -ENOMEM;
>> -
>> - cp110_clk_data = devm_kzalloc(&pdev->dev,
>> - sizeof(*cp110_clk_data),
>> + cp110_clk_data = devm_kcalloc(&pdev->dev, sizeof(*cp110_clk_data),
>> + sizeof(struct clk_hw *) * CP110_CLK_NUM,
>> GFP_KERNEL);
>
> This doesn't look right. Why are calloc()ing clk_hw_onecell_data this
> way?
After some time, at a first sight it seems I should've used following:
cp110_clk_data = devm_kzalloc(&pdev->dev, sizeof(*cp110_clk_data) +
sizeof(struct
clk_hw *) * CP110_CLK_NUM,
GFP_KERNEL);
I'll re-check, but is that what you meant?
Best regards,
Marcin
^ permalink raw reply
* [PATCH v3 3/3] clk: mvebu: migrate CP110 system controller to clk_hw API and registration
From: Stephen Boyd @ 2016-09-23 21:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474448759-24482-4-git-send-email-mw@semihalf.com>
On 09/21, Marcin Wojtas wrote:
> @@ -203,80 +202,75 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
> if (ret)
> return ret;
>
> - cp110_clks = devm_kcalloc(&pdev->dev, sizeof(struct clk *),
> - CP110_CLK_NUM, GFP_KERNEL);
> - if (!cp110_clks)
> - return -ENOMEM;
> -
> - cp110_clk_data = devm_kzalloc(&pdev->dev,
> - sizeof(*cp110_clk_data),
> + cp110_clk_data = devm_kcalloc(&pdev->dev, sizeof(*cp110_clk_data),
> + sizeof(struct clk_hw *) * CP110_CLK_NUM,
> GFP_KERNEL);
This doesn't look right. Why are calloc()ing clk_hw_onecell_data this
way?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v3 2/3] clk: mvebu: dynamically allocate resources in Armada CP110 system controller
From: Stephen Boyd @ 2016-09-23 21:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474448759-24482-3-git-send-email-mw@semihalf.com>
On 09/21, Marcin Wojtas wrote:
> Original commit, which added support for Armada CP110 system controller
> used global variables for storing all clock information. It worked
> fine for Armada 7k SoC, with single CP110 block. After dual-CP110 Armada 8k
> was introduced, the data got overwritten and corrupted.
>
> This patch fixes the issue by allocating resources dynamically in the
> driver probe and storing it as platform drvdata.
>
> Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system ...")
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> CC: <stable@vger.kernel.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
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