* [PATCH V2 6/6] arm64: Add uprobe support
From: Pratyush Anand @ 2016-09-27 7:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1474960629.git.panand@redhat.com>
This patch adds support for uprobe on ARM64 architecture.
Unit tests for following have been done so far and they have been found
working
1. Step-able instructions, like sub, ldr, add etc.
2. Simulation-able like ret, cbnz, cbz etc.
3. uretprobe
4. Reject-able instructions like sev, wfe etc.
5. trapped and abort xol path
6. probe at unaligned user address.
7. longjump test cases
Currently it does not support aarch32 instruction probing.
Signed-off-by: Pratyush Anand <panand@redhat.com>
---
arch/arm64/Kconfig | 3 +
arch/arm64/include/asm/cacheflush.h | 1 +
arch/arm64/include/asm/debug-monitors.h | 3 +
arch/arm64/include/asm/ptrace.h | 8 ++
arch/arm64/include/asm/thread_info.h | 5 +-
arch/arm64/include/asm/uprobes.h | 36 ++++++
arch/arm64/kernel/probes/Makefile | 2 +
arch/arm64/kernel/probes/uprobes.c | 221 ++++++++++++++++++++++++++++++++
arch/arm64/kernel/signal.c | 3 +
arch/arm64/mm/flush.c | 2 +-
10 files changed, 282 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/include/asm/uprobes.h
create mode 100644 arch/arm64/kernel/probes/uprobes.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 113326e637f0..2bee1b0b99af 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -236,6 +236,9 @@ config PGTABLE_LEVELS
default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
+config ARCH_SUPPORTS_UPROBES
+ def_bool y
+
source "init/Kconfig"
source "kernel/Kconfig.freezer"
diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index 2e5fb976a572..e9f64ecb75ce 100644
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -71,6 +71,7 @@ extern void __flush_dcache_area(void *addr, size_t len);
extern void __clean_dcache_area_poc(void *addr, size_t len);
extern void __clean_dcache_area_pou(void *addr, size_t len);
extern long __flush_cache_user_range(unsigned long start, unsigned long end);
+extern void sync_icache_aliases(void *kaddr, unsigned long len);
static inline void flush_cache_mm(struct mm_struct *mm)
{
diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h
index b71420a12f26..a44cf5225429 100644
--- a/arch/arm64/include/asm/debug-monitors.h
+++ b/arch/arm64/include/asm/debug-monitors.h
@@ -68,6 +68,9 @@
#define BRK64_ESR_MASK 0xFFFF
#define BRK64_ESR_KPROBES 0x0004
#define BRK64_OPCODE_KPROBES (AARCH64_BREAK_MON | (BRK64_ESR_KPROBES << 5))
+/* uprobes BRK opcodes with ESR encoding */
+#define BRK64_ESR_UPROBES 0x0005
+#define BRK64_OPCODE_UPROBES (AARCH64_BREAK_MON | (BRK64_ESR_UPROBES << 5))
/* AArch32 */
#define DBG_ESR_EVT_BKPT 0x4
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index ada08b5b036d..513daf050e84 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -217,6 +217,14 @@ int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task);
#include <asm-generic/ptrace.h>
+#define procedure_link_pointer(regs) ((regs)->regs[30])
+
+static inline void procedure_link_pointer_set(struct pt_regs *regs,
+ unsigned long val)
+{
+ procedure_link_pointer(regs) = val;
+}
+
#undef profile_pc
extern unsigned long profile_pc(struct pt_regs *regs);
diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h
index e9ea5a6bd449..f6859831462e 100644
--- a/arch/arm64/include/asm/thread_info.h
+++ b/arch/arm64/include/asm/thread_info.h
@@ -112,6 +112,7 @@ static inline struct thread_info *current_thread_info(void)
#define TIF_NEED_RESCHED 1
#define TIF_NOTIFY_RESUME 2 /* callback before returning to user */
#define TIF_FOREIGN_FPSTATE 3 /* CPU's FP state is not current's */
+#define TIF_UPROBE 4 /* uprobe breakpoint or singlestep */
#define TIF_NOHZ 7
#define TIF_SYSCALL_TRACE 8
#define TIF_SYSCALL_AUDIT 9
@@ -132,10 +133,12 @@ static inline struct thread_info *current_thread_info(void)
#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
#define _TIF_SECCOMP (1 << TIF_SECCOMP)
+#define _TIF_UPROBE (1 << TIF_UPROBE)
#define _TIF_32BIT (1 << TIF_32BIT)
#define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
- _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE)
+ _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE | \
+ _TIF_UPROBE)
#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
_TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP | \
diff --git a/arch/arm64/include/asm/uprobes.h b/arch/arm64/include/asm/uprobes.h
new file mode 100644
index 000000000000..8d004073d0e8
--- /dev/null
+++ b/arch/arm64/include/asm/uprobes.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2014-2016 Pratyush Anand <panand@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _ASM_UPROBES_H
+#define _ASM_UPROBES_H
+
+#include <asm/debug-monitors.h>
+#include <asm/insn.h>
+#include <asm/probes.h>
+
+#define MAX_UINSN_BYTES AARCH64_INSN_SIZE
+
+#define UPROBE_SWBP_INSN BRK64_OPCODE_UPROBES
+#define UPROBE_SWBP_INSN_SIZE AARCH64_INSN_SIZE
+#define UPROBE_XOL_SLOT_BYTES MAX_UINSN_BYTES
+
+typedef u32 uprobe_opcode_t;
+
+struct arch_uprobe_task {
+};
+
+struct arch_uprobe {
+ union {
+ u8 insn[MAX_UINSN_BYTES];
+ u8 ixol[MAX_UINSN_BYTES];
+ };
+ struct arch_probe_insn api;
+ bool simulate;
+};
+
+#endif
diff --git a/arch/arm64/kernel/probes/Makefile b/arch/arm64/kernel/probes/Makefile
index ce06312e3d34..89b6df613dde 100644
--- a/arch/arm64/kernel/probes/Makefile
+++ b/arch/arm64/kernel/probes/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_KPROBES) += kprobes.o decode-insn.o \
kprobes_trampoline.o \
simulate-insn.o
+obj-$(CONFIG_UPROBES) += uprobes.o decode-insn.o \
+ simulate-insn.o
diff --git a/arch/arm64/kernel/probes/uprobes.c b/arch/arm64/kernel/probes/uprobes.c
new file mode 100644
index 000000000000..d30d13040346
--- /dev/null
+++ b/arch/arm64/kernel/probes/uprobes.c
@@ -0,0 +1,221 @@
+/*
+ * Copyright (C) 2014-2016 Pratyush Anand <panand@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/highmem.h>
+#include <linux/ptrace.h>
+#include <linux/uprobes.h>
+#include <asm/cacheflush.h>
+
+#include "decode-insn.h"
+
+#define UPROBE_INV_FAULT_CODE UINT_MAX
+
+bool is_trap_insn(uprobe_opcode_t *insn)
+{
+ return false;
+}
+
+void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
+ void *src, unsigned long len)
+{
+ void *xol_page_kaddr = kmap_atomic(page);
+ void *dst = xol_page_kaddr + (vaddr & ~PAGE_MASK);
+
+ /* Initialize the slot */
+ memcpy(dst, src, len);
+
+ /* flush caches (dcache/icache) */
+ sync_icache_aliases(dst, len);
+
+ kunmap_atomic(xol_page_kaddr);
+}
+
+unsigned long uprobe_get_swbp_addr(struct pt_regs *regs)
+{
+ return instruction_pointer(regs);
+}
+
+int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
+ unsigned long addr)
+{
+ probe_opcode_t insn;
+
+ /* TODO: Currently we do not support AARCH32 instruction probing */
+ if (test_bit(TIF_32BIT, &mm->context.flags))
+ return -EINVAL;
+ else if (!IS_ALIGNED(addr, AARCH64_INSN_SIZE))
+ return -EINVAL;
+
+ insn = *(probe_opcode_t *)(&auprobe->insn[0]);
+
+ switch (arm_probe_decode_insn(insn, &auprobe->api)) {
+ case INSN_REJECTED:
+ return -EINVAL;
+
+ case INSN_GOOD_NO_SLOT:
+ auprobe->simulate = true;
+ break;
+
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+ struct uprobe_task *utask = current->utask;
+
+ /* Initialize with an invalid fault code to detect if ol insn trapped */
+ current->thread.fault_code = UPROBE_INV_FAULT_CODE;
+
+ /* Instruction points to execute ol */
+ instruction_pointer_set(regs, utask->xol_vaddr);
+
+ user_enable_single_step(current);
+
+ return 0;
+}
+
+int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+ struct uprobe_task *utask = current->utask;
+
+ WARN_ON_ONCE(current->thread.fault_code != UPROBE_INV_FAULT_CODE);
+
+ /* Instruction points to execute next to breakpoint address */
+ instruction_pointer_set(regs, utask->vaddr + 4);
+
+ user_disable_single_step(current);
+
+ return 0;
+}
+bool arch_uprobe_xol_was_trapped(struct task_struct *t)
+{
+ /*
+ * Between arch_uprobe_pre_xol and arch_uprobe_post_xol, if an xol
+ * insn itself is trapped, then detect the case with the help of
+ * invalid fault code which is being set in arch_uprobe_pre_xol
+ */
+ if (t->thread.fault_code != UPROBE_INV_FAULT_CODE)
+ return true;
+
+ return false;
+}
+
+bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+ probe_opcode_t insn;
+ unsigned long addr;
+
+ if (!auprobe->simulate)
+ return false;
+
+ insn = *(probe_opcode_t *)(&auprobe->insn[0]);
+ addr = instruction_pointer(regs);
+
+ if (auprobe->api.handler)
+ auprobe->api.handler(insn, addr, regs);
+
+ return true;
+}
+
+void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+ struct uprobe_task *utask = current->utask;
+
+ /*
+ * Task has received a fatal signal, so reset back to probbed
+ * address.
+ */
+ instruction_pointer_set(regs, utask->vaddr);
+
+ user_disable_single_step(current);
+}
+
+bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx,
+ struct pt_regs *regs)
+{
+ /*
+ * If a simple branch instruction (B) was called for retprobed
+ * assembly label then return true even when regs->sp and ret->stack
+ * are same. It will ensure that cleanup and reporting of return
+ * instances corresponding to callee label is done when
+ * handle_trampoline for called function is executed.
+ */
+ if (ctx == RP_CHECK_CHAIN_CALL)
+ return regs->sp <= ret->stack;
+ else
+ return regs->sp < ret->stack;
+}
+
+unsigned long
+arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr,
+ struct pt_regs *regs)
+{
+ unsigned long orig_ret_vaddr;
+
+ orig_ret_vaddr = procedure_link_pointer(regs);
+ /* Replace the return addr with trampoline addr */
+ procedure_link_pointer_set(regs, trampoline_vaddr);
+
+ return orig_ret_vaddr;
+}
+
+int arch_uprobe_exception_notify(struct notifier_block *self,
+ unsigned long val, void *data)
+{
+ return NOTIFY_DONE;
+}
+
+static int uprobe_breakpoint_handler(struct pt_regs *regs,
+ unsigned int esr)
+{
+ if (user_mode(regs) && uprobe_pre_sstep_notifier(regs))
+ return DBG_HOOK_HANDLED;
+
+ return DBG_HOOK_ERROR;
+}
+
+static int uprobe_single_step_handler(struct pt_regs *regs,
+ unsigned int esr)
+{
+ struct uprobe_task *utask = current->utask;
+
+ if (user_mode(regs)) {
+ WARN_ON(utask &&
+ (instruction_pointer(regs) != utask->xol_vaddr + 4));
+
+ if (uprobe_post_sstep_notifier(regs))
+ return DBG_HOOK_HANDLED;
+ }
+
+ return DBG_HOOK_ERROR;
+}
+
+/* uprobe breakpoint handler hook */
+static struct break_hook uprobes_break_hook = {
+ .esr_mask = BRK64_ESR_MASK,
+ .esr_val = BRK64_ESR_UPROBES,
+ .fn = uprobe_breakpoint_handler,
+};
+
+/* uprobe single step handler hook */
+static struct step_hook uprobes_step_hook = {
+ .fn = uprobe_single_step_handler,
+};
+
+static int __init arch_init_uprobes(void)
+{
+ register_break_hook(&uprobes_break_hook);
+ register_step_hook(&uprobes_step_hook);
+
+ return 0;
+}
+
+device_initcall(arch_init_uprobes);
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index 404dd67080b9..c7b6de62f9d3 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -414,6 +414,9 @@ asmlinkage void do_notify_resume(struct pt_regs *regs,
} else {
local_irq_enable();
+ if (thread_flags & _TIF_UPROBE)
+ uprobe_notify_resume(regs);
+
if (thread_flags & _TIF_SIGPENDING)
do_signal(regs);
diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
index 8377329d8c97..2d78d5a9b89f 100644
--- a/arch/arm64/mm/flush.c
+++ b/arch/arm64/mm/flush.c
@@ -32,7 +32,7 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
__flush_icache_all();
}
-static void sync_icache_aliases(void *kaddr, unsigned long len)
+void sync_icache_aliases(void *kaddr, unsigned long len)
{
unsigned long addr = (unsigned long)kaddr;
--
2.7.4
^ permalink raw reply related
* [PATCH V2 5/6] arm64: introduce mm context flag to keep 32 bit task information
From: Pratyush Anand @ 2016-09-27 7:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1474960629.git.panand@redhat.com>
We need to decide in some cases like uprobe instruction analysis that
whether the current mm context belongs to a 32 bit task or 64 bit.
This patch has introduced an unsigned flag variable in mm_context_t.
Currently, we set and clear TIF_32BIT depending on the condition that
whether an elf binary load sets personality for 32 bit or 64 bit
respectively.
Signed-off-by: Pratyush Anand <panand@redhat.com>
---
arch/arm64/include/asm/elf.h | 12 ++++++++++--
arch/arm64/include/asm/mmu.h | 1 +
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index a55384f4a5d7..5d1700425efe 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -138,7 +138,11 @@ typedef struct user_fpsimd_state elf_fpregset_t;
*/
#define ELF_PLAT_INIT(_r, load_addr) (_r)->regs[0] = 0
-#define SET_PERSONALITY(ex) clear_thread_flag(TIF_32BIT);
+#define SET_PERSONALITY(ex) \
+({ \
+ clear_bit(TIF_32BIT, ¤t->mm->context.flags); \
+ clear_thread_flag(TIF_32BIT); \
+})
/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
#define ARCH_DLINFO \
@@ -183,7 +187,11 @@ typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG];
((x)->e_flags & EF_ARM_EABI_MASK))
#define compat_start_thread compat_start_thread
-#define COMPAT_SET_PERSONALITY(ex) set_thread_flag(TIF_32BIT);
+#define COMPAT_SET_PERSONALITY(ex) \
+({ \
+ set_bit(TIF_32BIT, ¤t->mm->context.flags); \
+ set_thread_flag(TIF_32BIT); \
+ })
#define COMPAT_ARCH_DLINFO
extern int aarch32_setup_vectors_page(struct linux_binprm *bprm,
int uses_interp);
diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
index 8d9fce037b2f..d4fa21543771 100644
--- a/arch/arm64/include/asm/mmu.h
+++ b/arch/arm64/include/asm/mmu.h
@@ -19,6 +19,7 @@
typedef struct {
atomic64_t id;
void *vdso;
+ unsigned long flags;
} mm_context_t;
/*
--
2.7.4
^ permalink raw reply related
* [PATCH V2 4/6] arm64: Handle TRAP_BRKPT for user mode as well
From: Pratyush Anand @ 2016-09-27 7:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1474960629.git.panand@redhat.com>
uprobe is registered at break_hook with a unique ESR code. So, when a
TRAP_BRKPT occurs, call_break_hook checks if it was for uprobe. If not,
then send a SIGTRAP to user.
Signed-off-by: Pratyush Anand <panand@redhat.com>
---
arch/arm64/kernel/debug-monitors.c | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
index a8f8de012250..605df76f0a06 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -306,16 +306,20 @@ NOKPROBE_SYMBOL(call_break_hook);
static int brk_handler(unsigned long addr, unsigned int esr,
struct pt_regs *regs)
{
- if (user_mode(regs)) {
- send_user_sigtrap(TRAP_BRKPT);
- }
+ bool handler_found = false;
+
#ifdef CONFIG_KPROBES
- else if ((esr & BRK64_ESR_MASK) == BRK64_ESR_KPROBES) {
- if (kprobe_breakpoint_handler(regs, esr) != DBG_HOOK_HANDLED)
- return -EFAULT;
+ if ((esr & BRK64_ESR_MASK) == BRK64_ESR_KPROBES) {
+ if (kprobe_breakpoint_handler(regs, esr) == DBG_HOOK_HANDLED)
+ handler_found = true;
}
#endif
- else if (call_break_hook(regs, esr) != DBG_HOOK_HANDLED) {
+ if (!handler_found && call_break_hook(regs, esr) == DBG_HOOK_HANDLED)
+ handler_found = true;
+
+ if (!handler_found && user_mode(regs)) {
+ send_user_sigtrap(TRAP_BRKPT);
+ } else if (!handler_found) {
pr_warn("Unexpected kernel BRK exception at EL1\n");
return -EFAULT;
}
--
2.7.4
^ permalink raw reply related
* [PATCH V2 3/6] arm64: Handle TRAP_TRACE for user mode as well
From: Pratyush Anand @ 2016-09-27 7:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1474960629.git.panand@redhat.com>
uprobe registers a handler at step_hook. So, single_step_handler now
checks for user mode as well if there is a valid hook.
Signed-off-by: Pratyush Anand <panand@redhat.com>
---
arch/arm64/kernel/debug-monitors.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
index 73ae90ef434c..a8f8de012250 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -226,6 +226,8 @@ static void send_user_sigtrap(int si_code)
static int single_step_handler(unsigned long addr, unsigned int esr,
struct pt_regs *regs)
{
+ bool handler_found = false;
+
/*
* If we are stepping a pending breakpoint, call the hw_breakpoint
* handler first.
@@ -233,7 +235,14 @@ static int single_step_handler(unsigned long addr, unsigned int esr,
if (!reinstall_suspended_bps(regs))
return 0;
- if (user_mode(regs)) {
+#ifdef CONFIG_KPROBES
+ if (kprobe_single_step_handler(regs, esr) == DBG_HOOK_HANDLED)
+ handler_found = true;
+#endif
+ if (!handler_found && call_step_hook(regs, esr) == DBG_HOOK_HANDLED)
+ handler_found = true;
+
+ if (!handler_found && user_mode(regs)) {
send_user_sigtrap(TRAP_TRACE);
/*
@@ -243,15 +252,8 @@ static int single_step_handler(unsigned long addr, unsigned int esr,
* to the active-not-pending state).
*/
user_rewind_single_step(current);
- } else {
-#ifdef CONFIG_KPROBES
- if (kprobe_single_step_handler(regs, esr) == DBG_HOOK_HANDLED)
- return 0;
-#endif
- if (call_step_hook(regs, esr) == DBG_HOOK_HANDLED)
- return 0;
-
- pr_warning("Unexpected kernel single-step exception at EL1\n");
+ } else if (!handler_found) {
+ pr_warn("Unexpected kernel single-step exception at EL1\n");
/*
* Re-enable stepping since we know that we will be
* returning to regs.
--
2.7.4
^ permalink raw reply related
* [PATCH V2 2/6] arm64: kgdb_step_brk_fn: ignore other's exception
From: Pratyush Anand @ 2016-09-27 7:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1474960629.git.panand@redhat.com>
ARM64 step exception does not have any syndrome information. So, it is
responsibility of exception handler to take care that they handle it
only if exception was raised for them.
Since kgdb_step_brk_fn() always returns 0, therefore we might have problem
when we will have other step handler registered as well.
This patch fixes kgdb_step_brk_fn() to return error in case of step handler
was not meant for kgdb.
Signed-off-by: Pratyush Anand <panand@redhat.com>
---
arch/arm64/kernel/kgdb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c
index e017a9493b92..d217c9e95b06 100644
--- a/arch/arm64/kernel/kgdb.c
+++ b/arch/arm64/kernel/kgdb.c
@@ -247,6 +247,9 @@ NOKPROBE_SYMBOL(kgdb_compiled_brk_fn);
static int kgdb_step_brk_fn(struct pt_regs *regs, unsigned int esr)
{
+ if (!kgdb_single_step)
+ return DBG_HOOK_ERROR;
+
kgdb_handle_exception(1, SIGTRAP, 0, regs);
return 0;
}
--
2.7.4
^ permalink raw reply related
* [PATCH V2 1/6] arm64: kprobe: protect/rename few definitions to be reused by uprobe
From: Pratyush Anand @ 2016-09-27 7:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1474960629.git.panand@redhat.com>
decode-insn code has to be reused by arm64 uprobe implementation as well.
Therefore, this patch protects some portion of kprobe code and renames few
other, so that decode-insn functionality can be reused by uprobe even when
CONFIG_KPROBES is not defined.
kprobe_opcode_t and struct arch_specific_insn are also defined by
linux/kprobes.h, when CONFIG_KPROBES is not defined. So, protect these
definitions in asm/probes.h.
linux/kprobes.h already includes asm/kprobes.h. Therefore, remove inclusion
of asm/kprobes.h from decode-insn.c.
There are some definitions like kprobe_insn and kprobes_handler_t etc can
be re-used by uprobe. So, it would be better to remove 'k' from their
names.
struct arch_specific_insn is specific to kprobe. Therefore, introduce a new
struct arch_probe_insn which will be common for both kprobe and uprobe, so
that decode-insn code can be shared. Modify kprobe code accordingly.
Function arm_probe_decode_insn() will be needed by uprobe as well. So make
it global.
Signed-off-by: Pratyush Anand <panand@redhat.com>
---
arch/arm64/include/asm/probes.h | 19 ++++++++++--------
arch/arm64/kernel/probes/decode-insn.c | 32 ++++++++++++++++--------------
arch/arm64/kernel/probes/decode-insn.h | 8 ++++++--
arch/arm64/kernel/probes/kprobes.c | 36 +++++++++++++++++-----------------
4 files changed, 52 insertions(+), 43 deletions(-)
diff --git a/arch/arm64/include/asm/probes.h b/arch/arm64/include/asm/probes.h
index 5af574d632fa..e175a825b187 100644
--- a/arch/arm64/include/asm/probes.h
+++ b/arch/arm64/include/asm/probes.h
@@ -17,19 +17,22 @@
#include <asm/opcodes.h>
-struct kprobe;
-struct arch_specific_insn;
-
-typedef u32 kprobe_opcode_t;
-typedef void (kprobes_handler_t) (u32 opcode, long addr, struct pt_regs *);
+typedef u32 probe_opcode_t;
+typedef void (probes_handler_t) (u32 opcode, long addr, struct pt_regs *);
/* architecture specific copy of original instruction */
-struct arch_specific_insn {
- kprobe_opcode_t *insn;
+struct arch_probe_insn {
+ probe_opcode_t *insn;
pstate_check_t *pstate_cc;
- kprobes_handler_t *handler;
+ probes_handler_t *handler;
/* restore address after step xol */
unsigned long restore;
};
+#ifdef CONFIG_KPROBES
+typedef u32 kprobe_opcode_t;
+struct arch_specific_insn {
+ struct arch_probe_insn api;
+};
+#endif
#endif
diff --git a/arch/arm64/kernel/probes/decode-insn.c b/arch/arm64/kernel/probes/decode-insn.c
index d1731bf977ef..8a29d2982eec 100644
--- a/arch/arm64/kernel/probes/decode-insn.c
+++ b/arch/arm64/kernel/probes/decode-insn.c
@@ -78,8 +78,8 @@ static bool __kprobes aarch64_insn_is_steppable(u32 insn)
* INSN_GOOD If instruction is supported and uses instruction slot,
* INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
*/
-static enum kprobe_insn __kprobes
-arm_probe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+enum probe_insn __kprobes
+arm_probe_decode_insn(probe_opcode_t insn, struct arch_probe_insn *api)
{
/*
* Instructions reading or modifying the PC won't work from the XOL
@@ -89,26 +89,26 @@ arm_probe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
return INSN_GOOD;
if (aarch64_insn_is_bcond(insn)) {
- asi->handler = simulate_b_cond;
+ api->handler = simulate_b_cond;
} else if (aarch64_insn_is_cbz(insn) ||
aarch64_insn_is_cbnz(insn)) {
- asi->handler = simulate_cbz_cbnz;
+ api->handler = simulate_cbz_cbnz;
} else if (aarch64_insn_is_tbz(insn) ||
aarch64_insn_is_tbnz(insn)) {
- asi->handler = simulate_tbz_tbnz;
+ api->handler = simulate_tbz_tbnz;
} else if (aarch64_insn_is_adr_adrp(insn)) {
- asi->handler = simulate_adr_adrp;
+ api->handler = simulate_adr_adrp;
} else if (aarch64_insn_is_b(insn) ||
aarch64_insn_is_bl(insn)) {
- asi->handler = simulate_b_bl;
+ api->handler = simulate_b_bl;
} else if (aarch64_insn_is_br(insn) ||
aarch64_insn_is_blr(insn) ||
aarch64_insn_is_ret(insn)) {
- asi->handler = simulate_br_blr_ret;
+ api->handler = simulate_br_blr_ret;
} else if (aarch64_insn_is_ldr_lit(insn)) {
- asi->handler = simulate_ldr_literal;
+ api->handler = simulate_ldr_literal;
} else if (aarch64_insn_is_ldrsw_lit(insn)) {
- asi->handler = simulate_ldrsw_literal;
+ api->handler = simulate_ldrsw_literal;
} else {
/*
* Instruction cannot be stepped out-of-line and we don't
@@ -120,6 +120,7 @@ arm_probe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
return INSN_GOOD_NO_SLOT;
}
+#ifdef CONFIG_KPROBES
static bool __kprobes
is_probed_address_atomic(kprobe_opcode_t *scan_start, kprobe_opcode_t *scan_end)
{
@@ -138,12 +139,12 @@ is_probed_address_atomic(kprobe_opcode_t *scan_start, kprobe_opcode_t *scan_end)
return false;
}
-enum kprobe_insn __kprobes
+enum probe_insn __kprobes
arm_kprobe_decode_insn(kprobe_opcode_t *addr, struct arch_specific_insn *asi)
{
- enum kprobe_insn decoded;
- kprobe_opcode_t insn = le32_to_cpu(*addr);
- kprobe_opcode_t *scan_end = NULL;
+ enum probe_insn decoded;
+ probe_opcode_t insn = le32_to_cpu(*addr);
+ probe_opcode_t *scan_end = NULL;
unsigned long size = 0, offset = 0;
/*
@@ -162,7 +163,7 @@ arm_kprobe_decode_insn(kprobe_opcode_t *addr, struct arch_specific_insn *asi)
else
scan_end = addr - MAX_ATOMIC_CONTEXT_SIZE;
}
- decoded = arm_probe_decode_insn(insn, asi);
+ decoded = arm_probe_decode_insn(insn, &asi->api);
if (decoded != INSN_REJECTED && scan_end)
if (is_probed_address_atomic(addr - 1, scan_end))
@@ -170,3 +171,4 @@ arm_kprobe_decode_insn(kprobe_opcode_t *addr, struct arch_specific_insn *asi)
return decoded;
}
+#endif
diff --git a/arch/arm64/kernel/probes/decode-insn.h b/arch/arm64/kernel/probes/decode-insn.h
index d438289646a6..76d3f315407f 100644
--- a/arch/arm64/kernel/probes/decode-insn.h
+++ b/arch/arm64/kernel/probes/decode-insn.h
@@ -23,13 +23,17 @@
*/
#define MAX_ATOMIC_CONTEXT_SIZE (128 / sizeof(kprobe_opcode_t))
-enum kprobe_insn {
+enum probe_insn {
INSN_REJECTED,
INSN_GOOD_NO_SLOT,
INSN_GOOD,
};
-enum kprobe_insn __kprobes
+#ifdef CONFIG_KPROBES
+enum probe_insn __kprobes
arm_kprobe_decode_insn(kprobe_opcode_t *addr, struct arch_specific_insn *asi);
+#endif
+enum probe_insn __kprobes
+arm_probe_decode_insn(probe_opcode_t insn, struct arch_probe_insn *asi);
#endif /* _ARM_KERNEL_KPROBES_ARM64_H */
diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
index f5077ea7af6d..1decd2b2c730 100644
--- a/arch/arm64/kernel/probes/kprobes.c
+++ b/arch/arm64/kernel/probes/kprobes.c
@@ -44,31 +44,31 @@ post_kprobe_handler(struct kprobe_ctlblk *, struct pt_regs *);
static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
{
/* prepare insn slot */
- p->ainsn.insn[0] = cpu_to_le32(p->opcode);
+ p->ainsn.api.insn[0] = cpu_to_le32(p->opcode);
- flush_icache_range((uintptr_t) (p->ainsn.insn),
- (uintptr_t) (p->ainsn.insn) +
+ flush_icache_range((uintptr_t) (p->ainsn.api.insn),
+ (uintptr_t) (p->ainsn.api.insn) +
MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
/*
* Needs restoring of return address after stepping xol.
*/
- p->ainsn.restore = (unsigned long) p->addr +
+ p->ainsn.api.restore = (unsigned long) p->addr +
sizeof(kprobe_opcode_t);
}
static void __kprobes arch_prepare_simulate(struct kprobe *p)
{
/* This instructions is not executed xol. No need to adjust the PC */
- p->ainsn.restore = 0;
+ p->ainsn.api.restore = 0;
}
static void __kprobes arch_simulate_insn(struct kprobe *p, struct pt_regs *regs)
{
struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
- if (p->ainsn.handler)
- p->ainsn.handler((u32)p->opcode, (long)p->addr, regs);
+ if (p->ainsn.api.handler)
+ p->ainsn.api.handler((u32)p->opcode, (long)p->addr, regs);
/* single step simulated, now go for post processing */
post_kprobe_handler(kcb, regs);
@@ -98,18 +98,18 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
return -EINVAL;
case INSN_GOOD_NO_SLOT: /* insn need simulation */
- p->ainsn.insn = NULL;
+ p->ainsn.api.insn = NULL;
break;
case INSN_GOOD: /* instruction uses slot */
- p->ainsn.insn = get_insn_slot();
- if (!p->ainsn.insn)
+ p->ainsn.api.insn = get_insn_slot();
+ if (!p->ainsn.api.insn)
return -ENOMEM;
break;
};
/* prepare the instruction */
- if (p->ainsn.insn)
+ if (p->ainsn.api.insn)
arch_prepare_ss_slot(p);
else
arch_prepare_simulate(p);
@@ -142,9 +142,9 @@ void __kprobes arch_disarm_kprobe(struct kprobe *p)
void __kprobes arch_remove_kprobe(struct kprobe *p)
{
- if (p->ainsn.insn) {
- free_insn_slot(p->ainsn.insn, 0);
- p->ainsn.insn = NULL;
+ if (p->ainsn.api.insn) {
+ free_insn_slot(p->ainsn.api.insn, 0);
+ p->ainsn.api.insn = NULL;
}
}
@@ -244,9 +244,9 @@ static void __kprobes setup_singlestep(struct kprobe *p,
}
- if (p->ainsn.insn) {
+ if (p->ainsn.api.insn) {
/* prepare for single stepping */
- slot = (unsigned long)p->ainsn.insn;
+ slot = (unsigned long)p->ainsn.api.insn;
set_ss_context(kcb, slot); /* mark pending ss */
@@ -295,8 +295,8 @@ post_kprobe_handler(struct kprobe_ctlblk *kcb, struct pt_regs *regs)
return;
/* return addr restore if non-branching insn */
- if (cur->ainsn.restore != 0)
- instruction_pointer_set(regs, cur->ainsn.restore);
+ if (cur->ainsn.api.restore != 0)
+ instruction_pointer_set(regs, cur->ainsn.api.restore);
/* restore back original saved kprobe variables and continue */
if (kcb->kprobe_status == KPROBE_REENTER) {
--
2.7.4
^ permalink raw reply related
* [PATCHv2 2/3] tty/serial: at91: fix hardware handshake with GPIOs
From: Richard Genoud @ 2016-09-27 7:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160922132045.tbrd5u56qasaf7gn@pengutronix.de>
2016-09-22 15:20 GMT+02:00 Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>:
> On Mon, Sep 12, 2016 at 11:47:32AM +0200, Richard Genoud wrote:
>> Commit 1cf6e8fc8341 ("tty/serial: at91: fix RTS line management when
>> hardware handshake is enabled") broke the hardware handshake when GPIOs
>> where used.
>
> s/where/were/
ok.
>> Hardware handshake with GPIOs used to work before this commit because
>> the CRTSCTS flag (termios->c_cflag) was set, but not the
>> ATMEL_US_USMODE_HWHS flag (controller register) ; so hardware handshake
>> enabled, but not handled by the controller.
>>
>> This commit restores this behaviour.
>>
>> NB: -stable is not Cced because it doesn't cleanly apply on 4.1+
>> and it will also need previous commit:
>> "serial: mctrl_gpio: implement mctrl_gpio_use_rtscts"
>>
>> Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
>> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
>> Fixes: 1cf6e8fc8341 ("tty/serial: at91: fix RTS line management when hardware handshake is enabled")
>> ---
>> drivers/tty/serial/atmel_serial.c | 11 ++++++++---
>> 1 file changed, 8 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
>> index 2eaa18ddef61..e9b4fbf88c2d 100644
>> --- a/drivers/tty/serial/atmel_serial.c
>> +++ b/drivers/tty/serial/atmel_serial.c
>> @@ -2025,6 +2025,7 @@ static void atmel_serial_pm(struct uart_port *port, unsigned int state,
>> static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
>> struct ktermios *old)
>> {
>> + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
>> unsigned long flags;
>> unsigned int old_mode, mode, imr, quot, baud;
>>
>> @@ -2126,8 +2127,12 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
>> atmel_uart_writel(port, ATMEL_US_TTGR,
>> port->rs485.delay_rts_after_send);
>> mode |= ATMEL_US_USMODE_RS485;
>> - } else if (termios->c_cflag & CRTSCTS) {
>> - /* RS232 with hardware handshake (RTS/CTS) */
>> + } else if ((termios->c_cflag & CRTSCTS) &&
>> + !mctrl_gpio_use_rtscts(atmel_port->gpios)) {
>
> IMHO the behaviour of the hw controlled pins shouldn't change when
> mctrl_gpio is in use (if possible). But I don't understand the issue so
> I guess you need a better changelog.
Yes, the behavior of the CTS/RTS pins should the same whenever they
are GPIOs or not.
That was the case before commit 1cf6e8fc8341 ("tty/serial: at91: fix
RTS line management when
hardware handshake is enabled")
BUT, this commit (1cf6e8fc834) introduced the actual use of the
ATMEL_US_USMODE_HWHS flag.
This flags changes the way RTS/CTS pins are driven, and that's the
discussion we are having in patch 3/3.
>> + /*
>> + * RS232 with hardware handshake (RTS/CTS)
>> + * handled by the controller.
>> + */
>> if (atmel_use_dma_rx(port) && !atmel_use_fifo(port)) {
>> dev_info(port->dev, "not enabling hardware flow control because DMA is used");
>> termios->c_cflag &= ~CRTSCTS;
>> @@ -2135,7 +2140,7 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
>> mode |= ATMEL_US_USMODE_HWHS;
>> }
>> } else {
>> - /* RS232 without hadware handshake */
>> + /* RS232 without hadware handshake or controlled by GPIOs */
>
> When touching this line, please also do s/hadware/hardware/.
ok.
>
>> mode |= ATMEL_US_USMODE_NORMAL;
>> }
>
> Best regards
> Uwe
Thanks.
^ permalink raw reply
* [PATCH V2 0/6] ARM64: Uprobe support added
From: Pratyush Anand @ 2016-09-27 7:43 UTC (permalink / raw)
To: linux-arm-kernel
Changes since v1:
* Exposed sync_icache_aliases() and used that in stead of flush_uprobe_xol_access()
* Assigned 0x0005 to BRK64_ESR_UPROBES in stead of 0x0008
* moved uprobe_opcode_t from probes.h to uprobes.h
* Assigned 4 to TIF_UPROBE instead of 5
* Assigned AARCH64_INSN_SIZE to UPROBE_SWBP_INSN_SIZE instead of hard code 4.
* Removed saved_fault_code from struct arch_uprobe_task
* Removed preempt_dis(en)able() from arch_uprobe_copy_ixol()
* Removed case INSN_GOOD from arch_uprobe_analyze_insn()
* Now we do check that probe point is not for a 32 bit task.
* Return a false positive from is_tarp_insn()
* Changes for rebase conflict resolution
V1 was here: https://lkml.org/lkml/2016/8/2/29
Patches have been rebased on next-20160927, so that there would be no
conflicts with other arm64/for-next/core patches.
Patches have been tested for following:
1. Step-able instructions, like sub, ldr, add etc.
2. Simulation-able like ret, cbnz, cbz etc.
3. uretprobe
4. Reject-able instructions like sev, wfe etc.
5. trapped and abort xol path
6. probe at unaligned user address.
7. longjump test cases
aarch32 task probing is not yet supported.
Pratyush Anand (6):
arm64: kprobe: protect/rename few definitions to be reused by uprobe
arm64: kgdb_step_brk_fn: ignore other's exception
arm64: Handle TRAP_TRACE for user mode as well
arm64: Handle TRAP_BRKPT for user mode as well
arm64: introduce mm context flag to keep 32 bit task information
arm64: Add uprobe support
arch/arm64/Kconfig | 3 +
arch/arm64/include/asm/cacheflush.h | 1 +
arch/arm64/include/asm/debug-monitors.h | 3 +
arch/arm64/include/asm/elf.h | 12 +-
arch/arm64/include/asm/mmu.h | 1 +
arch/arm64/include/asm/probes.h | 19 +--
arch/arm64/include/asm/ptrace.h | 8 ++
arch/arm64/include/asm/thread_info.h | 5 +-
arch/arm64/include/asm/uprobes.h | 36 ++++++
arch/arm64/kernel/debug-monitors.c | 40 +++---
arch/arm64/kernel/kgdb.c | 3 +
arch/arm64/kernel/probes/Makefile | 2 +
arch/arm64/kernel/probes/decode-insn.c | 32 ++---
arch/arm64/kernel/probes/decode-insn.h | 8 +-
arch/arm64/kernel/probes/kprobes.c | 36 +++---
arch/arm64/kernel/probes/uprobes.c | 221 ++++++++++++++++++++++++++++++++
arch/arm64/kernel/signal.c | 3 +
arch/arm64/mm/flush.c | 2 +-
18 files changed, 371 insertions(+), 64 deletions(-)
create mode 100644 arch/arm64/include/asm/uprobes.h
create mode 100644 arch/arm64/kernel/probes/uprobes.c
--
2.7.4
^ permalink raw reply
* [PATCH 1/2] net: qcom/emac: do not use devm on internal phy pdev
From: David Miller @ 2016-09-27 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474640854-1698-1-git-send-email-timur@codeaurora.org>
This patch doesn't apply to net-next.
Also, when you send a patch series, you must send an initial
posting with Subject of the form "[PATCH {net,net-next} 0/2] ..."
explaining at a high level what your patch series is doing,
how it is doing it, and why it is doing it that way.
Thanks.
^ permalink raw reply
* ARM juno R2 board USB Issue (EHCI probe failed)
From: Sajjan, Vikas C @ 2016-09-27 7:03 UTC (permalink / raw)
To: linux-arm-kernel
Hi All,
I working on ARM juno R2 board, with latest kernel 4.8.rc7 and I get below USB EHCI probe error while booting with acpi=force.
EFI stub: Booting Linux Kernel...
ConvertPages: Incompatible memory types
EFI stub: Using DTB from command line
EFI stub: Exiting boot services and installing virtual address map...
[ 0.000000] Booting Linux on physical CPU 0x100
[ 0.000000] Linux version 4.8.0-rc7-00142-gb1f2beb (vikas at dctxvm241) (gcc version 4.8.3 20140401 (prerelease) (crosstool-NG linaro-1.13.1-4.8-2014.04 - Linaro GCC 4.8-2014.04) ) #48 SMP PREEMPT Mon Sep 26 15:31:48 IST 2016
[ 0.000000] Boot CPU: AArch64 Processor [410fd033]
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: EFI v2.50 by ARM Juno EFI Oct 15 2015 14:16:39
[ 0.000000] efi: ACPI=0xfe750000 ACPI 2.0=0xfe750014 PROP=0xfe794370
[ 0.000000] cma: Reserved 16 MiB at 0x00000000fd400000
[ 0.000000] ACPI: Early table checksum verification disabled
[ 0.000000] ACPI: RSDP 0x00000000FE750014 000024 (v02 ARMLTD)
[ 0.000000] ACPI: XSDT 0x00000000FE7400E8 00003C (v01 ARMLTD ARM-JUNO 20140727 01000013)
[ 0.000000] ACPI: FACP 0x00000000FE720000 00010C (v05 ARMLTD ARM-JUNO 20140727 ARM 00000099)
[ 0.000000] ACPI: DSDT 0x00000000FE6F0000 000317 (v01 ARMLTD ARM-JUNO 20140727 INTL 20140214)
[ 0.000000] ACPI: GTDT 0x00000000FE710000 000060 (v02 ARMLTD ARM-JUNO 20140727 ARM 00000099)
[ 0.000000] ACPI: APIC 0x00000000FE700000 000224 (v01 ARMLTD ARM-JUNO 20140727 ARM 00000099)
[ 0.000000] psci: probing for conduit method from ACPI.
[ 0.000000] psci: PSCIv1.0 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] percpu: Embedded 21 pages/cpu @ffff80097feb8000 s47488 r8192 d30336 u86016
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: enabling workaround for ARM erratum 845719
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 2060048
[ 0.000000] Kernel command line: dtb=board.dtb initrd=ramdisk.img console=ttyAMA0,115200 acpi=force root=/dev/sda1
[ 0.000000] log_buf_len individual max cpu contribution: 4096 bytes
[ 0.000000] log_buf_len total cpu_extra contributions: 20480 bytes
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
[ 1.223662] VFIO - User Level meta-driver version: 0.3
[ 1.229335] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 1.235882] ehci-pci: EHCI PCI platform driver
[ 1.240359] ehci-platform: EHCI generic platform driver
[ 1.245619] ehci-platform ARMH0D20:00: Error: DMA mask configuration failed
[ 1.272491] ehci-platform: probe of ARMH0D20:00 failed with error -5
[ 1.278876] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 1.285071] ohci-pci: OHCI PCI platform driver
[ 1.289548] ohci-platform: OHCI generic platform driver
[ 1.294884] usbcore: registered new interface driver usb-storage
[ 1.301231] mousedev: PS/2 mouse device common for all mice
[ 1.307197] rtc-efi rtc-efi: rtc core: registered rtc-efi as rtc0
But this error goes off, if I don't force ACPI booting, i.e., if I remove acpi=force from kernel command line , USB is detected and my RFS which is in the usb drive, gets mounted successfully.
Thanks and Regards
Vikas Sajjan
^ permalink raw reply
* [PATCH v2 1/3] ARM: dts: imx6qdl-apalis: Do not rely on DDC I2C bus bitbang for HDMI
From: Marcel Ziswiler @ 2016-09-27 6:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2263d508999ada9476268138b2922702eb50131f.1474260360.git.maitysanchayan@gmail.com>
On Mon, 2016-09-19 at 10:41 +0530, Sanchayan Maity wrote:
> Remove the use of DDC I2C bus bitbang to support reading of EDID
> and rely on support from internal HDMI I2C master controller instead.
> As a result remove the device tree property ddc-i2c-bus.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
> Changes since v1:
>
> Change the ranking in i2c aliases
>
> v1: https://lkml.org/lkml/2016/9/14/55
> ---
> ?arch/arm/boot/dts/imx6q-apalis-ixora.dts | 12 +++---------
> ?arch/arm/boot/dts/imx6qdl-apalis.dtsi????| 25 +++++++++-------------
> ---
> ?2 files changed, 12 insertions(+), 25 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> index 207b85b..82b81e0 100644
> --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> @@ -55,10 +55,9 @@
> ? ?????"fsl,imx6q";
> ?
> ? aliases {
> - i2c0 = &i2cddc;
> - i2c1 = &i2c1;
> - i2c2 = &i2c2;
> - i2c3 = &i2c3;
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> ? };
> ?
> ? aliases {
> @@ -186,11 +185,6 @@
> ?};
> ?
> ?&hdmi {
> - ddc-i2c-bus = <&i2cddc>;
> - status = "okay";
> -};
> -
> -&i2cddc {
> ? status = "okay";
> ?};
> ?
> diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> index 99e323b..8c67dd8 100644
> --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> @@ -53,18 +53,6 @@
> ? status = "disabled";
> ? };
> ?
> - /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */
> - i2cddc: i2c at 0 {
> - compatible = "i2c-gpio";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_i2c_ddc>;
> - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */
> - ?&gpio2 30 GPIO_ACTIVE_HIGH /* scl */
> - >;
> - i2c-gpio,delay-us = <2>; /* ~100 kHz */
> - status = "disabled";
> - };
> -
> ? reg_1p8v: regulator-1p8v {
> ? compatible = "regulator-fixed";
> ? regulator-name = "1P8V";
> @@ -209,6 +197,12 @@
> ? };
> ?};
> ?
> +&hdmi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hdmi_ddc>;
> + status = "disabled";
> +};
> +
> ?/*
> ? * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
> ? * board)
> @@ -633,11 +627,10 @@
> ? >;
> ? };
> ?
> - pinctrl_i2c_ddc: gpioi2cddcgrp {
> + pinctrl_hdmi_ddc: hdmiddcgrp {
> ? fsl,pins = <
> - /* DDC bitbang */
> - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
> - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0
> + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL
> 0x4001b8b1
> + MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA
> 0x4001b8b1
> ? >;
> ? };
^ permalink raw reply
* [PATCH] ARM: dts: imx6: Add support for Toradex Colibri iMX6 module
From: Marcel Ziswiler @ 2016-09-27 6:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921112438.8661-1-maitysanchayan@gmail.com>
On Wed, 2016-09-21 at 16:54 +0530, Sanchayan Maity wrote:
> Add support for Toradex Colibri iMX6 module.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
> ?arch/arm/boot/dts/Makefile???????????????????|???1 +
> ?arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 253 ++++++++
> ?arch/arm/boot/dts/imx6qdl-colibri.dtsi???????| 890
> +++++++++++++++++++++++++++
> ?3 files changed, 1144 insertions(+)
> ?create mode 100644 arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> ?create mode 100644 arch/arm/boot/dts/imx6qdl-colibri.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f79cac2..44ff380 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -323,6 +323,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> ? imx6dl-aristainetos_7.dtb \
> ? imx6dl-aristainetos2_4.dtb \
> ? imx6dl-aristainetos2_7.dtb \
> + imx6dl-colibri-eval-v3.dtb \
> ? imx6dl-cubox-i.dtb \
> ? imx6dl-dfi-fs700-m60.dtb \
> ? imx6dl-gw51xx.dtb \
> diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> new file mode 100644
> index 0000000..e0c2172
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> @@ -0,0 +1,253 @@
> +/*
> + * Copyright 2014-2016 Toradex AG
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this
> dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *??a) This file is free software; you can redistribute it and/or
> + *?????modify it under the terms of the GNU General Public License
> + *?????version 2 as published by the Free Software Foundation.
> + *
> + *?????This file is distributed in the hope that it will be useful
> + *?????but WITHOUT ANY WARRANTY; without even the implied warranty
> of
> + *?????MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.??See the
> + *?????GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + *??b) Permission is hereby granted, free of charge, to any person
> + *?????obtaining a copy of this software and associated
> documentation
> + *?????files (the "Software"), to deal in the Software without
> + *?????restriction, including without limitation the rights to use
> + *?????copy, modify, merge, publish, distribute, sublicense, and/or
> + *?????sell copies of the Software, and to permit persons to whom
> the
> + *?????Software is furnished to do so, subject to the following
> + *?????conditions:
> + *
> + *?????The above copyright notice and this permission notice shall
> be
> + *?????included in all copies or substantial portions of the
> Software.
> + *
> + *?????THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + *?????EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> + *?????OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *?????NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *?????HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + *?????WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *?????FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *?????OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include "imx6dl.dtsi"
> +#include "imx6qdl-colibri.dtsi"
> +
> +/ {
> + model = "Toradex Colibri iMX6DL/S on Colibri Evaluation
> Board V3";
> + compatible = "toradex,colibri_imx6dl-eval-v3",
> "toradex,colibri_imx6dl",
> + ?????"fsl,imx6dl";
> +
> + aliases {
> + i2c0 = &i2c2;
> + i2c1 = &i2c3;
> + };
> +
> + aliases {
> + rtc0 = &rtc_i2c;
> + rtc1 = &snvs_rtc;
> + };
> +
> + clocks {
> + /* Fixed crystal dedicated to mcp251x */
> + clk16m: clk at 1 {
> + compatible = "fixed-clock";
> + reg = <1>;
> + #clock-cells = <0>;
> + clock-frequency = <16000000>;
> + clock-output-names = "clk16m";
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_keys>;
> +
> + wakeup {
> + label = "Wake-Up";
> + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /*
> SODIMM 45 */
> + linux,code = <KEY_WAKEUP>;
> + debounce-interval = <10>;
> + wakeup-source;
> + };
> + };
> +
> + lcd_display: display at di0 {
> + compatible = "fsl,imx-parallel-display";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interface-pix-fmt = "bgr666";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ipu1_lcdif>;
> + status = "okay";
> +
> + port at 0 {
> + reg = <0>;
> +
> + lcd_display_in: endpoint {
> + remote-endpoint = <&ipu1_di0_disp0>;
> + };
> + };
> +
> + port at 1 {
> + reg = <1>;
> +
> + lcd_display_out: endpoint {
> + remote-endpoint = <&lcd_panel_in>;
> + };
> + };
> + };
> +
> + panel: panel {
> + /*
> + ?* edt,et057090dhu: EDT 5.7" LCD TFT
> + ?* edt,et070080dh6: EDT 7.0" LCD TFT
> + ?*/
> + compatible = "edt,et057090dhu";
> + backlight = <&backlight>;
> +
> + port {
> + lcd_panel_in: endpoint {
> + remote-endpoint =
> <&lcd_display_out>;
> + };
> + };
> + };
> +};
> +
> +&backlight {
> + brightness-levels = <0 127 191 223 239 247 251 255>;
> + default-brightness-level = <1>;
> + status = "okay";
> +};
> +
> +/* Colibri SSP */
> +&ecspi4 {
> + status = "okay";
> +
> + mcp251x0: mcp251x at 1 {
> + compatible = "microchip,mcp2515";
> + reg = <0>;
> + clocks = <&clk16m>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <27 0x2>;
> + spi-max-frequency = <10000000>;
> + status = "okay";
> + };
> +};
> +
> +&hdmi {
> + status = "okay";
> +};
> +
> +/*
> + * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier
> board)
> + */
> +&i2c3 {
> + status = "okay";
> +
> + /* M41T0M6 real time clock on carrier board */
> + rtc_i2c: rtc at 68 {
> + compatible = "st,m41t00";
> + reg = <0x68>;
> + };
> +};
> +
> +&ipu1_di0_disp0 {
> + remote-endpoint = <&lcd_display_in>;
> +};
> +
> +&pwm1 {
> + status = "okay";
> +};
> +
> +&pwm2 {
> + status = "okay";
> +};
> +
> +&pwm3 {
> + status = "okay";
> +};
> +
> +&pwm4 {
> + status = "okay";
> +};
> +
> +®_usb_host_vbus {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> +
> +&usbh1 {
> + vbus-supply = <®_usb_host_vbus>;
> + status = "okay";
> +};
> +
> +&usbotg {
> + status = "okay";
> +};
> +
> +/* Colibri MMC */
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mmc_cd>;
> + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
> + status = "okay";
> +};
> +
> +&weim {
> + status = "okay";
> +
> + /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */
> + ranges = <0 0 0x08000000 0x02000000
> + ??1 0 0x0a000000 0x02000000
> + ??2 0 0x0c000000 0x02000000>;
> +
> + /* SRAM on Colibri nEXT_CS0 */
> + sram at 0,0 {
> + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
> + reg = <0 0 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bank-width = <2>;
> + fsl,weim-cs-timing = <0x00010081 0x00000000
> 0x04000000
> + ??????0x00000000 0x04000040
> 0x00000000>;
> + };
> +
> + /* SRAM on Colibri nEXT_CS1 */
> + sram at 1,0 {
> + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
> + reg = <1 0 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bank-width = <2>;
> + fsl,weim-cs-timing = <0x00010081 0x00000000
> 0x04000000
> + ??????0x00000000 0x04000040
> 0x00000000>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> new file mode 100644
> index 0000000..e6faa65
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> @@ -0,0 +1,890 @@
> +/*
> + * Copyright 2014-2016 Toradex AG
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this
> dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *??a) This file is free software; you can redistribute it and/or
> + *?????modify it under the terms of the GNU General Public License
> + *?????version 2 as published by the Free Software Foundation.
> + *
> + *?????This file is distributed in the hope that it will be useful
> + *?????but WITHOUT ANY WARRANTY; without even the implied warranty
> of
> + *?????MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.??See the
> + *?????GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + *??b) Permission is hereby granted, free of charge, to any person
> + *?????obtaining a copy of this software and associated
> documentation
> + *?????files (the "Software"), to deal in the Software without
> + *?????restriction, including without limitation the rights to use
> + *?????copy, modify, merge, publish, distribute, sublicense, and/or
> + *?????sell copies of the Software, and to permit persons to whom
> the
> + *?????Software is furnished to do so, subject to the following
> + *?????conditions:
> + *
> + *?????The above copyright notice and this permission notice shall
> be
> + *?????included in all copies or substantial portions of the
> Software.
> + *
> + *?????THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + *?????EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> + *?????OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *?????NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *?????HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + *?????WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *?????FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *?????OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Toradex Colibri iMX6DL/S Module";
> + compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_bl_on>;
> + pwms = <&pwm3 0 5000000>;
> + enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /*
> Colibri BL_ON */
> + status = "disabled";
> + };
> +
> + reg_1p8v: regulator-1p8v {
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + reg_2p5v: regulator-2p5v {
> + compatible = "regulator-fixed";
> + regulator-name = "2P5V";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-always-on;
> + };
> +
> + reg_3p3v: regulator-3p3v {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reg_usb_host_vbus: regulator-usb-host-vbus {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
> + regulator-name = "usb_host_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
> + status = "disabled";
> + };
> +
> + sound {
> + compatible = "fsl,imx-audio-sgtl5000";
> + model = "imx6dl-colibri-sgtl5000";
> + ssi-controller = <&ssi1>;
> + audio-codec = <&codec>;
> + audio-routing =
> + "Headphone Jack", "HP_OUT",
> + "LINE_IN", "Line In Jack",
> + "MIC_IN", "Mic Jack",
> + "Mic Jack", "Mic Bias";
> + mux-int-port = <1>;
> + mux-ext-port = <5>;
> + };
> +
> + /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137
> or 168 */
> + sound_spdif: sound-spdif {
> + compatible = "fsl,imx-audio-spdif";
> + model = "imx-spdif";
> + spdif-controller = <&spdif>;
> + spdif-in;
> + spdif-out;
> + status = "disabled";
> + };
> +};
> +
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
> + status = "okay";
> +};
> +
> +/* Optional on SODIMM 55/63 */
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + status = "disabled";
> +};
> +
> +/* Optional on SODIMM 178/188 */
> +&can2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + status = "disabled";
> +};
> +
> +/* Colibri SSP */
> +&ecspi4 {
> + fsl,spi-num-chipselects = <1>;
> + cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi4>;
> + status = "disabled";
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rmii";
> + status = "okay";
> +};
> +
> +&hdmi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hdmi_ddc>;
> + status = "disabled";
> +};
> +
> +/*
> + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
> + * touch screen controller
> + */
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +
> + pmic: pfuze100 at 08 {
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> +
> + regulators {
> + sw1a_reg: sw1ab {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw1c_reg: sw1c {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw3a_reg: sw3a {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + swbst_reg: swbst {
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + snvs_reg: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vref_reg: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* vgen1: unused */
> +
> + vgen2_reg: vgen2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* vgen3: unused */
> +
> + vgen4_reg: vgen4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vgen5_reg: vgen5 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vgen6_reg: vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + codec: sgtl5000 at 0a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + clocks = <&clks IMX6QDL_CLK_CKO>;
> + VDDA-supply = <®_2p5v>;
> + VDDIO-supply = <®_3p3v>;
> + };
> +
> + /* STMPE811 touch screen controller */
> + stmpe811 at 41 {
> + compatible = "st,stmpe811";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_touch_int>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x41>;
> + interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-parent = <&gpio6>;
> + interrupt-controller;
> + id = <0>;
> + blocks = <0x5>;
> + irq-trigger = <0x1>;
> +
> + stmpe_touchscreen {
> + compatible = "st,stmpe-ts";
> + reg = <0>;
> + /* 3.25 MHz ADC clock speed */
> + st,adc-freq = <1>;
> + /* 8 sample average control */
> + st,ave-ctrl = <3>;
> + /* 7 length fractional part in z */
> + st,fraction-z = <7>;
> + /*
> + ?* 50 mA typical 80 mA max touchscreen
> drivers
> + ?* current limit value
> + ?*/
> + st,i-drive = <1>;
> + /* 12-bit ADC */
> + st,mod-12b = <1>;
> + /* internal ADC reference */
> + st,ref-sel = <0>;
> + /* ADC converstion time: 80 clocks */
> + st,sample-time = <4>;
> + /* 1 ms panel driver settling time */
> + st,settling = <3>;
> + /* 5 ms touch detect interrupt delay */
> + st,touch-det-delay = <5>;
> + };
> + };
> +};
> +
> +/*
> + * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
> + */
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default", "recovery";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + pinctrl-1 = <&pinctrl_i2c3_recovery>;
> + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
> + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<B> */
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<D> */
> +&pwm2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<A> */
> +&pwm3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm3>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<C> */
> +&pwm4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm4>;
> + status = "disabled";
> +};
> +
> +/* Optional S/PDIF out on SODIMM 137 */
> +&spdif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spdif>;
> + status = "disabled";
> +};
> +
> +&ssi1 {
> + status = "okay";
> +};
> +
> +/* Colibri UART_A */
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
> + fsl,dte-mode;
> + uart-has-rtscts;
> + status = "disabled";
> +};
> +
> +/* Colibri UART_B */
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2_dte>;
> + fsl,dte-mode;
> + uart-has-rtscts;
> + status = "disabled";
> +};
> +
> +/* Colibri UART_C */
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3_dte>;
> + fsl,dte-mode;
> + status = "disabled";
> +};
> +
> +&usbotg {
> + pinctrl-names = "default";
> + disable-over-current;
> + dr_mode = "peripheral";
> + status = "disabled";
> +};
> +
> +/* Colibri MMC */
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + vqmmc-supply = <®_3p3v>;
> + bus-width = <4>;
> + voltage-ranges = <3300 3300>;
> + status = "disabled";
> +};
> +
> +/* eMMC */
> +&usdhc3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + vqmmc-supply = <®_3p3v>;
> + bus-width = <8>;
> + voltage-ranges = <3300 3300>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&weim {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_weim_sram??&pinctrl_weim_cs0
> + ?????&pinctrl_weim_cs1???&pinctrl_weim_cs2
> + ?????&pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> + status = "disabled";
> +};
> +
> +&iomuxc {
> + pinctrl_audmux: audmuxgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
> + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
> + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b
> 0
> + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
> + /* SGTL5000 sys_mclk */
> + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
> + >;
> + };
> +
> + pinctrl_cam_mclk: cammclkgrp {
> + fsl,pins = <
> + /* Parallel Camera CAM sys_mclk */
> + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b
> 0
> + >;
> + };
> +
> + pinctrl_ecspi4: ecspi4grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100
> b1
> + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100
> b1
> + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
> + /* SPI CS */
> + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b
> 1
> + >;
> + };
> +
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDC__ENET_MDC
> 0x1b0b0
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO
> 0x1b0b0
> + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0
> x1b0b0
> + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0
> x1b0b0
> + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1
> b0b0
> + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1
> b0b0
> + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0
> x1b0b0
> + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0
> x1b0b0
> + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x
> 1b0b0
> + MX6QDL_PAD_GPIO_16__ENET_REF_CLK?????((1<<30
> ) | 0x1b0b0)
> + >;
> + };
> +
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX
> 0x1b0b0
> + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX
> 0x1b0b0
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b
> 0b0
> + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b
> 0b0
> + >;
> + };
> +
> + pinctrl_gpio_bl_on: gpioblon {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D26__GPIO3_IO26
> 0x1b0b0
> + >;
> + };
> +
> + pinctrl_gpio_keys: gpiokeys {
> + fsl,pins = <
> + /* Power button */
> + MX6QDL_PAD_EIM_A16__GPIO2_IO22
> 0x1b0b0
> + >;
> + };
> +
> + pinctrl_hdmi_ddc: hdmiddcgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL
> 0x4001b8b1
> + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA
> 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
> + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c3_recovery: i2c3recoverygrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
> + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12
> 0xb0b1
> + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13
> 0xb0b1
> + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14
> 0xb0b1
> + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15
> 0xb0b1
> + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16
> 0xb0b1
> + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17
> 0xb0b1
> + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18
> 0xb0b1
> + MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19
> 0xb0b1
> + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK
> 0xb0b1
> + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0
> xb0b1
> + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0
> xb0b1
> + /* Disable PWM pins on camera interface */
> + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09
> 0x40
> + MX6QDL_PAD_GPIO_1__GPIO1_IO01
> 0x40
> + >;
> + };
> +
> + pinctrl_ipu1_lcdif: ipu1lcdifgrp {
> + fsl,pins = <
> + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK
> 0xa1
> + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15
> 0xa1
> + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02
> 0xa1
> + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03
> 0xa1
> + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00
> 0xa1
> + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01
> 0xa1
> + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02
> 0xa1
> + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03
> 0xa1
> + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04
> 0xa1
> + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05
> 0xa1
> + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06
> 0xa1
> + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07
> 0xa1
> + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08
> 0xa1
> + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09
> 0xa1
> + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10
> 0xa1
> + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11
> 0xa1
> + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12
> 0xa1
> + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13
> 0xa1
> + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14
> 0xa1
> + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15
> 0xa1
> + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16
> 0xa1
> + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17
> 0xa1
> + >;
> + };
> +
> + pinctrl_mic_gnd: gpiomicgnd {
> + fsl,pins = <
> + /* Controls Mic GND, PU or '1' pull Mic GND
> to GND */
> + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
> + >;
> + };
> +
> + pinctrl_mmc_cd: gpiommccd {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x800
> 00000
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
> + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0004
> 0
> + >;
> + };
> +
> + pinctrl_pwm3: pwm3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
> + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0004
> 0
> + >;
> + };
> +
> + pinctrl_pwm4: pwm4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
> + fsl,pins = <
> + /* USBH_EN */
> + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f05
> 8
> + >;
> + };
> +
> + pinctrl_spdif: spdifgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
> + >;
> + };
> +
> + pinctrl_touch_int: gpiotouchintgrp {
> + fsl,pins = <
> + /* STMPE811 interrupt */
> + MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
> + >;
> + };
> +
> + pinctrl_uart1_dce: uart1dcegrp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + /* DTE mode */
> + pinctrl_uart1_dte: uart1dtegrp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0
> b1
> + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
> + >;
> + };
> +
> + /* Additional DTR, DSR, DCD */
> + pinctrl_uart1_ctrl: uart1ctrlgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
> + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
> + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
> + >;
> + };
> +
> + pinctrl_uart2_dte: uart2dtegrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x
> 1b0b1
> + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x
> 1b0b1
> + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b
> 0b1
> + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b
> 0b1
> + >;
> + };
> +
> + pinctrl_uart3_dte: uart3dtegrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1
> b0b1
> + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1
> b0b1
> + >;
> + };
> +
> + pinctrl_usbc_det: usbcdetgrp {
> + fsl,pins = <
> + /* USBC_DET */
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12
> 0x1b0b0
> + /* USBC_DET_EN */
> + MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0
> x0f058
> + /* USBC_DET_OVERWRITE */
> + MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f
> 058
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
> + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
> + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x1707
> 1
> + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x1707
> 1
> + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x1707
> 1
> + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x1707
> 1
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x1705
> 9
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x1705
> 9
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x1705
> 9
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x1705
> 9
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x1705
> 9
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x1705
> 9
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x1705
> 9
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x1705
> 9
> + /* eMMC reset */
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b
> 9
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b
> 9
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b
> 9
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b
> 9
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b
> 9
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b
> 9
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b
> 9
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b
> 9
> + /* eMMC reset */
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
> + >;
> + };
> +
> + pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f
> 9
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f
> 9
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f
> 9
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f
> 9
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f
> 9
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f
> 9
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f
> 9
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f
> 9
> + /* eMMC reset */
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
> + >;
> + };
> +
> + pinctrl_weim_cs0: weimcs0grp {
> + fsl,pins = <
> + /* nEXT_CS0 */
> + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_cs1: weimcs1grp {
> + fsl,pins = <
> + /* nEXT_CS1 */
> + MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_cs2: weimcs2grp {
> + fsl,pins = <
> + /* nEXT_CS2 */
> + MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_sram: weimsramgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_OE__EIM_OE_B 0
> xb0b1
> + MX6QDL_PAD_EIM_RW__EIM_RW 0xb
> 0b1
> + /* Data */
> + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0
> x1b0b0
> + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1
> b0b0
> + MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b
> 0b0
> + MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b
> 0b0
> + MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b
> 0b0
> + MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b
> 0b0
> + MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b
> 0b0
> + MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b
> 0b0
> + MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1
> b0b0
> + MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1
> b0b0
> + MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1
> b0b0
> + MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1
> b0b0
> + MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1
> b0b0
> + MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1
> b0b0
> + MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1
> b0b0
> + MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1
> b0b0
> + /* Address */
> + MX6QDL_PAD_EIM_DA15__EIM_AD15
> 0xb0b1
> + MX6QDL_PAD_EIM_DA14__EIM_AD14
> 0xb0b1
> + MX6QDL_PAD_EIM_DA13__EIM_AD13
> 0xb0b1
> + MX6QDL_PAD_EIM_DA12__EIM_AD12
> 0xb0b1
> + MX6QDL_PAD_EIM_DA11__EIM_AD11
> 0xb0b1
> + MX6QDL_PAD_EIM_DA10__EIM_AD10
> 0xb0b1
> + MX6QDL_PAD_EIM_DA9__EIM_AD09
> 0xb0b1
> + MX6QDL_PAD_EIM_DA8__EIM_AD08
> 0xb0b1
> + MX6QDL_PAD_EIM_DA7__EIM_AD07
> 0xb0b1
> + MX6QDL_PAD_EIM_DA6__EIM_AD06
> 0xb0b1
> + MX6QDL_PAD_EIM_DA5__EIM_AD05
> 0xb0b1
> + MX6QDL_PAD_EIM_DA4__EIM_AD04
> 0xb0b1
> + MX6QDL_PAD_EIM_DA3__EIM_AD03
> 0xb0b1
> + MX6QDL_PAD_EIM_DA2__EIM_AD02
> 0xb0b1
> + MX6QDL_PAD_EIM_DA1__EIM_AD01
> 0xb0b1
> + MX6QDL_PAD_EIM_DA0__EIM_AD00
> 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_rdnwr: weimrdnwr {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CLK__GPIO1_IO10
> 0x0040
> + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x13
> 0b0
> + >;
> + };
> +
> + pinctrl_weim_npwe: weimnpwe {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12
> 0x0040
> + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x13
> 0b0
> + >;
> + };
> +
> + /* ADDRESS[16:18] [25] used as GPIO */
> + pinctrl_weim_gpio_1: weimgpio-1 {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15
> 0x1b0b0
> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11
> 0x1b0b0
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10
> 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x
> 1b0b0
> + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x
> 1b0b0
> + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x
> 1b0b0
> + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x
> 1b0b0
> + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x
> 1b0b0
> + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x
> 1b0b0
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01
> 0x1b0b0
> + >;
> + };
> +
> + /* ADDRESS[19:24] used as GPIO */
> + pinctrl_weim_gpio_2: weimgpio-2 {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11
> 0x1b0b0
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10
> 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x
> 1b0b0
> + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x
> 1b0b0
> + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x
> 1b0b0
> + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x
> 1b0b0
> + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x
> 1b0b0
> + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x
> 1b0b0
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01
> 0x1b0b0
> + >;
> + };
> +
> + /* DATA[16:31] used as GPIO */
> + pinctrl_weim_gpio_3: weimgpio-3 {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27
> 0x1b0b0
> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31
> 0x1b0b0
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b
> 0b0
> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b
> 0b0
> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b
> 0b0
> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b
> 0b0
> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1
> b0b0
> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b
> 0b0
> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b
> 0b0
> + MX6QDL_PAD_GPIO_19__GPIO4_IO05
> 0x1b0b0
> + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b
> 0b0
> + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x
> 1b0b0
> + MX6QDL_PAD_GPIO_4__GPIO1_IO04
> 0x1b0b0
> + MX6QDL_PAD_GPIO_5__GPIO1_IO05
> 0x1b0b0
> + MX6QDL_PAD_GPIO_2__GPIO1_IO02
> 0x1b0b0
> + >;
> + };
> +
> + /* DQM[0:3] used as GPIO */
> + pinctrl_weim_gpio_4: weimgpio-4 {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28
> 0x1b0b0
> + MX6QDL_PAD_EIM_EB1__GPIO2_IO29
> 0x1b0b0
> + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13
> 0x1b0b0
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00
> 0x1b0b0
> + >;
> + };
> +
> + /* RDY used as GPIO */
> + pinctrl_weim_gpio_5: weimgpio-5 {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00
> 0x1b0b0
> + >;
> + };
> +
> + /* ADDRESS[16] DATA[30] used as GPIO */
> + pinctrl_weim_gpio_6: weimgpio-6 {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15
> 0x1b0b0
> + MX6QDL_PAD_KEY_COL4__GPIO4_IO14
> 0x1b0b0
> + >;
> + };
> +};
^ permalink raw reply
* [PATCH] arm64, numa: Add cpu_to_node() implementation.
From: Hanjun Guo @ 2016-09-27 6:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160920132120.GQ25086@rric.localdomain>
On 09/20/2016 09:21 PM, Robert Richter wrote:
> On 20.09.16 19:32:34, Hanjun Guo wrote:
>> On 09/20/2016 06:43 PM, Robert Richter wrote:
>
>>> Unfortunately either your nor my code does fix the BUG_ON() I see with
>>> the numa kernel:
>>>
>>> kernel BUG at mm/page_alloc.c:1848!
>>>
>>> See below for the core dump. It looks like this happens due to moving
>>> a mem block where first and last page are mapped to different numa
>>> nodes, thus, triggering the BUG_ON().
>>
>> Didn't triggered it on our NUMA hardware, could you provide your
>> config then we can have a try?
>
> Config attached. Other configs with an initrd fail too.
hmm, we can't reproduce it on our hardware, do we need
to run some specific stress test on it?
Thanks
Hanjun
^ permalink raw reply
* linux-next: manual merge of the gpio tree with the arm-soc tree
From: Stephen Rothwell @ 2016-09-27 5:05 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
Today's linux-next merge of the gpio tree got a conflict in:
arch/arm/mach-omap2/board-rx51-peripherals.c
between commit:
9b7141d01a76 ("ARM: OMAP2+: Drop legacy board file for n900")
from the arm-soc tree and commit:
9132ce450bd1 ("ARM: omap2: fix missing include")
from the gpio tree.
I fixed it up (the former removed the file, so I did that) and can
carry the fix as necessary. This is now fixed as far as linux-next is
concerned, but any non trivial conflicts should be mentioned to your
upstream maintainer when your tree is submitted for merging. You may
also want to consider cooperating with the maintainer of the conflicting
tree to minimise any particularly complex conflicts.
--
Cheers,
Stephen Rothwell
^ permalink raw reply
* [RFC/PATCH] usb: misc: Add a driver for TC7USB40MU
From: Peter Chen @ 2016-09-27 4:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <147491549050.5206.9497559526723777799@sboyd-linaro>
On Mon, Sep 26, 2016 at 11:44:50AM -0700, Stephen Boyd wrote:
> Quoting Peter Chen (2016-09-25 20:29:27)
> > On Thu, Sep 22, 2016 at 11:51:02AM -0700, Stephen Boyd wrote:
> > > Quoting Peter Chen (2016-09-16 18:16:05)
> > > > On Wed, Sep 14, 2016 at 01:55:02AM -0700, Stephen Boyd wrote:
> > > > > Quoting Stephen Boyd (2016-09-13 18:42:46)
> > > > > > On the db410c 96boards platform we have a TC7USB40MU[1] on the
> > > > > > board to mux the D+/D- lines from the SoC between a micro usb
> > > > > > "device" port and a USB hub for "host" roles. Upon a role switch,
> > > > > > we need to change this mux to forward the D+/D- lines to either
> > > > > > the port or the hub. Therefore, introduce a driver for this
> > > > > > device that intercepts extcon USB_HOST events and logically
> > > > > > asserts a gpio to mux the "host" D+/D- lines when a host cable is
> > > > > > attached. When the cable goes away, it will logically deassert
> > > > > > the gpio and mux the "device" lines.
> > > > > >
> > > > > > [1] https://toshiba.semicon-storage.com/ap-en/product/logic/bus-switch/detail.TC7USB40MU.html
> > > > > >
> > > > > > Cc: MyungJoo Ham <myungjoo.ham@samsung.com>
> > > > > > Cc: Chanwoo Choi <cw00.choi@samsung.com>
> > > > > > Cc: <devicetree@vger.kernel.org>
> > > > > > Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
> > > > > > ---
> > > > > >
> > > > > > Should I make the extcon part optional? I could see a case where there are two
> > > > > > "OTG" ports connected to the mux (or two hubs), and for some reason the
> > > > > > software may want to mux between them at runtime. If we mandate an extcon,
> > > > > > that won't be possible to support. Perhaps it would be better to have
> > > > > > the node, but connect it to the usb controller with a phandle (maybe of_graph
> > > > > > endpoints would be useful too) so that when the controller wants to mux over
> > > > > > a port it can do so.
> > > > >
> > > > > Here's some dts mock-up on top of the db410c for the of_graph stuff. I
> > > > > haven't written any code around it, but the idea is to allow the binding
> > > > > to specify how the mux is connected to upstream and downstream D+/D-
> > > > > lines. This way, we can do some dt parsing of the endpoints and their
> > > > > parent nodes to figure out if the mux needs to be set high or low to use
> > > > > a device connector or a usb hub based on if the id cable is present.
> > > > > Maybe I'm over thinking things though and we could just have a DT
> > > > > property for that.
> > > > >
> > > > > soc {
> > > > > usb at 78d9000 {
> > > > > extcon = <&usb_id>, <&usb_id>;
> > > >
> > > > Why you have two same extcon phandler? From my mind, one should id,
> > > > another should is vbus. Besides, I find extcon-usb-gpio.c is lack of
> > > > vbus support, how you support vbus detection for
> > > > connection/disconnection with PC for your chipidea msm patch set?
> > >
> > > This was already in the dts files for db410c. In the chipidea binding
> > > one is for EXTCON_USB (vbus) and one is for EXTCON_USB_HOST (id). My
> > > understanding is that extcon-usb-gpio.c sends events for both EXTCON_USB
> > > and EXTCON_USB_HOST when the gpio changes state. vbus detection is not
> > > that great on this board because we only have on gpio for this.
> >
> > I think extcon-usb-gpio.c needs to extend for supporting vbus event,
> > otherwise, the micro-b cable's connect/disconnect will introduce
> > EXTCON_USB_HOST event, if you use two <&usb_idx> for both id and
> > vbus event.
> >
>
> Sorry, I'm lost now. extcon-usb-gpio.c already supports EXTCON_USB as an
> event. Is the problem that we're using two of the same phandles in the
> binding?
No, ID and VBUS are different events.
http://www.spinics.net/lists/linux-usb/msg147004.html
--
Best Regards,
Peter Chen
^ permalink raw reply
* [PATCH v2 1/3] ARM: dts: imx6qdl-apalis: Do not rely on DDC I2C bus bitbang for HDMI
From: maitysanchayan at gmail.com @ 2016-09-27 4:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2263d508999ada9476268138b2922702eb50131f.1474260360.git.maitysanchayan@gmail.com>
Hello,
Ping?
- Sanchayan.
On 16-09-19 10:41:51, Sanchayan Maity wrote:
> Remove the use of DDC I2C bus bitbang to support reading of EDID
> and rely on support from internal HDMI I2C master controller instead.
> As a result remove the device tree property ddc-i2c-bus.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> ---
> Changes since v1:
>
> Change the ranking in i2c aliases
>
> v1: https://lkml.org/lkml/2016/9/14/55
> ---
> arch/arm/boot/dts/imx6q-apalis-ixora.dts | 12 +++---------
> arch/arm/boot/dts/imx6qdl-apalis.dtsi | 25 +++++++++----------------
> 2 files changed, 12 insertions(+), 25 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> index 207b85b..82b81e0 100644
> --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> @@ -55,10 +55,9 @@
> "fsl,imx6q";
>
> aliases {
> - i2c0 = &i2cddc;
> - i2c1 = &i2c1;
> - i2c2 = &i2c2;
> - i2c3 = &i2c3;
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> };
>
> aliases {
> @@ -186,11 +185,6 @@
> };
>
> &hdmi {
> - ddc-i2c-bus = <&i2cddc>;
> - status = "okay";
> -};
> -
> -&i2cddc {
> status = "okay";
> };
>
> diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> index 99e323b..8c67dd8 100644
> --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> @@ -53,18 +53,6 @@
> status = "disabled";
> };
>
> - /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */
> - i2cddc: i2c at 0 {
> - compatible = "i2c-gpio";
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_i2c_ddc>;
> - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */
> - &gpio2 30 GPIO_ACTIVE_HIGH /* scl */
> - >;
> - i2c-gpio,delay-us = <2>; /* ~100 kHz */
> - status = "disabled";
> - };
> -
> reg_1p8v: regulator-1p8v {
> compatible = "regulator-fixed";
> regulator-name = "1P8V";
> @@ -209,6 +197,12 @@
> };
> };
>
> +&hdmi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hdmi_ddc>;
> + status = "disabled";
> +};
> +
> /*
> * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
> * board)
> @@ -633,11 +627,10 @@
> >;
> };
>
> - pinctrl_i2c_ddc: gpioi2cddcgrp {
> + pinctrl_hdmi_ddc: hdmiddcgrp {
> fsl,pins = <
> - /* DDC bitbang */
> - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
> - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0
> + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
> + MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
> >;
> };
>
> --
> 2.9.3
>
^ permalink raw reply
* [PATCH] ARM: dts: imx6: Add support for Toradex Colibri iMX6 module
From: maitysanchayan at gmail.com @ 2016-09-27 4:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160921112438.8661-1-maitysanchayan@gmail.com>
Hello,
Ping?
- Sanchayan.
On 16-09-21 16:54:38, Sanchayan Maity wrote:
> Add support for Toradex Colibri iMX6 module.
>
> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 253 ++++++++
> arch/arm/boot/dts/imx6qdl-colibri.dtsi | 890 +++++++++++++++++++++++++++
> 3 files changed, 1144 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> create mode 100644 arch/arm/boot/dts/imx6qdl-colibri.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f79cac2..44ff380 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -323,6 +323,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> imx6dl-aristainetos_7.dtb \
> imx6dl-aristainetos2_4.dtb \
> imx6dl-aristainetos2_7.dtb \
> + imx6dl-colibri-eval-v3.dtb \
> imx6dl-cubox-i.dtb \
> imx6dl-dfi-fs700-m60.dtb \
> imx6dl-gw51xx.dtb \
> diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> new file mode 100644
> index 0000000..e0c2172
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> @@ -0,0 +1,253 @@
> +/*
> + * Copyright 2014-2016 Toradex AG
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This file is distributed in the hope that it will be useful
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include "imx6dl.dtsi"
> +#include "imx6qdl-colibri.dtsi"
> +
> +/ {
> + model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3";
> + compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
> + "fsl,imx6dl";
> +
> + aliases {
> + i2c0 = &i2c2;
> + i2c1 = &i2c3;
> + };
> +
> + aliases {
> + rtc0 = &rtc_i2c;
> + rtc1 = &snvs_rtc;
> + };
> +
> + clocks {
> + /* Fixed crystal dedicated to mcp251x */
> + clk16m: clk at 1 {
> + compatible = "fixed-clock";
> + reg = <1>;
> + #clock-cells = <0>;
> + clock-frequency = <16000000>;
> + clock-output-names = "clk16m";
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_keys>;
> +
> + wakeup {
> + label = "Wake-Up";
> + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
> + linux,code = <KEY_WAKEUP>;
> + debounce-interval = <10>;
> + wakeup-source;
> + };
> + };
> +
> + lcd_display: display at di0 {
> + compatible = "fsl,imx-parallel-display";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interface-pix-fmt = "bgr666";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ipu1_lcdif>;
> + status = "okay";
> +
> + port at 0 {
> + reg = <0>;
> +
> + lcd_display_in: endpoint {
> + remote-endpoint = <&ipu1_di0_disp0>;
> + };
> + };
> +
> + port at 1 {
> + reg = <1>;
> +
> + lcd_display_out: endpoint {
> + remote-endpoint = <&lcd_panel_in>;
> + };
> + };
> + };
> +
> + panel: panel {
> + /*
> + * edt,et057090dhu: EDT 5.7" LCD TFT
> + * edt,et070080dh6: EDT 7.0" LCD TFT
> + */
> + compatible = "edt,et057090dhu";
> + backlight = <&backlight>;
> +
> + port {
> + lcd_panel_in: endpoint {
> + remote-endpoint = <&lcd_display_out>;
> + };
> + };
> + };
> +};
> +
> +&backlight {
> + brightness-levels = <0 127 191 223 239 247 251 255>;
> + default-brightness-level = <1>;
> + status = "okay";
> +};
> +
> +/* Colibri SSP */
> +&ecspi4 {
> + status = "okay";
> +
> + mcp251x0: mcp251x at 1 {
> + compatible = "microchip,mcp2515";
> + reg = <0>;
> + clocks = <&clk16m>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <27 0x2>;
> + spi-max-frequency = <10000000>;
> + status = "okay";
> + };
> +};
> +
> +&hdmi {
> + status = "okay";
> +};
> +
> +/*
> + * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
> + */
> +&i2c3 {
> + status = "okay";
> +
> + /* M41T0M6 real time clock on carrier board */
> + rtc_i2c: rtc at 68 {
> + compatible = "st,m41t00";
> + reg = <0x68>;
> + };
> +};
> +
> +&ipu1_di0_disp0 {
> + remote-endpoint = <&lcd_display_in>;
> +};
> +
> +&pwm1 {
> + status = "okay";
> +};
> +
> +&pwm2 {
> + status = "okay";
> +};
> +
> +&pwm3 {
> + status = "okay";
> +};
> +
> +&pwm4 {
> + status = "okay";
> +};
> +
> +®_usb_host_vbus {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> +
> +&usbh1 {
> + vbus-supply = <®_usb_host_vbus>;
> + status = "okay";
> +};
> +
> +&usbotg {
> + status = "okay";
> +};
> +
> +/* Colibri MMC */
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mmc_cd>;
> + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
> + status = "okay";
> +};
> +
> +&weim {
> + status = "okay";
> +
> + /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */
> + ranges = <0 0 0x08000000 0x02000000
> + 1 0 0x0a000000 0x02000000
> + 2 0 0x0c000000 0x02000000>;
> +
> + /* SRAM on Colibri nEXT_CS0 */
> + sram at 0,0 {
> + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
> + reg = <0 0 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bank-width = <2>;
> + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
> + 0x00000000 0x04000040 0x00000000>;
> + };
> +
> + /* SRAM on Colibri nEXT_CS1 */
> + sram at 1,0 {
> + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
> + reg = <1 0 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bank-width = <2>;
> + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
> + 0x00000000 0x04000040 0x00000000>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> new file mode 100644
> index 0000000..e6faa65
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> @@ -0,0 +1,890 @@
> +/*
> + * Copyright 2014-2016 Toradex AG
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This file is distributed in the hope that it will be useful
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Toradex Colibri iMX6DL/S Module";
> + compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_bl_on>;
> + pwms = <&pwm3 0 5000000>;
> + enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
> + status = "disabled";
> + };
> +
> + reg_1p8v: regulator-1p8v {
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + reg_2p5v: regulator-2p5v {
> + compatible = "regulator-fixed";
> + regulator-name = "2P5V";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-always-on;
> + };
> +
> + reg_3p3v: regulator-3p3v {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reg_usb_host_vbus: regulator-usb-host-vbus {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
> + regulator-name = "usb_host_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
> + status = "disabled";
> + };
> +
> + sound {
> + compatible = "fsl,imx-audio-sgtl5000";
> + model = "imx6dl-colibri-sgtl5000";
> + ssi-controller = <&ssi1>;
> + audio-codec = <&codec>;
> + audio-routing =
> + "Headphone Jack", "HP_OUT",
> + "LINE_IN", "Line In Jack",
> + "MIC_IN", "Mic Jack",
> + "Mic Jack", "Mic Bias";
> + mux-int-port = <1>;
> + mux-ext-port = <5>;
> + };
> +
> + /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
> + sound_spdif: sound-spdif {
> + compatible = "fsl,imx-audio-spdif";
> + model = "imx-spdif";
> + spdif-controller = <&spdif>;
> + spdif-in;
> + spdif-out;
> + status = "disabled";
> + };
> +};
> +
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
> + status = "okay";
> +};
> +
> +/* Optional on SODIMM 55/63 */
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + status = "disabled";
> +};
> +
> +/* Optional on SODIMM 178/188 */
> +&can2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + status = "disabled";
> +};
> +
> +/* Colibri SSP */
> +&ecspi4 {
> + fsl,spi-num-chipselects = <1>;
> + cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi4>;
> + status = "disabled";
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rmii";
> + status = "okay";
> +};
> +
> +&hdmi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hdmi_ddc>;
> + status = "disabled";
> +};
> +
> +/*
> + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
> + * touch screen controller
> + */
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +
> + pmic: pfuze100 at 08 {
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> +
> + regulators {
> + sw1a_reg: sw1ab {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw1c_reg: sw1c {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw3a_reg: sw3a {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + swbst_reg: swbst {
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + snvs_reg: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vref_reg: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* vgen1: unused */
> +
> + vgen2_reg: vgen2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* vgen3: unused */
> +
> + vgen4_reg: vgen4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vgen5_reg: vgen5 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vgen6_reg: vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + codec: sgtl5000 at 0a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + clocks = <&clks IMX6QDL_CLK_CKO>;
> + VDDA-supply = <®_2p5v>;
> + VDDIO-supply = <®_3p3v>;
> + };
> +
> + /* STMPE811 touch screen controller */
> + stmpe811 at 41 {
> + compatible = "st,stmpe811";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_touch_int>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x41>;
> + interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-parent = <&gpio6>;
> + interrupt-controller;
> + id = <0>;
> + blocks = <0x5>;
> + irq-trigger = <0x1>;
> +
> + stmpe_touchscreen {
> + compatible = "st,stmpe-ts";
> + reg = <0>;
> + /* 3.25 MHz ADC clock speed */
> + st,adc-freq = <1>;
> + /* 8 sample average control */
> + st,ave-ctrl = <3>;
> + /* 7 length fractional part in z */
> + st,fraction-z = <7>;
> + /*
> + * 50 mA typical 80 mA max touchscreen drivers
> + * current limit value
> + */
> + st,i-drive = <1>;
> + /* 12-bit ADC */
> + st,mod-12b = <1>;
> + /* internal ADC reference */
> + st,ref-sel = <0>;
> + /* ADC converstion time: 80 clocks */
> + st,sample-time = <4>;
> + /* 1 ms panel driver settling time */
> + st,settling = <3>;
> + /* 5 ms touch detect interrupt delay */
> + st,touch-det-delay = <5>;
> + };
> + };
> +};
> +
> +/*
> + * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
> + */
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default", "recovery";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + pinctrl-1 = <&pinctrl_i2c3_recovery>;
> + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
> + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<B> */
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<D> */
> +&pwm2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<A> */
> +&pwm3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm3>;
> + status = "disabled";
> +};
> +
> +/* Colibri PWM<C> */
> +&pwm4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm4>;
> + status = "disabled";
> +};
> +
> +/* Optional S/PDIF out on SODIMM 137 */
> +&spdif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spdif>;
> + status = "disabled";
> +};
> +
> +&ssi1 {
> + status = "okay";
> +};
> +
> +/* Colibri UART_A */
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
> + fsl,dte-mode;
> + uart-has-rtscts;
> + status = "disabled";
> +};
> +
> +/* Colibri UART_B */
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2_dte>;
> + fsl,dte-mode;
> + uart-has-rtscts;
> + status = "disabled";
> +};
> +
> +/* Colibri UART_C */
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3_dte>;
> + fsl,dte-mode;
> + status = "disabled";
> +};
> +
> +&usbotg {
> + pinctrl-names = "default";
> + disable-over-current;
> + dr_mode = "peripheral";
> + status = "disabled";
> +};
> +
> +/* Colibri MMC */
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + vqmmc-supply = <®_3p3v>;
> + bus-width = <4>;
> + voltage-ranges = <3300 3300>;
> + status = "disabled";
> +};
> +
> +/* eMMC */
> +&usdhc3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + vqmmc-supply = <®_3p3v>;
> + bus-width = <8>;
> + voltage-ranges = <3300 3300>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&weim {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
> + &pinctrl_weim_cs1 &pinctrl_weim_cs2
> + &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> + status = "disabled";
> +};
> +
> +&iomuxc {
> + pinctrl_audmux: audmuxgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
> + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
> + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
> + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
> + /* SGTL5000 sys_mclk */
> + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
> + >;
> + };
> +
> + pinctrl_cam_mclk: cammclkgrp {
> + fsl,pins = <
> + /* Parallel Camera CAM sys_mclk */
> + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
> + >;
> + };
> +
> + pinctrl_ecspi4: ecspi4grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
> + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
> + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
> + /* SPI CS */
> + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
> + >;
> + };
> +
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
> + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
> + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
> + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
> + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
> + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
> + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
> + MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
> + >;
> + };
> +
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
> + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
> + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
> + >;
> + };
> +
> + pinctrl_gpio_bl_on: gpioblon {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
> + >;
> + };
> +
> + pinctrl_gpio_keys: gpiokeys {
> + fsl,pins = <
> + /* Power button */
> + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0
> + >;
> + };
> +
> + pinctrl_hdmi_ddc: hdmiddcgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
> + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
> + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c3_recovery: i2c3recoverygrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
> + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
> + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
> + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
> + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
> + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
> + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
> + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
> + MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
> + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
> + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
> + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
> + /* Disable PWM pins on camera interface */
> + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
> + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
> + >;
> + };
> +
> + pinctrl_ipu1_lcdif: ipu1lcdifgrp {
> + fsl,pins = <
> + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
> + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
> + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
> + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
> + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
> + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
> + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
> + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
> + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
> + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
> + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
> + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
> + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
> + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
> + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
> + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
> + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
> + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
> + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
> + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
> + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
> + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
> + >;
> + };
> +
> + pinctrl_mic_gnd: gpiomicgnd {
> + fsl,pins = <
> + /* Controls Mic GND, PU or '1' pull Mic GND to GND */
> + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
> + >;
> + };
> +
> + pinctrl_mmc_cd: gpiommccd {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
> + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
> + >;
> + };
> +
> + pinctrl_pwm3: pwm3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
> + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
> + >;
> + };
> +
> + pinctrl_pwm4: pwm4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
> + fsl,pins = <
> + /* USBH_EN */
> + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
> + >;
> + };
> +
> + pinctrl_spdif: spdifgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
> + >;
> + };
> +
> + pinctrl_touch_int: gpiotouchintgrp {
> + fsl,pins = <
> + /* STMPE811 interrupt */
> + MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
> + >;
> + };
> +
> + pinctrl_uart1_dce: uart1dcegrp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + /* DTE mode */
> + pinctrl_uart1_dte: uart1dtegrp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
> + >;
> + };
> +
> + /* Additional DTR, DSR, DCD */
> + pinctrl_uart1_ctrl: uart1ctrlgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
> + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
> + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
> + >;
> + };
> +
> + pinctrl_uart2_dte: uart2dtegrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
> + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
> + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
> + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart3_dte: uart3dtegrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
> + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbc_det: usbcdetgrp {
> + fsl,pins = <
> + /* USBC_DET */
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
> + /* USBC_DET_EN */
> + MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
> + /* USBC_DET_OVERWRITE */
> + MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
> + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
> + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
> + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
> + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
> + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + /* eMMC reset */
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
> + /* eMMC reset */
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
> + >;
> + };
> +
> + pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
> + /* eMMC reset */
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
> + >;
> + };
> +
> + pinctrl_weim_cs0: weimcs0grp {
> + fsl,pins = <
> + /* nEXT_CS0 */
> + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_cs1: weimcs1grp {
> + fsl,pins = <
> + /* nEXT_CS1 */
> + MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_cs2: weimcs2grp {
> + fsl,pins = <
> + /* nEXT_CS2 */
> + MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_sram: weimsramgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
> + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
> + /* Data */
> + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
> + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
> + /* Address */
> + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
> + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
> + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
> + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
> + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
> + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
> + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
> + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
> + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
> + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
> + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
> + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
> + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
> + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
> + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
> + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
> + >;
> + };
> +
> + pinctrl_weim_rdnwr: weimrdnwr {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
> + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
> + >;
> + };
> +
> + pinctrl_weim_npwe: weimnpwe {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
> + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
> + >;
> + };
> +
> + /* ADDRESS[16:18] [25] used as GPIO */
> + pinctrl_weim_gpio_1: weimgpio-1 {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
> + >;
> + };
> +
> + /* ADDRESS[19:24] used as GPIO */
> + pinctrl_weim_gpio_2: weimgpio-2 {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
> + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
> + >;
> + };
> +
> + /* DATA[16:31] used as GPIO */
> + pinctrl_weim_gpio_3: weimgpio-3 {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
> + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
> + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
> + >;
> + };
> +
> + /* DQM[0:3] used as GPIO */
> + pinctrl_weim_gpio_4: weimgpio-4 {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
> + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
> + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
> + >;
> + };
> +
> + /* RDY used as GPIO */
> + pinctrl_weim_gpio_5: weimgpio-5 {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
> + >;
> + };
> +
> + /* ADDRESS[16] DATA[30] used as GPIO */
> + pinctrl_weim_gpio_6: weimgpio-6 {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
> + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
> + >;
> + };
> +};
> --
> 2.10.0
>
^ permalink raw reply
* [PATCH -next] arm64: Kconfig: remove SMP dependence for NUMA
From: Kefeng Wang @ 2016-09-27 3:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474875410-23016-1-git-send-email-wangkefeng.wang@huawei.com>
The arm64 forces CONFIG_SMP=y with commit 4b3dc9679cf7, no need to
add SMP dependence for NUMA.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 4572f00..17c14a1d 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -579,7 +579,6 @@ config HOTPLUG_CPU
# Common NUMA Features
config NUMA
bool "Numa Memory Allocation and Scheduler Support"
- depends on SMP
select ACPI_NUMA if ACPI
select OF_NUMA
help
--
1.7.12.4
^ permalink raw reply related
* [PATCH] ARM: dts: lpc32xx: add pwm-cells to base dts file
From: Vladimir Zapolskiy @ 2016-09-26 22:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474915641-11209-1-git-send-email-slemieux.tyco@gmail.com>
Hi Sylvain,
On 26.09.2016 21:47, Sylvain Lemieux wrote:
> From: Sylvain Lemieux <slemieux@tycoint.com>
>
> There is no need to define the "pwm-cells" in the board
> specific dts file; move the entry to the base dts file.
>
> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
> ---
> Note:
> * This patch should be apply after
> "ARM: dts: lpc32xx: set default parent clock for pwm1 & pwm2"
> http://www.spinics.net/lists/arm-kernel/msg530277.html
> - There is no dependency between the patches.
>
> arch/arm/boot/dts/lpc32xx.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
> index 218d9fa..c031c94 100644
> --- a/arch/arm/boot/dts/lpc32xx.dtsi
> +++ b/arch/arm/boot/dts/lpc32xx.dtsi
> @@ -472,6 +472,7 @@
> assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
> assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
> status = "disabled";
> + #pwm-cells = <2>;
> };
>
> pwm2: pwm at 4005C004 {
> @@ -481,6 +482,7 @@
> assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
> assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
> status = "disabled";
> + #pwm-cells = <2>;
> };
>
> timer3: timer at 40060000 {
>
that's something I have done locally and in a different manner, but I haven't
published it yet, please find below a draft.
First of all from multiple places in the User's Manual you can find that there
are "two single output PWM blocks" or "the LPC32x0 provides two 8-bit PWMs" etc.
In this case it does not make sense to set PWM cells to 2 (there is only one
channel), and 1 cell for frequency is good enough, and that's the proposed
change to support it:
diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c
index a9b3cff..447ae44 100644
--- a/drivers/pwm/pwm-lpc32xx.c
+++ b/drivers/pwm/pwm-lpc32xx.c
@@ -99,6 +99,22 @@ static const struct pwm_ops lpc32xx_pwm_ops = {
.owner = THIS_MODULE,
};
+static struct pwm_device *lpc32xx_pwm_of_xlate(struct pwm_chip *pc,
+ const struct of_phandle_args *args)
+{
+ struct pwm_device *pwm;
+
+ pwm = pwm_request_from_chip(pc, 0, NULL);
+ if (IS_ERR(pwm))
+ return pwm;
+
+ pwm->args.period = args->args[0];
+
+ return pwm;
+}
+
static int lpc32xx_pwm_probe(struct platform_device *pdev)
{
struct lpc32xx_pwm_chip *lpc32xx;
@@ -123,6 +139,8 @@ static int lpc32xx_pwm_probe(struct platform_device *pdev)
lpc32xx->chip.ops = &lpc32xx_pwm_ops;
lpc32xx->chip.npwm = 1;
lpc32xx->chip.base = -1;
+ lpc32xx->chip.of_xlate = lpc32xx_pwm_of_xlate;
+ lpc32xx->chip.of_pwm_n_cells = 1;
ret = pwmchip_add(&lpc32xx->chip);
if (ret < 0) {
What is your opinion about this proposal?
If this change is applied, then lpc32xx.dtsi should contain #pwm-cells = <1>.
--
With best wishes,
Vladimir
^ permalink raw reply related
* [PATCH 4/4] ARM: sa11x0/pxa: get rid of get_clock_tick_rate
From: Russell King - ARM Linux @ 2016-09-26 21:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474312335-20997-5-git-send-email-robert.jarzmik@free.fr>
On Mon, Sep 19, 2016 at 09:12:15PM +0200, Robert Jarzmik wrote:
> The last user of this function is gone, so remove it. The clock API
> should now be used to get clock rates.
>
> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH 3/4] watchdog: sa11x0/pxa: get rid of get_clock_tick_rate
From: Russell King - ARM Linux @ 2016-09-26 21:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474312335-20997-4-git-send-email-robert.jarzmik@free.fr>
On Mon, Sep 19, 2016 at 09:12:14PM +0200, Robert Jarzmik wrote:
> The OS timer rate used for the watchdog can now be fetched from the
> standard clock API. This will remove the last user of
> get_clock_tick_rate() in both pxa and sa11x0 architectures.
>
> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Thanks.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH 2/4] ARM: sa11x0/pxa: acquire timer rate from the clock rate
From: Russell King - ARM Linux @ 2016-09-26 21:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474312335-20997-3-git-send-email-robert.jarzmik@free.fr>
On Mon, Sep 19, 2016 at 09:12:13PM +0200, Robert Jarzmik wrote:
> As both pxa and sa1100 provide a clock to the timer, the rate can be
> inferred from the clock rather than hard encoded in a functional call.
>
> This patch changes the pxa timer to have a mandatory clock which is used
> as the timer rate.
>
> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Thanks.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH] soc: rockchip: power-domain: Don't (incorrectly) set rk3399 up/down counts
From: Heiko Stuebner @ 2016-09-26 20:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1471546561-4459-1-git-send-email-dianders@chromium.org>
Am Donnerstag, 18. August 2016, 11:56:01 CEST schrieb Douglas Anderson:
> On rk3288 it was important that powerdown and powerup counts for the
> CPU/GPU in the kernel because:
> * The power on default was crazy long.
> * We couldn't rely on the firmware to set this up because really this
> wasn't the firmware's job--the kernel was the only one that really
> cared about bringing up / down CPUs and the GPU and doing suspend /
> resume (which involves bringing up / down CPUs).
>
> On newer ARM systems (like rk3399) ARM Trusted Firmware is in charge of
> bringing up and down the CPUs and it really should be in charge of
> setting all these counts right. After all ATF is in charge of suspend /
> resume and CPU up / down. Let's get out of the way and let ATF do its
> job.
>
> A few other motivations for doing this:
> * Depending on another configuration (PMU_24M_EN_CFG) these counts can
> be either in 24M or 32k cycles. Thus, though ATF isn't really so
> involved in bringing up the GPU, ATF should probably manage the counts
> for everything so it can also manage the 24M / 32k choice.
> * It turns out that (right now) 24M mode is broken on rk3399 and not
> being used. That means that the count the kernel was programming
> in (24) was not 1 us (which it seems was intended) but was actually
> .75 ms
> * On rk3399 there are actually 2 separate registers for setting CPU
> up/down time plus 1 register for GPU up/down time. The curent kernel
> code actually was putting the register for the "little" cores in the
> "CPU" slot and the register for the "big" cores in the "GPU" slot. It
> was never initting the GPU counts.
>
> Note: this change assumes that ATF will actually set these values at
> boot, as I'm proposing in <http://crosreview.com/372381>.
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
applied to my drivers branch for 4.10
Thanks
Heiko
^ permalink raw reply
* [PATCH v10 0/4] ACPI: parse the SPCR table
From: Aleksey Makarov @ 2016-09-26 19:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <98ed1e6b-0994-4429-c085-2293b4a89edf@linaro.org>
On 09/21/2016 10:22 AM, Aleksey Makarov wrote:
>
>
> On 09/21/2016 07:38 PM, Greg Kroah-Hartman wrote:
>> On Wed, Sep 21, 2016 at 11:19:35AM -0500, Timur Tabi wrote:
>>> On Wed, Sep 21, 2016 at 5:37 AM, Greg Kroah-Hartman
>>> <gregkh@linuxfoundation.org> wrote:
>>>>
>>>> I thought you asked Rafael to take them, they are not in my queue
>>>> anymore because of that. Don't try to shop-around for maintainers
>>>> please, that's kind of rude...
>>>
>>> In Aleksey's defense, these patches have been floating around for far
>>> too long, so I can understand his frustration.
>>
>> I understand the frustration as well, cross-maintainer messy patches
>> like this are hard to get merged at times at they fall between the
>> cracks a lot.
>>
>>> But as you said, I really hope Rafael picks these up for 4.9. We need
>>> these patches for ARM server.
>>
>> I thought I saw an email saying he would do so, but it might have been
>> for some other patchset, sorry...
>
> This can be for "ACPI: ARM64: support for ACPI_TABLE_UPGRADE":
>
> https://lkml.kernel.org/r/CAJZ5v0goXsQ2umcDXU0six+QtxcKGZq7mxhgxuvXTH2iZt6YNA at mail.gmail.com
>
> As for this patchset, Rafael ACKed the ACPI part:
>
> https://lkml.kernel.org/r/CAJZ5v0hdoLTfjrD8+WxSoxM48dqbZK2KwY_h+63kHKHKgO=JFA at mail.gmail.com
>
> but I can not find any acknowledge from him that he is ready to merge the series.
> On the contrary, he expressed his doubt that he is "the right maintainer to send this to":
>
> https://lkml.kernel.org/r/CAJZ5v0gzjtFzig7nEumr83+J2dGb+OA8GNR2i45ZqznfV_hA-A at mail.gmail.com
>
> I asked the ARM64 people, they said they prefer Rafael to do that:
>
> https://lkml.kernel.org/r/20160909151758.GA11418 at arm.com
>
> I interpreted the silence from Rafael as unwillingness to pull the series
> and thought it's OK to ask you.
>
> I am sorry if this looks rude for Rafael, I did not mean that.
Hi Greg,
Can you give advise on how to deal with this situation please?
It looks like Rafael does not want to pull the patches. Some time ago he wrote:
"Honestly, I'm not sure why I'm regarded as the right maintainer to send this to.
The only patch here touching generic ACPI code is [3/5] (the [2/5] is
going in through ACPICA) and the rest is all about ARM64 AFAICS. Why
don't you send it to the ARM64 maintainers instead?"
(https://lkml.kernel.org/r/CAJZ5v0gzjtFzig7nEumr83+J2dGb+OA8GNR2i45ZqznfV_hA-A at mail.gmail.com)
ARM64 maintainer said
"The series should go via Rafael, since the bulk of the changes are
outside of arch/arm64."
(https://lkml.kernel.org/r/20160909151758.GA11418 at arm.com)
So should I continue to try to reach Rafael or ask another maintainer?
Can you pull it for 4.9?
Thank you
Aleksey Makarov
>
> Thank you
> Aleksey Makarov
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* [PATCH] ARM: dts: socfpga: enable arm,shared-override in the pl310
From: dinguyen at opensource.altera.com @ 2016-09-26 19:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Enable the bit(22) shared-override bit for the SoCFPGA family. While at it,
enable the prefetch-data and prefetch-instr settings for the Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga.dtsi | 1 +
arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 9f48141..28ff6e4 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -686,6 +686,7 @@
arm,data-latency = <2 1 1>;
prefetch-data = <1>;
prefetch-instr = <1>;
+ arm,shared-override;
};
mmc: dwmmc0 at ff704000 {
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 94000cb..16fcb9f 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -573,6 +573,9 @@
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-level = <2>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+ arm,shared-override;
};
mmc: dwmmc0 at ff808000 {
--
1.7.9.5
^ permalink raw reply related
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