* [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support
From: Sergei Shtylyov @ 2016-09-28 20:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdXz5K66AU7d-+NsPrAyc8V53mDxzggiUk-TrFRAwBFXOg@mail.gmail.com>
On 09/19/2016 11:19 AM, Geert Uytterhoeven wrote:
>> --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi
>> +++ renesas/arch/arm/boot/dts/r8a7743.dtsi
>> @@ -90,6 +90,70 @@
>> #power-domain-cells = <1>;
>> };
>>
>> + dmac0: dma-controller at e6700000 {
>> + compatible = "renesas,dmac-r8a7743",
>
> To be documented.
The R-Car DMAC binding has "renesas,dmac-<soctype>" documented.
I can add the mention of RZ/G and new examples though...
> Gr{oetje,eeting}s,
>
> Geert
MBR, Sergei
^ permalink raw reply
* [PATCH V7 2/6] thermal: bcm2835: add thermal driver for bcm2835 soc
From: Eric Anholt @ 2016-09-28 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474446227-1147-3-git-send-email-kernel@martin.sperl.org>
kernel at martin.sperl.org writes:
> From: Martin Sperl <kernel@martin.sperl.org>
>
> Add basic thermal driver for bcm2835 SOC.
>
> This driver currently relies on the firmware setting up the
> tsense HW block and does not set it up itself.
>
> Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
> Acked-by: Eric Anholt <eric@anholt.net>
> Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
What's the status of merging this one? I'd like to merge the other
patches.
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* [PATCH][v2] drm/sun4i: rgb: Enable panel after controller
From: Maxime Ripard @ 2016-09-28 21:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160926102146.19129-1-net147@gmail.com>
Hi,
On Mon, Sep 26, 2016 at 08:21:45PM +1000, Jonathan Liu wrote:
> The panel should be enabled after the controller so that we do not have
> visual glitches on the panel while the controller is setup. Similarly,
> the panel should be disabled before the controller.
>
> Signed-off-by: Jonathan Liu <net147@gmail.com>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH] drm/sun4i: rgb: Enable panel after controller
From: Maxime Ripard @ 2016-09-28 21:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOw6vbKxJeSZYsCwVWYbVosZUK+FfBq1ytrpRUNpbH+kM6Ow6Q@mail.gmail.com>
Hi Sean,
On Tue, Sep 27, 2016 at 10:42:09AM -0400, Sean Paul wrote:
> As an aside, it seems like (from the diff, I haven't looked at the
> code) the bridge_pre_enable and bridge_post_disable calls are missing,
> and the enable/disable calls are in the wrong place.
You're right. I have to push more bridges support patches in the
upcoming weeks, I'll take care of that.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH v3 7/7] i2c: bcm2835: Add support for dynamic clock
From: Eric Anholt @ 2016-09-28 21:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475085056-5205-8-git-send-email-noralf@tronnes.org>
Noralf Tr?nnes <noralf@tronnes.org> writes:
> Support a dynamic clock by reading the frequency and setting the
> divisor in the transfer function instead of during probe.
Is this fixing some particular case you could note in the commit
message? As is, it makes me think that we should be using a notifier
for when the parent clock (that's the one I assume you're talking about
being dynamic) changes. But maybe you're working around a variable VPU
clock being set by the firmware, because we don't have a notifier for
it?
I'm a bit worried because I think this is going to be pretty expensive
to be doing per transfer.
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* [PATCH v3 2/7] i2c: bcm2835: Protect against unexpected TXW/RXR interrupts
From: Eric Anholt @ 2016-09-28 22:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475085056-5205-3-git-send-email-noralf@tronnes.org>
Noralf Tr?nnes <noralf@tronnes.org> writes:
> If an unexpected TXW or RXR interrupt occurs (msg_buf_remaining == 0),
> the driver has no way to fill/drain the FIFO to stop the interrupts.
> In this case the controller has to be disabled and the transfer
> completed to avoid hang.
>
> (CLKT | ERR) and DONE interrupts are completed in their own paths, and
> the controller is disabled in the transfer function after completion.
> Unite the code paths and do disabling inside the interrupt routine.
>
> Clear interrupt status bits in the united completion path instead of
> trying to do it on every interrupt which isn't necessary.
> Only CLKT, ERR and DONE can be cleared that way.
>
> Add the status value to the error value in case of TXW/RXR errors to
> distinguish them from the other S_LEN error.
I was surprised that not writing the TXW/RXR bits on handling their
interrupts was OK, given that we were doing so before, but it's a level
interrupt and those bits are basically ignored on write.
This patch and 3, 4, and 6 are:
Reviewed-by: Eric Anholt <eric@anholt.net>
Patch 5 is:
Acked-by: Eric Anholt <eric@anholt.net>
Note for future debug: The I2C_C_CLEAR on errors will take some time to
resolve -- if you were in non-idle state and I2C_C_READ, it sets an
abort_rx flag and runs through the state machine to send a NACK and a
STOP, I think. Since we're setting CLEAR without I2CEN, that NACK will
be hanging around queued up for next time we start the engine.
Patch 7 I had questions about but probably will send an ack when you
reply.
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* [PATCH v1] ARM: decompressor: reset ttbcr fields to use TTBR0 on ARMv7
From: Russell King - ARM Linux @ 2016-09-28 22:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475066728-27290-1-git-send-email-sramana@codeaurora.org>
On Wed, Sep 28, 2016 at 06:15:28PM +0530, Srinivas Ramana wrote:
> If the bootloader uses the long descriptor format and jumps to
> kernel decompressor code, TTBCR may not be in a right state.
> Before enabling the MMU, it is required to clear the TTBCR.PD0
> field to use TTBR0 for translation table walks.
>
> The commit dbece45894d3a ("ARM: 7501/1: decompressor:
> reset ttbcr for VMSA ARMv7 cores") does the reset of TTBCR.N, but
> doesn't consider all the bits for the size of TTBCR.N.
>
> Clear TTBCR.PD0 field and reset all the three bits of TTBCR.N to
> indicate the use of TTBR0 and the correct base address width.
>
> Fixes: dbece45894d3 ("ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores")
> Acked-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Please submit to the patch system, thanks.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [PATCH v3 7/7] i2c: bcm2835: Add support for dynamic clock
From: Noralf Trønnes @ 2016-09-28 22:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87r383g1kb.fsf@eliezer.anholt.net>
Den 28.09.2016 23:24, skrev Eric Anholt:
> Noralf Tr?nnes <noralf@tronnes.org> writes:
>
>> Support a dynamic clock by reading the frequency and setting the
>> divisor in the transfer function instead of during probe.
> Is this fixing some particular case you could note in the commit
> message? As is, it makes me think that we should be using a notifier
> for when the parent clock (that's the one I assume you're talking about
> being dynamic) changes. But maybe you're working around a variable VPU
> clock being set by the firmware, because we don't have a notifier for
> it?
>
> I'm a bit worried because I think this is going to be pretty expensive
> to be doing per transfer.
Actually I thought that this was a known problem, but trying to track
it down now, I can't find anything definitive. I don't have any tool
to look at the bus signals, so I couldn't actually test it.
Sorry about this, we can just drop this patch.
Noralf.
^ permalink raw reply
* [PATCH v3 2/7] i2c: bcm2835: Protect against unexpected TXW/RXR interrupts
From: Noralf Trønnes @ 2016-09-28 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87oa37fzx6.fsf@eliezer.anholt.net>
Den 29.09.2016 00:00, skrev Eric Anholt:
> Noralf Tr?nnes <noralf@tronnes.org> writes:
>
>> If an unexpected TXW or RXR interrupt occurs (msg_buf_remaining == 0),
>> the driver has no way to fill/drain the FIFO to stop the interrupts.
>> In this case the controller has to be disabled and the transfer
>> completed to avoid hang.
>>
>> (CLKT | ERR) and DONE interrupts are completed in their own paths, and
>> the controller is disabled in the transfer function after completion.
>> Unite the code paths and do disabling inside the interrupt routine.
>>
>> Clear interrupt status bits in the united completion path instead of
>> trying to do it on every interrupt which isn't necessary.
>> Only CLKT, ERR and DONE can be cleared that way.
>>
>> Add the status value to the error value in case of TXW/RXR errors to
>> distinguish them from the other S_LEN error.
> I was surprised that not writing the TXW/RXR bits on handling their
> interrupts was OK, given that we were doing so before, but it's a level
> interrupt and those bits are basically ignored on write.
>
> This patch and 3, 4, and 6 are:
>
> Reviewed-by: Eric Anholt <eric@anholt.net>
>
> Patch 5 is:
>
> Acked-by: Eric Anholt <eric@anholt.net>
>
> Note for future debug: The I2C_C_CLEAR on errors will take some time to
> resolve -- if you were in non-idle state and I2C_C_READ, it sets an
> abort_rx flag and runs through the state machine to send a NACK and a
> STOP, I think. Since we're setting CLEAR without I2CEN, that NACK will
> be hanging around queued up for next time we start the engine.
Maybe you're able to explain the issues I had with reset:
https://github.com/raspberrypi/linux/issues/1653
Should we put your note into the commit message?
It will most likely be lost if it just stays in this email.
Noralf.
^ permalink raw reply
* [PATCH v19 05/12] fpga-mgr: add fpga image information struct
From: Moritz Fischer @ 2016-09-28 23:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160928182200.15800-6-atull@opensource.altera.com>
Hi Alan,
generally ok with the change.
On Wed, Sep 28, 2016 at 11:21 AM, Alan Tull <atull@opensource.altera.com> wrote:
> -int fpga_mgr_buf_load(struct fpga_manager *mgr, u32 flags, const char *buf,
> - size_t count)
> +int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
> + const char *buf, size_t count)
Doesn't this break the both socfpga and zynq if [6/12] and [7/12] are
not part of this commit?
i.e shouldn't 5,6 and 7 be a single commit?
Cheers,
Moritz
^ permalink raw reply
* [RFC PATCH 0/3] efi: MMC proxy support for the UEFI varstore
From: Arnd Bergmann @ 2016-09-28 23:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474543806-19210-1-git-send-email-ard.biesheuvel@linaro.org>
On Thursday 22 September 2016, Ard Biesheuvel wrote:
> ================================================================================
> NOTE: this is a work in progress, and not fully functional yet. In particular,
> the actual MMC host protocol methods are stubbed out at the moment, and need to
> be wired up to the Linux device drivers.
> ================================================================================
>
> On mobile and embedded systems, there is usually only a single MMC device for
> non-volatile storage, which sits behind a controller that is owned by the OS at
> runtime. This makes it difficult to host the UEFI variable store on MMC as well,
> since the UEFI runtime services routines expect ownership of the underlying
> device as well.
>
> This series proposes an approach to work around this. It implements the UEFI
> MMC host protocol in the kernel, in a way that makes it possible to expose it
> to the firmware. At the same time, the firmware needs be set up for this, i.e.,
> it needs to expose its MMC host protocol pointer via a UEFI configuration table,
> so that the kernel can override it if it decides to expose this functionality
> to the firmware.
>
> Note that these patches are based on patches in the EFI tree that are queued
> for v4.9, which replace the runtime wrappers spinlock with a semaphore. This
> allows us to sleep in the firmware callbacks.
Would it be possible to implement the UEFI varstore more generally on top
of the Linux pstore interface and then have a pstore backend on top of
MMC? That could give us very similar behavior, but also a bit more flexibility.
It would be a bit confusing to have the 'dmesg' pstore target on top of
UEFI varstore which in turn is on top of pstore on MMC, but I think that's
ok as long as we prevent recursion.
Arnd
^ permalink raw reply
* [RFC PATCH 0/3] efi: MMC proxy support for the UEFI varstore
From: Ard Biesheuvel @ 2016-09-29 0:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201609290154.34433.arnd@arndb.de>
On 28 September 2016 at 16:54, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thursday 22 September 2016, Ard Biesheuvel wrote:
>> ================================================================================
>> NOTE: this is a work in progress, and not fully functional yet. In particular,
>> the actual MMC host protocol methods are stubbed out at the moment, and need to
>> be wired up to the Linux device drivers.
>> ================================================================================
>>
>> On mobile and embedded systems, there is usually only a single MMC device for
>> non-volatile storage, which sits behind a controller that is owned by the OS at
>> runtime. This makes it difficult to host the UEFI variable store on MMC as well,
>> since the UEFI runtime services routines expect ownership of the underlying
>> device as well.
>>
>> This series proposes an approach to work around this. It implements the UEFI
>> MMC host protocol in the kernel, in a way that makes it possible to expose it
>> to the firmware. At the same time, the firmware needs be set up for this, i.e.,
>> it needs to expose its MMC host protocol pointer via a UEFI configuration table,
>> so that the kernel can override it if it decides to expose this functionality
>> to the firmware.
>>
>> Note that these patches are based on patches in the EFI tree that are queued
>> for v4.9, which replace the runtime wrappers spinlock with a semaphore. This
>> allows us to sleep in the firmware callbacks.
>
> Would it be possible to implement the UEFI varstore more generally on top
> of the Linux pstore interface and then have a pstore backend on top of
> MMC? That could give us very similar behavior, but also a bit more flexibility.
> It would be a bit confusing to have the 'dmesg' pstore target on top of
> UEFI varstore which in turn is on top of pstore on MMC, but I think that's
> ok as long as we prevent recursion.
>
The reason for choosing MMC over block I/O or other more generic
interfaces is that it should also allow firmware implementations that
support UEFI secure boot using RPMB/MMC, where the authentication and
the RPMB related crypto are performed by a secure world component that
talks to the firmware directly.
^ permalink raw reply
* [PATCH 1/8] pinctrl: aspeed: "Not enabled" is a significant mux state
From: Joel Stanley @ 2016-09-29 0:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a2fce70d4285ec2321a64a4f7145ea8a90d988b3.1474986045.git-series.andrew@aj.id.au>
On Wed, Sep 28, 2016 at 12:20 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> Consider a scenario with one pin P that has two signals A and B, where A
> is defined to be higher priority than B: That is, if the mux IP is in a
> state that would consider both A and B to be active on P, then A will be
> the active signal.
>
> To instead configure B as the active signal we must configure the mux so
> that A is inactive. The mux state for signals can be described by
> logical operations on one or more bits from one or more registers (a
> "signal expression"), which in some cases leads to aliased mux states for
> a particular signal. Further, signals described by multi-bit bitfields
> often do not only need to record the states that would make them active
> (the "enable" expressions), but also the states that makes them inactive
> (the "disable" expressions). All of this combined leads to four possible
> states for a signal:
>
> 1. A signal is active with respect to an "enable" expression
> 2. A signal is not active with respect to an "enable" expression
> 3. A signal is inactive with respect to a "disable" expression
> 4. A signal is not inactive with respect to a "disable" expression
>
> In the case of P, if we are looking to activate B without explicitly
> having configured A it's enough to consider A inactive if all of A's
> "enable" signal expressions evaluate to "not active". If any evaluate to
> "active" then the corresponding "disable" states must be applied so it
> becomes inactive.
>
> For example, on the AST2400 the pins composing GPIO bank H provide
> signals ROMD8 through ROMD15 (high priority) and those for UART6 (low
> priority). The mux states for ROMD8 through ROMD15 are aliased, i.e.
> there are two mux states that result in the respective signals being
> configured:
>
> A. SCU90[6]=1
> B. Strap[4,1:0]=100
>
> Further, the second mux state is a 3-bit bitfield that explicitly
> defines the enabled state but the disabled state is implicit, i.e. if
> Strap[4,1:0] is not exactly "100" then ROMD8 through ROMD15 are not
> considered active. This requires the mux function evaluation logic to
> use approach 2. above, however the existing code was using approach 3.
> The problem was brought to light on the Palmetto machines where the
> strap register value is 0x120ce416, and prevented GPIO requests in bank
> H from succeeding despite the hardware being in a position to allow
> them.
>
> Fixes: 318398c09a8d ("pinctrl: Add core pinctrl support for Aspeed SoCs")
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
That's a decent commit message.
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/pinctrl/aspeed/pinctrl-aspeed.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
> index 0391f9f13f3e..49aeba912531 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
> @@ -166,13 +166,9 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
> bool enable, struct regmap *map)
> {
> int i;
> - bool ret;
> -
> - ret = aspeed_sig_expr_eval(expr, enable, map);
> - if (ret)
> - return ret;
>
> for (i = 0; i < expr->ndescs; i++) {
> + bool ret;
> const struct aspeed_sig_desc *desc = &expr->descs[i];
> u32 pattern = enable ? desc->enable : desc->disable;
>
> @@ -199,12 +195,18 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
> static bool aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr,
> struct regmap *map)
> {
> + if (aspeed_sig_expr_eval(expr, true, map))
> + return true;
> +
> return aspeed_sig_expr_set(expr, true, map);
> }
>
> static bool aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr,
> struct regmap *map)
> {
> + if (!aspeed_sig_expr_eval(expr, true, map))
> + return true;
> +
> return aspeed_sig_expr_set(expr, false, map);
> }
>
> --
> git-series 0.8.10
^ permalink raw reply
* [PATCH 2/8] pinctrl: aspeed-g5: Fix names of GPID2 pins
From: Joel Stanley @ 2016-09-29 0:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <69eda17c16684f4212a9f3e64d9587abfcc7ae74.1474986045.git-series.andrew@aj.id.au>
On Wed, Sep 28, 2016 at 12:20 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> Fixes simple typos in the initial commit. There is no behavioural
> change.
>
> Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver)
> Reported-by: Xo Wang <xow@google.com>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> index e1ab864e1a7f..14639834a5eb 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> @@ -151,21 +151,21 @@ FUNC_GROUP_DECL(GPID0, F19, E21);
>
> #define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
>
> -#define D20 26
> +#define F20 26
> SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
> SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC);
> SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC);
> SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID);
> -MS_PIN_DECL(D20, GPIOD2, SD2DAT0, GPID2IN);
> +MS_PIN_DECL(F20, GPIOD2, SD2DAT0, GPID2IN);
>
> -#define D21 27
> +#define D20 27
> SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
> SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC);
> SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC);
> SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID);
> -MS_PIN_DECL(D21, GPIOD3, SD2DAT1, GPID2OUT);
> +MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT);
>
> -FUNC_GROUP_DECL(GPID2, D20, D21);
> +FUNC_GROUP_DECL(GPID2, F20, D20);
>
> #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21)
> #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
> @@ -614,7 +614,6 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(D10),
> ASPEED_PINCTRL_PIN(D2),
> ASPEED_PINCTRL_PIN(D20),
> - ASPEED_PINCTRL_PIN(D21),
> ASPEED_PINCTRL_PIN(D4),
> ASPEED_PINCTRL_PIN(D5),
> ASPEED_PINCTRL_PIN(D6),
> @@ -630,6 +629,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(E7),
> ASPEED_PINCTRL_PIN(E9),
> ASPEED_PINCTRL_PIN(F19),
> + ASPEED_PINCTRL_PIN(F20),
> ASPEED_PINCTRL_PIN(F9),
> ASPEED_PINCTRL_PIN(H20),
> ASPEED_PINCTRL_PIN(L1),
> --
> git-series 0.8.10
^ permalink raw reply
* [PATCH 3/8] pinctrl: aspeed-g5: Fix GPIOE1 typo
From: Joel Stanley @ 2016-09-29 0:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9364de84d3be30a5349298e219ca827d176d7ba8.1474986045.git-series.andrew@aj.id.au>
On Wed, Sep 28, 2016 at 12:20 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> This prevented C20 from successfully being muxed as GPIO.
>
> Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver)
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> index 14639834a5eb..235d929e74fd 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> @@ -182,7 +182,7 @@ SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
> SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
> SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
> SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
> -MS_PIN_DECL(C20, GPIE0, NDCD3, GPIE0OUT);
> +MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
>
> FUNC_GROUP_DECL(GPIE0, B20, C20);
>
> --
> git-series 0.8.10
^ permalink raw reply
* [PATCH 4/8] pinctrl: aspeed-g5: Fix pin association of SPI1 function
From: Joel Stanley @ 2016-09-29 0:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <bdd34f8c4bfabbc1d3cd05a66ac8734da514b1e5.1474986045.git-series.andrew@aj.id.au>
On Wed, Sep 28, 2016 at 12:20 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> The SPI1 function was associated with the wrong pins: The functions that
> those pins provide is either an SPI debug or passthrough function
> coupled to SPI1. Make the SPI1 mux function configure the relevant pins
> and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins
> that were already defined.
>
> The notation used in the datasheet's multi-function pin table for the SoC is
> often creative: in this case the SYS* signals are enabled by a single bit,
> which is nothing unusual on its own, but in this case the bit was also
> participating in a multi-bit bitfield and therefore represented multiple
> functions. This fact was overlooked in the original patch.
>
> Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver)
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 4 +-
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 86 ++++++-
> 2 files changed, 81 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> index 5e60ad18f147..2ad18c4ea55c 100644
> --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> @@ -43,7 +43,9 @@ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
>
> GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
> I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
> -RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8
> +RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
> +TIMER7 TIMER8 VGABIOSROM
> +
>
> Examples:
>
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> index 235d929e74fd..c8c72e8259d3 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> @@ -186,24 +186,84 @@ MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
>
> FUNC_GROUP_DECL(GPIE0, B20, C20);
>
> -#define SPI1_DESC SIG_DESC_SET(HW_STRAP1, 13)
> +#define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
> +#define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
> +#define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
> +
> #define C18 64
> -SIG_EXPR_LIST_DECL_SINGLE(SYSCS, SPI1, COND1, SPI1_DESC);
> +SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
> +SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU);
> SS_PIN_DECL(C18, GPIOI0, SYSCS);
>
> #define E15 65
> -SIG_EXPR_LIST_DECL_SINGLE(SYSCK, SPI1, COND1, SPI1_DESC);
> +SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
> +SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU);
> SS_PIN_DECL(E15, GPIOI1, SYSCK);
>
> -#define A14 66
> -SIG_EXPR_LIST_DECL_SINGLE(SYSMOSI, SPI1, COND1, SPI1_DESC);
> -SS_PIN_DECL(A14, GPIOI2, SYSMOSI);
> +#define B16 66
> +SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
> +SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
> +SS_PIN_DECL(B16, GPIOI2, SYSMOSI);
>
> #define C16 67
> -SIG_EXPR_LIST_DECL_SINGLE(SYSMISO, SPI1, COND1, SPI1_DESC);
> +SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
> +SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
> SS_PIN_DECL(C16, GPIOI3, SYSMISO);
>
> -FUNC_GROUP_DECL(SPI1, C18, E15, A14, C16);
> +#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
> +
> +#define B15 68
> +SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC);
> +SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
> +SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1),
> + SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
> + SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
> +SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC);
> +MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS);
> +
> +#define C15 69
> +SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC);
> +SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
> +SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1),
> + SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
> + SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
> +SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC);
> +MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK);
> +
> +#define A14 70
> +SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC);
> +SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
> +SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1),
> + SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
> + SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
> +SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC);
> +MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI);
> +
> +#define A15 71
> +SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC);
> +SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
> +SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1),
> + SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
> + SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
> +SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC);
> +MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO);
> +
> +FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
> +FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
> +FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
> +FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
> +
> +#define R2 72
> +SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
> +SS_PIN_DECL(R2, GPIOJ0, SGPMCK);
>
> #define L2 73
> SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
> @@ -580,6 +640,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(A12),
> ASPEED_PINCTRL_PIN(A13),
> ASPEED_PINCTRL_PIN(A14),
> + ASPEED_PINCTRL_PIN(A15),
> ASPEED_PINCTRL_PIN(A2),
> ASPEED_PINCTRL_PIN(A3),
> ASPEED_PINCTRL_PIN(A4),
> @@ -592,6 +653,8 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(B12),
> ASPEED_PINCTRL_PIN(B13),
> ASPEED_PINCTRL_PIN(B14),
> + ASPEED_PINCTRL_PIN(B15),
> + ASPEED_PINCTRL_PIN(B16),
> ASPEED_PINCTRL_PIN(B2),
> ASPEED_PINCTRL_PIN(B20),
> ASPEED_PINCTRL_PIN(B3),
> @@ -603,6 +666,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(C12),
> ASPEED_PINCTRL_PIN(C13),
> ASPEED_PINCTRL_PIN(C14),
> + ASPEED_PINCTRL_PIN(C15),
> ASPEED_PINCTRL_PIN(C16),
> ASPEED_PINCTRL_PIN(C18),
> ASPEED_PINCTRL_PIN(C2),
> @@ -691,11 +755,14 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
> ASPEED_PINCTRL_GROUP(RMII2),
> ASPEED_PINCTRL_GROUP(SD1),
> ASPEED_PINCTRL_GROUP(SPI1),
> + ASPEED_PINCTRL_GROUP(SPI1DEBUG),
> + ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
> ASPEED_PINCTRL_GROUP(TIMER4),
> ASPEED_PINCTRL_GROUP(TIMER5),
> ASPEED_PINCTRL_GROUP(TIMER6),
> ASPEED_PINCTRL_GROUP(TIMER7),
> ASPEED_PINCTRL_GROUP(TIMER8),
> + ASPEED_PINCTRL_GROUP(VGABIOSROM),
> };
>
> static const struct aspeed_pin_function aspeed_g5_functions[] = {
> @@ -733,11 +800,14 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
> ASPEED_PINCTRL_FUNC(RMII2),
> ASPEED_PINCTRL_FUNC(SD1),
> ASPEED_PINCTRL_FUNC(SPI1),
> + ASPEED_PINCTRL_FUNC(SPI1DEBUG),
> + ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
> ASPEED_PINCTRL_FUNC(TIMER4),
> ASPEED_PINCTRL_FUNC(TIMER5),
> ASPEED_PINCTRL_FUNC(TIMER6),
> ASPEED_PINCTRL_FUNC(TIMER7),
> ASPEED_PINCTRL_FUNC(TIMER8),
> + ASPEED_PINCTRL_FUNC(VGABIOSROM),
> };
>
> static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
> --
> git-series 0.8.10
^ permalink raw reply
* [PATCH 7/8] pinctrl: aspeed-g4: Add mux configuration for all pins
From: Joel Stanley @ 2016-09-29 0:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e0d8fa6cd444972e6f048f98da98f0439e6ca39b.1474986045.git-series.andrew@aj.id.au>
On Wed, Sep 28, 2016 at 12:20 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> The patch introducing the g4 pinctrl driver implemented a smattering of
> pins to flesh out the implementation of the core and provide bare-bones
> support for some OpenPOWER platforms. Now, update the bindings document
> to reflect the complete functionality and implement the necessary pin
> configuration tables in the driver.
>
> Cc: Timothy Pearson <tpearson@raptorengineering.com>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
^ permalink raw reply
* [PATCH 8/8] pinctrl: aspeed-g5: Add mux configuration for all pins
From: Joel Stanley @ 2016-09-29 0:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a17175fdeaf1656afa307a180a4ab4953d4ad19c.1474986045.git-series.andrew@aj.id.au>
On Wed, Sep 28, 2016 at 12:20 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> The patch introducing the g5 pinctrl driver implemented a smattering of
> pins to flesh out the implementation of the core and provide bare-bones
> support for some OpenPOWER platforms and the AST2500 evaluation board.
> Now, update the bindings document to reflect the complete functionality
> and implement the necessary pin configuration tables in the driver.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
> ---
> Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 17 +-
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 1476 ++++++-
> drivers/pinctrl/aspeed/pinctrl-aspeed.h | 1 +-
> 3 files changed, 1487 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> index 0defef01ff83..67e133ba3113 100644
> --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> @@ -46,10 +46,19 @@ VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
>
> aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
>
> -GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
> -I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
> -RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
> -TIMER7 TIMER8 VGABIOSROM
> +ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
> +ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT ESPI FWSPICS1 FWSPICS2 GPID0 GPID2 GPID4
> +GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6
> +I2C7 I2C8 I2C9 LAD0 LAD1 LAD2 LAD3 LCLK LFRAME LPCHC LPCPD LPCPLUS LPCPME
> +LPCRST LPCSMI LSIRQ MAC1LINK MAC2LINK MDIO1 MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1
> +NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 NDTR1 NDTR2 NDTR3 NDTR4 NRI1 NRI2
> +NRI3 NRI4 NRTS1 NRTS2 NRTS3 NRTS4 OSCCLK PEWAKE PNOR PWM0 PWM1 PWM2 PWM3 PWM4
> +PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 RXD1 RXD2 RXD3 RXD4 SALT1 SALT10
> +SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9
> +SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ
> +SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0
> +SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
> +TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2
>
>
> Examples:
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> index c8c72e8259d3..481e836d12e5 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> @@ -24,14 +24,27 @@
> #include "../pinctrl-utils.h"
> #include "pinctrl-aspeed.h"
>
> -#define ASPEED_G5_NR_PINS 228
> +#define ASPEED_G5_NR_PINS 232
>
> #define COND1 SIG_DESC_BIT(SCU90, 6, 0)
> #define COND2 { SCU94, GENMASK(1, 0), 0, 0 }
>
> +#define LHCR0 SIG_DESC_TO_REG(ASPEED_IP_LPC, 0xA0)
> +#define GFX064 SIG_DESC_TO_REG(ASPEED_IP_GFX, 0x64)
> +
> #define B14 0
> SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
>
> +#define D14 1
> +SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
> +
> +#define D13 2
> +SIG_EXPR_LIST_DECL_SINGLE(SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15));
> +SIG_EXPR_LIST_DECL_SINGLE(TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2));
> +MS_PIN_DECL(D13, GPIOA2, SPI1CS1, TIMER3);
> +FUNC_GROUP_DECL(SPI1CS1, D13);
> +FUNC_GROUP_DECL(TIMER3, D13);
> +
> #define E13 3
> SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
>
> @@ -71,6 +84,32 @@ FUNC_GROUP_DECL(TIMER8, B13);
>
> FUNC_GROUP_DECL(MDIO2, C13, B13);
>
> +#define K19 8
> +GPIO_PIN_DECL(K19, GPIOB0);
> +
> +#define L19 9
> +GPIO_PIN_DECL(L19, GPIOB1);
> +
> +#define L18 10
> +GPIO_PIN_DECL(L18, GPIOB2);
> +
> +#define K18 11
> +GPIO_PIN_DECL(K18, GPIOB3);
> +
> +#define J20 12
> +SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
> +
> +#define H21 13
> +#define H21_DESC SIG_DESC_SET(SCU80, 13)
> +SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H21_DESC, SIG_DESC_BIT(SIORD30, 1, 0));
> +SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H21_DESC, SIG_DESC_SET(SIORD30, 1));
> +MS_PIN_DECL(H21, GPIOB5, LPCPD, LPCSMI);
> +FUNC_GROUP_DECL(LPCPD, H21);
> +FUNC_GROUP_DECL(LPCSMI, H21);
> +
> +#define H22 14
> +SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
> +
> #define H20 15
> GPIO_PIN_DECL(H20, GPIOB7);
>
> @@ -167,7 +206,44 @@ MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT);
>
> FUNC_GROUP_DECL(GPID2, F20, D20);
>
> -#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21)
> +#define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
> +
> +#define D21 28
> +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC);
> +SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC);
> +SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID);
> +MS_PIN_DECL(D21, GPIOD4, SD2DAT2, GPID4IN);
> +
> +#define E20 29
> +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC);
> +SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC);
> +SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID);
> +MS_PIN_DECL(E20, GPIOD5, SD2DAT3, GPID4OUT);
> +
> +FUNC_GROUP_DECL(GPID4, D21, E20);
> +
> +#define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
> +
> +#define G18 30
> +SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC);
> +SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC);
> +SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID);
> +MS_PIN_DECL(G18, GPIOD6, SD2CD, GPID6IN);
> +
> +#define C21 31
> +SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC);
> +SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC);
> +SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID);
> +MS_PIN_DECL(C21, GPIOD7, SD2WP, GPID6OUT);
> +
> +FUNC_GROUP_DECL(GPID6, G18, C21);
> +FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21);
> +
> +#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
> #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
>
> #define B20 32
> @@ -176,6 +252,7 @@ SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC);
> SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC);
> SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE);
> MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN);
> +FUNC_GROUP_DECL(NCTS3, B20);
>
> #define C20 33
> SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
> @@ -183,9 +260,227 @@ SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
> SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
> SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
> MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
> +FUNC_GROUP_DECL(NDCD3, C20);
>
> FUNC_GROUP_DECL(GPIE0, B20, C20);
>
> +#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
> +
> +#define F18 34
> +SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
> +SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC);
> +SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE);
> +MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN);
> +FUNC_GROUP_DECL(NDSR3, F18);
> +
> +
> +#define F17 35
> +SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
> +SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC);
> +SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE);
> +MS_PIN_DECL(F17, GPIOE3, NRI3, GPIE2OUT);
> +FUNC_GROUP_DECL(NRI3, F17);
> +
> +FUNC_GROUP_DECL(GPIE2, F18, F17);
> +
> +#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14)
> +
> +#define E18 36
> +SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
> +SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC);
> +SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE);
> +MS_PIN_DECL(E18, GPIOE4, NDTR3, GPIE4IN);
> +FUNC_GROUP_DECL(NDTR3, E18);
> +
> +#define D19 37
> +SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
> +SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC);
> +SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE);
> +MS_PIN_DECL(D19, GPIOE5, NRTS3, GPIE4OUT);
> +FUNC_GROUP_DECL(NRTS3, D19);
> +
> +FUNC_GROUP_DECL(GPIE4, E18, D19);
> +
> +#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
> +
> +#define A20 38
> +SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
> +SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC);
> +SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE);
> +MS_PIN_DECL(A20, GPIOE6, TXD3, GPIE6IN);
> +FUNC_GROUP_DECL(TXD3, A20);
> +
> +#define B19 39
> +SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
> +SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC);
> +SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE);
> +MS_PIN_DECL(B19, GPIOE7, RXD3, GPIE6OUT);
> +FUNC_GROUP_DECL(RXD3, B19);
> +
> +FUNC_GROUP_DECL(GPIE6, A20, B19);
> +
> +#define LPCHC_DESC SIG_DESC_SET(LHCR0, 0)
> +#define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30)
> +
> +#define J19 40
> +SIG_EXPR_DECL(LHAD0, LPCHC, LPCHC_DESC);
> +SIG_EXPR_DECL(LHAD0, LPCPLUS, LPCPLUS_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(LHAD0, LPCHC, LPCPLUS);
> +SIG_EXPR_LIST_DECL_SINGLE(NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24));
> +MS_PIN_DECL(J19, GPIOF0, LHAD0, NCTS4);
> +FUNC_GROUP_DECL(NCTS4, J19);
> +
> +#define J18 41
> +SIG_EXPR_DECL(LHAD1, LPCHC, LPCHC_DESC);
> +SIG_EXPR_DECL(LHAD1, LPCPLUS, LPCPLUS_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(LHAD1, LPCHC, LPCPLUS);
> +SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
> +MS_PIN_DECL(J18, GPIOF1, LHAD1, NDCD4);
> +FUNC_GROUP_DECL(NDCD4, J18);
> +
> +#define B22 42
> +SIG_EXPR_DECL(LHAD2, LPCHC, LPCHC_DESC);
> +SIG_EXPR_DECL(LHAD2, LPCPLUS, LPCPLUS_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(LHAD2, LPCHC, LPCPLUS);
> +SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
> +MS_PIN_DECL(B22, GPIOF2, LHAD2, NDSR4);
> +FUNC_GROUP_DECL(NDSR4, B22);
> +
> +#define B21 43
> +SIG_EXPR_DECL(LHAD3, LPCHC, LPCHC_DESC);
> +SIG_EXPR_DECL(LHAD3, LPCPLUS, LPCPLUS_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(LHAD3, LPCHC, LPCPLUS);
> +SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
> +MS_PIN_DECL(B21, GPIOF3, LHAD3, NRI4);
> +FUNC_GROUP_DECL(NRI4, B21);
> +
> +#define A21 44
> +SIG_EXPR_DECL(LHCLK, LPCHC, LPCHC_DESC);
> +SIG_EXPR_DECL(LHCLK, LPCPLUS, LPCPLUS_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(LHCLK, LPCHC, LPCPLUS);
> +SIG_EXPR_LIST_DECL_SINGLE(NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28));
> +MS_PIN_DECL(A21, GPIOF4, LHCLK, NDTR4);
> +FUNC_GROUP_DECL(NDTR4, A21);
> +
> +#define H19 45
> +SIG_EXPR_DECL(LHFRAME, LPCHC, LPCHC_DESC);
> +SIG_EXPR_DECL(LHFRAME, LPCPLUS, LPCPLUS_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(LHFRAME, LPCHC, LPCPLUS);
> +SIG_EXPR_LIST_DECL_SINGLE(NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29));
> +MS_PIN_DECL(H19, GPIOF5, LHFRAME, NRTS4);
> +FUNC_GROUP_DECL(NRTS4, H19);
> +
> +#define G17 46
> +SIG_EXPR_LIST_DECL_SINGLE(LHSIRQ, LPCHC, LPCHC_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(TXD4, TXD4, SIG_DESC_SET(SCU80, 30));
> +MS_PIN_DECL(G17, GPIOF6, LHSIRQ, TXD4);
> +FUNC_GROUP_DECL(TXD4, G17);
> +
> +#define H18 47
> +SIG_EXPR_DECL(LHRST, LPCHC, LPCHC_DESC);
> +SIG_EXPR_DECL(LHRST, LPCPLUS, LPCPLUS_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(LHRST, LPCHC, LPCPLUS);
> +SIG_EXPR_LIST_DECL_SINGLE(RXD4, RXD4, SIG_DESC_SET(SCU80, 31));
> +MS_PIN_DECL(H18, GPIOF7, LHRST, RXD4);
> +FUNC_GROUP_DECL(RXD4, H18);
> +
> +FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18);
> +FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18);
> +
> +#define A19 48
> +SIG_EXPR_LIST_DECL_SINGLE(SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0));
> +SS_PIN_DECL(A19, GPIOG0, SGPS1CK);
> +
> +#define E19 49
> +SIG_EXPR_LIST_DECL_SINGLE(SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
> +SS_PIN_DECL(E19, GPIOG1, SGPS1LD);
> +
> +#define C19 50
> +SIG_EXPR_LIST_DECL_SINGLE(SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2));
> +SS_PIN_DECL(C19, GPIOG2, SGPS1I0);
> +
> +#define E16 51
> +SIG_EXPR_LIST_DECL_SINGLE(SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3));
> +SS_PIN_DECL(E16, GPIOG3, SGPS1I1);
> +
> +FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16);
> +
> +#define SGPS2_DESC SIG_DESC_SET(SCU94, 12)
> +
> +#define E17 52
> +SIG_EXPR_LIST_DECL_SINGLE(SGPS2CK, SGPS2, COND1, SGPS2_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4));
> +MS_PIN_DECL(E17, GPIOG4, SGPS2CK, SALT1);
> +FUNC_GROUP_DECL(SALT1, E17);
> +
> +#define D16 53
> +SIG_EXPR_LIST_DECL_SINGLE(SGPS2LD, SGPS2, COND1, SGPS2_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5));
> +MS_PIN_DECL(D16, GPIOG5, SGPS2LD, SALT2);
> +FUNC_GROUP_DECL(SALT2, D16);
> +
> +#define D15 54
> +SIG_EXPR_LIST_DECL_SINGLE(SGPS2I0, SGPS2, COND1, SGPS2_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
> +MS_PIN_DECL(D15, GPIOG6, SGPS2I0, SALT3);
> +FUNC_GROUP_DECL(SALT3, D15);
> +
> +#define E14 55
> +SIG_EXPR_LIST_DECL_SINGLE(SGPS2I1, SGPS2, COND1, SGPS2_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7));
> +MS_PIN_DECL(E14, GPIOG7, SGPS2I1, SALT4);
> +FUNC_GROUP_DECL(SALT4, E14);
> +
> +FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14);
> +
> +#define UART6_DESC SIG_DESC_SET(SCU90, 7)
> +
> +#define A18 56
> +SIG_EXPR_LIST_DECL_SINGLE(DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
> +SIG_EXPR_LIST_DECL_SINGLE(NCTS6, UART6, COND1, UART6_DESC);
> +MS_PIN_DECL(A18, GPIOH0, DASHA18, NCTS6);
> +
> +#define B18 57
> +SIG_EXPR_LIST_DECL_SINGLE(DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
> +SIG_EXPR_LIST_DECL_SINGLE(NDCD6, UART6, COND1, UART6_DESC);
> +MS_PIN_DECL(B18, GPIOH1, DASHB18, NDCD6);
> +
> +#define D17 58
> +SIG_EXPR_LIST_DECL_SINGLE(DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
> +SIG_EXPR_LIST_DECL_SINGLE(NDSR6, UART6, COND1, UART6_DESC);
> +MS_PIN_DECL(D17, GPIOH2, DASHD17, NDSR6);
> +
> +#define C17 59
> +SIG_EXPR_LIST_DECL_SINGLE(DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
> +SIG_EXPR_LIST_DECL_SINGLE(NRI6, UART6, COND1, UART6_DESC);
> +MS_PIN_DECL(C17, GPIOH3, DASHC17, NRI6);
> +
> +#define A17 60
> +SIG_EXPR_LIST_DECL_SINGLE(DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
> +SIG_EXPR_LIST_DECL_SINGLE(NDTR6, UART6, COND1, UART6_DESC);
> +MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6);
> +
> +#define B17 61
> +SIG_EXPR_LIST_DECL_SINGLE(DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
> +SIG_EXPR_LIST_DECL_SINGLE(NRTS6, UART6, COND1, UART6_DESC);
> +MS_PIN_DECL(B17, GPIOH5, DASHB17, NRTS6);
> +
> +#define A16 62
> +SIG_EXPR_LIST_DECL_SINGLE(TXD6, UART6, COND1, UART6_DESC);
> +SS_PIN_DECL(A16, GPIOH6, TXD6);
> +
> +#define D18 63
> +SIG_EXPR_LIST_DECL_SINGLE(RXD6, UART6, COND1, UART6_DESC);
> +SS_PIN_DECL(D18, GPIOH7, RXD6);
> +
> +FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18);
> +
> #define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
> #define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
> #define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
> @@ -277,6 +572,30 @@ SS_PIN_DECL(N3, GPIOJ2, SGPMO);
> SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
> SS_PIN_DECL(N4, GPIOJ3, SGPMI);
>
> +#define N5 76
> +SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
> +SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
> +MS_PIN_DECL(N5, GPIOJ4, VGAHS, DASHN5);
> +FUNC_GROUP_DECL(VGAHS, N5);
> +
> +#define R4 77
> +SIG_EXPR_LIST_DECL_SINGLE(VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
> +SIG_EXPR_LIST_DECL_SINGLE(DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
> +MS_PIN_DECL(R4, GPIOJ5, VGAVS, DASHR4);
> +FUNC_GROUP_DECL(VGAVS, R4);
> +
> +#define R3 78
> +SIG_EXPR_LIST_DECL_SINGLE(DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14));
> +SIG_EXPR_LIST_DECL_SINGLE(DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
> +MS_PIN_DECL(R3, GPIOJ6, DDCCLK, DASHR3);
> +FUNC_GROUP_DECL(DDCCLK, R3);
> +
> +#define T3 79
> +SIG_EXPR_LIST_DECL_SINGLE(DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15));
> +SIG_EXPR_LIST_DECL_SINGLE(DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
> +MS_PIN_DECL(T3, GPIOJ7, DDCDAT, DASHT3);
> +FUNC_GROUP_DECL(DDCDAT, T3);
> +
> #define I2C5_DESC SIG_DESC_SET(SCU90, 18)
>
> #define L3 80
> @@ -325,10 +644,119 @@ SS_PIN_DECL(R1, GPIOK7, SDA8);
>
> FUNC_GROUP_DECL(I2C8, P2, R1);
>
> +#define T2 88
> +SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
> +
> #define VPIOFF0_DESC { SCU90, GENMASK(5, 4), 0, 0 }
> #define VPIOFF1_DESC { SCU90, GENMASK(5, 4), 1, 0 }
> #define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 }
> #define VPIRSVD_DESC { SCU90, GENMASK(5, 4), 3, 0 }
> +#define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5)
> +
> +#define T1 89
> +#define T1_DESC SIG_DESC_SET(SCU84, 17)
> +SIG_EXPR_LIST_DECL_SINGLE(VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T1_DESC, COND2);
> +MS_PIN_DECL(T1, GPIOL1, VPIDE, NDCD1);
> +FUNC_GROUP_DECL(NDCD1, T1);
> +
> +#define U1 90
> +#define U1_DESC SIG_DESC_SET(SCU84, 18)
> +SIG_EXPR_LIST_DECL_SINGLE(DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U1_DESC);
> +MS_PIN_DECL(U1, GPIOL2, DASHU1, NDSR1);
> +FUNC_GROUP_DECL(NDSR1, U1);
> +
> +#define U2 91
> +#define U2_DESC SIG_DESC_SET(SCU84, 19)
> +SIG_EXPR_LIST_DECL_SINGLE(VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, U2_DESC, COND2);
> +MS_PIN_DECL(U2, GPIOL3, VPIHS, NRI1);
> +FUNC_GROUP_DECL(NRI1, U2);
> +
> +#define P4 92
> +#define P4_DESC SIG_DESC_SET(SCU84, 20)
> +SIG_EXPR_LIST_DECL_SINGLE(VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, P4_DESC, COND2);
> +MS_PIN_DECL(P4, GPIOL4, VPIVS, NDTR1);
> +FUNC_GROUP_DECL(NDTR1, P4);
> +
> +#define P3 93
> +#define P3_DESC SIG_DESC_SET(SCU84, 21)
> +SIG_EXPR_LIST_DECL_SINGLE(VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, P3_DESC, COND2);
> +MS_PIN_DECL(P3, GPIOL5, VPICLK, NRTS1);
> +FUNC_GROUP_DECL(NRTS1, P3);
> +
> +#define V1 94
> +#define V1_DESC SIG_DESC_SET(SCU84, 22)
> +SIG_EXPR_LIST_DECL_SINGLE(DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, V1_DESC, COND2);
> +MS_PIN_DECL(V1, GPIOL6, DASHV1, TXD1);
> +FUNC_GROUP_DECL(TXD1, V1);
> +
> +#define W1 95
> +#define W1_DESC SIG_DESC_SET(SCU84, 23)
> +SIG_EXPR_LIST_DECL_SINGLE(DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, W1_DESC, COND2);
> +MS_PIN_DECL(W1, GPIOL7, DASHW1, RXD1);
> +FUNC_GROUP_DECL(RXD1, W1);
> +
> +#define Y1 96
> +#define Y1_DESC SIG_DESC_SET(SCU84, 24)
> +SIG_EXPR_LIST_DECL_SINGLE(VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, Y1_DESC, COND2);
> +MS_PIN_DECL(Y1, GPIOM0, VPIB2, NCTS2);
> +FUNC_GROUP_DECL(NCTS2, Y1);
> +
> +#define AB2 97
> +#define AB2_DESC SIG_DESC_SET(SCU84, 25)
> +SIG_EXPR_LIST_DECL_SINGLE(VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, AB2_DESC, COND2);
> +MS_PIN_DECL(AB2, GPIOM1, VPIB3, NDCD2);
> +FUNC_GROUP_DECL(NDCD2, AB2);
> +
> +#define AA1 98
> +#define AA1_DESC SIG_DESC_SET(SCU84, 26)
> +SIG_EXPR_LIST_DECL_SINGLE(VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, AA1_DESC, COND2);
> +MS_PIN_DECL(AA1, GPIOM2, VPIB4, NDSR2);
> +FUNC_GROUP_DECL(NDSR2, AA1);
> +
> +#define Y2 99
> +#define Y2_DESC SIG_DESC_SET(SCU84, 27)
> +SIG_EXPR_LIST_DECL_SINGLE(VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, Y2_DESC, COND2);
> +MS_PIN_DECL(Y2, GPIOM3, VPIB5, NRI2);
> +FUNC_GROUP_DECL(NRI2, Y2);
> +
> +#define AA2 100
> +#define AA2_DESC SIG_DESC_SET(SCU84, 28)
> +SIG_EXPR_LIST_DECL_SINGLE(VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, AA2_DESC, COND2);
> +MS_PIN_DECL(AA2, GPIOM4, VPIB6, NDTR2);
> +FUNC_GROUP_DECL(NDTR2, AA2);
> +
> +#define P5 101
> +#define P5_DESC SIG_DESC_SET(SCU84, 29)
> +SIG_EXPR_LIST_DECL_SINGLE(VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, P5_DESC, COND2);
> +MS_PIN_DECL(P5, GPIOM5, VPIB7, NRTS2);
> +FUNC_GROUP_DECL(NRTS2, P5);
> +
> +#define R5 102
> +#define R5_DESC SIG_DESC_SET(SCU84, 30)
> +SIG_EXPR_LIST_DECL_SINGLE(VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, R5_DESC, COND2);
> +MS_PIN_DECL(R5, GPIOM6, VPIB8, TXD2);
> +FUNC_GROUP_DECL(TXD2, R5);
> +
> +#define T5 103
> +#define T5_DESC SIG_DESC_SET(SCU84, 31)
> +SIG_EXPR_LIST_DECL_SINGLE(VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
> +SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, T5_DESC, COND2);
> +MS_PIN_DECL(T5, GPIOM7, VPIB9, RXD2);
> +FUNC_GROUP_DECL(RXD2, T5);
>
> #define V2 104
> #define V2_DESC SIG_DESC_SET(SCU88, 0)
> @@ -394,9 +822,88 @@ SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2);
> MS_PIN_DECL(T4, GPION7, VPIG7, PWM7);
> FUNC_GROUP_DECL(PWM7, T4);
>
> +#define U5 112
> +SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8),
> + COND2);
> +SS_PIN_DECL(U5, GPIOO0, VPIG8);
> +
> +#define U4 113
> +SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9),
> + COND2);
> +SS_PIN_DECL(U4, GPIOO1, VPIG9);
> +
> +#define V5 114
> +SIG_EXPR_LIST_DECL_SINGLE(DASHV5, DASHV5, VPI_24_RSVD_DESC,
> + SIG_DESC_SET(SCU88, 10));
> +SS_PIN_DECL(V5, GPIOO2, DASHV5);
> +
> +#define AB4 115
> +SIG_EXPR_LIST_DECL_SINGLE(DASHAB4, DASHAB4, VPI_24_RSVD_DESC,
> + SIG_DESC_SET(SCU88, 11));
> +SS_PIN_DECL(AB4, GPIOO3, DASHAB4);
> +
> +#define AB3 116
> +SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12),
> + COND2);
> +SS_PIN_DECL(AB3, GPIOO4, VPIR2);
> +
> +#define Y4 117
> +SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13),
> + COND2);
> +SS_PIN_DECL(Y4, GPIOO5, VPIR3);
> +
> +#define AA4 118
> +SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14),
> + COND2);
> +SS_PIN_DECL(AA4, GPIOO6, VPIR4);
> +
> +#define W4 119
> +SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15),
> + COND2);
> +SS_PIN_DECL(W4, GPIOO7, VPIR5);
> +
> +#define V4 120
> +SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16),
> + COND2);
> +SS_PIN_DECL(V4, GPIOP0, VPIR6);
> +
> +#define W5 121
> +SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17),
> + COND2);
> +SS_PIN_DECL(W5, GPIOP1, VPIR7);
> +
> +#define AA5 122
> +SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18),
> + COND2);
> +SS_PIN_DECL(AA5, GPIOP2, VPIR8);
> +
> +#define AB5 123
> +SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19),
> + COND2);
> +SS_PIN_DECL(AB5, GPIOP3, VPIR9);
> +
> +FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
> + U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5,
> + AB5);
> +
> +#define Y6 124
> +SIG_EXPR_LIST_DECL_SINGLE(DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28),
> + SIG_DESC_SET(SCU88, 20));
> +SS_PIN_DECL(Y6, GPIOP4, DASHY6);
> +
> +#define Y5 125
> +SIG_EXPR_LIST_DECL_SINGLE(DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28),
> + SIG_DESC_SET(SCU88, 21));
> +SS_PIN_DECL(Y5, GPIOP5, DASHY5);
> +
> +#define W6 126
> +SIG_EXPR_LIST_DECL_SINGLE(DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28),
> + SIG_DESC_SET(SCU88, 22));
> +SS_PIN_DECL(W6, GPIOP6, DASHW6);
> +
> #define V6 127
> SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
> - SIG_DESC_SET(SCU88, 23));
> + SIG_DESC_SET(SCU88, 23));
> SS_PIN_DECL(V6, GPIOP7, DASHV6);
>
> #define I2C3_DESC SIG_DESC_SET(SCU90, 16)
> @@ -441,6 +948,24 @@ SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
> #define N20 135
> SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29));
>
> +#define AA19 136
> +SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2);
> +
> +#define T19 137
> +SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2);
> +
> +#define T17 138
> +SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2);
> +
> +#define Y19 139
> +SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2);
> +
> +#define W19 140
> +SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2);
> +
> +#define V19 141
> +SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2);
> +
> #define D8 142
> SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
> SS_PIN_DECL(D8, GPIOR6, MDC1);
> @@ -451,6 +976,93 @@ SS_PIN_DECL(E10, GPIOR7, MDIO1);
>
> FUNC_GROUP_DECL(MDIO1, D8, E10);
>
> +#define VPOOFF0_DESC { SCU94, GENMASK(1, 0), 0, 0 }
> +#define VPO_DESC { SCU94, GENMASK(1, 0), 1, 0 }
> +#define VPOOFF1_DESC { SCU94, GENMASK(1, 0), 2, 0 }
> +#define VPOOFF2_DESC { SCU94, GENMASK(1, 0), 3, 0 }
> +
> +#define CRT_DVO_EN_DESC SIG_DESC_SET(GFX064, 7)
> +
> +#define V20 144
> +#define V20_DESC SIG_DESC_SET(SCU8C, 0)
> +SIG_EXPR_DECL(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO),
> + SIG_EXPR_PTR(VPOB2, VPOOFF1), SIG_EXPR_PTR(VPOB2, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(SPI2CS1, SPI2CS1, V20_DESC);
> +MS_PIN_DECL(V20, GPIOS0, VPOB2, SPI2CS1);
> +FUNC_GROUP_DECL(SPI2CS1, V20);
> +
> +#define U19 145
> +#define U19_DESC SIG_DESC_SET(SCU8C, 1)
> +SIG_EXPR_DECL(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO),
> + SIG_EXPR_PTR(VPOB3, VPOOFF1), SIG_EXPR_PTR(VPOB3, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(BMCINT, BMCINT, U19_DESC);
> +MS_PIN_DECL(U19, GPIOS1, VPOB3, BMCINT);
> +FUNC_GROUP_DECL(BMCINT, U19);
> +
> +#define R18 146
> +#define R18_DESC SIG_DESC_SET(SCU8C, 2)
> +SIG_EXPR_DECL(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO),
> + SIG_EXPR_PTR(VPOB4, VPOOFF1), SIG_EXPR_PTR(VPOB4, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(SALT5, SALT5, R18_DESC);
> +MS_PIN_DECL(R18, GPIOS2, VPOB4, SALT5);
> +FUNC_GROUP_DECL(SALT5, R18);
> +
> +#define P18 147
> +#define P18_DESC SIG_DESC_SET(SCU8C, 3)
> +SIG_EXPR_DECL(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO),
> + SIG_EXPR_PTR(VPOB5, VPOOFF1), SIG_EXPR_PTR(VPOB5, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(SALT6, SALT6, P18_DESC);
> +MS_PIN_DECL(P18, GPIOS3, VPOB5, SALT6);
> +FUNC_GROUP_DECL(SALT6, P18);
> +
> +#define R19 148
> +#define R19_DESC SIG_DESC_SET(SCU8C, 4)
> +SIG_EXPR_DECL(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO),
> + SIG_EXPR_PTR(VPOB6, VPOOFF1), SIG_EXPR_PTR(VPOB6, VPOOFF2));
> +SS_PIN_DECL(R19, GPIOS4, VPOB6);
> +
> +#define W20 149
> +#define W20_DESC SIG_DESC_SET(SCU8C, 5)
> +SIG_EXPR_DECL(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO),
> + SIG_EXPR_PTR(VPOB7, VPOOFF1), SIG_EXPR_PTR(VPOB7, VPOOFF2));
> +SS_PIN_DECL(W20, GPIOS5, VPOB7);
> +
> +#define U20 150
> +#define U20_DESC SIG_DESC_SET(SCU8C, 6)
> +SIG_EXPR_DECL(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOB8, SIG_EXPR_PTR(VPOB8, VPO),
> + SIG_EXPR_PTR(VPOB8, VPOOFF1), SIG_EXPR_PTR(VPOB8, VPOOFF2));
> +SS_PIN_DECL(U20, GPIOS6, VPOB8);
> +
> +#define AA20 151
> +#define AA20_DESC SIG_DESC_SET(SCU8C, 7)
> +SIG_EXPR_DECL(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOB9, SIG_EXPR_PTR(VPOB9, VPO),
> + SIG_EXPR_PTR(VPOB9, VPOOFF1), SIG_EXPR_PTR(VPOB9, VPOOFF2));
> +SS_PIN_DECL(AA20, GPIOS7, VPOB9);
> +
> /* RGMII1/RMII1 */
>
> #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
> @@ -632,6 +1244,481 @@ MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER),
> FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
> FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
>
> +#define F4 176
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0);
> +MS_PIN_DECL_(F4, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0));
> +FUNC_GROUP_DECL(ADC0, F4);
> +
> +#define F5 177
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1);
> +MS_PIN_DECL_(F5, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1));
> +FUNC_GROUP_DECL(ADC1, F5);
> +
> +#define E2 178
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2);
> +MS_PIN_DECL_(E2, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2));
> +FUNC_GROUP_DECL(ADC2, E2);
> +
> +#define E1 179
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3);
> +MS_PIN_DECL_(E1, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3));
> +FUNC_GROUP_DECL(ADC3, E1);
> +
> +#define F3 180
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4);
> +MS_PIN_DECL_(F3, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4));
> +FUNC_GROUP_DECL(ADC4, F3);
> +
> +#define E3 181
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5);
> +MS_PIN_DECL_(E3, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5));
> +FUNC_GROUP_DECL(ADC5, E3);
> +
> +#define G5 182
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6);
> +MS_PIN_DECL_(G5, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6));
> +FUNC_GROUP_DECL(ADC6, G5);
> +
> +#define G4 183
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7);
> +MS_PIN_DECL_(G4, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7));
> +FUNC_GROUP_DECL(ADC7, G4);
> +
> +#define F2 184
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8);
> +MS_PIN_DECL_(F2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8));
> +FUNC_GROUP_DECL(ADC8, F2);
> +
> +#define G3 185
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9);
> +MS_PIN_DECL_(G3, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9));
> +FUNC_GROUP_DECL(ADC9, G3);
> +
> +#define G2 186
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10);
> +MS_PIN_DECL_(G2, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10));
> +FUNC_GROUP_DECL(ADC10, G2);
> +
> +#define F1 187
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11);
> +MS_PIN_DECL_(F1, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11));
> +FUNC_GROUP_DECL(ADC11, F1);
> +
> +#define H5 188
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12);
> +MS_PIN_DECL_(H5, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12));
> +FUNC_GROUP_DECL(ADC12, H5);
> +
> +#define G1 189
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13);
> +MS_PIN_DECL_(G1, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13));
> +FUNC_GROUP_DECL(ADC13, G1);
> +
> +#define H3 190
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14);
> +MS_PIN_DECL_(H3, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14));
> +FUNC_GROUP_DECL(ADC14, H3);
> +
> +#define H4 191
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
> +SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15);
> +MS_PIN_DECL_(H4, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15));
> +FUNC_GROUP_DECL(ADC15, H4);
> +
> +#define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19)
> +
> +#define R22 192
> +SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
> +SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI);
> +SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
> +MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22);
> +FUNC_GROUP_DECL(SIOS3, R22);
> +
> +#define R21 193
> +SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
> +SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI);
> +SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
> +MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21);
> +FUNC_GROUP_DECL(SIOS5, R21);
> +
> +#define P22 194
> +SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
> +SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI);
> +SIG_EXPR_LIST_DECL_SINGLE(DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
> +MS_PIN_DECL(P22, GPIOY2, SIOPWREQ, DASHP22);
> +FUNC_GROUP_DECL(SIOPWREQ, P22);
> +
> +#define P21 195
> +SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
> +SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI);
> +SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
> +MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21);
> +FUNC_GROUP_DECL(SIOONCTRL, P21);
> +
> +#define M18 196
> +SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12));
> +
> +#define M19 197
> +SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13));
> +
> +#define M20 198
> +SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14));
> +
> +#define P20 199
> +SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15));
> +
> +#define PNOR_DESC SIG_DESC_SET(SCU90, 31)
> +
> +#define Y20 200
> +#define Y20_DESC SIG_DESC_SET(SCUA4, 16)
> +SIG_EXPR_DECL(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO),
> + SIG_EXPR_PTR(VPOG2, VPOOFF1), SIG_EXPR_PTR(VPOG2, VPOOFF2));
> +SIG_EXPR_DECL(SIOPBI, SIOPBI, Y20_DESC);
> +SIG_EXPR_DECL(SIOPBI, ACPI, Y20_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI);
> +SIG_EXPR_LIST_DECL_SINGLE(NORA0, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ0, GPIOZ0);
> +MS_PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(VPOG2), SIG_EXPR_LIST_PTR(SIOPBI),
> + SIG_EXPR_LIST_PTR(NORA0), SIG_EXPR_LIST_PTR(GPIOZ0));
> +FUNC_GROUP_DECL(SIOPBI, Y20);
> +
> +#define AB20 201
> +#define AB20_DESC SIG_DESC_SET(SCUA4, 17)
> +SIG_EXPR_DECL(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO),
> + SIG_EXPR_PTR(VPOG3, VPOOFF1), SIG_EXPR_PTR(VPOG3, VPOOFF2));
> +SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, AB20_DESC);
> +SIG_EXPR_DECL(SIOPWRGD, ACPI, AB20_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI);
> +SIG_EXPR_LIST_DECL_SINGLE(NORA1, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ1, GPIOZ1);
> +MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(VPOG3), SIG_EXPR_LIST_PTR(SIOPWRGD),
> + SIG_EXPR_LIST_PTR(NORA1), SIG_EXPR_LIST_PTR(GPIOZ1));
> +FUNC_GROUP_DECL(SIOPWRGD, AB20);
> +
> +#define AB21 202
> +#define AB21_DESC SIG_DESC_SET(SCUA4, 18)
> +SIG_EXPR_DECL(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOG4, SIG_EXPR_PTR(VPOG4, VPO),
> + SIG_EXPR_PTR(VPOG4, VPOOFF1), SIG_EXPR_PTR(VPOG4, VPOOFF2));
> +SIG_EXPR_DECL(SIOPBO, SIOPBO, AB21_DESC);
> +SIG_EXPR_DECL(SIOPBO, ACPI, AB21_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI);
> +SIG_EXPR_LIST_DECL_SINGLE(NORA2, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ2, GPIOZ2);
> +MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(VPOG4), SIG_EXPR_LIST_PTR(SIOPBO),
> + SIG_EXPR_LIST_PTR(NORA2), SIG_EXPR_LIST_PTR(GPIOZ2));
> +FUNC_GROUP_DECL(SIOPBO, AB21);
> +
> +#define AA21 203
> +#define AA21_DESC SIG_DESC_SET(SCUA4, 19)
> +SIG_EXPR_DECL(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOG5, SIG_EXPR_PTR(VPOG5, VPO),
> + SIG_EXPR_PTR(VPOG5, VPOOFF1), SIG_EXPR_PTR(VPOG5, VPOOFF2));
> +SIG_EXPR_DECL(SIOSCI, SIOSCI, AA21_DESC);
> +SIG_EXPR_DECL(SIOSCI, ACPI, AA21_DESC);
> +SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI);
> +SIG_EXPR_LIST_DECL_SINGLE(NORA3, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ3, GPIOZ3);
> +MS_PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(VPOG5), SIG_EXPR_LIST_PTR(SIOSCI),
> + SIG_EXPR_LIST_PTR(NORA3), SIG_EXPR_LIST_PTR(GPIOZ3));
> +FUNC_GROUP_DECL(SIOSCI, AA21);
> +
> +FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21);
> +
> +/* CRT DVO disabled, configured for single-edge mode */
> +#define CRT_DVO_DS_DESC { GFX064, GENMASK(7, 6), 0, 0 }
> +
> +/* CRT DVO disabled, configured for dual-edge mode */
> +#define CRT_DVO_DD_DESC { GFX064, GENMASK(7, 6), 1, 1 }
> +
> +/* CRT DVO enabled, configured for single-edge mode */
> +#define CRT_DVO_ES_DESC { GFX064, GENMASK(7, 6), 2, 2 }
> +
> +/* CRT DVO enabled, configured for dual-edge mode */
> +#define CRT_DVO_ED_DESC { GFX064, GENMASK(7, 6), 3, 3 }
> +
> +#define U21 204
> +#define U21_DESC SIG_DESC_SET(SCUA4, 20)
> +SIG_EXPR_DECL(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOG6, SIG_EXPR_PTR(VPOG6, VPO),
> + SIG_EXPR_PTR(VPOG6, VPOOFF1), SIG_EXPR_PTR(VPOG6, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(NORA4, PNOR, PNOR_DESC);
> +MS_PIN_DECL(U21, GPIOZ4, VPOG6, NORA4);
> +
> +#define W22 205
> +#define W22_DESC SIG_DESC_SET(SCUA4, 21)
> +SIG_EXPR_DECL(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOG7, SIG_EXPR_PTR(VPOG7, VPO),
> + SIG_EXPR_PTR(VPOG7, VPOOFF1), SIG_EXPR_PTR(VPOG7, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(NORA5, PNOR, PNOR_DESC);
> +MS_PIN_DECL(W22, GPIOZ5, VPOG7, NORA5);
> +
> +#define V22 206
> +#define V22_DESC SIG_DESC_SET(SCUA4, 22)
> +SIG_EXPR_DECL(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOG8, SIG_EXPR_PTR(VPOG8, VPO),
> + SIG_EXPR_PTR(VPOG8, VPOOFF1), SIG_EXPR_PTR(VPOG8, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(NORA6, PNOR, PNOR_DESC);
> +MS_PIN_DECL(V22, GPIOZ6, VPOG8, NORA6);
> +
> +#define W21 207
> +#define W21_DESC SIG_DESC_SET(SCUA4, 23)
> +SIG_EXPR_DECL(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOG9, SIG_EXPR_PTR(VPOG9, VPO),
> + SIG_EXPR_PTR(VPOG9, VPOOFF1), SIG_EXPR_PTR(VPOG9, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(NORA7, PNOR, PNOR_DESC);
> +MS_PIN_DECL(W21, GPIOZ7, VPOG9, NORA7);
> +
> +#define Y21 208
> +#define Y21_DESC SIG_DESC_SET(SCUA4, 24)
> +SIG_EXPR_DECL(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOR2, SIG_EXPR_PTR(VPOR2, VPO),
> + SIG_EXPR_PTR(VPOR2, VPOOFF1), SIG_EXPR_PTR(VPOR2, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(SALT7, SALT7, Y21_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(NORD0, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA0, GPIOAA0);
> +MS_PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(VPOR2), SIG_EXPR_LIST_PTR(SALT7),
> + SIG_EXPR_LIST_PTR(NORD0), SIG_EXPR_LIST_PTR(GPIOAA0));
> +FUNC_GROUP_DECL(SALT7, Y21);
> +
> +#define V21 209
> +#define V21_DESC SIG_DESC_SET(SCUA4, 25)
> +SIG_EXPR_DECL(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOR3, SIG_EXPR_PTR(VPOR3, VPO),
> + SIG_EXPR_PTR(VPOR3, VPOOFF1), SIG_EXPR_PTR(VPOR3, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(SALT8, SALT8, V21_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(NORD1, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA1, GPIOAA1);
> +MS_PIN_DECL_(V21, SIG_EXPR_LIST_PTR(VPOR3), SIG_EXPR_LIST_PTR(SALT8),
> + SIG_EXPR_LIST_PTR(NORD1), SIG_EXPR_LIST_PTR(GPIOAA1));
> +FUNC_GROUP_DECL(SALT8, V21);
> +
> +#define Y22 210
> +#define Y22_DESC SIG_DESC_SET(SCUA4, 26)
> +SIG_EXPR_DECL(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOR4, SIG_EXPR_PTR(VPOR4, VPO),
> + SIG_EXPR_PTR(VPOR4, VPOOFF1), SIG_EXPR_PTR(VPOR4, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(SALT9, SALT9, Y22_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(NORD2, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA2, GPIOAA2);
> +MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(VPOR4), SIG_EXPR_LIST_PTR(SALT9),
> + SIG_EXPR_LIST_PTR(NORD2), SIG_EXPR_LIST_PTR(GPIOAA2));
> +FUNC_GROUP_DECL(SALT9, Y22);
> +
> +#define AA22 211
> +#define AA22_DESC SIG_DESC_SET(SCUA4, 27)
> +SIG_EXPR_DECL(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOR5, SIG_EXPR_PTR(VPOR5, VPO),
> + SIG_EXPR_PTR(VPOR5, VPOOFF1), SIG_EXPR_PTR(VPOR5, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(SALT10, SALT10, AA22_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(NORD3, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA3, GPIOAA3);
> +MS_PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(VPOR5), SIG_EXPR_LIST_PTR(SALT10),
> + SIG_EXPR_LIST_PTR(NORD3), SIG_EXPR_LIST_PTR(GPIOAA3));
> +FUNC_GROUP_DECL(SALT10, AA22);
> +
> +#define U22 212
> +#define U22_DESC SIG_DESC_SET(SCUA4, 28)
> +SIG_EXPR_DECL(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOR6, SIG_EXPR_PTR(VPOR6, VPO),
> + SIG_EXPR_PTR(VPOR6, VPOOFF1), SIG_EXPR_PTR(VPOR6, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(SALT11, SALT11, U22_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(NORD4, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA4, GPIOAA4);
> +MS_PIN_DECL_(U22, SIG_EXPR_LIST_PTR(VPOR6), SIG_EXPR_LIST_PTR(SALT11),
> + SIG_EXPR_LIST_PTR(NORD4), SIG_EXPR_LIST_PTR(GPIOAA4));
> +FUNC_GROUP_DECL(SALT11, U22);
> +
> +#define T20 213
> +#define T20_DESC SIG_DESC_SET(SCUA4, 29)
> +SIG_EXPR_DECL(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOR7, SIG_EXPR_PTR(VPOR7, VPO),
> + SIG_EXPR_PTR(VPOR7, VPOOFF1), SIG_EXPR_PTR(VPOR7, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(SALT12, SALT12, T20_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(NORD5, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA5, GPIOAA5);
> +MS_PIN_DECL_(T20, SIG_EXPR_LIST_PTR(VPOR7), SIG_EXPR_LIST_PTR(SALT12),
> + SIG_EXPR_LIST_PTR(NORD5), SIG_EXPR_LIST_PTR(GPIOAA5));
> +FUNC_GROUP_DECL(SALT12, T20);
> +
> +#define N18 214
> +#define N18_DESC SIG_DESC_SET(SCUA4, 30)
> +SIG_EXPR_DECL(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOR8, SIG_EXPR_PTR(VPOR8, VPO),
> + SIG_EXPR_PTR(VPOR8, VPOOFF1), SIG_EXPR_PTR(VPOR8, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(SALT13, SALT13, N18_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(NORD6, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA6, GPIOAA6);
> +MS_PIN_DECL_(N18, SIG_EXPR_LIST_PTR(VPOR8), SIG_EXPR_LIST_PTR(SALT13),
> + SIG_EXPR_LIST_PTR(NORD6), SIG_EXPR_LIST_PTR(GPIOAA6));
> +FUNC_GROUP_DECL(SALT13, N18);
> +
> +#define P19 215
> +#define P19_DESC SIG_DESC_SET(SCUA4, 31)
> +SIG_EXPR_DECL(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_DECL(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
> +SIG_EXPR_LIST_DECL(VPOR9, SIG_EXPR_PTR(VPOR9, VPO),
> + SIG_EXPR_PTR(VPOR9, VPOOFF1), SIG_EXPR_PTR(VPOR9, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(SALT14, SALT14, P19_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(NORD7, PNOR, PNOR_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA7, GPIOAA7);
> +MS_PIN_DECL_(P19, SIG_EXPR_LIST_PTR(VPOR9), SIG_EXPR_LIST_PTR(SALT14),
> + SIG_EXPR_LIST_PTR(NORD7), SIG_EXPR_LIST_PTR(GPIOAA7));
> +FUNC_GROUP_DECL(SALT14, P19);
> +
> +#define N19 216
> +#define N19_DESC SIG_DESC_SET(SCUA8, 0)
> +SIG_EXPR_DECL(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPODE, SIG_EXPR_PTR(VPODE, VPO),
> + SIG_EXPR_PTR(VPODE, VPOOFF1), SIG_EXPR_PTR(VPODE, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(NOROE, PNOR, PNOR_DESC);
> +MS_PIN_DECL(N19, GPIOAB0, VPODE, NOROE);
> +
> +#define T21 217
> +#define T21_DESC SIG_DESC_SET(SCUA8, 1)
> +SIG_EXPR_DECL(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOHS, SIG_EXPR_PTR(VPOHS, VPO),
> + SIG_EXPR_PTR(VPOHS, VPOOFF1), SIG_EXPR_PTR(VPOHS, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(NORWE, PNOR, PNOR_DESC);
> +MS_PIN_DECL(T21, GPIOAB1, VPOHS, NORWE);
> +
> +FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22,
> + AA22, U22, T20, N18, P19, N19, T21);
> +
> +#define T22 218
> +#define T22_DESC SIG_DESC_SET(SCUA8, 2)
> +SIG_EXPR_DECL(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOVS, SIG_EXPR_PTR(VPOVS, VPO),
> + SIG_EXPR_PTR(VPOVS, VPOOFF1), SIG_EXPR_PTR(VPOVS, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, T22_DESC);
> +MS_PIN_DECL(T22, GPIOAB2, VPOVS, WDTRST1);
> +FUNC_GROUP_DECL(WDTRST1, T22);
> +
> +#define R20 219
> +#define R20_DESC SIG_DESC_SET(SCUA8, 3)
> +SIG_EXPR_DECL(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_DECL(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
> +SIG_EXPR_LIST_DECL(VPOCLK, SIG_EXPR_PTR(VPOCLK, VPO),
> + SIG_EXPR_PTR(VPOCLK, VPOOFF1), SIG_EXPR_PTR(VPOCLK, VPOOFF2));
> +SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, R20_DESC);
> +MS_PIN_DECL(R20, GPIOAB3, VPOCLK, WDTRST2);
> +FUNC_GROUP_DECL(WDTRST2, R20);
> +
> +FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20,
> + AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20,
> + N18, P19, N19, T21, T22, R20);
> +
> +#define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25)
> +
> +#define G21 224
> +SIG_EXPR_LIST_DECL_SINGLE(ESPID0, ESPI, ESPI_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(LAD0, LAD0, SIG_DESC_SET(SCUAC, 0));
> +MS_PIN_DECL(G21, GPIOAC0, ESPID0, LAD0);
> +FUNC_GROUP_DECL(LAD0, G21);
> +
> +#define G20 225
> +SIG_EXPR_LIST_DECL_SINGLE(ESPID1, ESPI, ESPI_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
> +MS_PIN_DECL(G20, GPIOAC1, ESPID1, LAD1);
> +FUNC_GROUP_DECL(LAD1, G20);
> +
> +#define D22 226
> +SIG_EXPR_LIST_DECL_SINGLE(ESPID2, ESPI, ESPI_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(LAD2, LAD2, SIG_DESC_SET(SCUAC, 2));
> +MS_PIN_DECL(D22, GPIOAC2, ESPID2, LAD2);
> +FUNC_GROUP_DECL(LAD2, D22);
> +
> +#define E22 227
> +SIG_EXPR_LIST_DECL_SINGLE(ESPID3, ESPI, ESPI_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(LAD3, LAD3, SIG_DESC_SET(SCUAC, 3));
> +MS_PIN_DECL(E22, GPIOAC3, ESPID3, LAD3);
> +FUNC_GROUP_DECL(LAD3, E22);
> +
> +#define C22 228
> +SIG_EXPR_LIST_DECL_SINGLE(ESPICK, ESPI, ESPI_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(LCLK, LCLK, SIG_DESC_SET(SCUAC, 4));
> +MS_PIN_DECL(C22, GPIOAC4, ESPICK, LCLK);
> +FUNC_GROUP_DECL(LCLK, C22);
> +
> +#define F21 229
> +SIG_EXPR_LIST_DECL_SINGLE(ESPICS, ESPI, ESPI_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5));
> +MS_PIN_DECL(F21, GPIOAC5, ESPICS, LFRAME);
> +FUNC_GROUP_DECL(LFRAME, F21);
> +
> +#define F22 230
> +SIG_EXPR_LIST_DECL_SINGLE(ESPIALT, ESPI, ESPI_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6));
> +MS_PIN_DECL(F22, GPIOAC6, ESPIALT, LSIRQ);
> +FUNC_GROUP_DECL(LSIRQ, F22);
> +
> +#define G22 231
> +SIG_EXPR_LIST_DECL_SINGLE(ESPIRST, ESPI, ESPI_DESC);
> +SIG_EXPR_LIST_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7));
> +MS_PIN_DECL(G22, GPIOAC7, ESPIRST, LPCRST);
> +FUNC_GROUP_DECL(LPCRST, G22);
> +
> +FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
> +
> /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
>
> static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> @@ -641,12 +1728,32 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(A13),
> ASPEED_PINCTRL_PIN(A14),
> ASPEED_PINCTRL_PIN(A15),
> + ASPEED_PINCTRL_PIN(A16),
> + ASPEED_PINCTRL_PIN(A17),
> + ASPEED_PINCTRL_PIN(A18),
> + ASPEED_PINCTRL_PIN(A19),
> ASPEED_PINCTRL_PIN(A2),
> + ASPEED_PINCTRL_PIN(A20),
> + ASPEED_PINCTRL_PIN(A21),
> ASPEED_PINCTRL_PIN(A3),
> ASPEED_PINCTRL_PIN(A4),
> ASPEED_PINCTRL_PIN(A5),
> ASPEED_PINCTRL_PIN(A9),
> + ASPEED_PINCTRL_PIN(AA1),
> + ASPEED_PINCTRL_PIN(AA19),
> + ASPEED_PINCTRL_PIN(AA2),
> + ASPEED_PINCTRL_PIN(AA20),
> + ASPEED_PINCTRL_PIN(AA21),
> + ASPEED_PINCTRL_PIN(AA22),
> ASPEED_PINCTRL_PIN(AA3),
> + ASPEED_PINCTRL_PIN(AA4),
> + ASPEED_PINCTRL_PIN(AA5),
> + ASPEED_PINCTRL_PIN(AB2),
> + ASPEED_PINCTRL_PIN(AB20),
> + ASPEED_PINCTRL_PIN(AB21),
> + ASPEED_PINCTRL_PIN(AB3),
> + ASPEED_PINCTRL_PIN(AB4),
> + ASPEED_PINCTRL_PIN(AB5),
> ASPEED_PINCTRL_PIN(B1),
> ASPEED_PINCTRL_PIN(B10),
> ASPEED_PINCTRL_PIN(B11),
> @@ -655,8 +1762,13 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(B14),
> ASPEED_PINCTRL_PIN(B15),
> ASPEED_PINCTRL_PIN(B16),
> + ASPEED_PINCTRL_PIN(B17),
> + ASPEED_PINCTRL_PIN(B18),
> + ASPEED_PINCTRL_PIN(B19),
> ASPEED_PINCTRL_PIN(B2),
> ASPEED_PINCTRL_PIN(B20),
> + ASPEED_PINCTRL_PIN(B21),
> + ASPEED_PINCTRL_PIN(B22),
> ASPEED_PINCTRL_PIN(B3),
> ASPEED_PINCTRL_PIN(B4),
> ASPEED_PINCTRL_PIN(B5),
> @@ -668,62 +1780,210 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(C14),
> ASPEED_PINCTRL_PIN(C15),
> ASPEED_PINCTRL_PIN(C16),
> + ASPEED_PINCTRL_PIN(C17),
> ASPEED_PINCTRL_PIN(C18),
> + ASPEED_PINCTRL_PIN(C19),
> ASPEED_PINCTRL_PIN(C2),
> ASPEED_PINCTRL_PIN(C20),
> + ASPEED_PINCTRL_PIN(C21),
> + ASPEED_PINCTRL_PIN(C22),
> ASPEED_PINCTRL_PIN(C3),
> ASPEED_PINCTRL_PIN(C4),
> ASPEED_PINCTRL_PIN(C5),
> ASPEED_PINCTRL_PIN(D1),
> ASPEED_PINCTRL_PIN(D10),
> + ASPEED_PINCTRL_PIN(D13),
> + ASPEED_PINCTRL_PIN(D14),
> + ASPEED_PINCTRL_PIN(D15),
> + ASPEED_PINCTRL_PIN(D16),
> + ASPEED_PINCTRL_PIN(D17),
> + ASPEED_PINCTRL_PIN(D18),
> + ASPEED_PINCTRL_PIN(D19),
> ASPEED_PINCTRL_PIN(D2),
> ASPEED_PINCTRL_PIN(D20),
> + ASPEED_PINCTRL_PIN(D21),
> + ASPEED_PINCTRL_PIN(D22),
> ASPEED_PINCTRL_PIN(D4),
> ASPEED_PINCTRL_PIN(D5),
> ASPEED_PINCTRL_PIN(D6),
> ASPEED_PINCTRL_PIN(D7),
> ASPEED_PINCTRL_PIN(D8),
> ASPEED_PINCTRL_PIN(D9),
> + ASPEED_PINCTRL_PIN(E1),
> ASPEED_PINCTRL_PIN(E10),
> ASPEED_PINCTRL_PIN(E12),
> ASPEED_PINCTRL_PIN(E13),
> + ASPEED_PINCTRL_PIN(E14),
> ASPEED_PINCTRL_PIN(E15),
> + ASPEED_PINCTRL_PIN(E16),
> + ASPEED_PINCTRL_PIN(E17),
> + ASPEED_PINCTRL_PIN(E18),
> + ASPEED_PINCTRL_PIN(E19),
> + ASPEED_PINCTRL_PIN(E2),
> + ASPEED_PINCTRL_PIN(E20),
> ASPEED_PINCTRL_PIN(E21),
> + ASPEED_PINCTRL_PIN(E22),
> + ASPEED_PINCTRL_PIN(E3),
> ASPEED_PINCTRL_PIN(E6),
> ASPEED_PINCTRL_PIN(E7),
> ASPEED_PINCTRL_PIN(E9),
> + ASPEED_PINCTRL_PIN(F1),
> + ASPEED_PINCTRL_PIN(F17),
> + ASPEED_PINCTRL_PIN(F18),
> ASPEED_PINCTRL_PIN(F19),
> + ASPEED_PINCTRL_PIN(F2),
> ASPEED_PINCTRL_PIN(F20),
> + ASPEED_PINCTRL_PIN(F21),
> + ASPEED_PINCTRL_PIN(F22),
> + ASPEED_PINCTRL_PIN(F3),
> + ASPEED_PINCTRL_PIN(F4),
> + ASPEED_PINCTRL_PIN(F5),
> ASPEED_PINCTRL_PIN(F9),
> + ASPEED_PINCTRL_PIN(G1),
> + ASPEED_PINCTRL_PIN(G17),
> + ASPEED_PINCTRL_PIN(G18),
> + ASPEED_PINCTRL_PIN(G2),
> + ASPEED_PINCTRL_PIN(G20),
> + ASPEED_PINCTRL_PIN(G21),
> + ASPEED_PINCTRL_PIN(G22),
> + ASPEED_PINCTRL_PIN(G3),
> + ASPEED_PINCTRL_PIN(G4),
> + ASPEED_PINCTRL_PIN(G5),
> + ASPEED_PINCTRL_PIN(H18),
> + ASPEED_PINCTRL_PIN(H19),
> ASPEED_PINCTRL_PIN(H20),
> + ASPEED_PINCTRL_PIN(H21),
> + ASPEED_PINCTRL_PIN(H22),
> + ASPEED_PINCTRL_PIN(H3),
> + ASPEED_PINCTRL_PIN(H4),
> + ASPEED_PINCTRL_PIN(H5),
> + ASPEED_PINCTRL_PIN(J18),
> + ASPEED_PINCTRL_PIN(J19),
> + ASPEED_PINCTRL_PIN(J20),
> + ASPEED_PINCTRL_PIN(K18),
> + ASPEED_PINCTRL_PIN(K19),
> ASPEED_PINCTRL_PIN(L1),
> + ASPEED_PINCTRL_PIN(L18),
> + ASPEED_PINCTRL_PIN(L19),
> ASPEED_PINCTRL_PIN(L2),
> ASPEED_PINCTRL_PIN(L3),
> ASPEED_PINCTRL_PIN(L4),
> + ASPEED_PINCTRL_PIN(M18),
> + ASPEED_PINCTRL_PIN(M19),
> + ASPEED_PINCTRL_PIN(M20),
> ASPEED_PINCTRL_PIN(N1),
> + ASPEED_PINCTRL_PIN(N18),
> + ASPEED_PINCTRL_PIN(N19),
> ASPEED_PINCTRL_PIN(N2),
> ASPEED_PINCTRL_PIN(N20),
> ASPEED_PINCTRL_PIN(N21),
> ASPEED_PINCTRL_PIN(N22),
> ASPEED_PINCTRL_PIN(N3),
> ASPEED_PINCTRL_PIN(N4),
> + ASPEED_PINCTRL_PIN(N5),
> ASPEED_PINCTRL_PIN(P1),
> + ASPEED_PINCTRL_PIN(P18),
> + ASPEED_PINCTRL_PIN(P19),
> ASPEED_PINCTRL_PIN(P2),
> + ASPEED_PINCTRL_PIN(P20),
> + ASPEED_PINCTRL_PIN(P21),
> + ASPEED_PINCTRL_PIN(P22),
> + ASPEED_PINCTRL_PIN(P3),
> + ASPEED_PINCTRL_PIN(P4),
> + ASPEED_PINCTRL_PIN(P5),
> ASPEED_PINCTRL_PIN(R1),
> + ASPEED_PINCTRL_PIN(R18),
> + ASPEED_PINCTRL_PIN(R19),
> + ASPEED_PINCTRL_PIN(R2),
> + ASPEED_PINCTRL_PIN(R20),
> + ASPEED_PINCTRL_PIN(R21),
> + ASPEED_PINCTRL_PIN(R22),
> + ASPEED_PINCTRL_PIN(R3),
> + ASPEED_PINCTRL_PIN(R4),
> + ASPEED_PINCTRL_PIN(R5),
> + ASPEED_PINCTRL_PIN(T1),
> + ASPEED_PINCTRL_PIN(T17),
> + ASPEED_PINCTRL_PIN(T19),
> + ASPEED_PINCTRL_PIN(T2),
> + ASPEED_PINCTRL_PIN(T20),
> + ASPEED_PINCTRL_PIN(T21),
> + ASPEED_PINCTRL_PIN(T22),
> + ASPEED_PINCTRL_PIN(T3),
> ASPEED_PINCTRL_PIN(T4),
> + ASPEED_PINCTRL_PIN(T5),
> + ASPEED_PINCTRL_PIN(U1),
> + ASPEED_PINCTRL_PIN(U19),
> + ASPEED_PINCTRL_PIN(U2),
> + ASPEED_PINCTRL_PIN(U20),
> + ASPEED_PINCTRL_PIN(U21),
> + ASPEED_PINCTRL_PIN(U22),
> ASPEED_PINCTRL_PIN(U3),
> + ASPEED_PINCTRL_PIN(U4),
> + ASPEED_PINCTRL_PIN(U5),
> + ASPEED_PINCTRL_PIN(V1),
> + ASPEED_PINCTRL_PIN(V19),
> ASPEED_PINCTRL_PIN(V2),
> + ASPEED_PINCTRL_PIN(V20),
> + ASPEED_PINCTRL_PIN(V21),
> + ASPEED_PINCTRL_PIN(V22),
> ASPEED_PINCTRL_PIN(V3),
> + ASPEED_PINCTRL_PIN(V4),
> + ASPEED_PINCTRL_PIN(V5),
> ASPEED_PINCTRL_PIN(V6),
> + ASPEED_PINCTRL_PIN(W1),
> + ASPEED_PINCTRL_PIN(W19),
> ASPEED_PINCTRL_PIN(W2),
> + ASPEED_PINCTRL_PIN(W20),
> + ASPEED_PINCTRL_PIN(W21),
> + ASPEED_PINCTRL_PIN(W22),
> ASPEED_PINCTRL_PIN(W3),
> + ASPEED_PINCTRL_PIN(W4),
> + ASPEED_PINCTRL_PIN(W5),
> + ASPEED_PINCTRL_PIN(W6),
> + ASPEED_PINCTRL_PIN(Y1),
> + ASPEED_PINCTRL_PIN(Y19),
> + ASPEED_PINCTRL_PIN(Y2),
> + ASPEED_PINCTRL_PIN(Y20),
> + ASPEED_PINCTRL_PIN(Y21),
> + ASPEED_PINCTRL_PIN(Y22),
> ASPEED_PINCTRL_PIN(Y3),
> + ASPEED_PINCTRL_PIN(Y4),
> + ASPEED_PINCTRL_PIN(Y5),
> + ASPEED_PINCTRL_PIN(Y6),
> };
>
> static const struct aspeed_pin_group aspeed_g5_groups[] = {
> + ASPEED_PINCTRL_GROUP(ACPI),
> + ASPEED_PINCTRL_GROUP(ADC0),
> + ASPEED_PINCTRL_GROUP(ADC1),
> + ASPEED_PINCTRL_GROUP(ADC10),
> + ASPEED_PINCTRL_GROUP(ADC11),
> + ASPEED_PINCTRL_GROUP(ADC12),
> + ASPEED_PINCTRL_GROUP(ADC13),
> + ASPEED_PINCTRL_GROUP(ADC14),
> + ASPEED_PINCTRL_GROUP(ADC15),
> + ASPEED_PINCTRL_GROUP(ADC2),
> + ASPEED_PINCTRL_GROUP(ADC3),
> + ASPEED_PINCTRL_GROUP(ADC4),
> + ASPEED_PINCTRL_GROUP(ADC5),
> + ASPEED_PINCTRL_GROUP(ADC6),
> + ASPEED_PINCTRL_GROUP(ADC7),
> + ASPEED_PINCTRL_GROUP(ADC8),
> + ASPEED_PINCTRL_GROUP(ADC9),
> + ASPEED_PINCTRL_GROUP(BMCINT),
> + ASPEED_PINCTRL_GROUP(DDCCLK),
> + ASPEED_PINCTRL_GROUP(DDCDAT),
> + ASPEED_PINCTRL_GROUP(ESPI),
> + ASPEED_PINCTRL_GROUP(FWSPICS1),
> + ASPEED_PINCTRL_GROUP(FWSPICS2),
> ASPEED_PINCTRL_GROUP(GPID0),
> ASPEED_PINCTRL_GROUP(GPID2),
> + ASPEED_PINCTRL_GROUP(GPID4),
> + ASPEED_PINCTRL_GROUP(GPID6),
> ASPEED_PINCTRL_GROUP(GPIE0),
> + ASPEED_PINCTRL_GROUP(GPIE2),
> + ASPEED_PINCTRL_GROUP(GPIE4),
> + ASPEED_PINCTRL_GROUP(GPIE6),
> ASPEED_PINCTRL_GROUP(I2C10),
> ASPEED_PINCTRL_GROUP(I2C11),
> ASPEED_PINCTRL_GROUP(I2C12),
> @@ -736,11 +1996,50 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
> ASPEED_PINCTRL_GROUP(I2C7),
> ASPEED_PINCTRL_GROUP(I2C8),
> ASPEED_PINCTRL_GROUP(I2C9),
> + ASPEED_PINCTRL_GROUP(LAD0),
> + ASPEED_PINCTRL_GROUP(LAD1),
> + ASPEED_PINCTRL_GROUP(LAD2),
> + ASPEED_PINCTRL_GROUP(LAD3),
> + ASPEED_PINCTRL_GROUP(LCLK),
> + ASPEED_PINCTRL_GROUP(LFRAME),
> + ASPEED_PINCTRL_GROUP(LPCHC),
> + ASPEED_PINCTRL_GROUP(LPCPD),
> + ASPEED_PINCTRL_GROUP(LPCPLUS),
> + ASPEED_PINCTRL_GROUP(LPCPME),
> + ASPEED_PINCTRL_GROUP(LPCRST),
> + ASPEED_PINCTRL_GROUP(LPCSMI),
> + ASPEED_PINCTRL_GROUP(LSIRQ),
> ASPEED_PINCTRL_GROUP(MAC1LINK),
> + ASPEED_PINCTRL_GROUP(MAC2LINK),
> ASPEED_PINCTRL_GROUP(MDIO1),
> ASPEED_PINCTRL_GROUP(MDIO2),
> + ASPEED_PINCTRL_GROUP(NCTS1),
> + ASPEED_PINCTRL_GROUP(NCTS2),
> + ASPEED_PINCTRL_GROUP(NCTS3),
> + ASPEED_PINCTRL_GROUP(NCTS4),
> + ASPEED_PINCTRL_GROUP(NDCD1),
> + ASPEED_PINCTRL_GROUP(NDCD2),
> + ASPEED_PINCTRL_GROUP(NDCD3),
> + ASPEED_PINCTRL_GROUP(NDCD4),
> + ASPEED_PINCTRL_GROUP(NDSR1),
> + ASPEED_PINCTRL_GROUP(NDSR2),
> + ASPEED_PINCTRL_GROUP(NDSR3),
> + ASPEED_PINCTRL_GROUP(NDSR4),
> + ASPEED_PINCTRL_GROUP(NDTR1),
> + ASPEED_PINCTRL_GROUP(NDTR2),
> + ASPEED_PINCTRL_GROUP(NDTR3),
> + ASPEED_PINCTRL_GROUP(NDTR4),
> + ASPEED_PINCTRL_GROUP(NRI1),
> + ASPEED_PINCTRL_GROUP(NRI2),
> + ASPEED_PINCTRL_GROUP(NRI3),
> + ASPEED_PINCTRL_GROUP(NRI4),
> + ASPEED_PINCTRL_GROUP(NRTS1),
> + ASPEED_PINCTRL_GROUP(NRTS2),
> + ASPEED_PINCTRL_GROUP(NRTS3),
> + ASPEED_PINCTRL_GROUP(NRTS4),
> ASPEED_PINCTRL_GROUP(OSCCLK),
> ASPEED_PINCTRL_GROUP(PEWAKE),
> + ASPEED_PINCTRL_GROUP(PNOR),
> ASPEED_PINCTRL_GROUP(PWM0),
> ASPEED_PINCTRL_GROUP(PWM1),
> ASPEED_PINCTRL_GROUP(PWM2),
> @@ -753,22 +2052,102 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
> ASPEED_PINCTRL_GROUP(RGMII2),
> ASPEED_PINCTRL_GROUP(RMII1),
> ASPEED_PINCTRL_GROUP(RMII2),
> + ASPEED_PINCTRL_GROUP(RXD1),
> + ASPEED_PINCTRL_GROUP(RXD2),
> + ASPEED_PINCTRL_GROUP(RXD3),
> + ASPEED_PINCTRL_GROUP(RXD4),
> + ASPEED_PINCTRL_GROUP(SALT1),
> + ASPEED_PINCTRL_GROUP(SALT10),
> + ASPEED_PINCTRL_GROUP(SALT11),
> + ASPEED_PINCTRL_GROUP(SALT12),
> + ASPEED_PINCTRL_GROUP(SALT13),
> + ASPEED_PINCTRL_GROUP(SALT14),
> + ASPEED_PINCTRL_GROUP(SALT2),
> + ASPEED_PINCTRL_GROUP(SALT3),
> + ASPEED_PINCTRL_GROUP(SALT4),
> + ASPEED_PINCTRL_GROUP(SALT5),
> + ASPEED_PINCTRL_GROUP(SALT6),
> + ASPEED_PINCTRL_GROUP(SALT7),
> + ASPEED_PINCTRL_GROUP(SALT8),
> + ASPEED_PINCTRL_GROUP(SALT9),
> + ASPEED_PINCTRL_GROUP(SCL1),
> + ASPEED_PINCTRL_GROUP(SCL2),
> ASPEED_PINCTRL_GROUP(SD1),
> + ASPEED_PINCTRL_GROUP(SD2),
> + ASPEED_PINCTRL_GROUP(SDA1),
> + ASPEED_PINCTRL_GROUP(SDA2),
> + ASPEED_PINCTRL_GROUP(SGPS1),
> + ASPEED_PINCTRL_GROUP(SGPS2),
> + ASPEED_PINCTRL_GROUP(SIOONCTRL),
> + ASPEED_PINCTRL_GROUP(SIOPBI),
> + ASPEED_PINCTRL_GROUP(SIOPBO),
> + ASPEED_PINCTRL_GROUP(SIOPWREQ),
> + ASPEED_PINCTRL_GROUP(SIOPWRGD),
> + ASPEED_PINCTRL_GROUP(SIOS3),
> + ASPEED_PINCTRL_GROUP(SIOS5),
> + ASPEED_PINCTRL_GROUP(SIOSCI),
> ASPEED_PINCTRL_GROUP(SPI1),
> + ASPEED_PINCTRL_GROUP(SPI1CS1),
> ASPEED_PINCTRL_GROUP(SPI1DEBUG),
> ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
> + ASPEED_PINCTRL_GROUP(SPI2CK),
> + ASPEED_PINCTRL_GROUP(SPI2CS0),
> + ASPEED_PINCTRL_GROUP(SPI2CS1),
> + ASPEED_PINCTRL_GROUP(SPI2MISO),
> + ASPEED_PINCTRL_GROUP(SPI2MOSI),
> + ASPEED_PINCTRL_GROUP(TIMER3),
> ASPEED_PINCTRL_GROUP(TIMER4),
> ASPEED_PINCTRL_GROUP(TIMER5),
> ASPEED_PINCTRL_GROUP(TIMER6),
> ASPEED_PINCTRL_GROUP(TIMER7),
> ASPEED_PINCTRL_GROUP(TIMER8),
> + ASPEED_PINCTRL_GROUP(TXD1),
> + ASPEED_PINCTRL_GROUP(TXD2),
> + ASPEED_PINCTRL_GROUP(TXD3),
> + ASPEED_PINCTRL_GROUP(TXD4),
> + ASPEED_PINCTRL_GROUP(UART6),
> + ASPEED_PINCTRL_GROUP(USBCKI),
> ASPEED_PINCTRL_GROUP(VGABIOSROM),
> + ASPEED_PINCTRL_GROUP(VGAHS),
> + ASPEED_PINCTRL_GROUP(VGAVS),
> + ASPEED_PINCTRL_GROUP(VPI24),
> + ASPEED_PINCTRL_GROUP(VPO),
> + ASPEED_PINCTRL_GROUP(WDTRST1),
> + ASPEED_PINCTRL_GROUP(WDTRST2),
> };
>
> static const struct aspeed_pin_function aspeed_g5_functions[] = {
> + ASPEED_PINCTRL_FUNC(ACPI),
> + ASPEED_PINCTRL_FUNC(ADC0),
> + ASPEED_PINCTRL_FUNC(ADC1),
> + ASPEED_PINCTRL_FUNC(ADC10),
> + ASPEED_PINCTRL_FUNC(ADC11),
> + ASPEED_PINCTRL_FUNC(ADC12),
> + ASPEED_PINCTRL_FUNC(ADC13),
> + ASPEED_PINCTRL_FUNC(ADC14),
> + ASPEED_PINCTRL_FUNC(ADC15),
> + ASPEED_PINCTRL_FUNC(ADC2),
> + ASPEED_PINCTRL_FUNC(ADC3),
> + ASPEED_PINCTRL_FUNC(ADC4),
> + ASPEED_PINCTRL_FUNC(ADC5),
> + ASPEED_PINCTRL_FUNC(ADC6),
> + ASPEED_PINCTRL_FUNC(ADC7),
> + ASPEED_PINCTRL_FUNC(ADC8),
> + ASPEED_PINCTRL_FUNC(ADC9),
> + ASPEED_PINCTRL_FUNC(BMCINT),
> + ASPEED_PINCTRL_FUNC(DDCCLK),
> + ASPEED_PINCTRL_FUNC(DDCDAT),
> + ASPEED_PINCTRL_FUNC(ESPI),
> + ASPEED_PINCTRL_FUNC(FWSPICS1),
> + ASPEED_PINCTRL_FUNC(FWSPICS2),
> ASPEED_PINCTRL_FUNC(GPID0),
> ASPEED_PINCTRL_FUNC(GPID2),
> + ASPEED_PINCTRL_FUNC(GPID4),
> + ASPEED_PINCTRL_FUNC(GPID6),
> ASPEED_PINCTRL_FUNC(GPIE0),
> + ASPEED_PINCTRL_FUNC(GPIE2),
> + ASPEED_PINCTRL_FUNC(GPIE4),
> + ASPEED_PINCTRL_FUNC(GPIE6),
> ASPEED_PINCTRL_FUNC(I2C10),
> ASPEED_PINCTRL_FUNC(I2C11),
> ASPEED_PINCTRL_FUNC(I2C12),
> @@ -781,11 +2160,50 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
> ASPEED_PINCTRL_FUNC(I2C7),
> ASPEED_PINCTRL_FUNC(I2C8),
> ASPEED_PINCTRL_FUNC(I2C9),
> + ASPEED_PINCTRL_FUNC(LAD0),
> + ASPEED_PINCTRL_FUNC(LAD1),
> + ASPEED_PINCTRL_FUNC(LAD2),
> + ASPEED_PINCTRL_FUNC(LAD3),
> + ASPEED_PINCTRL_FUNC(LCLK),
> + ASPEED_PINCTRL_FUNC(LFRAME),
> + ASPEED_PINCTRL_FUNC(LPCHC),
> + ASPEED_PINCTRL_FUNC(LPCPD),
> + ASPEED_PINCTRL_FUNC(LPCPLUS),
> + ASPEED_PINCTRL_FUNC(LPCPME),
> + ASPEED_PINCTRL_FUNC(LPCRST),
> + ASPEED_PINCTRL_FUNC(LPCSMI),
> + ASPEED_PINCTRL_FUNC(LSIRQ),
> ASPEED_PINCTRL_FUNC(MAC1LINK),
> + ASPEED_PINCTRL_FUNC(MAC2LINK),
> ASPEED_PINCTRL_FUNC(MDIO1),
> ASPEED_PINCTRL_FUNC(MDIO2),
> + ASPEED_PINCTRL_FUNC(NCTS1),
> + ASPEED_PINCTRL_FUNC(NCTS2),
> + ASPEED_PINCTRL_FUNC(NCTS3),
> + ASPEED_PINCTRL_FUNC(NCTS4),
> + ASPEED_PINCTRL_FUNC(NDCD1),
> + ASPEED_PINCTRL_FUNC(NDCD2),
> + ASPEED_PINCTRL_FUNC(NDCD3),
> + ASPEED_PINCTRL_FUNC(NDCD4),
> + ASPEED_PINCTRL_FUNC(NDSR1),
> + ASPEED_PINCTRL_FUNC(NDSR2),
> + ASPEED_PINCTRL_FUNC(NDSR3),
> + ASPEED_PINCTRL_FUNC(NDSR4),
> + ASPEED_PINCTRL_FUNC(NDTR1),
> + ASPEED_PINCTRL_FUNC(NDTR2),
> + ASPEED_PINCTRL_FUNC(NDTR3),
> + ASPEED_PINCTRL_FUNC(NDTR4),
> + ASPEED_PINCTRL_FUNC(NRI1),
> + ASPEED_PINCTRL_FUNC(NRI2),
> + ASPEED_PINCTRL_FUNC(NRI3),
> + ASPEED_PINCTRL_FUNC(NRI4),
> + ASPEED_PINCTRL_FUNC(NRTS1),
> + ASPEED_PINCTRL_FUNC(NRTS2),
> + ASPEED_PINCTRL_FUNC(NRTS3),
> + ASPEED_PINCTRL_FUNC(NRTS4),
> ASPEED_PINCTRL_FUNC(OSCCLK),
> ASPEED_PINCTRL_FUNC(PEWAKE),
> + ASPEED_PINCTRL_FUNC(PNOR),
> ASPEED_PINCTRL_FUNC(PWM0),
> ASPEED_PINCTRL_FUNC(PWM1),
> ASPEED_PINCTRL_FUNC(PWM2),
> @@ -798,16 +2216,68 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
> ASPEED_PINCTRL_FUNC(RGMII2),
> ASPEED_PINCTRL_FUNC(RMII1),
> ASPEED_PINCTRL_FUNC(RMII2),
> + ASPEED_PINCTRL_FUNC(RXD1),
> + ASPEED_PINCTRL_FUNC(RXD2),
> + ASPEED_PINCTRL_FUNC(RXD3),
> + ASPEED_PINCTRL_FUNC(RXD4),
> + ASPEED_PINCTRL_FUNC(SALT1),
> + ASPEED_PINCTRL_FUNC(SALT10),
> + ASPEED_PINCTRL_FUNC(SALT11),
> + ASPEED_PINCTRL_FUNC(SALT12),
> + ASPEED_PINCTRL_FUNC(SALT13),
> + ASPEED_PINCTRL_FUNC(SALT14),
> + ASPEED_PINCTRL_FUNC(SALT2),
> + ASPEED_PINCTRL_FUNC(SALT3),
> + ASPEED_PINCTRL_FUNC(SALT4),
> + ASPEED_PINCTRL_FUNC(SALT5),
> + ASPEED_PINCTRL_FUNC(SALT6),
> + ASPEED_PINCTRL_FUNC(SALT7),
> + ASPEED_PINCTRL_FUNC(SALT8),
> + ASPEED_PINCTRL_FUNC(SALT9),
> + ASPEED_PINCTRL_FUNC(SCL1),
> + ASPEED_PINCTRL_FUNC(SCL2),
> ASPEED_PINCTRL_FUNC(SD1),
> + ASPEED_PINCTRL_FUNC(SD2),
> + ASPEED_PINCTRL_FUNC(SDA1),
> + ASPEED_PINCTRL_FUNC(SDA2),
> + ASPEED_PINCTRL_FUNC(SGPS1),
> + ASPEED_PINCTRL_FUNC(SGPS2),
> + ASPEED_PINCTRL_FUNC(SIOONCTRL),
> + ASPEED_PINCTRL_FUNC(SIOPBI),
> + ASPEED_PINCTRL_FUNC(SIOPBO),
> + ASPEED_PINCTRL_FUNC(SIOPWREQ),
> + ASPEED_PINCTRL_FUNC(SIOPWRGD),
> + ASPEED_PINCTRL_FUNC(SIOS3),
> + ASPEED_PINCTRL_FUNC(SIOS5),
> + ASPEED_PINCTRL_FUNC(SIOSCI),
> ASPEED_PINCTRL_FUNC(SPI1),
> + ASPEED_PINCTRL_FUNC(SPI1CS1),
> ASPEED_PINCTRL_FUNC(SPI1DEBUG),
> ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
> + ASPEED_PINCTRL_FUNC(SPI2CK),
> + ASPEED_PINCTRL_FUNC(SPI2CS0),
> + ASPEED_PINCTRL_FUNC(SPI2CS1),
> + ASPEED_PINCTRL_FUNC(SPI2MISO),
> + ASPEED_PINCTRL_FUNC(SPI2MOSI),
> + ASPEED_PINCTRL_FUNC(TIMER3),
> ASPEED_PINCTRL_FUNC(TIMER4),
> ASPEED_PINCTRL_FUNC(TIMER5),
> ASPEED_PINCTRL_FUNC(TIMER6),
> ASPEED_PINCTRL_FUNC(TIMER7),
> ASPEED_PINCTRL_FUNC(TIMER8),
> + ASPEED_PINCTRL_FUNC(TXD1),
> + ASPEED_PINCTRL_FUNC(TXD2),
> + ASPEED_PINCTRL_FUNC(TXD3),
> + ASPEED_PINCTRL_FUNC(TXD4),
> + ASPEED_PINCTRL_FUNC(UART6),
> + ASPEED_PINCTRL_FUNC(USBCKI),
> ASPEED_PINCTRL_FUNC(VGABIOSROM),
> + ASPEED_PINCTRL_FUNC(VGAHS),
> + ASPEED_PINCTRL_FUNC(VGAVS),
> + ASPEED_PINCTRL_FUNC(VPI24),
> + ASPEED_PINCTRL_FUNC(VPO),
> + ASPEED_PINCTRL_FUNC(WDTRST1),
> + ASPEED_PINCTRL_FUNC(WDTRST2),
> };
>
> static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
> index 3a76d2c95584..68315a82e9b9 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
> @@ -264,6 +264,7 @@
> #define SCUA0 0xA0 /* Multi-function Pin Control #7 */
> #define SCUA4 0xA4 /* Multi-function Pin Control #8 */
> #define SCUA8 0xA8 /* Multi-function Pin Control #9 */
> +#define SCUAC 0xAC /* Multi-function Pin Control #10 */
> #define HW_STRAP2 0xD0 /* Strapping */
>
> #define SIORD30 SIG_DESC_TO_REG(ASPEED_IP_SIO, 0x30)
> --
> git-series 0.8.10
^ permalink raw reply
* [RESEND][PATCH] [media] atmel-isc: start dma in some scenario
From: Songjun Wu @ 2016-09-29 1:21 UTC (permalink / raw)
To: linux-arm-kernel
If a new vb buf is added to vb queue, the queue is
empty and steaming, dma should be started.
Signed-off-by: Songjun Wu <songjun.wu@microchip.com>
---
drivers/media/platform/atmel/atmel-isc.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/atmel/atmel-isc.c b/drivers/media/platform/atmel/atmel-isc.c
index ccfe13b..ff403d5 100644
--- a/drivers/media/platform/atmel/atmel-isc.c
+++ b/drivers/media/platform/atmel/atmel-isc.c
@@ -617,7 +617,14 @@ static void isc_buffer_queue(struct vb2_buffer *vb)
unsigned long flags;
spin_lock_irqsave(&isc->dma_queue_lock, flags);
- list_add_tail(&buf->list, &isc->dma_queue);
+ if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
+ vb2_is_streaming(vb->vb2_queue)) {
+ isc->cur_frm = buf;
+ isc_start_dma(isc->regmap, isc->cur_frm,
+ isc->current_fmt->reg_dctrl_dview);
+ } else {
+ list_add_tail(&buf->list, &isc->dma_queue);
+ }
spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
}
--
2.7.4
^ permalink raw reply related
* [PATCH V4 00/10] dmaengine: qcom_hidma: add MSI interrupt support
From: Sinan Kaya @ 2016-09-29 2:12 UTC (permalink / raw)
To: linux-arm-kernel
The new version of the HW supports MSI interrupts instead of wired
interrupts. The MSI interrupts are especially useful for the guest machine
execution. The wired interrupts usually trap to the hypervisor and then are
relayed to the actual interrupt.
The MSI interrupts can be directly fed into the interrupt controller.
Adding a new OF compat string (qcom,hidma-1.1) and ACPI string (QCOM8062)
to distinguish newer HW from the older ones.
v4:
* device tree binding update to refer to msi.txt
v3:
* day 0 fix for when ACPI is not compiled in
* https://www.spinics.net/lists/arm-kernel/msg532179.html
v2:
https://patchwork.kernel.org/patch/9326399/
* Documentation update for DT bindings
* Rebased to slave-next
* Dropped dmaengine: qcom_hidma: eliminate processed variables. Replaced it
with dmaengine: qcom_hidma: protect common data structures
v1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/444167.html
* initial implementation
Sinan Kaya (10):
Documentation: DT: qcom_hidma: update binding for MSI
Documentation: DT: qcom_hidma: correct spelling mistakes
of: irq: make of_msi_configure accessible from modules
dmaengine: qcom_hidma: configure DMA and MSI for OF
dmaengine: qcom_hidma: make pending_tre_count atomic
dmaengine: qcom_hidma: make error and success path common
dmaengine: qcom_hidma: bring out interrupt cause
dmaengine: qcom_hidma: add a common API to setup the interrupt
dmaengine: qcom_hidma: protect common data structures
dmaengine: qcom_hidma: add MSI support for interrupts
.../devicetree/bindings/dma/qcom_hidma_mgmt.txt | 12 +-
drivers/dma/qcom/hidma.c | 129 +++++++++-
drivers/dma/qcom/hidma.h | 6 +-
drivers/dma/qcom/hidma_dbg.c | 3 +-
drivers/dma/qcom/hidma_ll.c | 278 ++++++++++-----------
drivers/dma/qcom/hidma_mgmt.c | 5 +-
drivers/of/irq.c | 1 +
7 files changed, 275 insertions(+), 159 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH V4 01/10] Documentation: DT: qcom_hidma: update binding for MSI
From: Sinan Kaya @ 2016-09-29 2:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475115167-5898-1-git-send-email-okaya@codeaurora.org>
Adding a new binding for qcom,hidma-1.1 to distinguish HW supporting
MSI interrupts from the older revision.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
index fd5618b..2c5e4b8 100644
--- a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
@@ -47,12 +47,18 @@ When the OS is not in control of the management interface (i.e. it's a guest),
the channel nodes appear on their own, not under a management node.
Required properties:
-- compatible: must contain "qcom,hidma-1.0"
+- compatible: must contain "qcom,hidma-1.0" for initial HW or "qcom,hidma-1.1"
+for MSI capable HW.
- reg: Addresses for the transfer and event channel
- interrupts: Should contain the event interrupt
- desc-count: Number of asynchronous requests this channel can handle
- iommus: required a iommu node
+Optional properties for MSI:
+- msi-parent : See the generic MSI binding described in
+ devicetree/bindings/interrupt-controller/msi.txt for a description of the
+ msi-parent property.
+
Example:
Hypervisor OS configuration:
--
1.9.1
^ permalink raw reply related
* [PATCH V4 02/10] Documentation: DT: qcom_hidma: correct spelling mistakes
From: Sinan Kaya @ 2016-09-29 2:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475115167-5898-1-git-send-email-okaya@codeaurora.org>
Fix the spelling mistakes and extra and statements in the sentences.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
index 2c5e4b8..55492c2 100644
--- a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt
@@ -5,13 +5,13 @@ memcpy and memset capabilities. It has been designed for virtualized
environments.
Each HIDMA HW instance consists of multiple DMA channels. These channels
-share the same bandwidth. The bandwidth utilization can be parititioned
+share the same bandwidth. The bandwidth utilization can be partitioned
among channels based on the priority and weight assignments.
There are only two priority levels and 15 weigh assignments possible.
Other parameters here determine how much of the system bus this HIDMA
-instance can use like maximum read/write request and and number of bytes to
+instance can use like maximum read/write request and number of bytes to
read/write in a single burst.
Main node required properties:
--
1.9.1
^ permalink raw reply related
* [PATCH V4 03/10] of: irq: make of_msi_configure accessible from modules
From: Sinan Kaya @ 2016-09-29 2:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475115167-5898-1-git-send-email-okaya@codeaurora.org>
The of_msi_configure routine is only accessible by the built-in
kernel drivers. Export this function so that modules can use it
too.
This function is useful for configuring MSI on child device tree
nodes on hierarchical objects.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/of/irq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index a2e68f7..20c09e0 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -767,3 +767,4 @@ void of_msi_configure(struct device *dev, struct device_node *np)
dev_set_msi_domain(dev,
of_msi_get_domain(dev, np, DOMAIN_BUS_PLATFORM_MSI));
}
+EXPORT_SYMBOL_GPL(of_msi_configure);
--
1.9.1
^ permalink raw reply related
* [PATCH V4 04/10] dmaengine: qcom_hidma: configure DMA and MSI for OF
From: Sinan Kaya @ 2016-09-29 2:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475115167-5898-1-git-send-email-okaya@codeaurora.org>
Configure the DMA bindings for the device tree based firmware.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/dma/qcom/hidma_mgmt.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/qcom/hidma_mgmt.c b/drivers/dma/qcom/hidma_mgmt.c
index 82f36e4..e8f6b84 100644
--- a/drivers/dma/qcom/hidma_mgmt.c
+++ b/drivers/dma/qcom/hidma_mgmt.c
@@ -375,8 +375,11 @@ static int __init hidma_mgmt_of_populate_channels(struct device_node *np)
ret = PTR_ERR(new_pdev);
goto out;
}
+ of_node_get(child);
+ new_pdev->dev.of_node = child;
of_dma_configure(&new_pdev->dev, child);
-
+ of_msi_configure(&new_pdev->dev, child);
+ of_node_put(child);
kfree(res);
res = NULL;
}
--
1.9.1
^ permalink raw reply related
* [PATCH V4 05/10] dmaengine: qcom_hidma: make pending_tre_count atomic
From: Sinan Kaya @ 2016-09-29 2:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1475115167-5898-1-git-send-email-okaya@codeaurora.org>
Getting ready for the MSI interrupts. The pending_tre_count is used
in the interrupt handler to make sure all outstanding requests are
serviced.
Making it atomic so that it can be updated from multiple contexts.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/dma/qcom/hidma.h | 2 +-
drivers/dma/qcom/hidma_dbg.c | 3 ++-
drivers/dma/qcom/hidma_ll.c | 13 ++++++-------
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/dma/qcom/hidma.h b/drivers/dma/qcom/hidma.h
index e52e207..3f2ddd4 100644
--- a/drivers/dma/qcom/hidma.h
+++ b/drivers/dma/qcom/hidma.h
@@ -58,7 +58,7 @@ struct hidma_lldev {
void __iomem *evca; /* Event Channel address */
struct hidma_tre
**pending_tre_list; /* Pointers to pending TREs */
- s32 pending_tre_count; /* Number of TREs pending */
+ atomic_t pending_tre_count; /* Number of TREs pending */
void *tre_ring; /* TRE ring */
dma_addr_t tre_dma; /* TRE ring to be shared with HW */
diff --git a/drivers/dma/qcom/hidma_dbg.c b/drivers/dma/qcom/hidma_dbg.c
index fa827e5..87db285 100644
--- a/drivers/dma/qcom/hidma_dbg.c
+++ b/drivers/dma/qcom/hidma_dbg.c
@@ -74,7 +74,8 @@ static void hidma_ll_devstats(struct seq_file *s, void *llhndl)
seq_printf(s, "tre_ring_handle=%pap\n", &lldev->tre_dma);
seq_printf(s, "tre_ring_size = 0x%x\n", lldev->tre_ring_size);
seq_printf(s, "tre_processed_off = 0x%x\n", lldev->tre_processed_off);
- seq_printf(s, "pending_tre_count=%d\n", lldev->pending_tre_count);
+ seq_printf(s, "pending_tre_count=%d\n",
+ atomic_read(&lldev->pending_tre_count));
seq_printf(s, "evca=%p\n", lldev->evca);
seq_printf(s, "evre_ring=%p\n", lldev->evre_ring);
seq_printf(s, "evre_ring_handle=%pap\n", &lldev->evre_dma);
diff --git a/drivers/dma/qcom/hidma_ll.c b/drivers/dma/qcom/hidma_ll.c
index 3224f24..29fef4f 100644
--- a/drivers/dma/qcom/hidma_ll.c
+++ b/drivers/dma/qcom/hidma_ll.c
@@ -218,10 +218,9 @@ static int hidma_post_completed(struct hidma_lldev *lldev, int tre_iterator,
* Keep track of pending TREs that SW is expecting to receive
* from HW. We got one now. Decrement our counter.
*/
- lldev->pending_tre_count--;
- if (lldev->pending_tre_count < 0) {
+ if (atomic_dec_return(&lldev->pending_tre_count) < 0) {
dev_warn(lldev->dev, "tre count mismatch on completion");
- lldev->pending_tre_count = 0;
+ atomic_set(&lldev->pending_tre_count, 0);
}
spin_unlock_irqrestore(&lldev->lock, flags);
@@ -321,7 +320,7 @@ void hidma_cleanup_pending_tre(struct hidma_lldev *lldev, u8 err_info,
u32 tre_read_off;
tre_iterator = lldev->tre_processed_off;
- while (lldev->pending_tre_count) {
+ while (atomic_read(&lldev->pending_tre_count)) {
if (hidma_post_completed(lldev, tre_iterator, err_info,
err_code))
break;
@@ -548,7 +547,7 @@ void hidma_ll_queue_request(struct hidma_lldev *lldev, u32 tre_ch)
tre->err_code = 0;
tre->err_info = 0;
tre->queued = 1;
- lldev->pending_tre_count++;
+ atomic_inc(&lldev->pending_tre_count);
lldev->tre_write_offset = (lldev->tre_write_offset + HIDMA_TRE_SIZE)
% lldev->tre_ring_size;
spin_unlock_irqrestore(&lldev->lock, flags);
@@ -654,7 +653,7 @@ int hidma_ll_setup(struct hidma_lldev *lldev)
u32 val;
u32 nr_tres = lldev->nr_tres;
- lldev->pending_tre_count = 0;
+ atomic_set(&lldev->pending_tre_count, 0);
lldev->tre_processed_off = 0;
lldev->evre_processed_off = 0;
lldev->tre_write_offset = 0;
@@ -816,7 +815,7 @@ int hidma_ll_uninit(struct hidma_lldev *lldev)
tasklet_kill(&lldev->task);
memset(lldev->trepool, 0, required_bytes);
lldev->trepool = NULL;
- lldev->pending_tre_count = 0;
+ atomic_set(&lldev->pending_tre_count, 0);
lldev->tre_write_offset = 0;
rc = hidma_ll_reset(lldev);
--
1.9.1
^ permalink raw reply related
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